[B]

1. B
2. B0
3. B0SEL
4. B0_CMDREG1
5. B0_CMDREG2
6. B0_CNTRL_A
7. B0_CNTRL_B
8. B0_CNTRL_C
9. B0_CTRL
10. B0_CTST
11. B0_DAS
12. B0_HWE_IMSK
13. B0_HWE_ISRC
14. B0_IMR
15. B0_IMSK
16. B0_IMSK3L
17. B0_IMSK3U
18. B0_INTR_MASK
19. B0_ISRC
20. B0_IVR
21. B0_LED
22. B0_MARR
23. B0_MARW
24. B0_MDREG1
25. B0_MDREG3
26. B0_MDRL
27. B0_MDRU
28. B0_POWER_CTRL
29. B0_R1_CSR
30. B0_R2_CSR
31. B0_RAP
32. B0_SP_ISRC
33. B0_ST1L
34. B0_ST1U
35. B0_ST2L
36. B0_ST2U
37. B0_ST3L
38. B0_ST3U
39. B0_STATUS_A
40. B0_STATUS_B
41. B0_TST_CTRL
42. B0_XA1_CSR
43. B0_XA2_CSR
44. B0_XA_CSR
45. B0_XM1_IMSK
46. B0_XM1_ISRC
47. B0_XM1_PHY_ADDR
48. B0_XM1_PHY_DATA
49. B0_XM2_IMSK
50. B0_XM2_ISRC
51. B0_XM2_PHY_ADDR
52. B0_XM2_PHY_DATA
53. B0_XMIT_VECTOR
54. B0_XS1_CSR
55. B0_XS2_CSR
56. B0_XS_CSR
57. B0_Y2_SP_EISR
58. B0_Y2_SP_ICR
59. B0_Y2_SP_ISRC2
60. B0_Y2_SP_ISRC3
61. B0_Y2_SP_LISR
62. B1
63. B10
64. B1000000
65. B11
66. B110
67. B115200
68. B1152000
69. B12
70. B1200
71. B13
72. B134
73. B14
74. B15
75. B150
76. B1500000
77. B153600
78. B15_RAC_FLUSH_REG
79. B16
80. B16_IO_PORT_SEL
81. B16_RAM_REGS
82. B17
83. B18
84. B1800
85. B19
86. B19200
87. B1SEL
88. B1_ANALYSE
89. B1_INSTAT
90. B1_OUTSTAT
91. B1_PROT_56KBIT_TRANSPARENT
92. B1_PROT_64KBIT_HDLC
93. B1_PROT_64KBIT_INV_HDLC
94. B1_PROT_64KBIT_TRANSPARENT
95. B1_PROT_T30
96. B1_PROT_V110_ASYNCH
97. B1_PROT_V110_SYNCH
98. B1_READ
99. B1_RESET
100. B1_REVISION
101. B1_STAT0
102. B1_STAT1
103. B1_WRITE
104. B2
105. B20
106. B200
107. B2000000
108. B2055_C1_B0NB_RSSIVCM
109. B2055_C1_GENSPARE2
110. B2055_C1_LGBUF_AIDAC
111. B2055_C1_LGBUF_ATUNE
112. B2055_C1_LGBUF_DIV
113. B2055_C1_LGBUF_GIDAC
114. B2055_C1_LGBUF_GTUNE
115. B2055_C1_LGBUF_IDACFO
116. B2055_C1_LGBUF_SPARE
117. B2055_C1_LNA_GAINBST
118. B2055_C1_PD_LGBUF
119. B2055_C1_PD_RSSIMISC
120. B2055_C1_PD_RXTX
121. B2055_C1_PD_TX
122. B2055_C1_PWRDET_LGBUF
123. B2055_C1_PWRDET_RXTX
124. B2055_C1_RX_BB_BLCMP
125. B2055_C1_RX_BB_BUFOCTL
126. B2055_C1_RX_BB_LPF
127. B2055_C1_RX_BB_MIDACHP
128. B2055_C1_RX_BB_RCCALCTL
129. B2055_C1_RX_BB_REG
130. B2055_C1_RX_BB_RSSICTL1
131. B2055_C1_RX_BB_RSSICTL2
132. B2055_C1_RX_BB_RSSICTL3
133. B2055_C1_RX_BB_RSSICTL4
134. B2055_C1_RX_BB_RSSICTL5
135. B2055_C1_RX_BB_SPARE1
136. B2055_C1_RX_BB_VGA1IDAC
137. B2055_C1_RX_BB_VGA2IDAC
138. B2055_C1_RX_BB_VGA3IDAC
139. B2055_C1_RX_RFR1
140. B2055_C1_RX_RFR2
141. B2055_C1_RX_RFRCAL
142. B2055_C1_RX_RFSPC1
143. B2055_C1_RX_TXBBRCAL
144. B2055_C1_SP_LPFBWSEL
145. B2055_C1_SP_PDMISC
146. B2055_C1_SP_RSSI
147. B2055_C1_SP_RXGC1
148. B2055_C1_SP_RXGC2
149. B2055_C1_SP_TXGC1
150. B2055_C1_SP_TXGC2
151. B2055_C1_TXBB_LPF1
152. B2055_C1_TXBB_RCCAL
153. B2055_C1_TX_BB_MXGM
154. B2055_C1_TX_LPF_MXGMIDAC
155. B2055_C1_TX_MXBGTRIM
156. B2055_C1_TX_PADIDAC1
157. B2055_C1_TX_PADIDAC2
158. B2055_C1_TX_PGAPADTN
159. B2055_C1_TX_RF_CNTPAD1
160. B2055_C1_TX_RF_CNTPGA1
161. B2055_C1_TX_RF_IQCAL1
162. B2055_C1_TX_RF_IQCAL2
163. B2055_C1_TX_RF_PADTSSI1
164. B2055_C1_TX_RF_PADTSSI2
165. B2055_C1_TX_RF_PGAIDAC
166. B2055_C1_TX_RF_RCAL
167. B2055_C1_TX_RF_SPAD
168. B2055_C1_TX_RF_SPARE
169. B2055_C1_TX_RF_SPGA
170. B2055_C1_TX_VOSCNCL
171. B2055_C2_B0NB_RSSIVCM
172. B2055_C2_GENSPARE2
173. B2055_C2_LGBUF_AIDAC
174. B2055_C2_LGBUF_ATUNE
175. B2055_C2_LGBUF_DIV
176. B2055_C2_LGBUF_GIDAC
177. B2055_C2_LGBUF_GTUNE
178. B2055_C2_LGBUF_IDACFO
179. B2055_C2_LGBUF_SPARE
180. B2055_C2_LNA_GAINBST
181. B2055_C2_PD_LGBUF
182. B2055_C2_PD_RSSIMISC
183. B2055_C2_PD_RXTX
184. B2055_C2_PD_TX
185. B2055_C2_PWRDET_LGBUF
186. B2055_C2_PWRDET_RXTX
187. B2055_C2_RX_BB_BLCMP
188. B2055_C2_RX_BB_BUFOCTL
189. B2055_C2_RX_BB_LPF
190. B2055_C2_RX_BB_MIDACHP
191. B2055_C2_RX_BB_RCCALCTL
192. B2055_C2_RX_BB_REG
193. B2055_C2_RX_BB_RSSICTL1
194. B2055_C2_RX_BB_RSSICTL2
195. B2055_C2_RX_BB_RSSICTL3
196. B2055_C2_RX_BB_RSSICTL4
197. B2055_C2_RX_BB_RSSICTL5
198. B2055_C2_RX_BB_SPARE1
199. B2055_C2_RX_BB_VGA1IDAC
200. B2055_C2_RX_BB_VGA2IDAC
201. B2055_C2_RX_BB_VGA3IDAC
202. B2055_C2_RX_RFR1
203. B2055_C2_RX_RFR2
204. B2055_C2_RX_RFRCAL
205. B2055_C2_RX_RFSPC1
206. B2055_C2_RX_TXBBRCAL
207. B2055_C2_SP_LPFBWSEL
208. B2055_C2_SP_PDMISC
209. B2055_C2_SP_RSSI
210. B2055_C2_SP_RXGC1
211. B2055_C2_SP_RXGC2
212. B2055_C2_SP_TXGC1
213. B2055_C2_SP_TXGC2
214. B2055_C2_TXBB_LPF1
215. B2055_C2_TXBB_RCCAL
216. B2055_C2_TX_BB_MXGM
217. B2055_C2_TX_LPF_MXGMIDAC
218. B2055_C2_TX_MXBGTRIM
219. B2055_C2_TX_PADIDAC1
220. B2055_C2_TX_PADIDAC2
221. B2055_C2_TX_PGAPADTN
222. B2055_C2_TX_RF_CNTPAD1
223. B2055_C2_TX_RF_CNTPGA1
224. B2055_C2_TX_RF_IQCAL1
225. B2055_C2_TX_RF_IQCAL2
226. B2055_C2_TX_RF_PADTSSI1
227. B2055_C2_TX_RF_PADTSSI2
228. B2055_C2_TX_RF_PGAIDAC
229. B2055_C2_TX_RF_RCAL
230. B2055_C2_TX_RF_SPAD
231. B2055_C2_TX_RF_SPARE
232. B2055_C2_TX_RF_SPGA
233. B2055_C2_TX_VOSCNCL
234. B2055_CAL_COUT
235. B2055_CAL_COUT2
236. B2055_CAL_CVARCTL
237. B2055_CAL_LPOCTL
238. B2055_CAL_MISC
239. B2055_CAL_RCALRTS
240. B2055_CAL_RCCALRTS
241. B2055_CAL_RVARCTL
242. B2055_CAL_TS
243. B2055_GEN_SPARE
244. B2055_INITTAB_ENTRY_OK
245. B2055_INITTAB_UPLOAD
246. B2055_LGBUF_CENBUF
247. B2055_LGEN_BIASC
248. B2055_LGEN_BIASIDAC
249. B2055_LGEN_DIV
250. B2055_LGEN_IDAC1
251. B2055_LGEN_IDAC2
252. B2055_LGEN_RCAL
253. B2055_LGEN_SPARE2
254. B2055_LGEN_TUNE1
255. B2055_LGEN_TUNE2
256. B2055_MASTER1
257. B2055_MASTER2
258. B2055_PADDRV
259. B2055_PD_LGEN
260. B2055_PD_PLLTS
261. B2055_PLL_CALVTH
262. B2055_PLL_CPREG
263. B2055_PLL_IDAC_CPOPAMP
264. B2055_PLL_LFC1
265. B2055_PLL_LFC2
266. B2055_PLL_LFR1
267. B2055_PLL_PFDCP
268. B2055_PLL_RCAL
269. B2055_PLL_REF
270. B2055_PLL_RFVTH
271. B2055_PRG_GCHP21
272. B2055_PRG_GCHP22
273. B2055_PRG_GCHP23
274. B2055_PRG_GCHP24
275. B2055_PRG_GCHP25
276. B2055_PRG_GCHP26
277. B2055_PRG_GCHP27
278. B2055_PRG_GCHP28
279. B2055_PRG_GCHP29
280. B2055_PRG_GCHP30
281. B2055_PWRDET_LGEN
282. B2055_RF_MMDIDAC0
283. B2055_RF_MMDIDAC1
284. B2055_RF_MMDSP
285. B2055_RF_PLLMOD0
286. B2055_RF_PLLMOD1
287. B2055_RRCCAL_CS
288. B2055_RRCCAL_NOPTSEL
289. B2055_SP_PINPD
290. B2055_VCO_CAL1
291. B2055_VCO_CAL10
292. B2055_VCO_CAL11
293. B2055_VCO_CAL12
294. B2055_VCO_CAL13
295. B2055_VCO_CAL14
296. B2055_VCO_CAL15
297. B2055_VCO_CAL16
298. B2055_VCO_CAL2
299. B2055_VCO_CAL3
300. B2055_VCO_CAL4
301. B2055_VCO_CAL5
302. B2055_VCO_CAL6
303. B2055_VCO_CAL7
304. B2055_VCO_CAL8
305. B2055_VCO_CAL9
306. B2055_VCO_CAPTAIL
307. B2055_VCO_IDACVCO
308. B2055_VCO_KVCO
309. B2055_VCO_REG
310. B2055_XOCTL1
311. B2055_XOCTL2
312. B2055_XOMISC
313. B2055_XOREGUL
314. B2056_ALLRX
315. B2056_ALLTX
316. B2056_BB_LPF_PU
317. B2056_INITTAB_ENTRY_OK
318. B2056_INITTAB_UPLOAD
319. B2056_LNA1_A_PU
320. B2056_LNA1_G_PU
321. B2056_LNA2_A_PU
322. B2056_LNA2_G_PU
323. B2056_MIXA_PU_GM
324. B2056_MIXA_PU_I
325. B2056_MIXA_PU_Q
326. B2056_MIXG_PU_GM
327. B2056_MIXG_PU_I
328. B2056_MIXG_PU_Q
329. B2056_NB_PU
330. B2056_RSSI_NB_SEL
331. B2056_RSSI_VCM_SHIFT
332. B2056_RSSI_W1_SEL
333. B2056_RSSI_W2_SEL
334. B2056_RX0
335. B2056_RX1
336. B2056_RX_AACI_MASTER
337. B2056_RX_BB_LPF_MASTER
338. B2056_RX_BIASPOLE_LNAA1_IDAC
339. B2056_RX_BIASPOLE_LNAG1_IDAC
340. B2056_RX_COM_CTRL
341. B2056_RX_COM_OVR
342. B2056_RX_COM_PU
343. B2056_RX_COM_RCAL
344. B2056_RX_COM_RC_RXHPF
345. B2056_RX_COM_RC_RXLPF
346. B2056_RX_COM_RC_TXLPF
347. B2056_RX_COM_RESET
348. B2056_RX_IDCODE
349. B2056_RX_LNA1A_MISC
350. B2056_RX_LNA1G_MISC
351. B2056_RX_LNAA2_IDAC
352. B2056_RX_LNAA_GAIN
353. B2056_RX_LNAA_MASTER
354. B2056_RX_LNAA_TUNE
355. B2056_RX_LNAG2_IDAC
356. B2056_RX_LNAG_GAIN
357. B2056_RX_LNAG_MASTER
358. B2056_RX_LNAG_TUNE
359. B2056_RX_LNA_A_SLOPE
360. B2056_RX_LNA_G_SLOPE
361. B2056_RX_MIXA_BIAS_AUX
362. B2056_RX_MIXA_BIAS_MAIN
363. B2056_RX_MIXA_BIAS_MISC
364. B2056_RX_MIXA_CMFB_IDAC
365. B2056_RX_MIXA_CORE_IDAC
366. B2056_RX_MIXA_CTRLPTAT
367. B2056_RX_MIXA_LOB_BIAS
368. B2056_RX_MIXA_MASTER
369. B2056_RX_MIXA_MAST_BIAS
370. B2056_RX_MIXA_VCM
371. B2056_RX_MIXG_BIAS_AUX
372. B2056_RX_MIXG_BIAS_MAIN
373. B2056_RX_MIXG_BIAS_MISC
374. B2056_RX_MIXG_CMFB_IDAC
375. B2056_RX_MIXG_CORE_IDAC
376. B2056_RX_MIXG_CTRLPTAT
377. B2056_RX_MIXG_LOB_BIAS
378. B2056_RX_MIXG_MASTER
379. B2056_RX_MIXG_MAST_BIAS
380. B2056_RX_MIXG_VCM
381. B2056_RX_RESERVED_ADDR0
382. B2056_RX_RESERVED_ADDR16
383. B2056_RX_RESERVED_ADDR17
384. B2056_RX_RESERVED_ADDR18
385. B2056_RX_RESERVED_ADDR19
386. B2056_RX_RESERVED_ADDR2
387. B2056_RX_RESERVED_ADDR20
388. B2056_RX_RESERVED_ADDR21
389. B2056_RX_RESERVED_ADDR22
390. B2056_RX_RESERVED_ADDR23
391. B2056_RX_RESERVED_ADDR24
392. B2056_RX_RESERVED_ADDR25
393. B2056_RX_RESERVED_ADDR26
394. B2056_RX_RESERVED_ADDR27
395. B2056_RX_RESERVED_ADDR28
396. B2056_RX_RESERVED_ADDR29
397. B2056_RX_RESERVED_ADDR3
398. B2056_RX_RESERVED_ADDR30
399. B2056_RX_RESERVED_ADDR31
400. B2056_RX_RESERVED_ADDR4
401. B2056_RX_RESERVED_ADDR5
402. B2056_RX_RESERVED_ADDR6
403. B2056_RX_RESERVED_ADDR7
404. B2056_RX_RSSI_GAIN
405. B2056_RX_RSSI_MISC
406. B2056_RX_RSSI_NB_IDAC
407. B2056_RX_RSSI_POLE
408. B2056_RX_RSSI_PU
409. B2056_RX_RSSI_SEL
410. B2056_RX_RSSI_WB1_IDAC
411. B2056_RX_RSSI_WB2I_IDAC_1
412. B2056_RX_RSSI_WB2I_IDAC_2
413. B2056_RX_RSSI_WB2Q_IDAC_1
414. B2056_RX_RSSI_WB2Q_IDAC_2
415. B2056_RX_RXHPF_OFF0
416. B2056_RX_RXHPF_OFF1
417. B2056_RX_RXHPF_OFF2
418. B2056_RX_RXHPF_OFF3
419. B2056_RX_RXHPF_OFF4
420. B2056_RX_RXHPF_OFF5
421. B2056_RX_RXHPF_OFF6
422. B2056_RX_RXHPF_OFF7
423. B2056_RX_RXIQCAL_RXMUX
424. B2056_RX_RXLPF_BIAS_DCCANCEL
425. B2056_RX_RXLPF_CC_OP
426. B2056_RX_RXLPF_GAIN
427. B2056_RX_RXLPF_HP_CORNER_BW
428. B2056_RX_RXLPF_IDAC
429. B2056_RX_RXLPF_INVCM_BODY
430. B2056_RX_RXLPF_OFF_0
431. B2056_RX_RXLPF_OFF_1
432. B2056_RX_RXLPF_OFF_2
433. B2056_RX_RXLPF_OFF_3
434. B2056_RX_RXLPF_OFF_4
435. B2056_RX_RXLPF_OPAMPBIAS_HIGHQ
436. B2056_RX_RXLPF_OPAMPBIAS_LOWQ
437. B2056_RX_RXLPF_OUTVCM
438. B2056_RX_RXLPF_Q_BW
439. B2056_RX_RXLPF_RCCAL_HPC
440. B2056_RX_RXLPF_RCCAL_LPC
441. B2056_RX_RXSPARE1
442. B2056_RX_RXSPARE10
443. B2056_RX_RXSPARE11
444. B2056_RX_RXSPARE12
445. B2056_RX_RXSPARE13
446. B2056_RX_RXSPARE14
447. B2056_RX_RXSPARE15
448. B2056_RX_RXSPARE16
449. B2056_RX_RXSPARE2
450. B2056_RX_RXSPARE3
451. B2056_RX_RXSPARE4
452. B2056_RX_RXSPARE5
453. B2056_RX_RXSPARE6
454. B2056_RX_RXSPARE7
455. B2056_RX_RXSPARE8
456. B2056_RX_RXSPARE9
457. B2056_RX_STATUS_HPC_RC
458. B2056_RX_STATUS_LNAA_GAIN
459. B2056_RX_STATUS_LNAG_GAIN
460. B2056_RX_STATUS_MIXTIA_GAIN
461. B2056_RX_STATUS_RXLPF_BUF_BW
462. B2056_RX_STATUS_RXLPF_GAIN
463. B2056_RX_STATUS_RXLPF_Q
464. B2056_RX_STATUS_RXLPF_RC
465. B2056_RX_STATUS_RXLPF_VGA_HPC
466. B2056_RX_STATUS_VGA_BUF_GAIN
467. B2056_RX_TIA_GAIN
468. B2056_RX_TIA_IMISC
469. B2056_RX_TIA_IOPAMP
470. B2056_RX_TIA_MASTER
471. B2056_RX_TIA_QMISC
472. B2056_RX_TIA_QOPAMP
473. B2056_RX_TIA_SPARE1
474. B2056_RX_TIA_SPARE2
475. B2056_RX_TXFBMIX_A
476. B2056_RX_TXFBMIX_G
477. B2056_RX_UNUSED
478. B2056_RX_VGABUF_BIAS
479. B2056_RX_VGABUF_GAIN_BW
480. B2056_RX_VGA_BIAS
481. B2056_RX_VGA_BIAS_DCCANCEL
482. B2056_RX_VGA_GAIN
483. B2056_RX_VGA_HP_CORNER_BW
484. B2056_RX_VGA_MASTER
485. B2056_SYN
486. B2056_SYN_AFEREG
487. B2056_SYN_CALEN
488. B2056_SYN_COM_CTRL
489. B2056_SYN_COM_OVR
490. B2056_SYN_COM_PU
491. B2056_SYN_COM_RCAL
492. B2056_SYN_COM_RC_RXHPF
493. B2056_SYN_COM_RC_RXLPF
494. B2056_SYN_COM_RC_TXLPF
495. B2056_SYN_COM_RESET
496. B2056_SYN_GPIO_MASTER1
497. B2056_SYN_GPIO_MASTER2
498. B2056_SYN_IDCODE
499. B2056_SYN_LOGENBUF2
500. B2056_SYN_LOGEN_ACL1
501. B2056_SYN_LOGEN_ACL2
502. B2056_SYN_LOGEN_ACL3
503. B2056_SYN_LOGEN_ACL4
504. B2056_SYN_LOGEN_ACL5
505. B2056_SYN_LOGEN_ACL6
506. B2056_SYN_LOGEN_ACLCAL1
507. B2056_SYN_LOGEN_ACLCAL2
508. B2056_SYN_LOGEN_ACLCAL3
509. B2056_SYN_LOGEN_ACLOUT
510. B2056_SYN_LOGEN_ACL_WAITCNT
511. B2056_SYN_LOGEN_BIAS_RESET
512. B2056_SYN_LOGEN_BUF1
513. B2056_SYN_LOGEN_BUF3
514. B2056_SYN_LOGEN_BUF4
515. B2056_SYN_LOGEN_BUF5
516. B2056_SYN_LOGEN_BUF5_OVRVAL
517. B2056_SYN_LOGEN_BUF6
518. B2056_SYN_LOGEN_BUF6_OVRVAL
519. B2056_SYN_LOGEN_CBUFRX1
520. B2056_SYN_LOGEN_CBUFRX1_OVRVAL
521. B2056_SYN_LOGEN_CBUFRX2
522. B2056_SYN_LOGEN_CBUFRX2_OVRVAL
523. B2056_SYN_LOGEN_CBUFRX3
524. B2056_SYN_LOGEN_CBUFRX3_OVRVAL
525. B2056_SYN_LOGEN_CBUFRX4
526. B2056_SYN_LOGEN_CBUFRX4_OVRVAL
527. B2056_SYN_LOGEN_CBUFTX1
528. B2056_SYN_LOGEN_CBUFTX1_OVRVAL
529. B2056_SYN_LOGEN_CBUFTX2
530. B2056_SYN_LOGEN_CBUFTX2_OVRVAL
531. B2056_SYN_LOGEN_CBUFTX3
532. B2056_SYN_LOGEN_CBUFTX3_OVRVAL
533. B2056_SYN_LOGEN_CBUFTX4
534. B2056_SYN_LOGEN_CBUFTX4_OVRVAL
535. B2056_SYN_LOGEN_CMOSRX1
536. B2056_SYN_LOGEN_CMOSRX1_OVRVAL
537. B2056_SYN_LOGEN_CMOSRX2
538. B2056_SYN_LOGEN_CMOSRX2_OVRVAL
539. B2056_SYN_LOGEN_CMOSRX3
540. B2056_SYN_LOGEN_CMOSRX3_OVRVAL
541. B2056_SYN_LOGEN_CMOSRX4
542. B2056_SYN_LOGEN_CMOSRX4_OVRVAL
543. B2056_SYN_LOGEN_CMOSTX1
544. B2056_SYN_LOGEN_CMOSTX1_OVRVAL
545. B2056_SYN_LOGEN_CMOSTX2
546. B2056_SYN_LOGEN_CMOSTX2_OVRVAL
547. B2056_SYN_LOGEN_CMOSTX3
548. B2056_SYN_LOGEN_CMOSTX3_OVRVAL
549. B2056_SYN_LOGEN_CMOSTX4
550. B2056_SYN_LOGEN_CMOSTX4_OVRVAL
551. B2056_SYN_LOGEN_CORE_ACL_OVR
552. B2056_SYN_LOGEN_CORE_CALVALID
553. B2056_SYN_LOGEN_DIV1
554. B2056_SYN_LOGEN_DIV2
555. B2056_SYN_LOGEN_DIV3
556. B2056_SYN_LOGEN_MIXER1
557. B2056_SYN_LOGEN_MIXER2
558. B2056_SYN_LOGEN_MIXER3
559. B2056_SYN_LOGEN_MIXER3_OVRVAL
560. B2056_SYN_LOGEN_PEAKDET1
561. B2056_SYN_LOGEN_PU0
562. B2056_SYN_LOGEN_PU1
563. B2056_SYN_LOGEN_PU2
564. B2056_SYN_LOGEN_PU3
565. B2056_SYN_LOGEN_PU5
566. B2056_SYN_LOGEN_PU6
567. B2056_SYN_LOGEN_PU7
568. B2056_SYN_LOGEN_PU8
569. B2056_SYN_LOGEN_RCCR1
570. B2056_SYN_LOGEN_RX_CMOS_ACL_OVR
571. B2056_SYN_LOGEN_RX_CMOS_CALVALID
572. B2056_SYN_LOGEN_RX_DIFF_ACL_OVR
573. B2056_SYN_LOGEN_TX_CMOS_ACL_OVR
574. B2056_SYN_LOGEN_TX_CMOS_VALID
575. B2056_SYN_LOGEN_TX_DIFF_ACL_OVR
576. B2056_SYN_LOGEN_VCOBUF1
577. B2056_SYN_LOGEN_VCOBUF2
578. B2056_SYN_LOGEN_VCOBUF2_OVRVAL
579. B2056_SYN_LPO
580. B2056_SYN_PLL_BIAS_RESET
581. B2056_SYN_PLL_CP1
582. B2056_SYN_PLL_CP2
583. B2056_SYN_PLL_CP3
584. B2056_SYN_PLL_LOOPFILTER1
585. B2056_SYN_PLL_LOOPFILTER2
586. B2056_SYN_PLL_LOOPFILTER3
587. B2056_SYN_PLL_LOOPFILTER4
588. B2056_SYN_PLL_LOOPFILTER5
589. B2056_SYN_PLL_MAST1
590. B2056_SYN_PLL_MAST2
591. B2056_SYN_PLL_MAST3
592. B2056_SYN_PLL_MMD1
593. B2056_SYN_PLL_MMD2
594. B2056_SYN_PLL_MONITOR1
595. B2056_SYN_PLL_MONITOR2
596. B2056_SYN_PLL_PFD
597. B2056_SYN_PLL_REFDIV
598. B2056_SYN_PLL_STATUS1
599. B2056_SYN_PLL_STATUS2
600. B2056_SYN_PLL_STATUS3
601. B2056_SYN_PLL_VCO1
602. B2056_SYN_PLL_VCO2
603. B2056_SYN_PLL_VCOCAL1
604. B2056_SYN_PLL_VCOCAL10
605. B2056_SYN_PLL_VCOCAL11
606. B2056_SYN_PLL_VCOCAL12
607. B2056_SYN_PLL_VCOCAL13
608. B2056_SYN_PLL_VCOCAL2
609. B2056_SYN_PLL_VCOCAL4
610. B2056_SYN_PLL_VCOCAL5
611. B2056_SYN_PLL_VCOCAL6
612. B2056_SYN_PLL_VCOCAL7
613. B2056_SYN_PLL_VCOCAL8
614. B2056_SYN_PLL_VCOCAL9
615. B2056_SYN_PLL_VREG
616. B2056_SYN_PLL_XTAL0
617. B2056_SYN_PLL_XTAL1
618. B2056_SYN_PLL_XTAL3
619. B2056_SYN_PLL_XTAL4
620. B2056_SYN_PLL_XTAL5
621. B2056_SYN_PLL_XTAL6
622. B2056_SYN_RCAL_CODE_OUT
623. B2056_SYN_RCAL_MASTER
624. B2056_SYN_RCCAL_CTRL0
625. B2056_SYN_RCCAL_CTRL1
626. B2056_SYN_RCCAL_CTRL10
627. B2056_SYN_RCCAL_CTRL11
628. B2056_SYN_RCCAL_CTRL2
629. B2056_SYN_RCCAL_CTRL3
630. B2056_SYN_RCCAL_CTRL4
631. B2056_SYN_RCCAL_CTRL5
632. B2056_SYN_RCCAL_CTRL6
633. B2056_SYN_RCCAL_CTRL7
634. B2056_SYN_RCCAL_CTRL8
635. B2056_SYN_RCCAL_CTRL9
636. B2056_SYN_RESERVED_ADDR0
637. B2056_SYN_RESERVED_ADDR16
638. B2056_SYN_RESERVED_ADDR17
639. B2056_SYN_RESERVED_ADDR18
640. B2056_SYN_RESERVED_ADDR19
641. B2056_SYN_RESERVED_ADDR2
642. B2056_SYN_RESERVED_ADDR20
643. B2056_SYN_RESERVED_ADDR21
644. B2056_SYN_RESERVED_ADDR22
645. B2056_SYN_RESERVED_ADDR23
646. B2056_SYN_RESERVED_ADDR24
647. B2056_SYN_RESERVED_ADDR25
648. B2056_SYN_RESERVED_ADDR26
649. B2056_SYN_RESERVED_ADDR27
650. B2056_SYN_RESERVED_ADDR28
651. B2056_SYN_RESERVED_ADDR29
652. B2056_SYN_RESERVED_ADDR3
653. B2056_SYN_RESERVED_ADDR30
654. B2056_SYN_RESERVED_ADDR31
655. B2056_SYN_RESERVED_ADDR4
656. B2056_SYN_RESERVED_ADDR5
657. B2056_SYN_RESERVED_ADDR6
658. B2056_SYN_RESERVED_ADDR7
659. B2056_SYN_TEMPPROCSENSE
660. B2056_SYN_TEMPPROCSENSEIDAC
661. B2056_SYN_TEMPPROCSENSERCAL
662. B2056_SYN_TOPBIAS_MASTER
663. B2056_SYN_TOPBIAS_RCAL
664. B2056_SYN_VDDCAL_IDAC
665. B2056_SYN_VDDCAL_MASTER
666. B2056_SYN_VDDCAL_STATUS
667. B2056_SYN_ZCAL_SPARE1
668. B2056_SYN_ZCAL_SPARE2
669. B2056_TIA_PU
670. B2056_TX0
671. B2056_TX1
672. B2056_TX_BB_GM_MASTER
673. B2056_TX_COM_CTRL
674. B2056_TX_COM_OVR
675. B2056_TX_COM_PU
676. B2056_TX_COM_RCAL
677. B2056_TX_COM_RC_RXHPF
678. B2056_TX_COM_RC_RXLPF
679. B2056_TX_COM_RC_TXLPF
680. B2056_TX_COM_RESET
681. B2056_TX_GMBB_GM
682. B2056_TX_GMBB_IDAC
683. B2056_TX_GMBB_IDAC0
684. B2056_TX_GMBB_IDAC1
685. B2056_TX_GMBB_IDAC2
686. B2056_TX_GMBB_IDAC3
687. B2056_TX_GMBB_IDAC4
688. B2056_TX_GMBB_IDAC5
689. B2056_TX_GMBB_IDAC6
690. B2056_TX_GMBB_IDAC7
691. B2056_TX_IDCODE
692. B2056_TX_INTPAA_BOOST_TUNE
693. B2056_TX_INTPAA_CASCBIAS
694. B2056_TX_INTPAA_GAIN
695. B2056_TX_INTPAA_IAUX_DYN
696. B2056_TX_INTPAA_IAUX_STAT
697. B2056_TX_INTPAA_IMAIN_DYN
698. B2056_TX_INTPAA_IMAIN_STAT
699. B2056_TX_INTPAA_MASTER
700. B2056_TX_INTPAA_PASLOPE
701. B2056_TX_INTPAA_PA_MISC
702. B2056_TX_INTPAG_BOOST_TUNE
703. B2056_TX_INTPAG_CASCBIAS
704. B2056_TX_INTPAG_GAIN
705. B2056_TX_INTPAG_IAUX_DYN
706. B2056_TX_INTPAG_IAUX_STAT
707. B2056_TX_INTPAG_IMAIN_DYN
708. B2056_TX_INTPAG_IMAIN_STAT
709. B2056_TX_INTPAG_MASTER
710. B2056_TX_INTPAG_PASLOPE
711. B2056_TX_INTPAG_PA_MISC
712. B2056_TX_IQCAL_GAIN_BW
713. B2056_TX_IQCAL_IDAC
714. B2056_TX_IQCAL_VCM_HG
715. B2056_TX_LOFT_COARSE_I
716. B2056_TX_LOFT_COARSE_Q
717. B2056_TX_LOFT_FINE_I
718. B2056_TX_LOFT_FINE_Q
719. B2056_TX_MIXA_BOOST_TUNE
720. B2056_TX_MIXA_MASTER
721. B2056_TX_MIXG
722. B2056_TX_MIXG_BOOST_TUNE
723. B2056_TX_PADA_BOOST_TUNE
724. B2056_TX_PADA_CASCBIAS
725. B2056_TX_PADA_GAIN
726. B2056_TX_PADA_IDAC
727. B2056_TX_PADA_MASTER
728. B2056_TX_PADA_SLOPE
729. B2056_TX_PADG_BOOST_TUNE
730. B2056_TX_PADG_CASCBIAS
731. B2056_TX_PADG_GAIN
732. B2056_TX_PADG_IDAC
733. B2056_TX_PADG_MASTER
734. B2056_TX_PADG_SLOPE
735. B2056_TX_PA_SPARE1
736. B2056_TX_PA_SPARE2
737. B2056_TX_PGAA_BOOST_TUNE
738. B2056_TX_PGAA_GAIN
739. B2056_TX_PGAA_IDAC
740. B2056_TX_PGAA_MASTER
741. B2056_TX_PGAA_MISC
742. B2056_TX_PGAA_SLOPE
743. B2056_TX_PGAG_BOOST_TUNE
744. B2056_TX_PGAG_GAIN
745. B2056_TX_PGAG_IDAC
746. B2056_TX_PGAG_MASTER
747. B2056_TX_PGAG_MISC
748. B2056_TX_PGAG_SLOPE
749. B2056_TX_RESERVED_ADDR0
750. B2056_TX_RESERVED_ADDR16
751. B2056_TX_RESERVED_ADDR17
752. B2056_TX_RESERVED_ADDR18
753. B2056_TX_RESERVED_ADDR19
754. B2056_TX_RESERVED_ADDR2
755. B2056_TX_RESERVED_ADDR20
756. B2056_TX_RESERVED_ADDR21
757. B2056_TX_RESERVED_ADDR22
758. B2056_TX_RESERVED_ADDR23
759. B2056_TX_RESERVED_ADDR24
760. B2056_TX_RESERVED_ADDR25
761. B2056_TX_RESERVED_ADDR26
762. B2056_TX_RESERVED_ADDR27
763. B2056_TX_RESERVED_ADDR28
764. B2056_TX_RESERVED_ADDR29
765. B2056_TX_RESERVED_ADDR3
766. B2056_TX_RESERVED_ADDR30
767. B2056_TX_RESERVED_ADDR31
768. B2056_TX_RESERVED_ADDR4
769. B2056_TX_RESERVED_ADDR5
770. B2056_TX_RESERVED_ADDR6
771. B2056_TX_RESERVED_ADDR7
772. B2056_TX_RXIQCAL_TXMUX
773. B2056_TX_STATUS_GM_TXLPF_GAIN
774. B2056_TX_STATUS_INTPA_GAIN
775. B2056_TX_STATUS_PAD_GAIN
776. B2056_TX_STATUS_PGA_GAIN
777. B2056_TX_STATUS_TXLPF_BW
778. B2056_TX_STATUS_TXLPF_RC
779. B2056_TX_TSSIA
780. B2056_TX_TSSIG
781. B2056_TX_TSSI_MISC1
782. B2056_TX_TSSI_MISC2
783. B2056_TX_TSSI_MISC3
784. B2056_TX_TSSI_VCM
785. B2056_TX_TXLPF_BW
786. B2056_TX_TXLPF_GAIN
787. B2056_TX_TXLPF_IDAC
788. B2056_TX_TXLPF_IDAC_0
789. B2056_TX_TXLPF_IDAC_1
790. B2056_TX_TXLPF_IDAC_2
791. B2056_TX_TXLPF_IDAC_3
792. B2056_TX_TXLPF_IDAC_4
793. B2056_TX_TXLPF_IDAC_5
794. B2056_TX_TXLPF_IDAC_6
795. B2056_TX_TXLPF_MASTER
796. B2056_TX_TXLPF_MISC
797. B2056_TX_TXLPF_OPAMP_IDAC
798. B2056_TX_TXLPF_RCCAL
799. B2056_TX_TXLPF_RCCAL_OFF0
800. B2056_TX_TXLPF_RCCAL_OFF1
801. B2056_TX_TXLPF_RCCAL_OFF2
802. B2056_TX_TXLPF_RCCAL_OFF3
803. B2056_TX_TXLPF_RCCAL_OFF4
804. B2056_TX_TXLPF_RCCAL_OFF5
805. B2056_TX_TXLPF_RCCAL_OFF6
806. B2056_TX_TXSPARE1
807. B2056_TX_TXSPARE10
808. B2056_TX_TXSPARE11
809. B2056_TX_TXSPARE12
810. B2056_TX_TXSPARE13
811. B2056_TX_TXSPARE14
812. B2056_TX_TXSPARE15
813. B2056_TX_TXSPARE16
814. B2056_TX_TXSPARE2
815. B2056_TX_TXSPARE3
816. B2056_TX_TXSPARE4
817. B2056_TX_TXSPARE5
818. B2056_TX_TXSPARE6
819. B2056_TX_TXSPARE7
820. B2056_TX_TXSPARE8
821. B2056_TX_TXSPARE9
822. B2056_TX_TX_AMP_DET
823. B2056_TX_TX_COM_MASTER1
824. B2056_TX_TX_COM_MASTER2
825. B2056_TX_TX_SSI_MASTER
826. B2056_TX_TX_SSI_MUX
827. B2056_VCM_MASK
828. B2056_W1_PU
829. B2056_W2_PU
830. B2062_N_CALIB_CTL0
831. B2062_N_CALIB_CTL1
832. B2062_N_CALIB_CTL2
833. B2062_N_CALIB_CTL3
834. B2062_N_CALIB_CTL4
835. B2062_N_CALIB_DBG0
836. B2062_N_CALIB_DBG1
837. B2062_N_CALIB_DBG2
838. B2062_N_CALIB_DBG3
839. B2062_N_CALIB_TS
840. B2062_N_COMM1
841. B2062_N_COMM10
842. B2062_N_COMM11
843. B2062_N_COMM12
844. B2062_N_COMM13
845. B2062_N_COMM14
846. B2062_N_COMM15
847. B2062_N_COMM2
848. B2062_N_COMM3
849. B2062_N_COMM4
850. B2062_N_COMM5
851. B2062_N_COMM6
852. B2062_N_COMM7
853. B2062_N_COMM8
854. B2062_N_COMM9
855. B2062_N_GEN_CTL0
856. B2062_N_IQ_CALIB
857. B2062_N_IQ_CALIB_CTL0
858. B2062_N_IQ_CALIB_CTL1
859. B2062_N_IQ_CALIB_CTL2
860. B2062_N_LGENA_BIAS0
861. B2062_N_LGENA_CTL0
862. B2062_N_LGENA_CTL1
863. B2062_N_LGENA_CTL2
864. B2062_N_LGENA_CTL3
865. B2062_N_LGENA_CTL4
866. B2062_N_LGENA_CTL5
867. B2062_N_LGENA_CTL6
868. B2062_N_LGENA_CTL7
869. B2062_N_LGENA_LPF
870. B2062_N_LGENA_TUNE0
871. B2062_N_LGENA_TUNE1
872. B2062_N_LGENA_TUNE2
873. B2062_N_LGENA_TUNE3
874. B2062_N_LGENC
875. B2062_N_LGNEA_BIAS1
876. B2062_N_PDN_CTL0
877. B2062_N_PDN_CTL1
878. B2062_N_PDN_CTL2
879. B2062_N_PDN_CTL3
880. B2062_N_PDN_CTL4
881. B2062_N_PSENSE_CTL0
882. B2062_N_PSENSE_CTL1
883. B2062_N_PSENSE_CTL2
884. B2062_N_RXA_CTL0
885. B2062_N_RXA_CTL1
886. B2062_N_RXA_CTL2
887. B2062_N_RXA_CTL3
888. B2062_N_RXA_CTL4
889. B2062_N_RXA_CTL5
890. B2062_N_RXA_CTL6
891. B2062_N_RXA_CTL7
892. B2062_N_RXBB_BIAS0
893. B2062_N_RXBB_BIAS1
894. B2062_N_RXBB_BIAS2
895. B2062_N_RXBB_BIAS3
896. B2062_N_RXBB_BIAS4
897. B2062_N_RXBB_BIAS5
898. B2062_N_RXBB_CALIB0
899. B2062_N_RXBB_CALIB1
900. B2062_N_RXBB_CALIB2
901. B2062_N_RXBB_CTL0
902. B2062_N_RXBB_CTL1
903. B2062_N_RXBB_CTL2
904. B2062_N_RXBB_GAIN0
905. B2062_N_RXBB_GAIN1
906. B2062_N_RXBB_GAIN2
907. B2062_N_RXBB_GAIN3
908. B2062_N_RXBB_RSSI0
909. B2062_N_RXBB_RSSI1
910. B2062_N_RXBB_RSSI2
911. B2062_N_RXBB_RSSI3
912. B2062_N_RXBB_RSSI4
913. B2062_N_RXBB_RSSI5
914. B2062_N_TEST_BUF0
915. B2062_N_TSSI_CTL0
916. B2062_N_TSSI_CTL1
917. B2062_N_TSSI_CTL2
918. B2062_N_TX_CTL0
919. B2062_N_TX_CTL1
920. B2062_N_TX_CTL2
921. B2062_N_TX_CTL3
922. B2062_N_TX_CTL4
923. B2062_N_TX_CTL5
924. B2062_N_TX_CTL6
925. B2062_N_TX_CTL7
926. B2062_N_TX_CTL8
927. B2062_N_TX_CTL9
928. B2062_N_TX_CTL_A
929. B2062_N_TX_GC2G
930. B2062_N_TX_GC5G
931. B2062_N_TX_PAD
932. B2062_N_TX_PADAUX
933. B2062_N_TX_PGA
934. B2062_N_TX_PGAAUX
935. B2062_N_TX_TUNE
936. B2062_S_BG_CTL0
937. B2062_S_BG_CTL1
938. B2062_S_BG_CTL2
939. B2062_S_COMM1
940. B2062_S_COMM10
941. B2062_S_COMM11
942. B2062_S_COMM12
943. B2062_S_COMM13
944. B2062_S_COMM14
945. B2062_S_COMM15
946. B2062_S_COMM2
947. B2062_S_COMM3
948. B2062_S_COMM4
949. B2062_S_COMM5
950. B2062_S_COMM6
951. B2062_S_COMM7
952. B2062_S_COMM8
953. B2062_S_COMM9
954. B2062_S_LGENG_CTL0
955. B2062_S_LGENG_CTL1
956. B2062_S_LGENG_CTL10
957. B2062_S_LGENG_CTL11
958. B2062_S_LGENG_CTL2
959. B2062_S_LGENG_CTL3
960. B2062_S_LGENG_CTL4
961. B2062_S_LGENG_CTL5
962. B2062_S_LGENG_CTL6
963. B2062_S_LGENG_CTL7
964. B2062_S_LGENG_CTL8
965. B2062_S_LGENG_CTL9
966. B2062_S_PDS_CTL0
967. B2062_S_PDS_CTL1
968. B2062_S_PDS_CTL2
969. B2062_S_PDS_CTL3
970. B2062_S_RADIO_ID_CODE
971. B2062_S_REFPLL_CTL0
972. B2062_S_REFPLL_CTL1
973. B2062_S_REFPLL_CTL10
974. B2062_S_REFPLL_CTL11
975. B2062_S_REFPLL_CTL12
976. B2062_S_REFPLL_CTL13
977. B2062_S_REFPLL_CTL14
978. B2062_S_REFPLL_CTL15
979. B2062_S_REFPLL_CTL16
980. B2062_S_REFPLL_CTL2
981. B2062_S_REFPLL_CTL3
982. B2062_S_REFPLL_CTL4
983. B2062_S_REFPLL_CTL5
984. B2062_S_REFPLL_CTL6
985. B2062_S_REFPLL_CTL7
986. B2062_S_REFPLL_CTL8
987. B2062_S_REFPLL_CTL9
988. B2062_S_RFPLL_CTL0
989. B2062_S_RFPLL_CTL1
990. B2062_S_RFPLL_CTL10
991. B2062_S_RFPLL_CTL11
992. B2062_S_RFPLL_CTL12
993. B2062_S_RFPLL_CTL13
994. B2062_S_RFPLL_CTL14
995. B2062_S_RFPLL_CTL15
996. B2062_S_RFPLL_CTL16
997. B2062_S_RFPLL_CTL17
998. B2062_S_RFPLL_CTL18
999. B2062_S_RFPLL_CTL19
1000. B2062_S_RFPLL_CTL2
1001. B2062_S_RFPLL_CTL20
1002. B2062_S_RFPLL_CTL21
1003. B2062_S_RFPLL_CTL22
1004. B2062_S_RFPLL_CTL23
1005. B2062_S_RFPLL_CTL24
1006. B2062_S_RFPLL_CTL25
1007. B2062_S_RFPLL_CTL26
1008. B2062_S_RFPLL_CTL27
1009. B2062_S_RFPLL_CTL28
1010. B2062_S_RFPLL_CTL29
1011. B2062_S_RFPLL_CTL3
1012. B2062_S_RFPLL_CTL30
1013. B2062_S_RFPLL_CTL31
1014. B2062_S_RFPLL_CTL32
1015. B2062_S_RFPLL_CTL33
1016. B2062_S_RFPLL_CTL34
1017. B2062_S_RFPLL_CTL4
1018. B2062_S_RFPLL_CTL5
1019. B2062_S_RFPLL_CTL6
1020. B2062_S_RFPLL_CTL7
1021. B2062_S_RFPLL_CTL8
1022. B2062_S_RFPLL_CTL9
1023. B2062_S_RXG_CNT0
1024. B2062_S_RXG_CNT1
1025. B2062_S_RXG_CNT10
1026. B2062_S_RXG_CNT11
1027. B2062_S_RXG_CNT12
1028. B2062_S_RXG_CNT13
1029. B2062_S_RXG_CNT14
1030. B2062_S_RXG_CNT15
1031. B2062_S_RXG_CNT16
1032. B2062_S_RXG_CNT17
1033. B2062_S_RXG_CNT2
1034. B2062_S_RXG_CNT3
1035. B2062_S_RXG_CNT4
1036. B2062_S_RXG_CNT5
1037. B2062_S_RXG_CNT6
1038. B2062_S_RXG_CNT7
1039. B2062_S_RXG_CNT8
1040. B2062_S_RXG_CNT9
1041. B2063_AFE_CTL
1042. B2063_AMUX_CTL1
1043. B2063_A_RX_1ST1
1044. B2063_A_RX_1ST2
1045. B2063_A_RX_1ST3
1046. B2063_A_RX_1ST4
1047. B2063_A_RX_1ST5
1048. B2063_A_RX_2ND1
1049. B2063_A_RX_2ND2
1050. B2063_A_RX_2ND3
1051. B2063_A_RX_2ND4
1052. B2063_A_RX_2ND5
1053. B2063_A_RX_2ND6
1054. B2063_A_RX_2ND7
1055. B2063_A_RX_MIX1
1056. B2063_A_RX_MIX2
1057. B2063_A_RX_MIX3
1058. B2063_A_RX_MIX4
1059. B2063_A_RX_MIX5
1060. B2063_A_RX_MIX6
1061. B2063_A_RX_MIX7
1062. B2063_A_RX_MIX8
1063. B2063_A_RX_PS1
1064. B2063_A_RX_PS2
1065. B2063_A_RX_PS3
1066. B2063_A_RX_PS4
1067. B2063_A_RX_PS5
1068. B2063_A_RX_PS6
1069. B2063_A_RX_PWRDET1
1070. B2063_A_RX_SP1
1071. B2063_A_RX_SP2
1072. B2063_A_RX_SP3
1073. B2063_A_RX_SP4
1074. B2063_A_RX_SP5
1075. B2063_A_RX_SP6
1076. B2063_A_RX_SP7
1077. B2063_A_RX_SPARE1
1078. B2063_A_RX_SPARE2
1079. B2063_A_RX_SPARE3
1080. B2063_BANDGAP_CTL1
1081. B2063_BANDGAP_CTL2
1082. B2063_COMM1
1083. B2063_COMM10
1084. B2063_COMM11
1085. B2063_COMM12
1086. B2063_COMM13
1087. B2063_COMM14
1088. B2063_COMM15
1089. B2063_COMM16
1090. B2063_COMM17
1091. B2063_COMM18
1092. B2063_COMM19
1093. B2063_COMM2
1094. B2063_COMM20
1095. B2063_COMM21
1096. B2063_COMM22
1097. B2063_COMM23
1098. B2063_COMM24
1099. B2063_COMM3
1100. B2063_COMM4
1101. B2063_COMM5
1102. B2063_COMM6
1103. B2063_COMM7
1104. B2063_COMM8
1105. B2063_COMM9
1106. B2063_EXT_TSSI_CTL1
1107. B2063_EXT_TSSI_CTL2
1108. B2063_GPIO_CTL1
1109. B2063_G_RX_1ST1
1110. B2063_G_RX_1ST2
1111. B2063_G_RX_1ST3
1112. B2063_G_RX_2ND1
1113. B2063_G_RX_2ND2
1114. B2063_G_RX_2ND3
1115. B2063_G_RX_2ND4
1116. B2063_G_RX_2ND5
1117. B2063_G_RX_2ND6
1118. B2063_G_RX_2ND7
1119. B2063_G_RX_2ND8
1120. B2063_G_RX_MIX1
1121. B2063_G_RX_MIX2
1122. B2063_G_RX_MIX3
1123. B2063_G_RX_MIX4
1124. B2063_G_RX_MIX5
1125. B2063_G_RX_MIX6
1126. B2063_G_RX_MIX7
1127. B2063_G_RX_MIX8
1128. B2063_G_RX_PDET1
1129. B2063_G_RX_PS1
1130. B2063_G_RX_PS2
1131. B2063_G_RX_PS3
1132. B2063_G_RX_PS4
1133. B2063_G_RX_PS5
1134. B2063_G_RX_SP1
1135. B2063_G_RX_SP10
1136. B2063_G_RX_SP11
1137. B2063_G_RX_SP2
1138. B2063_G_RX_SP3
1139. B2063_G_RX_SP4
1140. B2063_G_RX_SP5
1141. B2063_G_RX_SP6
1142. B2063_G_RX_SP7
1143. B2063_G_RX_SP8
1144. B2063_G_RX_SP9
1145. B2063_G_RX_SPARES1
1146. B2063_G_RX_SPARES2
1147. B2063_G_RX_SPARES3
1148. B2063_IQ_CALIB_CTL1
1149. B2063_IQ_CALIB_CTL2
1150. B2063_IQ_CALIB_GVAR
1151. B2063_LOGEN_ACL1
1152. B2063_LOGEN_ACL2
1153. B2063_LOGEN_ACL3
1154. B2063_LOGEN_ACL4
1155. B2063_LOGEN_ACL5
1156. B2063_LOGEN_BUF1
1157. B2063_LOGEN_BUF2
1158. B2063_LOGEN_CALIB_EN
1159. B2063_LOGEN_CBUFRX1
1160. B2063_LOGEN_CBUFRX2
1161. B2063_LOGEN_CBUFTX1
1162. B2063_LOGEN_CBUFTX2
1163. B2063_LOGEN_DIV1
1164. B2063_LOGEN_DIV2
1165. B2063_LOGEN_DIV3
1166. B2063_LOGEN_IDAC1
1167. B2063_LOGEN_MIXER1
1168. B2063_LOGEN_MIXER2
1169. B2063_LOGEN_PEAKDET1
1170. B2063_LOGEN_RCCR1
1171. B2063_LOGEN_SP1
1172. B2063_LOGEN_SP2
1173. B2063_LOGEN_SP3
1174. B2063_LOGEN_SP4
1175. B2063_LOGEN_SP5
1176. B2063_LOGEN_SPARE1
1177. B2063_LOGEN_SPARE2
1178. B2063_LOGEN_SPARE3
1179. B2063_LOGEN_VCOBUF1
1180. B2063_LO_CALIB_CALVLD1
1181. B2063_LO_CALIB_CALVLD2
1182. B2063_LO_CALIB_CTL1
1183. B2063_LO_CALIB_CTL2
1184. B2063_LO_CALIB_CTL3
1185. B2063_LO_CALIB_CVAL1
1186. B2063_LO_CALIB_CVAL2
1187. B2063_LO_CALIB_CVAL3
1188. B2063_LO_CALIB_CVAL4
1189. B2063_LO_CALIB_CVAL5
1190. B2063_LO_CALIB_CVAL6
1191. B2063_LO_CALIB_CVAL7
1192. B2063_LO_CALIB_INPUTS
1193. B2063_LO_CALIB_OVAL1
1194. B2063_LO_CALIB_OVAL2
1195. B2063_LO_CALIB_OVAL3
1196. B2063_LO_CALIB_OVAL4
1197. B2063_LO_CALIB_OVAL5
1198. B2063_LO_CALIB_OVAL6
1199. B2063_LO_CALIB_OVAL7
1200. B2063_LO_CALIB_OVR1
1201. B2063_LO_CALIB_OVR2
1202. B2063_LO_CALIB_WAITCNT
1203. B2063_LPO_CTL1
1204. B2063_PA_CTL1
1205. B2063_PA_CTL10
1206. B2063_PA_CTL11
1207. B2063_PA_CTL12
1208. B2063_PA_CTL13
1209. B2063_PA_CTL2
1210. B2063_PA_CTL3
1211. B2063_PA_CTL4
1212. B2063_PA_CTL5
1213. B2063_PA_CTL6
1214. B2063_PA_CTL7
1215. B2063_PA_CTL8
1216. B2063_PA_CTL9
1217. B2063_PA_SP1
1218. B2063_PA_SP2
1219. B2063_PA_SP3
1220. B2063_PA_SP4
1221. B2063_PA_SP5
1222. B2063_PA_SP6
1223. B2063_PA_SP7
1224. B2063_PLL_JTAG_CALNRST
1225. B2063_PLL_JTAG_IN_PLL1
1226. B2063_PLL_JTAG_IN_PLL2
1227. B2063_PLL_JTAG_PLL_CP1
1228. B2063_PLL_JTAG_PLL_CP2
1229. B2063_PLL_JTAG_PLL_CP3
1230. B2063_PLL_JTAG_PLL_CP4
1231. B2063_PLL_JTAG_PLL_CTL1
1232. B2063_PLL_JTAG_PLL_LF1
1233. B2063_PLL_JTAG_PLL_LF2
1234. B2063_PLL_JTAG_PLL_LF3
1235. B2063_PLL_JTAG_PLL_LF4
1236. B2063_PLL_JTAG_PLL_SG1
1237. B2063_PLL_JTAG_PLL_SG2
1238. B2063_PLL_JTAG_PLL_SG3
1239. B2063_PLL_JTAG_PLL_SG4
1240. B2063_PLL_JTAG_PLL_SG5
1241. B2063_PLL_JTAG_PLL_VCO1
1242. B2063_PLL_JTAG_PLL_VCO2
1243. B2063_PLL_JTAG_PLL_VCO_CALIB1
1244. B2063_PLL_JTAG_PLL_VCO_CALIB10
1245. B2063_PLL_JTAG_PLL_VCO_CALIB2
1246. B2063_PLL_JTAG_PLL_VCO_CALIB3
1247. B2063_PLL_JTAG_PLL_VCO_CALIB4
1248. B2063_PLL_JTAG_PLL_VCO_CALIB5
1249. B2063_PLL_JTAG_PLL_VCO_CALIB6
1250. B2063_PLL_JTAG_PLL_VCO_CALIB7
1251. B2063_PLL_JTAG_PLL_VCO_CALIB8
1252. B2063_PLL_JTAG_PLL_VCO_CALIB9
1253. B2063_PLL_JTAG_PLL_XTAL3
1254. B2063_PLL_JTAG_PLL_XTAL_12
1255. B2063_PLL_SP1
1256. B2063_PLL_SP2
1257. B2063_PWR_SWITCH_CTL
1258. B2063_RADIO_ID_CODE
1259. B2063_RC_CALIB_CTL1
1260. B2063_RC_CALIB_CTL10
1261. B2063_RC_CALIB_CTL2
1262. B2063_RC_CALIB_CTL3
1263. B2063_RC_CALIB_CTL4
1264. B2063_RC_CALIB_CTL5
1265. B2063_RC_CALIB_CTL6
1266. B2063_RC_CALIB_CTL7
1267. B2063_RC_CALIB_CTL8
1268. B2063_RC_CALIB_CTL9
1269. B2063_REG_SP1
1270. B2063_RX_BB_CTL1
1271. B2063_RX_BB_CTL2
1272. B2063_RX_BB_CTL3
1273. B2063_RX_BB_CTL4
1274. B2063_RX_BB_CTL5
1275. B2063_RX_BB_CTL6
1276. B2063_RX_BB_CTL7
1277. B2063_RX_BB_CTL8
1278. B2063_RX_BB_CTL9
1279. B2063_RX_BB_SP1
1280. B2063_RX_BB_SP2
1281. B2063_RX_BB_SP3
1282. B2063_RX_BB_SP4
1283. B2063_RX_BB_SP5
1284. B2063_RX_BB_SP6
1285. B2063_RX_BB_SP7
1286. B2063_RX_BB_SP8
1287. B2063_RX_TIA_CTL1
1288. B2063_RX_TIA_CTL2
1289. B2063_RX_TIA_CTL3
1290. B2063_RX_TIA_CTL4
1291. B2063_RX_TIA_CTL5
1292. B2063_RX_TIA_CTL6
1293. B2063_TEMPSENSE_CTL1
1294. B2063_TEMPSENSE_CTL2
1295. B2063_TX_BB_CTL1
1296. B2063_TX_BB_CTL2
1297. B2063_TX_BB_CTL3
1298. B2063_TX_BB_CTL4
1299. B2063_TX_BB_SP1
1300. B2063_TX_BB_SP2
1301. B2063_TX_BB_SP3
1302. B2063_TX_RF_CTL1
1303. B2063_TX_RF_CTL10
1304. B2063_TX_RF_CTL14
1305. B2063_TX_RF_CTL15
1306. B2063_TX_RF_CTL2
1307. B2063_TX_RF_CTL3
1308. B2063_TX_RF_CTL4
1309. B2063_TX_RF_CTL5
1310. B2063_TX_RF_CTL6
1311. B2063_TX_RF_CTL7
1312. B2063_TX_RF_CTL8
1313. B2063_TX_RF_CTL9
1314. B2063_TX_RF_IDAC_LO_BB_I
1315. B2063_TX_RF_IDAC_LO_BB_Q
1316. B2063_TX_RF_IDAC_LO_RF_I
1317. B2063_TX_RF_IDAC_LO_RF_Q
1318. B2063_TX_RF_SP1
1319. B2063_TX_RF_SP10
1320. B2063_TX_RF_SP11
1321. B2063_TX_RF_SP12
1322. B2063_TX_RF_SP13
1323. B2063_TX_RF_SP14
1324. B2063_TX_RF_SP15
1325. B2063_TX_RF_SP16
1326. B2063_TX_RF_SP17
1327. B2063_TX_RF_SP2
1328. B2063_TX_RF_SP3
1329. B2063_TX_RF_SP4
1330. B2063_TX_RF_SP5
1331. B2063_TX_RF_SP6
1332. B2063_TX_RF_SP7
1333. B2063_TX_RF_SP8
1334. B2063_TX_RF_SP9
1335. B2063_TX_RX_LOOPBACK1
1336. B2063_TX_RX_LOOPBACK2
1337. B2063_VREG_CTL1
1338. B206X_FLAG_A
1339. B206X_FLAG_G
1340. B21
1341. B22
1342. B230400
1343. B24
1344. B2400
1345. B25
1346. B2500000
1347. B26
1348. B28_DPT_CTRL
1349. B28_DPT_INI
1350. B28_DPT_TST
1351. B28_DPT_VAL
1352. B28_Y2_ASF_HOST_COM
1353. B28_Y2_ASF_IRQ_V_BASE
1354. B28_Y2_ASF_STAT_CMD
1355. B28_Y2_DATA_REG_1
1356. B28_Y2_DATA_REG_2
1357. B28_Y2_DATA_REG_3
1358. B28_Y2_DATA_REG_4
1359. B28_Y2_SMB_CONFIG
1360. B28_Y2_SMB_CSD_REG
1361. B2C2_FLEX_INTERNALADDR_TO_PCIOFFSET
1362. B2C2_FLEX_PCIOFFSET_TO_INTERNALADDR
1363. B2C2_USB_CTRL_PIPE_IN
1364. B2C2_USB_CTRL_PIPE_OUT
1365. B2C2_USB_DATA_PIPE
1366. B2C2_USB_FLASH_BLOCK
1367. B2C2_USB_FRAMES_PER_ISO
1368. B2C2_USB_I2C_REQUEST
1369. B2C2_USB_NUM_ISO_URB
1370. B2C2_USB_READ_REG
1371. B2C2_USB_READ_V8_MEM
1372. B2C2_USB_UTILITY
1373. B2C2_USB_WRITEREGHI
1374. B2C2_USB_WRITE_REG
1375. B2C2_USB_WRITE_V8_MEM
1376. B2C2_WAIT_FOR_OPERATION_RDW
1377. B2C2_WAIT_FOR_OPERATION_RW
1378. B2C2_WAIT_FOR_OPERATION_V8FLASH
1379. B2C2_WAIT_FOR_OPERATION_V8READ
1380. B2C2_WAIT_FOR_OPERATION_V8WRITE
1381. B2C2_WAIT_FOR_OPERATION_WDW
1382. B2GPAPEPOLARITY
1383. B2I
1384. B2R2MCDE
1385. B2SEL
1386. B2_BSC_CTRL
1387. B2_BSC_INI
1388. B2_BSC_STAT
1389. B2_BSC_TST
1390. B2_BSC_VAL
1391. B2_CHIP_ID
1392. B2_CONN_TYP
1393. B2_CTRL_2
1394. B2_DESC_ADDR_H
1395. B2_E_0
1396. B2_E_1
1397. B2_E_2
1398. B2_E_3
1399. B2_FAR
1400. B2_FDP
1401. B2_GP_IO
1402. B2_I2C_CTRL
1403. B2_I2C_DATA
1404. B2_I2C_IRQ
1405. B2_I2C_SW
1406. B2_IFACE_REG
1407. B2_IRQM_CTRL
1408. B2_IRQM_HWE_MSK
1409. B2_IRQM_INI
1410. B2_IRQM_MSK
1411. B2_IRQM_TEST
1412. B2_IRQM_VAL
1413. B2_IRQ_MOD_CTRL
1414. B2_IRQ_MOD_INI
1415. B2_IRQ_MOD_TEST
1416. B2_IRQ_MOD_VAL
1417. B2_LD_CRTL
1418. B2_LD_CTRL
1419. B2_LD_TEST
1420. B2_MAC_0
1421. B2_MAC_1
1422. B2_MAC_2
1423. B2_MAC_3
1424. B2_MAC_4
1425. B2_MAC_5
1426. B2_MAC_6
1427. B2_MAC_7
1428. B2_MAC_CFG
1429. B2_PMD_TYP
1430. B2_PROT_ISO7776
1431. B2_PROT_LAPD
1432. B2_PROT_PPP
1433. B2_PROT_SDLC
1434. B2_PROT_T30
1435. B2_PROT_TRANSPARENT
1436. B2_PROT_TRANSPARENT_IGNORE_B1_FRAMING_ERRORS
1437. B2_RTM_CRTL
1438. B2_RTM_INI
1439. B2_RTM_TEST
1440. B2_RTM_VAL
1441. B2_TI_CRTL
1442. B2_TI_CTRL
1443. B2_TI_INI
1444. B2_TI_TEST
1445. B2_TI_VAL
1446. B2_TOK_COUNT
1447. B2_TST_CTRL1
1448. B2_TST_CTRL2
1449. B2_TST_CTRL_2
1450. B2_WDOG_CRTL
1451. B2_WDOG_INI
1452. B2_WDOG_TEST
1453. B2_WDOG_VAL
1454. B2_Y2_CLK_CTRL
1455. B2_Y2_CLK_GATE
1456. B2_Y2_HW_RES
1457. B3
1458. B300
1459. B3000000
1460. B307200
1461. B3500000
1462. B38400
1463. B3SEL
1464. B3WIREADDREAALENGTH
1465. B3WIREADDRESSLENGTH
1466. B3WIREDATALENGTH
1467. B3WIRERFPOWERDOWN
1468. B3WIRE_ADDRESSLENGTH
1469. B3WIRE_DATALENGTH
1470. B3_CFG_SPC
1471. B3_MA_RCINI_RX1
1472. B3_MA_RCINI_RX2
1473. B3_MA_RCINI_TX1
1474. B3_MA_RCINI_TX2
1475. B3_MA_RCVAL_RX1
1476. B3_MA_RCVAL_RX2
1477. B3_MA_RCVAL_TX1
1478. B3_MA_RCVAL_TX2
1479. B3_MA_RC_CTRL
1480. B3_MA_RC_TEST
1481. B3_MA_TOINI_RX1
1482. B3_MA_TOINI_RX2
1483. B3_MA_TOINI_TX1
1484. B3_MA_TOINI_TX2
1485. B3_MA_TOVAL_RX1
1486. B3_MA_TOVAL_RX2
1487. B3_MA_TOVAL_TX1
1488. B3_MA_TOVAL_TX2
1489. B3_MA_TO_CTRL
1490. B3_MA_TO_TEST
1491. B3_PA_CTRL
1492. B3_PA_TEST
1493. B3_PA_TOINI_RX1
1494. B3_PA_TOINI_RX2
1495. B3_PA_TOINI_TX1
1496. B3_PA_TOINI_TX2
1497. B3_PA_TOVAL_RX1
1498. B3_PA_TOVAL_RX2
1499. B3_PA_TOVAL_TX1
1500. B3_PA_TOVAL_TX2
1501. B3_PROT_ISO8208
1502. B3_PROT_T30
1503. B3_PROT_T30EXT
1504. B3_PROT_T90NL
1505. B3_PROT_TRANSPARENT
1506. B3_PROT_X25_DCE
1507. B3_RAM_ADDR
1508. B3_RAM_DATA_HI
1509. B3_RAM_DATA_LO
1510. B3_RI_CTRL
1511. B3_RI_RTO_R1
1512. B3_RI_RTO_R2
1513. B3_RI_RTO_XA1
1514. B3_RI_RTO_XA2
1515. B3_RI_RTO_XS1
1516. B3_RI_RTO_XS2
1517. B3_RI_TEST
1518. B3_RI_TO_VAL
1519. B3_RI_WTO_R1
1520. B3_RI_WTO_R2
1521. B3_RI_WTO_XA1
1522. B3_RI_WTO_XA2
1523. B3_RI_WTO_XS1
1524. B3_RI_WTO_XS2
1525. B4
1526. B4000000
1527. B40MDCLKPOWERUP
1528. B43_ANTENNA0
1529. B43_ANTENNA1
1530. B43_ANTENNA2
1531. B43_ANTENNA3
1532. B43_ANTENNA_AUTO
1533. B43_ANTENNA_AUTO0
1534. B43_ANTENNA_AUTO1
1535. B43_ANTENNA_DEFAULT
1536. B43_BAND_2G
1537. B43_BAND_5G_HI
1538. B43_BAND_5G_LO
1539. B43_BAND_5G_MI
1540. B43_BCMA_CLKCTLST_80211_PLL_REQ
1541. B43_BCMA_CLKCTLST_80211_PLL_ST
1542. B43_BCMA_CLKCTLST_PHY_PLL_REQ
1543. B43_BCMA_CLKCTLST_PHY_PLL_ST
1544. B43_BCMA_IOCTL_DAC
1545. B43_BCMA_IOCTL_GMODE
1546. B43_BCMA_IOCTL_MACPHYCLKEN
1547. B43_BCMA_IOCTL_PHY_BW
1548. B43_BCMA_IOCTL_PHY_BW_10MHZ
1549. B43_BCMA_IOCTL_PHY_BW_20MHZ
1550. B43_BCMA_IOCTL_PHY_BW_40MHZ
1551. B43_BCMA_IOCTL_PHY_BW_80MHZ
1552. B43_BCMA_IOCTL_PHY_CLKEN
1553. B43_BCMA_IOCTL_PHY_RESET
1554. B43_BCMA_IOCTL_PLLREFSEL
1555. B43_BCMA_IOST_2G_PHY
1556. B43_BCMA_IOST_5G_PHY
1557. B43_BCMA_IOST_DUALB_PHY
1558. B43_BCMA_IOST_FASTCLKA
1559. B43_BFH2_GPLL_WAR2
1560. B43_BFH2_INTERNDET_TXIQCAL
1561. B43_BFH2_IPALVLSHIFT_3P3
1562. B43_BFH2_XTALBUFOUTEN
1563. B43_BFH_3TSWITCH
1564. B43_BFH_BUCKBOOST
1565. B43_BFH_EXTLNA_5GHZ
1566. B43_BFH_FEM_BT
1567. B43_BFH_NOCBUCK
1568. B43_BFH_NOPA
1569. B43_BFH_PALDO
1570. B43_BFH_PAREF
1571. B43_BFH_PHASESHIFT
1572. B43_BFH_RSSIINV
1573. B43_BFL2_2G_SPUR_WAR
1574. B43_BFL2_2X4_DIV
1575. B43_BFL2_5G_PWRGAIN
1576. B43_BFL2_APLL_WAR
1577. B43_BFL2_BTC3WIRE
1578. B43_BFL2_CAESERS_BRD
1579. B43_BFL2_GPLL_WAR
1580. B43_BFL2_PCIEWAR_OVR
1581. B43_BFL2_RXBB_INT_REG_DIS
1582. B43_BFL2_SINGLEANT_CCK
1583. B43_BFL2_SKWRKFEM_BRD
1584. B43_BFL2_SPUR_WAR
1585. B43_BFL2_TXPWRCTRL_EN
1586. B43_BFL_AFTERBURNER
1587. B43_BFL_AIRLINEMODE
1588. B43_BFL_ALTIQ
1589. B43_BFL_BTCMOD
1590. B43_BFL_BTCOEXIST
1591. B43_BFL_CCKHIPWR
1592. B43_BFL_ENETADM
1593. B43_BFL_ENETSPI
1594. B43_BFL_ENETVLAN
1595. B43_BFL_EXTLNA
1596. B43_BFL_FEM
1597. B43_BFL_HGPA
1598. B43_BFL_NOPCI
1599. B43_BFL_PACTRL
1600. B43_BFL_RSSI
1601. B43_BFL_XTAL_NOSLOW
1602. B43_BUS_BCMA
1603. B43_BUS_H_
1604. B43_BUS_SSB
1605. B43_CCK_RATE_11MB
1606. B43_CCK_RATE_1MB
1607. B43_CCK_RATE_2MB
1608. B43_CCK_RATE_5MB
1609. B43_DBG_DMAOVERFLOW
1610. B43_DBG_DMAVERBOSE
1611. B43_DBG_FIRMWARE
1612. B43_DBG_KEYS
1613. B43_DBG_LO
1614. B43_DBG_PWORK_FAST
1615. B43_DBG_PWORK_STOP
1616. B43_DBG_VERBOSESTATS
1617. B43_DBG_XMITPOWER
1618. B43_DC_LT_SIZE
1619. B43_DEBUG
1620. B43_DEBUGFS_FOPS
1621. B43_DEBUGFS_H_
1622. B43_DEBUGIRQ_ACK
1623. B43_DEBUGIRQ_DUMP_REGS
1624. B43_DEBUGIRQ_DUMP_SHM
1625. B43_DEBUGIRQ_MARKER
1626. B43_DEBUGIRQ_PANIC
1627. B43_DEBUGIRQ_REASON_REG
1628. B43_DEFAULT_LONG_RETRY_LIMIT
1629. B43_DEFAULT_SHORT_RETRY_LIMIT
1630. B43_DMA0_RX_FW351_BUFSIZE
1631. B43_DMA0_RX_FW351_FO
1632. B43_DMA0_RX_FW598_BUFSIZE
1633. B43_DMA0_RX_FW598_FO
1634. B43_DMA32_DCTL_ADDREXT_MASK
1635. B43_DMA32_DCTL_ADDREXT_SHIFT
1636. B43_DMA32_DCTL_BYTECNT
1637. B43_DMA32_DCTL_DTABLEEND
1638. B43_DMA32_DCTL_FRAMEEND
1639. B43_DMA32_DCTL_FRAMESTART
1640. B43_DMA32_DCTL_IRQ
1641. B43_DMA32_RINGMEMSIZE
1642. B43_DMA32_RXACTIVE
1643. B43_DMA32_RXADDREXT_MASK
1644. B43_DMA32_RXADDREXT_SHIFT
1645. B43_DMA32_RXCTL
1646. B43_DMA32_RXDIRECTFIFO
1647. B43_DMA32_RXDPTR
1648. B43_DMA32_RXENABLE
1649. B43_DMA32_RXERROR
1650. B43_DMA32_RXERR_BUFWRITE
1651. B43_DMA32_RXERR_DESCREAD
1652. B43_DMA32_RXERR_NOERR
1653. B43_DMA32_RXERR_OVERFLOW
1654. B43_DMA32_RXERR_PROT
1655. B43_DMA32_RXFROFF_MASK
1656. B43_DMA32_RXFROFF_SHIFT
1657. B43_DMA32_RXINDEX
1658. B43_DMA32_RXPARITYDISABLE
1659. B43_DMA32_RXRING
1660. B43_DMA32_RXSTATE
1661. B43_DMA32_RXSTATUS
1662. B43_DMA32_RXSTAT_ACTIVE
1663. B43_DMA32_RXSTAT_DISABLED
1664. B43_DMA32_RXSTAT_IDLEWAIT
1665. B43_DMA32_RXSTAT_STOPPED
1666. B43_DMA32_TXACTIVE
1667. B43_DMA32_TXADDREXT_MASK
1668. B43_DMA32_TXADDREXT_SHIFT
1669. B43_DMA32_TXCTL
1670. B43_DMA32_TXDPTR
1671. B43_DMA32_TXENABLE
1672. B43_DMA32_TXERROR
1673. B43_DMA32_TXERR_BUFREAD
1674. B43_DMA32_TXERR_DESCREAD
1675. B43_DMA32_TXERR_NOERR
1676. B43_DMA32_TXERR_PROT
1677. B43_DMA32_TXERR_UNDERRUN
1678. B43_DMA32_TXFLUSH
1679. B43_DMA32_TXINDEX
1680. B43_DMA32_TXLOOPBACK
1681. B43_DMA32_TXPARITYDISABLE
1682. B43_DMA32_TXRING
1683. B43_DMA32_TXSTATE
1684. B43_DMA32_TXSTATUS
1685. B43_DMA32_TXSTAT_ACTIVE
1686. B43_DMA32_TXSTAT_DISABLED
1687. B43_DMA32_TXSTAT_IDLEWAIT
1688. B43_DMA32_TXSTAT_STOPPED
1689. B43_DMA32_TXSTAT_SUSP
1690. B43_DMA32_TXSUSPEND
1691. B43_DMA64_DCTL0_DTABLEEND
1692. B43_DMA64_DCTL0_FRAMEEND
1693. B43_DMA64_DCTL0_FRAMESTART
1694. B43_DMA64_DCTL0_IRQ
1695. B43_DMA64_DCTL1_ADDREXT_MASK
1696. B43_DMA64_DCTL1_ADDREXT_SHIFT
1697. B43_DMA64_DCTL1_BYTECNT
1698. B43_DMA64_RINGMEMSIZE
1699. B43_DMA64_RXADDREXT_MASK
1700. B43_DMA64_RXADDREXT_SHIFT
1701. B43_DMA64_RXCTL
1702. B43_DMA64_RXDIRECTFIFO
1703. B43_DMA64_RXENABLE
1704. B43_DMA64_RXERR
1705. B43_DMA64_RXERRDPTR
1706. B43_DMA64_RXERROR
1707. B43_DMA64_RXERR_CORE
1708. B43_DMA64_RXERR_DESCREAD
1709. B43_DMA64_RXERR_NOERR
1710. B43_DMA64_RXERR_PROT
1711. B43_DMA64_RXERR_TRANSFER
1712. B43_DMA64_RXERR_UNDERRUN
1713. B43_DMA64_RXFROFF_MASK
1714. B43_DMA64_RXFROFF_SHIFT
1715. B43_DMA64_RXINDEX
1716. B43_DMA64_RXPARITYDISABLE
1717. B43_DMA64_RXRINGHI
1718. B43_DMA64_RXRINGLO
1719. B43_DMA64_RXSTAT
1720. B43_DMA64_RXSTATDPTR
1721. B43_DMA64_RXSTATUS
1722. B43_DMA64_RXSTAT_ACTIVE
1723. B43_DMA64_RXSTAT_DISABLED
1724. B43_DMA64_RXSTAT_IDLEWAIT
1725. B43_DMA64_RXSTAT_STOPPED
1726. B43_DMA64_RXSTAT_SUSP
1727. B43_DMA64_TXADDREXT_MASK
1728. B43_DMA64_TXADDREXT_SHIFT
1729. B43_DMA64_TXCTL
1730. B43_DMA64_TXENABLE
1731. B43_DMA64_TXERR
1732. B43_DMA64_TXERRDPTR
1733. B43_DMA64_TXERROR
1734. B43_DMA64_TXERR_CORE
1735. B43_DMA64_TXERR_DESCREAD
1736. B43_DMA64_TXERR_NOERR
1737. B43_DMA64_TXERR_PROT
1738. B43_DMA64_TXERR_TRANSFER
1739. B43_DMA64_TXERR_UNDERRUN
1740. B43_DMA64_TXFLUSH
1741. B43_DMA64_TXINDEX
1742. B43_DMA64_TXLOOPBACK
1743. B43_DMA64_TXPARITYDISABLE
1744. B43_DMA64_TXRINGHI
1745. B43_DMA64_TXRINGLO
1746. B43_DMA64_TXSTAT
1747. B43_DMA64_TXSTATDPTR
1748. B43_DMA64_TXSTATUS
1749. B43_DMA64_TXSTAT_ACTIVE
1750. B43_DMA64_TXSTAT_DISABLED
1751. B43_DMA64_TXSTAT_IDLEWAIT
1752. B43_DMA64_TXSTAT_STOPPED
1753. B43_DMA64_TXSTAT_SUSP
1754. B43_DMA64_TXSUSPEND
1755. B43_DMAIRQ_FATALMASK
1756. B43_DMAIRQ_RDESC_UFLOW
1757. B43_DMAIRQ_RX_DONE
1758. B43_DMA_30BIT
1759. B43_DMA_32BIT
1760. B43_DMA_64BIT
1761. B43_DMA_ADDR_EXT
1762. B43_DMA_ADDR_HIGH
1763. B43_DMA_ADDR_LOW
1764. B43_DMA_H_
1765. B43_DMA_PTR_POISON
1766. B43_FWCAPA_HWCRYPTO
1767. B43_FWCAPA_QOS
1768. B43_FWPANIC_DIE
1769. B43_FWPANIC_REASON_REG
1770. B43_FWPANIC_RESTART
1771. B43_FWTYPE_OPENSOURCE
1772. B43_FWTYPE_PROPRIETARY
1773. B43_FW_HDR_351
1774. B43_FW_HDR_410
1775. B43_FW_HDR_598
1776. B43_FW_TYPE_IV
1777. B43_FW_TYPE_PCM
1778. B43_FW_TYPE_UCODE
1779. B43_GPIO_CONTROL
1780. B43_GTAB
1781. B43_GTAB_NRSSI
1782. B43_GTAB_ORIGTR
1783. B43_GTAB_TRFEMW
1784. B43_HF_2060W
1785. B43_HF_20IN40IQW
1786. B43_HF_4318TSSI
1787. B43_HF_ACIW
1788. B43_HF_ACPR
1789. B43_HF_AFTERBURNER
1790. B43_HF_ANTDIVHELP
1791. B43_HF_ANTSEL
1792. B43_HF_ANTSELEN
1793. B43_HF_ANTSELMODE
1794. B43_HF_BT3COEXT
1795. B43_HF_BT4PRIOCOEX
1796. B43_HF_BTCANT
1797. B43_HF_BTCOEX
1798. B43_HF_BTCOEXALT
1799. B43_HF_CCKBOOST
1800. B43_HF_DSCRQ
1801. B43_HF_EDCF
1802. B43_HF_FBCMCFIFO
1803. B43_HF_FWKUP
1804. B43_HF_GDCW
1805. B43_HF_HWPCTL
1806. B43_HF_MLADVW
1807. B43_HF_N40W
1808. B43_HF_OFDMPABOOST
1809. B43_HF_PCISCW
1810. B43_HF_PR45960W
1811. B43_HF_RADARW
1812. B43_HF_RXPULLW
1813. B43_HF_SKCFPUP
1814. B43_HF_SYMW
1815. B43_HF_TSSIRPSMW
1816. B43_HF_TXBTCHECK
1817. B43_HF_USEDEFKEYS
1818. B43_HF_VCORECALC
1819. B43_HTTAB16
1820. B43_HTTAB32
1821. B43_HTTAB8
1822. B43_HTTAB_16BIT
1823. B43_HTTAB_1A_C0_LATE_SIZE
1824. B43_HTTAB_32BIT
1825. B43_HTTAB_8BIT
1826. B43_HTTAB_TYPEMASK
1827. B43_H_
1828. B43_INTERFMODE_AUTOWLAN
1829. B43_INTERFMODE_MANUALWLAN
1830. B43_INTERFMODE_NONE
1831. B43_INTERFMODE_NONWLAN
1832. B43_INTERFSTACK_SIZE
1833. B43_IRQ_ALL
1834. B43_IRQ_ATIM_END
1835. B43_IRQ_BEACON
1836. B43_IRQ_BEACON_CANCEL
1837. B43_IRQ_BEACON_TX_OK
1838. B43_IRQ_CCA_MEASURE_OK
1839. B43_IRQ_DMA
1840. B43_IRQ_MAC_SUSPENDED
1841. B43_IRQ_MAC_TXERR
1842. B43_IRQ_MASKTEMPLATE
1843. B43_IRQ_NOISESAMPLE_OK
1844. B43_IRQ_PHY_G_CHANGED
1845. B43_IRQ_PHY_TXERR
1846. B43_IRQ_PIO_WORKAROUND
1847. B43_IRQ_PMEVENT
1848. B43_IRQ_PMQ
1849. B43_IRQ_RFKILL
1850. B43_IRQ_TBTT_INDI
1851. B43_IRQ_TIMEOUT
1852. B43_IRQ_TIMER0
1853. B43_IRQ_TIMER1
1854. B43_IRQ_TXFIFO_FLUSH_OK
1855. B43_IRQ_TX_OK
1856. B43_IRQ_UCODE_DEBUG
1857. B43_IV_32BIT
1858. B43_IV_OFFSET_MASK
1859. B43_LCNTAB16
1860. B43_LCNTAB32
1861. B43_LCNTAB8
1862. B43_LCNTAB_16BIT
1863. B43_LCNTAB_32BIT
1864. B43_LCNTAB_8BIT
1865. B43_LCNTAB_TX_GAIN_SIZE
1866. B43_LCNTAB_TYPEMASK
1867. B43_LEDS_H_
1868. B43_LED_ACTIVELOW
1869. B43_LED_ACTIVITY
1870. B43_LED_APTRANSFER
1871. B43_LED_ASSOC
1872. B43_LED_BEHAVIOUR
1873. B43_LED_INACTIVE
1874. B43_LED_MAX_NAME_LEN
1875. B43_LED_MODE_BG
1876. B43_LED_OFF
1877. B43_LED_ON
1878. B43_LED_RADIO_A
1879. B43_LED_RADIO_ALL
1880. B43_LED_RADIO_B
1881. B43_LED_TRANSFER
1882. B43_LED_WEIRD
1883. B43_LOCTL_POISON
1884. B43_LO_CALIB_EXPIRE
1885. B43_LO_H_
1886. B43_LO_PWRVEC_EXPIRE
1887. B43_LO_TXCTL_EXPIRE
1888. B43_LPPHY_4C3
1889. B43_LPPHY_4C4
1890. B43_LPPHY_4C5
1891. B43_LPPHY_ADC_COMPENSATION_CTL
1892. B43_LPPHY_ADVANCEDRETARDROTOR_ADDR
1893. B43_LPPHY_AFE_ADC_CTL_0
1894. B43_LPPHY_AFE_ADC_CTL_1
1895. B43_LPPHY_AFE_ADC_CTL_2
1896. B43_LPPHY_AFE_CTL
1897. B43_LPPHY_AFE_CTL_OVR
1898. B43_LPPHY_AFE_CTL_OVRVAL
1899. B43_LPPHY_AFE_DAC_CTL
1900. B43_LPPHY_AFE_DDFS
1901. B43_LPPHY_AFE_DDFS_INCR_INIT
1902. B43_LPPHY_AFE_DDFS_POINTER_INIT
1903. B43_LPPHY_AFE_RSSI_CTL_0
1904. B43_LPPHY_AFE_RSSI_CTL_1
1905. B43_LPPHY_AFE_RSSI_SEL
1906. B43_LPPHY_AGC_GAIN
1907. B43_LPPHY_ALPHA1
1908. B43_LPPHY_ALPHA2
1909. B43_LPPHY_ANGLESCALE
1910. B43_LPPHY_A_PHY_CTL_ADDR
1911. B43_LPPHY_BBCONFIG
1912. B43_LPPHY_BETA1
1913. B43_LPPHY_BETA2
1914. B43_LPPHY_BISTSTAT0
1915. B43_LPPHY_BISTSTAT1
1916. B43_LPPHY_BLANKCOUNTLNAPGA
1917. B43_LPPHY_B_BBCONFIG
1918. B43_LPPHY_B_BIST_STAT
1919. B43_LPPHY_B_CHANNEL
1920. B43_LPPHY_B_CRS_THRESH
1921. B43_LPPHY_B_FOURWIRE_ADDR
1922. B43_LPPHY_B_FOURWIRE_DATA_HI
1923. B43_LPPHY_B_FOURWIRE_DATA_LO
1924. B43_LPPHY_B_RX_STAT0
1925. B43_LPPHY_B_RX_STAT1
1926. B43_LPPHY_B_RX_STAT2
1927. B43_LPPHY_B_RX_STAT3
1928. B43_LPPHY_B_TEST
1929. B43_LPPHY_B_TXERROR
1930. B43_LPPHY_B_VERSION
1931. B43_LPPHY_B_WORKAROUND
1932. B43_LPPHY_CCKCOEFF1
1933. B43_LPPHY_CCKCOEFF2
1934. B43_LPPHY_CCKLMSSTEPSIZE
1935. B43_LPPHY_CCKSTARTDELAYLONG
1936. B43_LPPHY_CCKSTARTDELAYSHORT
1937. B43_LPPHY_CCK_TX_PHY_CRS_DELAY_VAL
1938. B43_LPPHY_CHANNEL
1939. B43_LPPHY_CLASSIFIER_CTL
1940. B43_LPPHY_CLIPCTRTHRESH
1941. B43_LPPHY_CLIPTHRESH
1942. B43_LPPHY_CLKEN_CTL
1943. B43_LPPHY_COARSEESTIM_ADDR
1944. B43_LPPHY_CORRELATOR_DIS_DELAY
1945. B43_LPPHY_CPAROTATEVAL
1946. B43_LPPHY_CPA_TAILCOUNT_VAL
1947. B43_LPPHY_CRSDROPOUTTO
1948. B43_LPPHY_CRSGAIN_CTL
1949. B43_LPPHY_CRS_ED_THRESH
1950. B43_LPPHY_DATA_TO
1951. B43_LPPHY_DCOFFSETTRANSIENT
1952. B43_LPPHY_DC_BLANK_INT
1953. B43_LPPHY_DC_FILTER_DELAY1
1954. B43_LPPHY_DETECTOR_DELAY_ADJUST
1955. B43_LPPHY_DFEBYPASS
1956. B43_LPPHY_DIVERSITY_GAINBACK
1957. B43_LPPHY_DSSSCOEFF1
1958. B43_LPPHY_DSSSCOEFF2
1959. B43_LPPHY_DSSSPWR_THRESH0
1960. B43_LPPHY_DSSSPWR_THRESH1
1961. B43_LPPHY_DSSSSIGPOW
1962. B43_LPPHY_DSSSSTEP
1963. B43_LPPHY_DSSSWARMUP
1964. B43_LPPHY_DSSS_CONFIRM_CNT
1965. B43_LPPHY_ED_OFFSET_CONFIRM_TIMER_VAL
1966. B43_LPPHY_ED_ON_CONFIRM_TIMER_VAL
1967. B43_LPPHY_ED_TOVAL
1968. B43_LPPHY_FINEDIGIGAIN_CTL
1969. B43_LPPHY_FINEFREQEST
1970. B43_LPPHY_FOURWIREDATAHI
1971. B43_LPPHY_FOURWIREDATALO
1972. B43_LPPHY_FOURWIRE_ADDR
1973. B43_LPPHY_FOURWIRE_CTL
1974. B43_LPPHY_GAINDIRECTMISMATCH
1975. B43_LPPHY_GAINMISMATCH
1976. B43_LPPHY_GAINTBLLNATRSW
1977. B43_LPPHY_GAIN_MISMATCH_LIMIT
1978. B43_LPPHY_GPIO_OUT
1979. B43_LPPHY_GPIO_OUTEN
1980. B43_LPPHY_GPIO_SELECT
1981. B43_LPPHY_HIGAINDB
1982. B43_LPPHY_HOLD_CRS_ON_VAL
1983. B43_LPPHY_IDLEAFTERPKTRXTO
1984. B43_LPPHY_IDLETIME_CRS_ON_HI
1985. B43_LPPHY_IDLETIME_CRS_ON_LO
1986. B43_LPPHY_IDLETIME_CTL
1987. B43_LPPHY_IDLETIME_MEAS_TIME_HI
1988. B43_LPPHY_IDLETIME_MEAS_TIME_LO
1989. B43_LPPHY_INPUT_PWRDB
1990. B43_LPPHY_IQLO_CAL_CMD
1991. B43_LPPHY_IQLO_CAL_CMD_G_CTL
1992. B43_LPPHY_IQLO_CAL_CMD_N_NUM
1993. B43_LPPHY_IQ_ACC_HI_ADDR
1994. B43_LPPHY_IQ_ACC_LO_ADDR
1995. B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR
1996. B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR
1997. B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR
1998. B43_LPPHY_IQ_NUM_SMPLS_ADDR
1999. B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR
2000. B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR
2001. B43_LPPHY_IQ_THRES_H
2002. B43_LPPHY_IQ_THRES_HH
2003. B43_LPPHY_IQ_THRES_L
2004. B43_LPPHY_IQ_THRES_LL
2005. B43_LPPHY_JSSI
2006. B43_LPPHY_JSSICTL
2007. B43_LPPHY_LG2GAINTBLLNA28
2008. B43_LPPHY_LG2GAINTBLLNA44
2009. B43_LPPHY_LG2GAINTBLLNA62
2010. B43_LPPHY_LG2GAINTBLLNA8
2011. B43_LPPHY_LG2INITGAIN
2012. B43_LPPHY_LNAGAINTWOBIT10
2013. B43_LPPHY_LNAGAINTWOBIT32
2014. B43_LPPHY_LNAGAINTWOBIT54
2015. B43_LPPHY_LNAGAINTWOBIT76
2016. B43_LPPHY_LNA_GAIN_RANGE
2017. B43_LPPHY_LOG2_R16QAM_ADDR
2018. B43_LPPHY_LOG2_R64QAM_ADDR
2019. B43_LPPHY_LOG2_RBPSK_ADDR
2020. B43_LPPHY_LOG2_RQPSK_ADDR
2021. B43_LPPHY_LOOP_NUM_ADDR
2022. B43_LPPHY_LOWGAINDB
2023. B43_LPPHY_LO_IQ_MAG_ACC
2024. B43_LPPHY_LO_LEAKAGE
2025. B43_LPPHY_LO_RSSIACC
2026. B43_LPPHY_LP_PHY_CTL
2027. B43_LPPHY_LP_RF_SIGNAL_LUT
2028. B43_LPPHY_LTRN_CTL
2029. B43_LPPHY_MACINT_DBG_REGISTER
2030. B43_LPPHY_MAXNUMSTEPS
2031. B43_LPPHY_MAX_SMPL_COARSE_FINE_ADDR
2032. B43_LPPHY_MAX_SMPL_COARSE_STR0CTR_ADDR
2033. B43_LPPHY_MINPWR_LEVEL
2034. B43_LPPHY_MRCNOISEREDUCTION
2035. B43_LPPHY_MUFACTORADDR
2036. B43_LPPHY_NRSSI_STAT_ADDR
2037. B43_LPPHY_NUM_PASS_THROUGH_ADDR
2038. B43_LPPHY_NUM_ROTOR_ADDR
2039. B43_LPPHY_OFDMPWR_THRESH0
2040. B43_LPPHY_OFDMPWR_THRESH1
2041. B43_LPPHY_OFDMPWR_THRESH2
2042. B43_LPPHY_OFDMSYNCTHRESH0
2043. B43_LPPHY_OFDMSYNCTHRESH1
2044. B43_LPPHY_OFDMSYNCTIMER_CTL
2045. B43_LPPHY_OFDM_SYNC_CTL
2046. B43_LPPHY_OFDM_TX_PHY_CRS_DELAY_VAL
2047. B43_LPPHY_OFFSET_16QAM_ADDR
2048. B43_LPPHY_OFFSET_64QAM_ADDR
2049. B43_LPPHY_OFFSET_BPSK_ADDR
2050. B43_LPPHY_OFFSET_QPSK_ADDR
2051. B43_LPPHY_OPTIONALMODES
2052. B43_LPPHY_OPTIONALMODES2
2053. B43_LPPHY_PACKET_RX_ACTIVE_TO
2054. B43_LPPHY_PA_RAMP_TX_TIME_IN
2055. B43_LPPHY_PA_RAMP_TX_TO
2056. B43_LPPHY_PEAKENERGY
2057. B43_LPPHY_PEAKENERGYH
2058. B43_LPPHY_PEAKENERGYL
2059. B43_LPPHY_PHASE_SHIFT_CTL
2060. B43_LPPHY_PHY_CRS_ENABLE_ADDR
2061. B43_LPPHY_PHY_CRS_OFFSET_TIMER_VAL
2062. B43_LPPHY_PKTGAINVAL_ADDR
2063. B43_LPPHY_PKT_FSM_RESET_LEN_VAL
2064. B43_LPPHY_PLCP_TMT_STR0_CTR_MIN
2065. B43_LPPHY_PLL_COEFF_S
2066. B43_LPPHY_PLL_OUT
2067. B43_LPPHY_PPROCCHDELAY
2068. B43_LPPHY_PPROCONOFF
2069. B43_LPPHY_PR3931
2070. B43_LPPHY_PREAMBLECONFIRMTO
2071. B43_LPPHY_PREAMBLEINTO
2072. B43_LPPHY_PSEUDOSHORTTO
2073. B43_LPPHY_PS_CTL_OVERRIDE_VAL0
2074. B43_LPPHY_PS_CTL_OVERRIDE_VAL1
2075. B43_LPPHY_PS_CTL_OVERRIDE_VAL2
2076. B43_LPPHY_PWDNDACDELAY
2077. B43_LPPHY_PWR_THRESH0
2078. B43_LPPHY_PWR_THRESH1
2079. B43_LPPHY_RADAR_BLANK_INT
2080. B43_LPPHY_RADAR_DETECT_EN
2081. B43_LPPHY_RADAR_DETECT_FM_CTL
2082. B43_LPPHY_RADAR_FIFO_STAT
2083. B43_LPPHY_RADAR_GAIN_TO
2084. B43_LPPHY_RADAR_MIN_FM_INT
2085. B43_LPPHY_RADAR_PULSE_TO
2086. B43_LPPHY_RADAR_RD_DATA_REG
2087. B43_LPPHY_RADAR_THRESH
2088. B43_LPPHY_READSYM2RESET_CTL
2089. B43_LPPHY_REDUCED_DETECTOR_DELAY
2090. B43_LPPHY_REG_CRS_ENABLE
2091. B43_LPPHY_RESET_CTL
2092. B43_LPPHY_RESET_LEN_OFDM_RX_ADDR
2093. B43_LPPHY_RESET_LEN_OFDM_TX_ADDR
2094. B43_LPPHY_RF_OVERRIDE_0
2095. B43_LPPHY_RF_OVERRIDE_2
2096. B43_LPPHY_RF_OVERRIDE_2_VAL
2097. B43_LPPHY_RF_OVERRIDE_VAL_0
2098. B43_LPPHY_RF_PWR_OVERRIDE
2099. B43_LPPHY_RF_SYNTH_DC_TIMER
2100. B43_LPPHY_ROTORPHASE_ADDR
2101. B43_LPPHY_RSSIADCDELAY_CTL_ADDR
2102. B43_LPPHY_RSSISELLOOKUP1
2103. B43_LPPHY_RSSI_THRES
2104. B43_LPPHY_RXDBG
2105. B43_LPPHY_RX_COMP_COEFF_S
2106. B43_LPPHY_RX_DELAYCOMP
2107. B43_LPPHY_RX_FILTER_TIME_IN
2108. B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL
2109. B43_LPPHY_RX_RADIO_CTL
2110. B43_LPPHY_RX_RADIO_CTL_FILTER_STATE
2111. B43_LPPHY_RX_STAT0
2112. B43_LPPHY_RX_STAT1
2113. B43_LPPHY_SCRAMSTATE_ADDR
2114. B43_LPPHY_SFDCTL
2115. B43_LPPHY_SFDDETECTBLOCKTIME
2116. B43_LPPHY_SFDTO
2117. B43_LPPHY_SMPL_COLLECT_WAIT_ADDR
2118. B43_LPPHY_SMPL_PLAY_BUFFER_CTL
2119. B43_LPPHY_SMPL_PLAY_COUNT
2120. B43_LPPHY_STATE_TRANSITION_ADDR
2121. B43_LPPHY_STR_COLLMAX_SMPL_ADDR
2122. B43_LPPHY_SYNCCTL
2123. B43_LPPHY_SYNCDIVERSITYCTL
2124. B43_LPPHY_SYNCFREQ
2125. B43_LPPHY_SYNCPEAKCNT
2126. B43_LPPHY_TABLEDATAHI
2127. B43_LPPHY_TABLEDATALO
2128. B43_LPPHY_TABLE_ADDR
2129. B43_LPPHY_TEMPSENSESTAT_ADDR
2130. B43_LPPHY_TEMPSENSE_CTL_ADDR
2131. B43_LPPHY_TRCORR
2132. B43_LPPHY_TRN_OFFSET_ADDR
2133. B43_LPPHY_TR_LOOKUP_1
2134. B43_LPPHY_TR_LOOKUP_2
2135. B43_LPPHY_TR_LOOKUP_3
2136. B43_LPPHY_TR_LOOKUP_4
2137. B43_LPPHY_TR_LOOKUP_5
2138. B43_LPPHY_TR_LOOKUP_6
2139. B43_LPPHY_TR_LOOKUP_7
2140. B43_LPPHY_TR_LOOKUP_8
2141. B43_LPPHY_TR_LOSS
2142. B43_LPPHY_TSSI
2143. B43_LPPHY_TSSISTAT_ADDR
2144. B43_LPPHY_TSSI_CTL
2145. B43_LPPHY_TXHOLDOFFADDR
2146. B43_LPPHY_TXPCTL_HW
2147. B43_LPPHY_TXPCTL_OFF
2148. B43_LPPHY_TXPCTL_SW
2149. B43_LPPHY_TXPCTL_UNKNOWN
2150. B43_LPPHY_TX_DCOFFSET1
2151. B43_LPPHY_TX_DCOFFSET2
2152. B43_LPPHY_TX_ERROR
2153. B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL
2154. B43_LPPHY_TX_PWR_CTL_BASEINDEX
2155. B43_LPPHY_TX_PWR_CTL_CMD
2156. B43_LPPHY_TX_PWR_CTL_CMD_MODE
2157. B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW
2158. B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF
2159. B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW
2160. B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT
2161. B43_LPPHY_TX_PWR_CTL_IDLETSSI
2162. B43_LPPHY_TX_PWR_CTL_NNUM
2163. B43_LPPHY_TX_PWR_CTL_PWR_INDEX
2164. B43_LPPHY_TX_PWR_CTL_STAT
2165. B43_LPPHY_TX_PWR_CTL_TARGETPWR
2166. B43_LPPHY_VERSION
2167. B43_LPPHY_VERYLOWGAINDB
2168. B43_LPPHY_VITERBI_OFFSET_ADDR
2169. B43_LPPHY_WAITFORPHYSELTO
2170. B43_LPPHY_WORKAROUND
2171. B43_LPPHY_WRSSISTAT_ADDR
2172. B43_LPTAB16
2173. B43_LPTAB32
2174. B43_LPTAB8
2175. B43_LPTAB_16BIT
2176. B43_LPTAB_32BIT
2177. B43_LPTAB_8BIT
2178. B43_LPTAB_TXPWR_R0_1
2179. B43_LPTAB_TXPWR_R2PLUS
2180. B43_LPTAB_TYPEMASK
2181. B43_LP_NORTH
2182. B43_LP_RADIO
2183. B43_LP_SOUTH
2184. B43_MACCMD_BEACON0_VALID
2185. B43_MACCMD_BEACON1_VALID
2186. B43_MACCMD_BGNOISE
2187. B43_MACCMD_CCA
2188. B43_MACCMD_DFQ_VALID
2189. B43_MACCTL_AP
2190. B43_MACCTL_AWAKE
2191. B43_MACCTL_BE
2192. B43_MACCTL_BEACPROMISC
2193. B43_MACCTL_CLOSEDNET
2194. B43_MACCTL_DISCPMQ
2195. B43_MACCTL_DISCTXSTAT
2196. B43_MACCTL_ENABLED
2197. B43_MACCTL_GMODE
2198. B43_MACCTL_GPOUTSMSK
2199. B43_MACCTL_HWPS
2200. B43_MACCTL_IHR_ENABLED
2201. B43_MACCTL_INFRA
2202. B43_MACCTL_KEEP_BAD
2203. B43_MACCTL_KEEP_BADPLCP
2204. B43_MACCTL_KEEP_CTL
2205. B43_MACCTL_PHY_LOCK
2206. B43_MACCTL_PROMISC
2207. B43_MACCTL_PSM_DBG
2208. B43_MACCTL_PSM_JMP0
2209. B43_MACCTL_PSM_RUN
2210. B43_MACCTL_RADIOLOCK
2211. B43_MACCTL_SHM_ENABLED
2212. B43_MACCTL_SHM_UPPER
2213. B43_MACCTL_TBTTHOLD
2214. B43_MACFILTER_BSSID
2215. B43_MACFILTER_SELF
2216. B43_MAIN_H_
2217. B43_MARKER_ID_REG
2218. B43_MARKER_LINE_REG
2219. B43_MAX_MMIO_ACCESS
2220. B43_MAX_NR_LEDS
2221. B43_MAX_SHM_ADDR
2222. B43_MAX_SHM_ROUTING
2223. B43_MAX_WRITES_IN_ROW
2224. B43_MMIO_ANTENNA
2225. B43_MMIO_BTCOEX_CTL
2226. B43_MMIO_BTCOEX_STAT
2227. B43_MMIO_BTCOEX_TXCTL
2228. B43_MMIO_CHANNEL
2229. B43_MMIO_CHANNEL_EXT
2230. B43_MMIO_DMA0_IRQ_MASK
2231. B43_MMIO_DMA0_REASON
2232. B43_MMIO_DMA1_IRQ_MASK
2233. B43_MMIO_DMA1_REASON
2234. B43_MMIO_DMA2_IRQ_MASK
2235. B43_MMIO_DMA2_REASON
2236. B43_MMIO_DMA32_BASE0
2237. B43_MMIO_DMA32_BASE1
2238. B43_MMIO_DMA32_BASE2
2239. B43_MMIO_DMA32_BASE3
2240. B43_MMIO_DMA32_BASE4
2241. B43_MMIO_DMA32_BASE5
2242. B43_MMIO_DMA3_IRQ_MASK
2243. B43_MMIO_DMA3_REASON
2244. B43_MMIO_DMA4_IRQ_MASK
2245. B43_MMIO_DMA4_REASON
2246. B43_MMIO_DMA5_IRQ_MASK
2247. B43_MMIO_DMA5_REASON
2248. B43_MMIO_DMA64_BASE0
2249. B43_MMIO_DMA64_BASE1
2250. B43_MMIO_DMA64_BASE2
2251. B43_MMIO_DMA64_BASE3
2252. B43_MMIO_DMA64_BASE4
2253. B43_MMIO_DMA64_BASE5
2254. B43_MMIO_GEN_IRQ_MASK
2255. B43_MMIO_GEN_IRQ_REASON
2256. B43_MMIO_GPIO_CONTROL
2257. B43_MMIO_GPIO_MASK
2258. B43_MMIO_IFSCTL
2259. B43_MMIO_IFSCTL_USE_EDCF
2260. B43_MMIO_IFSMEDBUSYCTL
2261. B43_MMIO_IFSSLOT
2262. B43_MMIO_IFSSTAT
2263. B43_MMIO_IFTXDUR
2264. B43_MMIO_MACCMD
2265. B43_MMIO_MACCTL
2266. B43_MMIO_MACFILTER_CONTROL
2267. B43_MMIO_MACFILTER_DATA
2268. B43_MMIO_MAC_HW_CAP
2269. B43_MMIO_PHY0
2270. B43_MMIO_PHY_CONTROL
2271. B43_MMIO_PHY_DATA
2272. B43_MMIO_PHY_RADIO
2273. B43_MMIO_PHY_VER
2274. B43_MMIO_PIO11_BASE0
2275. B43_MMIO_PIO11_BASE1
2276. B43_MMIO_PIO11_BASE2
2277. B43_MMIO_PIO11_BASE3
2278. B43_MMIO_PIO11_BASE4
2279. B43_MMIO_PIO11_BASE5
2280. B43_MMIO_PIO_BASE0
2281. B43_MMIO_PIO_BASE1
2282. B43_MMIO_PIO_BASE2
2283. B43_MMIO_PIO_BASE3
2284. B43_MMIO_PIO_BASE4
2285. B43_MMIO_PIO_BASE5
2286. B43_MMIO_PIO_BASE6
2287. B43_MMIO_PIO_BASE7
2288. B43_MMIO_POWERUP_DELAY
2289. B43_MMIO_PSM_PHY_HDR
2290. B43_MMIO_PS_STATUS
2291. B43_MMIO_RADIO24_CONTROL
2292. B43_MMIO_RADIO24_DATA
2293. B43_MMIO_RADIO_CONTROL
2294. B43_MMIO_RADIO_DATA_HIGH
2295. B43_MMIO_RADIO_DATA_LOW
2296. B43_MMIO_RADIO_HWENABLED_HI
2297. B43_MMIO_RADIO_HWENABLED_HI_MASK
2298. B43_MMIO_RADIO_HWENABLED_LO
2299. B43_MMIO_RADIO_HWENABLED_LO_MASK
2300. B43_MMIO_RAM_CONTROL
2301. B43_MMIO_RAM_DATA
2302. B43_MMIO_RCMTA_COUNT
2303. B43_MMIO_REV3PLUS_TSF_HIGH
2304. B43_MMIO_REV3PLUS_TSF_LOW
2305. B43_MMIO_RNG
2306. B43_MMIO_SHM_CONTROL
2307. B43_MMIO_SHM_DATA
2308. B43_MMIO_SHM_DATA_UNALIGNED
2309. B43_MMIO_SMPL_CLCT_CURPTR
2310. B43_MMIO_SMPL_CLCT_STPPTR
2311. B43_MMIO_SMPL_CLCT_STRPTR
2312. B43_MMIO_TSF_0
2313. B43_MMIO_TSF_1
2314. B43_MMIO_TSF_2
2315. B43_MMIO_TSF_3
2316. B43_MMIO_TSF_CFP_MAXDUR
2317. B43_MMIO_TSF_CFP_PRETBTT
2318. B43_MMIO_TSF_CFP_REP
2319. B43_MMIO_TSF_CFP_START
2320. B43_MMIO_TSF_CFP_START_HIGH
2321. B43_MMIO_TSF_CFP_START_LOW
2322. B43_MMIO_TSF_CLK_FRAC_HIGH
2323. B43_MMIO_TSF_CLK_FRAC_LOW
2324. B43_MMIO_TXE0_AUX
2325. B43_MMIO_TXE0_CTL
2326. B43_MMIO_TXE0_MMPLCP0
2327. B43_MMIO_TXE0_MMPLCP1
2328. B43_MMIO_TXE0_PHYCTL
2329. B43_MMIO_TXE0_PHYCTL1
2330. B43_MMIO_TXE0_STATUS
2331. B43_MMIO_TXE0_TIME_OUT
2332. B43_MMIO_TXE0_TS_LOC
2333. B43_MMIO_TXE0_WM_0
2334. B43_MMIO_TXE0_WM_1
2335. B43_MMIO_WEPCTL
2336. B43_MMIO_XMITSTAT_0
2337. B43_MMIO_XMITSTAT_1
2338. B43_MMIO_XMTFIFOCMD
2339. B43_MMIO_XMTFIFODEF
2340. B43_MMIO_XMTFIFODEF1
2341. B43_MMIO_XMTFIFOFLUSH
2342. B43_MMIO_XMTFIFOPRIRDY
2343. B43_MMIO_XMTFIFORDY
2344. B43_MMIO_XMTFIFORQPRI
2345. B43_MMIO_XMTFIFOTHRESH
2346. B43_MMIO_XMTFIFO_BYTE_CNT
2347. B43_MMIO_XMTFIFO_FRAME_CNT
2348. B43_MMIO_XMTFIFO_HEAD
2349. B43_MMIO_XMTFIFO_RD_PTR
2350. B43_MMIO_XMTFIFO_WR_PTR
2351. B43_MMIO_XMTSEL
2352. B43_MMIO_XMTTPLATEDATAHI
2353. B43_MMIO_XMTTPLATEDATALO
2354. B43_MMIO_XMTTPLATEPTR
2355. B43_MMIO_XMTTPLATETXPTR
2356. B43_MMIO_XMTTXCNT
2357. B43_MMIO_XMTTXSHMADDR
2358. B43_NPHY_4WI_ADDR
2359. B43_NPHY_4WI_DATAHI
2360. B43_NPHY_4WI_DATALO
2361. B43_NPHY_A0RADAR_FIFOCTL
2362. B43_NPHY_A0RADAR_FIFODAT
2363. B43_NPHY_A1RADAR_FIFOCTL
2364. B43_NPHY_A1RADAR_FIFODAT
2365. B43_NPHY_AFECTL_C1
2366. B43_NPHY_AFECTL_C2
2367. B43_NPHY_AFECTL_C3
2368. B43_NPHY_AFECTL_C4
2369. B43_NPHY_AFECTL_DACGAIN1
2370. B43_NPHY_AFECTL_DACGAIN2
2371. B43_NPHY_AFECTL_DACGAIN3
2372. B43_NPHY_AFECTL_DACGAIN4
2373. B43_NPHY_AFECTL_OVER
2374. B43_NPHY_AFECTL_OVER1
2375. B43_NPHY_AFESEQINITDACGAIN
2376. B43_NPHY_AFESEQ_RX2TX_PUD
2377. B43_NPHY_AFESEQ_RX2TX_PUD_10M
2378. B43_NPHY_AFESEQ_RX2TX_PUD_20M
2379. B43_NPHY_AFESEQ_RX2TX_PUD_40M
2380. B43_NPHY_AFESEQ_TX2RX_PUD
2381. B43_NPHY_AFESEQ_TX2RX_PUD_10M
2382. B43_NPHY_AFESEQ_TX2RX_PUD_20M
2383. B43_NPHY_AFESEQ_TX2RX_PUD_40M
2384. B43_NPHY_ANTENNACCKDIVDWELLTIME
2385. B43_NPHY_ANTENNADIVBACKOFFGAIN
2386. B43_NPHY_ANTENNADIVDWELLTIME
2387. B43_NPHY_ANTENNADIVMINGAIN
2388. B43_NPHY_BANDCTL
2389. B43_NPHY_BANDCTL_5GHZ
2390. B43_NPHY_BBCFG
2391. B43_NPHY_BBCFG_RSTCCA
2392. B43_NPHY_BBCFG_RSTRX
2393. B43_NPHY_BIST_STAT0
2394. B43_NPHY_BIST_STAT1
2395. B43_NPHY_BIST_STAT2
2396. B43_NPHY_BIST_STAT3
2397. B43_NPHY_BIST_STAT4
2398. B43_NPHY_BPHYCRSMINPOWER0
2399. B43_NPHY_BPHYCRSMINPOWER1
2400. B43_NPHY_BPHYCRSMINPOWER2
2401. B43_NPHY_BPHYFILTBYPASS
2402. B43_NPHY_BPHYFILTDEN0COEF
2403. B43_NPHY_BPHYFILTDEN1COEF
2404. B43_NPHY_BPHYFILTDEN2COEF
2405. B43_NPHY_BPHYFILTNUM01COEF2
2406. B43_NPHY_BPHYFILTNUM0COEF
2407. B43_NPHY_BPHYFILTNUM1COEF
2408. B43_NPHY_BPHYFILTNUM2COEF
2409. B43_NPHY_BPHYTESTCONTROL
2410. B43_NPHY_BPHY_CTL1
2411. B43_NPHY_BPHY_CTL2
2412. B43_NPHY_BPHY_CTL2_LUT
2413. B43_NPHY_BPHY_CTL2_LUT_SHIFT
2414. B43_NPHY_BPHY_CTL2_MACDEL
2415. B43_NPHY_BPHY_CTL2_MACDEL_SHIFT
2416. B43_NPHY_BPHY_CTL3
2417. B43_NPHY_BPHY_CTL3_FSC
2418. B43_NPHY_BPHY_CTL3_FSC_SHIFT
2419. B43_NPHY_BPHY_CTL3_SCALE
2420. B43_NPHY_BPHY_CTL3_SCALE_SHIFT
2421. B43_NPHY_BPHY_CTL4
2422. B43_NPHY_BPHY_CTL5
2423. B43_NPHY_BRDSEL_NORMVARHYSTTH
2424. B43_NPHY_BW1A
2425. B43_NPHY_BW2
2426. B43_NPHY_BW3
2427. B43_NPHY_BW4
2428. B43_NPHY_BW5
2429. B43_NPHY_BW6
2430. B43_NPHY_C1_ADCCLIP
2431. B43_NPHY_C1_BCLIPBKOFF
2432. B43_NPHY_C1_BPHY_RXIQCA0
2433. B43_NPHY_C1_BPHY_RXIQCB0
2434. B43_NPHY_C1_CCK_BCLIPBKOFF
2435. B43_NPHY_C1_CCK_CGAINI
2436. B43_NPHY_C1_CCK_CGAINI_CLIPGBKOFF
2437. B43_NPHY_C1_CCK_CGAINI_GAINBKOFF
2438. B43_NPHY_C1_CCK_DESPWR
2439. B43_NPHY_C1_CCK_MAXGAIN
2440. B43_NPHY_C1_CCK_MAXGAIN_SHIFT
2441. B43_NPHY_C1_CCK_MINGAIN
2442. B43_NPHY_C1_CCK_MINGAIN_SHIFT
2443. B43_NPHY_C1_CCK_MINMAX_GAIN
2444. B43_NPHY_C1_CGAINI
2445. B43_NPHY_C1_CGAINI_CL2DETECT
2446. B43_NPHY_C1_CGAINI_CLIPGBKOFF
2447. B43_NPHY_C1_CGAINI_CLIPGBKOFF_SHIFT
2448. B43_NPHY_C1_CGAINI_GAINBKOFF
2449. B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT
2450. B43_NPHY_C1_CGAINI_GAINSTEP
2451. B43_NPHY_C1_CGAINI_GAINSTEP_SHIFT
2452. B43_NPHY_C1_CLIP1THRES
2453. B43_NPHY_C1_CLIP1_HIGAIN
2454. B43_NPHY_C1_CLIP1_LOGAIN
2455. B43_NPHY_C1_CLIP1_MEDGAIN
2456. B43_NPHY_C1_CLIP2THRES
2457. B43_NPHY_C1_CLIP2_GAIN
2458. B43_NPHY_C1_CLIPWBTHRES
2459. B43_NPHY_C1_CLIPWBTHRES_CLIP1
2460. B43_NPHY_C1_CLIPWBTHRES_CLIP1_SHIFT
2461. B43_NPHY_C1_CLIPWBTHRES_CLIP2
2462. B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT
2463. B43_NPHY_C1_DESPWR
2464. B43_NPHY_C1_EDTHRES
2465. B43_NPHY_C1_FILTERGAIN
2466. B43_NPHY_C1_INITGAIN
2467. B43_NPHY_C1_INITGAIN_EXTLNA
2468. B43_NPHY_C1_INITGAIN_HPVGA1
2469. B43_NPHY_C1_INITGAIN_HPVGA1_SHIFT
2470. B43_NPHY_C1_INITGAIN_HPVGA2
2471. B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT
2472. B43_NPHY_C1_INITGAIN_LNA
2473. B43_NPHY_C1_INITGAIN_LNAIDX_SHIFT
2474. B43_NPHY_C1_INITGAIN_TRRX
2475. B43_NPHY_C1_INITGAIN_TRTX
2476. B43_NPHY_C1_LPF_QHPF_BW
2477. B43_NPHY_C1_MAXGAIN
2478. B43_NPHY_C1_MAXGAIN_SHIFT
2479. B43_NPHY_C1_MINGAIN
2480. B43_NPHY_C1_MINGAIN_SHIFT
2481. B43_NPHY_C1_MINMAX_GAIN
2482. B43_NPHY_C1_NBCLIPTHRES
2483. B43_NPHY_C1_RXIQ_COMPA0
2484. B43_NPHY_C1_RXIQ_COMPB0
2485. B43_NPHY_C1_SMSIGTHRES
2486. B43_NPHY_C1_TXBBMULT
2487. B43_NPHY_C1_TXCTL
2488. B43_NPHY_C1_TXIQ_COMP_OFF
2489. B43_NPHY_C1_TXPCTL_STAT
2490. B43_NPHY_C1_W1THRES
2491. B43_NPHY_C2_ADCCLIP
2492. B43_NPHY_C2_BCLIPBKOFF
2493. B43_NPHY_C2_BPHY_RXIQCA1
2494. B43_NPHY_C2_BPHY_RXIQCB1
2495. B43_NPHY_C2_CCK_BCLIPBKOFF
2496. B43_NPHY_C2_CCK_CGAINI
2497. B43_NPHY_C2_CCK_CGAINI_CLIPGBKOFF
2498. B43_NPHY_C2_CCK_CGAINI_GAINBKOFF
2499. B43_NPHY_C2_CCK_DESPWR
2500. B43_NPHY_C2_CCK_MAXGAIN
2501. B43_NPHY_C2_CCK_MAXGAIN_SHIFT
2502. B43_NPHY_C2_CCK_MINGAIN
2503. B43_NPHY_C2_CCK_MINGAIN_SHIFT
2504. B43_NPHY_C2_CCK_MINMAX_GAIN
2505. B43_NPHY_C2_CGAINI
2506. B43_NPHY_C2_CGAINI_CL2DETECT
2507. B43_NPHY_C2_CGAINI_CLIPGBKOFF
2508. B43_NPHY_C2_CGAINI_CLIPGBKOFF_SHIFT
2509. B43_NPHY_C2_CGAINI_GAINBKOFF
2510. B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT
2511. B43_NPHY_C2_CGAINI_GAINSTEP
2512. B43_NPHY_C2_CGAINI_GAINSTEP_SHIFT
2513. B43_NPHY_C2_CLIP1THRES
2514. B43_NPHY_C2_CLIP1_HIGAIN
2515. B43_NPHY_C2_CLIP1_LOGAIN
2516. B43_NPHY_C2_CLIP1_MEDGAIN
2517. B43_NPHY_C2_CLIP2THRES
2518. B43_NPHY_C2_CLIP2_GAIN
2519. B43_NPHY_C2_CLIPWBTHRES
2520. B43_NPHY_C2_CLIPWBTHRES_CLIP1
2521. B43_NPHY_C2_CLIPWBTHRES_CLIP1_SHIFT
2522. B43_NPHY_C2_CLIPWBTHRES_CLIP2
2523. B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT
2524. B43_NPHY_C2_DESPWR
2525. B43_NPHY_C2_EDTHRES
2526. B43_NPHY_C2_FILTERGAIN
2527. B43_NPHY_C2_INITGAIN
2528. B43_NPHY_C2_INITGAIN_EXTLNA
2529. B43_NPHY_C2_INITGAIN_HPVGA1
2530. B43_NPHY_C2_INITGAIN_HPVGA1_SHIFT
2531. B43_NPHY_C2_INITGAIN_HPVGA2
2532. B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT
2533. B43_NPHY_C2_INITGAIN_LNA
2534. B43_NPHY_C2_INITGAIN_LNAIDX_SHIFT
2535. B43_NPHY_C2_INITGAIN_TRRX
2536. B43_NPHY_C2_INITGAIN_TRTX
2537. B43_NPHY_C2_LPF_QHPF_BW
2538. B43_NPHY_C2_MAXGAIN
2539. B43_NPHY_C2_MAXGAIN_SHIFT
2540. B43_NPHY_C2_MINGAIN
2541. B43_NPHY_C2_MINGAIN_SHIFT
2542. B43_NPHY_C2_MINMAX_GAIN
2543. B43_NPHY_C2_NBCLIPTHRES
2544. B43_NPHY_C2_RXIQ_COMPA1
2545. B43_NPHY_C2_RXIQ_COMPB1
2546. B43_NPHY_C2_SMSIGTHRES
2547. B43_NPHY_C2_TXBBMULT
2548. B43_NPHY_C2_TXCTL
2549. B43_NPHY_C2_TXIQ_COMP_OFF
2550. B43_NPHY_C2_TXPCTL_STAT
2551. B43_NPHY_C2_W1THRES
2552. B43_NPHY_CARRSRC_TLEN
2553. B43_NPHY_CCKPAYDECODETIMEOUTLEN
2554. B43_NPHY_CCK_SHIFTB_REF
2555. B43_NPHY_CHANEST_CDDSH
2556. B43_NPHY_CHANNEL
2557. B43_NPHY_CHANUPSYM01
2558. B43_NPHY_CHANUPSYM2
2559. B43_NPHY_CHAN_ESTHANG
2560. B43_NPHY_CLASSCTL
2561. B43_NPHY_CLASSCTL_CCKEN
2562. B43_NPHY_CLASSCTL_OFDMEN
2563. B43_NPHY_CLASSCTL_WAITEDEN
2564. B43_NPHY_CLIP1CARR_DLEN
2565. B43_NPHY_CLIP1GAIN_SLEN
2566. B43_NPHY_CLIP1_NBDWELL_LEN
2567. B43_NPHY_CLIP2CARR_DLEN
2568. B43_NPHY_CLIP2GAIN_SLEN
2569. B43_NPHY_CLIP2_NBDWELL_LEN
2570. B43_NPHY_COALEN0
2571. B43_NPHY_COALEN1
2572. B43_NPHY_CORECONFIG
2573. B43_NPHY_CRCPOLY
2574. B43_NPHY_CRCPOLY_ORDER
2575. B43_NPHY_CRSACIDETECTTHRESH
2576. B43_NPHY_CRSACIDETECTTHRESHL
2577. B43_NPHY_CRSACIDETECTTHRESHU
2578. B43_NPHY_CRSCHECK1
2579. B43_NPHY_CRSCHECK2
2580. B43_NPHY_CRSCHECK3
2581. B43_NPHY_CRSCTL
2582. B43_NPHY_CRSCTL_L
2583. B43_NPHY_CRSCTL_U
2584. B43_NPHY_CRSHIGHLOWPOWTHRESHOLD
2585. B43_NPHY_CRSHIGHLOWPOWTHRESHOLDL
2586. B43_NPHY_CRSHIGHLOWPOWTHRESHOLDU
2587. B43_NPHY_CRSHIGHPOWTHRESHOLD1
2588. B43_NPHY_CRSHIGHPOWTHRESHOLD1L
2589. B43_NPHY_CRSHIGHPOWTHRESHOLD1U
2590. B43_NPHY_CRSHIGHPOWTHRESHOLD2
2591. B43_NPHY_CRSHIGHPOWTHRESHOLD2L
2592. B43_NPHY_CRSHIGHPOWTHRESHOLD2U
2593. B43_NPHY_CRSIT_COCNT_HI
2594. B43_NPHY_CRSIT_COCNT_LO
2595. B43_NPHY_CRSIT_MTCNT_HI
2596. B43_NPHY_CRSIT_MTCNT_LO
2597. B43_NPHY_CRSMINPOWER0
2598. B43_NPHY_CRSMINPOWER1
2599. B43_NPHY_CRSMINPOWER2
2600. B43_NPHY_CRSMINPOWERL0
2601. B43_NPHY_CRSMINPOWERL1
2602. B43_NPHY_CRSMINPOWERL2
2603. B43_NPHY_CRSMINPOWERU0
2604. B43_NPHY_CRSMINPOWERU1
2605. B43_NPHY_CRSMINPOWERU2
2606. B43_NPHY_CRSTHRES_1L
2607. B43_NPHY_CRSTHRES_1U
2608. B43_NPHY_CRSTHRES_2L
2609. B43_NPHY_CRSTHRES_2U
2610. B43_NPHY_CRSTHRES_3L
2611. B43_NPHY_CRSTHRES_3U
2612. B43_NPHY_CRS_CHECK
2613. B43_NPHY_CRS_THRES1
2614. B43_NPHY_CRS_THRES2
2615. B43_NPHY_CRS_THRES3
2616. B43_NPHY_CSEN_20IN40_DLEN
2617. B43_NPHY_DCFADDR
2618. B43_NPHY_DSSSCCK_CRSEXTL
2619. B43_NPHY_DSSSCCK_GAINSL
2620. B43_NPHY_DUP40_BL
2621. B43_NPHY_DUP40_GFBL
2622. B43_NPHY_DUP40_TGNSYNC_CYCD
2623. B43_NPHY_DUPSCALE
2624. B43_NPHY_EDCRS_ASSTHRES0
2625. B43_NPHY_EDCRS_ASSTHRES1
2626. B43_NPHY_EDCRS_DEASSTHRES0
2627. B43_NPHY_EDCRS_DEASSTHRES1
2628. B43_NPHY_EDROP_CSENSE_EXTLEN
2629. B43_NPHY_ED_CRS
2630. B43_NPHY_ED_CRS20LASSERTTHRESH0
2631. B43_NPHY_ED_CRS20LASSERTTHRESH1
2632. B43_NPHY_ED_CRS20LDEASSERTTHRESH0
2633. B43_NPHY_ED_CRS20LDEASSERTTHRESH1
2634. B43_NPHY_ED_CRS20UASSERTTHRESH0
2635. B43_NPHY_ED_CRS20UASSERTTHRESH1
2636. B43_NPHY_ED_CRS20UDEASSERTTHRESH0
2637. B43_NPHY_ED_CRS20UDEASSERTTHRESH1
2638. B43_NPHY_ED_CRS40ASSERTTHRESH0
2639. B43_NPHY_ED_CRS40ASSERTTHRESH1
2640. B43_NPHY_ED_CRS40DEASSERTTHRESH0
2641. B43_NPHY_ED_CRS40DEASSERTTHRESH1
2642. B43_NPHY_ED_CRSEN
2643. B43_NPHY_ENDROP_TLEN
2644. B43_NPHY_ENERGYDROPTIMEOUTLEN2
2645. B43_NPHY_EPS_OVERRIDEI_0
2646. B43_NPHY_EPS_OVERRIDEI_1
2647. B43_NPHY_EPS_OVERRIDEQ_0
2648. B43_NPHY_EPS_OVERRIDEQ_1
2649. B43_NPHY_EPS_TABLE_ADJ0
2650. B43_NPHY_EPS_TABLE_ADJ1
2651. B43_NPHY_ESTPWR1
2652. B43_NPHY_ESTPWR2
2653. B43_NPHY_ESTPWR_PWR
2654. B43_NPHY_ESTPWR_PWR_SHIFT
2655. B43_NPHY_ESTPWR_VALID
2656. B43_NPHY_FINERX2_CGC
2657. B43_NPHY_FINERX2_CGC_DECGC
2658. B43_NPHY_FMDEM_CFG
2659. B43_NPHY_FORCEFRONT0
2660. B43_NPHY_FORCEFRONT1
2661. B43_NPHY_FREQGAIN0
2662. B43_NPHY_FREQGAIN1
2663. B43_NPHY_FREQGAIN2
2664. B43_NPHY_FREQGAIN3
2665. B43_NPHY_FREQGAIN4
2666. B43_NPHY_FREQGAIN5
2667. B43_NPHY_FREQGAIN6
2668. B43_NPHY_FREQGAIN7
2669. B43_NPHY_FREQGAIN_BYPASS
2670. B43_NPHY_GPIO_CLKCTL
2671. B43_NPHY_GPIO_HIOEN
2672. B43_NPHY_GPIO_HIOUT
2673. B43_NPHY_GPIO_LOOEN
2674. B43_NPHY_GPIO_LOOUT
2675. B43_NPHY_GPIO_SEL
2676. B43_NPHY_HPANT_SWTHRES
2677. B43_NPHY_HTAGC_WCNT
2678. B43_NPHY_HTSIGTONES
2679. B43_NPHY_HT_SIGFMOD_11N
2680. B43_NPHY_H_
2681. B43_NPHY_INITCARR_DLEN
2682. B43_NPHY_INITGAIN_SLEN
2683. B43_NPHY_INITSWIZP
2684. B43_NPHY_INITSWIZPATTLEG
2685. B43_NPHY_IQEST_CMD
2686. B43_NPHY_IQEST_CMD_MODE
2687. B43_NPHY_IQEST_CMD_START
2688. B43_NPHY_IQEST_IPACC_HI0
2689. B43_NPHY_IQEST_IPACC_HI1
2690. B43_NPHY_IQEST_IPACC_LO0
2691. B43_NPHY_IQEST_IPACC_LO1
2692. B43_NPHY_IQEST_IQACC_HI0
2693. B43_NPHY_IQEST_IQACC_HI1
2694. B43_NPHY_IQEST_IQACC_LO0
2695. B43_NPHY_IQEST_IQACC_LO1
2696. B43_NPHY_IQEST_QPACC_HI0
2697. B43_NPHY_IQEST_QPACC_HI1
2698. B43_NPHY_IQEST_QPACC_LO0
2699. B43_NPHY_IQEST_QPACC_LO1
2700. B43_NPHY_IQEST_SAMCNT
2701. B43_NPHY_IQEST_WT
2702. B43_NPHY_IQEST_WT_VAL
2703. B43_NPHY_IQEST_WT_VAL_SHIFT
2704. B43_NPHY_IQFLIP
2705. B43_NPHY_IQFLIP_ADC1
2706. B43_NPHY_IQFLIP_ADC2
2707. B43_NPHY_IQLOCAL_CMD
2708. B43_NPHY_IQLOCAL_CMDGCTL
2709. B43_NPHY_IQLOCAL_CMDNNUM
2710. B43_NPHY_IQLOCAL_CMD_EN
2711. B43_NPHY_ITSSI1
2712. B43_NPHY_ITSSI2
2713. B43_NPHY_ITSSI_VAL
2714. B43_NPHY_ITSSI_VAL_SHIFT
2715. B43_NPHY_JMPSTP0
2716. B43_NPHY_JMPSTP1
2717. B43_NPHY_LEGDUP_FTA
2718. B43_NPHY_LEG_SIGFMOD_11N
2719. B43_NPHY_LTRN_OFF
2720. B43_NPHY_LTRN_OFFGAIN
2721. B43_NPHY_LTRN_OFF_20L
2722. B43_NPHY_LTRN_OFF_20U
2723. B43_NPHY_LTRN_OFF_G20L
2724. B43_NPHY_LTRN_OFF_G20U
2725. B43_NPHY_MAXRSSI_DTIME
2726. B43_NPHY_MCSDUP6M
2727. B43_NPHY_MIMOCFG
2728. B43_NPHY_MIMOCFG_AUTO
2729. B43_NPHY_MIMOCFG_GFMIX
2730. B43_NPHY_MIMO_CRSTXEXT
2731. B43_NPHY_MLCTL
2732. B43_NPHY_MLPARM
2733. B43_NPHY_MLUA
2734. B43_NPHY_ML_LOGSS_RAT
2735. B43_NPHY_ML_LOGSS_RATSLOPE
2736. B43_NPHY_ML_LOG_TXEVM0
2737. B43_NPHY_ML_LOG_TXEVM1
2738. B43_NPHY_ML_LOG_TXEVM2
2739. B43_NPHY_ML_LOG_TXEVM3
2740. B43_NPHY_ML_LOG_TXEVM4
2741. B43_NPHY_ML_LOG_TXEVM5
2742. B43_NPHY_ML_LOG_TXEVM6
2743. B43_NPHY_ML_LOG_TXEVM7
2744. B43_NPHY_ML_SCALE_TWEAK
2745. B43_NPHY_NDATAT_DUP40
2746. B43_NPHY_NONPAYDECODETIMEOUTLEN
2747. B43_NPHY_NORMVARHYSTTH
2748. B43_NPHY_NRDATAT_TGNSYNC20SIG
2749. B43_NPHY_NRDATAT_TGNSYNC40SIG
2750. B43_NPHY_NRDATAT_WWISE20SIG
2751. B43_NPHY_NRDATAT_WWISE40SIG
2752. B43_NPHY_NRDTO_TGNSYNC
2753. B43_NPHY_NRDTO_WWISE
2754. B43_NPHY_OFDMPAYDECODETIMEOUTLEN
2755. B43_NPHY_OVER_DGAIN0
2756. B43_NPHY_OVER_DGAIN1
2757. B43_NPHY_OVER_DGAIN_CCKDGECV
2758. B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT
2759. B43_NPHY_OVER_DGAIN_FDGEN
2760. B43_NPHY_OVER_DGAIN_FDGV
2761. B43_NPHY_OVER_DGAIN_FDGV_SHIFT
2762. B43_NPHY_PACKGAIN_SLEN
2763. B43_NPHY_PACPROC_DBG
2764. B43_NPHY_PAPD_CAL_ADDRESS
2765. B43_NPHY_PAPD_CAL_CORRELATE
2766. B43_NPHY_PAPD_CAL_SETTLE
2767. B43_NPHY_PAPD_CAL_SHIFTS0
2768. B43_NPHY_PAPD_CAL_SHIFTS1
2769. B43_NPHY_PAPD_CAL_YREFEPSILON
2770. B43_NPHY_PAPD_EN0
2771. B43_NPHY_PAPD_EN1
2772. B43_NPHY_PHASETR_A0
2773. B43_NPHY_PHASETR_A1
2774. B43_NPHY_PHASETR_A2
2775. B43_NPHY_PHASETR_B0
2776. B43_NPHY_PHASETR_B1
2777. B43_NPHY_PHASETR_B2
2778. B43_NPHY_PHASETR_CHG0
2779. B43_NPHY_PHASETR_CHG1
2780. B43_NPHY_PHASETW_OFF
2781. B43_NPHY_PHYLB_MODE
2782. B43_NPHY_PHYSTAT_ADVRET
2783. B43_NPHY_PHYSTAT_FREQEST
2784. B43_NPHY_PHYSTAT_GAIN0
2785. B43_NPHY_PHYSTAT_GAIN1
2786. B43_NPHY_PILTONE_MIDX1
2787. B43_NPHY_PILTONE_MIDX2
2788. B43_NPHY_PILTONE_MIDX3
2789. B43_NPHY_PIL_CYC1
2790. B43_NPHY_PIL_CYC2
2791. B43_NPHY_PIL_DW0
2792. B43_NPHY_PIL_DW1
2793. B43_NPHY_PIL_DW2
2794. B43_NPHY_PIL_DW_16QAM
2795. B43_NPHY_PIL_DW_16QAM_SHIFT
2796. B43_NPHY_PIL_DW_64QAM
2797. B43_NPHY_PIL_DW_64QAM_SHIFT
2798. B43_NPHY_PIL_DW_BPSK
2799. B43_NPHY_PIL_DW_BPSK_SHIFT
2800. B43_NPHY_PIL_DW_QPSK
2801. B43_NPHY_PIL_DW_QPSK_SHIFT
2802. B43_NPHY_PLOAD_CSENSE_EXTLEN
2803. B43_NPHY_PPROC_RSTLEN
2804. B43_NPHY_PTHROUGH_CNT
2805. B43_NPHY_PWRDET1
2806. B43_NPHY_PWRDET2
2807. B43_NPHY_RADAR_ADC_TO_DBM
2808. B43_NPHY_RADAR_BLNKCTL
2809. B43_NPHY_RADAR_MAL
2810. B43_NPHY_RADAR_SRCCTL
2811. B43_NPHY_RADAR_T2_MIN
2812. B43_NPHY_RADAR_THRES0
2813. B43_NPHY_RADAR_THRES0R
2814. B43_NPHY_RADAR_THRES1
2815. B43_NPHY_RADAR_THRES1R
2816. B43_NPHY_REV3_C1_CLIP2_GAIN_A
2817. B43_NPHY_REV3_C1_CLIP2_GAIN_B
2818. B43_NPHY_REV3_C1_CLIP_HIGAIN_A
2819. B43_NPHY_REV3_C1_CLIP_HIGAIN_B
2820. B43_NPHY_REV3_C1_CLIP_LOGAIN_A
2821. B43_NPHY_REV3_C1_CLIP_LOGAIN_B
2822. B43_NPHY_REV3_C1_CLIP_MEDGAIN_A
2823. B43_NPHY_REV3_C1_CLIP_MEDGAIN_B
2824. B43_NPHY_REV3_C1_INITGAIN_A
2825. B43_NPHY_REV3_C1_INITGAIN_B
2826. B43_NPHY_REV3_C2_CLIP2_GAIN_A
2827. B43_NPHY_REV3_C2_CLIP2_GAIN_B
2828. B43_NPHY_REV3_C2_CLIP_HIGAIN_A
2829. B43_NPHY_REV3_C2_CLIP_HIGAIN_B
2830. B43_NPHY_REV3_C2_CLIP_LOGAIN_A
2831. B43_NPHY_REV3_C2_CLIP_LOGAIN_B
2832. B43_NPHY_REV3_C2_CLIP_MEDGAIN_A
2833. B43_NPHY_REV3_C2_CLIP_MEDGAIN_B
2834. B43_NPHY_REV3_C2_INITGAIN_A
2835. B43_NPHY_REV3_C2_INITGAIN_B
2836. B43_NPHY_REV3_RFCTL_OVER0
2837. B43_NPHY_REV3_RFCTL_OVER1
2838. B43_NPHY_REV7_RF_CTL_MISC_REG3
2839. B43_NPHY_REV7_RF_CTL_MISC_REG4
2840. B43_NPHY_REV7_RF_CTL_MISC_REG5
2841. B43_NPHY_REV7_RF_CTL_MISC_REG6
2842. B43_NPHY_REV7_RF_CTL_OVER3
2843. B43_NPHY_REV7_RF_CTL_OVER4
2844. B43_NPHY_REV7_RF_CTL_OVER5
2845. B43_NPHY_REV7_RF_CTL_OVER6
2846. B43_NPHY_RFCTL_CMD
2847. B43_NPHY_RFCTL_CMD_CHIP0PU
2848. B43_NPHY_RFCTL_CMD_CORESEL
2849. B43_NPHY_RFCTL_CMD_CORESEL_SHIFT
2850. B43_NPHY_RFCTL_CMD_EN
2851. B43_NPHY_RFCTL_CMD_OEPORFORCE
2852. B43_NPHY_RFCTL_CMD_PORFORCE
2853. B43_NPHY_RFCTL_CMD_RXEN
2854. B43_NPHY_RFCTL_CMD_RXTX
2855. B43_NPHY_RFCTL_CMD_SEQENCORE
2856. B43_NPHY_RFCTL_CMD_SEQENCORE_SHIFT
2857. B43_NPHY_RFCTL_CMD_START
2858. B43_NPHY_RFCTL_CMD_TXEN
2859. B43_NPHY_RFCTL_CST0
2860. B43_NPHY_RFCTL_CST1
2861. B43_NPHY_RFCTL_CST2O
2862. B43_NPHY_RFCTL_DBG
2863. B43_NPHY_RFCTL_INTC1
2864. B43_NPHY_RFCTL_INTC2
2865. B43_NPHY_RFCTL_INTC3
2866. B43_NPHY_RFCTL_INTC4
2867. B43_NPHY_RFCTL_LUT_LNAPA1
2868. B43_NPHY_RFCTL_LUT_LNAPA2
2869. B43_NPHY_RFCTL_LUT_LNAPA3
2870. B43_NPHY_RFCTL_LUT_LNAPA4
2871. B43_NPHY_RFCTL_LUT_TRSW_LO1
2872. B43_NPHY_RFCTL_LUT_TRSW_LO2
2873. B43_NPHY_RFCTL_LUT_TRSW_LO3
2874. B43_NPHY_RFCTL_LUT_TRSW_LO4
2875. B43_NPHY_RFCTL_LUT_TRSW_UP1
2876. B43_NPHY_RFCTL_LUT_TRSW_UP2
2877. B43_NPHY_RFCTL_LUT_TRSW_UP3
2878. B43_NPHY_RFCTL_LUT_TRSW_UP4
2879. B43_NPHY_RFCTL_OVER
2880. B43_NPHY_RFCTL_RSSIO1
2881. B43_NPHY_RFCTL_RSSIO1_HIQDISCO
2882. B43_NPHY_RFCTL_RSSIO1_HPFBWHI
2883. B43_NPHY_RFCTL_RSSIO1_LPFBW
2884. B43_NPHY_RFCTL_RSSIO1_PAPD
2885. B43_NPHY_RFCTL_RSSIO1_RSSICTL
2886. B43_NPHY_RFCTL_RSSIO1_RXPD
2887. B43_NPHY_RFCTL_RSSIO1_TXPD
2888. B43_NPHY_RFCTL_RSSIO2
2889. B43_NPHY_RFCTL_RSSIO2_HIQDISCO
2890. B43_NPHY_RFCTL_RSSIO2_HPFBWHI
2891. B43_NPHY_RFCTL_RSSIO2_LPFBW
2892. B43_NPHY_RFCTL_RSSIO2_PAPD
2893. B43_NPHY_RFCTL_RSSIO2_RSSICTL
2894. B43_NPHY_RFCTL_RSSIO2_RXPD
2895. B43_NPHY_RFCTL_RSSIO2_TXPD
2896. B43_NPHY_RFCTL_RSSIO3
2897. B43_NPHY_RFCTL_RSSIO3_HIQDISCO
2898. B43_NPHY_RFCTL_RSSIO3_HPFBWHI
2899. B43_NPHY_RFCTL_RSSIO3_LPFBW
2900. B43_NPHY_RFCTL_RSSIO3_PAPD
2901. B43_NPHY_RFCTL_RSSIO3_RSSICTL
2902. B43_NPHY_RFCTL_RSSIO3_RXPD
2903. B43_NPHY_RFCTL_RSSIO3_TXPD
2904. B43_NPHY_RFCTL_RSSIO4
2905. B43_NPHY_RFCTL_RSSIO4_HIQDISCO
2906. B43_NPHY_RFCTL_RSSIO4_HPFBWHI
2907. B43_NPHY_RFCTL_RSSIO4_LPFBW
2908. B43_NPHY_RFCTL_RSSIO4_PAPD
2909. B43_NPHY_RFCTL_RSSIO4_RSSICTL
2910. B43_NPHY_RFCTL_RSSIO4_RXPD
2911. B43_NPHY_RFCTL_RSSIO4_TXPD
2912. B43_NPHY_RFCTL_RXG1
2913. B43_NPHY_RFCTL_RXG2
2914. B43_NPHY_RFCTL_RXG3
2915. B43_NPHY_RFCTL_RXG4
2916. B43_NPHY_RFCTL_TXG1
2917. B43_NPHY_RFCTL_TXG2
2918. B43_NPHY_RFCTL_TXG3
2919. B43_NPHY_RFCTL_TXG4
2920. B43_NPHY_RFCTRLCORE0GPIO0
2921. B43_NPHY_RFCTRLCORE0GPIO1
2922. B43_NPHY_RFCTRLCORE0GPIO2
2923. B43_NPHY_RFCTRLCORE0GPIO3
2924. B43_NPHY_RFCTRLCORE1GPIO0
2925. B43_NPHY_RFCTRLCORE1GPIO1
2926. B43_NPHY_RFCTRLCORE1GPIO2
2927. B43_NPHY_RFCTRLCORE1GPIO3
2928. B43_NPHY_RFSEQCA
2929. B43_NPHY_RFSEQCA_RXDIS
2930. B43_NPHY_RFSEQCA_RXDIS_SHIFT
2931. B43_NPHY_RFSEQCA_RXEN
2932. B43_NPHY_RFSEQCA_RXEN_SHIFT
2933. B43_NPHY_RFSEQCA_TXDIS
2934. B43_NPHY_RFSEQCA_TXDIS_SHIFT
2935. B43_NPHY_RFSEQCA_TXEN
2936. B43_NPHY_RFSEQCA_TXEN_SHIFT
2937. B43_NPHY_RFSEQMODE
2938. B43_NPHY_RFSEQMODE_CAOVER
2939. B43_NPHY_RFSEQMODE_TROVER
2940. B43_NPHY_RFSEQST
2941. B43_NPHY_RFSEQTR
2942. B43_NPHY_RFSEQTR_RST2RX
2943. B43_NPHY_RFSEQTR_RX2TX
2944. B43_NPHY_RFSEQTR_TX2RX
2945. B43_NPHY_RFSEQTR_UPGH
2946. B43_NPHY_RFSEQTR_UPGL
2947. B43_NPHY_RFSEQTR_UPGU
2948. B43_NPHY_RFSEQ_LPFBW
2949. B43_NPHY_RIFS_SRCTL
2950. B43_NPHY_RSSI1
2951. B43_NPHY_RSSI2
2952. B43_NPHY_RSSIMC_0I_PWRDET
2953. B43_NPHY_RSSIMC_0I_RSSI_X
2954. B43_NPHY_RSSIMC_0I_RSSI_Y
2955. B43_NPHY_RSSIMC_0I_RSSI_Z
2956. B43_NPHY_RSSIMC_0I_TBD
2957. B43_NPHY_RSSIMC_0I_TSSI
2958. B43_NPHY_RSSIMC_0Q_PWRDET
2959. B43_NPHY_RSSIMC_0Q_RSSI_X
2960. B43_NPHY_RSSIMC_0Q_RSSI_Y
2961. B43_NPHY_RSSIMC_0Q_RSSI_Z
2962. B43_NPHY_RSSIMC_0Q_TBD
2963. B43_NPHY_RSSIMC_0Q_TSSI
2964. B43_NPHY_RSSIMC_1I_PWRDET
2965. B43_NPHY_RSSIMC_1I_RSSI_X
2966. B43_NPHY_RSSIMC_1I_RSSI_Y
2967. B43_NPHY_RSSIMC_1I_RSSI_Z
2968. B43_NPHY_RSSIMC_1I_TBD
2969. B43_NPHY_RSSIMC_1I_TSSI
2970. B43_NPHY_RSSIMC_1Q_PWRDET
2971. B43_NPHY_RSSIMC_1Q_RSSI_X
2972. B43_NPHY_RSSIMC_1Q_RSSI_Y
2973. B43_NPHY_RSSIMC_1Q_RSSI_Z
2974. B43_NPHY_RSSIMC_1Q_TBD
2975. B43_NPHY_RSSIMC_1Q_TSSI
2976. B43_NPHY_RXANTSWITCHCTRL
2977. B43_NPHY_RXCTL
2978. B43_NPHY_RXCTL_BSELU20
2979. B43_NPHY_RXCTL_RIFSEN
2980. B43_NPHY_RXF20_DENOM0
2981. B43_NPHY_RXF20_DENOM1
2982. B43_NPHY_RXF20_DENOM10
2983. B43_NPHY_RXF20_DENOM11
2984. B43_NPHY_RXF20_NUM0
2985. B43_NPHY_RXF20_NUM1
2986. B43_NPHY_RXF20_NUM10
2987. B43_NPHY_RXF20_NUM11
2988. B43_NPHY_RXF20_NUM12
2989. B43_NPHY_RXF20_NUM2
2990. B43_NPHY_RXF40_DENOM0
2991. B43_NPHY_RXF40_DENOM1
2992. B43_NPHY_RXF40_DENOM10
2993. B43_NPHY_RXF40_DENOM11
2994. B43_NPHY_RXF40_NUM0
2995. B43_NPHY_RXF40_NUM1
2996. B43_NPHY_RXF40_NUM10
2997. B43_NPHY_RXF40_NUM11
2998. B43_NPHY_RXF40_NUM12
2999. B43_NPHY_RXF40_NUM2
3000. B43_NPHY_RXMACIFM
3001. B43_NPHY_RXPIL_CYCNT0
3002. B43_NPHY_RXPIL_CYCNT1
3003. B43_NPHY_RXPIL_CYCNT2
3004. B43_NPHY_RXSTRNFILT20DEN00
3005. B43_NPHY_RXSTRNFILT20DEN01
3006. B43_NPHY_RXSTRNFILT20DEN10
3007. B43_NPHY_RXSTRNFILT20DEN11
3008. B43_NPHY_RXSTRNFILT20NUM00
3009. B43_NPHY_RXSTRNFILT20NUM01
3010. B43_NPHY_RXSTRNFILT20NUM02
3011. B43_NPHY_RXSTRNFILT20NUM10
3012. B43_NPHY_RXSTRNFILT20NUM11
3013. B43_NPHY_RXSTRNFILT20NUM12
3014. B43_NPHY_RXSTRNFILT40DEN00
3015. B43_NPHY_RXSTRNFILT40DEN01
3016. B43_NPHY_RXSTRNFILT40DEN10
3017. B43_NPHY_RXSTRNFILT40DEN11
3018. B43_NPHY_RXSTRNFILT40NUM00
3019. B43_NPHY_RXSTRNFILT40NUM01
3020. B43_NPHY_RXSTRNFILT40NUM02
3021. B43_NPHY_RXSTRNFILT40NUM10
3022. B43_NPHY_RXSTRNFILT40NUM11
3023. B43_NPHY_RXSTRNFILT40NUM12
3024. B43_NPHY_RX_SIGCTL
3025. B43_NPHY_SAMC_WCNT
3026. B43_NPHY_SAMPLE_START_ADDR
3027. B43_NPHY_SAMP_CMD
3028. B43_NPHY_SAMP_CMD_STOP
3029. B43_NPHY_SAMP_DEPCNT
3030. B43_NPHY_SAMP_LOOPCNT
3031. B43_NPHY_SAMP_STAT
3032. B43_NPHY_SAMP_WAITCNT
3033. B43_NPHY_SAMTWC
3034. B43_NPHY_SCRAM_SIGCTL
3035. B43_NPHY_SCRAM_SIGCTL_INITST
3036. B43_NPHY_SCRAM_SIGCTL_INITST_SHIFT
3037. B43_NPHY_SCRAM_SIGCTL_SCM
3038. B43_NPHY_SCRAM_SIGCTL_SICE
3039. B43_NPHY_SCRAM_SIGCTL_START
3040. B43_NPHY_SCRAM_SIGCTL_START_SHIFT
3041. B43_NPHY_SGILTRNOFFSET
3042. B43_NPHY_SIGCNT
3043. B43_NPHY_SIGFLDTOL
3044. B43_NPHY_SIGFMOD_WWISE
3045. B43_NPHY_SIGMA_N_MULT
3046. B43_NPHY_SIGSTARTBIT_CTL
3047. B43_NPHY_SISO_SNR_THRES
3048. B43_NPHY_SMALLSGS_LEN
3049. B43_NPHY_SQPARM
3050. B43_NPHY_STRA_1L
3051. B43_NPHY_STRA_1U
3052. B43_NPHY_STRA_2L
3053. B43_NPHY_STRA_2U
3054. B43_NPHY_STRPARAM
3055. B43_NPHY_STRPARAML
3056. B43_NPHY_STRPARAMU
3057. B43_NPHY_STR_ADDR1
3058. B43_NPHY_STR_ADDR2
3059. B43_NPHY_STR_WTIME20L
3060. B43_NPHY_STR_WTIME20U
3061. B43_NPHY_TABLE_ADDR
3062. B43_NPHY_TABLE_DATAHI
3063. B43_NPHY_TABLE_DATALO
3064. B43_NPHY_TGNSYNC_20NCYCDAT
3065. B43_NPHY_TGNSYNC_40NCYCDAT
3066. B43_NPHY_TGNSYNC_CRCM0
3067. B43_NPHY_TGNSYNC_CRCM1
3068. B43_NPHY_TGNSYNC_CRCM2
3069. B43_NPHY_TGNSYNC_CRCM3
3070. B43_NPHY_TGNSYNC_CRCM4
3071. B43_NPHY_TGNSYNC_LENIDX
3072. B43_NPHY_TGNSYNC_SCRAMI0
3073. B43_NPHY_TGNSYNC_SCRAMI1
3074. B43_NPHY_TIMEOUTEN
3075. B43_NPHY_TIMEOUTSTATUS
3076. B43_NPHY_TISRC_TLEN
3077. B43_NPHY_TONE_MIDX20_1
3078. B43_NPHY_TONE_MIDX20_2
3079. B43_NPHY_TONE_MIDX20_3
3080. B43_NPHY_TONE_MIDX40_1
3081. B43_NPHY_TONE_MIDX40_2
3082. B43_NPHY_TONE_MIDX40_3
3083. B43_NPHY_TONE_MIDX40_4
3084. B43_NPHY_TONE_MIDX657M
3085. B43_NPHY_TRLOSS
3086. B43_NPHY_TSSIBIAS1
3087. B43_NPHY_TSSIBIAS2
3088. B43_NPHY_TSSIBIAS_BIAS
3089. B43_NPHY_TSSIBIAS_BIAS_SHIFT
3090. B43_NPHY_TSSIBIAS_VAL
3091. B43_NPHY_TSSIBIAS_VAL_SHIFT
3092. B43_NPHY_TSSIMODE
3093. B43_NPHY_TSSIMODE_EN
3094. B43_NPHY_TSSIMODE_PDEN
3095. B43_NPHY_TSSI_MAXTDT
3096. B43_NPHY_TSSI_MAXTDT_VAL
3097. B43_NPHY_TSSI_MAXTDT_VAL_SHIFT
3098. B43_NPHY_TSSI_MAXTXFDT
3099. B43_NPHY_TSSI_MAXTXFDT_VAL
3100. B43_NPHY_TSSI_MAXTXFDT_VAL_SHIFT
3101. B43_NPHY_TXANTSWLUT
3102. B43_NPHY_TXCCKERROR
3103. B43_NPHY_TXERR
3104. B43_NPHY_TXFRAMEDELAY
3105. B43_NPHY_TXF_20CO_AS0
3106. B43_NPHY_TXF_20CO_AS1
3107. B43_NPHY_TXF_20CO_AS2
3108. B43_NPHY_TXF_20CO_B1S0
3109. B43_NPHY_TXF_20CO_B1S1
3110. B43_NPHY_TXF_20CO_B1S2
3111. B43_NPHY_TXF_20CO_B32S0
3112. B43_NPHY_TXF_20CO_B32S1
3113. B43_NPHY_TXF_20CO_B32S2
3114. B43_NPHY_TXF_20CO_S0A1
3115. B43_NPHY_TXF_20CO_S0A2
3116. B43_NPHY_TXF_20CO_S0B1
3117. B43_NPHY_TXF_20CO_S0B2
3118. B43_NPHY_TXF_20CO_S0B3
3119. B43_NPHY_TXF_20CO_S1A1
3120. B43_NPHY_TXF_20CO_S1A2
3121. B43_NPHY_TXF_20CO_S1B1
3122. B43_NPHY_TXF_20CO_S1B2
3123. B43_NPHY_TXF_20CO_S1B3
3124. B43_NPHY_TXF_20CO_S2A1
3125. B43_NPHY_TXF_20CO_S2A2
3126. B43_NPHY_TXF_20CO_S2B1
3127. B43_NPHY_TXF_20CO_S2B2
3128. B43_NPHY_TXF_20CO_S2B3
3129. B43_NPHY_TXF_40CO_AS0
3130. B43_NPHY_TXF_40CO_AS1
3131. B43_NPHY_TXF_40CO_AS2
3132. B43_NPHY_TXF_40CO_B1S0
3133. B43_NPHY_TXF_40CO_B1S1
3134. B43_NPHY_TXF_40CO_B1S2
3135. B43_NPHY_TXF_40CO_B32S0
3136. B43_NPHY_TXF_40CO_B32S1
3137. B43_NPHY_TXF_40CO_B32S2
3138. B43_NPHY_TXF_40CO_S0A1
3139. B43_NPHY_TXF_40CO_S0A2
3140. B43_NPHY_TXF_40CO_S0B1
3141. B43_NPHY_TXF_40CO_S0B2
3142. B43_NPHY_TXF_40CO_S0B3
3143. B43_NPHY_TXF_40CO_S1A1
3144. B43_NPHY_TXF_40CO_S1A2
3145. B43_NPHY_TXF_40CO_S1B1
3146. B43_NPHY_TXF_40CO_S1B2
3147. B43_NPHY_TXF_40CO_S1B3
3148. B43_NPHY_TXF_40CO_S2A1
3149. B43_NPHY_TXF_40CO_S2A2
3150. B43_NPHY_TXF_40CO_S2B1
3151. B43_NPHY_TXF_40CO_S2B2
3152. B43_NPHY_TXF_40CO_S2B3
3153. B43_NPHY_TXMACDELAY
3154. B43_NPHY_TXMACIF_HOLDOFF
3155. B43_NPHY_TXPCTL_BIDX
3156. B43_NPHY_TXPCTL_BIDX_0
3157. B43_NPHY_TXPCTL_BIDX_0_SHIFT
3158. B43_NPHY_TXPCTL_BIDX_1
3159. B43_NPHY_TXPCTL_BIDX_1_SHIFT
3160. B43_NPHY_TXPCTL_BIDX_LOAD
3161. B43_NPHY_TXPCTL_CMD
3162. B43_NPHY_TXPCTL_CMD_COEFF
3163. B43_NPHY_TXPCTL_CMD_HWPCTLEN
3164. B43_NPHY_TXPCTL_CMD_INIT
3165. B43_NPHY_TXPCTL_CMD_INIT_SHIFT
3166. B43_NPHY_TXPCTL_CMD_PCTLEN
3167. B43_NPHY_TXPCTL_INIT
3168. B43_NPHY_TXPCTL_INIT_PIDXI1
3169. B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT
3170. B43_NPHY_TXPCTL_ITSSI
3171. B43_NPHY_TXPCTL_ITSSI_0
3172. B43_NPHY_TXPCTL_ITSSI_0_SHIFT
3173. B43_NPHY_TXPCTL_ITSSI_1
3174. B43_NPHY_TXPCTL_ITSSI_1_SHIFT
3175. B43_NPHY_TXPCTL_ITSSI_BINF
3176. B43_NPHY_TXPCTL_N
3177. B43_NPHY_TXPCTL_N_NPTIL2
3178. B43_NPHY_TXPCTL_N_NPTIL2_SHIFT
3179. B43_NPHY_TXPCTL_N_TSSID
3180. B43_NPHY_TXPCTL_N_TSSID_SHIFT
3181. B43_NPHY_TXPCTL_PIDX
3182. B43_NPHY_TXPCTL_PIDX_0
3183. B43_NPHY_TXPCTL_PIDX_0_SHIFT
3184. B43_NPHY_TXPCTL_PIDX_1
3185. B43_NPHY_TXPCTL_PIDX_1_SHIFT
3186. B43_NPHY_TXPCTL_STAT_BIDX
3187. B43_NPHY_TXPCTL_STAT_BIDX_SHIFT
3188. B43_NPHY_TXPCTL_STAT_EST
3189. B43_NPHY_TXPCTL_STAT_ESTVALID
3190. B43_NPHY_TXPCTL_STAT_EST_SHIFT
3191. B43_NPHY_TXPCTL_TPWR
3192. B43_NPHY_TXPCTL_TPWR_0
3193. B43_NPHY_TXPCTL_TPWR_0_SHIFT
3194. B43_NPHY_TXPCTL_TPWR_1
3195. B43_NPHY_TXPCTL_TPWR_1_SHIFT
3196. B43_NPHY_TXPWRCTRLDAMPING
3197. B43_NPHY_TXREALFD
3198. B43_NPHY_TXRIFS_FRDEL
3199. B43_NPHY_TXSERFLD
3200. B43_NPHY_TXTAILCNT
3201. B43_NPHY_VLD_DTDAT
3202. B43_NPHY_VLD_DTSIG
3203. B43_NPHY_W1CLIP1_DWELL_LEN
3204. B43_NPHY_W1CLIP2_DWELL_LEN
3205. B43_NPHY_W2CLIP1_DWELL_LEN
3206. B43_NPHY_WWISE_20NCYCDAT
3207. B43_NPHY_WWISE_40NCYCDAT
3208. B43_NPHY_WWISE_CRCM0
3209. B43_NPHY_WWISE_CRCM1
3210. B43_NPHY_WWISE_CRCM2
3211. B43_NPHY_WWISE_CRCM3
3212. B43_NPHY_WWISE_CRCM4
3213. B43_NPHY_WWISE_LENIDX
3214. B43_NPHY_ZFUA
3215. B43_NR_FWTYPES
3216. B43_NR_GROUP_KEYS
3217. B43_NR_LOGGED_TXSTATUS
3218. B43_NR_PAIRWISE_KEYS
3219. B43_NR_QOSPARAMS
3220. B43_NTAB16
3221. B43_NTAB32
3222. B43_NTAB8
3223. B43_NTAB_16BIT
3224. B43_NTAB_32BIT
3225. B43_NTAB_8BIT
3226. B43_NTAB_ANT_SW_CTL_R3
3227. B43_NTAB_BDI
3228. B43_NTAB_BDI_SIZE
3229. B43_NTAB_C0_ADJPLT
3230. B43_NTAB_C0_ADJPLT_R3
3231. B43_NTAB_C0_ADJPLT_SIZE
3232. B43_NTAB_C0_ESTPLT
3233. B43_NTAB_C0_ESTPLT_R3
3234. B43_NTAB_C0_ESTPLT_SIZE
3235. B43_NTAB_C0_GAINCTL
3236. B43_NTAB_C0_GAINCTL_R3
3237. B43_NTAB_C0_GAINCTL_SIZE
3238. B43_NTAB_C0_IQLT
3239. B43_NTAB_C0_IQLT_R3
3240. B43_NTAB_C0_IQLT_SIZE
3241. B43_NTAB_C0_LOFEEDTH
3242. B43_NTAB_C0_LOFEEDTH_R3
3243. B43_NTAB_C0_LOFEEDTH_SIZE
3244. B43_NTAB_C0_PAPD_COMP_R3
3245. B43_NTAB_C1_ADJPLT
3246. B43_NTAB_C1_ADJPLT_R3
3247. B43_NTAB_C1_ADJPLT_SIZE
3248. B43_NTAB_C1_ESTPLT
3249. B43_NTAB_C1_ESTPLT_R3
3250. B43_NTAB_C1_ESTPLT_SIZE
3251. B43_NTAB_C1_GAINCTL
3252. B43_NTAB_C1_GAINCTL_R3
3253. B43_NTAB_C1_GAINCTL_SIZE
3254. B43_NTAB_C1_IQLT
3255. B43_NTAB_C1_IQLT_R3
3256. B43_NTAB_C1_IQLT_SIZE
3257. B43_NTAB_C1_LOFEEDTH
3258. B43_NTAB_C1_LOFEEDTH_R3
3259. B43_NTAB_C1_LOFEEDTH_SIZE
3260. B43_NTAB_C1_PAPD_COMP_R3
3261. B43_NTAB_CHANEST
3262. B43_NTAB_CHANEST_R3
3263. B43_NTAB_CHANEST_SIZE
3264. B43_NTAB_FRAMELT
3265. B43_NTAB_FRAMELT_R3
3266. B43_NTAB_FRAMELT_SIZE
3267. B43_NTAB_FRAMESTRUCT
3268. B43_NTAB_FRAMESTRUCT_R3
3269. B43_NTAB_FRAMESTRUCT_SIZE
3270. B43_NTAB_INTLEVEL
3271. B43_NTAB_INTLEVEL_R3
3272. B43_NTAB_INTLEVEL_SIZE
3273. B43_NTAB_MCS
3274. B43_NTAB_MCS_R3
3275. B43_NTAB_MCS_SIZE
3276. B43_NTAB_NOISEVAR10
3277. B43_NTAB_NOISEVAR10_SIZE
3278. B43_NTAB_NOISEVAR11
3279. B43_NTAB_NOISEVAR11_SIZE
3280. B43_NTAB_NOISEVAR_R3
3281. B43_NTAB_NOISEVAR_R7
3282. B43_NTAB_PILOT
3283. B43_NTAB_PILOTLT
3284. B43_NTAB_PILOTLT_R3
3285. B43_NTAB_PILOTLT_SIZE
3286. B43_NTAB_PILOT_R3
3287. B43_NTAB_PILOT_SIZE
3288. B43_NTAB_TDI20A0
3289. B43_NTAB_TDI20A0_R3
3290. B43_NTAB_TDI20A0_SIZE
3291. B43_NTAB_TDI20A1
3292. B43_NTAB_TDI20A1_R3
3293. B43_NTAB_TDI20A1_SIZE
3294. B43_NTAB_TDI40A0
3295. B43_NTAB_TDI40A0_R3
3296. B43_NTAB_TDI40A0_SIZE
3297. B43_NTAB_TDI40A1
3298. B43_NTAB_TDI40A1_R3
3299. B43_NTAB_TDI40A1_SIZE
3300. B43_NTAB_TDTRN
3301. B43_NTAB_TDTRN_R3
3302. B43_NTAB_TDTRN_SIZE
3303. B43_NTAB_TMAP
3304. B43_NTAB_TMAP_R3
3305. B43_NTAB_TMAP_R7
3306. B43_NTAB_TMAP_SIZE
3307. B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL
3308. B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3
3309. B43_NTAB_TX_IQLO_CAL_CMDS_RECAL
3310. B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3
3311. B43_NTAB_TX_IQLO_CAL_IQIMB_LADDER_20_SIZE
3312. B43_NTAB_TX_IQLO_CAL_IQIMB_LADDER_40_SIZE
3313. B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE
3314. B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE
3315. B43_NTAB_TX_IQLO_CAL_STARTCOEFS
3316. B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3
3317. B43_NTAB_TYPEMASK
3318. B43_OFDMTAB
3319. B43_OFDMTAB_ADVRETARD
3320. B43_OFDMTAB_AGC1
3321. B43_OFDMTAB_AGC1_R1
3322. B43_OFDMTAB_AGC2
3323. B43_OFDMTAB_AGC3
3324. B43_OFDMTAB_AGC3_R1
3325. B43_OFDMTAB_DAC
3326. B43_OFDMTAB_DACOFF
3327. B43_OFDMTAB_DACRFPABB
3328. B43_OFDMTAB_DC
3329. B43_OFDMTAB_DCBIAS
3330. B43_OFDMTAB_DIRECTION_READ
3331. B43_OFDMTAB_DIRECTION_UNKNOWN
3332. B43_OFDMTAB_DIRECTION_WRITE
3333. B43_OFDMTAB_GAIN0
3334. B43_OFDMTAB_GAIN1
3335. B43_OFDMTAB_GAIN2
3336. B43_OFDMTAB_GAINX
3337. B43_OFDMTAB_GAINX_R1
3338. B43_OFDMTAB_LNAGAIN
3339. B43_OFDMTAB_LNAHPFGAIN1
3340. B43_OFDMTAB_LNAHPFGAIN2
3341. B43_OFDMTAB_LPFGAIN
3342. B43_OFDMTAB_MINSIGSQ
3343. B43_OFDMTAB_NOISESCALE
3344. B43_OFDMTAB_PWRDYN2
3345. B43_OFDMTAB_ROTOR
3346. B43_OFDMTAB_RSSI
3347. B43_OFDMTAB_TSSI
3348. B43_OFDMTAB_UNKNOWN_0F
3349. B43_OFDMTAB_UNKNOWN_11
3350. B43_OFDMTAB_UNKNOWN_APHY
3351. B43_OFDMTAB_WRSSI
3352. B43_OFDMTAB_WRSSI_R1
3353. B43_OFDM_RATE_12MB
3354. B43_OFDM_RATE_18MB
3355. B43_OFDM_RATE_24MB
3356. B43_OFDM_RATE_36MB
3357. B43_OFDM_RATE_48MB
3358. B43_OFDM_RATE_54MB
3359. B43_OFDM_RATE_6MB
3360. B43_OFDM_RATE_9MB
3361. B43_PCTL_CLK_DYNAMIC
3362. B43_PCTL_CLK_FAST
3363. B43_PCTL_CLK_SLOW
3364. B43_PCTL_DYN_XTAL
3365. B43_PCTL_FORCE_PLL
3366. B43_PCTL_FORCE_SLOW
3367. B43_PCTL_IN
3368. B43_PCTL_OUT
3369. B43_PCTL_OUTENABLE
3370. B43_PCTL_PLL_POWERDOWN
3371. B43_PCTL_XTAL_POWERUP
3372. B43_PHYROUTE
3373. B43_PHYROUTE_BASE
3374. B43_PHYROUTE_EXT_GPHY
3375. B43_PHYROUTE_N_BMODE
3376. B43_PHYROUTE_OFDM_GPHY
3377. B43_PHYTYPE_A
3378. B43_PHYTYPE_AC
3379. B43_PHYTYPE_B
3380. B43_PHYTYPE_G
3381. B43_PHYTYPE_HT
3382. B43_PHYTYPE_LCN
3383. B43_PHYTYPE_LCN40
3384. B43_PHYTYPE_LCNXN
3385. B43_PHYTYPE_LP
3386. B43_PHYTYPE_N
3387. B43_PHYTYPE_SSLPN
3388. B43_PHYVER_ANALOG
3389. B43_PHYVER_ANALOG_SHIFT
3390. B43_PHYVER_TYPE
3391. B43_PHYVER_TYPE_SHIFT
3392. B43_PHYVER_VERSION
3393. B43_PHY_AC_BANDCTL
3394. B43_PHY_AC_BANDCTL_5GHZ
3395. B43_PHY_AC_BBCFG
3396. B43_PHY_AC_BBCFG_RSTCCA
3397. B43_PHY_AC_BW1A
3398. B43_PHY_AC_BW2
3399. B43_PHY_AC_BW3
3400. B43_PHY_AC_BW4
3401. B43_PHY_AC_BW5
3402. B43_PHY_AC_BW6
3403. B43_PHY_AC_C1_CLIP
3404. B43_PHY_AC_C1_CLIP_DIS
3405. B43_PHY_AC_C2_CLIP
3406. B43_PHY_AC_C2_CLIP_DIS
3407. B43_PHY_AC_C3_CLIP
3408. B43_PHY_AC_C3_CLIP_DIS
3409. B43_PHY_AC_CLASSCTL
3410. B43_PHY_AC_CLASSCTL_CCKEN
3411. B43_PHY_AC_CLASSCTL_OFDMEN
3412. B43_PHY_AC_CLASSCTL_WAITEDEN
3413. B43_PHY_AC_H_
3414. B43_PHY_AC_RFCTL_CMD
3415. B43_PHY_AC_TABLE_DATA1
3416. B43_PHY_AC_TABLE_DATA2
3417. B43_PHY_AC_TABLE_DATA3
3418. B43_PHY_AC_TABLE_ID
3419. B43_PHY_AC_TABLE_OFFSET
3420. B43_PHY_ADCCTL
3421. B43_PHY_ADIVRELATED
3422. B43_PHY_ANALOGOVER
3423. B43_PHY_ANALOGOVERVAL
3424. B43_PHY_ANTDWELL
3425. B43_PHY_ANTDWELL_AUTODIV1
3426. B43_PHY_ANTWRSETT
3427. B43_PHY_ANTWRSETT_ARXDIV
3428. B43_PHY_A_CRS
3429. B43_PHY_A_PCTL
3430. B43_PHY_A_TEMP_SENSE
3431. B43_PHY_BBANDCFG
3432. B43_PHY_BBANDCFG_RXANT
3433. B43_PHY_BBANDCFG_RXANT_SHIFT
3434. B43_PHY_BBTXDC_BIAS
3435. B43_PHY_B_BBCFG
3436. B43_PHY_B_BBCFG_RSTCCA
3437. B43_PHY_B_BBCFG_RSTRX
3438. B43_PHY_B_TEST
3439. B43_PHY_CCK
3440. B43_PHY_CCKBBANDCFG
3441. B43_PHY_CCKSHIFTBITS
3442. B43_PHY_CCKSHIFTBITS_WA
3443. B43_PHY_CLASSCTL
3444. B43_PHY_CLIPN1P2THRES
3445. B43_PHY_CLIPP2THRES
3446. B43_PHY_CLIPP3THRES
3447. B43_PHY_CLIPPWRDOWNT
3448. B43_PHY_CLIPTHRES
3449. B43_PHY_CRS0
3450. B43_PHY_CRS0_EN
3451. B43_PHY_CRSTHRES1
3452. B43_PHY_CRSTHRES1_R1
3453. B43_PHY_CRSTHRES2
3454. B43_PHY_DACCTL
3455. B43_PHY_DC_LTBASE
3456. B43_PHY_DIVP1P2GAIN
3457. B43_PHY_DIVSRCHGAINBACK
3458. B43_PHY_DIVSRCHGAINCHNG
3459. B43_PHY_DIVSRCHIDX
3460. B43_PHY_ENCORE
3461. B43_PHY_ENCORE_EN
3462. B43_PHY_ENERGY
3463. B43_PHY_EXTG
3464. B43_PHY_FBCTL1
3465. B43_PHY_FBCTL2
3466. B43_PHY_GAIN_LTBASE
3467. B43_PHY_GTABCTL
3468. B43_PHY_GTABDATA
3469. B43_PHY_GTABNR
3470. B43_PHY_GTABNR_SHIFT
3471. B43_PHY_GTABOFF
3472. B43_PHY_G_CRS
3473. B43_PHY_G_LO_CONTROL
3474. B43_PHY_G_PCTL
3475. B43_PHY_HPWR_TSSICTL
3476. B43_PHY_HT_AFE_C1
3477. B43_PHY_HT_AFE_C1_OVER
3478. B43_PHY_HT_AFE_C2
3479. B43_PHY_HT_AFE_C2_OVER
3480. B43_PHY_HT_AFE_C3
3481. B43_PHY_HT_AFE_C3_OVER
3482. B43_PHY_HT_BANDCTL
3483. B43_PHY_HT_BANDCTL_5GHZ
3484. B43_PHY_HT_BBCFG
3485. B43_PHY_HT_BBCFG_RSTCCA
3486. B43_PHY_HT_BBCFG_RSTRX
3487. B43_PHY_HT_BW1
3488. B43_PHY_HT_BW2
3489. B43_PHY_HT_BW3
3490. B43_PHY_HT_BW4
3491. B43_PHY_HT_BW5
3492. B43_PHY_HT_BW6
3493. B43_PHY_HT_C1_CLIP1THRES
3494. B43_PHY_HT_C2_CLIP1THRES
3495. B43_PHY_HT_C3_CLIP1THRES
3496. B43_PHY_HT_CLASS_CTL
3497. B43_PHY_HT_CLASS_CTL_CCK_EN
3498. B43_PHY_HT_CLASS_CTL_OFDM_EN
3499. B43_PHY_HT_CLASS_CTL_WAITED_EN
3500. B43_PHY_HT_EST_PWR_C1
3501. B43_PHY_HT_EST_PWR_C2
3502. B43_PHY_HT_EST_PWR_C3
3503. B43_PHY_HT_H_
3504. B43_PHY_HT_IQLOCAL_CMDGCTL
3505. B43_PHY_HT_RF_CTL_CMD
3506. B43_PHY_HT_RF_CTL_CMD_CHIP0_PU
3507. B43_PHY_HT_RF_CTL_CMD_FORCE
3508. B43_PHY_HT_RF_CTL_INT_C1
3509. B43_PHY_HT_RF_CTL_INT_C2
3510. B43_PHY_HT_RF_CTL_INT_C3
3511. B43_PHY_HT_RF_SEQ_MODE
3512. B43_PHY_HT_RF_SEQ_MODE_CA_OVER
3513. B43_PHY_HT_RF_SEQ_MODE_TR_OVER
3514. B43_PHY_HT_RF_SEQ_STATUS
3515. B43_PHY_HT_RF_SEQ_TRIG
3516. B43_PHY_HT_RF_SEQ_TRIG_RST2RX
3517. B43_PHY_HT_RF_SEQ_TRIG_RX2TX
3518. B43_PHY_HT_RF_SEQ_TRIG_TX2RX
3519. B43_PHY_HT_RF_SEQ_TRIG_UPGH
3520. B43_PHY_HT_RF_SEQ_TRIG_UPGL
3521. B43_PHY_HT_RF_SEQ_TRIG_UPGU
3522. B43_PHY_HT_RSSI_C1
3523. B43_PHY_HT_RSSI_C2
3524. B43_PHY_HT_RSSI_C3
3525. B43_PHY_HT_SAMP_CMD
3526. B43_PHY_HT_SAMP_CMD_STOP
3527. B43_PHY_HT_SAMP_DEP_CNT
3528. B43_PHY_HT_SAMP_LOOP_CNT
3529. B43_PHY_HT_SAMP_STAT
3530. B43_PHY_HT_SAMP_WAIT_CNT
3531. B43_PHY_HT_TABLE_ADDR
3532. B43_PHY_HT_TABLE_DATAHI
3533. B43_PHY_HT_TABLE_DATALO
3534. B43_PHY_HT_TEST
3535. B43_PHY_HT_TSSIMODE
3536. B43_PHY_HT_TSSIMODE_EN
3537. B43_PHY_HT_TSSIMODE_PDEN
3538. B43_PHY_HT_TXPCTL_CMD_C1
3539. B43_PHY_HT_TXPCTL_CMD_C1_COEFF
3540. B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN
3541. B43_PHY_HT_TXPCTL_CMD_C1_INIT
3542. B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN
3543. B43_PHY_HT_TXPCTL_CMD_C2
3544. B43_PHY_HT_TXPCTL_CMD_C2_INIT
3545. B43_PHY_HT_TXPCTL_CMD_C3
3546. B43_PHY_HT_TXPCTL_CMD_C3_INIT
3547. B43_PHY_HT_TXPCTL_IDLE_TSSI
3548. B43_PHY_HT_TXPCTL_IDLE_TSSI2
3549. B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3
3550. B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT
3551. B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF
3552. B43_PHY_HT_TXPCTL_IDLE_TSSI_C1
3553. B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT
3554. B43_PHY_HT_TXPCTL_IDLE_TSSI_C2
3555. B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT
3556. B43_PHY_HT_TXPCTL_N
3557. B43_PHY_HT_TXPCTL_N_NPTIL2
3558. B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT
3559. B43_PHY_HT_TXPCTL_N_TSSID
3560. B43_PHY_HT_TXPCTL_N_TSSID_SHIFT
3561. B43_PHY_HT_TXPCTL_TARG_PWR
3562. B43_PHY_HT_TXPCTL_TARG_PWR2
3563. B43_PHY_HT_TXPCTL_TARG_PWR2_C3
3564. B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT
3565. B43_PHY_HT_TXPCTL_TARG_PWR_C1
3566. B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT
3567. B43_PHY_HT_TXPCTL_TARG_PWR_C2
3568. B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT
3569. B43_PHY_HT_TX_PCTL_STATUS_C1
3570. B43_PHY_HT_TX_PCTL_STATUS_C2
3571. B43_PHY_HT_TX_PCTL_STATUS_C3
3572. B43_PHY_IDLE_TSSI
3573. B43_PHY_ILT_A_CTRL
3574. B43_PHY_ILT_A_DATA1
3575. B43_PHY_ILT_A_DATA2
3576. B43_PHY_ILT_G_CTRL
3577. B43_PHY_ILT_G_DATA1
3578. B43_PHY_ILT_G_DATA2
3579. B43_PHY_IQBAL
3580. B43_PHY_ITSSI
3581. B43_PHY_LCN_AFE_CTL1
3582. B43_PHY_LCN_AFE_CTL2
3583. B43_PHY_LCN_H_
3584. B43_PHY_LCN_RF_CTL1
3585. B43_PHY_LCN_RF_CTL2
3586. B43_PHY_LCN_RF_CTL3
3587. B43_PHY_LCN_RF_CTL4
3588. B43_PHY_LCN_RF_CTL5
3589. B43_PHY_LCN_RF_CTL6
3590. B43_PHY_LCN_RF_CTL7
3591. B43_PHY_LCN_TABLE_ADDR
3592. B43_PHY_LCN_TABLE_DATAHI
3593. B43_PHY_LCN_TABLE_DATALO
3594. B43_PHY_LMS
3595. B43_PHY_LNAHPFCTL
3596. B43_PHY_LO_CTL
3597. B43_PHY_LO_LEAKAGE
3598. B43_PHY_LO_MASK
3599. B43_PHY_LPFGAINCTL
3600. B43_PHY_N
3601. B43_PHY_N1N2GAIN
3602. B43_PHY_N1P1GAIN
3603. B43_PHY_NRSSILT_CTRL
3604. B43_PHY_NRSSILT_DATA
3605. B43_PHY_NRSSITHRES
3606. B43_PHY_N_BMODE
3607. B43_PHY_OFDM
3608. B43_PHY_OFDM61
3609. B43_PHY_OFDM61_10
3610. B43_PHY_OFDM9B
3611. B43_PHY_OTABLECTL
3612. B43_PHY_OTABLEI
3613. B43_PHY_OTABLENR
3614. B43_PHY_OTABLENR_SHIFT
3615. B43_PHY_OTABLEOFF
3616. B43_PHY_OTABLEQ
3617. B43_PHY_P1P2GAIN
3618. B43_PHY_PEAK_COUNT
3619. B43_PHY_PGACTL
3620. B43_PHY_PGACTL_LOWBANDW
3621. B43_PHY_PGACTL_LPF
3622. B43_PHY_PGACTL_UNKNOWN
3623. B43_PHY_PWRDOWN
3624. B43_PHY_RADIO_BITFIELD
3625. B43_PHY_RCCALOVER
3626. B43_PHY_RFOVER
3627. B43_PHY_RFOVERVAL
3628. B43_PHY_RFOVERVAL_BW
3629. B43_PHY_RFOVERVAL_BW_LBW
3630. B43_PHY_RFOVERVAL_BW_LPF
3631. B43_PHY_RFOVERVAL_EXTLNA
3632. B43_PHY_RFOVERVAL_LNA
3633. B43_PHY_RFOVERVAL_LNA_SHIFT
3634. B43_PHY_RFOVERVAL_PGA
3635. B43_PHY_RFOVERVAL_PGA_SHIFT
3636. B43_PHY_RFOVERVAL_TRSWRX
3637. B43_PHY_RFOVERVAL_UNK
3638. B43_PHY_SYNCCTL
3639. B43_PHY_TSSIP_LTBASE
3640. B43_PHY_TX_BADNESS_LIMIT
3641. B43_PHY_VERSION_CCK
3642. B43_PHY_VERSION_OFDM
3643. B43_PIO8_RXCTL
3644. B43_PIO8_RXCTL_DATARDY
3645. B43_PIO8_RXCTL_FRAMERDY
3646. B43_PIO8_RXDATA
3647. B43_PIO8_TXCTL
3648. B43_PIO8_TXCTL_0_7
3649. B43_PIO8_TXCTL_16_23
3650. B43_PIO8_TXCTL_24_31
3651. B43_PIO8_TXCTL_8_15
3652. B43_PIO8_TXCTL_EOF
3653. B43_PIO8_TXCTL_FLUSHPEND
3654. B43_PIO8_TXCTL_FLUSHREQ
3655. B43_PIO8_TXCTL_FREADY
3656. B43_PIO8_TXCTL_QSUSP
3657. B43_PIO8_TXCTL_SUSPREQ
3658. B43_PIO8_TXDATA
3659. B43_PIO_H_
3660. B43_PIO_MAX_NR_TXPACKETS
3661. B43_PIO_RXCTL
3662. B43_PIO_RXCTL_DATARDY
3663. B43_PIO_RXCTL_FRAMERDY
3664. B43_PIO_RXDATA
3665. B43_PIO_TXCTL
3666. B43_PIO_TXCTL_COMMCNT
3667. B43_PIO_TXCTL_COMMCNT_SHIFT
3668. B43_PIO_TXCTL_EOF
3669. B43_PIO_TXCTL_FLUSHPEND
3670. B43_PIO_TXCTL_FLUSHREQ
3671. B43_PIO_TXCTL_FREADY
3672. B43_PIO_TXCTL_QSUSP
3673. B43_PIO_TXCTL_SUSPREQ
3674. B43_PIO_TXCTL_WRITEHI
3675. B43_PIO_TXCTL_WRITELO
3676. B43_PIO_TXDATA
3677. B43_PIO_TXQBUFSIZE
3678. B43_PPR_CCK_RATES_NUM
3679. B43_PPR_MCS_RATES_NUM
3680. B43_PPR_OFDM_RATES_NUM
3681. B43_PPR_RATES_NUM
3682. B43_PSM_HDR_MAC_PHY_CLOCK_EN
3683. B43_PSM_HDR_MAC_PHY_FORCE_CLK
3684. B43_PSM_HDR_MAC_PHY_RESET
3685. B43_PS_ASLEEP
3686. B43_PS_AWAKE
3687. B43_PS_DISABLED
3688. B43_PS_ENABLED
3689. B43_QOSPARAM_AIFS
3690. B43_QOSPARAM_BSLOTS
3691. B43_QOSPARAM_CWCUR
3692. B43_QOSPARAM_CWMAX
3693. B43_QOSPARAM_CWMIN
3694. B43_QOSPARAM_REGGAP
3695. B43_QOSPARAM_STATUS
3696. B43_QOSPARAM_TXOP
3697. B43_QOS_BACKGROUND
3698. B43_QOS_BESTEFFORT
3699. B43_QOS_PARAMS
3700. B43_QOS_QUEUE_NUM
3701. B43_QOS_VIDEO
3702. B43_QOS_VOICE
3703. B43_RADIOCTL_ID
3704. B43_RADIO_2055_H_
3705. B43_RADIO_2056_H_
3706. B43_RADIO_2057_H_
3707. B43_RADIO_2059_H_
3708. B43_RATE_TO_BASE100KBPS
3709. B43_RFKILL_H_
3710. B43_RFSEQ_RESET2RX
3711. B43_RFSEQ_RX2TX
3712. B43_RFSEQ_TX2RX
3713. B43_RFSEQ_UPDATE_GAINH
3714. B43_RFSEQ_UPDATE_GAINL
3715. B43_RFSEQ_UPDATE_GAINU
3716. B43_RXRING_SLOTS
3717. B43_RX_CHAN_40MHZ
3718. B43_RX_CHAN_5GHZ
3719. B43_RX_CHAN_ID
3720. B43_RX_CHAN_ID_SHIFT
3721. B43_RX_CHAN_PHYTYPE
3722. B43_RX_MAC_AGGTYPE
3723. B43_RX_MAC_AGGTYPE_SHIFT
3724. B43_RX_MAC_AMSDU
3725. B43_RX_MAC_BEACONSENT
3726. B43_RX_MAC_DEC
3727. B43_RX_MAC_DECERR
3728. B43_RX_MAC_FCSERR
3729. B43_RX_MAC_KEYIDX
3730. B43_RX_MAC_KEYIDX_SHIFT
3731. B43_RX_MAC_PADDING
3732. B43_RX_MAC_RESP
3733. B43_RX_MAC_RXST_VALID
3734. B43_RX_MAC_TKIP_MICATT
3735. B43_RX_MAC_TKIP_MICERR
3736. B43_RX_PHYST0_ANT
3737. B43_RX_PHYST0_CCK
3738. B43_RX_PHYST0_CLIP
3739. B43_RX_PHYST0_CLIP_SHIFT
3740. B43_RX_PHYST0_FTYPE
3741. B43_RX_PHYST0_GAINCTL
3742. B43_RX_PHYST0_LCRS
3743. B43_RX_PHYST0_OFDM
3744. B43_RX_PHYST0_PLCPFV
3745. B43_RX_PHYST0_PLCPHCF
3746. B43_RX_PHYST0_PRE_N
3747. B43_RX_PHYST0_SHORTPRMBL
3748. B43_RX_PHYST0_STD_N
3749. B43_RX_PHYST0_UNSRATE
3750. B43_RX_PHYST2_FOFF
3751. B43_RX_PHYST2_LNAG
3752. B43_RX_PHYST2_LNAG_SHIFT
3753. B43_RX_PHYST2_PNAG
3754. B43_RX_PHYST2_PNAG_SHIFT
3755. B43_RX_PHYST3_DIGG
3756. B43_RX_PHYST3_DIGG_SHIFT
3757. B43_RX_PHYST3_TRSTATE
3758. B43_SDIO_BLOCK_SIZE
3759. B43_SDIO_H_
3760. B43_SEC_ALGO_AES
3761. B43_SEC_ALGO_AES_LEGACY
3762. B43_SEC_ALGO_NONE
3763. B43_SEC_ALGO_TKIP
3764. B43_SEC_ALGO_WEP104
3765. B43_SEC_ALGO_WEP40
3766. B43_SEC_KEYSIZE
3767. B43_SENSE_TEMP
3768. B43_SENSE_VBAT
3769. B43_SHM_AUTOINC_R
3770. B43_SHM_AUTOINC_RW
3771. B43_SHM_AUTOINC_W
3772. B43_SHM_HW
3773. B43_SHM_RCMTA
3774. B43_SHM_SCRATCH
3775. B43_SHM_SC_BTL0LEN
3776. B43_SHM_SC_BTL1LEN
3777. B43_SHM_SC_CURCONT
3778. B43_SHM_SC_DTIMC
3779. B43_SHM_SC_LCFB
3780. B43_SHM_SC_LRLIMIT
3781. B43_SHM_SC_MAXCONT
3782. B43_SHM_SC_MINCONT
3783. B43_SHM_SC_SCFB
3784. B43_SHM_SC_SRLIMIT
3785. B43_SHM_SHARED
3786. B43_SHM_SH_ACKCTSPHYCTL
3787. B43_SHM_SH_ANTSWAP
3788. B43_SHM_SH_BCMCFIFOID
3789. B43_SHM_SH_BCN_LI
3790. B43_SHM_SH_BEACPHYCTL
3791. B43_SHM_SH_BTL0
3792. B43_SHM_SH_BTL1
3793. B43_SHM_SH_BTSFOFF
3794. B43_SHM_SH_BT_BASE0
3795. B43_SHM_SH_BT_BASE1
3796. B43_SHM_SH_CCKBASIC
3797. B43_SHM_SH_CCKDIRECT
3798. B43_SHM_SH_CHAN
3799. B43_SHM_SH_CHAN_40MHZ
3800. B43_SHM_SH_CHAN_5GHZ
3801. B43_SHM_SH_DEFAULTIV
3802. B43_SHM_SH_DTIMP
3803. B43_SHM_SH_DTIMPER
3804. B43_SHM_SH_EDCFQ
3805. B43_SHM_SH_EDCFSTAT
3806. B43_SHM_SH_EXTNPHYCTL
3807. B43_SHM_SH_FWCAPA
3808. B43_SHM_SH_HOSTF1
3809. B43_SHM_SH_HOSTF2
3810. B43_SHM_SH_HOSTF3
3811. B43_SHM_SH_HOSTF4
3812. B43_SHM_SH_HOSTF5
3813. B43_SHM_SH_JSSI0
3814. B43_SHM_SH_JSSI1
3815. B43_SHM_SH_JSSIAUX
3816. B43_SHM_SH_KEYIDXBLOCK
3817. B43_SHM_SH_KTP
3818. B43_SHM_SH_LFFBLIM
3819. B43_SHM_SH_MACHW_H
3820. B43_SHM_SH_MACHW_L
3821. B43_SHM_SH_MAXBFRAMES
3822. B43_SHM_SH_MCASTCOOKIE
3823. B43_SHM_SH_NOSLPZNATDTIM
3824. B43_SHM_SH_NPHY_TXIQW0
3825. B43_SHM_SH_NPHY_TXIQW1
3826. B43_SHM_SH_NPHY_TXIQW2
3827. B43_SHM_SH_NPHY_TXIQW3
3828. B43_SHM_SH_NPHY_TXPWR_INDX0
3829. B43_SHM_SH_NPHY_TXPWR_INDX1
3830. B43_SHM_SH_NRRXTRANS
3831. B43_SHM_SH_OFDMBASIC
3832. B43_SHM_SH_OFDMDIRECT
3833. B43_SHM_SH_PCTLWDPOS
3834. B43_SHM_SH_PHYTXNOI
3835. B43_SHM_SH_PHYTYPE
3836. B43_SHM_SH_PHYVER
3837. B43_SHM_SH_PRETBTT
3838. B43_SHM_SH_PRMAXTIME
3839. B43_SHM_SH_PRPHYCTL
3840. B43_SHM_SH_PRSSID
3841. B43_SHM_SH_PRSSIDLEN
3842. B43_SHM_SH_PRTLEN
3843. B43_SHM_SH_PSM
3844. B43_SHM_SH_RADAR
3845. B43_SHM_SH_RFATT
3846. B43_SHM_SH_RFRXSP1
3847. B43_SHM_SH_RXPADOFF
3848. B43_SHM_SH_SFFBLIM
3849. B43_SHM_SH_SIZE01
3850. B43_SHM_SH_SIZE23
3851. B43_SHM_SH_SIZE45
3852. B43_SHM_SH_SIZE67
3853. B43_SHM_SH_SLOTT
3854. B43_SHM_SH_SPUWKUP
3855. B43_SHM_SH_TIMBPOS
3856. B43_SHM_SH_TKIPTSCTTAK
3857. B43_SHM_SH_TSSI_CCK
3858. B43_SHM_SH_TSSI_OFDM_A
3859. B43_SHM_SH_TSSI_OFDM_G
3860. B43_SHM_SH_TXFCUR
3861. B43_SHM_SH_UCODEDATE
3862. B43_SHM_SH_UCODEPATCH
3863. B43_SHM_SH_UCODEREV
3864. B43_SHM_SH_UCODESTAT
3865. B43_SHM_SH_UCODESTAT_ACTIVE
3866. B43_SHM_SH_UCODESTAT_INIT
3867. B43_SHM_SH_UCODESTAT_INVALID
3868. B43_SHM_SH_UCODESTAT_SLEEP
3869. B43_SHM_SH_UCODESTAT_SUSP
3870. B43_SHM_SH_UCODETIME
3871. B43_SHM_SH_WLCOREREV
3872. B43_SHM_UCODE
3873. B43_SPUR_AVOID_AUTO
3874. B43_SPUR_AVOID_DISABLE
3875. B43_SPUR_AVOID_FORCE
3876. B43_STAT_INITIALIZED
3877. B43_STAT_STARTED
3878. B43_STAT_UNINIT
3879. B43_SYSFS_H_
3880. B43_TABLES_H_
3881. B43_TABLES_LPPHY_H_
3882. B43_TABLES_NPHY_H_
3883. B43_TABLES_PHY_HT_H_
3884. B43_TABLES_PHY_LCN_H_
3885. B43_TAB_FINEFREQA_SIZE
3886. B43_TAB_FINEFREQG_SIZE
3887. B43_TAB_NOISEA2_SIZE
3888. B43_TAB_NOISEA3_SIZE
3889. B43_TAB_NOISEG1_SIZE
3890. B43_TAB_NOISEG2_SIZE
3891. B43_TAB_NOISESCALE_SIZE
3892. B43_TAB_RETARD_SIZE
3893. B43_TAB_ROTOR_SIZE
3894. B43_TAB_RSSIAGC1_SIZE
3895. B43_TAB_RSSIAGC2_SIZE
3896. B43_TAB_SIGMASQR_SIZE
3897. B43_TMSHIGH_DUALBAND_PHY
3898. B43_TMSHIGH_FCLOCK
3899. B43_TMSHIGH_HAVE_2GHZ_PHY
3900. B43_TMSHIGH_HAVE_5GHZ_PHY
3901. B43_TMSLOW_GMODE
3902. B43_TMSLOW_MACPHYCLKEN
3903. B43_TMSLOW_PHYCLKEN
3904. B43_TMSLOW_PHYRESET
3905. B43_TMSLOW_PHY_BANDWIDTH
3906. B43_TMSLOW_PHY_BANDWIDTH_10MHZ
3907. B43_TMSLOW_PHY_BANDWIDTH_20MHZ
3908. B43_TMSLOW_PHY_BANDWIDTH_40MHZ
3909. B43_TMSLOW_PLLREFSEL
3910. B43_TSSI_MAX
3911. B43_TXCTL_PA2DB
3912. B43_TXCTL_PA3DB
3913. B43_TXCTL_TXMIX
3914. B43_TXH_EFT_FB
3915. B43_TXH_EFT_FB_CCK
3916. B43_TXH_EFT_FB_HT
3917. B43_TXH_EFT_FB_OFDM
3918. B43_TXH_EFT_FB_VHT
3919. B43_TXH_EFT_RTS
3920. B43_TXH_EFT_RTSFB
3921. B43_TXH_EFT_RTSFB_CCK
3922. B43_TXH_EFT_RTSFB_HT
3923. B43_TXH_EFT_RTSFB_OFDM
3924. B43_TXH_EFT_RTSFB_VHT
3925. B43_TXH_EFT_RTS_CCK
3926. B43_TXH_EFT_RTS_HT
3927. B43_TXH_EFT_RTS_OFDM
3928. B43_TXH_EFT_RTS_VHT
3929. B43_TXH_MAC_40MHZ
3930. B43_TXH_MAC_5GHZ
3931. B43_TXH_MAC_ACK
3932. B43_TXH_MAC_ALT_TXPWR
3933. B43_TXH_MAC_AMIC
3934. B43_TXH_MAC_AMPDU
3935. B43_TXH_MAC_AMPDU_FIRST
3936. B43_TXH_MAC_AMPDU_INTER
3937. B43_TXH_MAC_AMPDU_LAST
3938. B43_TXH_MAC_AMPDU_MPDU
3939. B43_TXH_MAC_DFCS
3940. B43_TXH_MAC_FB_SHORTPRMBL
3941. B43_TXH_MAC_FRAMEBURST
3942. B43_TXH_MAC_HWSEQ
3943. B43_TXH_MAC_IGNPMQ
3944. B43_TXH_MAC_KEYALG
3945. B43_TXH_MAC_KEYALG_SHIFT
3946. B43_TXH_MAC_KEYIDX
3947. B43_TXH_MAC_KEYIDX_SHIFT
3948. B43_TXH_MAC_LIFETIME
3949. B43_TXH_MAC_LONGFRAME
3950. B43_TXH_MAC_RIFS
3951. B43_TXH_MAC_RTS_FB_SHORTPRMBL
3952. B43_TXH_MAC_RTS_SHORTPRMBL
3953. B43_TXH_MAC_SENDCTS
3954. B43_TXH_MAC_SENDRTS
3955. B43_TXH_MAC_STMSDU
3956. B43_TXH_MAC_USEFBR
3957. B43_TXH_PHY1_BW
3958. B43_TXH_PHY1_BW_10
3959. B43_TXH_PHY1_BW_10U
3960. B43_TXH_PHY1_BW_20
3961. B43_TXH_PHY1_BW_20U
3962. B43_TXH_PHY1_BW_40
3963. B43_TXH_PHY1_BW_40DUP
3964. B43_TXH_PHY1_CRATE
3965. B43_TXH_PHY1_CRATE_1_2
3966. B43_TXH_PHY1_CRATE_2_3
3967. B43_TXH_PHY1_CRATE_3_4
3968. B43_TXH_PHY1_CRATE_4_5
3969. B43_TXH_PHY1_CRATE_5_6
3970. B43_TXH_PHY1_CRATE_7_8
3971. B43_TXH_PHY1_MODE
3972. B43_TXH_PHY1_MODE_CDD
3973. B43_TXH_PHY1_MODE_SDM
3974. B43_TXH_PHY1_MODE_SISO
3975. B43_TXH_PHY1_MODE_STBC
3976. B43_TXH_PHY1_MODUL
3977. B43_TXH_PHY1_MODUL_BPSK
3978. B43_TXH_PHY1_MODUL_QAM16
3979. B43_TXH_PHY1_MODUL_QAM256
3980. B43_TXH_PHY1_MODUL_QAM64
3981. B43_TXH_PHY1_MODUL_QPSK
3982. B43_TXH_PHY_ANT
3983. B43_TXH_PHY_ANT0
3984. B43_TXH_PHY_ANT01AUTO
3985. B43_TXH_PHY_ANT1
3986. B43_TXH_PHY_ANT2
3987. B43_TXH_PHY_ANT3
3988. B43_TXH_PHY_ENC
3989. B43_TXH_PHY_ENC_CCK
3990. B43_TXH_PHY_ENC_HT
3991. B43_TXH_PHY_ENC_OFDM
3992. B43_TXH_PHY_ENC_VHT
3993. B43_TXH_PHY_SHORTPRMBL
3994. B43_TXH_PHY_TXPWR
3995. B43_TXH_PHY_TXPWR_SHIFT
3996. B43_TXPWR_IGNORE_TIME
3997. B43_TXPWR_IGNORE_TSSI
3998. B43_TXPWR_RES_DONE
3999. B43_TXPWR_RES_NEED_ADJUST
4000. B43_TXRING_SLOTS
4001. B43_TXST_SUPP_ABNACK
4002. B43_TXST_SUPP_CHAN
4003. B43_TXST_SUPP_FLUSH
4004. B43_TXST_SUPP_LIFE
4005. B43_TXST_SUPP_NONE
4006. B43_TXST_SUPP_PMQ
4007. B43_TXST_SUPP_PREV
4008. B43_TXST_SUPP_UNDER
4009. B43_VERBOSITY_DEBUG
4010. B43_VERBOSITY_DEFAULT
4011. B43_VERBOSITY_ERROR
4012. B43_VERBOSITY_INFO
4013. B43_VERBOSITY_MAX
4014. B43_VERBOSITY_WARN
4015. B43_WARN_ON
4016. B43_WATCHDOG_REG
4017. B43_WA_H_
4018. B43_XMIT_H_
4019. B43legacy_ANTENNA0
4020. B43legacy_ANTENNA1
4021. B43legacy_ANTENNA_AUTO
4022. B43legacy_ANTENNA_AUTO0
4023. B43legacy_ANTENNA_AUTO1
4024. B43legacy_ANTENNA_DEFAULT
4025. B43legacy_BFL_EXTLNA
4026. B43legacy_BFL_PACTRL
4027. B43legacy_BFL_RSSI
4028. B43legacy_BUG_ON
4029. B43legacy_CCK_RATE_11MB
4030. B43legacy_CCK_RATE_1MB
4031. B43legacy_CCK_RATE_2MB
4032. B43legacy_CCK_RATE_5MB
4033. B43legacy_CIR_BASE
4034. B43legacy_CIR_SBIMCONFIGLOW
4035. B43legacy_CIR_SBIMSTATE
4036. B43legacy_CIR_SBINTVEC
4037. B43legacy_CIR_SBTMSTATEHIGH
4038. B43legacy_CIR_SBTMSTATELOW
4039. B43legacy_CIR_SBTPSFLAG
4040. B43legacy_CIR_SB_ID_HI
4041. B43legacy_DBG_DMAOVERFLOW
4042. B43legacy_DBG_DMAVERBOSE
4043. B43legacy_DBG_PWORK_FAST
4044. B43legacy_DBG_PWORK_STOP
4045. B43legacy_DBG_XMITPOWER
4046. B43legacy_DEBUG
4047. B43legacy_DEBUGFS_FOPS
4048. B43legacy_DEBUGFS_H_
4049. B43legacy_DEFAULT_LONG_RETRY_LIMIT
4050. B43legacy_DEFAULT_SHORT_RETRY_LIMIT
4051. B43legacy_DMA0_RX_BUFFERSIZE
4052. B43legacy_DMA0_RX_FRAMEOFFSET
4053. B43legacy_DMA32_DCTL_ADDREXT_MASK
4054. B43legacy_DMA32_DCTL_ADDREXT_SHIFT
4055. B43legacy_DMA32_DCTL_BYTECNT
4056. B43legacy_DMA32_DCTL_DTABLEEND
4057. B43legacy_DMA32_DCTL_FRAMEEND
4058. B43legacy_DMA32_DCTL_FRAMESTART
4059. B43legacy_DMA32_DCTL_IRQ
4060. B43legacy_DMA32_RXACTIVE
4061. B43legacy_DMA32_RXADDREXT_MASK
4062. B43legacy_DMA32_RXADDREXT_SHIFT
4063. B43legacy_DMA32_RXCTL
4064. B43legacy_DMA32_RXDIRECTFIFO
4065. B43legacy_DMA32_RXDPTR
4066. B43legacy_DMA32_RXENABLE
4067. B43legacy_DMA32_RXERROR
4068. B43legacy_DMA32_RXERR_BUFWRITE
4069. B43legacy_DMA32_RXERR_DESCREAD
4070. B43legacy_DMA32_RXERR_NOERR
4071. B43legacy_DMA32_RXERR_OVERFLOW
4072. B43legacy_DMA32_RXERR_PROT
4073. B43legacy_DMA32_RXFROFF_MASK
4074. B43legacy_DMA32_RXFROFF_SHIFT
4075. B43legacy_DMA32_RXINDEX
4076. B43legacy_DMA32_RXRING
4077. B43legacy_DMA32_RXSTATE
4078. B43legacy_DMA32_RXSTATUS
4079. B43legacy_DMA32_RXSTAT_ACTIVE
4080. B43legacy_DMA32_RXSTAT_DISABLED
4081. B43legacy_DMA32_RXSTAT_IDLEWAIT
4082. B43legacy_DMA32_RXSTAT_STOPPED
4083. B43legacy_DMA32_TXACTIVE
4084. B43legacy_DMA32_TXADDREXT_MASK
4085. B43legacy_DMA32_TXADDREXT_SHIFT
4086. B43legacy_DMA32_TXCTL
4087. B43legacy_DMA32_TXDPTR
4088. B43legacy_DMA32_TXENABLE
4089. B43legacy_DMA32_TXERROR
4090. B43legacy_DMA32_TXERR_BUFREAD
4091. B43legacy_DMA32_TXERR_DESCREAD
4092. B43legacy_DMA32_TXERR_NOERR
4093. B43legacy_DMA32_TXERR_PROT
4094. B43legacy_DMA32_TXERR_UNDERRUN
4095. B43legacy_DMA32_TXFLUSH
4096. B43legacy_DMA32_TXINDEX
4097. B43legacy_DMA32_TXLOOPBACK
4098. B43legacy_DMA32_TXRING
4099. B43legacy_DMA32_TXSTATE
4100. B43legacy_DMA32_TXSTATUS
4101. B43legacy_DMA32_TXSTAT_ACTIVE
4102. B43legacy_DMA32_TXSTAT_DISABLED
4103. B43legacy_DMA32_TXSTAT_IDLEWAIT
4104. B43legacy_DMA32_TXSTAT_STOPPED
4105. B43legacy_DMA32_TXSTAT_SUSP
4106. B43legacy_DMA32_TXSUSPEND
4107. B43legacy_DMA3_RX_BUFFERSIZE
4108. B43legacy_DMA3_RX_FRAMEOFFSET
4109. B43legacy_DMAIRQ_FATALMASK
4110. B43legacy_DMAIRQ_NONFATALMASK
4111. B43legacy_DMAIRQ_RX_DONE
4112. B43legacy_DMA_30BIT
4113. B43legacy_DMA_32BIT
4114. B43legacy_DMA_H_
4115. B43legacy_DMA_RINGMEMSIZE
4116. B43legacy_FW_TYPE_IV
4117. B43legacy_FW_TYPE_PCM
4118. B43legacy_FW_TYPE_UCODE
4119. B43legacy_GPIO_CONTROL
4120. B43legacy_HF_EDCF
4121. B43legacy_HF_GDCW
4122. B43legacy_HF_OFDMPABOOST
4123. B43legacy_HF_SYMW
4124. B43legacy_H_
4125. B43legacy_ILT_FINEFREQA_SIZE
4126. B43legacy_ILT_FINEFREQG_SIZE
4127. B43legacy_ILT_H_
4128. B43legacy_ILT_NOISEA2_SIZE
4129. B43legacy_ILT_NOISEA3_SIZE
4130. B43legacy_ILT_NOISEG1_SIZE
4131. B43legacy_ILT_NOISEG2_SIZE
4132. B43legacy_ILT_NOISESCALEG_SIZE
4133. B43legacy_ILT_RETARD_SIZE
4134. B43legacy_ILT_ROTOR_SIZE
4135. B43legacy_ILT_SIGMASQR_SIZE
4136. B43legacy_INTERFMODE_AUTOWLAN
4137. B43legacy_INTERFMODE_MANUALWLAN
4138. B43legacy_INTERFMODE_NONE
4139. B43legacy_INTERFMODE_NONWLAN
4140. B43legacy_INTERFSTACK_SIZE
4141. B43legacy_IRQWAIT_MAX_RETRIES
4142. B43legacy_IRQ_ALL
4143. B43legacy_IRQ_ATIM_END
4144. B43legacy_IRQ_BEACON
4145. B43legacy_IRQ_BEACON_CANCEL
4146. B43legacy_IRQ_BEACON_TX_OK
4147. B43legacy_IRQ_CCA_MEASURE_OK
4148. B43legacy_IRQ_DMA
4149. B43legacy_IRQ_MAC_SUSPENDED
4150. B43legacy_IRQ_MAC_TXERR
4151. B43legacy_IRQ_MASKTEMPLATE
4152. B43legacy_IRQ_NOISESAMPLE_OK
4153. B43legacy_IRQ_PHY_G_CHANGED
4154. B43legacy_IRQ_PHY_TXERR
4155. B43legacy_IRQ_PIO_WORKAROUND
4156. B43legacy_IRQ_PMEVENT
4157. B43legacy_IRQ_PMQ
4158. B43legacy_IRQ_RFKILL
4159. B43legacy_IRQ_TBTT_INDI
4160. B43legacy_IRQ_TIMEOUT
4161. B43legacy_IRQ_TIMER0
4162. B43legacy_IRQ_TIMER1
4163. B43legacy_IRQ_TXFIFO_FLUSH_OK
4164. B43legacy_IRQ_TX_OK
4165. B43legacy_IRQ_UCODE_DEBUG
4166. B43legacy_IV_32BIT
4167. B43legacy_IV_OFFSET_MASK
4168. B43legacy_LEDS_H_
4169. B43legacy_LED_ACTIVELOW
4170. B43legacy_LED_ACTIVITY
4171. B43legacy_LED_APTRANSFER
4172. B43legacy_LED_ASSOC
4173. B43legacy_LED_BEHAVIOUR
4174. B43legacy_LED_INACTIVE
4175. B43legacy_LED_MAX_NAME_LEN
4176. B43legacy_LED_MODE_BG
4177. B43legacy_LED_OFF
4178. B43legacy_LED_ON
4179. B43legacy_LED_RADIO_A
4180. B43legacy_LED_RADIO_ALL
4181. B43legacy_LED_RADIO_B
4182. B43legacy_LED_TRANSFER
4183. B43legacy_LED_WEIRD
4184. B43legacy_LO_COUNT
4185. B43legacy_MACCMD_BEACON0_VALID
4186. B43legacy_MACCMD_BEACON1_VALID
4187. B43legacy_MACCMD_BGNOISE
4188. B43legacy_MACCMD_CCA
4189. B43legacy_MACCMD_DFQ_VALID
4190. B43legacy_MACCTL_AP
4191. B43legacy_MACCTL_AWAKE
4192. B43legacy_MACCTL_BE
4193. B43legacy_MACCTL_BEACPROMISC
4194. B43legacy_MACCTL_ENABLED
4195. B43legacy_MACCTL_GMODE
4196. B43legacy_MACCTL_HWPS
4197. B43legacy_MACCTL_IHR_ENABLED
4198. B43legacy_MACCTL_INFRA
4199. B43legacy_MACCTL_KEEP_BAD
4200. B43legacy_MACCTL_KEEP_BADPLCP
4201. B43legacy_MACCTL_KEEP_CTL
4202. B43legacy_MACCTL_PROMISC
4203. B43legacy_MACCTL_PSM_JMP0
4204. B43legacy_MACCTL_PSM_RUN
4205. B43legacy_MACCTL_RADIOLOCK
4206. B43legacy_MACCTL_SHM_ENABLED
4207. B43legacy_MACCTL_TBTTHOLD
4208. B43legacy_MACFILTER_BSSID
4209. B43legacy_MACFILTER_MAC
4210. B43legacy_MACFILTER_SELF
4211. B43legacy_MAIN_H_
4212. B43legacy_MMIO_ANTENNA
4213. B43legacy_MMIO_CHANNEL
4214. B43legacy_MMIO_CHANNEL_EXT
4215. B43legacy_MMIO_DMA0_IRQ_MASK
4216. B43legacy_MMIO_DMA0_REASON
4217. B43legacy_MMIO_DMA1_IRQ_MASK
4218. B43legacy_MMIO_DMA1_REASON
4219. B43legacy_MMIO_DMA2_IRQ_MASK
4220. B43legacy_MMIO_DMA2_REASON
4221. B43legacy_MMIO_DMA32_BASE0
4222. B43legacy_MMIO_DMA32_BASE1
4223. B43legacy_MMIO_DMA32_BASE2
4224. B43legacy_MMIO_DMA32_BASE3
4225. B43legacy_MMIO_DMA32_BASE4
4226. B43legacy_MMIO_DMA32_BASE5
4227. B43legacy_MMIO_DMA3_IRQ_MASK
4228. B43legacy_MMIO_DMA3_REASON
4229. B43legacy_MMIO_DMA4_IRQ_MASK
4230. B43legacy_MMIO_DMA4_REASON
4231. B43legacy_MMIO_DMA5_IRQ_MASK
4232. B43legacy_MMIO_DMA5_REASON
4233. B43legacy_MMIO_DMA64_BASE0
4234. B43legacy_MMIO_DMA64_BASE1
4235. B43legacy_MMIO_DMA64_BASE2
4236. B43legacy_MMIO_DMA64_BASE3
4237. B43legacy_MMIO_DMA64_BASE4
4238. B43legacy_MMIO_DMA64_BASE5
4239. B43legacy_MMIO_GEN_IRQ_MASK
4240. B43legacy_MMIO_GEN_IRQ_REASON
4241. B43legacy_MMIO_GPIO_CONTROL
4242. B43legacy_MMIO_GPIO_MASK
4243. B43legacy_MMIO_MACCMD
4244. B43legacy_MMIO_MACCTL
4245. B43legacy_MMIO_MACFILTER_CONTROL
4246. B43legacy_MMIO_MACFILTER_DATA
4247. B43legacy_MMIO_PHY0
4248. B43legacy_MMIO_PHY_CONTROL
4249. B43legacy_MMIO_PHY_DATA
4250. B43legacy_MMIO_PHY_RADIO
4251. B43legacy_MMIO_PHY_VER
4252. B43legacy_MMIO_PIO1_BASE
4253. B43legacy_MMIO_PIO2_BASE
4254. B43legacy_MMIO_PIO3_BASE
4255. B43legacy_MMIO_PIO4_BASE
4256. B43legacy_MMIO_POWERUP_DELAY
4257. B43legacy_MMIO_PS_STATUS
4258. B43legacy_MMIO_RADIO_CONTROL
4259. B43legacy_MMIO_RADIO_DATA_HIGH
4260. B43legacy_MMIO_RADIO_DATA_LOW
4261. B43legacy_MMIO_RADIO_HWENABLED_HI
4262. B43legacy_MMIO_RADIO_HWENABLED_HI_MASK
4263. B43legacy_MMIO_RADIO_HWENABLED_LO
4264. B43legacy_MMIO_RADIO_HWENABLED_LO_MASK
4265. B43legacy_MMIO_RAM_CONTROL
4266. B43legacy_MMIO_RAM_DATA
4267. B43legacy_MMIO_RCMTA_COUNT
4268. B43legacy_MMIO_REV3PLUS_TSF_HIGH
4269. B43legacy_MMIO_REV3PLUS_TSF_LOW
4270. B43legacy_MMIO_RNG
4271. B43legacy_MMIO_SHM_CONTROL
4272. B43legacy_MMIO_SHM_DATA
4273. B43legacy_MMIO_SHM_DATA_UNALIGNED
4274. B43legacy_MMIO_TSF_0
4275. B43legacy_MMIO_TSF_1
4276. B43legacy_MMIO_TSF_2
4277. B43legacy_MMIO_TSF_3
4278. B43legacy_MMIO_TSF_CFP_PRETBTT
4279. B43legacy_MMIO_TSF_CFP_REP
4280. B43legacy_MMIO_TSF_CFP_START
4281. B43legacy_MMIO_XMITSTAT_0
4282. B43legacy_MMIO_XMITSTAT_1
4283. B43legacy_NR_LOGGED_TXSTATUS
4284. B43legacy_NR_QOSPARMS
4285. B43legacy_OFDMTAB
4286. B43legacy_OFDMTAB_ADVRETARD
4287. B43legacy_OFDMTAB_AGC1
4288. B43legacy_OFDMTAB_AGC1_R1
4289. B43legacy_OFDMTAB_AGC2
4290. B43legacy_OFDMTAB_AGC3
4291. B43legacy_OFDMTAB_AGC3_R1
4292. B43legacy_OFDMTAB_DAC
4293. B43legacy_OFDMTAB_DACOFF
4294. B43legacy_OFDMTAB_DACRFPABB
4295. B43legacy_OFDMTAB_DC
4296. B43legacy_OFDMTAB_DCBIAS
4297. B43legacy_OFDMTAB_GAIN0
4298. B43legacy_OFDMTAB_GAIN1
4299. B43legacy_OFDMTAB_GAIN2
4300. B43legacy_OFDMTAB_GAINX
4301. B43legacy_OFDMTAB_GAINX_R1
4302. B43legacy_OFDMTAB_LNAGAIN
4303. B43legacy_OFDMTAB_LNAHPFGAIN1
4304. B43legacy_OFDMTAB_LNAHPFGAIN2
4305. B43legacy_OFDMTAB_LPFGAIN
4306. B43legacy_OFDMTAB_MINSIGSQ
4307. B43legacy_OFDMTAB_NOISESCALE
4308. B43legacy_OFDMTAB_PWRDYN2
4309. B43legacy_OFDMTAB_ROTOR
4310. B43legacy_OFDMTAB_RSSI
4311. B43legacy_OFDMTAB_TSSI
4312. B43legacy_OFDMTAB_WRSSI
4313. B43legacy_OFDMTAB_WRSSI_R1
4314. B43legacy_OFDM_RATE_12MB
4315. B43legacy_OFDM_RATE_18MB
4316. B43legacy_OFDM_RATE_24MB
4317. B43legacy_OFDM_RATE_36MB
4318. B43legacy_OFDM_RATE_48MB
4319. B43legacy_OFDM_RATE_54MB
4320. B43legacy_OFDM_RATE_6MB
4321. B43legacy_OFDM_RATE_9MB
4322. B43legacy_PHYMODE
4323. B43legacy_PHYMODE_B
4324. B43legacy_PHYMODE_G
4325. B43legacy_PHYROUTE_EXT_GPHY
4326. B43legacy_PHYROUTE_OFDM_GPHY
4327. B43legacy_PHYTYPE_B
4328. B43legacy_PHYTYPE_G
4329. B43legacy_PHYVER_ANALOG
4330. B43legacy_PHYVER_ANALOG_SHIFT
4331. B43legacy_PHYVER_TYPE
4332. B43legacy_PHYVER_TYPE_SHIFT
4333. B43legacy_PHYVER_VERSION
4334. B43legacy_PHY_ADIVRELATED
4335. B43legacy_PHY_ANTDWELL
4336. B43legacy_PHY_ANTDWELL_AUTODIV1
4337. B43legacy_PHY_ANTWRSETT
4338. B43legacy_PHY_ANTWRSETT_ARXDIV
4339. B43legacy_PHY_BASE
4340. B43legacy_PHY_BBANDCFG
4341. B43legacy_PHY_BBANDCFG_RXANT
4342. B43legacy_PHY_BBANDCFG_RXANT_SHIFT
4343. B43legacy_PHY_CLASSCTL
4344. B43legacy_PHY_CLIPN1P2THRES
4345. B43legacy_PHY_CLIPP2THRES
4346. B43legacy_PHY_CLIPP3THRES
4347. B43legacy_PHY_CLIPPWRDOWNT
4348. B43legacy_PHY_CLIPTHRES
4349. B43legacy_PHY_CRS0
4350. B43legacy_PHY_CRSTHRES1
4351. B43legacy_PHY_CRSTHRES1_R1
4352. B43legacy_PHY_CRSTHRES2_R1
4353. B43legacy_PHY_DC_LTBASE
4354. B43legacy_PHY_DIVP1P2GAIN
4355. B43legacy_PHY_DIVSRCHGAINBACK
4356. B43legacy_PHY_DIVSRCHGAINCHNG
4357. B43legacy_PHY_DIVSRCHIDX
4358. B43legacy_PHY_ENCORE
4359. B43legacy_PHY_ENCORE_EN
4360. B43legacy_PHY_EXTG
4361. B43legacy_PHY_GAIN_LTBASE
4362. B43legacy_PHY_GTABCTL
4363. B43legacy_PHY_GTABDATA
4364. B43legacy_PHY_GTABNR
4365. B43legacy_PHY_GTABNR_SHIFT
4366. B43legacy_PHY_GTABOFF
4367. B43legacy_PHY_G_CRS
4368. B43legacy_PHY_G_LO_CONTROL
4369. B43legacy_PHY_G_PCTL
4370. B43legacy_PHY_HPWR_TSSICTL
4371. B43legacy_PHY_H_
4372. B43legacy_PHY_ILT_G_CTRL
4373. B43legacy_PHY_ILT_G_DATA1
4374. B43legacy_PHY_ILT_G_DATA2
4375. B43legacy_PHY_IQBAL
4376. B43legacy_PHY_LMS
4377. B43legacy_PHY_LNAHPFCTL
4378. B43legacy_PHY_LO_CTL
4379. B43legacy_PHY_LO_MASK
4380. B43legacy_PHY_N1N2GAIN
4381. B43legacy_PHY_N1P1GAIN
4382. B43legacy_PHY_NRSSILT_CTRL
4383. B43legacy_PHY_NRSSILT_DATA
4384. B43legacy_PHY_NRSSITHRES
4385. B43legacy_PHY_OFDM
4386. B43legacy_PHY_OFDM61
4387. B43legacy_PHY_OFDM61_10
4388. B43legacy_PHY_OFDM9B
4389. B43legacy_PHY_OTABLECTL
4390. B43legacy_PHY_OTABLEI
4391. B43legacy_PHY_OTABLENR
4392. B43legacy_PHY_OTABLENR_SHIFT
4393. B43legacy_PHY_OTABLEOFF
4394. B43legacy_PHY_OTABLEQ
4395. B43legacy_PHY_P1P2GAIN
4396. B43legacy_PHY_PWRDOWN
4397. B43legacy_PHY_RADIO_BITFIELD
4398. B43legacy_PHY_RFOVER
4399. B43legacy_PHY_RFOVERVAL
4400. B43legacy_PHY_TSSIP_LTBASE
4401. B43legacy_PHY_TX_BADNESS_LIMIT
4402. B43legacy_PHY_VERSION_OFDM
4403. B43legacy_PIO_H_
4404. B43legacy_PIO_MAXTXDEVQPACKETS
4405. B43legacy_PIO_MAXTXPACKETS
4406. B43legacy_PIO_RXCTL
4407. B43legacy_PIO_RXCTL_DATAAVAILABLE
4408. B43legacy_PIO_RXCTL_READY
4409. B43legacy_PIO_RXDATA
4410. B43legacy_PIO_TXCTL
4411. B43legacy_PIO_TXCTL_COMPLETE
4412. B43legacy_PIO_TXCTL_INIT
4413. B43legacy_PIO_TXCTL_SUSPEND
4414. B43legacy_PIO_TXCTL_WRITEHI
4415. B43legacy_PIO_TXCTL_WRITELO
4416. B43legacy_PIO_TXDATA
4417. B43legacy_PIO_TXQADJUST
4418. B43legacy_PIO_TXQBUFSIZE
4419. B43legacy_QOSPARM_AIFS
4420. B43legacy_QOSPARM_BSLOTS
4421. B43legacy_QOSPARM_CWCUR
4422. B43legacy_QOSPARM_CWMAX
4423. B43legacy_QOSPARM_CWMIN
4424. B43legacy_QOSPARM_REGGAP
4425. B43legacy_QOSPARM_STATUS
4426. B43legacy_QOSPARM_TXOP
4427. B43legacy_QOS_QUEUE_NUM
4428. B43legacy_RADIOCTL_ID
4429. B43legacy_RADIO_DEFAULT_CHANNEL_BG
4430. B43legacy_RADIO_H_
4431. B43legacy_RADIO_INTERFMODE_AUTOWLAN
4432. B43legacy_RADIO_INTERFMODE_MANUALWLAN
4433. B43legacy_RADIO_INTERFMODE_NONE
4434. B43legacy_RADIO_INTERFMODE_NONWLAN
4435. B43legacy_RADIO_TXANTENNA_0
4436. B43legacy_RADIO_TXANTENNA_1
4437. B43legacy_RADIO_TXANTENNA_DEFAULT
4438. B43legacy_RADIO_TXANTENNA_LASTPLCP
4439. B43legacy_RATE_TO_100KBPS
4440. B43legacy_RFKILL_H_
4441. B43legacy_RXRING_SLOTS
4442. B43legacy_RX_CHAN_GAIN
4443. B43legacy_RX_CHAN_GAIN_SHIFT
4444. B43legacy_RX_CHAN_ID
4445. B43legacy_RX_CHAN_ID_SHIFT
4446. B43legacy_RX_CHAN_PHYTYPE
4447. B43legacy_RX_MAC_BEACONSENT
4448. B43legacy_RX_MAC_DEC
4449. B43legacy_RX_MAC_DECERR
4450. B43legacy_RX_MAC_FCSERR
4451. B43legacy_RX_MAC_KEYIDX
4452. B43legacy_RX_MAC_KEYIDX_SHIFT
4453. B43legacy_RX_MAC_PADDING
4454. B43legacy_RX_MAC_RESP
4455. B43legacy_RX_PHYST0_ANT
4456. B43legacy_RX_PHYST0_CCK
4457. B43legacy_RX_PHYST0_CLIP
4458. B43legacy_RX_PHYST0_CLIP_SHIFT
4459. B43legacy_RX_PHYST0_FTYPE
4460. B43legacy_RX_PHYST0_GAINCTL
4461. B43legacy_RX_PHYST0_LCRS
4462. B43legacy_RX_PHYST0_OFDM
4463. B43legacy_RX_PHYST0_PLCPFV
4464. B43legacy_RX_PHYST0_PLCPHCF
4465. B43legacy_RX_PHYST0_PRE_N
4466. B43legacy_RX_PHYST0_SHORTPRMBL
4467. B43legacy_RX_PHYST0_STD_N
4468. B43legacy_RX_PHYST0_UNSRATE
4469. B43legacy_RX_PHYST2_FOFF
4470. B43legacy_RX_PHYST2_LNAG
4471. B43legacy_RX_PHYST2_LNAG_SHIFT
4472. B43legacy_RX_PHYST2_PNAG
4473. B43legacy_RX_PHYST2_PNAG_SHIFT
4474. B43legacy_RX_PHYST3_DIGG
4475. B43legacy_RX_PHYST3_DIGG_SHIFT
4476. B43legacy_RX_PHYST3_TRSTATE
4477. B43legacy_SBIMSTATE_IB_ERROR
4478. B43legacy_SBIMSTATE_TIMEOUT
4479. B43legacy_SBTMSTATEHIGH_BISTCOMPLETE
4480. B43legacy_SBTMSTATEHIGH_BISTFAILED
4481. B43legacy_SBTMSTATEHIGH_BUSY
4482. B43legacy_SBTMSTATEHIGH_COREFLAGS
4483. B43legacy_SBTMSTATEHIGH_DMA64BIT
4484. B43legacy_SBTMSTATEHIGH_GATEDCLK
4485. B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL
4486. B43legacy_SBTMSTATEHIGH_SERROR
4487. B43legacy_SBTMSTATEHIGH_TIMEOUT
4488. B43legacy_SEC_ALGO_AES
4489. B43legacy_SEC_ALGO_AES_LEGACY
4490. B43legacy_SEC_ALGO_NONE
4491. B43legacy_SEC_ALGO_TKIP
4492. B43legacy_SEC_ALGO_WEP104
4493. B43legacy_SEC_ALGO_WEP40
4494. B43legacy_SEC_KEYSIZE
4495. B43legacy_SHM_AUTOINC_R
4496. B43legacy_SHM_AUTOINC_RW
4497. B43legacy_SHM_AUTOINC_W
4498. B43legacy_SHM_HW
4499. B43legacy_SHM_SHARED
4500. B43legacy_SHM_SH_ACKCTSPHYCTL
4501. B43legacy_SHM_SH_BEACPHYCTL
4502. B43legacy_SHM_SH_BTL0
4503. B43legacy_SHM_SH_BTL1
4504. B43legacy_SHM_SH_BTSFOFF
4505. B43legacy_SHM_SH_CCKBASIC
4506. B43legacy_SHM_SH_CCKDIRECT
4507. B43legacy_SHM_SH_DTIMP
4508. B43legacy_SHM_SH_HOSTFHI
4509. B43legacy_SHM_SH_HOSTFLO
4510. B43legacy_SHM_SH_KEYIDXBLOCK
4511. B43legacy_SHM_SH_OFDMBASIC
4512. B43legacy_SHM_SH_OFDMDIRECT
4513. B43legacy_SHM_SH_PRETBTT
4514. B43legacy_SHM_SH_PRMAXTIME
4515. B43legacy_SHM_SH_PRPHYCTL
4516. B43legacy_SHM_SH_PRTLEN
4517. B43legacy_SHM_SH_SPUWKUP
4518. B43legacy_SHM_SH_TIMPOS
4519. B43legacy_SHM_SH_UCODEDATE
4520. B43legacy_SHM_SH_UCODEPATCH
4521. B43legacy_SHM_SH_UCODEREV
4522. B43legacy_SHM_SH_UCODETIME
4523. B43legacy_SHM_SH_WLCOREREV
4524. B43legacy_SHM_UCODE
4525. B43legacy_SHM_WIRELESS
4526. B43legacy_STAT_INITIALIZED
4527. B43legacy_STAT_STARTED
4528. B43legacy_STAT_UNINIT
4529. B43legacy_SYSFS_H_
4530. B43legacy_TMSHIGH_FCLOCK
4531. B43legacy_TMSHIGH_GPHY
4532. B43legacy_TMSLOW_GMODE
4533. B43legacy_TMSLOW_MACPHYCLKEN
4534. B43legacy_TMSLOW_PHYCLKEN
4535. B43legacy_TMSLOW_PHYRESET
4536. B43legacy_TMSLOW_PLLREFSEL
4537. B43legacy_TX4_EFT_FBOFDM
4538. B43legacy_TX4_EFT_RTSFBOFDM
4539. B43legacy_TX4_EFT_RTSOFDM
4540. B43legacy_TX4_MAC_5GHZ
4541. B43legacy_TX4_MAC_ACK
4542. B43legacy_TX4_MAC_AMPDU
4543. B43legacy_TX4_MAC_AMPDU_SHIFT
4544. B43legacy_TX4_MAC_CTSFALLBACKOFDM
4545. B43legacy_TX4_MAC_FALLBACKOFDM
4546. B43legacy_TX4_MAC_FRAMEBURST
4547. B43legacy_TX4_MAC_HWSEQ
4548. B43legacy_TX4_MAC_IGNPMQ
4549. B43legacy_TX4_MAC_KEYALG
4550. B43legacy_TX4_MAC_KEYALG_SHIFT
4551. B43legacy_TX4_MAC_KEYIDX
4552. B43legacy_TX4_MAC_KEYIDX_SHIFT
4553. B43legacy_TX4_MAC_LIFETIME
4554. B43legacy_TX4_MAC_LONGFRAME
4555. B43legacy_TX4_MAC_SENDCTS
4556. B43legacy_TX4_MAC_SENDRTS
4557. B43legacy_TX4_MAC_STMSDU
4558. B43legacy_TX4_PHY_ANT
4559. B43legacy_TX4_PHY_ANT0
4560. B43legacy_TX4_PHY_ANT1
4561. B43legacy_TX4_PHY_ANTLAST
4562. B43legacy_TX4_PHY_ENC
4563. B43legacy_TX4_PHY_ENC_CCK
4564. B43legacy_TX4_PHY_ENC_OFDM
4565. B43legacy_TX4_PHY_SHORTPRMBL
4566. B43legacy_TXRING_SLOTS
4567. B43legacy_TXST_SUPP_ABNACK
4568. B43legacy_TXST_SUPP_CHAN
4569. B43legacy_TXST_SUPP_FLUSH
4570. B43legacy_TXST_SUPP_LIFE
4571. B43legacy_TXST_SUPP_NONE
4572. B43legacy_TXST_SUPP_PMQ
4573. B43legacy_TXST_SUPP_PREV
4574. B43legacy_TXST_SUPP_UNDER
4575. B43legacy_UCODEFLAGS_OFFSET
4576. B43legacy_UCODEFLAG_AUTODIV
4577. B43legacy_WARN_ON
4578. B43legacy_XMIT_H_
4579. B44_ADDR_HI
4580. B44_ADDR_LO
4581. B44_BIST_STAT
4582. B44_BOARDFLAG_ADM
4583. B44_BOARDFLAG_ROBO
4584. B44_CAM_CTRL
4585. B44_CAM_DATA_HI
4586. B44_CAM_DATA_LO
4587. B44_CHIP_RESET_FULL
4588. B44_CHIP_RESET_PARTIAL
4589. B44_DEF_MSG_ENABLE
4590. B44_DEF_RX_RING_PENDING
4591. B44_DEF_TX_RING_PENDING
4592. B44_DEVCTRL
4593. B44_DMAFIFO_AD
4594. B44_DMAFIFO_HI
4595. B44_DMAFIFO_LO
4596. B44_DMARX_ADDR
4597. B44_DMARX_CTRL
4598. B44_DMARX_PTR
4599. B44_DMARX_STAT
4600. B44_DMATX_ADDR
4601. B44_DMATX_CTRL
4602. B44_DMATX_PTR
4603. B44_DMATX_STAT
4604. B44_EMAC_IMASK
4605. B44_EMAC_ISTAT
4606. B44_ENET_CTRL
4607. B44_ETHIPV4UDP_HLEN
4608. B44_ETHIPV6UDP_HLEN
4609. B44_FILT_ADDR
4610. B44_FILT_DATA
4611. B44_FLAG_100_BASE_T
4612. B44_FLAG_ADV_100FULL
4613. B44_FLAG_ADV_100HALF
4614. B44_FLAG_ADV_10FULL
4615. B44_FLAG_ADV_10HALF
4616. B44_FLAG_B0_ANDLATER
4617. B44_FLAG_BUGGY_TXPTR
4618. B44_FLAG_EXTERNAL_PHY
4619. B44_FLAG_FORCE_LINK
4620. B44_FLAG_FULL_DUPLEX
4621. B44_FLAG_PAUSE_AUTO
4622. B44_FLAG_REORDER_BUG
4623. B44_FLAG_RX_PAUSE
4624. B44_FLAG_RX_RING_HACK
4625. B44_FLAG_TX_PAUSE
4626. B44_FLAG_TX_RING_HACK
4627. B44_FLAG_WOL_ENABLE
4628. B44_FULL_RESET
4629. B44_FULL_RESET_SKIP_PHY
4630. B44_GPTIMER
4631. B44_IMASK
4632. B44_ISTAT
4633. B44_MAC_CTRL
4634. B44_MAC_FLOW
4635. B44_MAX_MTU
4636. B44_MAX_PATTERNS
4637. B44_MCAST_TABLE_SIZE
4638. B44_MDC_RATIO
4639. B44_MDIO_CTRL
4640. B44_MDIO_DATA
4641. B44_MIB_CTRL
4642. B44_MII_ALEDCTRL
4643. B44_MII_AUXCTRL
4644. B44_MII_TLEDCTRL
4645. B44_MIN_MTU
4646. B44_PARTIAL_RESET
4647. B44_PATTERN_BASE
4648. B44_PATTERN_SIZE
4649. B44_PHY_ADDR_NO_LOCAL_PHY
4650. B44_PHY_ADDR_NO_PHY
4651. B44_PMASK_BASE
4652. B44_PMASK_SIZE
4653. B44_RCV_LAZY
4654. B44_RXBURST
4655. B44_RXCONFIG
4656. B44_RXMAXLEN
4657. B44_RX_1024_MAX
4658. B44_RX_128_255
4659. B44_RX_256_511
4660. B44_RX_512_1023
4661. B44_RX_64
4662. B44_RX_65_127
4663. B44_RX_ALIGN
4664. B44_RX_BCAST
4665. B44_RX_CRC
4666. B44_RX_CRCA
4667. B44_RX_FRAG
4668. B44_RX_GOOD_O
4669. B44_RX_GOOD_P
4670. B44_RX_JABBER
4671. B44_RX_MCAST
4672. B44_RX_MISS
4673. B44_RX_NPAUSE
4674. B44_RX_O
4675. B44_RX_OSIZE
4676. B44_RX_P
4677. B44_RX_PAUSE
4678. B44_RX_RING_BYTES
4679. B44_RX_RING_SIZE
4680. B44_RX_SYM
4681. B44_RX_USIZE
4682. B44_STAT_REG_DECLARE
4683. B44_TXBURST
4684. B44_TXMAXLEN
4685. B44_TX_1024_MAX
4686. B44_TX_128_255
4687. B44_TX_256_511
4688. B44_TX_512_1023
4689. B44_TX_64
4690. B44_TX_65_127
4691. B44_TX_BCAST
4692. B44_TX_CLOST
4693. B44_TX_CTRL
4694. B44_TX_DEFERED
4695. B44_TX_ECOLS
4696. B44_TX_FRAG
4697. B44_TX_GOOD_O
4698. B44_TX_GOOD_P
4699. B44_TX_JABBER
4700. B44_TX_LCOLS
4701. B44_TX_MCAST
4702. B44_TX_MCOLS
4703. B44_TX_O
4704. B44_TX_OSIZE
4705. B44_TX_P
4706. B44_TX_PAUSE
4707. B44_TX_RING_BYTES
4708. B44_TX_RING_SIZE
4709. B44_TX_SCOLS
4710. B44_TX_TCOLS
4711. B44_TX_TIMEOUT
4712. B44_TX_URUNS
4713. B44_TX_WAKEUP_THRESH
4714. B44_TX_WMARK
4715. B44_WKUP_LEN
4716. B460800
4717. B4800
4718. B4_R1_AC
4719. B4_R1_AC_H
4720. B4_R1_BC
4721. B4_R1_CSR
4722. B4_R1_D
4723. B4_R1_DA
4724. B4_R1_DA_H
4725. B4_R1_F
4726. B4_R1_T1
4727. B4_R1_T1_RD
4728. B4_R1_T1_SV
4729. B4_R1_T1_TR
4730. B4_R1_T1_WR
4731. B4_R1_T2
4732. B4_R1_T3
4733. B4_R2_AC
4734. B4_R2_BC
4735. B4_R2_CSR
4736. B4_R2_D
4737. B4_R2_DA
4738. B4_R2_F
4739. B4_R2_T1
4740. B4_R2_T1_RD
4741. B4_R2_T1_SV
4742. B4_R2_T1_TR
4743. B4_R2_T1_WR
4744. B4_R2_T2
4745. B4_R2_T3
4746. B5
4747. B50
4748. B500000
4749. B53_802_1P_EN
4750. B53_ALL_PORT_PAGE
4751. B53_ARLCTRL_PAGE
4752. B53_ARLIO_PAGE
4753. B53_ARLTBL_DATA_ENTRY
4754. B53_ARLTBL_MAC_VID_ENTRY
4755. B53_ARLTBL_MAX_BIN_ENTRIES
4756. B53_ARLTBL_RW_CTRL
4757. B53_ARL_SRCH_ADDR
4758. B53_ARL_SRCH_ADDR_25
4759. B53_ARL_SRCH_ADDR_65
4760. B53_ARL_SRCH_CTL
4761. B53_ARL_SRCH_CTL_25
4762. B53_ARL_SRCH_RSTL
4763. B53_ARL_SRCH_RSTL_0
4764. B53_ARL_SRCH_RSTL_0_MACVID
4765. B53_ARL_SRCH_RSTL_0_MACVID_25
4766. B53_ARL_SRCH_RSTL_0_MACVID_65
4767. B53_ARL_SRCH_RSTL_MACVID
4768. B53_BRCM_HDR
4769. B53_BRCM_HDR_RX_DIS
4770. B53_BRCM_HDR_TX_DIS
4771. B53_BRCM_OUI_1
4772. B53_BRCM_OUI_2
4773. B53_BRCM_OUI_3
4774. B53_BRCM_OUI_4
4775. B53_CFP_CTRL
4776. B53_CFP_PAGE
4777. B53_CPU_PORT
4778. B53_CPU_PORT_25
4779. B53_CTRL_PAGE
4780. B53_DEVICE_ID
4781. B53_DUPLEX_STAT_63XX
4782. B53_DUPLEX_STAT_FE
4783. B53_DUPLEX_STAT_GE
4784. B53_EEE_EN_CTRL
4785. B53_EEE_LPI_ASSERT_STS
4786. B53_EEE_LPI_INDICATE
4787. B53_EEE_MIN_LP_TIMER_FE
4788. B53_EEE_MIN_LP_TIMER_GIG
4789. B53_EEE_PAGE
4790. B53_EEE_PIP_TIMER
4791. B53_EEE_RX_IDLE_SYM_STS
4792. B53_EEE_SLEEP_TIMER_FE
4793. B53_EEE_SLEEP_TIMER_GIG
4794. B53_EEE_WAKE_TIMER_FE
4795. B53_EEE_WAKE_TIMER_GIG
4796. B53_EG_MIR_CTL
4797. B53_EG_MIR_DIV
4798. B53_EG_MIR_MAC
4799. B53_FAST_AGE_CTRL
4800. B53_FAST_AGE_PORT_CTRL
4801. B53_FAST_AGE_VID_CTRL
4802. B53_FRAMEBUF_PAGE
4803. B53_GLOBAL_CONFIG
4804. B53_GMII_PORT_OVERRIDE_CTRL
4805. B53_IG_MIR_CTL
4806. B53_IG_MIR_DIV
4807. B53_IG_MIR_MAC
4808. B53_IM_PORT_PAGE
4809. B53_INVALID_LANE
4810. B53_IPMC_FLOOD_MASK
4811. B53_IPMC_FWD_EN
4812. B53_IP_MULTICAST_CTRL
4813. B53_JOIN_ALL_VLAN_EN
4814. B53_JUMBO_MAX_SIZE
4815. B53_JUMBO_MAX_SIZE_63XX
4816. B53_JUMBO_PAGE
4817. B53_JUMBO_PORT_MASK
4818. B53_JUMBO_PORT_MASK_63XX
4819. B53_LINK_STAT
4820. B53_LINK_STAT_CHANGE
4821. B53_MAC_ADDR_IDX
4822. B53_MC_FLOOD_MASK
4823. B53_MC_FWD_EN
4824. B53_MEM_ACCESS_PAGE
4825. B53_MGMT_PAGE
4826. B53_MIBS_58XX_SIZE
4827. B53_MIBS_63XX_SIZE
4828. B53_MIBS_65_SIZE
4829. B53_MIBS_SIZE
4830. B53_MIB_AC_PAGE
4831. B53_MIB_PAGE
4832. B53_MII_DUMB_FWDG_EN
4833. B53_MIR_CAP_CTL
4834. B53_MUX_CONFIG_P4
4835. B53_MUX_CONFIG_P5
4836. B53_N_PORTS
4837. B53_N_PORTS_25
4838. B53_PD_MODE_CTRL_25
4839. B53_PORT_CTRL
4840. B53_PORT_MII_PAGE
4841. B53_PORT_OVERRIDE_CTRL
4842. B53_PVLAN_PAGE
4843. B53_PVLAN_PORT_MASK
4844. B53_QOS_GLOBAL_CTL
4845. B53_QOS_PAGE
4846. B53_RAC_FLUSH_REG
4847. B53_REV_ID
4848. B53_REV_ID_25
4849. B53_RGMII_CTRL_IMP
4850. B53_RGMII_CTRL_P
4851. B53_SERDES_BLKADDR
4852. B53_SERDES_DIGITAL_CONTROL
4853. B53_SERDES_DIGITAL_STATUS
4854. B53_SERDES_ID0
4855. B53_SERDES_LANE
4856. B53_SERDES_MII_REG
4857. B53_SERDES_PAGE
4858. B53_SMP_CTRL
4859. B53_SOFTRESET
4860. B53_SPEED_STAT
4861. B53_SPI_CMD_FAST
4862. B53_SPI_CMD_NORMAL
4863. B53_SPI_CMD_RACK
4864. B53_SPI_CMD_READ
4865. B53_SPI_CMD_SPIF
4866. B53_SPI_CMD_WRITE
4867. B53_SPI_DATA
4868. B53_SPI_PAGE_SELECT
4869. B53_SPI_STATUS
4870. B53_SRAB_1588_SYNC
4871. B53_SRAB_CMDSTAT
4872. B53_SRAB_CMDSTAT_GORDYN
4873. B53_SRAB_CMDSTAT_PAGE
4874. B53_SRAB_CMDSTAT_REG
4875. B53_SRAB_CMDSTAT_RST
4876. B53_SRAB_CMDSTAT_WRITE
4877. B53_SRAB_CTRLS
4878. B53_SRAB_CTRLS_HOST_INTR
4879. B53_SRAB_CTRLS_RCAGNT
4880. B53_SRAB_CTRLS_RCAREQ
4881. B53_SRAB_CTRLS_SW_INIT_DONE
4882. B53_SRAB_IMP0_SLEEP_TIMER
4883. B53_SRAB_IMP1_SLEEP_TIMER
4884. B53_SRAB_INTR
4885. B53_SRAB_INTR_P
4886. B53_SRAB_P7_SLEEP_TIMER
4887. B53_SRAB_RD_H
4888. B53_SRAB_RD_L
4889. B53_SRAB_SWITCH_PHY
4890. B53_SRAB_WD_H
4891. B53_SRAB_WD_L
4892. B53_STAT_PAGE
4893. B53_STRAP_VALUE
4894. B53_SWITCH_CTRL
4895. B53_SWITCH_MODE
4896. B53_UC_FLOOD_MASK
4897. B53_UC_FWD_EN
4898. B53_VLAN_CTRL0
4899. B53_VLAN_CTRL1
4900. B53_VLAN_CTRL2
4901. B53_VLAN_CTRL3
4902. B53_VLAN_CTRL3_63XX
4903. B53_VLAN_CTRL4
4904. B53_VLAN_CTRL4_25
4905. B53_VLAN_CTRL4_63XX
4906. B53_VLAN_CTRL5
4907. B53_VLAN_CTRL5_25
4908. B53_VLAN_CTRL5_63XX
4909. B53_VLAN_CTRL6
4910. B53_VLAN_CTRL6_63XX
4911. B53_VLAN_ID_IDX
4912. B53_VLAN_PAGE
4913. B53_VLAN_PORT_DEF_TAG
4914. B53_VLAN_READ
4915. B53_VLAN_TABLE_ACCESS_25
4916. B53_VLAN_TABLE_ACCESS_65
4917. B53_VLAN_WRITE_25
4918. B53_VLAN_WRITE_65
4919. B53_VTA_REGS
4920. B53_VTA_REGS_63XX
4921. B53_VTA_REGS_9798
4922. B53_VT_ACCESS
4923. B53_VT_ACCESS_63XX
4924. B53_VT_ACCESS_9798
4925. B53_VT_ENTRY
4926. B53_VT_ENTRY_63XX
4927. B53_VT_ENTRY_9798
4928. B53_VT_INDEX
4929. B53_VT_INDEX_63XX
4930. B53_VT_INDEX_9798
4931. B57600
4932. B576000
4933. B577XX_DOORBELL_HDR_CONN_TYPE
4934. B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT
4935. B577XX_DOORBELL_HDR_DB_TYPE
4936. B577XX_DOORBELL_HDR_DB_TYPE_SHIFT
4937. B577XX_DOORBELL_HDR_DPM_SIZE
4938. B577XX_DOORBELL_HDR_DPM_SIZE_SHIFT
4939. B577XX_DOORBELL_HDR_RX
4940. B577XX_DOORBELL_HDR_RX_SHIFT
4941. B577XX_FCOE_CONNECTION_TYPE
4942. B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM
4943. B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM_SHIFT
4944. B577XX_FCOE_RX_DOORBELL_OPCODE
4945. B577XX_FCOE_RX_DOORBELL_OPCODE_SHIFT
4946. B577XX_ISCSI_CONNECTION_TYPE
4947. B5GPAPEPOLARITY
4948. B5_XA_AC
4949. B5_XA_AC_H
4950. B5_XA_BC
4951. B5_XA_CSR
4952. B5_XA_D
4953. B5_XA_DA
4954. B5_XA_DA_H
4955. B5_XA_F
4956. B5_XA_T1
4957. B5_XA_T1_RD
4958. B5_XA_T1_SV
4959. B5_XA_T1_TR
4960. B5_XA_T1_WR
4961. B5_XA_T2
4962. B5_XA_T3
4963. B5_XS_AC
4964. B5_XS_AC_H
4965. B5_XS_BC
4966. B5_XS_CSR
4967. B5_XS_D
4968. B5_XS_DA
4969. B5_XS_DA_H
4970. B5_XS_F
4971. B5_XS_T1
4972. B5_XS_T1_RD
4973. B5_XS_T1_SV
4974. B5_XS_T1_TR
4975. B5_XS_T1_WR
4976. B5_XS_T2
4977. B5_XS_T3
4978. B6
4979. B600
4980. B614400
4981. B6_EXT_REG
4982. B7
4983. B75
4984. B76800
4985. B7_CFG_SPC
4986. B8
4987. B80MCLKDELAY
4988. B8_Q_REGS
4989. B8_RQ1_REGS
4990. B8_RQ2_REGS
4991. B8_TA1_REGS
4992. B8_TA2_REGS
4993. B8_TS1_REGS
4994. B8_TS2_REGS
4995. B9
4996. B921600
4997. B9600
4998. BA
4999. BA0_ACCAD
5000. BA0_ACCAD2
5001. BA0_ACCDA
5002. BA0_ACCDA2
5003. BA0_ACCTL
5004. BA0_ACCTL2
5005. BA0_ACCTL_CRW
5006. BA0_ACCTL_DCV
5007. BA0_ACCTL_ESYN
5008. BA0_ACCTL_TC
5009. BA0_ACCTL_VFRM
5010. BA0_ACISV
5011. BA0_ACISV2
5012. BA0_ACISV_SLV
5013. BA0_ACOSV
5014. BA0_ACOSV2
5015. BA0_ACOSV_SLV
5016. BA0_ACSAD
5017. BA0_ACSAD2
5018. BA0_ACSDA
5019. BA0_ACSDA2
5020. BA0_ACSTS
5021. BA0_ACSTS2
5022. BA0_ACSTS_CRDY
5023. BA0_ACSTS_VSTS
5024. BA0_ADCSR
5025. BA0_AODSD1
5026. BA0_AODSD1_NDS
5027. BA0_AODSD2
5028. BA0_AODSD2_NDS
5029. BA0_ASER_FADDR
5030. BA0_ASER_MASTER
5031. BA0_B0AP
5032. BA0_B1AP
5033. BA0_B1DP
5034. BA0_CASR
5035. BA0_CFGI
5036. BA0_CFL1
5037. BA0_CFL2
5038. BA0_CFLR
5039. BA0_CFLR_DEFAULT
5040. BA0_CLKCR1
5041. BA0_CLKCR1_CLKON
5042. BA0_CLKCR1_DLLOS
5043. BA0_CLKCR1_DLLP
5044. BA0_CLKCR1_DLLRDY
5045. BA0_CLKCR1_DLLSS
5046. BA0_CLKCR1_SWCE
5047. BA0_CLKCR2
5048. BA0_CWPR
5049. BA0_DACSR
5050. BA0_DBA0
5051. BA0_DBA1
5052. BA0_DBA2
5053. BA0_DBA3
5054. BA0_DBC0
5055. BA0_DBC1
5056. BA0_DBC2
5057. BA0_DBC3
5058. BA0_DCA0
5059. BA0_DCA1
5060. BA0_DCA2
5061. BA0_DCA3
5062. BA0_DCC0
5063. BA0_DCC1
5064. BA0_DCC2
5065. BA0_DCC3
5066. BA0_DCR0
5067. BA0_DCR1
5068. BA0_DCR2
5069. BA0_DCR3
5070. BA0_DCR_HTCIE
5071. BA0_DCR_MSK
5072. BA0_DCR_TCIE
5073. BA0_DMR0
5074. BA0_DMR1
5075. BA0_DMR2
5076. BA0_DMR3
5077. BA0_DMR_AUTO
5078. BA0_DMR_BEND
5079. BA0_DMR_CBC
5080. BA0_DMR_DEC
5081. BA0_DMR_DMA
5082. BA0_DMR_MONO
5083. BA0_DMR_POLL
5084. BA0_DMR_SIZE20
5085. BA0_DMR_SIZE8
5086. BA0_DMR_SWAPC
5087. BA0_DMR_TBC
5088. BA0_DMR_TR_READ
5089. BA0_DMR_TR_VERIFY
5090. BA0_DMR_TR_WRITE
5091. BA0_DMR_TYPE_BLOCK
5092. BA0_DMR_TYPE_CASCADE
5093. BA0_DMR_TYPE_DEMAND
5094. BA0_DMR_TYPE_SINGLE
5095. BA0_DMR_USIGN
5096. BA0_DMSR
5097. BA0_DPCIA
5098. BA0_DPCIC
5099. BA0_DPCID
5100. BA0_EGPIODR
5101. BA0_EGPIOPTR
5102. BA0_EGPIOSR
5103. BA0_EGPIOTR
5104. BA0_EGPIOWR
5105. BA0_EPCIPMC
5106. BA0_EPPMC
5107. BA0_EPPMC_FPDN
5108. BA0_FCHS
5109. BA0_FCHS_FE
5110. BA0_FCHS_FF
5111. BA0_FCHS_IOR
5112. BA0_FCHS_LCI
5113. BA0_FCHS_LCO
5114. BA0_FCHS_MRP
5115. BA0_FCHS_RCI
5116. BA0_FCHS_RCO
5117. BA0_FCR0
5118. BA0_FCR1
5119. BA0_FCR2
5120. BA0_FCR3
5121. BA0_FCR_DACZ
5122. BA0_FCR_FEN
5123. BA0_FCR_LS
5124. BA0_FCR_OF
5125. BA0_FCR_PSH
5126. BA0_FCR_RS
5127. BA0_FCR_SZ
5128. BA0_FMDP
5129. BA0_FMLVC
5130. BA0_FMRVC
5131. BA0_FMSR
5132. BA0_FPDR0
5133. BA0_FPDR1
5134. BA0_FPDR2
5135. BA0_FPDR3
5136. BA0_FRR
5137. BA0_FSIC0
5138. BA0_FSIC1
5139. BA0_FSIC2
5140. BA0_FSIC3
5141. BA0_FSIC_FIC
5142. BA0_FSIC_FOR
5143. BA0_FSIC_FORIE
5144. BA0_FSIC_FSC
5145. BA0_FSIC_FSCIE
5146. BA0_FSIC_FSCR
5147. BA0_FSIC_FUR
5148. BA0_FSIC_FURIE
5149. BA0_GPIOR
5150. BA0_HDAR
5151. BA0_HDCR
5152. BA0_HDMR
5153. BA0_HDSR0
5154. BA0_HDSR1
5155. BA0_HDSR2
5156. BA0_HDSR3
5157. BA0_HDSR_CH1P
5158. BA0_HDSR_CH2P
5159. BA0_HDSR_DHTC
5160. BA0_HDSR_DRUN
5161. BA0_HDSR_DTC
5162. BA0_HDSR_RQ
5163. BA0_HICR
5164. BA0_HICR_CHGM
5165. BA0_HICR_EOI
5166. BA0_HICR_IEV
5167. BA0_HIMR
5168. BA0_HISR
5169. BA0_HISR_DMA
5170. BA0_HISR_DMAI
5171. BA0_HISR_FIFO
5172. BA0_HISR_FIFOI
5173. BA0_HISR_GP1I
5174. BA0_HISR_GP3I
5175. BA0_HISR_GPPI
5176. BA0_HISR_GPSI
5177. BA0_HISR_INTENA
5178. BA0_HISR_MIDI
5179. BA0_HISR_VDNI
5180. BA0_HISR_VUPI
5181. BA0_HSAR
5182. BA0_HSR0
5183. BA0_IIER
5184. BA0_IISR
5185. BA0_IOTAC0
5186. BA0_IOTAC1
5187. BA0_IOTAC10
5188. BA0_IOTAC11
5189. BA0_IOTAC2
5190. BA0_IOTAC3
5191. BA0_IOTAC4
5192. BA0_IOTAC5
5193. BA0_IOTAC6
5194. BA0_IOTAC7
5195. BA0_IOTAC8
5196. BA0_IOTAC9
5197. BA0_IOTCR
5198. BA0_IOTFIFO
5199. BA0_IOTFP
5200. BA0_IOTFR0
5201. BA0_IOTFR1
5202. BA0_IOTFR2
5203. BA0_IOTFR3
5204. BA0_IOTFR4
5205. BA0_IOTFR5
5206. BA0_IOTFR6
5207. BA0_IOTFR7
5208. BA0_IOTRRD
5209. BA0_JSC1
5210. BA0_JSC2
5211. BA0_JSCTL
5212. BA0_JSIO
5213. BA0_JSPT
5214. BA0_MIDCMD
5215. BA0_MIDCR
5216. BA0_MIDCR_MLB
5217. BA0_MIDCR_MRST
5218. BA0_MIDCR_RIE
5219. BA0_MIDCR_RXE
5220. BA0_MIDCR_TIE
5221. BA0_MIDCR_TXE
5222. BA0_MIDRP
5223. BA0_MIDSR
5224. BA0_MIDSR_RBE
5225. BA0_MIDSR_RDA
5226. BA0_MIDSR_TBE
5227. BA0_MIDSR_TBF
5228. BA0_MIDWP
5229. BA0_PASR
5230. BA0_PCICFG00
5231. BA0_PCICFG04
5232. BA0_PCICFG08
5233. BA0_PCICFG0C
5234. BA0_PCICFG10
5235. BA0_PCICFG14
5236. BA0_PCICFG18
5237. BA0_PCICFG1C
5238. BA0_PCICFG20
5239. BA0_PCICFG24
5240. BA0_PCICFG28
5241. BA0_PCICFG2C
5242. BA0_PCICFG30
5243. BA0_PCICFG34
5244. BA0_PCICFG38
5245. BA0_PCICFG3C
5246. BA0_PCPCIEN
5247. BA0_PCPCIG
5248. BA0_PCPCIR
5249. BA0_PFCV1
5250. BA0_PFCV2
5251. BA0_PFMC
5252. BA0_PLLCC
5253. BA0_PLLM
5254. BA0_PMCS
5255. BA0_PPLVC
5256. BA0_PPRVC
5257. BA0_SERACC
5258. BA0_SERBAD
5259. BA0_SERBCF
5260. BA0_SERBCM
5261. BA0_SERBRP
5262. BA0_SERBSP
5263. BA0_SERBST
5264. BA0_SERBWP
5265. BA0_SERC1
5266. BA0_SERC1_AC97
5267. BA0_SERC1_SO1EN
5268. BA0_SERC1_SO1F
5269. BA0_SERC2
5270. BA0_SERC2_AC97
5271. BA0_SERC2_SI1EN
5272. BA0_SERC2_SI1F
5273. BA0_SERC3
5274. BA0_SERC4
5275. BA0_SERC5
5276. BA0_SERC6
5277. BA0_SERC7
5278. BA0_SERMC
5279. BA0_SERMC1
5280. BA0_SERMC2
5281. BA0_SERMC_FCRN
5282. BA0_SERMC_LOVF
5283. BA0_SERMC_MSPE
5284. BA0_SERMC_ODSEN1
5285. BA0_SERMC_ODSEN2
5286. BA0_SERMC_PLB
5287. BA0_SERMC_PTC
5288. BA0_SERMC_PTC_AC97
5289. BA0_SERMC_PXLB
5290. BA0_SERMC_SLB
5291. BA0_SERMC_SXLB
5292. BA0_SERMC_TCID
5293. BA0_SLT12M
5294. BA0_SLT12M2
5295. BA0_SLT12O
5296. BA0_SPMC
5297. BA0_SPMC_ASDI2E
5298. BA0_SPMC_ASDO
5299. BA0_SPMC_ASYNC
5300. BA0_SPMC_EESPD
5301. BA0_SPMC_GIPPEN
5302. BA0_SPMC_GISPEN
5303. BA0_SPMC_RSTN
5304. BA0_SPMC_WUP1
5305. BA0_SPMC_WUP2
5306. BA0_SRCSA
5307. BA0_SSCR
5308. BA0_SSCR_CDTX
5309. BA0_SSCR_HVC
5310. BA0_SSCR_HVS1
5311. BA0_SSCR_LPSRC
5312. BA0_SSCR_MVAD
5313. BA0_SSCR_MVCS
5314. BA0_SSCR_MVLD
5315. BA0_SSCR_MVMD
5316. BA0_SSCR_XLPSRC
5317. BA0_SSPM
5318. BA0_SSPM_ACLEN
5319. BA0_SSPM_CSRCEN
5320. BA0_SSPM_FMEN
5321. BA0_SSPM_JSEN
5322. BA0_SSPM_MIXEN
5323. BA0_SSPM_PSRCEN
5324. BA0_SSVID
5325. BA0_TMS
5326. BA1_CBA
5327. BA1_CCI
5328. BA1_CCST
5329. BA1_CCTL
5330. BA1_CD
5331. BA1_CFG1
5332. BA1_CFG2
5333. BA1_CIE
5334. BA1_CPI
5335. BA1_CSPB
5336. BA1_CSRC
5337. BA1_CVOL
5338. BA1_DREG
5339. BA1_DSRWP
5340. BA1_DWORD_SIZE
5341. BA1_FGR1
5342. BA1_FRCC
5343. BA1_FRMT
5344. BA1_FRSC
5345. BA1_MEMORY_COUNT
5346. BA1_OMNI_MEM
5347. BA1_PBA
5348. BA1_PCTL
5349. BA1_PDTC
5350. BA1_PFIE
5351. BA1_PPI
5352. BA1_PSRC
5353. BA1_PVOL
5354. BA1_SDSR
5355. BA1_SPCR
5356. BA1_SPCS
5357. BA1_SPIR
5358. BA1_SPWR
5359. BA1_SP_DMEM0
5360. BA1_SP_DMEM1
5361. BA1_SP_PMEM
5362. BA1_SP_REG
5363. BA1_TWPR
5364. BA1_VARIDEC_BUF_1
5365. BABBLE
5366. BABL
5367. BABLM
5368. BABOON_BASE
5369. BABOON_SOURCE_BASE
5370. BACAMCMD
5371. BACAMCONTENT
5372. BACKBIAS_DPM_CNTL
5373. BACKBIAS_PAD_EN
5374. BACKBIAS_VALUE
5375. BACKEND_DISABLE
5376. BACKEND_DISABLE_MASK
5377. BACKEND_DISABLE_SHIFT
5378. BACKEND_MAP
5379. BACKGROUND_COLOR_ALPHA
5380. BACKGROUND_COLOR_BLUE
5381. BACKGROUND_COLOR_GREEN
5382. BACKGROUND_COLOR_RED
5383. BACKING_DEV_OFFLINE_TIMEOUT
5384. BACKLIGHT_DAC_OFF
5385. BACKLIGHT_DUTY_CYCLE_MASK
5386. BACKLIGHT_DUTY_CYCLE_MASK_PNV
5387. BACKLIGHT_DUTY_CYCLE_SHIFT
5388. BACKLIGHT_EN
5389. BACKLIGHT_ENABLE
5390. BACKLIGHT_FIRMWARE
5391. BACKLIGHT_KEY
5392. BACKLIGHT_LEVEL_ADDR
5393. BACKLIGHT_LEVEL_MAX
5394. BACKLIGHT_LVDS_OFF
5395. BACKLIGHT_MODULATION_FREQ_MASK
5396. BACKLIGHT_MODULATION_FREQ_SHIFT
5397. BACKLIGHT_OFF
5398. BACKLIGHT_ON
5399. BACKLIGHT_PARAM_POWER
5400. BACKLIGHT_PLATFORM
5401. BACKLIGHT_RAW
5402. BACKLIGHT_REGISTERED
5403. BACKLIGHT_SCALE_LINEAR
5404. BACKLIGHT_SCALE_NON_LINEAR
5405. BACKLIGHT_SCALE_UNKNOWN
5406. BACKLIGHT_STATE_ADDR
5407. BACKLIGHT_STATE_OFF_DATA
5408. BACKLIGHT_STATE_ON_DATA
5409. BACKLIGHT_TYPE_MAX
5410. BACKLIGHT_UNREGISTERED
5411. BACKLIGHT_UPDATE_HOTKEY
5412. BACKLIGHT_UPDATE_SYSFS
5413. BACKOFF_LABEL
5414. BACKOFF_LIMIT
5415. BACKOFF_OFF
5416. BACKOFF_SEEDSET_LFSRS
5417. BACKOFF_SEEDSET_ROWS
5418. BACKOFF_SETUP
5419. BACKOFF_SPIN
5420. BACKPACK_VERSION
5421. BACKPORCH
5422. BACKP_ENABLE
5423. BACKP_JAM_LEN_MASK
5424. BACKP_LOW_MASK
5425. BACKP_MODE
5426. BACKREF_FOUND_SHARED
5427. BACKSPACEBLOCK
5428. BACKSPACEFILE
5429. BACKUP_REGS_SZ
5430. BACKUP_REGS_SZ_MAX
5431. BACKUP_REGS_SZ_V4A
5432. BACKUP_REGS_SZ_V4B
5433. BACKUP_SECINFO
5434. BACK_BSREQ_MARK
5435. BACK_LIGHT_COMPENSATION_FORMATTER
5436. BACK_MARK
5437. BACK_PORCH
5438. BACK_PORCH_MASK
5439. BACK_PORCH_SHIFT
5440. BACK_PTYPE_LINE
5441. BACK_PTYPE_POINT
5442. BACK_PTYPE_TRIANGE
5443. BACK_RING_ATTACH
5444. BACK_RING_INIT
5445. BACO_CNTL_IND__BACO_ANA_ISO_DIS_MASK
5446. BACO_CNTL_IND__BACO_ANA_ISO_DIS__SHIFT
5447. BACO_CNTL_IND__BACO_BCLK_OFF_MASK
5448. BACO_CNTL_IND__BACO_BCLK_OFF__SHIFT
5449. BACO_CNTL_IND__BACO_BF_MEM_PHY_ISO_CNTRL_MASK
5450. BACO_CNTL_IND__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT
5451. BACO_CNTL_IND__BACO_EN_MASK
5452. BACO_CNTL_IND__BACO_EN__SHIFT
5453. BACO_CNTL_IND__BACO_HANG_PROTECTION_EN_MASK
5454. BACO_CNTL_IND__BACO_HANG_PROTECTION_EN__SHIFT
5455. BACO_CNTL_IND__BACO_ISO_DIS_MASK
5456. BACO_CNTL_IND__BACO_ISO_DIS__SHIFT
5457. BACO_CNTL_IND__BACO_MODE_MASK
5458. BACO_CNTL_IND__BACO_MODE__SHIFT
5459. BACO_CNTL_IND__BACO_POWER_OFF_DRAM_MASK
5460. BACO_CNTL_IND__BACO_POWER_OFF_DRAM__SHIFT
5461. BACO_CNTL_IND__BACO_POWER_OFF_MASK
5462. BACO_CNTL_IND__BACO_POWER_OFF__SHIFT
5463. BACO_CNTL_IND__BACO_RESET_EN_MASK
5464. BACO_CNTL_IND__BACO_RESET_EN__SHIFT
5465. BACO_CNTL_IND__PWRGOOD_BF_MASK
5466. BACO_CNTL_IND__PWRGOOD_BF__SHIFT
5467. BACO_CNTL_IND__PWRGOOD_DVO_MASK
5468. BACO_CNTL_IND__PWRGOOD_DVO__SHIFT
5469. BACO_CNTL_IND__PWRGOOD_GPIO_MASK
5470. BACO_CNTL_IND__PWRGOOD_GPIO__SHIFT
5471. BACO_CNTL_IND__PWRGOOD_IDSC_MASK
5472. BACO_CNTL_IND__PWRGOOD_IDSC__SHIFT
5473. BACO_CNTL_IND__PWRGOOD_MEM_MASK
5474. BACO_CNTL_IND__PWRGOOD_MEM__SHIFT
5475. BACO_CNTL_IND__RCU_BIF_CONFIG_DONE_MASK
5476. BACO_CNTL_IND__RCU_BIF_CONFIG_DONE__SHIFT
5477. BACO_CNTL_MISC_IND__BACO_LINK_RST_WIDTH_SEL_MASK
5478. BACO_CNTL_MISC_IND__BACO_LINK_RST_WIDTH_SEL__SHIFT
5479. BACO_CNTL_MISC_IND__BIF_AZ_REQ_DIS_MASK
5480. BACO_CNTL_MISC_IND__BIF_AZ_REQ_DIS__SHIFT
5481. BACO_CNTL_MISC_IND__BIF_ROM_REQ_DIS_MASK
5482. BACO_CNTL_MISC_IND__BIF_ROM_REQ_DIS__SHIFT
5483. BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK
5484. BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT
5485. BACO_CNTL_MISC__BACO_REFCLK_SEL_MASK
5486. BACO_CNTL_MISC__BACO_REFCLK_SEL__SHIFT
5487. BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK
5488. BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT
5489. BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK
5490. BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT
5491. BACO_CNTL__BACO_ANA_ISO_DIS_MASK
5492. BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT
5493. BACO_CNTL__BACO_AUTO_EXIT_MASK
5494. BACO_CNTL__BACO_AUTO_EXIT__MASK
5495. BACO_CNTL__BACO_AUTO_EXIT__SHIFT
5496. BACO_CNTL__BACO_BCLK_OFF_MASK
5497. BACO_CNTL__BACO_BCLK_OFF__SHIFT
5498. BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK
5499. BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT
5500. BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK
5501. BACO_CNTL__BACO_BIF_LCLK_SWITCH__MASK
5502. BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT
5503. BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK
5504. BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT
5505. BACO_CNTL__BACO_DSTATE_BYPASS_MASK
5506. BACO_CNTL__BACO_DSTATE_BYPASS__MASK
5507. BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT
5508. BACO_CNTL__BACO_DUMMY_EN_MASK
5509. BACO_CNTL__BACO_DUMMY_EN__MASK
5510. BACO_CNTL__BACO_DUMMY_EN__SHIFT
5511. BACO_CNTL__BACO_EN_MASK
5512. BACO_CNTL__BACO_EN__MASK
5513. BACO_CNTL__BACO_EN__SHIFT
5514. BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK
5515. BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT
5516. BACO_CNTL__BACO_ISO_DIS_MASK
5517. BACO_CNTL__BACO_ISO_DIS__SHIFT
5518. BACO_CNTL__BACO_MODE_MASK
5519. BACO_CNTL__BACO_MODE__MASK
5520. BACO_CNTL__BACO_MODE__SHIFT
5521. BACO_CNTL__BACO_POWER_OFF_DRAM_MASK
5522. BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT
5523. BACO_CNTL__BACO_POWER_OFF_MASK
5524. BACO_CNTL__BACO_POWER_OFF__MASK
5525. BACO_CNTL__BACO_POWER_OFF__SHIFT
5526. BACO_CNTL__BACO_RESET_EN_MASK
5527. BACO_CNTL__BACO_RESET_EN__SHIFT
5528. BACO_CNTL__BACO_RST_INTR_MASK_MASK
5529. BACO_CNTL__BACO_RST_INTR_MASK__MASK
5530. BACO_CNTL__BACO_RST_INTR_MASK__SHIFT
5531. BACO_CNTL__PWRGOOD_BF_MASK
5532. BACO_CNTL__PWRGOOD_BF__SHIFT
5533. BACO_CNTL__PWRGOOD_DVO_MASK
5534. BACO_CNTL__PWRGOOD_DVO__SHIFT
5535. BACO_CNTL__PWRGOOD_GPIO_MASK
5536. BACO_CNTL__PWRGOOD_GPIO__SHIFT
5537. BACO_CNTL__PWRGOOD_IDSC_MASK
5538. BACO_CNTL__PWRGOOD_IDSC__SHIFT
5539. BACO_CNTL__PWRGOOD_MEM_MASK
5540. BACO_CNTL__PWRGOOD_MEM__SHIFT
5541. BACO_CNTL__PWRGOOD_VDDSOC_MASK
5542. BACO_CNTL__PWRGOOD_VDDSOC__SHIFT
5543. BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK
5544. BACO_CNTL__RCU_BIF_CONFIG_DONE__MASK
5545. BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT
5546. BACO_SEQUENCE
5547. BACO_SEQ_BACO
5548. BACO_SEQ_BAMACO
5549. BACO_SEQ_COUNT
5550. BACO_SEQ_MSR
5551. BACO_SEQ_ULPS
5552. BACO_STATE
5553. BACO_STATE_IN
5554. BACO_STATE_OUT
5555. BACTRL
5556. BAD
5557. BAD110P_CURRENT
5558. BAD11NPUT_RANGE
5559. BAD11POWERUP_ATRX
5560. BAD11POWERUP_ATTX
5561. BAD11SH_GAIN
5562. BAD7POWERUP
5563. BADA_EN
5564. BADBLOCK_I
5565. BADBLOCK_MARKER_LENGTH
5566. BADBLOCK_SCAN_MASK
5567. BADCLKPHASE
5568. BADCODEM1
5569. BADC_BACKOFF
5570. BADFMT
5571. BADGE4_5V_INITIALLY
5572. BADGE4_5V_PCMCIA_SOCK
5573. BADGE4_5V_PCMCIA_SOCK0
5574. BADGE4_5V_PCMCIA_SOCK1
5575. BADGE4_5V_USB
5576. BADGE4_GPIO_BGNT_1111
5577. BADGE4_GPIO_BREQ_1111
5578. BADGE4_GPIO_CLK_1111
5579. BADGE4_GPIO_GPA_VID
5580. BADGE4_GPIO_GPB_VID
5581. BADGE4_GPIO_GPC_VID
5582. BADGE4_GPIO_INT_1111
5583. BADGE4_GPIO_INT_VID
5584. BADGE4_GPIO_LGP2
5585. BADGE4_GPIO_LGP3
5586. BADGE4_GPIO_LGP4
5587. BADGE4_GPIO_LGP5
5588. BADGE4_GPIO_LGP6
5589. BADGE4_GPIO_LGP7
5590. BADGE4_GPIO_LGP8
5591. BADGE4_GPIO_LGP9
5592. BADGE4_GPIO_MUXSEL0
5593. BADGE4_GPIO_PCMEN5V
5594. BADGE4_GPIO_SA1111_NRST
5595. BADGE4_GPIO_SDSCL
5596. BADGE4_GPIO_SDSDA
5597. BADGE4_GPIO_SDTYP0
5598. BADGE4_GPIO_SDTYP1
5599. BADGE4_GPIO_TESTPT_J5
5600. BADGE4_GPIO_TESTPT_J6
5601. BADGE4_GPIO_TESTPT_J7
5602. BADGE4_GPIO_UART_HS1
5603. BADGE4_GPIO_UART_HS2
5604. BADGE4_IRQ_GPIO_SA1111
5605. BADGE4_SA1111_BASE
5606. BADIDX
5607. BADMAG
5608. BADVADDR
5609. BADVA_OFF
5610. BADV_TIME_CTRL
5611. BADV_UPD_CFO
5612. BADV_UPD_EQZ
5613. BAD_ACCESS
5614. BAD_ADDR
5615. BAD_ADDREXCPTN
5616. BAD_APICID
5617. BAD_ARG
5618. BAD_BLOCK
5619. BAD_BLOCK_BYTE_NUM
5620. BAD_BLOCK_IN_SPARE_AREA
5621. BAD_BLOCK_SYSTEM_INODE
5622. BAD_CLK_INDEX
5623. BAD_CLK_NAME
5624. BAD_COMMAND
5625. BAD_CPT_TYPES
5626. BAD_CRC
5627. BAD_DATA
5628. BAD_DEST
5629. BAD_DMA_DRIVE
5630. BAD_ERROR
5631. BAD_EXT_STATUS
5632. BAD_FAT12
5633. BAD_FAT16
5634. BAD_FAT32
5635. BAD_FIQ
5636. BAD_FUNC
5637. BAD_FW
5638. BAD_INSTR
5639. BAD_INT_S0
5640. BAD_INT_S1
5641. BAD_INT_VEC
5642. BAD_IRQ
5643. BAD_L2_ERR
5644. BAD_MADT_ENTRY
5645. BAD_MADT_GICC_ENTRY
5646. BAD_MAGIC
5647. BAD_MULTI_IO
5648. BAD_NIP
5649. BAD_NO_DAC
5650. BAD_NO_EXTRA_DAC
5651. BAD_NO_EXTRA_SURR_DAC
5652. BAD_NO_INDEP_HP
5653. BAD_NO_PRIMARY_DAC
5654. BAD_PAGE
5655. BAD_PAGETABLE
5656. BAD_PERSONALITY_TYP
5657. BAD_PREFETCH
5658. BAD_PROT
5659. BAD_PROTO
5660. BAD_PROT_ID
5661. BAD_RATE
5662. BAD_REGADDR
5663. BAD_RING
5664. BAD_R_STAT
5665. BAD_SCALED_DIV_VALUE
5666. BAD_SHARED_CLFE
5667. BAD_SHARED_EXTRA_SURROUND
5668. BAD_SHARED_SURROUND
5669. BAD_SHARED_VOL
5670. BAD_SNAP_INDEX
5671. BAD_STACK
5672. BAD_STACK_TRAMPOLINE
5673. BAD_STAT
5674. BAD_STATE
5675. BAD_SYNC
5676. BAD_TRAP
5677. BAD_TRAP_P
5678. BAD_UNDEFINSTR
5679. BAD_VCC_REQ
5680. BAD_VCC_REQ_DISB
5681. BAD_WORK_MSG
5682. BAD_W_STAT
5683. BAFEWATCHDOGENABLE
5684. BAFE_LOOPBACK
5685. BAGCADDRESS
5686. BAGCRXCODE
5687. BAGCTXCODE
5688. BAIndexBase
5689. BAJustPoint
5690. BALANCE_LEG_DISABLE
5691. BALANCE_LEG_DISABLE_SHIFT
5692. BALANCE_LEG_MASK
5693. BALANCE_LEG_SHIFT
5694. BALLOON3_AUX_NIRQ
5695. BALLOON3_BP_CF_NRDY_IRQ
5696. BALLOON3_BP_NSTSCHG_IRQ
5697. BALLOON3_CF_ADD_ENABLE
5698. BALLOON3_CF_CONTROL_REG
5699. BALLOON3_CF_ENABLE
5700. BALLOON3_CF_RESET
5701. BALLOON3_CF_STATUS_REG
5702. BALLOON3_CF_nIRQ
5703. BALLOON3_CF_nSTSCHG_BVD1
5704. BALLOON3_CODEC_IRQ
5705. BALLOON3_FEATURE_AUDIO
5706. BALLOON3_FEATURE_CF
5707. BALLOON3_FEATURE_MMC
5708. BALLOON3_FEATURE_OHCI
5709. BALLOON3_FEATURE_TOPPOLY
5710. BALLOON3_FPGA_LENGTH
5711. BALLOON3_FPGA_PHYS
5712. BALLOON3_FPGA_SETnCLR
5713. BALLOON3_FPGA_VER
5714. BALLOON3_FPGA_VIRT
5715. BALLOON3_GPIO_AUX_NIRQ
5716. BALLOON3_GPIO_CODEC_IRQ
5717. BALLOON3_GPIO_LED_IDLE
5718. BALLOON3_GPIO_LED_NAND
5719. BALLOON3_GPIO_RUN_BACKLIGHT
5720. BALLOON3_GPIO_RUN_NAND
5721. BALLOON3_GPIO_S0_CD
5722. BALLOON3_INT_CONTROL_REG
5723. BALLOON3_INT_S0_IRQ
5724. BALLOON3_INT_S0_STSCHG
5725. BALLOON3_IRQ
5726. BALLOON3_NAND_BASE
5727. BALLOON3_NAND_CONTROL2_16BIT
5728. BALLOON3_NAND_CONTROL2_REG
5729. BALLOON3_NAND_CONTROL_FLALE
5730. BALLOON3_NAND_CONTROL_FLCE0
5731. BALLOON3_NAND_CONTROL_FLCE1
5732. BALLOON3_NAND_CONTROL_FLCE2
5733. BALLOON3_NAND_CONTROL_FLCE3
5734. BALLOON3_NAND_CONTROL_FLCLE
5735. BALLOON3_NAND_CONTROL_FLSE
5736. BALLOON3_NAND_CONTROL_FLWP
5737. BALLOON3_NAND_CONTROL_REG
5738. BALLOON3_NAND_IO_REG
5739. BALLOON3_NAND_STAT_REG
5740. BALLOON3_NAND_STAT_RNB
5741. BALLOON3_NR_IRQS
5742. BALLOON3_PCF_GPIO_BASE
5743. BALLOON3_PCF_GPIO_LED0
5744. BALLOON3_PCF_GPIO_LED1
5745. BALLOON3_PCF_GPIO_LED2
5746. BALLOON3_PCF_GPIO_LED3
5747. BALLOON3_PCF_GPIO_LED4
5748. BALLOON3_PCF_GPIO_LED5
5749. BALLOON3_PCF_GPIO_LED6
5750. BALLOON3_PCF_GPIO_LED7
5751. BALLOON3_SAMOSA_ADDR_REG
5752. BALLOON3_SAMOSA_DATA_REG
5753. BALLOON3_SAMOSA_STATUS_REG
5754. BALLOON3_VERSION_REG
5755. BALLOON_CLASS_NAME
5756. BALLOON_DEFLATE
5757. BALLOON_INFLATE
5758. BALLOON_KVM_MAGIC
5759. BALLOON_MIGRATE
5760. BALLOON_SHOW
5761. BALLOON_VMW_MAGIC
5762. BALLOUT_V8_ARMIO3
5763. BAM16BUF
5764. BAM16BUF_EN_CK
5765. BAM16BUF_IDX_END2
5766. BAM16BUF_IDX_ST2
5767. BAM16BUF_LOJ
5768. BAM16BUF_OFFSET2
5769. BAM32BUF
5770. BAM32BUF_EN_CK
5771. BAM32BUF_IDX_END3
5772. BAM32BUF_IDX_ST3
5773. BAM32BUF_LOJ
5774. BAM32BUF_OFFSET3
5775. BAM4BUF
5776. BAM4BUF_EN_CK
5777. BAM4BUF_IDX_END0
5778. BAM4BUF_IDX_ST0
5779. BAM4BUF_LOJ
5780. BAM4BUF_OFFSET0
5781. BAM8BUF
5782. BAM8BUF_EN_CK
5783. BAM8BUF_IDX_END1
5784. BAM8BUF_IDX_ST1
5785. BAM8BUF_LOJ
5786. BAM8BUF_OFFSET1
5787. BAMACO_SEQUENCE
5788. BAMBOO_PAD
5789. BAMBOO_PEN
5790. BAMBOO_PT
5791. BAMBOO_TOUCH
5792. BAM_AU_ACCUMED
5793. BAM_AU_P_RES
5794. BAM_BIT
5795. BAM_CACHED_DESC_STORE
5796. BAM_CMD_ENABLE
5797. BAM_CNFG_BITS
5798. BAM_CNFG_BITS_DEFAULT
5799. BAM_CTRL
5800. BAM_DESC_CACHE_SEL_MASK
5801. BAM_DESC_CACHE_SEL_SHIFT
5802. BAM_DESC_CNT_TRSHLD
5803. BAM_DESC_FIFO_SIZE
5804. BAM_DMA_AUTOSUSPEND_DELAY
5805. BAM_EMPTY_CLR
5806. BAM_EMPTY_EN
5807. BAM_EMPTY_IRQ
5808. BAM_EN
5809. BAM_EN_ACCUM
5810. BAM_ERROR_CLR
5811. BAM_ERROR_EN
5812. BAM_ERROR_IRQ
5813. BAM_FIFO_SIZE
5814. BAM_FULL_PIPE
5815. BAM_HAS_NO_BYPASS
5816. BAM_HRESP_ERR_CLR
5817. BAM_HRESP_ERR_EN
5818. BAM_HRESP_ERR_IRQ
5819. BAM_IBC_DISABLE
5820. BAM_IRQ
5821. BAM_IRQ_CLR
5822. BAM_IRQ_EN
5823. BAM_IRQ_MSK
5824. BAM_IRQ_SRCS
5825. BAM_IRQ_SRCS_EE
5826. BAM_IRQ_SRCS_MSK
5827. BAM_IRQ_SRCS_MSK_EE
5828. BAM_IRQ_SRCS_UNMASKED
5829. BAM_IRQ_STTS
5830. BAM_MODE_EN
5831. BAM_NON_PIPE_GRP_MASK
5832. BAM_NON_PIPE_GRP_SHIFT
5833. BAM_NO_EXT_P_RST
5834. BAM_NUM_PIPES
5835. BAM_NUM_PIPES_MASK
5836. BAM_NUM_PIPES_SHIFT
5837. BAM_PIPE_CNFG
5838. BAM_PIPE_SETS_MASK
5839. BAM_PIPE_SETS_SHIFT
5840. BAM_PSM_CSW_REQ
5841. BAM_PSM_P_HD_DATA
5842. BAM_PSM_P_RES
5843. BAM_P_CTRL
5844. BAM_P_DATA_FIFO_ADDR
5845. BAM_P_DESC_FIFO_ADDR
5846. BAM_P_EVNT_DEST_ADDR
5847. BAM_P_EVNT_GEN_TRSHLD
5848. BAM_P_EVNT_REG
5849. BAM_P_FIFO_SIZES
5850. BAM_P_HALT
5851. BAM_P_IRQ_CLR
5852. BAM_P_IRQ_EN
5853. BAM_P_IRQ_STTS
5854. BAM_P_RST
5855. BAM_P_SW_OFSTS
5856. BAM_READ_COMMAND
5857. BAM_REG_P_EN
5858. BAM_REVISION
5859. BAM_SB_CLK_REQ
5860. BAM_SI_P_RES
5861. BAM_SW_RST
5862. BAM_TESTBUS_SEL_MASK
5863. BAM_TESTBUS_SEL_SHIFT
5864. BAM_TIMER_CLR
5865. BAM_TIMER_EN
5866. BAM_TIMER_IRQ
5867. BAM_WB_BLK_CSW
5868. BAM_WB_CSW_ACK_IDL
5869. BAM_WB_DSC_AVL_P_RST
5870. BAM_WB_P_RES
5871. BAM_WB_RETR_SVPNT
5872. BAM_WRITE_COMMAND
5873. BAND1
5874. BAND2
5875. BAND3
5876. BAND4
5877. BAND5
5878. BANDB_232USB9M_PID
5879. BANDB_485USB9F_2W_PID
5880. BANDB_485USB9F_4W_PID
5881. BANDB_485USBTB_2W_PID
5882. BANDB_485USBTB_4W_PID
5883. BANDB_DEVICE_ID_US9ML2_2
5884. BANDB_DEVICE_ID_US9ML2_4
5885. BANDB_DEVICE_ID_USO9ML2_2
5886. BANDB_DEVICE_ID_USO9ML2_2P
5887. BANDB_DEVICE_ID_USO9ML2_4
5888. BANDB_DEVICE_ID_USO9ML2_4P
5889. BANDB_DEVICE_ID_USOPTL2_4
5890. BANDB_DEVICE_ID_USOPTL4_2
5891. BANDB_DEVICE_ID_USOPTL4_2P
5892. BANDB_DEVICE_ID_USOPTL4_4
5893. BANDB_DEVICE_ID_USOPTL4_4P
5894. BANDB_DEVICE_ID_USPTL4_2
5895. BANDB_DEVICE_ID_USPTL4_4
5896. BANDB_TTL3USB9M_PID
5897. BANDB_TTL5USB9M_PID
5898. BANDB_USO9ML2DR_2_PID
5899. BANDB_USO9ML2DR_PID
5900. BANDB_USO9ML2_PID
5901. BANDB_USOPTL4DR2_PID
5902. BANDB_USOPTL4DR_PID
5903. BANDB_USOPTL4_PID
5904. BANDB_USOTL4_PID
5905. BANDB_USPTL4_PID
5906. BANDB_USTL4_PID
5907. BANDB_VID
5908. BANDB_ZZ_PROG1_USB_PID
5909. BANDGAP_100_00
5910. BANDGAP_93_17
5911. BANDGAP_94_15
5912. BANDGAP_95_12
5913. BANDGAP_96_10
5914. BANDGAP_97_07
5915. BANDGAP_98_05
5916. BANDGAP_99_02
5917. BANDGAP_AND_BIAS_CONTROL
5918. BANDGAP_LNC_CIRCUIT
5919. BANDGAP_MASK
5920. BANDGAP_ON
5921. BANDGAP_PNW_CIRCUIT
5922. BANDGAP_SEL
5923. BANDIT_COHERENT
5924. BANDIT_DEVID_2
5925. BANDIT_DEVNUM
5926. BANDIT_MAGIC
5927. BANDIT_REVID
5928. BANDMAX
5929. BANDRICH_PRODUCT_1004
5930. BANDRICH_PRODUCT_1005
5931. BANDRICH_PRODUCT_1006
5932. BANDRICH_PRODUCT_1007
5933. BANDRICH_PRODUCT_1008
5934. BANDRICH_PRODUCT_1009
5935. BANDRICH_PRODUCT_100A
5936. BANDRICH_PRODUCT_100B
5937. BANDRICH_PRODUCT_100C
5938. BANDRICH_PRODUCT_100D
5939. BANDRICH_PRODUCT_100E
5940. BANDRICH_PRODUCT_100F
5941. BANDRICH_PRODUCT_1010
5942. BANDRICH_PRODUCT_1011
5943. BANDRICH_PRODUCT_1012
5944. BANDRICH_PRODUCT_C100_1
5945. BANDRICH_PRODUCT_C100_2
5946. BANDRICH_VENDOR_ID
5947. BANDWIDTH
5948. BANDWIDTH_10_MHZ
5949. BANDWIDTH_1_712_MHZ
5950. BANDWIDTH_5_MHZ
5951. BANDWIDTH_6_MHZ
5952. BANDWIDTH_7_MHZ
5953. BANDWIDTH_8_MHZ
5954. BANDWIDTH_AUTO
5955. BANDWIDTH_AVAILABLE_INITIAL
5956. BANDWIDTH_INTERVAL
5957. BANDWIDTH_TO_HZ
5958. BANDWIDTH_TO_KHZ
5959. BAND_2G_INDEX
5960. BAND_5G_INDEX
5961. BAND_5G_PWR_LVLS
5962. BAND_A
5963. BAND_AAC
5964. BAND_ADC_0
5965. BAND_ADC_1
5966. BAND_AM
5967. BAND_AN
5968. BAND_B
5969. BAND_CBAND
5970. BAND_CONFIG_A
5971. BAND_CONFIG_BG
5972. BAND_FM
5973. BAND_FM_JAPAN
5974. BAND_G
5975. BAND_GN
5976. BAND_LBAND
5977. BAND_MAX
5978. BAND_MODE0
5979. BAND_NUM
5980. BAND_OF_FREQUENCY
5981. BAND_ON_2_4G
5982. BAND_ON_5G
5983. BAND_ON_BOTH
5984. BAND_OUT_SEL
5985. BAND_SBAND
5986. BAND_SET
5987. BAND_SW
5988. BAND_TYPE
5989. BAND_UHF
5990. BAND_VHF
5991. BANFF_PMIC_GPIO_BASE
5992. BANFF_PMIC_IRQ_BASE
5993. BANIAS
5994. BANK
5995. BANK0
5996. BANK0_HWIRQ_MASK
5997. BANK0_NR_PINS
5998. BANK0_VALID_MASK
5999. BANK1
6000. BANK1_HWIRQ
6001. BANK1_NR_PINS
6002. BANK2_HWIRQ
6003. BANK2_NR_PINS
6004. BANKGRP_B0_BASE
6005. BANKGRP_B1_BASE
6006. BANKGRP_MAX_VAL_MASK
6007. BANK_0
6008. BANK_0U
6009. BANK_1
6010. BANK_1U
6011. BANK_2
6012. BANK_2U
6013. BANK_3
6014. BANK_4
6015. BANK_ACCDET_SWRST_MASK
6016. BANK_ACCDET_SWRST_MASK_SFT
6017. BANK_ACCDET_SWRST_SFT
6018. BANK_ANALOG_DSP
6019. BANK_AUDIO_SWRST_MASK
6020. BANK_AUDIO_SWRST_MASK_SFT
6021. BANK_AUDIO_SWRST_SFT
6022. BANK_AUDZCD_SWRST_MASK
6023. BANK_AUDZCD_SWRST_MASK_SFT
6024. BANK_AUDZCD_SWRST_SFT
6025. BANK_B0_BASE
6026. BANK_B1_BASE
6027. BANK_B2_BASE
6028. BANK_BIST
6029. BANK_B_EN
6030. BANK_CTX_NUM
6031. BANK_DS
6032. BANK_EN
6033. BANK_ENABLE
6034. BANK_FC
6035. BANK_FM
6036. BANK_FT
6037. BANK_HEIGHT
6038. BANK_INTERLEAVE_SIZE
6039. BANK_L_CTX
6040. BANK_MASK
6041. BANK_MAX
6042. BANK_MAX_VAL_MASK
6043. BANK_MEM_SIZE
6044. BANK_OFF
6045. BANK_OFFSET_STRIDE
6046. BANK_ON
6047. BANK_PMX
6048. BANK_R_CTX
6049. BANK_SEL
6050. BANK_SELECT
6051. BANK_SELECT_0
6052. BANK_SELECT_1
6053. BANK_SEL_DSP
6054. BANK_SEL_REG
6055. BANK_SEL_SENS
6056. BANK_SHIFT
6057. BANK_SWAPS
6058. BANK_SZ
6059. BANK_TILING
6060. BANK_TM
6061. BANK_USED
6062. BANK_VM
6063. BANK_WIDTH
6064. BANK_WOL
6065. BANNER
6066. BANSHEE_MAX_PIXCLOCK
6067. BANTENNA_MAPPING
6068. BANTL
6069. BANT_HT1
6070. BANT_HT1S1
6071. BANT_HT2
6072. BANT_NONHT
6073. BANT_NONHTS1
6074. BAP0
6075. BAP1
6076. BAPM_PARAMETERS_2__MaxPwrGpu_MASK
6077. BAPM_PARAMETERS_2__MaxPwrGpu__SHIFT
6078. BAPM_PARAMETERS_2__NomPwrGpu_MASK
6079. BAPM_PARAMETERS_2__NomPwrGpu__SHIFT
6080. BAPM_PARAMETERS_3__EnergyCntNorm_MASK
6081. BAPM_PARAMETERS_3__EnergyCntNorm__SHIFT
6082. BAPM_PARAMETERS_3__Reserved_MASK
6083. BAPM_PARAMETERS_3__Reserved__SHIFT
6084. BAPM_PARAMETERS_3__TjOffset_MASK
6085. BAPM_PARAMETERS_3__TjOffset__SHIFT
6086. BAPM_PARAMETERS_4__MidPwrCpu_0_MASK
6087. BAPM_PARAMETERS_4__MidPwrCpu_0__SHIFT
6088. BAPM_PARAMETERS_4__MidPwrCpu_1_MASK
6089. BAPM_PARAMETERS_4__MidPwrCpu_1__SHIFT
6090. BAPM_PARAMETERS_4__MinPwrGpu_MASK
6091. BAPM_PARAMETERS_4__MinPwrGpu__SHIFT
6092. BAPM_PARAMETERS__MaxPwrCpu_0_MASK
6093. BAPM_PARAMETERS__MaxPwrCpu_0__SHIFT
6094. BAPM_PARAMETERS__MaxPwrCpu_1_MASK
6095. BAPM_PARAMETERS__MaxPwrCpu_1__SHIFT
6096. BAPM_PARAMETERS__NomPwrCpu_0_MASK
6097. BAPM_PARAMETERS__NomPwrCpu_0__SHIFT
6098. BAPM_PARAMETERS__NomPwrCpu_1_MASK
6099. BAPM_PARAMETERS__NomPwrCpu_1__SHIFT
6100. BAPM_STATUS__COUNT_CORE0_MASK
6101. BAPM_STATUS__COUNT_CORE0__SHIFT
6102. BAPM_STATUS__COUNT_CORE1_MASK
6103. BAPM_STATUS__COUNT_CORE1__SHIFT
6104. BAPM_STATUS__THROTTLE_LAST_MASK
6105. BAPM_STATUS__THROTTLE_LAST__SHIFT
6106. BAPM_STATUS__THROTTLE_MASK
6107. BAPM_STATUS__THROTTLE__SHIFT
6108. BAP_BUSY
6109. BAP_DONE
6110. BAP_ERR
6111. BAR
6112. BAR0
6113. BAR0_LEN_FX00
6114. BAR0_MAP_REG_MSDM_RAM
6115. BAR0_MAP_REG_PSDM_RAM
6116. BAR0_MAP_REG_TSDM_RAM
6117. BAR0_MAP_REG_USDM_RAM
6118. BAR0_MAP_REG_XSDM_RAM
6119. BAR0_MAP_REG_YSDM_RAM
6120. BAR1
6121. BAR1_INDEX_DYNAMIC_MAP
6122. BAR1_INDEX_STATIC_MAP
6123. BAR2_LEN_FX00
6124. BARB
6125. BARBH
6126. BARER
6127. BARE_ADDRESS_SIZE
6128. BARG_LEN
6129. BARH
6130. BARL
6131. BARM
6132. BARRIER
6133. BARRIERS_H
6134. BARRIER_ACKED
6135. BARRIER_BUCKETS_NR
6136. BARRIER_BUCKETS_NR_BITS
6137. BARRIER_EIEIO
6138. BARRIER_ISYNC
6139. BARRIER_LWSYNC
6140. BARRIER_MASK
6141. BARRIER_PTESYNC
6142. BARRIER_SYNC
6143. BARRIER_TEST_PATTERN
6144. BARRIER_UNIT_SECTOR_BITS
6145. BARRIER_UNIT_SECTOR_SIZE
6146. BARSTATUS
6147. BARTS_CGCG_CGLS_DEFAULT_LENGTH
6148. BARTS_CGCG_CGLS_DISABLE_LENGTH
6149. BARTS_CGCG_CGLS_ENABLE_LENGTH
6150. BARTS_GB_ADDR_CONFIG_GOLDEN
6151. BARTS_MGCGCGTSSMCTRL_DFLT
6152. BARTS_MGCG_DEFAULT_LENGTH
6153. BARTS_MGCG_DISABLE_LENGTH
6154. BARTS_MGCG_ENABLE_LENGTH
6155. BARTS_SMC_INT_VECTOR_SIZE
6156. BARTS_SMC_INT_VECTOR_START
6157. BARTS_SMC_UCODE_SIZE
6158. BARTS_SMC_UCODE_START
6159. BARTS_SYSLS_DEFAULT_LENGTH
6160. BARTS_SYSLS_DISABLE_LENGTH
6161. BARTS_SYSLS_ENABLE_LENGTH
6162. BARYC_AT_SAMPLE_ENA
6163. BARYC_SAMPLE_CNTL
6164. BAR_0
6165. BAR_1
6166. BAR_2
6167. BAR_3
6168. BAR_4
6169. BAR_5
6170. BAR_ADDRS
6171. BAR_CNT
6172. BAR_CSTRORM_INTMEM
6173. BAR_DESC_SIZE
6174. BAR_DOORBELL_OFFSET
6175. BAR_FRAME_RELEASE
6176. BAR_ID
6177. BAR_ID_0
6178. BAR_ID_1
6179. BAR_IGU_INTMEM
6180. BAR_INFO_BOTH_VALID
6181. BAR_INFO_HORIZONTAL_VALID
6182. BAR_INFO_NOT_VALID
6183. BAR_INFO_VERTICAL_VALID
6184. BAR_MASK
6185. BAR_ME_REGISTER
6186. BAR_NUM
6187. BAR_RX_EVENT
6188. BAR_TSTRORM_INTMEM
6189. BAR_USTRORM_INTMEM
6190. BAR_XSTRORM_INTMEM
6191. BASCL
6192. BASE
6193. BASE0
6194. BASE0_MASK
6195. BASE0_SHIFT
6196. BASE1
6197. BASE100X
6198. BASE1_MASK
6199. BASE1_RSVD
6200. BASE1_SHIFT
6201. BASE2
6202. BASE2ADDR
6203. BASE2_BKP_MASK
6204. BASE2_BKP_SHIFT
6205. BASE2_MASK
6206. BASE2_SHIFT
6207. BASE64_CHARS
6208. BASEADDR_G
6209. BASEADDR_M
6210. BASEADDR_S
6211. BASEADDR_V7M_SCB
6212. BASEA_RSVD
6213. BASEA_START
6214. BASEBAND_CONFIG_AGC_TAB
6215. BASEBAND_CONFIG_PHY_REG
6216. BASEBAND_SOUND
6217. BASEBAND_SPARROW_M_A0
6218. BASEBAND_SPARROW_M_A1
6219. BASEBAND_SPARROW_M_B0
6220. BASEBAND_SPARROW_M_C0
6221. BASEBAND_SPARROW_M_D0
6222. BASEBAND_TALYN_M_A0
6223. BASEBAND_TALYN_M_B0
6224. BASEBAND_UNKNOWN
6225. BASEB_IOMAP_MASK
6226. BASEB_RSVD
6227. BASEB_START
6228. BASECHG
6229. BASEC_MASK
6230. BASEC_RSVD
6231. BASEC_START
6232. BASED
6233. BASEDEC
6234. BASEHD
6235. BASEIO_BRIDGE_INDEX
6236. BASEIO_IOC3_INDEX
6237. BASEIO_SCSI1_INDEX
6238. BASEIO_SCSI2_INDEX
6239. BASEMASK_BASE_MASK
6240. BASEMASK_BASE_SHIFT
6241. BASEMASK_MASK_MASK
6242. BASEMASK_MASK_SHIFT
6243. BASEMASK_REMAP_EN
6244. BASEMASK_SWAP_EN
6245. BASEMAX
6246. BASERXH
6247. BASERXL
6248. BASER_INDEX
6249. BASETXH
6250. BASETXL
6251. BASE_A1_IN
6252. BASE_A1_OUT
6253. BASE_A2_IN
6254. BASE_A2_OUT
6255. BASE_ACTIVATE_DELAY
6256. BASE_ADCHS_CLK
6257. BASE_ADDR
6258. BASE_ADDR0
6259. BASE_ADDR1
6260. BASE_ADDRESS
6261. BASE_ADDR_1__BASE_ADDR_MASK
6262. BASE_ADDR_1__BASE_ADDR__MASK
6263. BASE_ADDR_1__BASE_ADDR__SHIFT
6264. BASE_ADDR_2__BASE_ADDR_MASK
6265. BASE_ADDR_2__BASE_ADDR__MASK
6266. BASE_ADDR_2__BASE_ADDR__SHIFT
6267. BASE_ADDR_3__BASE_ADDR_MASK
6268. BASE_ADDR_3__BASE_ADDR__MASK
6269. BASE_ADDR_3__BASE_ADDR__SHIFT
6270. BASE_ADDR_4__BASE_ADDR_MASK
6271. BASE_ADDR_4__BASE_ADDR__MASK
6272. BASE_ADDR_4__BASE_ADDR__SHIFT
6273. BASE_ADDR_5__BASE_ADDR_MASK
6274. BASE_ADDR_5__BASE_ADDR__MASK
6275. BASE_ADDR_5__BASE_ADDR__SHIFT
6276. BASE_ADDR_6__BASE_ADDR_MASK
6277. BASE_ADDR_6__BASE_ADDR__MASK
6278. BASE_ADDR_6__BASE_ADDR__SHIFT
6279. BASE_ADDR_END_FUNC
6280. BASE_AECAGC
6281. BASE_APB1_CLK
6282. BASE_APB3_CLK
6283. BASE_AUDIO_CLK
6284. BASE_BAUD
6285. BASE_CGU_OUT0_CLK
6286. BASE_CGU_OUT1_CLK
6287. BASE_CHAIN
6288. BASE_CHECK
6289. BASE_CLASS
6290. BASE_CLASS__BASE_CLASS_MASK
6291. BASE_CLASS__BASE_CLASS__MASK
6292. BASE_CLASS__BASE_CLASS__SHIFT
6293. BASE_CLK_FREQ_100
6294. BASE_CLK_FREQ_200
6295. BASE_CLK_FREQ_50
6296. BASE_CLK_MAX
6297. BASE_CLOCK
6298. BASE_CODE
6299. BASE_COLOR_SIZE101010
6300. BASE_COLOR_SIZE111
6301. BASE_COLOR_SIZE121212
6302. BASE_COLOR_SIZE222
6303. BASE_COLOR_SIZE332
6304. BASE_COLOR_SIZE333
6305. BASE_COLOR_SIZE444
6306. BASE_COLOR_SIZE555
6307. BASE_COLOR_SIZE565
6308. BASE_COLOR_SIZE666
6309. BASE_COLOR_SIZE888
6310. BASE_COLOR_SIZE_101010
6311. BASE_COLOR_SIZE_111
6312. BASE_COLOR_SIZE_121212
6313. BASE_COLOR_SIZE_222
6314. BASE_COLOR_SIZE_332
6315. BASE_COLOR_SIZE_333
6316. BASE_COLOR_SIZE_444
6317. BASE_COLOR_SIZE_555
6318. BASE_COLOR_SIZE_565
6319. BASE_COLOR_SIZE_666
6320. BASE_COLOR_SIZE_888
6321. BASE_COLOR_SIZE_MASK
6322. BASE_CPU_CLK
6323. BASE_CPU_MASK
6324. BASE_CPU_SHIFT
6325. BASE_DATA
6326. BASE_DEF
6327. BASE_DELAY_INTERVAL
6328. BASE_DIR
6329. BASE_DISCOVER_AGENT
6330. BASE_DISCOVER_IMPLEMENT_VERSION
6331. BASE_DISCOVER_LIST_PROTOCOLS
6332. BASE_DISCOVER_SUB_VENDOR
6333. BASE_DISCOVER_VENDOR
6334. BASE_ENT
6335. BASE_EVEN1
6336. BASE_EVEN2
6337. BASE_EVEN3
6338. BASE_FREQ
6339. BASE_GMAC_1
6340. BASE_GMAC_2
6341. BASE_HIGH_5G_CHAN
6342. BASE_IFACE
6343. BASE_IMG_DISPLAY_CTRL
6344. BASE_INNER
6345. BASE_INTEN_ADDR
6346. BASE_IPI_IRQ
6347. BASE_LCD_CLK
6348. BASE_LOW_5G_CHAN
6349. BASE_MAX
6350. BASE_MID_5G_CHAN
6351. BASE_NOTIFY_ERRORS
6352. BASE_ODD1
6353. BASE_ODD2
6354. BASE_ODD3
6355. BASE_OFFSET
6356. BASE_OUT_CLK
6357. BASE_PAGE1
6358. BASE_PAGE2
6359. BASE_PAGE3
6360. BASE_PAV
6361. BASE_PCI_IRQ
6362. BASE_PERIPH_CLK
6363. BASE_PHY_RX_CLK
6364. BASE_PHY_TX_CLK
6365. BASE_PREFETCH
6366. BASE_PREFIX
6367. BASE_QUEUE_NOT_REQUESTED
6368. BASE_REG
6369. BASE_RES1_CLK
6370. BASE_RES2_CLK
6371. BASE_RES3_CLK
6372. BASE_RES4_CLK
6373. BASE_RX_PORTID
6374. BASE_SAFE_CLK
6375. BASE_SDIO_CLK
6376. BASE_SENDPAGE
6377. BASE_SIGFRAME_SIZE
6378. BASE_SP
6379. BASE_SPIFI_CLK
6380. BASE_SPI_CLK
6381. BASE_SSP0_CLK
6382. BASE_SSP1_CLK
6383. BASE_STACKFRAME
6384. BASE_STD
6385. BASE_SYSFS_ATTR_NO
6386. BASE_TABLE
6387. BASE_TX_PORTID
6388. BASE_TYPES
6389. BASE_UART0_CLK
6390. BASE_UART1_CLK
6391. BASE_UART2_CLK
6392. BASE_UART3_CLK
6393. BASE_UNIT_CONVERSION
6394. BASE_USB0_CLK
6395. BASE_USB1_CLK
6396. BASE_VALID
6397. BASE_VECTORS_V3_HW
6398. BASE_VIDIOC_PRIVATE
6399. BASE_XBOW_PORT
6400. BASE_XMAC_1
6401. BASE_XMAC_2
6402. BASIC
6403. BASIC_BLOCK_FOR_FN
6404. BASIC_DATA_MASK
6405. BASIC_DATA_REG_MASK
6406. BASIC_H_SIZE
6407. BASIC_INTERRUPT
6408. BASIC_MODE
6409. BASIC_MODE_FROM_REG
6410. BASIC_MODE_MASK
6411. BASIC_MODE_REG_FROM_REG
6412. BASIC_MODE_REG_MASK
6413. BASIC_MODE_REG_SHIFT
6414. BASIC_MODE_REG_VALUE
6415. BASIC_MODE_SHIFT
6416. BASIC_RATE
6417. BASIC_TX_RATES
6418. BASR_ACK
6419. BASR_ATN
6420. BASR_BUSY_ERROR
6421. BASR_DRQ
6422. BASR_END_DMA_TRANSFER
6423. BASR_IRQ
6424. BASR_PARITY_ERROR
6425. BASR_PHASE_MATCH
6426. BASS_GPR
6427. BASTREAM_FLAG_DIRECTION_UPSTREAM
6428. BASTREAM_FLAG_IMMEDIATE_TYPE
6429. BAST_ASIXNET_CS
6430. BAST_CPLD_CTLR2_IDERST
6431. BAST_CPLD_CTRL1_LRCADC
6432. BAST_CPLD_CTRL1_LRCARM
6433. BAST_CPLD_CTRL1_LRCDAC
6434. BAST_CPLD_CTRL1_LRCOFF
6435. BAST_CPLD_CTRL1_LRMASK
6436. BAST_CPLD_CTRL2_WNAND
6437. BAST_CPLD_CTRL3_IDMASK
6438. BAST_CPLD_CTRL3_ROMWEN
6439. BAST_CPLD_CTRL4_LCDCMD
6440. BAST_CPLD_CTRL4_LCDE2
6441. BAST_CPLD_CTRL4_LCDRW
6442. BAST_CPLD_CTRL4_LLAT
6443. BAST_CPLD_DMA0_ISA15
6444. BAST_CPLD_DMA0_ISA36
6445. BAST_CPLD_DMA0_PRIIDE
6446. BAST_CPLD_DMA0_SECIDE
6447. BAST_CPLD_DMA1_ISA15
6448. BAST_CPLD_DMA1_ISA36
6449. BAST_CPLD_DMA1_PRIIDE
6450. BAST_CPLD_DMA1_SECIDE
6451. BAST_DM9000_CS
6452. BAST_IDE_CS
6453. BAST_IOADDR
6454. BAST_IRQ_ASIX
6455. BAST_IRQ_DM9000
6456. BAST_IRQ_IDE0
6457. BAST_IRQ_IDE1
6458. BAST_IRQ_ISA
6459. BAST_IRQ_PCPARALLEL
6460. BAST_IRQ_PCSERIAL1
6461. BAST_IRQ_PCSERIAL2
6462. BAST_IRQ_SMALERT
6463. BAST_IRQ_USBOC
6464. BAST_PA_ASIXNET
6465. BAST_PA_CTRL1
6466. BAST_PA_CTRL2
6467. BAST_PA_CTRL3
6468. BAST_PA_CTRL4
6469. BAST_PA_DM9000
6470. BAST_PA_IDEPRI
6471. BAST_PA_IDEPRIAUX
6472. BAST_PA_IDESEC
6473. BAST_PA_IDESECAUX
6474. BAST_PA_ISAIO
6475. BAST_PA_ISAMEM
6476. BAST_PA_LCD_RCMD1
6477. BAST_PA_LCD_RCMD2
6478. BAST_PA_LCD_RDATA1
6479. BAST_PA_LCD_RDATA2
6480. BAST_PA_LCD_WCMD1
6481. BAST_PA_LCD_WCMD2
6482. BAST_PA_LCD_WDATA1
6483. BAST_PA_LCD_WDATA2
6484. BAST_PA_PC104_IRQMASK
6485. BAST_PA_PC104_IRQRAW
6486. BAST_PA_PC104_IRQREQ
6487. BAST_PA_SUPERIO
6488. BAST_PCSIO
6489. BAST_VAM_CS2
6490. BAST_VAM_CS3
6491. BAST_VAM_CS4
6492. BAST_VAM_CS5
6493. BAST_VA_ASIXNET
6494. BAST_VA_CTRL1
6495. BAST_VA_CTRL2
6496. BAST_VA_CTRL3
6497. BAST_VA_CTRL4
6498. BAST_VA_DM9000
6499. BAST_VA_IDEPRI
6500. BAST_VA_IDEPRIAUX
6501. BAST_VA_IDESEC
6502. BAST_VA_IDESECAUX
6503. BAST_VA_ISAIO
6504. BAST_VA_ISAMEM
6505. BAST_VA_LCD_RCMD1
6506. BAST_VA_LCD_RCMD2
6507. BAST_VA_LCD_RDATA1
6508. BAST_VA_LCD_RDATA2
6509. BAST_VA_LCD_WCMD1
6510. BAST_VA_LCD_WCMD2
6511. BAST_VA_LCD_WDATA1
6512. BAST_VA_LCD_WDATA2
6513. BAST_VA_MULTISPACE
6514. BAST_VA_PC104_IRQMASK
6515. BAST_VA_PC104_IRQRAW
6516. BAST_VA_PC104_IRQREQ
6517. BAST_VA_SUPERIO
6518. BAS_CHANNELS
6519. BAS_CORRFRAMES
6520. BAS_FRAMETIME
6521. BAS_HIGHFRAME
6522. BAS_INBUFSIZE
6523. BAS_INURBS
6524. BAS_LOWFRAME
6525. BAS_MAXFRAME
6526. BAS_NORMFRAME
6527. BAS_NUMFRAMES
6528. BAS_OUTBUFPAD
6529. BAS_OUTBUFSIZE
6530. BAS_OUTURBS
6531. BAS_RETRY
6532. BAS_TIMEOUT
6533. BAT
6534. BATADV_ATTR
6535. BATADV_ATTR_ACTIVE
6536. BATADV_ATTR_AGGREGATED_OGMS_ENABLED
6537. BATADV_ATTR_ALGO_NAME
6538. BATADV_ATTR_AP_ISOLATION_ENABLED
6539. BATADV_ATTR_BANDWIDTH_DOWN
6540. BATADV_ATTR_BANDWIDTH_UP
6541. BATADV_ATTR_BLA_ADDRESS
6542. BATADV_ATTR_BLA_BACKBONE
6543. BATADV_ATTR_BLA_CRC
6544. BATADV_ATTR_BLA_OWN
6545. BATADV_ATTR_BLA_VID
6546. BATADV_ATTR_BONDING_ENABLED
6547. BATADV_ATTR_BRIDGE_LOOP_AVOIDANCE_ENABLED
6548. BATADV_ATTR_DAT_CACHE_HWADDRESS
6549. BATADV_ATTR_DAT_CACHE_IP4ADDRESS
6550. BATADV_ATTR_DAT_CACHE_VID
6551. BATADV_ATTR_DISTRIBUTED_ARP_TABLE_ENABLED
6552. BATADV_ATTR_ELP_INTERVAL
6553. BATADV_ATTR_FLAG_BEST
6554. BATADV_ATTR_FRAGMENTATION_ENABLED
6555. BATADV_ATTR_GW_BANDWIDTH_DOWN
6556. BATADV_ATTR_GW_BANDWIDTH_UP
6557. BATADV_ATTR_GW_MODE
6558. BATADV_ATTR_GW_SEL_CLASS
6559. BATADV_ATTR_HARD_ADDRESS
6560. BATADV_ATTR_HARD_IFINDEX
6561. BATADV_ATTR_HARD_IFNAME
6562. BATADV_ATTR_HIF_SHOW_UINT
6563. BATADV_ATTR_HIF_STORE_UINT
6564. BATADV_ATTR_HIF_UINT
6565. BATADV_ATTR_HOP_PENALTY
6566. BATADV_ATTR_ISOLATION_MARK
6567. BATADV_ATTR_ISOLATION_MASK
6568. BATADV_ATTR_LAST_SEEN_MSECS
6569. BATADV_ATTR_LOG_LEVEL
6570. BATADV_ATTR_MAX
6571. BATADV_ATTR_MCAST_FLAGS
6572. BATADV_ATTR_MCAST_FLAGS_PRIV
6573. BATADV_ATTR_MESH_ADDRESS
6574. BATADV_ATTR_MESH_IFINDEX
6575. BATADV_ATTR_MESH_IFNAME
6576. BATADV_ATTR_MULTICAST_FANOUT
6577. BATADV_ATTR_MULTICAST_FORCEFLOOD_ENABLED
6578. BATADV_ATTR_NEIGH_ADDRESS
6579. BATADV_ATTR_NETWORK_CODING_ENABLED
6580. BATADV_ATTR_ORIG_ADDRESS
6581. BATADV_ATTR_ORIG_INTERVAL
6582. BATADV_ATTR_PAD
6583. BATADV_ATTR_ROUTER
6584. BATADV_ATTR_SIF_BOOL
6585. BATADV_ATTR_SIF_SHOW_BOOL
6586. BATADV_ATTR_SIF_SHOW_UINT
6587. BATADV_ATTR_SIF_STORE_BOOL
6588. BATADV_ATTR_SIF_STORE_UINT
6589. BATADV_ATTR_SIF_UINT
6590. BATADV_ATTR_THROUGHPUT
6591. BATADV_ATTR_THROUGHPUT_OVERRIDE
6592. BATADV_ATTR_TPMETER_BYTES
6593. BATADV_ATTR_TPMETER_COOKIE
6594. BATADV_ATTR_TPMETER_RESULT
6595. BATADV_ATTR_TPMETER_TEST_TIME
6596. BATADV_ATTR_TQ
6597. BATADV_ATTR_TT_ADDRESS
6598. BATADV_ATTR_TT_CRC32
6599. BATADV_ATTR_TT_FLAGS
6600. BATADV_ATTR_TT_LAST_TTVN
6601. BATADV_ATTR_TT_TTVN
6602. BATADV_ATTR_TT_VID
6603. BATADV_ATTR_UNSPEC
6604. BATADV_ATTR_VERSION
6605. BATADV_ATTR_VLAN
6606. BATADV_ATTR_VLANID
6607. BATADV_ATTR_VLAN_BOOL
6608. BATADV_ATTR_VLAN_SHOW_BOOL
6609. BATADV_ATTR_VLAN_STORE_BOOL
6610. BATADV_BATMAN_QUEUE_LEN
6611. BATADV_BCAST
6612. BATADV_BCAST_MAX_AGE
6613. BATADV_BCAST_QUEUE_LEN
6614. BATADV_BLA_BACKBONE_TIMEOUT
6615. BATADV_BLA_CLAIM_TIMEOUT
6616. BATADV_BLA_CRC_INIT
6617. BATADV_BLA_LOOPDETECT_PERIODS
6618. BATADV_BLA_LOOPDETECT_TIMEOUT
6619. BATADV_BLA_PERIOD_LENGTH
6620. BATADV_BLA_WAIT_PERIODS
6621. BATADV_BOOTREPLY
6622. BATADV_BW_UNIT_KBIT
6623. BATADV_BW_UNIT_MBIT
6624. BATADV_CLAIM_TYPE_ANNOUNCE
6625. BATADV_CLAIM_TYPE_CLAIM
6626. BATADV_CLAIM_TYPE_LOOPDETECT
6627. BATADV_CLAIM_TYPE_REQUEST
6628. BATADV_CLAIM_TYPE_UNCLAIM
6629. BATADV_CMD_GET_BLA_BACKBONE
6630. BATADV_CMD_GET_BLA_CLAIM
6631. BATADV_CMD_GET_DAT_CACHE
6632. BATADV_CMD_GET_GATEWAYS
6633. BATADV_CMD_GET_HARDIF
6634. BATADV_CMD_GET_HARDIFS
6635. BATADV_CMD_GET_MCAST_FLAGS
6636. BATADV_CMD_GET_MESH
6637. BATADV_CMD_GET_MESH_INFO
6638. BATADV_CMD_GET_NEIGHBORS
6639. BATADV_CMD_GET_ORIGINATORS
6640. BATADV_CMD_GET_ROUTING_ALGOS
6641. BATADV_CMD_GET_TRANSTABLE_GLOBAL
6642. BATADV_CMD_GET_TRANSTABLE_LOCAL
6643. BATADV_CMD_GET_VLAN
6644. BATADV_CMD_MAX
6645. BATADV_CMD_SET_HARDIF
6646. BATADV_CMD_SET_MESH
6647. BATADV_CMD_SET_VLAN
6648. BATADV_CMD_TP_METER
6649. BATADV_CMD_TP_METER_CANCEL
6650. BATADV_CMD_UNSPEC
6651. BATADV_CNT_DAT_CACHED_REPLY_TX
6652. BATADV_CNT_DAT_GET_RX
6653. BATADV_CNT_DAT_GET_TX
6654. BATADV_CNT_DAT_PUT_RX
6655. BATADV_CNT_DAT_PUT_TX
6656. BATADV_CNT_FORWARD
6657. BATADV_CNT_FORWARD_BYTES
6658. BATADV_CNT_FRAG_FWD
6659. BATADV_CNT_FRAG_FWD_BYTES
6660. BATADV_CNT_FRAG_RX
6661. BATADV_CNT_FRAG_RX_BYTES
6662. BATADV_CNT_FRAG_TX
6663. BATADV_CNT_FRAG_TX_BYTES
6664. BATADV_CNT_MGMT_RX
6665. BATADV_CNT_MGMT_RX_BYTES
6666. BATADV_CNT_MGMT_TX
6667. BATADV_CNT_MGMT_TX_BYTES
6668. BATADV_CNT_NC_BUFFER
6669. BATADV_CNT_NC_CODE
6670. BATADV_CNT_NC_CODE_BYTES
6671. BATADV_CNT_NC_DECODE
6672. BATADV_CNT_NC_DECODE_BYTES
6673. BATADV_CNT_NC_DECODE_FAILED
6674. BATADV_CNT_NC_RECODE
6675. BATADV_CNT_NC_RECODE_BYTES
6676. BATADV_CNT_NC_SNIFFED
6677. BATADV_CNT_NUM
6678. BATADV_CNT_RX
6679. BATADV_CNT_RX_BYTES
6680. BATADV_CNT_TT_REQUEST_RX
6681. BATADV_CNT_TT_REQUEST_TX
6682. BATADV_CNT_TT_RESPONSE_RX
6683. BATADV_CNT_TT_RESPONSE_TX
6684. BATADV_CNT_TT_ROAM_ADV_RX
6685. BATADV_CNT_TT_ROAM_ADV_TX
6686. BATADV_CNT_TX
6687. BATADV_CNT_TX_BYTES
6688. BATADV_CNT_TX_DROPPED
6689. BATADV_CODED
6690. BATADV_COMPAT_VERSION
6691. BATADV_DAT_ADDR_MAX
6692. BATADV_DAT_CANDIDATES_NUM
6693. BATADV_DAT_CANDIDATE_NOT_FOUND
6694. BATADV_DAT_CANDIDATE_ORIG
6695. BATADV_DAT_ENTRY_TIMEOUT
6696. BATADV_DBG_ALL
6697. BATADV_DBG_BATMAN
6698. BATADV_DBG_BLA
6699. BATADV_DBG_DAT
6700. BATADV_DBG_MCAST
6701. BATADV_DBG_NC
6702. BATADV_DBG_ROUTES
6703. BATADV_DBG_TP_METER
6704. BATADV_DBG_TT
6705. BATADV_DEBUGFS_SUBDIR
6706. BATADV_DEBUGINFO
6707. BATADV_DESTINATION_UNREACHABLE
6708. BATADV_DHCPACK
6709. BATADV_DHCP_CHADDR_LEN
6710. BATADV_DHCP_CHADDR_OFFSET
6711. BATADV_DHCP_HLEN_OFFSET
6712. BATADV_DHCP_HTYPE_ETHERNET
6713. BATADV_DHCP_HTYPE_OFFSET
6714. BATADV_DHCP_MAGIC
6715. BATADV_DHCP_NO
6716. BATADV_DHCP_OPT_END
6717. BATADV_DHCP_OPT_MSG_TYPE
6718. BATADV_DHCP_OPT_PAD
6719. BATADV_DHCP_TO_CLIENT
6720. BATADV_DHCP_TO_SERVER
6721. BATADV_DHCP_YIADDR_LEN
6722. BATADV_DIRECTLINK
6723. BATADV_DRIVER_AUTHOR
6724. BATADV_DRIVER_DESC
6725. BATADV_DRIVER_DEVICE
6726. BATADV_DUPLIST_SIZE
6727. BATADV_DUPLIST_TIMEOUT
6728. BATADV_ECHO_REPLY
6729. BATADV_ECHO_REQUEST
6730. BATADV_ELP
6731. BATADV_ELP_HLEN
6732. BATADV_ELP_MAX_AGE
6733. BATADV_ELP_MIN_PROBE_SIZE
6734. BATADV_ELP_PROBES_PER_NODE
6735. BATADV_ELP_PROBE_MAX_TX_DIFF
6736. BATADV_EXPECTED_SEQNO_RANGE
6737. BATADV_FLAG_NEED_HARDIF
6738. BATADV_FLAG_NEED_MESH
6739. BATADV_FLAG_NEED_VLAN
6740. BATADV_FORW_ALL
6741. BATADV_FORW_NONE
6742. BATADV_FORW_SINGLE
6743. BATADV_FORW_SOME
6744. BATADV_FRAG_BUFFER_COUNT
6745. BATADV_FRAG_MAX_FRAGMENTS
6746. BATADV_FRAG_MAX_FRAG_SIZE
6747. BATADV_FRAG_TIMEOUT
6748. BATADV_FULL_DUPLEX
6749. BATADV_GW_MODE_CLIENT
6750. BATADV_GW_MODE_CLIENT_NAME
6751. BATADV_GW_MODE_OFF
6752. BATADV_GW_MODE_OFF_NAME
6753. BATADV_GW_MODE_SERVER
6754. BATADV_GW_MODE_SERVER_NAME
6755. BATADV_GW_THRESHOLD
6756. BATADV_HARDIF_BCAST_DUPFWD
6757. BATADV_HARDIF_BCAST_DUPORIG
6758. BATADV_HARDIF_BCAST_NORECIPIENT
6759. BATADV_HARDIF_BCAST_OK
6760. BATADV_HARDIF_DEBUGINFO
6761. BATADV_HARDIF_WIFI_CFG80211_DIRECT
6762. BATADV_HARDIF_WIFI_CFG80211_INDIRECT
6763. BATADV_HARDIF_WIFI_WEXT_DIRECT
6764. BATADV_HARDIF_WIFI_WEXT_INDIRECT
6765. BATADV_HTYPE_ETHERNET
6766. BATADV_ICMP
6767. BATADV_ICMP_MAX_PACKET_SIZE
6768. BATADV_ICMP_SOCKET
6769. BATADV_IF_ACTIVE
6770. BATADV_IF_CLEANUP_AUTO
6771. BATADV_IF_CLEANUP_KEEP
6772. BATADV_IF_DEFAULT
6773. BATADV_IF_INACTIVE
6774. BATADV_IF_I_WANT_YOU
6775. BATADV_IF_NOT_IN_USE
6776. BATADV_IF_TO_BE_ACTIVATED
6777. BATADV_IF_TO_BE_REMOVED
6778. BATADV_IV_OGM
6779. BATADV_JITTER
6780. BATADV_LOG_BUFF_MASK
6781. BATADV_LOG_BUF_LEN
6782. BATADV_MAX_AGGREGATION_BYTES
6783. BATADV_MAX_AGGREGATION_MS
6784. BATADV_MAX_MSG_LEN
6785. BATADV_MCAST_FLAGS_BRIDGED
6786. BATADV_MCAST_FLAGS_QUERIER_IPV4_EXISTS
6787. BATADV_MCAST_FLAGS_QUERIER_IPV4_SHADOWING
6788. BATADV_MCAST_FLAGS_QUERIER_IPV6_EXISTS
6789. BATADV_MCAST_FLAGS_QUERIER_IPV6_SHADOWING
6790. BATADV_MCAST_WANT_ALL_IPV4
6791. BATADV_MCAST_WANT_ALL_IPV6
6792. BATADV_MCAST_WANT_ALL_UNSNOOPABLES
6793. BATADV_MCAST_WANT_NO_RTR4
6794. BATADV_MCAST_WANT_NO_RTR6
6795. BATADV_MCAST_WORK_PERIOD
6796. BATADV_MESH_ACTIVE
6797. BATADV_MESH_DEACTIVATING
6798. BATADV_MESH_INACTIVE
6799. BATADV_NC_NODE_TIMEOUT
6800. BATADV_NEIGH_DUP
6801. BATADV_NL_MCAST_GROUP_CONFIG
6802. BATADV_NL_MCAST_GROUP_TPMETER
6803. BATADV_NL_MCGRP_CONFIG
6804. BATADV_NL_MCGRP_TPMETER
6805. BATADV_NL_NAME
6806. BATADV_NOT_BEST_NEXT_HOP
6807. BATADV_NO_DUP
6808. BATADV_NO_FLAGS
6809. BATADV_NO_MARK
6810. BATADV_NULL_IFINDEX
6811. BATADV_NUM_BCASTS_DEFAULT
6812. BATADV_NUM_BCASTS_MAX
6813. BATADV_NUM_BCASTS_WIRELESS
6814. BATADV_NUM_WORDS
6815. BATADV_OGM2
6816. BATADV_OGM2_HLEN
6817. BATADV_OGM_HLEN
6818. BATADV_OGM_MAX_AGE
6819. BATADV_OGM_MAX_ORIGDIFF
6820. BATADV_ORIG_CAPA_HAS_DAT
6821. BATADV_ORIG_CAPA_HAS_MCAST
6822. BATADV_ORIG_CAPA_HAS_NC
6823. BATADV_ORIG_CAPA_HAS_TT
6824. BATADV_ORIG_DUP
6825. BATADV_ORIG_WORK_PERIOD
6826. BATADV_PARAMETER_PROBLEM
6827. BATADV_PRIMARIES_FIRST_HOP
6828. BATADV_PROTECTED
6829. BATADV_PURGE_TIMEOUT
6830. BATADV_P_DATA
6831. BATADV_P_DAT_CACHE_REPLY
6832. BATADV_P_DAT_DHT_GET
6833. BATADV_P_DAT_DHT_PUT
6834. BATADV_RESET_PROTECTION_MS
6835. BATADV_ROAMING_MAX_COUNT
6836. BATADV_ROAMING_MAX_TIME
6837. BATADV_RR_LEN
6838. BATADV_SKB_CB
6839. BATADV_SOURCE_VERSION
6840. BATADV_SYSFS_IF_BAT_SUBDIR
6841. BATADV_SYSFS_IF_MESH_SUBDIR
6842. BATADV_SYSFS_VLAN_SUBDIR_PREFIX
6843. BATADV_THROUGHPUT_DEFAULT_VALUE
6844. BATADV_THROUGHPUT_MAX_VALUE
6845. BATADV_TP
6846. BATADV_TP_ACK
6847. BATADV_TP_AWND
6848. BATADV_TP_DEF_TEST_LENGTH
6849. BATADV_TP_FIRST_SEQ
6850. BATADV_TP_MAX_NUM
6851. BATADV_TP_MAX_RTO
6852. BATADV_TP_MSG
6853. BATADV_TP_PACKET_LEN
6854. BATADV_TP_PLEN
6855. BATADV_TP_REASON_ALREADY_ONGOING
6856. BATADV_TP_REASON_CANCEL
6857. BATADV_TP_REASON_CANT_SEND
6858. BATADV_TP_REASON_COMPLETE
6859. BATADV_TP_REASON_DST_UNREACHABLE
6860. BATADV_TP_REASON_MEMORY_ERROR
6861. BATADV_TP_REASON_RESEND_LIMIT
6862. BATADV_TP_REASON_TOO_MANY
6863. BATADV_TP_RECEIVER
6864. BATADV_TP_RECV_TIMEOUT
6865. BATADV_TP_SENDER
6866. BATADV_TQ_GLOBAL_WINDOW_SIZE
6867. BATADV_TQ_LOCAL_BIDRECT_RECV_MINIMUM
6868. BATADV_TQ_LOCAL_BIDRECT_SEND_MINIMUM
6869. BATADV_TQ_LOCAL_WINDOW_SIZE
6870. BATADV_TQ_MAX_VALUE
6871. BATADV_TQ_SIMILARITY_THRESHOLD
6872. BATADV_TQ_TOTAL_BIDRECT_LIMIT
6873. BATADV_TTL
6874. BATADV_TTL_EXCEEDED
6875. BATADV_TT_CLIENT_DEL
6876. BATADV_TT_CLIENT_ISOLA
6877. BATADV_TT_CLIENT_NEW
6878. BATADV_TT_CLIENT_NOPURGE
6879. BATADV_TT_CLIENT_PENDING
6880. BATADV_TT_CLIENT_ROAM
6881. BATADV_TT_CLIENT_ROAM_TIMEOUT
6882. BATADV_TT_CLIENT_TEMP
6883. BATADV_TT_CLIENT_TEMP_TIMEOUT
6884. BATADV_TT_CLIENT_WIFI
6885. BATADV_TT_DATA_TYPE_MASK
6886. BATADV_TT_FULL_TABLE
6887. BATADV_TT_LOCAL_TIMEOUT
6888. BATADV_TT_OGM_APPEND_MAX
6889. BATADV_TT_OGM_DIFF
6890. BATADV_TT_REMOTE_MASK
6891. BATADV_TT_REQUEST
6892. BATADV_TT_REQUEST_TIMEOUT
6893. BATADV_TT_RESPONSE
6894. BATADV_TT_SYNC_MASK
6895. BATADV_TT_WORK_PERIOD
6896. BATADV_TVLV_DAT
6897. BATADV_TVLV_GW
6898. BATADV_TVLV_HANDLER_OGM_CALLED
6899. BATADV_TVLV_HANDLER_OGM_CIFNOTFND
6900. BATADV_TVLV_MCAST
6901. BATADV_TVLV_NC
6902. BATADV_TVLV_ROAM
6903. BATADV_TVLV_TT
6904. BATADV_UEV_ACTION_VAR
6905. BATADV_UEV_ADD
6906. BATADV_UEV_BLA
6907. BATADV_UEV_CHANGE
6908. BATADV_UEV_DATA_VAR
6909. BATADV_UEV_DEL
6910. BATADV_UEV_GW
6911. BATADV_UEV_LOOPDETECT
6912. BATADV_UEV_TYPE_VAR
6913. BATADV_UNICAST
6914. BATADV_UNICAST_4ADDR
6915. BATADV_UNICAST_FRAG
6916. BATADV_UNICAST_MAX
6917. BATADV_UNICAST_MIN
6918. BATADV_UNICAST_TVLV
6919. BATADV_VLAN_HAS_TAG
6920. BATADV_WARNING_DEFAULT
6921. BATCH
6922. BATCHREFILL_LIMIT
6923. BATCH_ARG_NB_MAX
6924. BATCH_BUFFER
6925. BATCH_BUFFER_2ND_LEVEL
6926. BATCH_BUFFER_2ND_LEVEL_BIT
6927. BATCH_BUFFER_ADDR_HIGH_MASK
6928. BATCH_BUFFER_ADDR_MASK
6929. BATCH_BUFFER_ADR_SPACE_BIT
6930. BATCH_BUFFER_INSTRUCTION
6931. BATCH_CMD
6932. BATCH_COMPLETE
6933. BATCH_INPUT_ADDR
6934. BATCH_LINE_LEN_MAX
6935. BATCH_OFFSET_BIAS
6936. BATCH_OUTPUT_ADDR
6937. BATCH_OUTPUT_SIZE
6938. BATCH_SCAN
6939. BATCH_SIZE
6940. BATCH_SUBMIT
6941. BATCH_ZAP_PAGES
6942. BATDETECT_INTR_OFFSET
6943. BATTERY_1_DISABLED
6944. BATTERY_1_FAILURE
6945. BATTERY_2_DISABLED
6946. BATTERY_2_FAILURE
6947. BATTERY_AC_ONLINE
6948. BATTERY_CAPACITY
6949. BATTERY_CHARGE_COUNTER
6950. BATTERY_CHARGE_DONE
6951. BATTERY_CHARGE_FAIL
6952. BATTERY_CHARGE_FULL_UAH
6953. BATTERY_CHARGE_INPROG
6954. BATTERY_CHARGE_MASK
6955. BATTERY_CHARGING
6956. BATTERY_CURRENT_AVG
6957. BATTERY_CURRENT_MAX
6958. BATTERY_CURRENT_NOW
6959. BATTERY_CYCLESTATE
6960. BATTERY_CYCLES_EXCEEDED
6961. BATTERY_CYCLE_COUNT
6962. BATTERY_DISCHARGING
6963. BATTERY_FULL_CHARGED
6964. BATTERY_FULL_DISCHARGED
6965. BATTERY_GOOD
6966. BATTERY_HEALTH
6967. BATTERY_INITIALIZED
6968. BATTERY_INT_ENABLE
6969. BATTERY_INT_MASK
6970. BATTERY_INT_STATUS
6971. BATTERY_LEVEL_MAX
6972. BATTERY_LOW
6973. BATTERY_LOW_VOLTAGE
6974. BATTERY_MODE_AMPS
6975. BATTERY_MODE_CAP_MULT_WATT
6976. BATTERY_MODE_MASK
6977. BATTERY_MODE_OFFSET
6978. BATTERY_MODE_WATTS
6979. BATTERY_MODULE_MISSING
6980. BATTERY_NO_REPORT
6981. BATTERY_ODT_MASK
6982. BATTERY_PACK_MISSING
6983. BATTERY_PERCENTAGE
6984. BATTERY_POLLING_COUNT
6985. BATTERY_PRESENT
6986. BATTERY_REMAINING
6987. BATTERY_REPORT_ID
6988. BATTERY_REPORT_SIZE
6989. BATTERY_STATUS
6990. BATTERY_STATUS_CHANGED
6991. BATTERY_STAT_CHARGING
6992. BATTERY_STAT_DISCONNECT
6993. BATTERY_STAT_FULL
6994. BATTERY_TEMP
6995. BATTERY_TEMP_HIGH
6996. BATTERY_UNKNOWN
6997. BATTERY_VENDOR_PARAM_MODE_GET
6998. BATTERY_VENDOR_PARAM_MODE_SET
6999. BATTERY_VOLTAGE
7000. BATTERY_VOLTAGE_MAX
7001. BATTERY_WARNING_TIME
7002. BATTRY_IRQ
7003. BATT_OK_INCREMENT
7004. BATT_OK_MAX_NR_INCREMENTS
7005. BATT_OK_MIN
7006. BATT_OVV
7007. BATT_OVV_ENA
7008. BATT_OVV_TH_3P7
7009. BATT_OVV_TH_4P75
7010. BATT_OVV_VALUE
7011. BATT_PERIOD
7012. BAT_ADDR_MFR_TYPE
7013. BAT_ANY
7014. BAT_CAPACITY
7015. BAT_CHARGE_DESIGN
7016. BAT_CHARGE_LIMIT
7017. BAT_CHARGE_LIMIT_MAX
7018. BAT_CHARGE_NOW
7019. BAT_CHRG_CURR
7020. BAT_CTRL
7021. BAT_CTRL_16U_ENA
7022. BAT_CTRL_18U_ENA
7023. BAT_CTRL_20U_ENA
7024. BAT_CTRL_7U_ENA
7025. BAT_CTRL_AND_IBAT
7026. BAT_CTRL_CMP_ENA
7027. BAT_CTRL_PULL_UP_ENA
7028. BAT_CURRENT_AVG
7029. BAT_CURRENT_NOW
7030. BAT_DEAD_EN
7031. BAT_DEAD_ST_CHG
7032. BAT_D_CURR
7033. BAT_ERR_ACR_FAIL
7034. BAT_ERR_GAUGESTOP
7035. BAT_ERR_ID_FAIL
7036. BAT_ERR_INFOFAIL
7037. BAT_ERR_OUT_OF_CONTROL
7038. BAT_ERR_OVERTEMP
7039. BAT_ERR_OVERVOLTAGE
7040. BAT_MANUFACTURER_NAME_ADDR
7041. BAT_MANUFACTURER_NAME_LEN
7042. BAT_MODEL_NAME_ADDR
7043. BAT_MODEL_NAME_LEN
7044. BAT_PHYS_ADDR
7045. BAT_POLL_INTERVAL
7046. BAT_POWER
7047. BAT_PRIMARY
7048. BAT_S0_AC
7049. BAT_S0_CHARGING
7050. BAT_S0_DISCHARGE
7051. BAT_S0_DISCHRG_CRITICAL
7052. BAT_S0_LOW
7053. BAT_S1_EMPTY
7054. BAT_S1_EXISTS
7055. BAT_S1_FULL
7056. BAT_S1_LiION_OR_NiMH
7057. BAT_S2_LOW_LOW
7058. BAT_SAFE_ENTER_IRQ
7059. BAT_SAFE_QUIT_IRQ
7060. BAT_SECONDARY
7061. BAT_SERIAL_NUMBER_ADDR
7062. BAT_SERIAL_NUMBER_LEN
7063. BAT_SHOW_601
7064. BAT_SHOW_603
7065. BAT_STATUS0
7066. BAT_STATUS1
7067. BAT_STATUS2
7068. BAT_STAT_AC
7069. BAT_STAT_CHARGING
7070. BAT_STAT_DESTROY
7071. BAT_STAT_DISCHARGING
7072. BAT_STAT_FULL
7073. BAT_STAT_LOW
7074. BAT_STAT_PRESENT
7075. BAT_STAT_TRICKLE
7076. BAT_STOP_CHARGE1
7077. BAT_STOP_CHARGE2
7078. BAT_STOP_CHRG1_BAD_CELL
7079. BAT_STOP_CHRG1_COMM_FAIL
7080. BAT_STOP_CHRG1_OVERTEMPERATURE
7081. BAT_STOP_CHRG1_OVERVOLTAGE
7082. BAT_TEMP
7083. BAT_TEMP_AND_IBAT
7084. BAT_TEMP_AVG
7085. BAT_VOLT
7086. BAT_VOLTAGE_DESIGN
7087. BAT_VOLTAGE_NOW
7088. BAT_WAR_CHG
7089. BAT_WAR_EN
7090. BAT_WU_LOG
7091. BAUDR_SCKDV_MAX
7092. BAUDR_SCKDV_MIN
7093. BAUD_BASE
7094. BAUD_DIVISOR
7095. BAUD_MASK
7096. BAUD_RATE_DEFAULT
7097. BAUD_RATE_GEN_FREQ
7098. BAUD_TABLE_LIMIT
7099. BAU_DESC_QUALIFIER
7100. BAU_MISC_CONTROL_MULT_MASK
7101. BAU_TRANS_MASK
7102. BAU_TRANS_SHIFT
7103. BAU_URGENCY_7_MASK
7104. BAU_URGENCY_7_SHIFT
7105. BAVG
7106. BAW_WITHIN
7107. BAYCOM
7108. BAYCOMCTL_GETDEBUG
7109. BAYCOM_DEBUG
7110. BAYCOM_MAGIC
7111. BAYCOM_OPTIONS_SOFTDCD
7112. BAYER_CONTOUR_CABLE_PID
7113. BAYER_HEIGHT_ALIGN
7114. BAYER_VID
7115. BAYER_WIDTH_ALIGN
7116. BA_ACTION
7117. BA_BYTE_LEN
7118. BA_FRAME_TIMEOUT
7119. BA_NOTIF
7120. BA_POLICY_DELAYED
7121. BA_POLICY_IMMEDIATE
7122. BA_QUEUE
7123. BA_RESULT_SUCCESS
7124. BA_RESULT_TIMEOUT
7125. BA_RJT_REASON_CODE_INVALID_COMMAND
7126. BA_RJT_REASON_CODE_UNABLE_TO_PERFORM
7127. BA_SESSION_RX_CONSTRAINT_EVENT_ID
7128. BA_SETUPT
7129. BA_SETUP_COMPLETE
7130. BA_SETUP_INPROGRESS
7131. BA_SETUP_MAX_PACKET_THRESHOLD
7132. BA_SETUP_NONE
7133. BA_SETUP_PACKET_OFFSET
7134. BA_SETUP_TIMEOUT
7135. BA_SIZE_BYTE
7136. BA_SIZE_LINE
7137. BA_SIZE_LONG
7138. BA_SIZE_WORD
7139. BA_STREAM_NOT_ALLOWED
7140. BA_TT_MOVE16
7141. BA_WINDOW_STATUS_NOTIFICATION_ID
7142. BA_WINDOW_STATUS_STA_ID_MSK
7143. BA_WINDOW_STATUS_STA_ID_POS
7144. BA_WINDOW_STATUS_TID_MSK
7145. BA_WINDOW_STATUS_VALID_MSK
7146. BA_WINDOW_STREAMS_MAX
7147. BB
7148. BB1_PROTECTED
7149. BB1_START_ADDR_MASK
7150. BB1_UNPROTECTED
7151. BB2_END_ADDR_MASK
7152. BBA
7153. BBADDR
7154. BBANDGAP_MBIAS_POWERUP
7155. BBANDSELECT
7156. BBAddr
7157. BBBCCKSTART
7158. BBBRESETB
7159. BBBSTART
7160. BBCFG_RESETCCA
7161. BBCFG_RESETRX
7162. BBCH_BBSEL_MASK
7163. BBCH_BBSEL_SHIFT
7164. BBC_AID
7165. BBC_AID_ID
7166. BBC_AID_RESV
7167. BBC_ARB
7168. BBC_ARB_CPU0
7169. BBC_ARB_CPU1
7170. BBC_ARB_CPU2
7171. BBC_ARB_CPU3
7172. BBC_ARB_RESV
7173. BBC_CSC
7174. BBC_CSC_RESV
7175. BBC_CSC_RST
7176. BBC_CSC_SCLOCK
7177. BBC_CSC_SDATA
7178. BBC_CSC_SLOAD
7179. BBC_DEVP
7180. BBC_DEVP_CPU0
7181. BBC_DEVP_CPU1
7182. BBC_DEVP_CPU2
7183. BBC_DEVP_CPU3
7184. BBC_DEVP_RESV
7185. BBC_EBUST
7186. BBC_ES_ABT
7187. BBC_ES_ABT_VAL
7188. BBC_ES_ACT
7189. BBC_ES_ACT_VAL
7190. BBC_ES_CTRL
7191. BBC_ES_CTRL_1_1
7192. BBC_ES_CTRL_1_2
7193. BBC_ES_CTRL_1_32
7194. BBC_ES_DABT
7195. BBC_ES_DACT
7196. BBC_ES_FSL
7197. BBC_ES_FSL_VAL
7198. BBC_ES_PST
7199. BBC_ES_PST_VAL
7200. BBC_ES_RESV
7201. BBC_I2C_0_S0
7202. BBC_I2C_0_S1
7203. BBC_I2C_1_S0
7204. BBC_I2C_1_S1
7205. BBC_I2C_SEL
7206. BBC_JTAG_CMD
7207. BBC_JTAG_CTRL
7208. BBC_KBC_BCNT_RESV
7209. BBC_KBD_BCNT
7210. BBC_KBD_BCNT_BITS
7211. BBC_KBD_BEEP
7212. BBC_KBD_BEEP_ENABLE
7213. BBC_KBD_BEEP_RESV
7214. BBC_PSRC
7215. BBC_PSRC_BUTTON
7216. BBC_PSRC_FE0
7217. BBC_PSRC_FE1
7218. BBC_PSRC_FE2
7219. BBC_PSRC_FE3
7220. BBC_PSRC_FE4
7221. BBC_PSRC_FE5
7222. BBC_PSRC_FE6
7223. BBC_PSRC_JTAG
7224. BBC_PSRC_PWRUP
7225. BBC_PSRC_RSC
7226. BBC_PSRC_SPG0
7227. BBC_PSRC_SPG1
7228. BBC_PSRC_SPG2
7229. BBC_PSRC_SPG3
7230. BBC_PSRC_SPGSYS
7231. BBC_PSRC_SYNTH
7232. BBC_PSRC_WDT
7233. BBC_QUIESCE
7234. BBC_QUIESCE_B02
7235. BBC_QUIESCE_B13
7236. BBC_QUIESCE_FD0
7237. BBC_QUIESCE_FD1
7238. BBC_QUIESCE_FD2
7239. BBC_QUIESCE_FD3
7240. BBC_QUIESCE_S02
7241. BBC_QUIESCE_S13
7242. BBC_REGS_SIZE
7243. BBC_SPG
7244. BBC_SPG_CPU0
7245. BBC_SPG_CPU1
7246. BBC_SPG_CPU2
7247. BBC_SPG_CPU3
7248. BBC_SPG_CPUALL
7249. BBC_SPG_RESV
7250. BBC_SXG
7251. BBC_SXG_CPU0
7252. BBC_SXG_CPU1
7253. BBC_SXG_CPU2
7254. BBC_SXG_CPU3
7255. BBC_SXG_RESV
7256. BBC_WDACTION
7257. BBC_WDACTION_RESV
7258. BBC_WDACTION_RST
7259. BBC_XSRC
7260. BBC_XSRC_JTAG
7261. BBC_XSRC_RESV
7262. BBC_XSRC_SXG0
7263. BBC_XSRC_SXG1
7264. BBC_XSRC_SXG2
7265. BBC_XSRC_SXG3
7266. BBC_XSRC_W_OR_B
7267. BBDMAC
7268. BBDMAC_0_3
7269. BBDMAC_11_14
7270. BBDMAC_15_18
7271. BBDMAC_19_22
7272. BBDMAC_23_26
7273. BBDMAC_27
7274. BBDMAC_28
7275. BBDMAC_29
7276. BBDMAC_30
7277. BBDMAC_31
7278. BBDMAC_4_7
7279. BBDMAC_8_10
7280. BBFCRCKO0
7281. BBFCRCKO1
7282. BBGVMIN
7283. BBIF1_FLOW_MARK
7284. BBIF1_RSCK_MARK
7285. BBIF1_RSYNC_MARK
7286. BBIF1_RXD_MARK
7287. BBIF1_RX_FLOW_N_MARK
7288. BBIF1_SS1_MARK
7289. BBIF1_SS2_MARK
7290. BBIF1_TSCK_MARK
7291. BBIF1_TSYNC_MARK
7292. BBIF1_TXD_MARK
7293. BBIF2_RXD2_PORT60_MARK
7294. BBIF2_RXD2_PORT90_MARK
7295. BBIF2_RXD_MARK
7296. BBIF2_SCK_MARK
7297. BBIF2_SYNC_MARK
7298. BBIF2_TSCK1_MARK
7299. BBIF2_TSCK2_MARK
7300. BBIF2_TSCK2_PORT59_MARK
7301. BBIF2_TSCK2_PORT89_MARK
7302. BBIF2_TSYNC1_MARK
7303. BBIF2_TSYNC2_MARK
7304. BBIF2_TSYNC2_PORT184_MARK
7305. BBIF2_TSYNC2_PORT6_MARK
7306. BBIF2_TXD1_MARK
7307. BBIF2_TXD2_MARK
7308. BBIF2_TXD2_PORT183_MARK
7309. BBIF2_TXD2_PORT5_MARK
7310. BBIF2_TXD_MARK
7311. BBINI_RDY
7312. BBLT_SOLID_FILL
7313. BBMASK
7314. BBM_SIZE
7315. BBO
7316. BBOAT2CB_MASK
7317. BBOATBI_MASK
7318. BBOATCB_MASK
7319. BBOAT_MASK
7320. BBOCB
7321. BBOCB_MASK
7322. BBOYBI_MASK
7323. BBOYCB_MASK
7324. BBOY_MASK
7325. BBO_MASK
7326. BBP105_DETECT_SIG_ON_PRIMARY
7327. BBP105_FEQ
7328. BBP105_MLD
7329. BBP105_SIG_REMODULATION
7330. BBP109_TX0_POWER
7331. BBP109_TX1_POWER
7332. BBP110_TX2_POWER
7333. BBP138_RX_ADC1
7334. BBP138_RX_ADC2
7335. BBP138_TX_DAC1
7336. BBP138_TX_DAC2
7337. BBP152_RX_DEFAULT_ANT
7338. BBP1_TX_ANTENNA
7339. BBP1_TX_POWER_CTRL
7340. BBP254_BIT7
7341. BBP27_RX_CHAIN_SEL
7342. BBP3_ADC_INIT_MODE
7343. BBP3_ADC_MODE_SWITCH
7344. BBP3_HT40_MINUS
7345. BBP3_RX_ADC
7346. BBP3_RX_ANTENNA
7347. BBP47_TSSI_ADC6
7348. BBP47_TSSI_REPORT_SEL
7349. BBP47_TSSI_TSSI_MODE
7350. BBP47_TSSI_UPDATE_REQ
7351. BBP49_UPDATE_FLAG
7352. BBP4_BANDWIDTH
7353. BBP4_MAC_IF_CTRL
7354. BBP4_TX_BF
7355. BBPCSR
7356. BBPCSR1
7357. BBPCSR1_CCK
7358. BBPCSR1_CCK_FLIP
7359. BBPCSR1_OFDM
7360. BBPCSR1_OFDM_FLIP
7361. BBPCSR_BUSY
7362. BBPCSR_REGNUM
7363. BBPCSR_VALUE
7364. BBPCSR_WRITE_CONTROL
7365. BBPPCSR
7366. BBP_BASE
7367. BBP_CSR_CFG
7368. BBP_CSR_CFG_BBP_PAR_DUR
7369. BBP_CSR_CFG_BBP_RW_MODE
7370. BBP_CSR_CFG_BUSY
7371. BBP_CSR_CFG_READ_CONTROL
7372. BBP_CSR_CFG_REGNUM
7373. BBP_CSR_CFG_VALUE
7374. BBP_INFO_40MHZ
7375. BBP_PROG_IN_TA
7376. BBP_PTR
7377. BBP_R14_RX_ANTENNA
7378. BBP_R14_RX_IQ_FLIP
7379. BBP_R1_TX_ANTENNA
7380. BBP_R2_BG_MODE
7381. BBP_R2_TX_ANTENNA
7382. BBP_R2_TX_IQ_FLIP
7383. BBP_R3_SMART_MODE
7384. BBP_R47_FLAG
7385. BBP_R47_F_PKT_T
7386. BBP_R47_F_TEMP
7387. BBP_R47_F_TSSI
7388. BBP_R47_F_TX_RATE
7389. BBP_R4_RX_ANTENNA
7390. BBP_R4_RX_ANTENNA_CONTROL
7391. BBP_R4_RX_FRAME_END
7392. BBP_R70_JAPAN_FILTER
7393. BBP_R77_RX_ANTENNA
7394. BBP_REG_WRITE
7395. BBP_SIZE
7396. BBP_TABLE
7397. BBP_TYPE_DEF
7398. BBP_TYPE_MAX
7399. BBP_TYPE_MIN
7400. BBREG2_CCA_MODE_MASK
7401. BBREG2_CCA_MODE_SHIFT
7402. BBREGCTL_DONE
7403. BBREGCTL_REGR
7404. BBREGCTL_REGW
7405. BBRSTN
7406. BBR_DRAIN
7407. BBR_PROBE_BW
7408. BBR_PROBE_RTT
7409. BBR_SCALE
7410. BBR_STARTUP
7411. BBR_UNIT
7412. BBSHIFT
7413. BBSIZE
7414. BBSWING
7415. BBTOB
7416. BBTR
7417. BBT_BLOCK_FACTORY_BAD
7418. BBT_BLOCK_GOOD
7419. BBT_BLOCK_RESERVED
7420. BBT_BLOCK_WORN
7421. BBT_ENTRY_MASK
7422. BBT_ENTRY_SHIFT
7423. BBU_AVG_NOISE_VAL
7424. BBU_RXRDY_CNT_REG
7425. BBW_OPTION
7426. BBW_SEARCH_L
7427. BBW_TH
7428. BBYTE0
7429. BBYTE1
7430. BBYTE2
7431. BBYTE3
7432. BB_ACK
7433. BB_ACK_MASK
7434. BB_ALPF_BANDSELECT
7435. BB_ANTATTEN_CHAN14
7436. BB_ANTENNA_B
7437. BB_BUF
7438. BB_BUF_OA
7439. BB_BUF_PROG_VALUES_REQ
7440. BB_CFG
7441. BB_DARWIN
7442. BB_DLPF_BANDSEL
7443. BB_END
7444. BB_GET_BIT
7445. BB_GET_BIT2
7446. BB_GLB_RSTN
7447. BB_GLOBAL_RESET
7448. BB_GLOBAL_RESET_BIT
7449. BB_HOST_BANG
7450. BB_HOST_BANG_CLK
7451. BB_HOST_BANG_DATA
7452. BB_HOST_BANG_EN
7453. BB_HOST_BANG_RW
7454. BB_INITSTATE_DLPF_TUNE
7455. BB_IQSWAP
7456. BB_LEDS
7457. BB_LEN
7458. BB_LEN_MASK
7459. BB_LOCAL_BASE
7460. BB_MAGIC
7461. BB_MAKE
7462. BB_MASK
7463. BB_MAX_CONTEXT_SIZE
7464. BB_MAX_LEN
7465. BB_MODE
7466. BB_MULT_MASK
7467. BB_MULT_VALID_MASK
7468. BB_OFFSET
7469. BB_OFFSET_MASK
7470. BB_PATH_A
7471. BB_PATH_AB
7472. BB_PATH_ABC
7473. BB_PATH_ABCD
7474. BB_PATH_ABD
7475. BB_PATH_AC
7476. BB_PATH_ACD
7477. BB_PATH_AD
7478. BB_PATH_B
7479. BB_PATH_BC
7480. BB_PATH_BCD
7481. BB_PATH_BD
7482. BB_PATH_C
7483. BB_PATH_CD
7484. BB_PATH_D
7485. BB_PLL_CONFIG_FRAC_LSB
7486. BB_PLL_CONFIG_FRAC_MASK
7487. BB_PLL_CONFIG_OFFSET
7488. BB_PLL_CONFIG_OUTDIV_LSB
7489. BB_PLL_CONFIG_OUTDIV_MASK
7490. BB_PROG_VALUES_REQUEST
7491. BB_PUT_BIT
7492. BB_READ_EN
7493. BB_REGISTER_DEFINITION_T
7494. BB_REG_BASE_ADDR
7495. BB_RESET
7496. BB_STAT1
7497. BB_STAT2
7498. BB_STAT2_AC_INTR
7499. BB_STAT2_FAN_INTR
7500. BB_STAT2_MASK
7501. BB_STAT2_PWR_INTR
7502. BB_STAT2_TMP_INTR
7503. BB_STAT3
7504. BB_TYPE_11A
7505. BB_TYPE_11B
7506. BB_TYPE_11G
7507. BB_VGA_CHANGE_THRESHOLD
7508. BB_VGA_LEVEL
7509. BB_WRITE_EN
7510. BB_WRITE_READ_MASK
7511. BBbReadEmbedded
7512. BBbVT3253Init
7513. BBbWriteEmbedded
7514. BBuGetFrameTime
7515. BBvExitDeepSleep
7516. BBvPowerSaveModeOFF
7517. BBvPowerSaveModeON
7518. BBvSetDeepSleep
7519. BBvSetRxAntennaMode
7520. BBvSetShortSlotTime
7521. BBvSetTxAntennaMode
7522. BBvSetVGAGainOffset
7523. BBvSoftwareReset
7524. BCACHE
7525. BCACHEDEVNAME_SIZE
7526. BCACHE_BSET_CSUM
7527. BCACHE_BSET_VERSION
7528. BCACHE_DEVICE_IDX_MAX
7529. BCACHE_DEV_CLOSING
7530. BCACHE_DEV_DETACHING
7531. BCACHE_DEV_RATE_DW_RUNNING
7532. BCACHE_DEV_UNLINK_DONE
7533. BCACHE_DEV_WB_RUNNING
7534. BCACHE_JSET_VERSION
7535. BCACHE_JSET_VERSION_UUID
7536. BCACHE_JSET_VERSION_UUIDv1
7537. BCACHE_MINORS
7538. BCACHE_SB_MAX_VERSION
7539. BCACHE_SB_VERSION_BDEV
7540. BCACHE_SB_VERSION_BDEV_WITH_OFFSET
7541. BCACHE_SB_VERSION_CDEV
7542. BCACHE_SB_VERSION_CDEV_WITH_UUID
7543. BCAPS
7544. BCAST
7545. BCAST1_4
7546. BCAST2_0
7547. BCAST_ACCEPT
7548. BCAST_DATA_MATCHED
7549. BCAST_FILTER_CMD
7550. BCAST_FILTER_FRAME_TYPE_ALL
7551. BCAST_FILTER_FRAME_TYPE_IPV4
7552. BCAST_FILTER_OFFSET_IP_END
7553. BCAST_FILTER_OFFSET_PAYLOAD_START
7554. BCAST_FLTR
7555. BCAST_HIDDEN
7556. BCAST_NORMAL
7557. BCAST_PROTOCOL
7558. BCAST_TYPE_MAX
7559. BCAST_UNKNOWN
7560. BCBCR
7561. BCC
7562. BCCAMASK
7563. BCCA_DROPOPTION
7564. BCCA_DROPTHRES
7565. BCCKEN
7566. BCCKLENGTHEXT
7567. BCCKRXPHASE
7568. BCCKRXRFSETTLE
7569. BCCKRX_AGC_FORMAT
7570. BCCKR_CP_MODE
7571. BCCKSAMPLERATE
7572. BCCKSIDEBAND
7573. BCCKTXCRC16
7574. BCCKTXLENGHT
7575. BCCKTXPREAMBLE
7576. BCCKTXSC
7577. BCCKTXSERVICE
7578. BCCKTXSFD
7579. BCCKTXSIG
7580. BCCKTXSTART
7581. BCCKTXSTATUS
7582. BCCK_ANTDIVERSITY
7583. BCCK_ANTENNA_POLARITY
7584. BCCK_BBMODE
7585. BCCK_BIST_MODE
7586. BCCK_CARRIER_RECOVERY
7587. BCCK_CCAMASK
7588. BCCK_CCA_COUNT
7589. BCCK_CCA_MODE
7590. BCCK_CH_ESTSTART
7591. BCCK_CORGBIT_SEL
7592. BCCK_CS_LIM
7593. BCCK_CS_RATIO
7594. BCCK_DAC_DEBUG
7595. BCCK_DCCANCEL
7596. BCCK_DEBUGPORT
7597. BCCK_DEFAULT_RXPATH
7598. BCCK_EQUALIZER
7599. BCCK_FACOUNTER_FREEZE
7600. BCCK_FALSEALARM_ENABLE
7601. BCCK_FALSEALARM_READ
7602. BCCK_FALSECS_LIM
7603. BCCK_FAST_FALSECCA
7604. BCCK_FIXED_RXAGC
7605. BCCK_ISICANCEL
7606. BCCK_LNA_POLARITY
7607. BCCK_MATCH_FILTER
7608. BCCK_NEWCCA
7609. BCCK_OPTION_RXPATH
7610. BCCK_PD_LIM
7611. BCCK_PREAMBLE_DETECT
7612. BCCK_RF_EXTEND
7613. BCCK_RX
7614. BCCK_RX1ST_BAIN
7615. BCCK_RXAGC_REPORT
7616. BCCK_RXAGC_REPORTTYPE
7617. BCCK_RXAGC_SATCOUNT
7618. BCCK_RXAGC_SATLEVEL
7619. BCCK_RXDAGC_EN
7620. BCCK_RXDAGC_PERIOD
7621. BCCK_RXDAGC_SATLEVEL
7622. BCCK_RXDC_OFFSET
7623. BCCK_RXFALSEALARM_ENABLE
7624. BCCK_RXFA_COUNTER_LOWER
7625. BCCK_RXFA_COUNTER_UPPER
7626. BCCK_RXHPAGC_FINAL
7627. BCCK_RXHPAGC_START
7628. BCCK_RXHP_OF_IG
7629. BCCK_RXIG
7630. BCCK_RXPOWERSAVING
7631. BCCK_RXREPORT_ANTSEL
7632. BCCK_RXREPORT_LOCKEDBIT
7633. BCCK_RXREPORT_MFOFF
7634. BCCK_RXREPORT_PKTLOSS
7635. BCCK_RXREPORT_RATEERROR
7636. BCCK_RXREPORT_RXRATE
7637. BCCK_RXREPORT_SQLOSS
7638. BCCK_RX_ADC_PHASE
7639. BCCK_SCRAMBLE
7640. BCCK_SIDEBAND
7641. BCCK_SYSTEM
7642. BCCK_TIMING_RECOVERY
7643. BCCK_TRSSI
7644. BCCK_TXC0
7645. BCCK_TXC1
7646. BCCK_TXC2
7647. BCCK_TXC3
7648. BCCK_TXC4
7649. BCCK_TXC5
7650. BCCK_TXC6
7651. BCCK_TXC7
7652. BCCK_TXDC_OFFSET
7653. BCCK_TXFILTER_TYPE
7654. BCCK_TXON
7655. BCCK_TXPATH_SEL
7656. BCCK_TXPOWERSAVING
7657. BCCK_TXRATE
7658. BCCK_TX_DAC_PHASE
7659. BCCR_BCBLACK
7660. BCCR_BCBLUE
7661. BCCR_BCGREEN
7662. BCCR_BCRED
7663. BCCR_BCWHITE
7664. BCCTR_FLUSH
7665. BCC_POWER_DB
7666. BCDC_DCMD_ERROR
7667. BCDC_DCMD_ID
7668. BCDC_DCMD_ID_MASK
7669. BCDC_DCMD_ID_SHIFT
7670. BCDC_DCMD_IF_MASK
7671. BCDC_DCMD_IF_SHIFT
7672. BCDC_DCMD_SET
7673. BCDC_FLAG2_IF_MASK
7674. BCDC_FLAG2_IF_SHIFT
7675. BCDC_FLAG_SUM_GOOD
7676. BCDC_FLAG_SUM_NEEDED
7677. BCDC_FLAG_VER_MASK
7678. BCDC_FLAG_VER_SHIFT
7679. BCDC_GET_IF_IDX
7680. BCDC_HEADER_LEN
7681. BCDC_PRIORITY_MASK
7682. BCDC_PROTO_VER
7683. BCDC_SET_IF_IDX
7684. BCD_EN_MASK
7685. BCD_EN_SHIFT
7686. BCD_REV
7687. BCE
7688. BCEN
7689. BCFG0_LATMEN
7690. BCFG0_MRDLDIS
7691. BCFG0_MRDMDIS
7692. BCFG0_MWMEN
7693. BCFG0_PERROFF
7694. BCFG0_VSERREN
7695. BCFG1_ARBITOPT
7696. BCFG1_CFUNOPT
7697. BCFG1_CISDLYEN
7698. BCFG1_CREQOPT
7699. BCFG1_DMA8
7700. BCFG1_MIOEN
7701. BCFG1_PCIMEN
7702. BCFOACC
7703. BCFOANTSUM
7704. BCFOEN
7705. BCFOLOOPBACK
7706. BCFOSTARTOFFSET
7707. BCFOSUMWEIGHT
7708. BCFOVALUE
7709. BCFO_ANTSUM_ID
7710. BCFO_REPORT_GET
7711. BCFR
7712. BCFRR
7713. BCFR_BIT
7714. BCFR_RPAUSE
7715. BCFR_UNLIMITED
7716. BCH16_ECC
7717. BCH4R_ECC_SIZE0
7718. BCH4R_ECC_SIZE1
7719. BCH4_BIT_PAD
7720. BCH4_ECC
7721. BCH8R_ECC_SIZE0
7722. BCH8R_ECC_SIZE1
7723. BCH8_ECC
7724. BCHG
7725. BCHGE
7726. BCHSMOOTH
7727. BCHSMOOTH_CFG1
7728. BCHSMOOTH_CFG2
7729. BCHSMOOTH_CFG3
7730. BCHSMOOTH_CFG4
7731. BCH_AUTO_GC_DIRTY_THRESHOLD
7732. BCH_BHCCR
7733. BCH_BHCNT
7734. BCH_BHCNT_BLOCKSIZE_MASK
7735. BCH_BHCNT_BLOCKSIZE_SHIFT
7736. BCH_BHCNT_DEC_COUNT_MASK
7737. BCH_BHCNT_DEC_COUNT_SHIFT
7738. BCH_BHCNT_ENC_COUNT_MASK
7739. BCH_BHCNT_ENC_COUNT_SHIFT
7740. BCH_BHCNT_PARITYSIZE_MASK
7741. BCH_BHCNT_PARITYSIZE_SHIFT
7742. BCH_BHCR
7743. BCH_BHCR_BCHE
7744. BCH_BHCR_BSEL
7745. BCH_BHCR_BSEL_MASK
7746. BCH_BHCR_BSEL_SHIFT
7747. BCH_BHCR_ENCE
7748. BCH_BHCR_INIT
7749. BCH_BHCSR
7750. BCH_BHDR
7751. BCH_BHERR0
7752. BCH_BHERR_INDEX0_MASK
7753. BCH_BHERR_INDEX0_SHIFT
7754. BCH_BHERR_INDEX1_MASK
7755. BCH_BHERR_INDEX1_SHIFT
7756. BCH_BHERR_INDEX_MASK
7757. BCH_BHERR_INDEX_SHIFT
7758. BCH_BHERR_MASK_MASK
7759. BCH_BHERR_MASK_SHIFT
7760. BCH_BHINT
7761. BCH_BHINTE
7762. BCH_BHINTEC
7763. BCH_BHINTES
7764. BCH_BHINT_ALL_0
7765. BCH_BHINT_ALL_F
7766. BCH_BHINT_DECF
7767. BCH_BHINT_ENCF
7768. BCH_BHINT_ERR
7769. BCH_BHINT_ERRC_MASK
7770. BCH_BHINT_ERRC_SHIFT
7771. BCH_BHINT_TERRC_MASK
7772. BCH_BHINT_TERRC_SHIFT
7773. BCH_BHINT_UNCOR
7774. BCH_BHPAR0
7775. BCH_CACHED_DEV_STOP_ALWAYS
7776. BCH_CACHED_DEV_STOP_AUTO
7777. BCH_CACHED_DEV_STOP_MODE_MAX
7778. BCH_CACHE_READA_ALL
7779. BCH_CACHE_READA_META_ONLY
7780. BCH_CLK_RATE
7781. BCH_CONFIG
7782. BCH_DO_AUTO_GC
7783. BCH_ECC_BYTES
7784. BCH_ECC_MAX_WORDS
7785. BCH_ECC_SIZE0
7786. BCH_ECC_SIZE1
7787. BCH_ECC_WORDS
7788. BCH_ENABLE
7789. BCH_ENABLE_AUTO_GC
7790. BCH_MAX_M
7791. BCH_MAX_T
7792. BCH_SEQ_READS
7793. BCH_TIMEOUT_US
7794. BCH_TVAL_14
7795. BCH_TVAL_16
7796. BCH_TVAL_4
7797. BCH_TVAL_8
7798. BCH_WRAPMODE_1
7799. BCH_WRAPMODE_6
7800. BCI_BD_BW_DISABLE
7801. BCI_BD_GET_BPP
7802. BCI_BD_GET_STRIDE
7803. BCI_BD_SET_BPP
7804. BCI_BD_SET_STRIDE
7805. BCI_BD_TILE_16
7806. BCI_BD_TILE_32
7807. BCI_BD_TILE_MASK
7808. BCI_BD_TILE_NONE
7809. BCI_BUFFER_OFFSET
7810. BCI_BUSY
7811. BCI_CLIP_BR
7812. BCI_CLIP_LR
7813. BCI_CLIP_TL
7814. BCI_CMD_BIT_TEXT
7815. BCI_CMD_BYTE_TEXT
7816. BCI_CMD_CLIP_CURRENT
7817. BCI_CMD_CLIP_LR
7818. BCI_CMD_CLIP_NEW
7819. BCI_CMD_CLIP_NONE
7820. BCI_CMD_DEST_GBD
7821. BCI_CMD_DEST_PBD
7822. BCI_CMD_DEST_PBD_NEW
7823. BCI_CMD_DEST_SBD
7824. BCI_CMD_DEST_SBD_NEW
7825. BCI_CMD_DMA
7826. BCI_CMD_DRAW_CONT
7827. BCI_CMD_DRAW_INDEXED_PRIM
7828. BCI_CMD_DRAW_NO_CD
7829. BCI_CMD_DRAW_NO_CS
7830. BCI_CMD_DRAW_NO_U0
7831. BCI_CMD_DRAW_NO_U1
7832. BCI_CMD_DRAW_NO_UV0
7833. BCI_CMD_DRAW_NO_UV1
7834. BCI_CMD_DRAW_NO_V0
7835. BCI_CMD_DRAW_NO_V1
7836. BCI_CMD_DRAW_NO_W
7837. BCI_CMD_DRAW_NO_Z
7838. BCI_CMD_DRAW_PRIM
7839. BCI_CMD_DRAW_SKIPFLAGS
7840. BCI_CMD_DRAW_TRIFAN
7841. BCI_CMD_DRAW_TRILIST
7842. BCI_CMD_DRAW_TRISTRIP
7843. BCI_CMD_GET_ROP
7844. BCI_CMD_LINE
7845. BCI_CMD_LINE_LAST_PIXEL
7846. BCI_CMD_NOP
7847. BCI_CMD_NT_BYTE_TEXT
7848. BCI_CMD_PAT_COLOR
7849. BCI_CMD_PAT_MONO
7850. BCI_CMD_PAT_NONE
7851. BCI_CMD_PAT_PBD_COLOR
7852. BCI_CMD_PAT_PBD_COLOR_NEW
7853. BCI_CMD_PAT_PBD_MONO
7854. BCI_CMD_PAT_PBD_MONO_NEW
7855. BCI_CMD_PAT_SBD_COLOR
7856. BCI_CMD_PAT_SBD_COLOR_NEW
7857. BCI_CMD_PAT_SBD_MONO
7858. BCI_CMD_PAT_SBD_MONO_NEW
7859. BCI_CMD_PAT_TRANSPARENT
7860. BCI_CMD_RECT
7861. BCI_CMD_RECT_XP
7862. BCI_CMD_RECT_YP
7863. BCI_CMD_SCANLINE
7864. BCI_CMD_SEND_COLOR
7865. BCI_CMD_SETREG
7866. BCI_CMD_SET_REGISTER
7867. BCI_CMD_SET_ROP
7868. BCI_CMD_SRC_COLOR
7869. BCI_CMD_SRC_GBD
7870. BCI_CMD_SRC_MONO
7871. BCI_CMD_SRC_PBD_COLOR
7872. BCI_CMD_SRC_PBD_COLOR_NEW
7873. BCI_CMD_SRC_PBD_MONO
7874. BCI_CMD_SRC_PBD_MONO_NEW
7875. BCI_CMD_SRC_SBD_COLOR
7876. BCI_CMD_SRC_SBD_COLOR_NEW
7877. BCI_CMD_SRC_SBD_MONO
7878. BCI_CMD_SRC_SBD_MONO_NEW
7879. BCI_CMD_SRC_SOLID
7880. BCI_CMD_SRC_TRANSPARENT
7881. BCI_CMD_UPDATE_EVENT_TAG
7882. BCI_CMD_WAIT
7883. BCI_CMD_WAIT_2D
7884. BCI_CMD_WAIT_3D
7885. BCI_DEBUG_READ__DATA_MASK
7886. BCI_DEBUG_READ__DATA__SHIFT
7887. BCI_DMA
7888. BCI_DRAW_INDICES_S3D
7889. BCI_DRAW_INDICES_S4
7890. BCI_DRAW_PRIMITIVE
7891. BCI_GBD1
7892. BCI_GBD2
7893. BCI_INTR_OFFSET
7894. BCI_LINE_MISC
7895. BCI_LINE_STEPS
7896. BCI_LINE_X_Y
7897. BCI_LOCALS
7898. BCI_PRES_INTR_OFFSET
7899. BCI_SEND
7900. BCI_SET_REGISTERS
7901. BCI_SIZE
7902. BCI_WRITE
7903. BCI_W_H
7904. BCI_X_W
7905. BCI_X_Y
7906. BCJ_ARM
7907. BCJ_ARMTHUMB
7908. BCJ_IA64
7909. BCJ_POWERPC
7910. BCJ_SPARC
7911. BCJ_X86
7912. BCK1_BCKUP_MASK
7913. BCK1_BCKUP_SHIFT
7914. BCK2_BCKUP_MASK
7915. BCK2_BCKUP_SHIFT
7916. BCK3_BCKUP_MASK
7917. BCK3_BCKUP_SHIFT
7918. BCK4_BCKUP_MASK
7919. BCK4_BCKUP_SHIFT
7920. BCK5_BCKUP_MASK
7921. BCK5_BCKUP_SHIFT
7922. BCKO_64
7923. BCKO_MASK
7924. BCK_EN
7925. BCK_INVERSE_MASK
7926. BCK_INVERSE_MASK_SFT
7927. BCK_INVERSE_SFT
7928. BCK_INV_MASK
7929. BCK_INV_MASK_SFT
7930. BCK_INV_SFT
7931. BCK_NEG_EG_LATCH_MASK
7932. BCK_NEG_EG_LATCH_MASK_SFT
7933. BCK_NEG_EG_LATCH_SFT
7934. BCLC
7935. BCLC2S216A
7936. BCLC2S232A
7937. BCLC2S28
7938. BCLC2S2Q
7939. BCLINK_MODE_BCAST
7940. BCLINK_MODE_RCAST
7941. BCLINK_MODE_SEL
7942. BCLINK_WIN_DEFAULT
7943. BCLINK_WIN_MIN
7944. BCLK1_OEN
7945. BCLK2_OEN
7946. BCLK2_RATE
7947. BCLK_AS_XCLK
7948. BCLK_TO_FS_MSK
7949. BCLR
7950. BCLRPAT
7951. BCLRPAT_A
7952. BCLRPAT_B
7953. BCLRPAT_C
7954. BCLSB
7955. BCM1250_M3_WAR
7956. BCM1480_DUART_CHANREG_SPACING
7957. BCM1480_DUART_NUM_PORTS
7958. BCM1480_HR_LEAF_OFFSET
7959. BCM1480_HR_LEAF_SPACING
7960. BCM1480_HR_NUM_LEAVES
7961. BCM1480_HR_NUM_PATHS
7962. BCM1480_HR_NUM_ROUTES
7963. BCM1480_HR_NUM_RULES
7964. BCM1480_HR_OP_OFFSET
7965. BCM1480_HR_PATH_OFFSET
7966. BCM1480_HR_PATH_SPACING
7967. BCM1480_HR_REGISTER_SPACING
7968. BCM1480_HR_ROUTE_OFFSET
7969. BCM1480_HR_ROUTE_SPACING
7970. BCM1480_HR_RULE_SPACING
7971. BCM1480_HR_TYPE_OFFSET
7972. BCM1480_HSP_REGISTER_SPACING
7973. BCM1480_HT_NUM_PORTS
7974. BCM1480_HT_PORT_SPACING
7975. BCM1480_IMR_ALIAS_MAILBOX_SPACING
7976. BCM1480_IMR_HL_SPACING
7977. BCM1480_IMR_INTERRUPT_MAP_COUNT
7978. BCM1480_IMR_INTERRUPT_STATUS_COUNT
7979. BCM1480_IMR_REGISTER_SPACING
7980. BCM1480_IMR_REGISTER_SPACING_SHIFT
7981. BCM1480_L2C_ENTRIES_PER_WAY
7982. BCM1480_L2C_NUM_WAYS
7983. BCM1480_MC_CSX_SPACING
7984. BCM1480_MC_REGISTER_SPACING
7985. BCM1480_NR_IRQS
7986. BCM1480_NR_IRQS_HALF
7987. BCM1480_PHYS_L2CACHE_NUM_WAYS
7988. BCM1480_PM_INT_FUNCTION_SPACING
7989. BCM1480_PM_INT_NUM_FUNCTIONS
7990. BCM1480_PM_INT_PACKING
7991. BCM1480_PM_LCL_REGISTER_SPACING
7992. BCM1480_PM_NUM_CHANNELS
7993. BCM1480_SCD_NUM_PERF_CNT
7994. BCM1480_SCD_NUM_WDOGS
7995. BCM1480_SCD_PERF_CNT_SPACING
7996. BCM203X_CHECK_FIRMWARE
7997. BCM203X_CHECK_MEMORY
7998. BCM203X_ERROR
7999. BCM203X_IN_EP
8000. BCM203X_LOAD_FIRMWARE
8001. BCM203X_LOAD_MINIDRV
8002. BCM203X_OUT_EP
8003. BCM203X_RESET
8004. BCM203X_SELECT_MEMORY
8005. BCM2055A0_IDCODE
8006. BCM2055_ID
8007. BCM2055_IDCODE
8008. BCM2056A0_IDCODE
8009. BCM2056_ID
8010. BCM2056_IDCODE
8011. BCM2057A0_IDCODE
8012. BCM2057_ID
8013. BCM2057_IDCODE
8014. BCM2064A0_IDCODE
8015. BCM2064_ID
8016. BCM2064_IDCODE
8017. BCM21664_AON_CCU_CLOCK_COUNT
8018. BCM21664_AON_CCU_HUB_TIMER
8019. BCM21664_CCU_COMMON
8020. BCM21664_DT_AON_CCU_COMPAT
8021. BCM21664_DT_MASTER_CCU_COMPAT
8022. BCM21664_DT_ROOT_CCU_COMPAT
8023. BCM21664_DT_SLAVE_CCU_COMPAT
8024. BCM21664_MASTER_CCU_CLOCK_COUNT
8025. BCM21664_MASTER_CCU_SDIO1
8026. BCM21664_MASTER_CCU_SDIO1_SLEEP
8027. BCM21664_MASTER_CCU_SDIO2
8028. BCM21664_MASTER_CCU_SDIO2_SLEEP
8029. BCM21664_MASTER_CCU_SDIO3
8030. BCM21664_MASTER_CCU_SDIO3_SLEEP
8031. BCM21664_MASTER_CCU_SDIO4
8032. BCM21664_MASTER_CCU_SDIO4_SLEEP
8033. BCM21664_ROOT_CCU_CLOCK_COUNT
8034. BCM21664_ROOT_CCU_FRAC_1M
8035. BCM21664_SLAVE_CCU_BSC1
8036. BCM21664_SLAVE_CCU_BSC2
8037. BCM21664_SLAVE_CCU_BSC3
8038. BCM21664_SLAVE_CCU_BSC4
8039. BCM21664_SLAVE_CCU_CLOCK_COUNT
8040. BCM21664_SLAVE_CCU_UARTB
8041. BCM21664_SLAVE_CCU_UARTB2
8042. BCM21664_SLAVE_CCU_UARTB3
8043. BCM2711_CLOCK_EMMC2
8044. BCM2711_PULL_DOWN
8045. BCM2711_PULL_NONE
8046. BCM2711_PULL_UP
8047. BCM281XX_AON_CCU_CLOCK_COUNT
8048. BCM281XX_AON_CCU_HUB_TIMER
8049. BCM281XX_AON_CCU_PMU_BSC
8050. BCM281XX_AON_CCU_PMU_BSC_VAR
8051. BCM281XX_CCU_COMMON
8052. BCM281XX_DT_AON_CCU_COMPAT
8053. BCM281XX_DT_HUB_CCU_COMPAT
8054. BCM281XX_DT_MASTER_CCU_COMPAT
8055. BCM281XX_DT_ROOT_CCU_COMPAT
8056. BCM281XX_DT_SLAVE_CCU_COMPAT
8057. BCM281XX_HDMI_PIN_REG_INPUT_DIS_MASK
8058. BCM281XX_HDMI_PIN_REG_INPUT_DIS_SHIFT
8059. BCM281XX_HDMI_PIN_REG_MODE_MASK
8060. BCM281XX_HDMI_PIN_REG_MODE_SHIFT
8061. BCM281XX_HUB_CCU_CLOCK_COUNT
8062. BCM281XX_HUB_CCU_TMON_1M
8063. BCM281XX_I2C_PIN_REG_INPUT_DIS_MASK
8064. BCM281XX_I2C_PIN_REG_INPUT_DIS_SHIFT
8065. BCM281XX_I2C_PIN_REG_PULL_UP_STR_MASK
8066. BCM281XX_I2C_PIN_REG_PULL_UP_STR_SHIFT
8067. BCM281XX_I2C_PIN_REG_SLEW_MASK
8068. BCM281XX_I2C_PIN_REG_SLEW_SHIFT
8069. BCM281XX_MASTER_CCU_CLOCK_COUNT
8070. BCM281XX_MASTER_CCU_HSIC2_12M
8071. BCM281XX_MASTER_CCU_HSIC2_48M
8072. BCM281XX_MASTER_CCU_SDIO1
8073. BCM281XX_MASTER_CCU_SDIO2
8074. BCM281XX_MASTER_CCU_SDIO3
8075. BCM281XX_MASTER_CCU_SDIO4
8076. BCM281XX_MASTER_CCU_USB_IC
8077. BCM281XX_PIN_ADCSYNC
8078. BCM281XX_PIN_BAT_RM
8079. BCM281XX_PIN_BSC1_SCL
8080. BCM281XX_PIN_BSC1_SDA
8081. BCM281XX_PIN_BSC2_SCL
8082. BCM281XX_PIN_BSC2_SDA
8083. BCM281XX_PIN_CLASSGPWR
8084. BCM281XX_PIN_CLKOUT_0
8085. BCM281XX_PIN_CLKOUT_1
8086. BCM281XX_PIN_CLKOUT_2
8087. BCM281XX_PIN_CLKOUT_3
8088. BCM281XX_PIN_CLKREQ_IN_0
8089. BCM281XX_PIN_CLKREQ_IN_1
8090. BCM281XX_PIN_CLK_CX8
8091. BCM281XX_PIN_CWS_SYS_REQ1
8092. BCM281XX_PIN_CWS_SYS_REQ2
8093. BCM281XX_PIN_CWS_SYS_REQ3
8094. BCM281XX_PIN_DESC
8095. BCM281XX_PIN_DIGMIC1_CLK
8096. BCM281XX_PIN_DIGMIC1_DQ
8097. BCM281XX_PIN_DIGMIC2_CLK
8098. BCM281XX_PIN_DIGMIC2_DQ
8099. BCM281XX_PIN_FUNCTION
8100. BCM281XX_PIN_GPEN13
8101. BCM281XX_PIN_GPEN14
8102. BCM281XX_PIN_GPEN15
8103. BCM281XX_PIN_GPIO00
8104. BCM281XX_PIN_GPIO01
8105. BCM281XX_PIN_GPIO02
8106. BCM281XX_PIN_GPIO03
8107. BCM281XX_PIN_GPIO04
8108. BCM281XX_PIN_GPIO05
8109. BCM281XX_PIN_GPIO06
8110. BCM281XX_PIN_GPIO07
8111. BCM281XX_PIN_GPIO08
8112. BCM281XX_PIN_GPIO09
8113. BCM281XX_PIN_GPIO10
8114. BCM281XX_PIN_GPIO11
8115. BCM281XX_PIN_GPIO12
8116. BCM281XX_PIN_GPIO13
8117. BCM281XX_PIN_GPIO14
8118. BCM281XX_PIN_GPS_PABLANK
8119. BCM281XX_PIN_GPS_TMARK
8120. BCM281XX_PIN_HDMI_SCL
8121. BCM281XX_PIN_HDMI_SDA
8122. BCM281XX_PIN_IC_DM
8123. BCM281XX_PIN_IC_DP
8124. BCM281XX_PIN_KP_COL_IP_0
8125. BCM281XX_PIN_KP_COL_IP_1
8126. BCM281XX_PIN_KP_COL_IP_2
8127. BCM281XX_PIN_KP_COL_IP_3
8128. BCM281XX_PIN_KP_ROW_OP_0
8129. BCM281XX_PIN_KP_ROW_OP_1
8130. BCM281XX_PIN_KP_ROW_OP_2
8131. BCM281XX_PIN_KP_ROW_OP_3
8132. BCM281XX_PIN_LCD_B_0
8133. BCM281XX_PIN_LCD_B_1
8134. BCM281XX_PIN_LCD_B_2
8135. BCM281XX_PIN_LCD_B_3
8136. BCM281XX_PIN_LCD_B_4
8137. BCM281XX_PIN_LCD_B_5
8138. BCM281XX_PIN_LCD_B_6
8139. BCM281XX_PIN_LCD_B_7
8140. BCM281XX_PIN_LCD_G_0
8141. BCM281XX_PIN_LCD_G_1
8142. BCM281XX_PIN_LCD_G_2
8143. BCM281XX_PIN_LCD_G_3
8144. BCM281XX_PIN_LCD_G_4
8145. BCM281XX_PIN_LCD_G_5
8146. BCM281XX_PIN_LCD_G_6
8147. BCM281XX_PIN_LCD_G_7
8148. BCM281XX_PIN_LCD_HSYNC
8149. BCM281XX_PIN_LCD_OE
8150. BCM281XX_PIN_LCD_PCLK
8151. BCM281XX_PIN_LCD_R_0
8152. BCM281XX_PIN_LCD_R_1
8153. BCM281XX_PIN_LCD_R_2
8154. BCM281XX_PIN_LCD_R_3
8155. BCM281XX_PIN_LCD_R_4
8156. BCM281XX_PIN_LCD_R_5
8157. BCM281XX_PIN_LCD_R_6
8158. BCM281XX_PIN_LCD_R_7
8159. BCM281XX_PIN_LCD_VSYNC
8160. BCM281XX_PIN_MASK
8161. BCM281XX_PIN_MDMGPIO0
8162. BCM281XX_PIN_MDMGPIO1
8163. BCM281XX_PIN_MDMGPIO2
8164. BCM281XX_PIN_MDMGPIO3
8165. BCM281XX_PIN_MDMGPIO4
8166. BCM281XX_PIN_MDMGPIO5
8167. BCM281XX_PIN_MDMGPIO6
8168. BCM281XX_PIN_MDMGPIO7
8169. BCM281XX_PIN_MDMGPIO8
8170. BCM281XX_PIN_MPHI_DATA_0
8171. BCM281XX_PIN_MPHI_DATA_1
8172. BCM281XX_PIN_MPHI_DATA_10
8173. BCM281XX_PIN_MPHI_DATA_11
8174. BCM281XX_PIN_MPHI_DATA_12
8175. BCM281XX_PIN_MPHI_DATA_13
8176. BCM281XX_PIN_MPHI_DATA_14
8177. BCM281XX_PIN_MPHI_DATA_15
8178. BCM281XX_PIN_MPHI_DATA_2
8179. BCM281XX_PIN_MPHI_DATA_3
8180. BCM281XX_PIN_MPHI_DATA_4
8181. BCM281XX_PIN_MPHI_DATA_5
8182. BCM281XX_PIN_MPHI_DATA_6
8183. BCM281XX_PIN_MPHI_DATA_7
8184. BCM281XX_PIN_MPHI_DATA_8
8185. BCM281XX_PIN_MPHI_DATA_9
8186. BCM281XX_PIN_MPHI_HA0
8187. BCM281XX_PIN_MPHI_HAT0
8188. BCM281XX_PIN_MPHI_HAT1
8189. BCM281XX_PIN_MPHI_HCE0_N
8190. BCM281XX_PIN_MPHI_HCE1_N
8191. BCM281XX_PIN_MPHI_HRD_N
8192. BCM281XX_PIN_MPHI_HWR_N
8193. BCM281XX_PIN_MPHI_RUN0
8194. BCM281XX_PIN_MPHI_RUN1
8195. BCM281XX_PIN_MTX_SCAN_CLK
8196. BCM281XX_PIN_MTX_SCAN_DATA
8197. BCM281XX_PIN_NAND_AD_0
8198. BCM281XX_PIN_NAND_AD_1
8199. BCM281XX_PIN_NAND_AD_2
8200. BCM281XX_PIN_NAND_AD_3
8201. BCM281XX_PIN_NAND_AD_4
8202. BCM281XX_PIN_NAND_AD_5
8203. BCM281XX_PIN_NAND_AD_6
8204. BCM281XX_PIN_NAND_AD_7
8205. BCM281XX_PIN_NAND_ALE
8206. BCM281XX_PIN_NAND_CEN_0
8207. BCM281XX_PIN_NAND_CEN_1
8208. BCM281XX_PIN_NAND_CLE
8209. BCM281XX_PIN_NAND_OEN
8210. BCM281XX_PIN_NAND_RDY_0
8211. BCM281XX_PIN_NAND_RDY_1
8212. BCM281XX_PIN_NAND_WEN
8213. BCM281XX_PIN_NAND_WP
8214. BCM281XX_PIN_PC1
8215. BCM281XX_PIN_PC2
8216. BCM281XX_PIN_PMU_INT
8217. BCM281XX_PIN_PMU_SCL
8218. BCM281XX_PIN_PMU_SDA
8219. BCM281XX_PIN_REG_F_SEL_MASK
8220. BCM281XX_PIN_REG_F_SEL_SHIFT
8221. BCM281XX_PIN_RFST2G_MTSLOTEN3G
8222. BCM281XX_PIN_RGMII_0_RXC
8223. BCM281XX_PIN_RGMII_0_RXD_0
8224. BCM281XX_PIN_RGMII_0_RXD_1
8225. BCM281XX_PIN_RGMII_0_RXD_2
8226. BCM281XX_PIN_RGMII_0_RXD_3
8227. BCM281XX_PIN_RGMII_0_RX_CTL
8228. BCM281XX_PIN_RGMII_0_TXC
8229. BCM281XX_PIN_RGMII_0_TXD_0
8230. BCM281XX_PIN_RGMII_0_TXD_1
8231. BCM281XX_PIN_RGMII_0_TXD_2
8232. BCM281XX_PIN_RGMII_0_TXD_3
8233. BCM281XX_PIN_RGMII_0_TX_CTL
8234. BCM281XX_PIN_RGMII_1_RXC
8235. BCM281XX_PIN_RGMII_1_RXD_0
8236. BCM281XX_PIN_RGMII_1_RXD_1
8237. BCM281XX_PIN_RGMII_1_RXD_2
8238. BCM281XX_PIN_RGMII_1_RXD_3
8239. BCM281XX_PIN_RGMII_1_RX_CTL
8240. BCM281XX_PIN_RGMII_1_TXC
8241. BCM281XX_PIN_RGMII_1_TXD_0
8242. BCM281XX_PIN_RGMII_1_TXD_1
8243. BCM281XX_PIN_RGMII_1_TXD_2
8244. BCM281XX_PIN_RGMII_1_TXD_3
8245. BCM281XX_PIN_RGMII_1_TX_CTL
8246. BCM281XX_PIN_RGMII_GPIO_0
8247. BCM281XX_PIN_RGMII_GPIO_1
8248. BCM281XX_PIN_RGMII_GPIO_2
8249. BCM281XX_PIN_RGMII_GPIO_3
8250. BCM281XX_PIN_RTXDATA2G_TXDATA3G1
8251. BCM281XX_PIN_RTXEN2G_TXDATA3G2
8252. BCM281XX_PIN_RXDATA3G0
8253. BCM281XX_PIN_RXDATA3G1
8254. BCM281XX_PIN_RXDATA3G2
8255. BCM281XX_PIN_SDIO1_CLK
8256. BCM281XX_PIN_SDIO1_CMD
8257. BCM281XX_PIN_SDIO1_DATA_0
8258. BCM281XX_PIN_SDIO1_DATA_1
8259. BCM281XX_PIN_SDIO1_DATA_2
8260. BCM281XX_PIN_SDIO1_DATA_3
8261. BCM281XX_PIN_SDIO4_CLK
8262. BCM281XX_PIN_SDIO4_CMD
8263. BCM281XX_PIN_SDIO4_DATA_0
8264. BCM281XX_PIN_SDIO4_DATA_1
8265. BCM281XX_PIN_SDIO4_DATA_2
8266. BCM281XX_PIN_SDIO4_DATA_3
8267. BCM281XX_PIN_SHIFT
8268. BCM281XX_PIN_SIM2_CLK
8269. BCM281XX_PIN_SIM2_DATA
8270. BCM281XX_PIN_SIM2_DET
8271. BCM281XX_PIN_SIM2_RESETN
8272. BCM281XX_PIN_SIM_CLK
8273. BCM281XX_PIN_SIM_DATA
8274. BCM281XX_PIN_SIM_DET
8275. BCM281XX_PIN_SIM_RESETN
8276. BCM281XX_PIN_SRI_C
8277. BCM281XX_PIN_SRI_D
8278. BCM281XX_PIN_SRI_E
8279. BCM281XX_PIN_SSP0_CLK
8280. BCM281XX_PIN_SSP0_FS
8281. BCM281XX_PIN_SSP0_RXD
8282. BCM281XX_PIN_SSP0_TXD
8283. BCM281XX_PIN_SSP2_CLK
8284. BCM281XX_PIN_SSP2_FS_0
8285. BCM281XX_PIN_SSP2_FS_1
8286. BCM281XX_PIN_SSP2_FS_2
8287. BCM281XX_PIN_SSP2_FS_3
8288. BCM281XX_PIN_SSP2_RXD_0
8289. BCM281XX_PIN_SSP2_RXD_1
8290. BCM281XX_PIN_SSP2_TXD_0
8291. BCM281XX_PIN_SSP2_TXD_1
8292. BCM281XX_PIN_SSP3_CLK
8293. BCM281XX_PIN_SSP3_FS
8294. BCM281XX_PIN_SSP3_RXD
8295. BCM281XX_PIN_SSP3_TXD
8296. BCM281XX_PIN_SSP4_CLK
8297. BCM281XX_PIN_SSP4_FS
8298. BCM281XX_PIN_SSP4_RXD
8299. BCM281XX_PIN_SSP4_TXD
8300. BCM281XX_PIN_SSP5_CLK
8301. BCM281XX_PIN_SSP5_FS
8302. BCM281XX_PIN_SSP5_RXD
8303. BCM281XX_PIN_SSP5_TXD
8304. BCM281XX_PIN_SSP6_CLK
8305. BCM281XX_PIN_SSP6_FS
8306. BCM281XX_PIN_SSP6_RXD
8307. BCM281XX_PIN_SSP6_TXD
8308. BCM281XX_PIN_SSP_EXTCLK
8309. BCM281XX_PIN_STAT_1
8310. BCM281XX_PIN_STAT_2
8311. BCM281XX_PIN_SYSCLKEN
8312. BCM281XX_PIN_TRACECLK
8313. BCM281XX_PIN_TRACEDT00
8314. BCM281XX_PIN_TRACEDT01
8315. BCM281XX_PIN_TRACEDT02
8316. BCM281XX_PIN_TRACEDT03
8317. BCM281XX_PIN_TRACEDT04
8318. BCM281XX_PIN_TRACEDT05
8319. BCM281XX_PIN_TRACEDT06
8320. BCM281XX_PIN_TRACEDT07
8321. BCM281XX_PIN_TRACEDT08
8322. BCM281XX_PIN_TRACEDT09
8323. BCM281XX_PIN_TRACEDT10
8324. BCM281XX_PIN_TRACEDT11
8325. BCM281XX_PIN_TRACEDT12
8326. BCM281XX_PIN_TRACEDT13
8327. BCM281XX_PIN_TRACEDT14
8328. BCM281XX_PIN_TRACEDT15
8329. BCM281XX_PIN_TXDATA3G0
8330. BCM281XX_PIN_TXPWRIND
8331. BCM281XX_PIN_TYPE_HDMI
8332. BCM281XX_PIN_TYPE_I2C
8333. BCM281XX_PIN_TYPE_STD
8334. BCM281XX_PIN_TYPE_UNKNOWN
8335. BCM281XX_PIN_UARTB1_UCTS
8336. BCM281XX_PIN_UARTB1_URTS
8337. BCM281XX_PIN_UARTB1_URXD
8338. BCM281XX_PIN_UARTB1_UTXD
8339. BCM281XX_PIN_UARTB2_URXD
8340. BCM281XX_PIN_UARTB2_UTXD
8341. BCM281XX_PIN_UARTB3_UCTS
8342. BCM281XX_PIN_UARTB3_URTS
8343. BCM281XX_PIN_UARTB3_URXD
8344. BCM281XX_PIN_UARTB3_UTXD
8345. BCM281XX_PIN_UARTB4_UCTS
8346. BCM281XX_PIN_UARTB4_URTS
8347. BCM281XX_PIN_UARTB4_URXD
8348. BCM281XX_PIN_UARTB4_UTXD
8349. BCM281XX_PIN_VC_CAM1_SCL
8350. BCM281XX_PIN_VC_CAM1_SDA
8351. BCM281XX_PIN_VC_CAM2_SCL
8352. BCM281XX_PIN_VC_CAM2_SDA
8353. BCM281XX_PIN_VC_CAM3_SCL
8354. BCM281XX_PIN_VC_CAM3_SDA
8355. BCM281XX_ROOT_CCU_CLOCK_COUNT
8356. BCM281XX_ROOT_CCU_FRAC_1M
8357. BCM281XX_SLAVE_CCU_BSC1
8358. BCM281XX_SLAVE_CCU_BSC2
8359. BCM281XX_SLAVE_CCU_BSC3
8360. BCM281XX_SLAVE_CCU_CLOCK_COUNT
8361. BCM281XX_SLAVE_CCU_PWM
8362. BCM281XX_SLAVE_CCU_SSP0
8363. BCM281XX_SLAVE_CCU_SSP2
8364. BCM281XX_SLAVE_CCU_UARTB
8365. BCM281XX_SLAVE_CCU_UARTB2
8366. BCM281XX_SLAVE_CCU_UARTB3
8367. BCM281XX_SLAVE_CCU_UARTB4
8368. BCM281XX_STD_PIN_REG_DRV_STR_MASK
8369. BCM281XX_STD_PIN_REG_DRV_STR_SHIFT
8370. BCM281XX_STD_PIN_REG_HYST_MASK
8371. BCM281XX_STD_PIN_REG_HYST_SHIFT
8372. BCM281XX_STD_PIN_REG_INPUT_DIS_MASK
8373. BCM281XX_STD_PIN_REG_INPUT_DIS_SHIFT
8374. BCM281XX_STD_PIN_REG_PULL_DN_MASK
8375. BCM281XX_STD_PIN_REG_PULL_DN_SHIFT
8376. BCM281XX_STD_PIN_REG_PULL_UP_MASK
8377. BCM281XX_STD_PIN_REG_PULL_UP_SHIFT
8378. BCM281XX_STD_PIN_REG_SLEW_MASK
8379. BCM281XX_STD_PIN_REG_SLEW_SHIFT
8380. BCM2835_AUXENB
8381. BCM2835_AUXIRQ
8382. BCM2835_AUX_CLOCK_COUNT
8383. BCM2835_AUX_CLOCK_SPI1
8384. BCM2835_AUX_CLOCK_SPI2
8385. BCM2835_AUX_CLOCK_UART
8386. BCM2835_AUX_SPI_CNTL0
8387. BCM2835_AUX_SPI_CNTL0_CLEARFIFO
8388. BCM2835_AUX_SPI_CNTL0_CPOL
8389. BCM2835_AUX_SPI_CNTL0_CS
8390. BCM2835_AUX_SPI_CNTL0_DOUTHOLD
8391. BCM2835_AUX_SPI_CNTL0_ENABLE
8392. BCM2835_AUX_SPI_CNTL0_IN_RISING
8393. BCM2835_AUX_SPI_CNTL0_MSBF_OUT
8394. BCM2835_AUX_SPI_CNTL0_OUT_RISING
8395. BCM2835_AUX_SPI_CNTL0_POSTINPUT
8396. BCM2835_AUX_SPI_CNTL0_SHIFTLEN
8397. BCM2835_AUX_SPI_CNTL0_SPEED
8398. BCM2835_AUX_SPI_CNTL0_SPEED_MAX
8399. BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT
8400. BCM2835_AUX_SPI_CNTL0_VAR_CS
8401. BCM2835_AUX_SPI_CNTL0_VAR_WIDTH
8402. BCM2835_AUX_SPI_CNTL1
8403. BCM2835_AUX_SPI_CNTL1_CSHIGH
8404. BCM2835_AUX_SPI_CNTL1_IDLE
8405. BCM2835_AUX_SPI_CNTL1_KEEP_IN
8406. BCM2835_AUX_SPI_CNTL1_MSBF_IN
8407. BCM2835_AUX_SPI_CNTL1_TXEMPTY
8408. BCM2835_AUX_SPI_IO
8409. BCM2835_AUX_SPI_PEEK
8410. BCM2835_AUX_SPI_STAT
8411. BCM2835_AUX_SPI_STAT_BITCOUNT
8412. BCM2835_AUX_SPI_STAT_BUSY
8413. BCM2835_AUX_SPI_STAT_RX_EMPTY
8414. BCM2835_AUX_SPI_STAT_RX_FULL
8415. BCM2835_AUX_SPI_STAT_RX_LVL
8416. BCM2835_AUX_SPI_STAT_TX_EMPTY
8417. BCM2835_AUX_SPI_STAT_TX_FULL
8418. BCM2835_AUX_SPI_STAT_TX_LVL
8419. BCM2835_AUX_SPI_TXHOLD
8420. BCM2835_CLOCK_AVEO
8421. BCM2835_CLOCK_CAM0
8422. BCM2835_CLOCK_CAM1
8423. BCM2835_CLOCK_DFT
8424. BCM2835_CLOCK_DPI
8425. BCM2835_CLOCK_DSI0E
8426. BCM2835_CLOCK_DSI0P
8427. BCM2835_CLOCK_DSI1E
8428. BCM2835_CLOCK_DSI1P
8429. BCM2835_CLOCK_EMMC
8430. BCM2835_CLOCK_GP0
8431. BCM2835_CLOCK_GP1
8432. BCM2835_CLOCK_GP2
8433. BCM2835_CLOCK_H264
8434. BCM2835_CLOCK_HSM
8435. BCM2835_CLOCK_ISP
8436. BCM2835_CLOCK_OTP
8437. BCM2835_CLOCK_PCM
8438. BCM2835_CLOCK_PERI_IMAGE
8439. BCM2835_CLOCK_PWM
8440. BCM2835_CLOCK_SDRAM
8441. BCM2835_CLOCK_SLIM
8442. BCM2835_CLOCK_SMI
8443. BCM2835_CLOCK_TEC
8444. BCM2835_CLOCK_TIMER
8445. BCM2835_CLOCK_TSENS
8446. BCM2835_CLOCK_UART
8447. BCM2835_CLOCK_V3D
8448. BCM2835_CLOCK_VEC
8449. BCM2835_CLOCK_VPU
8450. BCM2835_DMA_ABORT
8451. BCM2835_DMA_ACTIVE
8452. BCM2835_DMA_ADDR
8453. BCM2835_DMA_BURST_LENGTH
8454. BCM2835_DMA_CHAN
8455. BCM2835_DMA_CHANIO
8456. BCM2835_DMA_CHAN_NAME_SIZE
8457. BCM2835_DMA_CS
8458. BCM2835_DMA_DATA_TYPE_S128
8459. BCM2835_DMA_DATA_TYPE_S16
8460. BCM2835_DMA_DATA_TYPE_S32
8461. BCM2835_DMA_DATA_TYPE_S8
8462. BCM2835_DMA_DEBUG
8463. BCM2835_DMA_DEBUG_FIFO_ERR
8464. BCM2835_DMA_DEBUG_ID_BITS
8465. BCM2835_DMA_DEBUG_ID_SHIFT
8466. BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR
8467. BCM2835_DMA_DEBUG_LITE
8468. BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_BITS
8469. BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_SHIFT
8470. BCM2835_DMA_DEBUG_READ_ERR
8471. BCM2835_DMA_DEBUG_STATE_BITS
8472. BCM2835_DMA_DEBUG_STATE_SHIFT
8473. BCM2835_DMA_DEBUG_VERSION_BITS
8474. BCM2835_DMA_DEBUG_VERSION_SHIFT
8475. BCM2835_DMA_DEST_AD
8476. BCM2835_DMA_DIS_DEBUG
8477. BCM2835_DMA_DREQ
8478. BCM2835_DMA_D_DREQ
8479. BCM2835_DMA_D_IGNORE
8480. BCM2835_DMA_D_INC
8481. BCM2835_DMA_D_WIDTH
8482. BCM2835_DMA_ENABLE
8483. BCM2835_DMA_END
8484. BCM2835_DMA_ERR
8485. BCM2835_DMA_INT
8486. BCM2835_DMA_INT_EN
8487. BCM2835_DMA_INT_STATUS
8488. BCM2835_DMA_ISHELD
8489. BCM2835_DMA_ISPAUSED
8490. BCM2835_DMA_LEN
8491. BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED
8492. BCM2835_DMA_NEXTCB
8493. BCM2835_DMA_NO_WIDE_BURSTS
8494. BCM2835_DMA_PANIC_PRIORITY
8495. BCM2835_DMA_PER_MAP
8496. BCM2835_DMA_PRIORITY
8497. BCM2835_DMA_RESET
8498. BCM2835_DMA_SOURCE_AD
8499. BCM2835_DMA_STRIDE
8500. BCM2835_DMA_S_DREQ
8501. BCM2835_DMA_S_IGNORE
8502. BCM2835_DMA_S_INC
8503. BCM2835_DMA_S_WIDTH
8504. BCM2835_DMA_TDMODE
8505. BCM2835_DMA_TI
8506. BCM2835_DMA_WAIT
8507. BCM2835_DMA_WAITING_FOR_WRITES
8508. BCM2835_DMA_WAIT_FOR_WRITES
8509. BCM2835_DMA_WAIT_RESP
8510. BCM2835_FSEL_ALT0
8511. BCM2835_FSEL_ALT1
8512. BCM2835_FSEL_ALT2
8513. BCM2835_FSEL_ALT3
8514. BCM2835_FSEL_ALT4
8515. BCM2835_FSEL_ALT5
8516. BCM2835_FSEL_COUNT
8517. BCM2835_FSEL_GPIO_IN
8518. BCM2835_FSEL_GPIO_OUT
8519. BCM2835_FSEL_MASK
8520. BCM2835_GPIO_PIN
8521. BCM2835_I2C_A
8522. BCM2835_I2C_C
8523. BCM2835_I2C_CDIV_MAX
8524. BCM2835_I2C_CDIV_MIN
8525. BCM2835_I2C_CLKT
8526. BCM2835_I2C_C_CLEAR
8527. BCM2835_I2C_C_I2CEN
8528. BCM2835_I2C_C_INTD
8529. BCM2835_I2C_C_INTR
8530. BCM2835_I2C_C_INTT
8531. BCM2835_I2C_C_READ
8532. BCM2835_I2C_C_ST
8533. BCM2835_I2C_DEL
8534. BCM2835_I2C_DIV
8535. BCM2835_I2C_DLEN
8536. BCM2835_I2C_FEDL_SHIFT
8537. BCM2835_I2C_FIFO
8538. BCM2835_I2C_REDL_SHIFT
8539. BCM2835_I2C_S
8540. BCM2835_I2C_S_CLKT
8541. BCM2835_I2C_S_DONE
8542. BCM2835_I2C_S_ERR
8543. BCM2835_I2C_S_LEN
8544. BCM2835_I2C_S_RXD
8545. BCM2835_I2C_S_RXF
8546. BCM2835_I2C_S_RXR
8547. BCM2835_I2C_S_TA
8548. BCM2835_I2C_S_TXD
8549. BCM2835_I2C_S_TXE
8550. BCM2835_I2C_S_TXW
8551. BCM2835_I2S_CH1
8552. BCM2835_I2S_CH1_POS
8553. BCM2835_I2S_CH2
8554. BCM2835_I2S_CH2_POS
8555. BCM2835_I2S_CHEN
8556. BCM2835_I2S_CHPOS
8557. BCM2835_I2S_CHWEX
8558. BCM2835_I2S_CHWID
8559. BCM2835_I2S_CLKDIS
8560. BCM2835_I2S_CLKI
8561. BCM2835_I2S_CLKM
8562. BCM2835_I2S_CS_A_REG
8563. BCM2835_I2S_CS_RXERR
8564. BCM2835_I2S_CS_TXERR
8565. BCM2835_I2S_DMAEN
8566. BCM2835_I2S_DREQ_A_REG
8567. BCM2835_I2S_EN
8568. BCM2835_I2S_FIFO_A_REG
8569. BCM2835_I2S_FLEN
8570. BCM2835_I2S_FRXP
8571. BCM2835_I2S_FSI
8572. BCM2835_I2S_FSLEN
8573. BCM2835_I2S_FSM
8574. BCM2835_I2S_FTXP
8575. BCM2835_I2S_GRAY_REG
8576. BCM2835_I2S_INTEN_A_REG
8577. BCM2835_I2S_INTSTC_A_REG
8578. BCM2835_I2S_INT_RXERR
8579. BCM2835_I2S_INT_RXR
8580. BCM2835_I2S_INT_TXERR
8581. BCM2835_I2S_INT_TXW
8582. BCM2835_I2S_MAX_FRAME_LENGTH
8583. BCM2835_I2S_MODE_A_REG
8584. BCM2835_I2S_PDME
8585. BCM2835_I2S_PDMN
8586. BCM2835_I2S_RX
8587. BCM2835_I2S_RXCLR
8588. BCM2835_I2S_RXC_A_REG
8589. BCM2835_I2S_RXD
8590. BCM2835_I2S_RXF
8591. BCM2835_I2S_RXON
8592. BCM2835_I2S_RXR
8593. BCM2835_I2S_RXSEX
8594. BCM2835_I2S_RXSYNC
8595. BCM2835_I2S_RXTHR
8596. BCM2835_I2S_RX_PANIC
8597. BCM2835_I2S_STBY
8598. BCM2835_I2S_SYNC
8599. BCM2835_I2S_TX
8600. BCM2835_I2S_TXCLR
8601. BCM2835_I2S_TXC_A_REG
8602. BCM2835_I2S_TXD
8603. BCM2835_I2S_TXE
8604. BCM2835_I2S_TXON
8605. BCM2835_I2S_TXSYNC
8606. BCM2835_I2S_TXTHR
8607. BCM2835_I2S_TXW
8608. BCM2835_I2S_TX_PANIC
8609. BCM2835_MAX_FB_RATE
8610. BCM2835_MFD_PM_H
8611. BCM2835_NUM_BANKS
8612. BCM2835_NUM_GPIOS
8613. BCM2835_NUM_IRQS
8614. BCM2835_PINCONF_PARAM_PULL
8615. BCM2835_PIN_BITMAP_SZ
8616. BCM2835_PLLA
8617. BCM2835_PLLA_CCP2
8618. BCM2835_PLLA_CORE
8619. BCM2835_PLLA_DSI0
8620. BCM2835_PLLA_PER
8621. BCM2835_PLLB
8622. BCM2835_PLLB_ARM
8623. BCM2835_PLLC
8624. BCM2835_PLLC_CORE0
8625. BCM2835_PLLC_CORE1
8626. BCM2835_PLLC_CORE2
8627. BCM2835_PLLC_PER
8628. BCM2835_PLLD
8629. BCM2835_PLLD_CORE
8630. BCM2835_PLLD_DSI0
8631. BCM2835_PLLD_DSI1
8632. BCM2835_PLLD_PER
8633. BCM2835_PLLH
8634. BCM2835_PLLH_AUX
8635. BCM2835_PLLH_PIX
8636. BCM2835_PLLH_RCAL
8637. BCM2835_POWER_DOMAIN_CAM0
8638. BCM2835_POWER_DOMAIN_CAM1
8639. BCM2835_POWER_DOMAIN_CCP2TX
8640. BCM2835_POWER_DOMAIN_COUNT
8641. BCM2835_POWER_DOMAIN_DSI0
8642. BCM2835_POWER_DOMAIN_DSI1
8643. BCM2835_POWER_DOMAIN_GRAFX
8644. BCM2835_POWER_DOMAIN_GRAFX_V3D
8645. BCM2835_POWER_DOMAIN_HDMI
8646. BCM2835_POWER_DOMAIN_IMAGE
8647. BCM2835_POWER_DOMAIN_IMAGE_H264
8648. BCM2835_POWER_DOMAIN_IMAGE_ISP
8649. BCM2835_POWER_DOMAIN_IMAGE_PERI
8650. BCM2835_POWER_DOMAIN_USB
8651. BCM2835_PUD_DOWN
8652. BCM2835_PUD_OFF
8653. BCM2835_PUD_UP
8654. BCM2835_RESET_COUNT
8655. BCM2835_RESET_H264
8656. BCM2835_RESET_ISP
8657. BCM2835_RESET_V3D
8658. BCM2835_SPI_CLK
8659. BCM2835_SPI_CS
8660. BCM2835_SPI_CS_ADCS
8661. BCM2835_SPI_CS_CLEAR_RX
8662. BCM2835_SPI_CS_CLEAR_TX
8663. BCM2835_SPI_CS_CPHA
8664. BCM2835_SPI_CS_CPOL
8665. BCM2835_SPI_CS_CSPOL
8666. BCM2835_SPI_CS_CSPOL0
8667. BCM2835_SPI_CS_CSPOL1
8668. BCM2835_SPI_CS_CSPOL2
8669. BCM2835_SPI_CS_CS_01
8670. BCM2835_SPI_CS_CS_10
8671. BCM2835_SPI_CS_DMAEN
8672. BCM2835_SPI_CS_DMA_LEN
8673. BCM2835_SPI_CS_DONE
8674. BCM2835_SPI_CS_INTD
8675. BCM2835_SPI_CS_INTR
8676. BCM2835_SPI_CS_LEN
8677. BCM2835_SPI_CS_LEN_LONG
8678. BCM2835_SPI_CS_REN
8679. BCM2835_SPI_CS_RXD
8680. BCM2835_SPI_CS_RXF
8681. BCM2835_SPI_CS_RXR
8682. BCM2835_SPI_CS_TA
8683. BCM2835_SPI_CS_TXD
8684. BCM2835_SPI_DC
8685. BCM2835_SPI_DLEN
8686. BCM2835_SPI_DMA_MIN_LENGTH
8687. BCM2835_SPI_FIFO
8688. BCM2835_SPI_FIFO_SIZE
8689. BCM2835_SPI_FIFO_SIZE_3_4
8690. BCM2835_SPI_LTOH
8691. BCM2835_SPI_MODE_BITS
8692. BCM2835_SPI_NUM_CS
8693. BCM2835_TS_TSENSCTL
8694. BCM2835_TS_TSENSCTL_CLR_INT
8695. BCM2835_TS_TSENSCTL_CTRL_BITS
8696. BCM2835_TS_TSENSCTL_CTRL_DEFAULT
8697. BCM2835_TS_TSENSCTL_CTRL_MASK
8698. BCM2835_TS_TSENSCTL_CTRL_SHIFT
8699. BCM2835_TS_TSENSCTL_DIRECT
8700. BCM2835_TS_TSENSCTL_EN_INT
8701. BCM2835_TS_TSENSCTL_PRWDW
8702. BCM2835_TS_TSENSCTL_REGULEN
8703. BCM2835_TS_TSENSCTL_RSTB
8704. BCM2835_TS_TSENSCTL_RSTDELAY_BITS
8705. BCM2835_TS_TSENSCTL_RSTDELAY_SHIFT
8706. BCM2835_TS_TSENSCTL_THOLD_BITS
8707. BCM2835_TS_TSENSCTL_THOLD_MASK
8708. BCM2835_TS_TSENSCTL_THOLD_SHIFT
8709. BCM2835_TS_TSENSSTAT
8710. BCM2835_TS_TSENSSTAT_DATA_BITS
8711. BCM2835_TS_TSENSSTAT_DATA_MASK
8712. BCM2835_TS_TSENSSTAT_DATA_SHIFT
8713. BCM2835_TS_TSENSSTAT_INTERRUPT
8714. BCM2835_TS_TSENSSTAT_VALID
8715. BCM3368_CPU_ID
8716. BCM3368_RESET_DSL
8717. BCM3368_RESET_ENET
8718. BCM3368_RESET_ENETSW
8719. BCM3368_RESET_EPHY
8720. BCM3368_RESET_MPI
8721. BCM3368_RESET_PCIE
8722. BCM3368_RESET_PCIE_EXT
8723. BCM3368_RESET_PCM
8724. BCM3368_RESET_SAR
8725. BCM3368_RESET_SPI
8726. BCM3368_RESET_USBD
8727. BCM3368_RESET_USBH
8728. BCM3510_16VSB
8729. BCM3510_8VSB
8730. BCM3510_DEFAULT_FIRMWARE
8731. BCM3510_DEF_CONFIG_VERSION
8732. BCM3510_DEF_DEMOD_VERSION
8733. BCM3510_DEF_MICROCODE_VERSION
8734. BCM3510_DEF_SCRIPT_VERSION
8735. BCM3510_H
8736. BCM3510_IF_CABLE
8737. BCM3510_IF_TERRESTRIAL
8738. BCM3510_IF_USE_CMD
8739. BCM3510_QAM128
8740. BCM3510_QAM16
8741. BCM3510_QAM256
8742. BCM3510_QAM32
8743. BCM3510_QAM64
8744. BCM3510_SR_16QAM
8745. BCM3510_SR_256QAM
8746. BCM3510_SR_8VSB
8747. BCM3510_SR_MISC
8748. BCM3510_SR_USE_CMD
8749. BCM3510_SYMBOL_RATE
8750. BCM4313_CHIP_ID
8751. BCM4313_D11N2G_ID
8752. BCM4320_DEFAULT_TXPOWER_DBM_100
8753. BCM4320_DEFAULT_TXPOWER_DBM_25
8754. BCM4320_DEFAULT_TXPOWER_DBM_50
8755. BCM4320_DEFAULT_TXPOWER_DBM_75
8756. BCM43224_CHIP_ID
8757. BCM43224_D11N_ID
8758. BCM43224_D11N_ID_VEN1
8759. BCM43225_D11N2G_ID
8760. BCM43236_D11N2G_ID
8761. BCM43236_D11N_ID
8762. BCM4329_CORE_ARM_BASE
8763. BCM4329_CORE_BUS_BASE
8764. BCM4329_CORE_SOCRAM_BASE
8765. BCM4331_MMIO_SIZE
8766. BCM4331_PM_CAP
8767. BCM47XXPART_BYTES_TO_READ
8768. BCM47XXPART_MAX_PARTS
8769. BCM47XXSFLASH_TYPE_ATMEL
8770. BCM47XXSFLASH_TYPE_ST
8771. BCM47XXSFLASH_WINDOW_SZ
8772. BCM47XX_BOARD_ASUS_RTAC66U
8773. BCM47XX_BOARD_ASUS_RTN10
8774. BCM47XX_BOARD_ASUS_RTN10D
8775. BCM47XX_BOARD_ASUS_RTN10U
8776. BCM47XX_BOARD_ASUS_RTN12
8777. BCM47XX_BOARD_ASUS_RTN12B1
8778. BCM47XX_BOARD_ASUS_RTN12C1
8779. BCM47XX_BOARD_ASUS_RTN12D1
8780. BCM47XX_BOARD_ASUS_RTN12HP
8781. BCM47XX_BOARD_ASUS_RTN15U
8782. BCM47XX_BOARD_ASUS_RTN16
8783. BCM47XX_BOARD_ASUS_RTN53
8784. BCM47XX_BOARD_ASUS_RTN66U
8785. BCM47XX_BOARD_ASUS_WL300G
8786. BCM47XX_BOARD_ASUS_WL320GE
8787. BCM47XX_BOARD_ASUS_WL330GE
8788. BCM47XX_BOARD_ASUS_WL500G
8789. BCM47XX_BOARD_ASUS_WL500GD
8790. BCM47XX_BOARD_ASUS_WL500GPV1
8791. BCM47XX_BOARD_ASUS_WL500GPV2
8792. BCM47XX_BOARD_ASUS_WL500W
8793. BCM47XX_BOARD_ASUS_WL520GC
8794. BCM47XX_BOARD_ASUS_WL520GU
8795. BCM47XX_BOARD_ASUS_WL700GE
8796. BCM47XX_BOARD_ASUS_WLHDD
8797. BCM47XX_BOARD_BELKIN_F7D3301
8798. BCM47XX_BOARD_BELKIN_F7D3302
8799. BCM47XX_BOARD_BELKIN_F7D4301
8800. BCM47XX_BOARD_BELKIN_F7D4302
8801. BCM47XX_BOARD_BELKIN_F7D4401
8802. BCM47XX_BOARD_BUFFALO_WBR2_G54
8803. BCM47XX_BOARD_BUFFALO_WHR2_A54G54
8804. BCM47XX_BOARD_BUFFALO_WHR_G125
8805. BCM47XX_BOARD_BUFFALO_WHR_G54S
8806. BCM47XX_BOARD_BUFFALO_WHR_HP_G54
8807. BCM47XX_BOARD_BUFFALO_WLA2_G54L
8808. BCM47XX_BOARD_BUFFALO_WZR_G300N
8809. BCM47XX_BOARD_BUFFALO_WZR_RS_G54
8810. BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP
8811. BCM47XX_BOARD_CISCO_M10V1
8812. BCM47XX_BOARD_CISCO_M20V1
8813. BCM47XX_BOARD_DELL_TM2300
8814. BCM47XX_BOARD_DLINK_DIR130
8815. BCM47XX_BOARD_DLINK_DIR330
8816. BCM47XX_BOARD_HUAWEI_E970
8817. BCM47XX_BOARD_LINKSYS_E1000V1
8818. BCM47XX_BOARD_LINKSYS_E1000V2
8819. BCM47XX_BOARD_LINKSYS_E1000V21
8820. BCM47XX_BOARD_LINKSYS_E1200V2
8821. BCM47XX_BOARD_LINKSYS_E2000V1
8822. BCM47XX_BOARD_LINKSYS_E3000V1
8823. BCM47XX_BOARD_LINKSYS_E3200V1
8824. BCM47XX_BOARD_LINKSYS_E4200V1
8825. BCM47XX_BOARD_LINKSYS_E900V1
8826. BCM47XX_BOARD_LINKSYS_WRT150NV1
8827. BCM47XX_BOARD_LINKSYS_WRT150NV11
8828. BCM47XX_BOARD_LINKSYS_WRT160NV1
8829. BCM47XX_BOARD_LINKSYS_WRT160NV3
8830. BCM47XX_BOARD_LINKSYS_WRT300NV11
8831. BCM47XX_BOARD_LINKSYS_WRT300N_V1
8832. BCM47XX_BOARD_LINKSYS_WRT310NV1
8833. BCM47XX_BOARD_LINKSYS_WRT310NV2
8834. BCM47XX_BOARD_LINKSYS_WRT54G3GV2
8835. BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101
8836. BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467
8837. BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708
8838. BCM47XX_BOARD_LINKSYS_WRT600N_V11
8839. BCM47XX_BOARD_LINKSYS_WRT610NV1
8840. BCM47XX_BOARD_LINKSYS_WRT610NV2
8841. BCM47XX_BOARD_LINKSYS_WRTSL54GS
8842. BCM47XX_BOARD_LUXUL_ABR_4400_V1
8843. BCM47XX_BOARD_LUXUL_XAP_1210_V1
8844. BCM47XX_BOARD_LUXUL_XAP_1230_V1
8845. BCM47XX_BOARD_LUXUL_XAP_1240_V1
8846. BCM47XX_BOARD_LUXUL_XAP_1500_V1
8847. BCM47XX_BOARD_LUXUL_XAP_310_V1
8848. BCM47XX_BOARD_LUXUL_XBR_4400_V1
8849. BCM47XX_BOARD_LUXUL_XVW_P30_V1
8850. BCM47XX_BOARD_LUXUL_XWR_1750_V1
8851. BCM47XX_BOARD_LUXUL_XWR_600_V1
8852. BCM47XX_BOARD_MAX_NAME
8853. BCM47XX_BOARD_MICROSOFT_MN700
8854. BCM47XX_BOARD_MOTOROLA_WE800G
8855. BCM47XX_BOARD_MOTOROLA_WR850GP
8856. BCM47XX_BOARD_MOTOROLA_WR850GV2V3
8857. BCM47XX_BOARD_NETGEAR_R6200_V1
8858. BCM47XX_BOARD_NETGEAR_WGR614V8
8859. BCM47XX_BOARD_NETGEAR_WGR614V9
8860. BCM47XX_BOARD_NETGEAR_WGR614_V10
8861. BCM47XX_BOARD_NETGEAR_WNDR3300
8862. BCM47XX_BOARD_NETGEAR_WNDR3400V1
8863. BCM47XX_BOARD_NETGEAR_WNDR3400V2
8864. BCM47XX_BOARD_NETGEAR_WNDR3400VCNA
8865. BCM47XX_BOARD_NETGEAR_WNDR3400_V3
8866. BCM47XX_BOARD_NETGEAR_WNDR3700V3
8867. BCM47XX_BOARD_NETGEAR_WNDR4000
8868. BCM47XX_BOARD_NETGEAR_WNDR4500V1
8869. BCM47XX_BOARD_NETGEAR_WNDR4500V2
8870. BCM47XX_BOARD_NETGEAR_WNR1000_V3
8871. BCM47XX_BOARD_NETGEAR_WNR2000
8872. BCM47XX_BOARD_NETGEAR_WNR3500L
8873. BCM47XX_BOARD_NETGEAR_WNR3500U
8874. BCM47XX_BOARD_NETGEAR_WNR3500V2
8875. BCM47XX_BOARD_NETGEAR_WNR3500V2VC
8876. BCM47XX_BOARD_NETGEAR_WNR834BV2
8877. BCM47XX_BOARD_NO
8878. BCM47XX_BOARD_PHICOMM_M1
8879. BCM47XX_BOARD_SIEMENS_SE505V2
8880. BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE
8881. BCM47XX_BOARD_UNKNOWN
8882. BCM47XX_BOARD_ZTE_H218N
8883. BCM47XX_BUS_TYPE_BCMA
8884. BCM47XX_BUS_TYPE_SSB
8885. BCM47XX_GPIO_KEY
8886. BCM47XX_GPIO_KEY_H
8887. BCM47XX_GPIO_LED
8888. BCM47XX_GPIO_LED_TRIGGER
8889. BCM47XX_SERIAL_ADDR
8890. BCM53010_DEVICE_ID
8891. BCM53011_DEVICE_ID
8892. BCM53012_DEVICE_ID
8893. BCM53018_DEVICE_ID
8894. BCM53019_DEVICE_ID
8895. BCM53115_DEVICE_ID
8896. BCM53125_DEVICE_ID
8897. BCM53128_DEVICE_ID
8898. BCM5325_DEVICE_ID
8899. BCM5365_DEVICE_ID
8900. BCM5389_DEVICE_ID
8901. BCM5395_DEVICE_ID
8902. BCM5397_DEVICE_ID
8903. BCM5398_DEVICE_ID
8904. BCM5421_MODE_MASK
8905. BCM54612E_EXP_SPARE0
8906. BCM54612E_LED4_CLK125OUT_EN
8907. BCM54616_E_PHY_ID
8908. BCM5461_FIBER_DUPLEX
8909. BCM5461_FIBER_LINK
8910. BCM5461_MODE_MASK
8911. BCM5464R_AUX_CTL
8912. BCM5464R_AUX_CTL_DIAG_MODE
8913. BCM5464R_AUX_CTL_ER100
8914. BCM5464R_AUX_CTL_ER1000
8915. BCM5464R_AUX_CTL_ER1000_SHIFT
8916. BCM5464R_AUX_CTL_ER100_SHIFT
8917. BCM5464R_AUX_CTL_EXT_LB
8918. BCM5464R_AUX_CTL_EXT_PLEN
8919. BCM5464R_AUX_CTL_PRESP_DIS
8920. BCM5464R_AUX_CTL_RESV1
8921. BCM5464R_AUX_CTL_RESV2
8922. BCM5464R_AUX_CTL_RESV3
8923. BCM5464R_AUX_CTL_SR_SEL
8924. BCM5464R_AUX_CTL_SR_SEL_SHIFT
8925. BCM5464R_AUX_CTL_WRITE_1
8926. BCM5464R_CTRL1000_AS_MASTER
8927. BCM5464R_CTRL1000_ENABLE_AS_MASTER
8928. BCM54810_EXP_BROADREACH_LRE_MISC_CTL
8929. BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN
8930. BCM54810_SHD_CLK_CTL
8931. BCM54810_SHD_CLK_CTL_GTXCLK_EN
8932. BCM5482_SHD_LEDS1
8933. BCM5482_SHD_LEDS1_LED1
8934. BCM5482_SHD_LEDS1_LED3
8935. BCM5482_SHD_MODE
8936. BCM5482_SHD_MODE_1000BX
8937. BCM5482_SHD_SSD
8938. BCM5482_SHD_SSD_EN
8939. BCM5482_SHD_SSD_LEDM
8940. BCM5482_SSD_1000BX_CTL
8941. BCM5482_SSD_1000BX_CTL_PWRDOWN
8942. BCM5482_SSD_SGMII_SLAVE
8943. BCM5482_SSD_SGMII_SLAVE_AD
8944. BCM5482_SSD_SGMII_SLAVE_EN
8945. BCM54XX_COPPER
8946. BCM54XX_FIBER
8947. BCM54XX_GBIC
8948. BCM54XX_SGMII
8949. BCM54XX_SHD_APD
8950. BCM54XX_SHD_APD_EN
8951. BCM54XX_SHD_RGMII_MODE
8952. BCM54XX_SHD_SCR2
8953. BCM54XX_SHD_SCR2_WSPD_RTRY_DIS
8954. BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK
8955. BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET
8956. BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT
8957. BCM54XX_SHD_SCR3
8958. BCM54XX_SHD_SCR3_DEF_CLK125
8959. BCM54XX_SHD_SCR3_DLLAPD_DIS
8960. BCM54XX_SHD_SCR3_TRDDAPD
8961. BCM54XX_UNKNOWN
8962. BCM5706
8963. BCM5706S
8964. BCM5708
8965. BCM5708S
8966. BCM5708S_1000X_CTL1
8967. BCM5708S_1000X_CTL1_AUTODET_EN
8968. BCM5708S_1000X_CTL1_FIBER_MODE
8969. BCM5708S_1000X_CTL2
8970. BCM5708S_1000X_CTL2_PLLEL_DET_EN
8971. BCM5708S_1000X_STAT1
8972. BCM5708S_1000X_STAT1_FD
8973. BCM5708S_1000X_STAT1_LINK
8974. BCM5708S_1000X_STAT1_RX_PAUSE
8975. BCM5708S_1000X_STAT1_SGMII
8976. BCM5708S_1000X_STAT1_SPEED_10
8977. BCM5708S_1000X_STAT1_SPEED_100
8978. BCM5708S_1000X_STAT1_SPEED_1G
8979. BCM5708S_1000X_STAT1_SPEED_2G5
8980. BCM5708S_1000X_STAT1_SPEED_MASK
8981. BCM5708S_1000X_STAT1_TX_PAUSE
8982. BCM5708S_BLK_ADDR
8983. BCM5708S_BLK_ADDR_DIG
8984. BCM5708S_BLK_ADDR_DIG3
8985. BCM5708S_BLK_ADDR_TX_MISC
8986. BCM5708S_BMCR_FORCE_2500
8987. BCM5708S_DIG_3_0
8988. BCM5708S_DIG_3_0_USE_IEEE
8989. BCM5708S_TX_ACTL1
8990. BCM5708S_TX_ACTL1_DRIVER_VCM
8991. BCM5708S_TX_ACTL3
8992. BCM5708S_UP1
8993. BCM5708S_UP1_2G5
8994. BCM5709
8995. BCM5709S
8996. BCM5709_FLASH_BYTE_ADDR_MASK
8997. BCM5709_FLASH_PAGE_BITS
8998. BCM5709_FLASH_PAGE_SIZE
8999. BCM5709_FLASH_PHY_PAGE_SIZE
9000. BCM5716
9001. BCM5716S
9002. BCM57301
9003. BCM57302
9004. BCM57304
9005. BCM57311
9006. BCM57312
9007. BCM57314
9008. BCM57402
9009. BCM57402_NPAR
9010. BCM57404
9011. BCM57404_NPAR
9012. BCM57406
9013. BCM57406_NPAR
9014. BCM57407
9015. BCM57407_NPAR
9016. BCM57407_SFP
9017. BCM57412
9018. BCM57412_NPAR
9019. BCM57414
9020. BCM57414_NPAR
9021. BCM57416
9022. BCM57416_NPAR
9023. BCM57416_SFP
9024. BCM57417
9025. BCM57417_NPAR
9026. BCM57417_SFP
9027. BCM57452
9028. BCM57454
9029. BCM5745x_NPAR
9030. BCM57502
9031. BCM57502_NPAR
9032. BCM57504
9033. BCM57504_NPAR
9034. BCM57508
9035. BCM57508_NPAR
9036. BCM57710
9037. BCM57711
9038. BCM57711E
9039. BCM57712
9040. BCM57712_MF
9041. BCM57712_VF
9042. BCM57800
9043. BCM57800_MF
9044. BCM57800_VF
9045. BCM57810
9046. BCM57810_MF
9047. BCM57810_VF
9048. BCM57811
9049. BCM57811_MF
9050. BCM57811_VF
9051. BCM57840_2_20
9052. BCM57840_4_10
9053. BCM57840_MF
9054. BCM57840_MFO
9055. BCM57840_O
9056. BCM57840_VF
9057. BCM583XX_DEVICE_ID
9058. BCM58700
9059. BCM58802
9060. BCM58804
9061. BCM58808
9062. BCM58XX_DEVICE_ID
9063. BCM590XX_CSRPMCTRL1
9064. BCM590XX_CSRVOUT1
9065. BCM590XX_GPLDO1CTRL
9066. BCM590XX_GPLDO1PMCTRL1
9067. BCM590XX_GPLDO2CTRL
9068. BCM590XX_GPLDO2PMCTRL1
9069. BCM590XX_GPLDO3CTRL
9070. BCM590XX_GPLDO3PMCTRL1
9071. BCM590XX_GPLDO4CTRL
9072. BCM590XX_GPLDO4PMCTRL1
9073. BCM590XX_GPLDO5CTRL
9074. BCM590XX_GPLDO5PMCTRL1
9075. BCM590XX_GPLDO6CTRL
9076. BCM590XX_GPLDO6PMCTRL1
9077. BCM590XX_IOSR1PMCTRL1
9078. BCM590XX_IOSR2PMCTRL1
9079. BCM590XX_LDO_VSEL_MASK
9080. BCM590XX_MAX_REGISTER_PRI
9081. BCM590XX_MAX_REGISTER_SEC
9082. BCM590XX_MSRPMCTRL1
9083. BCM590XX_NUM_REGS
9084. BCM590XX_OTG_CTRL
9085. BCM590XX_REG_AUDLDO
9086. BCM590XX_REG_CAMLDO1
9087. BCM590XX_REG_CAMLDO2
9088. BCM590XX_REG_CSR
9089. BCM590XX_REG_ENABLE
9090. BCM590XX_REG_GPLDO1
9091. BCM590XX_REG_GPLDO2
9092. BCM590XX_REG_GPLDO3
9093. BCM590XX_REG_GPLDO4
9094. BCM590XX_REG_GPLDO5
9095. BCM590XX_REG_GPLDO6
9096. BCM590XX_REG_IOSR1
9097. BCM590XX_REG_IOSR2
9098. BCM590XX_REG_IS_GPLDO
9099. BCM590XX_REG_IS_LDO
9100. BCM590XX_REG_IS_VBUS
9101. BCM590XX_REG_MICLDO
9102. BCM590XX_REG_MMCLDO1
9103. BCM590XX_REG_MMCLDO2
9104. BCM590XX_REG_MSR
9105. BCM590XX_REG_RANGES
9106. BCM590XX_REG_RFLDO
9107. BCM590XX_REG_SDLDO
9108. BCM590XX_REG_SDSR1
9109. BCM590XX_REG_SDSR2
9110. BCM590XX_REG_SDXLDO
9111. BCM590XX_REG_SIMLDO1
9112. BCM590XX_REG_SIMLDO2
9113. BCM590XX_REG_TABLE
9114. BCM590XX_REG_USBLDO
9115. BCM590XX_REG_VBUS
9116. BCM590XX_REG_VIBLDO
9117. BCM590XX_REG_VSR
9118. BCM590XX_RFLDOCTRL
9119. BCM590XX_RFLDOPMCTRL1
9120. BCM590XX_SDSR1PMCTRL1
9121. BCM590XX_SDSR2PMCTRL1
9122. BCM590XX_SR_VSEL_MASK
9123. BCM590XX_VBUS_ENABLE
9124. BCM590XX_VSRPMCTRL1
9125. BCM5974_DEVICE
9126. BCM5974_WELLSPRING_MODE_READ_REQUEST_ID
9127. BCM5974_WELLSPRING_MODE_WRITE_REQUEST_ID
9128. BCM63138_CTLRDY
9129. BCM63138_NAND_INT_EN
9130. BCM63138_NAND_INT_STATUS
9131. BCM6328_CPU_ID
9132. BCM6328_INIT_MASK
9133. BCM6328_LED_DEF_DELAY
9134. BCM6328_LED_FAST_INTV_MASK
9135. BCM6328_LED_FAST_INTV_SHIFT
9136. BCM6328_LED_INTERVAL_MS
9137. BCM6328_LED_INTV_MASK
9138. BCM6328_LED_MAX_COUNT
9139. BCM6328_LED_MODE_BLINK
9140. BCM6328_LED_MODE_FAST
9141. BCM6328_LED_MODE_MASK
9142. BCM6328_LED_MODE_OFF
9143. BCM6328_LED_MODE_ON
9144. BCM6328_LED_SHIFT
9145. BCM6328_LED_SHIFT_TEST
9146. BCM6328_LED_TEST
9147. BCM6328_REG_HWDIS
9148. BCM6328_REG_INIT
9149. BCM6328_REG_LNKACTSEL_HI
9150. BCM6328_REG_LNKACTSEL_LO
9151. BCM6328_REG_MODE_HI
9152. BCM6328_REG_MODE_LO
9153. BCM6328_REG_RBACK
9154. BCM6328_REG_SERMUX
9155. BCM6328_REG_STROBE
9156. BCM6328_RESET_DSL
9157. BCM6328_RESET_ENET
9158. BCM6328_RESET_ENETSW
9159. BCM6328_RESET_EPHY
9160. BCM6328_RESET_MPI
9161. BCM6328_RESET_PCIE
9162. BCM6328_RESET_PCIE_EXT
9163. BCM6328_RESET_PCM
9164. BCM6328_RESET_SAR
9165. BCM6328_RESET_SPI
9166. BCM6328_RESET_USBD
9167. BCM6328_RESET_USBH
9168. BCM6328_SERIAL_LED_CLK_NPOL
9169. BCM6328_SERIAL_LED_DATA_PPOL
9170. BCM6328_SERIAL_LED_EN
9171. BCM6328_SERIAL_LED_MUX
9172. BCM6328_SERIAL_LED_SHIFT_DIR
9173. BCM6328_TP1_DISABLED
9174. BCM6338_CPU_ID
9175. BCM6338_RESET_DSL
9176. BCM6338_RESET_ENET
9177. BCM6338_RESET_ENETSW
9178. BCM6338_RESET_EPHY
9179. BCM6338_RESET_MPI
9180. BCM6338_RESET_PCIE
9181. BCM6338_RESET_PCIE_EXT
9182. BCM6338_RESET_PCM
9183. BCM6338_RESET_SAR
9184. BCM6338_RESET_SPI
9185. BCM6338_RESET_USBD
9186. BCM6338_RESET_USBH
9187. BCM6345_CPU_ID
9188. BCM6348_CPU_ID
9189. BCM6348_RESET_DSL
9190. BCM6348_RESET_ENET
9191. BCM6348_RESET_ENETSW
9192. BCM6348_RESET_EPHY
9193. BCM6348_RESET_MPI
9194. BCM6348_RESET_PCIE
9195. BCM6348_RESET_PCIE_EXT
9196. BCM6348_RESET_PCM
9197. BCM6348_RESET_SAR
9198. BCM6348_RESET_SPI
9199. BCM6348_RESET_USBD
9200. BCM6348_RESET_USBH
9201. BCM6358_CPU_ID
9202. BCM6358_REG_CTRL
9203. BCM6358_REG_MODE
9204. BCM6358_RESET_DSL
9205. BCM6358_RESET_ENET
9206. BCM6358_RESET_ENETSW
9207. BCM6358_RESET_EPHY
9208. BCM6358_RESET_MPI
9209. BCM6358_RESET_PCIE
9210. BCM6358_RESET_PCIE_EXT
9211. BCM6358_RESET_PCM
9212. BCM6358_RESET_SAR
9213. BCM6358_RESET_SPI
9214. BCM6358_RESET_USBD
9215. BCM6358_RESET_USBH
9216. BCM6358_SLED_BUSY
9217. BCM6358_SLED_CLKDIV_1
9218. BCM6358_SLED_CLKDIV_2
9219. BCM6358_SLED_CLKDIV_4
9220. BCM6358_SLED_CLKDIV_8
9221. BCM6358_SLED_CLKDIV_MASK
9222. BCM6358_SLED_MAX_COUNT
9223. BCM6358_SLED_POLARITY
9224. BCM6358_SLED_WAIT
9225. BCM6362_CPU_ID
9226. BCM6362_RESET_DSL
9227. BCM6362_RESET_ENET
9228. BCM6362_RESET_ENETSW
9229. BCM6362_RESET_EPHY
9230. BCM6362_RESET_MPI
9231. BCM6362_RESET_PCIE
9232. BCM6362_RESET_PCIE_EXT
9233. BCM6362_RESET_PCM
9234. BCM6362_RESET_SAR
9235. BCM6362_RESET_SPI
9236. BCM6362_RESET_USBD
9237. BCM6362_RESET_USBH
9238. BCM6368_BLOCK_ERASE
9239. BCM6368_COPY_BACK
9240. BCM6368_CPU_ID
9241. BCM6368_CTRL_READY
9242. BCM6368_DEV_RBPIN
9243. BCM6368_ECC_ERR_CORR
9244. BCM6368_ECC_ERR_UNC
9245. BCM6368_NAND_BASE_ADDR0
9246. BCM6368_NAND_BASE_ADDR1
9247. BCM6368_NAND_ENABLE_MASK
9248. BCM6368_NAND_ENABLE_SHIFT
9249. BCM6368_NAND_INT
9250. BCM6368_NAND_STATUS_MASK
9251. BCM6368_NAND_STATUS_SHIFT
9252. BCM6368_NP_READ
9253. BCM6368_PAGE_PGM
9254. BCM6368_RESET_DSL
9255. BCM6368_RESET_ENET
9256. BCM6368_RESET_ENETSW
9257. BCM6368_RESET_EPHY
9258. BCM6368_RESET_MPI
9259. BCM6368_RESET_PCIE
9260. BCM6368_RESET_PCIE_EXT
9261. BCM6368_RESET_PCM
9262. BCM6368_RESET_SAR
9263. BCM6368_RESET_SPI
9264. BCM6368_RESET_USBD
9265. BCM6368_RESET_USBH
9266. BCM63XX_BOARD_H_
9267. BCM63XX_CONSOLE
9268. BCM63XX_CPU_H_
9269. BCM63XX_CS_H
9270. BCM63XX_DEFAULT_PSI_SIZE
9271. BCM63XX_DEVICE_ID
9272. BCM63XX_DEV_ENET_H_
9273. BCM63XX_DEV_HSSPI_H
9274. BCM63XX_DEV_PCI_H_
9275. BCM63XX_DEV_PCMCIA_H_
9276. BCM63XX_DEV_SPI_H
9277. BCM63XX_DEV_UART_H_
9278. BCM63XX_DEV_USB_USBD_H_
9279. BCM63XX_ENET_H_
9280. BCM63XX_FLASH_TYPE_NAND
9281. BCM63XX_FLASH_TYPE_PARALLEL
9282. BCM63XX_FLASH_TYPE_SERIAL
9283. BCM63XX_GPIO_DIR_IN
9284. BCM63XX_GPIO_DIR_OUT
9285. BCM63XX_GPIO_H
9286. BCM63XX_IOREMAP_H_
9287. BCM63XX_IO_H_
9288. BCM63XX_IRQ_H_
9289. BCM63XX_IUDMA_H_
9290. BCM63XX_MAX_CTRL_PKT
9291. BCM63XX_NR_UARTS
9292. BCM63XX_NUM_EP
9293. BCM63XX_NUM_FIFO_PAIRS
9294. BCM63XX_NUM_IUDMA
9295. BCM63XX_NVRAM_H
9296. BCM63XX_PCMCIA_H_
9297. BCM63XX_PCMCIA_POLL_RATE
9298. BCM63XX_REGS_H_
9299. BCM63XX_RESET_DSL
9300. BCM63XX_RESET_ENET
9301. BCM63XX_RESET_ENETSW
9302. BCM63XX_RESET_EPHY
9303. BCM63XX_RESET_MPI
9304. BCM63XX_RESET_PCIE
9305. BCM63XX_RESET_PCIE_EXT
9306. BCM63XX_RESET_PCM
9307. BCM63XX_RESET_SAR
9308. BCM63XX_RESET_SPI
9309. BCM63XX_RESET_USBD
9310. BCM63XX_RESET_USBH
9311. BCM63XX_SPD_FULL
9312. BCM63XX_SPD_HIGH
9313. BCM63XX_SPI_BUS_NUM
9314. BCM63XX_SPI_MAX_CS
9315. BCM63XX_SPI_MAX_PREPEND
9316. BCM63XX_TIMER_COUNT
9317. BCM63XX_TIMER_H_
9318. BCM7278_DEVICE_ID
9319. BCM7445_DEVICE_ID
9320. BCM7XXX_28NM_EPHY
9321. BCM7XXX_28NM_GPHY
9322. BCM7XXX_40NM_EPHY
9323. BCM84858_PHY_ID
9324. BCM8704_PCS_10G_R_STATUS
9325. BCM8704_PCS_DEV_ADDR
9326. BCM8704_PHYXS_DEV_ADDR
9327. BCM8704_PHYXS_XGXS_LANE_STAT
9328. BCM8704_PMA_PMD_DEV_ADDR
9329. BCM8704_PMD_RCV_SIGDET
9330. BCM8704_USER_ANALOG_CLK
9331. BCM8704_USER_ANALOG_STATUS0
9332. BCM8704_USER_CONTROL
9333. BCM8704_USER_DEV3_ADDR
9334. BCM8704_USER_DEV4_ADDR
9335. BCM8704_USER_OPT_DIGITAL_CTRL
9336. BCM8704_USER_PMD_RX_CONTROL
9337. BCM8704_USER_PMD_TX_CONTROL
9338. BCM8704_USER_TX_ALARM_STATUS
9339. BCM87XX_10GBASER_PCS_STATUS
9340. BCM87XX_LASI_CONTROL
9341. BCM87XX_LASI_STATUS
9342. BCM87XX_PMD_RX_SIGNAL_DETECT
9343. BCM87XX_XGXS_LANE_STATUS
9344. BCM963XX_CFE_BLOCK_SIZE
9345. BCM963XX_CFE_MAGIC_OFFSET
9346. BCM963XX_CFE_VERSION_OFFSET
9347. BCM963XX_DEFAULT_PSI_SIZE
9348. BCM963XX_EXTENDED_SIZE
9349. BCM963XX_NVRAM_NAND_PART_BBT
9350. BCM963XX_NVRAM_NAND_PART_BOOT
9351. BCM963XX_NVRAM_NAND_PART_DATA
9352. BCM963XX_NVRAM_NAND_PART_OFFSET
9353. BCM963XX_NVRAM_NAND_PART_ROOTFS_1
9354. BCM963XX_NVRAM_NAND_PART_ROOTFS_2
9355. BCM963XX_NVRAM_NAND_PART_SIZE
9356. BCM963XX_NVRAM_OFFSET
9357. BCM963XX_NVRAM_V4_SIZE
9358. BCM963XX_NVRAM_V5_SIZE
9359. BCMA_ADDR_BASE
9360. BCMA_ANY_CLASS
9361. BCMA_ANY_ID
9362. BCMA_ANY_MANUF
9363. BCMA_ANY_REV
9364. BCMA_BOARD_TYPE_BCM94313BU
9365. BCMA_BOARD_TYPE_BCM94313EPA
9366. BCMA_BOARD_TYPE_BCM94313HM
9367. BCMA_BOARD_TYPE_BCM94313HMG
9368. BCMA_BOARD_TYPE_BCM943142HM
9369. BCMA_BOARD_TYPE_BCM943224M93
9370. BCMA_BOARD_TYPE_BCM943224M93A
9371. BCMA_BOARD_TYPE_BCM943224X16
9372. BCMA_BOARD_TYPE_BCM943224X21
9373. BCMA_BOARD_TYPE_BCM943224X21B
9374. BCMA_BOARD_TYPE_BCM943224X21_FCC
9375. BCMA_BOARD_TYPE_BCM943227HM4L
9376. BCMA_BOARD_TYPE_BCM943227HMB
9377. BCMA_BOARD_TYPE_BCM943228BU
9378. BCMA_BOARD_TYPE_BCM943228BU8
9379. BCMA_BOARD_TYPE_BCM943228BU9
9380. BCMA_BOARD_TYPE_BCM943228HM4L
9381. BCMA_BOARD_TYPE_BCM943228SD
9382. BCMA_BOARD_TYPE_BCM94322M35E
9383. BCMA_BOARD_TYPE_BCM94322X9
9384. BCMA_BOARD_TYPE_BCM94331BU
9385. BCMA_BOARD_TYPE_BCM94331CD
9386. BCMA_BOARD_TYPE_BCM94331CS
9387. BCMA_BOARD_TYPE_BCM94331CSAX
9388. BCMA_BOARD_TYPE_BCM94331HM
9389. BCMA_BOARD_TYPE_BCM94331MC
9390. BCMA_BOARD_TYPE_BCM94331MCH5
9391. BCMA_BOARD_TYPE_BCM94331MCI
9392. BCMA_BOARD_TYPE_BCM94331PCIEBT3AX
9393. BCMA_BOARD_TYPE_BCM94331PCIEBT4
9394. BCMA_BOARD_TYPE_BCM94331PCIEDUAL
9395. BCMA_BOARD_TYPE_BCM94331S9BU
9396. BCMA_BOARD_TYPE_BCM94331X12_2G
9397. BCMA_BOARD_TYPE_BCM94331X12_5G
9398. BCMA_BOARD_TYPE_BCM94331X19
9399. BCMA_BOARD_TYPE_BCM94331X19C
9400. BCMA_BOARD_TYPE_BCM94331X28
9401. BCMA_BOARD_TYPE_BCM94331X28B
9402. BCMA_BOARD_TYPE_BCM94331X29B
9403. BCMA_BOARD_TYPE_BCM94331X33
9404. BCMA_BOARD_TYPE_BCM94716NR2
9405. BCMA_BOARD_TYPE_BCM947188NR2
9406. BCMA_BOARD_TYPE_BCM953572BU
9407. BCMA_BOARD_TYPE_BCM953572NR2
9408. BCMA_BOARD_TYPE_BCM953572SDRNR2
9409. BCMA_BOOT_DEV_NAND
9410. BCMA_BOOT_DEV_PARALLEL
9411. BCMA_BOOT_DEV_ROM
9412. BCMA_BOOT_DEV_SERIAL
9413. BCMA_BOOT_DEV_UNK
9414. BCMA_CCB_MII_MNG_CMD_DATA
9415. BCMA_CCB_MII_MNG_CTL
9416. BCMA_CCTRL_4313_12MA_LED_DRIVE
9417. BCMA_CCTRL_43224A0_12MA_LED_DRIVE
9418. BCMA_CCTRL_43224B0_12MA_LED_DRIVE
9419. BCMA_CCTRL_43224_GPIO_TOGGLE
9420. BCMA_CC_4706_FLASHSCFG
9421. BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB
9422. BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB
9423. BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB
9424. BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB
9425. BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB
9426. BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB
9427. BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB
9428. BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK
9429. BCMA_CC_4706_FLASHSCFG_MASK
9430. BCMA_CC_4706_FLASHSCFG_NF1
9431. BCMA_CC_4706_FLASHSCFG_PF1
9432. BCMA_CC_4706_FLASHSCFG_SF1
9433. BCMA_CC_4706_FLASHSCFG_SF1_TYPE
9434. BCMA_CC_BCAST_ADDR
9435. BCMA_CC_BCAST_DATA
9436. BCMA_CC_BIST
9437. BCMA_CC_CAP
9438. BCMA_CC_CAP_64BIT
9439. BCMA_CC_CAP_BROM
9440. BCMA_CC_CAP_ECI
9441. BCMA_CC_CAP_EXT
9442. BCMA_CC_CAP_EXTBUS
9443. BCMA_CC_CAP_EXT_AOB_PRESENT
9444. BCMA_CC_CAP_EXT_GCI_PRESENT
9445. BCMA_CC_CAP_EXT_GSIO_PRESENT
9446. BCMA_CC_CAP_EXT_SECI_PRESENT
9447. BCMA_CC_CAP_EXT_SECI_PUART_PRESENT
9448. BCMA_CC_CAP_FLASHT
9449. BCMA_CC_CAP_JTAGM
9450. BCMA_CC_CAP_MIPSEB
9451. BCMA_CC_CAP_NFLASH
9452. BCMA_CC_CAP_NRUART
9453. BCMA_CC_CAP_OTPS
9454. BCMA_CC_CAP_OTPS_BASE
9455. BCMA_CC_CAP_OTPS_SHIFT
9456. BCMA_CC_CAP_PCTL
9457. BCMA_CC_CAP_PLLT
9458. BCMA_CC_CAP_PMU
9459. BCMA_CC_CAP_SPROM
9460. BCMA_CC_CAP_UARTCLK
9461. BCMA_CC_CAP_UARTCLK_INT
9462. BCMA_CC_CAP_UARTGPIO
9463. BCMA_CC_CHIPCTL
9464. BCMA_CC_CHIPSTAT
9465. BCMA_CC_CHIPST_4313_OTP_PRESENT
9466. BCMA_CC_CHIPST_4313_SPROM_PRESENT
9467. BCMA_CC_CHIPST_43228_ILP_DIV_EN
9468. BCMA_CC_CHIPST_43228_OTP_PRESENT
9469. BCMA_CC_CHIPST_43228_SDIO_MODE
9470. BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT
9471. BCMA_CC_CHIPST_43228_SDIO_RESET
9472. BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL
9473. BCMA_CC_CHIPST_4331_OTP_PRESENT
9474. BCMA_CC_CHIPST_4331_SPROM_PRESENT
9475. BCMA_CC_CHIPST_4360_XTAL_40MZ
9476. BCMA_CC_CHIPST_4706_MIPS_BENDIAN
9477. BCMA_CC_CHIPST_4706_PCIE1_DISABLE
9478. BCMA_CC_CHIPST_4706_PKG_OPTION
9479. BCMA_CC_CHIPST_4706_SFLASH_PRESENT
9480. BCMA_CC_CHIPST_4706_SFLASH_TYPE
9481. BCMA_CC_CHIPST_5357_NAND_BOOT
9482. BCMA_CC_CLKDIV
9483. BCMA_CC_CLKDIV_JTAG
9484. BCMA_CC_CLKDIV_JTAG_SHIFT
9485. BCMA_CC_CLKDIV_OTP
9486. BCMA_CC_CLKDIV_OTP_SHIFT
9487. BCMA_CC_CLKDIV_SFLASH
9488. BCMA_CC_CLKDIV_SFLASH_SHIFT
9489. BCMA_CC_CLKDIV_UART
9490. BCMA_CC_CLKSTSTR
9491. BCMA_CC_CLOCK_M2
9492. BCMA_CC_CLOCK_MIPS
9493. BCMA_CC_CLOCK_N
9494. BCMA_CC_CLOCK_PCI
9495. BCMA_CC_CLOCK_SB
9496. BCMA_CC_CORECTL
9497. BCMA_CC_CORECTL_SE
9498. BCMA_CC_CORECTL_UARTCLK0
9499. BCMA_CC_CORECTL_UARTCLKEN
9500. BCMA_CC_EROM
9501. BCMA_CC_FLASHADDR
9502. BCMA_CC_FLASHCTL
9503. BCMA_CC_FLASHCTL_ACTION
9504. BCMA_CC_FLASHCTL_AT_BLOCK_ERASE
9505. BCMA_CC_FLASHCTL_AT_BUF1_COMPARE
9506. BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM
9507. BCMA_CC_FLASHCTL_AT_BUF1_LOAD
9508. BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM
9509. BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM
9510. BCMA_CC_FLASHCTL_AT_BUF1_WRITE
9511. BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM
9512. BCMA_CC_FLASHCTL_AT_BUF2_COMPARE
9513. BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM
9514. BCMA_CC_FLASHCTL_AT_BUF2_LOAD
9515. BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM
9516. BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM
9517. BCMA_CC_FLASHCTL_AT_BUF2_WRITE
9518. BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM
9519. BCMA_CC_FLASHCTL_AT_PAGE_ERASE
9520. BCMA_CC_FLASHCTL_AT_PAGE_READ
9521. BCMA_CC_FLASHCTL_AT_READ
9522. BCMA_CC_FLASHCTL_AT_STATUS
9523. BCMA_CC_FLASHCTL_BUSY
9524. BCMA_CC_FLASHCTL_CS_ACTIVE
9525. BCMA_CC_FLASHCTL_OPCODE
9526. BCMA_CC_FLASHCTL_START
9527. BCMA_CC_FLASHCTL_ST_BE
9528. BCMA_CC_FLASHCTL_ST_CSA
9529. BCMA_CC_FLASHCTL_ST_DP
9530. BCMA_CC_FLASHCTL_ST_PP
9531. BCMA_CC_FLASHCTL_ST_RDSR
9532. BCMA_CC_FLASHCTL_ST_READ
9533. BCMA_CC_FLASHCTL_ST_RES
9534. BCMA_CC_FLASHCTL_ST_SE
9535. BCMA_CC_FLASHCTL_ST_SSE
9536. BCMA_CC_FLASHCTL_ST_WRDIS
9537. BCMA_CC_FLASHCTL_ST_WREN
9538. BCMA_CC_FLASHCTL_ST_WRSR
9539. BCMA_CC_FLASHDATA
9540. BCMA_CC_FLASHDATA_AT_ID_MASK
9541. BCMA_CC_FLASHDATA_AT_ID_SHIFT
9542. BCMA_CC_FLASHDATA_AT_MISMATCH
9543. BCMA_CC_FLASHDATA_AT_READY
9544. BCMA_CC_FLASHDATA_ST_BP_MASK
9545. BCMA_CC_FLASHDATA_ST_BP_SHIFT
9546. BCMA_CC_FLASHDATA_ST_SRWD
9547. BCMA_CC_FLASHDATA_ST_WEL
9548. BCMA_CC_FLASHDATA_ST_WIP
9549. BCMA_CC_FLASHT_ATSER
9550. BCMA_CC_FLASHT_NAND
9551. BCMA_CC_FLASHT_NONE
9552. BCMA_CC_FLASHT_PARA
9553. BCMA_CC_FLASHT_STSER
9554. BCMA_CC_FLASH_CFG
9555. BCMA_CC_FLASH_CFG_DS
9556. BCMA_CC_FLASH_WAITCNT
9557. BCMA_CC_FREFSELDELAY
9558. BCMA_CC_GPIOCTL
9559. BCMA_CC_GPIOIN
9560. BCMA_CC_GPIOIRQ
9561. BCMA_CC_GPIOOUT
9562. BCMA_CC_GPIOOUTEN
9563. BCMA_CC_GPIOPOL
9564. BCMA_CC_GPIOPULLDOWN
9565. BCMA_CC_GPIOPULLUP
9566. BCMA_CC_GPIOTIMER
9567. BCMA_CC_GPIOTIMER_OFFTIME
9568. BCMA_CC_GPIOTIMER_OFFTIME_SHIFT
9569. BCMA_CC_GPIOTIMER_ONTIME
9570. BCMA_CC_GPIOTIMER_ONTIME_SHIFT
9571. BCMA_CC_GPIOTOUTM
9572. BCMA_CC_HW_WORKAROUND
9573. BCMA_CC_ID
9574. BCMA_CC_IDE_ATTRWAIT
9575. BCMA_CC_IDE_CFG
9576. BCMA_CC_IDE_IOWAIT
9577. BCMA_CC_IDE_MEMWAIT
9578. BCMA_CC_ID_ID
9579. BCMA_CC_ID_ID_SHIFT
9580. BCMA_CC_ID_NRCORES
9581. BCMA_CC_ID_NRCORES_SHIFT
9582. BCMA_CC_ID_PKG
9583. BCMA_CC_ID_PKG_SHIFT
9584. BCMA_CC_ID_REV
9585. BCMA_CC_ID_REV_SHIFT
9586. BCMA_CC_ID_TYPE
9587. BCMA_CC_ID_TYPE_SHIFT
9588. BCMA_CC_IRQMASK
9589. BCMA_CC_IRQSTAT
9590. BCMA_CC_IRQ_EXT
9591. BCMA_CC_IRQ_GPIO
9592. BCMA_CC_IRQ_WDRESET
9593. BCMA_CC_JCMD
9594. BCMA_CC_JCMD0_ACC_DR
9595. BCMA_CC_JCMD0_ACC_IR
9596. BCMA_CC_JCMD0_ACC_IRDR
9597. BCMA_CC_JCMD0_ACC_IRPDR
9598. BCMA_CC_JCMD0_ACC_MASK
9599. BCMA_CC_JCMD0_ACC_PDR
9600. BCMA_CC_JCMD0_ACC_RESET
9601. BCMA_CC_JCMD0_IRW_MASK
9602. BCMA_CC_JCMD_ACC_DR
9603. BCMA_CC_JCMD_ACC_IR
9604. BCMA_CC_JCMD_ACC_IRDR
9605. BCMA_CC_JCMD_ACC_IRPDR
9606. BCMA_CC_JCMD_ACC_MASK
9607. BCMA_CC_JCMD_ACC_PDR
9608. BCMA_CC_JCMD_ACC_RESET
9609. BCMA_CC_JCMD_BUSY
9610. BCMA_CC_JCMD_DRW_MASK
9611. BCMA_CC_JCMD_IRW_MASK
9612. BCMA_CC_JCMD_IRW_SHIFT
9613. BCMA_CC_JCMD_PAUSE
9614. BCMA_CC_JCMD_START
9615. BCMA_CC_JCTL
9616. BCMA_CC_JCTL_EN
9617. BCMA_CC_JCTL_EXT_EN
9618. BCMA_CC_JCTL_FORCE_CLK
9619. BCMA_CC_JDR
9620. BCMA_CC_JIR
9621. BCMA_CC_NAND_ACC_CONTROL
9622. BCMA_CC_NAND_ACC_CONTROL_CS1
9623. BCMA_CC_NAND_BLK_WR_PROTECT
9624. BCMA_CC_NAND_BLOCK_ERASE_ADDR
9625. BCMA_CC_NAND_BLOCK_ERASE_ADDR_X
9626. BCMA_CC_NAND_BLOCK_LOCK_STATUS
9627. BCMA_CC_NAND_CACHE_ADDR
9628. BCMA_CC_NAND_CACHE_DATA
9629. BCMA_CC_NAND_CMD_ADDR
9630. BCMA_CC_NAND_CMD_ADDR_X
9631. BCMA_CC_NAND_CMD_END_ADDR
9632. BCMA_CC_NAND_CMD_START
9633. BCMA_CC_NAND_CONFIG
9634. BCMA_CC_NAND_CONFIG_CS1
9635. BCMA_CC_NAND_COPY_BACK_ADDR
9636. BCMA_CC_NAND_COPY_BACK_ADDR_X
9637. BCMA_CC_NAND_CORR_STAT_THRESHOLD
9638. BCMA_CC_NAND_CS_NAND_SELECT
9639. BCMA_CC_NAND_CS_NAND_XOR
9640. BCMA_CC_NAND_CTRL_CONFIG
9641. BCMA_CC_NAND_CTRL_STATUS
9642. BCMA_CC_NAND_DEVID
9643. BCMA_CC_NAND_DEVID_X
9644. BCMA_CC_NAND_ECC_CORR_ADDR
9645. BCMA_CC_NAND_ECC_CORR_ADDR_X
9646. BCMA_CC_NAND_ECC_UNC_ADDR
9647. BCMA_CC_NAND_ECC_UNC_ADDR_X
9648. BCMA_CC_NAND_INTFC_STATUS
9649. BCMA_CC_NAND_INV_READ_ADDR
9650. BCMA_CC_NAND_INV_READ_ADDR_X
9651. BCMA_CC_NAND_PAGE_PROGRAM_ADDR
9652. BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X
9653. BCMA_CC_NAND_READ_ADDR
9654. BCMA_CC_NAND_READ_ADDR_X
9655. BCMA_CC_NAND_READ_ERROR_COUNT
9656. BCMA_CC_NAND_REVISION
9657. BCMA_CC_NAND_SEMAPHORE
9658. BCMA_CC_NAND_SPARE_RD0
9659. BCMA_CC_NAND_SPARE_RD12
9660. BCMA_CC_NAND_SPARE_RD16
9661. BCMA_CC_NAND_SPARE_RD20
9662. BCMA_CC_NAND_SPARE_RD24
9663. BCMA_CC_NAND_SPARE_RD28
9664. BCMA_CC_NAND_SPARE_RD4
9665. BCMA_CC_NAND_SPARE_RD8
9666. BCMA_CC_NAND_SPARE_WR0
9667. BCMA_CC_NAND_SPARE_WR12
9668. BCMA_CC_NAND_SPARE_WR4
9669. BCMA_CC_NAND_SPARE_WR8
9670. BCMA_CC_NAND_TIMING_1
9671. BCMA_CC_NAND_TIMING_1_CS1
9672. BCMA_CC_NAND_TIMING_2
9673. BCMA_CC_NAND_TIMING_2_CS1
9674. BCMA_CC_NFLASH_COL_ADDR
9675. BCMA_CC_NFLASH_CONF
9676. BCMA_CC_NFLASH_CTL
9677. BCMA_CC_NFLASH_CTL_ERR
9678. BCMA_CC_NFLASH_DATA
9679. BCMA_CC_NFLASH_ROW_ADDR
9680. BCMA_CC_NFLASH_WAITCNT0
9681. BCMA_CC_OTPC
9682. BCMA_CC_OTPC_MAXFAIL
9683. BCMA_CC_OTPC_PROGWAIT
9684. BCMA_CC_OTPC_PRW_SHIFT
9685. BCMA_CC_OTPC_RECWAIT
9686. BCMA_CC_OTPC_SELVL
9687. BCMA_CC_OTPC_VSEL
9688. BCMA_CC_OTPL
9689. BCMA_CC_OTPL_GURGN_OFFSET
9690. BCMA_CC_OTPP
9691. BCMA_CC_OTPP_BUSY
9692. BCMA_CC_OTPP_COL
9693. BCMA_CC_OTPP_READ
9694. BCMA_CC_OTPP_READERR
9695. BCMA_CC_OTPP_ROW
9696. BCMA_CC_OTPP_ROW_SHIFT
9697. BCMA_CC_OTPP_START
9698. BCMA_CC_OTPP_VALUE
9699. BCMA_CC_OTPS
9700. BCMA_CC_OTPS_CID_PROTECT
9701. BCMA_CC_OTPS_GU_PROG_HW
9702. BCMA_CC_OTPS_GU_PROG_IND
9703. BCMA_CC_OTPS_GU_PROG_IND_SHIFT
9704. BCMA_CC_OTPS_HW_PROTECT
9705. BCMA_CC_OTPS_PROGFAIL
9706. BCMA_CC_OTPS_PROTECT
9707. BCMA_CC_OTPS_SW_PROTECT
9708. BCMA_CC_PCMCIA_ATTRWAIT
9709. BCMA_CC_PCMCIA_CFG
9710. BCMA_CC_PCMCIA_IOWAIT
9711. BCMA_CC_PCMCIA_MEMWAIT
9712. BCMA_CC_PLLONDELAY
9713. BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK
9714. BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT
9715. BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK
9716. BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT
9717. BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK
9718. BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT
9719. BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK
9720. BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT
9721. BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK
9722. BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT
9723. BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK
9724. BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT
9725. BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK
9726. BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT
9727. BCMA_CC_PMU15_PLL_PLLCTL0
9728. BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK
9729. BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT
9730. BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK
9731. BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT
9732. BCMA_CC_PMU4706_MAINPLL_PLL0
9733. BCMA_CC_PMU4716_MAINPLL_PLL0
9734. BCMA_CC_PMU5356_MAINPLL_PLL0
9735. BCMA_CC_PMU5357_MAINPLL_PLL0
9736. BCMA_CC_PMU5_MAINPLL_CPU
9737. BCMA_CC_PMU5_MAINPLL_MEM
9738. BCMA_CC_PMU5_MAINPLL_SSB
9739. BCMA_CC_PMU6_4706_PROCPLL_OFF
9740. BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK
9741. BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT
9742. BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK
9743. BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT
9744. BCMA_CC_PMU6_4706_PROC_P1DIV_MASK
9745. BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT
9746. BCMA_CC_PMU6_4706_PROC_P2DIV_MASK
9747. BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT
9748. BCMA_CC_PMU_ALP_CLOCK
9749. BCMA_CC_PMU_CAP
9750. BCMA_CC_PMU_CAP_REVISION
9751. BCMA_CC_PMU_CHIPCTL_ADDR
9752. BCMA_CC_PMU_CHIPCTL_DATA
9753. BCMA_CC_PMU_CLKSTRETCH
9754. BCMA_CC_PMU_CTL
9755. BCMA_CC_PMU_CTL_ALPREQEN
9756. BCMA_CC_PMU_CTL_HTREQEN
9757. BCMA_CC_PMU_CTL_ILPDIVEN
9758. BCMA_CC_PMU_CTL_ILP_DIV
9759. BCMA_CC_PMU_CTL_ILP_DIV_SHIFT
9760. BCMA_CC_PMU_CTL_LPOSEL
9761. BCMA_CC_PMU_CTL_NOILPONW
9762. BCMA_CC_PMU_CTL_PLL_UPD
9763. BCMA_CC_PMU_CTL_RES
9764. BCMA_CC_PMU_CTL_RES_RELOAD
9765. BCMA_CC_PMU_CTL_RES_SHIFT
9766. BCMA_CC_PMU_CTL_XTALFREQ
9767. BCMA_CC_PMU_CTL_XTALFREQ_SHIFT
9768. BCMA_CC_PMU_HT_CLOCK
9769. BCMA_CC_PMU_MAXRES_MSK
9770. BCMA_CC_PMU_MINRES_MSK
9771. BCMA_CC_PMU_PLLCTL_ADDR
9772. BCMA_CC_PMU_PLLCTL_DATA
9773. BCMA_CC_PMU_PLL_CTL0
9774. BCMA_CC_PMU_PLL_CTL1
9775. BCMA_CC_PMU_PLL_CTL2
9776. BCMA_CC_PMU_PLL_CTL3
9777. BCMA_CC_PMU_PLL_CTL4
9778. BCMA_CC_PMU_PLL_CTL5
9779. BCMA_CC_PMU_REGCTL_ADDR
9780. BCMA_CC_PMU_REGCTL_DATA
9781. BCMA_CC_PMU_RES_DEPMSK
9782. BCMA_CC_PMU_RES_PEND
9783. BCMA_CC_PMU_RES_REQM
9784. BCMA_CC_PMU_RES_REQT
9785. BCMA_CC_PMU_RES_REQTS
9786. BCMA_CC_PMU_RES_STAT
9787. BCMA_CC_PMU_RES_TABSEL
9788. BCMA_CC_PMU_RES_TIMER
9789. BCMA_CC_PMU_RES_UPDNTM
9790. BCMA_CC_PMU_STAT
9791. BCMA_CC_PMU_STAT_EXT_LPO_AVAIL
9792. BCMA_CC_PMU_STAT_HAVEALP
9793. BCMA_CC_PMU_STAT_HAVEHT
9794. BCMA_CC_PMU_STAT_INTPEND
9795. BCMA_CC_PMU_STAT_RESINIT
9796. BCMA_CC_PMU_STAT_SBCLKST
9797. BCMA_CC_PMU_STAT_WDRESET
9798. BCMA_CC_PMU_STRAPOPT
9799. BCMA_CC_PMU_TIMER
9800. BCMA_CC_PMU_WATCHDOG
9801. BCMA_CC_PMU_XTAL_FREQ
9802. BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK
9803. BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK
9804. BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT
9805. BCMA_CC_PPL_ABRAT_MASK
9806. BCMA_CC_PPL_ABRAT_SHIFT
9807. BCMA_CC_PPL_FDIV_MASK
9808. BCMA_CC_PPL_FMAB_OFF
9809. BCMA_CC_PPL_M14_OFF
9810. BCMA_CC_PPL_MDIV_MASK
9811. BCMA_CC_PPL_MDIV_WIDTH
9812. BCMA_CC_PPL_MRAT_MASK
9813. BCMA_CC_PPL_MRAT_SHIFT
9814. BCMA_CC_PPL_NDIV_MASK
9815. BCMA_CC_PPL_NDIV_SHIFT
9816. BCMA_CC_PPL_NM5_OFF
9817. BCMA_CC_PPL_P1P2_OFF
9818. BCMA_CC_PPL_P1_MASK
9819. BCMA_CC_PPL_P1_SHIFT
9820. BCMA_CC_PPL_P2_MASK
9821. BCMA_CC_PPL_P2_SHIFT
9822. BCMA_CC_PPL_PCHI_MASK
9823. BCMA_CC_PPL_PCHI_OFF
9824. BCMA_CC_PPL_PLLCTL_OFF
9825. BCMA_CC_PROG_CFG
9826. BCMA_CC_PROG_WAITCNT
9827. BCMA_CC_SLOECLKCTL_SRC_PCI
9828. BCMA_CC_SLOWCLKCTL
9829. BCMA_CC_SLOWCLKCTL_CLKDIV
9830. BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT
9831. BCMA_CC_SLOWCLKCTL_ENXTAL
9832. BCMA_CC_SLOWCLKCTL_FSLOW
9833. BCMA_CC_SLOWCLKCTL_IPLL
9834. BCMA_CC_SLOWCLKCTL_LPOFREQ
9835. BCMA_CC_SLOWCLKCTL_LPOPD
9836. BCMA_CC_SLOWCLKCTL_SRC
9837. BCMA_CC_SLOWCLKCTL_SRC_LPO
9838. BCMA_CC_SLOWCLKCTL_SRC_XTAL
9839. BCMA_CC_SLOWCLKCTL_XTALPU
9840. BCMA_CC_SPROM
9841. BCMA_CC_SROM_CONTROL
9842. BCMA_CC_SROM_CONTROL_BUSY
9843. BCMA_CC_SROM_CONTROL_LOCK
9844. BCMA_CC_SROM_CONTROL_OPCODE
9845. BCMA_CC_SROM_CONTROL_OP_READ
9846. BCMA_CC_SROM_CONTROL_OP_WRDIS
9847. BCMA_CC_SROM_CONTROL_OP_WREN
9848. BCMA_CC_SROM_CONTROL_OP_WRITE
9849. BCMA_CC_SROM_CONTROL_OTPSEL
9850. BCMA_CC_SROM_CONTROL_PRESENT
9851. BCMA_CC_SROM_CONTROL_SIZE_16K
9852. BCMA_CC_SROM_CONTROL_SIZE_1K
9853. BCMA_CC_SROM_CONTROL_SIZE_4K
9854. BCMA_CC_SROM_CONTROL_SIZE_MASK
9855. BCMA_CC_SROM_CONTROL_SIZE_SHIFT
9856. BCMA_CC_SROM_CONTROL_START
9857. BCMA_CC_SYSCLKCTL
9858. BCMA_CC_SYSCLKCTL_ALPEN
9859. BCMA_CC_SYSCLKCTL_CLKDIV
9860. BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT
9861. BCMA_CC_SYSCLKCTL_FORCEALP
9862. BCMA_CC_SYSCLKCTL_FORCEHT
9863. BCMA_CC_SYSCLKCTL_IDLPEN
9864. BCMA_CC_SYSCLKCTL_PLLEN
9865. BCMA_CC_UART0_DATA
9866. BCMA_CC_UART0_FCR
9867. BCMA_CC_UART0_IMR
9868. BCMA_CC_UART0_LCR
9869. BCMA_CC_UART0_LSR
9870. BCMA_CC_UART0_MCR
9871. BCMA_CC_UART0_MSR
9872. BCMA_CC_UART0_SCRATCH
9873. BCMA_CC_UART1_DATA
9874. BCMA_CC_UART1_FCR
9875. BCMA_CC_UART1_IMR
9876. BCMA_CC_UART1_LCR
9877. BCMA_CC_UART1_LSR
9878. BCMA_CC_UART1_MCR
9879. BCMA_CC_UART1_MSR
9880. BCMA_CC_UART1_SCRATCH
9881. BCMA_CC_WATCHDOG
9882. BCMA_CHIPCTL_4331_BT_COEXIST
9883. BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4
9884. BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5
9885. BCMA_CHIPCTL_4331_EXTPA_EN
9886. BCMA_CHIPCTL_4331_EXTPA_EN2
9887. BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5
9888. BCMA_CHIPCTL_4331_EXT_LNA
9889. BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS
9890. BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN
9891. BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN
9892. BCMA_CHIPCTL_4331_PCIE_AUXCLKEN
9893. BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS
9894. BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN
9895. BCMA_CHIPCTL_4331_SECI
9896. BCMA_CHIPCTL_4331_SPROM_GPIO13_15
9897. BCMA_CHIPCTL_5357_ANT_MUX_2O3
9898. BCMA_CHIPCTL_5357_EXTPA
9899. BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE
9900. BCMA_CHIPCTL_5357_I2S_PINS_ENABLE
9901. BCMA_CHIPCTL_5357_NFLASH
9902. BCMA_CHIP_ID_BCM4313
9903. BCMA_CHIP_ID_BCM43131
9904. BCMA_CHIP_ID_BCM43142
9905. BCMA_CHIP_ID_BCM43217
9906. BCMA_CHIP_ID_BCM43222
9907. BCMA_CHIP_ID_BCM43224
9908. BCMA_CHIP_ID_BCM43225
9909. BCMA_CHIP_ID_BCM43227
9910. BCMA_CHIP_ID_BCM43228
9911. BCMA_CHIP_ID_BCM4331
9912. BCMA_CHIP_ID_BCM43421
9913. BCMA_CHIP_ID_BCM43428
9914. BCMA_CHIP_ID_BCM43431
9915. BCMA_CHIP_ID_BCM43460
9916. BCMA_CHIP_ID_BCM4352
9917. BCMA_CHIP_ID_BCM4360
9918. BCMA_CHIP_ID_BCM4706
9919. BCMA_CHIP_ID_BCM4707
9920. BCMA_CHIP_ID_BCM47094
9921. BCMA_CHIP_ID_BCM4716
9922. BCMA_CHIP_ID_BCM47162
9923. BCMA_CHIP_ID_BCM4748
9924. BCMA_CHIP_ID_BCM4749
9925. BCMA_CHIP_ID_BCM53018
9926. BCMA_CHIP_ID_BCM5356
9927. BCMA_CHIP_ID_BCM5357
9928. BCMA_CHIP_ID_BCM53572
9929. BCMA_CHIP_ID_BCM53573
9930. BCMA_CHIP_ID_BCM6362
9931. BCMA_CLKCTLST
9932. BCMA_CLKCTLST_4328A0_HAVEALP
9933. BCMA_CLKCTLST_4328A0_HAVEHT
9934. BCMA_CLKCTLST_BP_ON_ALP
9935. BCMA_CLKCTLST_BP_ON_HT
9936. BCMA_CLKCTLST_EXTRESREQ
9937. BCMA_CLKCTLST_EXTRESREQ_SHIFT
9938. BCMA_CLKCTLST_EXTRESST
9939. BCMA_CLKCTLST_EXTRESST_SHIFT
9940. BCMA_CLKCTLST_FORCEALP
9941. BCMA_CLKCTLST_FORCEHT
9942. BCMA_CLKCTLST_FORCEILP
9943. BCMA_CLKCTLST_HAVEALP
9944. BCMA_CLKCTLST_HAVEALPREQ
9945. BCMA_CLKCTLST_HAVEHT
9946. BCMA_CLKCTLST_HAVEHTREQ
9947. BCMA_CLKCTLST_HQCLKREQ
9948. BCMA_CLKCTLST_HWCROFF
9949. BCMA_CLKMODE_DYNAMIC
9950. BCMA_CLKMODE_FAST
9951. BCMA_CL_CORESIGHT
9952. BCMA_CL_EROM
9953. BCMA_CL_GEN
9954. BCMA_CL_OPTIMO
9955. BCMA_CL_PRIMECELL
9956. BCMA_CL_SIM
9957. BCMA_CL_VERIF
9958. BCMA_CORE
9959. BCMA_CORE_4706_CHIPCOMMON
9960. BCMA_CORE_4706_MAC_GBIT
9961. BCMA_CORE_4706_MAC_GBIT_COMMON
9962. BCMA_CORE_4706_SOC_RAM
9963. BCMA_CORE_80211
9964. BCMA_CORE_ADSL
9965. BCMA_CORE_ALTA
9966. BCMA_CORE_AMEMC
9967. BCMA_CORE_ARMCA9
9968. BCMA_CORE_ARM_1176
9969. BCMA_CORE_ARM_7TDMI
9970. BCMA_CORE_ARM_CA7
9971. BCMA_CORE_ARM_CM3
9972. BCMA_CORE_ARM_CR4
9973. BCMA_CORE_CHIPCOMMON
9974. BCMA_CORE_CMEM
9975. BCMA_CORE_DDR12_MEM_CTL
9976. BCMA_CORE_DDR23_PHY
9977. BCMA_CORE_DEFAULT
9978. BCMA_CORE_ETHERNET
9979. BCMA_CORE_ETHERNET_GBIT
9980. BCMA_CORE_EXTIF
9981. BCMA_CORE_GCI
9982. BCMA_CORE_I2S
9983. BCMA_CORE_ILINE100
9984. BCMA_CORE_ILINE20
9985. BCMA_CORE_INTERNAL_MEM
9986. BCMA_CORE_INVALID
9987. BCMA_CORE_IPSEC
9988. BCMA_CORE_MAC_GBIT
9989. BCMA_CORE_MEMC_SDRAM
9990. BCMA_CORE_MINI_MACPHY
9991. BCMA_CORE_MIPS
9992. BCMA_CORE_MIPS_3302
9993. BCMA_CORE_MIPS_74K
9994. BCMA_CORE_NS_A9JTAG
9995. BCMA_CORE_NS_CHIPCOMMON_B
9996. BCMA_CORE_NS_DDR23
9997. BCMA_CORE_NS_DMA
9998. BCMA_CORE_NS_NAND
9999. BCMA_CORE_NS_PCIEG2
10000. BCMA_CORE_NS_QSPI
10001. BCMA_CORE_NS_ROM
10002. BCMA_CORE_NS_SDIO3
10003. BCMA_CORE_NS_USB20
10004. BCMA_CORE_NS_USB30
10005. BCMA_CORE_OCP_AHB_BRIDGE
10006. BCMA_CORE_OCP_OCP_BRIDGE
10007. BCMA_CORE_OFDM
10008. BCMA_CORE_OOB_ROUTER
10009. BCMA_CORE_PARA_ATA
10010. BCMA_CORE_PCI
10011. BCMA_CORE_PCIE
10012. BCMA_CORE_PCIE2
10013. BCMA_CORE_PCIE2_CFG_ADDR
10014. BCMA_CORE_PCIE2_CFG_DATA
10015. BCMA_CORE_PCIE2_CLK_CONTROL
10016. BCMA_CORE_PCIE2_CONFIGINDADDR
10017. BCMA_CORE_PCIE2_CONFIGINDDATA
10018. BCMA_CORE_PCIE2_D2H_INTMASK_0
10019. BCMA_CORE_PCIE2_D2H_INTRLAZY_0
10020. BCMA_CORE_PCIE2_D2H_INTSTAT_0
10021. BCMA_CORE_PCIE2_DATAINTF
10022. BCMA_CORE_PCIE2_EP_AXI_CONFIG
10023. BCMA_CORE_PCIE2_EP_LTR_CONTROL
10024. BCMA_CORE_PCIE2_EP_LTR_STATUS
10025. BCMA_CORE_PCIE2_EP_OBFF_STATUS
10026. BCMA_CORE_PCIE2_EP_PM_CONTROL
10027. BCMA_CORE_PCIE2_EP_PM_STATUS
10028. BCMA_CORE_PCIE2_FUNC0_IMAP0_0
10029. BCMA_CORE_PCIE2_FUNC0_IMAP0_1
10030. BCMA_CORE_PCIE2_FUNC0_IMAP0_2
10031. BCMA_CORE_PCIE2_FUNC0_IMAP0_3
10032. BCMA_CORE_PCIE2_FUNC0_IMAP0_4
10033. BCMA_CORE_PCIE2_FUNC0_IMAP0_5
10034. BCMA_CORE_PCIE2_FUNC0_IMAP0_6
10035. BCMA_CORE_PCIE2_FUNC0_IMAP0_7
10036. BCMA_CORE_PCIE2_FUNC0_IMAP1
10037. BCMA_CORE_PCIE2_FUNC0_IMAP2
10038. BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE
10039. BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE
10040. BCMA_CORE_PCIE2_FUNC1_IMAP0_0
10041. BCMA_CORE_PCIE2_FUNC1_IMAP0_1
10042. BCMA_CORE_PCIE2_FUNC1_IMAP0_2
10043. BCMA_CORE_PCIE2_FUNC1_IMAP0_3
10044. BCMA_CORE_PCIE2_FUNC1_IMAP0_4
10045. BCMA_CORE_PCIE2_FUNC1_IMAP0_5
10046. BCMA_CORE_PCIE2_FUNC1_IMAP0_6
10047. BCMA_CORE_PCIE2_FUNC1_IMAP0_7
10048. BCMA_CORE_PCIE2_FUNC1_IMAP1
10049. BCMA_CORE_PCIE2_FUNC1_IMAP2
10050. BCMA_CORE_PCIE2_H2D_INTMASK_0
10051. BCMA_CORE_PCIE2_H2D_INTRLAZY_0
10052. BCMA_CORE_PCIE2_H2D_INTSTAT_0
10053. BCMA_CORE_PCIE2_IARR0_LOWER
10054. BCMA_CORE_PCIE2_IARR0_UPPER
10055. BCMA_CORE_PCIE2_IARR1_LOWER
10056. BCMA_CORE_PCIE2_IARR1_UPPER
10057. BCMA_CORE_PCIE2_IARR2_LOWER
10058. BCMA_CORE_PCIE2_IARR2_UPPER
10059. BCMA_CORE_PCIE2_INTR_CLEAR
10060. BCMA_CORE_PCIE2_INTR_EN
10061. BCMA_CORE_PCIE2_INTR_STATUS
10062. BCMA_CORE_PCIE2_LINK_STATUS
10063. BCMA_CORE_PCIE2_LTR_STATE
10064. BCMA_CORE_PCIE2_MDIOCONTROL
10065. BCMA_CORE_PCIE2_MDIORDDATA
10066. BCMA_CORE_PCIE2_MDIOWRDATA
10067. BCMA_CORE_PCIE2_MEM_CONTROL
10068. BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0
10069. BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1
10070. BCMA_CORE_PCIE2_MISC_CONFIG
10071. BCMA_CORE_PCIE2_MISC_INTR_EN
10072. BCMA_CORE_PCIE2_MISC_STATUS
10073. BCMA_CORE_PCIE2_OARR0
10074. BCMA_CORE_PCIE2_OARR1
10075. BCMA_CORE_PCIE2_OARR2
10076. BCMA_CORE_PCIE2_OMAP0_LOWER
10077. BCMA_CORE_PCIE2_OMAP0_UPPER
10078. BCMA_CORE_PCIE2_OMAP1_LOWER
10079. BCMA_CORE_PCIE2_OMAP1_UPPER
10080. BCMA_CORE_PCIE2_OMAP2_LOWER
10081. BCMA_CORE_PCIE2_OMAP2_UPPER
10082. BCMA_CORE_PCIE2_PCIE_ERR_STATUS
10083. BCMA_CORE_PCIE2_PWR_INT_MASK
10084. BCMA_CORE_PCIE2_PWR_INT_STATUS
10085. BCMA_CORE_PCIE2_RC_AXI_CONFIG
10086. BCMA_CORE_PCIE2_RC_PM_CONTROL
10087. BCMA_CORE_PCIE2_RC_PM_STATUS
10088. BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN
10089. BCMA_CORE_PCIE2_RESET_STATUS
10090. BCMA_CORE_PCIE2_RXDEBUG_CONTROL0
10091. BCMA_CORE_PCIE2_RXDEBUG_STATUS0
10092. BCMA_CORE_PCIE2_SPROM
10093. BCMA_CORE_PCIE2_STRAP_STATUS
10094. BCMA_CORE_PCIE2_SYS_EP_INT_CSR0
10095. BCMA_CORE_PCIE2_SYS_EP_INT_CSR1
10096. BCMA_CORE_PCIE2_SYS_EP_INT_EN0
10097. BCMA_CORE_PCIE2_SYS_EP_INT_EN1
10098. BCMA_CORE_PCIE2_SYS_EQ_HEAD0
10099. BCMA_CORE_PCIE2_SYS_EQ_HEAD1
10100. BCMA_CORE_PCIE2_SYS_EQ_HEAD2
10101. BCMA_CORE_PCIE2_SYS_EQ_HEAD3
10102. BCMA_CORE_PCIE2_SYS_EQ_HEAD4
10103. BCMA_CORE_PCIE2_SYS_EQ_HEAD5
10104. BCMA_CORE_PCIE2_SYS_EQ_PAGE
10105. BCMA_CORE_PCIE2_SYS_EQ_TAIL0
10106. BCMA_CORE_PCIE2_SYS_EQ_TAIL1
10107. BCMA_CORE_PCIE2_SYS_EQ_TAIL2
10108. BCMA_CORE_PCIE2_SYS_EQ_TAIL3
10109. BCMA_CORE_PCIE2_SYS_EQ_TAIL4
10110. BCMA_CORE_PCIE2_SYS_EQ_TAIL5
10111. BCMA_CORE_PCIE2_SYS_HOST_INTR0
10112. BCMA_CORE_PCIE2_SYS_HOST_INTR1
10113. BCMA_CORE_PCIE2_SYS_HOST_INTR2
10114. BCMA_CORE_PCIE2_SYS_HOST_INTR3
10115. BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR
10116. BCMA_CORE_PCIE2_SYS_HOST_INTR_EN
10117. BCMA_CORE_PCIE2_SYS_MSI_CTRL0
10118. BCMA_CORE_PCIE2_SYS_MSI_CTRL1
10119. BCMA_CORE_PCIE2_SYS_MSI_CTRL2
10120. BCMA_CORE_PCIE2_SYS_MSI_CTRL3
10121. BCMA_CORE_PCIE2_SYS_MSI_CTRL4
10122. BCMA_CORE_PCIE2_SYS_MSI_CTRL5
10123. BCMA_CORE_PCIE2_SYS_MSI_INTREN
10124. BCMA_CORE_PCIE2_SYS_MSI_PAGE
10125. BCMA_CORE_PCIE2_SYS_MSI_REQ
10126. BCMA_CORE_PCIE2_SYS_RC_INTX_CSR
10127. BCMA_CORE_PCIE2_SYS_RC_INTX_EN
10128. BCMA_CORE_PCIE2_TX_DEBUG_CFG
10129. BCMA_CORE_PCIE_RC
10130. BCMA_CORE_PCI_
10131. BCMA_CORE_PCI_ARBCTL
10132. BCMA_CORE_PCI_ARBCTL_EXTERN
10133. BCMA_CORE_PCI_ARBCTL_INTERN
10134. BCMA_CORE_PCI_ARBCTL_PARKID
10135. BCMA_CORE_PCI_ARBCTL_PARKID_4710
10136. BCMA_CORE_PCI_ARBCTL_PARKID_EXT0
10137. BCMA_CORE_PCI_ARBCTL_PARKID_EXT1
10138. BCMA_CORE_PCI_ARBCTL_PARKID_LAST
10139. BCMA_CORE_PCI_ASPMTIMER_EXTEND
10140. BCMA_CORE_PCI_BCAST_ADDR
10141. BCMA_CORE_PCI_BCAST_ADDR_MASK
10142. BCMA_CORE_PCI_BCAST_DATA
10143. BCMA_CORE_PCI_BFL_NOPCI
10144. BCMA_CORE_PCI_CFG_BUS_MASK
10145. BCMA_CORE_PCI_CFG_BUS_SHIFT
10146. BCMA_CORE_PCI_CFG_DEVCTRL
10147. BCMA_CORE_PCI_CFG_FUN_MASK
10148. BCMA_CORE_PCI_CFG_FUN_SHIFT
10149. BCMA_CORE_PCI_CFG_OFF_MASK
10150. BCMA_CORE_PCI_CFG_OFF_SHIFT
10151. BCMA_CORE_PCI_CFG_SLOT_MASK
10152. BCMA_CORE_PCI_CFG_SLOT_SHIFT
10153. BCMA_CORE_PCI_CLKREQENCTRL
10154. BCMA_CORE_PCI_CONFIG_ADDR
10155. BCMA_CORE_PCI_CONFIG_DATA
10156. BCMA_CORE_PCI_CTL
10157. BCMA_CORE_PCI_CTL_CLK
10158. BCMA_CORE_PCI_CTL_CLK_OE
10159. BCMA_CORE_PCI_CTL_RST
10160. BCMA_CORE_PCI_CTL_RST_OE
10161. BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG
10162. BCMA_CORE_PCI_DLLP_ECTHRESHREG
10163. BCMA_CORE_PCI_DLLP_ERRCTRREG
10164. BCMA_CORE_PCI_DLLP_LACKTOREG
10165. BCMA_CORE_PCI_DLLP_LAMASKREG
10166. BCMA_CORE_PCI_DLLP_LAREG
10167. BCMA_CORE_PCI_DLLP_LCREG
10168. BCMA_CORE_PCI_DLLP_LRREG
10169. BCMA_CORE_PCI_DLLP_LSREG
10170. BCMA_CORE_PCI_DLLP_LSREG_LINKUP
10171. BCMA_CORE_PCI_DLLP_NAKRXCTRREG
10172. BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG
10173. BCMA_CORE_PCI_DLLP_PCIE11
10174. BCMA_CORE_PCI_DLLP_PKTBIST
10175. BCMA_CORE_PCI_DLLP_PMTHRESHREG
10176. BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG
10177. BCMA_CORE_PCI_DLLP_RTRRWREG
10178. BCMA_CORE_PCI_DLLP_RTRYPPREG
10179. BCMA_CORE_PCI_DLLP_RTRYRPREG
10180. BCMA_CORE_PCI_DLLP_RTRYWPREG
10181. BCMA_CORE_PCI_DLLP_RXSEQNUMREG
10182. BCMA_CORE_PCI_DLLP_TESTREG
10183. BCMA_CORE_PCI_DLLP_TLPERRCTRREG
10184. BCMA_CORE_PCI_GPIO_CTL
10185. BCMA_CORE_PCI_GPIO_ENABLE
10186. BCMA_CORE_PCI_GPIO_IN
10187. BCMA_CORE_PCI_GPIO_OUT
10188. BCMA_CORE_PCI_IMASK
10189. BCMA_CORE_PCI_IMASK_INTA
10190. BCMA_CORE_PCI_IMASK_INTB
10191. BCMA_CORE_PCI_IMASK_PERR
10192. BCMA_CORE_PCI_IMASK_PME
10193. BCMA_CORE_PCI_IMASK_SERR
10194. BCMA_CORE_PCI_ISTAT
10195. BCMA_CORE_PCI_ISTAT_INTA
10196. BCMA_CORE_PCI_ISTAT_INTB
10197. BCMA_CORE_PCI_ISTAT_PERR
10198. BCMA_CORE_PCI_ISTAT_PME
10199. BCMA_CORE_PCI_ISTAT_SERR
10200. BCMA_CORE_PCI_MBOX
10201. BCMA_CORE_PCI_MBOX_F0_0
10202. BCMA_CORE_PCI_MBOX_F0_1
10203. BCMA_CORE_PCI_MBOX_F1_0
10204. BCMA_CORE_PCI_MBOX_F1_1
10205. BCMA_CORE_PCI_MBOX_F2_0
10206. BCMA_CORE_PCI_MBOX_F2_1
10207. BCMA_CORE_PCI_MBOX_F3_0
10208. BCMA_CORE_PCI_MBOX_F3_1
10209. BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE
10210. BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK
10211. BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL
10212. BCMA_CORE_PCI_MDIOCTL_PREAM_EN
10213. BCMA_CORE_PCI_MDIODATA_BLK_ADDR
10214. BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK
10215. BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD
10216. BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF
10217. BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD
10218. BCMA_CORE_PCI_MDIODATA_DEV_ADDR
10219. BCMA_CORE_PCI_MDIODATA_DEV_PLL
10220. BCMA_CORE_PCI_MDIODATA_DEV_RX
10221. BCMA_CORE_PCI_MDIODATA_DEV_TX
10222. BCMA_CORE_PCI_MDIODATA_MASK
10223. BCMA_CORE_PCI_MDIODATA_READ
10224. BCMA_CORE_PCI_MDIODATA_REGADDR_MASK
10225. BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD
10226. BCMA_CORE_PCI_MDIODATA_REGADDR_SHF
10227. BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD
10228. BCMA_CORE_PCI_MDIODATA_START
10229. BCMA_CORE_PCI_MDIODATA_TA
10230. BCMA_CORE_PCI_MDIODATA_WRITE
10231. BCMA_CORE_PCI_MDIO_BLK0
10232. BCMA_CORE_PCI_MDIO_BLK1
10233. BCMA_CORE_PCI_MDIO_BLK1_MGMT0
10234. BCMA_CORE_PCI_MDIO_BLK1_MGMT1
10235. BCMA_CORE_PCI_MDIO_BLK1_MGMT2
10236. BCMA_CORE_PCI_MDIO_BLK1_MGMT3
10237. BCMA_CORE_PCI_MDIO_BLK1_MGMT4
10238. BCMA_CORE_PCI_MDIO_BLK2
10239. BCMA_CORE_PCI_MDIO_BLK3
10240. BCMA_CORE_PCI_MDIO_BLK4
10241. BCMA_CORE_PCI_MDIO_CONTROL
10242. BCMA_CORE_PCI_MDIO_DATA
10243. BCMA_CORE_PCI_MDIO_IEEE0
10244. BCMA_CORE_PCI_MDIO_IEEE1
10245. BCMA_CORE_PCI_MDIO_RXCTRL0
10246. BCMA_CORE_PCI_MDIO_SERDESID
10247. BCMA_CORE_PCI_MDIO_TXCTRL0
10248. BCMA_CORE_PCI_MDIO_TXPLL
10249. BCMA_CORE_PCI_PCICFG0
10250. BCMA_CORE_PCI_PCICFG1
10251. BCMA_CORE_PCI_PCICFG2
10252. BCMA_CORE_PCI_PCICFG3
10253. BCMA_CORE_PCI_PCIEIND_ADDR
10254. BCMA_CORE_PCI_PCIEIND_DATA
10255. BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN
10256. BCMA_CORE_PCI_PLP_ATTNMASKREG
10257. BCMA_CORE_PCI_PLP_ATTNREG
10258. BCMA_CORE_PCI_PLP_LTLANENUMREG
10259. BCMA_CORE_PCI_PLP_LTLINKNUMREG
10260. BCMA_CORE_PCI_PLP_LTNFTSREG
10261. BCMA_CORE_PCI_PLP_LTSSMCTRLREG
10262. BCMA_CORE_PCI_PLP_LTSSMDIAGREG
10263. BCMA_CORE_PCI_PLP_MODEREG
10264. BCMA_CORE_PCI_PLP_POLARITYINV_STAT
10265. BCMA_CORE_PCI_PLP_RXERRCTR
10266. BCMA_CORE_PCI_PLP_RXERRTHRESHREG
10267. BCMA_CORE_PCI_PLP_RXFRMERRCTR
10268. BCMA_CORE_PCI_PLP_RXTXSMDIAGREG
10269. BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG
10270. BCMA_CORE_PCI_PLP_STATUSREG
10271. BCMA_CORE_PCI_PLP_TESTCTRLREG
10272. BCMA_CORE_PCI_PLP_TIMINGOVRDREG
10273. BCMA_CORE_PCI_RC_CRS_VISIBILITY
10274. BCMA_CORE_PCI_SBTOPCI0
10275. BCMA_CORE_PCI_SBTOPCI0_MASK
10276. BCMA_CORE_PCI_SBTOPCI1
10277. BCMA_CORE_PCI_SBTOPCI1_MASK
10278. BCMA_CORE_PCI_SBTOPCI2
10279. BCMA_CORE_PCI_SBTOPCI2_MASK
10280. BCMA_CORE_PCI_SBTOPCI_BURST
10281. BCMA_CORE_PCI_SBTOPCI_CFG0
10282. BCMA_CORE_PCI_SBTOPCI_CFG1
10283. BCMA_CORE_PCI_SBTOPCI_IO
10284. BCMA_CORE_PCI_SBTOPCI_MEM
10285. BCMA_CORE_PCI_SBTOPCI_MRM
10286. BCMA_CORE_PCI_SBTOPCI_PREF
10287. BCMA_CORE_PCI_SBTOPCI_RC
10288. BCMA_CORE_PCI_SBTOPCI_RC_READ
10289. BCMA_CORE_PCI_SBTOPCI_RC_READL
10290. BCMA_CORE_PCI_SBTOPCI_RC_READM
10291. BCMA_CORE_PCI_SERDES_PLL_CTRL
10292. BCMA_CORE_PCI_SERDES_RX_CDR
10293. BCMA_CORE_PCI_SERDES_RX_CDRBW
10294. BCMA_CORE_PCI_SERDES_RX_CTRL
10295. BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE
10296. BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY
10297. BCMA_CORE_PCI_SERDES_RX_TIMER1
10298. BCMA_CORE_PCI_SPROM
10299. BCMA_CORE_PCI_SPROM_CLKREQ_ENB
10300. BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5
10301. BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST
10302. BCMA_CORE_PCI_SPROM_MISC_CONFIG
10303. BCMA_CORE_PCI_SPROM_PI_MASK
10304. BCMA_CORE_PCI_SPROM_PI_OFFSET
10305. BCMA_CORE_PCI_SPROM_PI_SHIFT
10306. BCMA_CORE_PCMCIA
10307. BCMA_CORE_PHY_A
10308. BCMA_CORE_PHY_AC
10309. BCMA_CORE_PHY_B
10310. BCMA_CORE_PHY_G
10311. BCMA_CORE_PHY_HT
10312. BCMA_CORE_PHY_LP
10313. BCMA_CORE_PHY_N
10314. BCMA_CORE_PHY_SSN
10315. BCMA_CORE_PMU
10316. BCMA_CORE_ROBOSWITCH
10317. BCMA_CORE_SATA_XORDMA
10318. BCMA_CORE_SDIO_DEV
10319. BCMA_CORE_SDIO_HOST
10320. BCMA_CORE_SDRAM
10321. BCMA_CORE_SDR_DDR1_MEM_CTL
10322. BCMA_CORE_SHARED_COMMON
10323. BCMA_CORE_SHIM
10324. BCMA_CORE_SIZE
10325. BCMA_CORE_SPI_HOST
10326. BCMA_CORE_SRAM
10327. BCMA_CORE_SRAM_CTL
10328. BCMA_CORE_SYS_MEM
10329. BCMA_CORE_USB11_DEV
10330. BCMA_CORE_USB11_HOST
10331. BCMA_CORE_USB11_HOSTDEV
10332. BCMA_CORE_USB20_DEV
10333. BCMA_CORE_USB20_HOST
10334. BCMA_CORE_USB30_DEV
10335. BCMA_CORE_UTOPIA
10336. BCMA_CORE_V90
10337. BCMA_DMA_TRANSLATION_DMA32_CMT
10338. BCMA_DMA_TRANSLATION_DMA64_CMT
10339. BCMA_DMA_TRANSLATION_MASK
10340. BCMA_DMA_TRANSLATION_NONE
10341. BCMA_DMU_CRU_CLKSET_KEY
10342. BCMA_DMU_CRU_STRAPS_CTRL
10343. BCMA_DMU_CRU_STRAPS_CTRL_4BYTE
10344. BCMA_DMU_CRU_STRAPS_CTRL_USB3
10345. BCMA_DMU_CRU_USB2_CONTROL
10346. BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK
10347. BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_SHIFT
10348. BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK
10349. BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_SHIFT
10350. BCMA_GMAC_CMN_CFP_ACCESS
10351. BCMA_GMAC_CMN_CFP_ACTION_DATA
10352. BCMA_GMAC_CMN_CFP_TCAM_DATA0
10353. BCMA_GMAC_CMN_CFP_TCAM_DATA1
10354. BCMA_GMAC_CMN_CFP_TCAM_DATA2
10355. BCMA_GMAC_CMN_CFP_TCAM_DATA3
10356. BCMA_GMAC_CMN_CFP_TCAM_DATA4
10357. BCMA_GMAC_CMN_CFP_TCAM_DATA5
10358. BCMA_GMAC_CMN_CFP_TCAM_DATA6
10359. BCMA_GMAC_CMN_CFP_TCAM_DATA7
10360. BCMA_GMAC_CMN_CFP_TCAM_MASK0
10361. BCMA_GMAC_CMN_CFP_TCAM_MASK1
10362. BCMA_GMAC_CMN_CFP_TCAM_MASK2
10363. BCMA_GMAC_CMN_CFP_TCAM_MASK3
10364. BCMA_GMAC_CMN_CFP_TCAM_MASK4
10365. BCMA_GMAC_CMN_CFP_TCAM_MASK5
10366. BCMA_GMAC_CMN_CFP_TCAM_MASK6
10367. BCMA_GMAC_CMN_CFP_TCAM_MASK7
10368. BCMA_GMAC_CMN_GMAC0_RGMII_CTL
10369. BCMA_GMAC_CMN_MIB_MAX_LEN
10370. BCMA_GMAC_CMN_PARSER_CTL
10371. BCMA_GMAC_CMN_PA_ADDR_MASK
10372. BCMA_GMAC_CMN_PA_ADDR_SHIFT
10373. BCMA_GMAC_CMN_PA_DATA_MASK
10374. BCMA_GMAC_CMN_PA_REG_MASK
10375. BCMA_GMAC_CMN_PA_REG_SHIFT
10376. BCMA_GMAC_CMN_PA_START
10377. BCMA_GMAC_CMN_PA_WRITE
10378. BCMA_GMAC_CMN_PC_EPA_MASK
10379. BCMA_GMAC_CMN_PC_MCT_MASK
10380. BCMA_GMAC_CMN_PC_MCT_SHIFT
10381. BCMA_GMAC_CMN_PC_MTE
10382. BCMA_GMAC_CMN_PHY_ACCESS
10383. BCMA_GMAC_CMN_PHY_CTL
10384. BCMA_GMAC_CMN_STAG0
10385. BCMA_GMAC_CMN_STAG1
10386. BCMA_GMAC_CMN_STAG2
10387. BCMA_GMAC_CMN_STAG3
10388. BCMA_GMAC_CMN_TCAM_BIST_CTL
10389. BCMA_GMAC_CMN_TCAM_BIST_STATUS
10390. BCMA_GMAC_CMN_TCAM_CMP_STATUS
10391. BCMA_GMAC_CMN_TCAM_DISABLE
10392. BCMA_GMAC_CMN_TCAM_TEST_CTL
10393. BCMA_GMAC_CMN_UDF_0_A3_A0
10394. BCMA_GMAC_CMN_UDF_0_A7_A4
10395. BCMA_GMAC_CMN_UDF_0_A8
10396. BCMA_GMAC_CMN_UDF_0_B3_B0
10397. BCMA_GMAC_CMN_UDF_0_B7_B4
10398. BCMA_GMAC_CMN_UDF_0_B8
10399. BCMA_GMAC_CMN_UDF_0_C3_C0
10400. BCMA_GMAC_CMN_UDF_0_C7_C4
10401. BCMA_GMAC_CMN_UDF_0_C8
10402. BCMA_GMAC_CMN_UDF_0_D11_D8
10403. BCMA_GMAC_CMN_UDF_0_D3_D0
10404. BCMA_GMAC_CMN_UDF_0_D7_D4
10405. BCMA_GMAC_CMN_UDF_1_A3_A0
10406. BCMA_GMAC_CMN_UDF_1_A7_A4
10407. BCMA_GMAC_CMN_UDF_1_A8
10408. BCMA_GMAC_CMN_UDF_1_B3_B0
10409. BCMA_GMAC_CMN_UDF_1_B7_B4
10410. BCMA_GMAC_CMN_UDF_1_B8
10411. BCMA_GMAC_CMN_UDF_1_C3_C0
10412. BCMA_GMAC_CMN_UDF_1_C7_C4
10413. BCMA_GMAC_CMN_UDF_1_C8
10414. BCMA_GMAC_CMN_UDF_2_A3_A0
10415. BCMA_GMAC_CMN_UDF_2_A7_A4
10416. BCMA_GMAC_CMN_UDF_2_A8
10417. BCMA_GMAC_CMN_UDF_2_B3_B0
10418. BCMA_GMAC_CMN_UDF_2_B7_B4
10419. BCMA_GMAC_CMN_UDF_2_B8
10420. BCMA_GMAC_CMN_UDF_2_C3_C0
10421. BCMA_GMAC_CMN_UDF_2_C7_C4
10422. BCMA_GMAC_CMN_UDF_2_C8
10423. BCMA_GPIO_MAX_PINS
10424. BCMA_HOSTTYPE_PCI
10425. BCMA_HOSTTYPE_SDIO
10426. BCMA_HOSTTYPE_SOC
10427. BCMA_IOCTL
10428. BCMA_IOCTL_BIST_EN
10429. BCMA_IOCTL_CLK
10430. BCMA_IOCTL_CORE_BITS
10431. BCMA_IOCTL_FGC
10432. BCMA_IOCTL_PME_EN
10433. BCMA_IOST
10434. BCMA_IOST_BIST_DONE
10435. BCMA_IOST_BIST_ERROR
10436. BCMA_IOST_CORE_BITS
10437. BCMA_IOST_DMA64
10438. BCMA_IOST_GATED_CLK
10439. BCMA_MANUF_ARM
10440. BCMA_MANUF_BCM
10441. BCMA_MANUF_MIPS
10442. BCMA_MAX_NR_CORES
10443. BCMA_MIPS_IPSFLAG
10444. BCMA_MIPS_IPSFLAG_IRQ1
10445. BCMA_MIPS_IPSFLAG_IRQ1_SHIFT
10446. BCMA_MIPS_IPSFLAG_IRQ2
10447. BCMA_MIPS_IPSFLAG_IRQ2_SHIFT
10448. BCMA_MIPS_IPSFLAG_IRQ3
10449. BCMA_MIPS_IPSFLAG_IRQ3_SHIFT
10450. BCMA_MIPS_IPSFLAG_IRQ4
10451. BCMA_MIPS_IPSFLAG_IRQ4_SHIFT
10452. BCMA_MIPS_MIPS74K_BIST
10453. BCMA_MIPS_MIPS74K_CLKCTLST
10454. BCMA_MIPS_MIPS74K_CORECTL
10455. BCMA_MIPS_MIPS74K_EXCEPTBASE
10456. BCMA_MIPS_MIPS74K_GPIOEN
10457. BCMA_MIPS_MIPS74K_GPIOOUT
10458. BCMA_MIPS_MIPS74K_GPIOSEL
10459. BCMA_MIPS_MIPS74K_INTMASK
10460. BCMA_MIPS_MIPS74K_INTMASK_INT0
10461. BCMA_MIPS_MIPS74K_NMIMASK
10462. BCMA_MIPS_OOBSELINA74
10463. BCMA_MIPS_OOBSELOUTA30
10464. BCMA_NS_ROM_IOST_BOOT_DEV_MASK
10465. BCMA_NS_ROM_IOST_BOOT_DEV_NAND
10466. BCMA_NS_ROM_IOST_BOOT_DEV_NOR
10467. BCMA_NS_ROM_IOST_BOOT_DEV_ROM
10468. BCMA_OOB_SEL_OUT_A30
10469. BCMA_PCIE2_BAR0_WIN2
10470. BCMA_PCI_BACKPLANE_IRQS
10471. BCMA_PCI_BAR0_WIN
10472. BCMA_PCI_BAR0_WIN2
10473. BCMA_PCI_BAR1_CONTROL
10474. BCMA_PCI_BAR1_WIN
10475. BCMA_PCI_GPIO_HWRAD
10476. BCMA_PCI_GPIO_IN
10477. BCMA_PCI_GPIO_OUT
10478. BCMA_PCI_GPIO_OUT_ENABLE
10479. BCMA_PCI_GPIO_PLL
10480. BCMA_PCI_GPIO_SCS
10481. BCMA_PCI_GPIO_XTAL
10482. BCMA_PCI_IRQMASK
10483. BCMA_PCI_IRQS
10484. BCMA_PCI_PE
10485. BCMA_PCI_PMCSR
10486. BCMA_PCI_SLOT_MAX
10487. BCMA_PCI_SPROMCTL
10488. BCMA_PCI_SPROMCTL_WE
10489. BCMA_PKG_ID_BCM43224_FAB_CSM
10490. BCMA_PKG_ID_BCM43224_FAB_SMIC
10491. BCMA_PKG_ID_BCM4706L
10492. BCMA_PKG_ID_BCM4707
10493. BCMA_PKG_ID_BCM4708
10494. BCMA_PKG_ID_BCM4709
10495. BCMA_PKG_ID_BCM4716
10496. BCMA_PKG_ID_BCM4717
10497. BCMA_PKG_ID_BCM4718
10498. BCMA_PKG_ID_BCM47186
10499. BCMA_PKG_ID_BCM47188
10500. BCMA_PKG_ID_BCM47189
10501. BCMA_PKG_ID_BCM5357
10502. BCMA_PKG_ID_BCM53573
10503. BCMA_PKG_ID_BCM5358
10504. BCMA_PLLTYPE_1
10505. BCMA_PLLTYPE_2
10506. BCMA_PLLTYPE_3
10507. BCMA_PLLTYPE_4
10508. BCMA_PLLTYPE_5
10509. BCMA_PLLTYPE_6
10510. BCMA_PLLTYPE_7
10511. BCMA_PLLTYPE_NONE
10512. BCMA_PM_OPS
10513. BCMA_RESET_CTL
10514. BCMA_RESET_CTL_RESET
10515. BCMA_RESET_ST
10516. BCMA_RES_4314_AFE_LDO_PU
10517. BCMA_RES_4314_ALP_AVAIL
10518. BCMA_RES_4314_CBUCK_LPOM_PU
10519. BCMA_RES_4314_CBUCK_PFM_PU
10520. BCMA_RES_4314_CLDO_PU
10521. BCMA_RES_4314_HT_AVAIL
10522. BCMA_RES_4314_ILP_REQ
10523. BCMA_RES_4314_LDO3P3_PU
10524. BCMA_RES_4314_LNLDO_PU
10525. BCMA_RES_4314_LOGIC_RET
10526. BCMA_RES_4314_LPLDO2_LVM
10527. BCMA_RES_4314_LPLDO_PU
10528. BCMA_RES_4314_LQ_AVAIL
10529. BCMA_RES_4314_MACPHY_CLK_AVAIL
10530. BCMA_RES_4314_MACPHY_RET
10531. BCMA_RES_4314_MEM_SLEEP
10532. BCMA_RES_4314_MISC_PWRSW_PU
10533. BCMA_RES_4314_OTP_PU
10534. BCMA_RES_4314_PMU_BG_PU
10535. BCMA_RES_4314_PMU_SLEEP_DIS
10536. BCMA_RES_4314_RADIO_PU
10537. BCMA_RES_4314_RX_LDO_PU
10538. BCMA_RES_4314_RX_PWRSW_PU
10539. BCMA_RES_4314_SYNTH_PWRSW_PU
10540. BCMA_RES_4314_TX_LDO_PU
10541. BCMA_RES_4314_VCO_LDO_PU
10542. BCMA_RES_4314_WL_CORE_READY
10543. BCMA_RES_4314_WL_PMU_PU
10544. BCMA_RES_4314_WL_PWRSW_PU
10545. BCMA_RES_4314_XTAL_PU
10546. BCMA_SCAN_H_
10547. BCMA_SOC_FLASH1
10548. BCMA_SOC_FLASH1_SZ
10549. BCMA_SOC_FLASH2
10550. BCMA_SOC_FLASH2_SZ
10551. BCMA_SOC_PCI1_CFG
10552. BCMA_SOC_PCI1_MEM
10553. BCMA_SOC_PCIE1_DMA_H32
10554. BCMA_SOC_PCIE_DMA_H32
10555. BCMA_SOC_PCIE_DMA_L32
10556. BCMA_SOC_PCI_CFG
10557. BCMA_SOC_PCI_DMA
10558. BCMA_SOC_PCI_DMA2
10559. BCMA_SOC_PCI_DMA_SZ
10560. BCMA_SOC_PCI_MEM
10561. BCMA_SOC_PCI_MEM_SZ
10562. BCMA_SOC_SDRAM_BASE
10563. BCMA_SOC_SDRAM_R2
10564. BCMA_SOC_SDRAM_SWAPPED
10565. BCMA_WRAP_BASE
10566. BCMCPU_IS_3368
10567. BCMCPU_IS_6328
10568. BCMCPU_IS_6338
10569. BCMCPU_IS_6345
10570. BCMCPU_IS_6348
10571. BCMCPU_IS_6358
10572. BCMCPU_IS_6362
10573. BCMCPU_IS_6368
10574. BCMENETSW_DMA_MAXBURST
10575. BCMENET_DEF_RX_DESC
10576. BCMENET_DEF_TX_DESC
10577. BCMENET_DMA_MAXBURST
10578. BCMENET_MAX_MTU
10579. BCMENET_TX_FIFO_TRESH
10580. BCMEP_BULK
10581. BCMEP_CTRL
10582. BCMEP_IN
10583. BCMEP_INTR
10584. BCMEP_ISOC
10585. BCMEP_OUT
10586. BCMEXTRAHDROOM
10587. BCME_STRLEN
10588. BCMGENET_STATS_LEN
10589. BCMGENET_STAT_MIB_RX
10590. BCMGENET_STAT_MIB_TX
10591. BCMGENET_STAT_MISC
10592. BCMGENET_STAT_NETDEV
10593. BCMGENET_STAT_OFFSET
10594. BCMGENET_STAT_RUNT
10595. BCMGENET_STAT_SOFT
10596. BCMILCP_BCM_SUBTYPE_EVENT
10597. BCMILCP_SUBTYPE_VENDOR_LONG
10598. BCMMSG
10599. BCMPCI_REG_TIMERS
10600. BCMSB
10601. BCM_3368_ATM_BASE
10602. BCM_3368_ATM_IRQ
10603. BCM_3368_DDR_BASE
10604. BCM_3368_DSL_BASE
10605. BCM_3368_DSL_IRQ
10606. BCM_3368_DSL_LMEM_BASE
10607. BCM_3368_EHCI0_BASE
10608. BCM_3368_EHCI0_IRQ
10609. BCM_3368_ENET0_BASE
10610. BCM_3368_ENET0_IRQ
10611. BCM_3368_ENET0_RXDMA_IRQ
10612. BCM_3368_ENET0_TXDMA_IRQ
10613. BCM_3368_ENET1_BASE
10614. BCM_3368_ENET1_IRQ
10615. BCM_3368_ENET1_RXDMA_IRQ
10616. BCM_3368_ENET1_TXDMA_IRQ
10617. BCM_3368_ENETDMAC_BASE
10618. BCM_3368_ENETDMAS_BASE
10619. BCM_3368_ENETDMA_BASE
10620. BCM_3368_ENETSW_BASE
10621. BCM_3368_ENETSW_RXDMA0_IRQ
10622. BCM_3368_ENETSW_RXDMA1_IRQ
10623. BCM_3368_ENETSW_RXDMA2_IRQ
10624. BCM_3368_ENETSW_RXDMA3_IRQ
10625. BCM_3368_ENETSW_TXDMA0_IRQ
10626. BCM_3368_ENETSW_TXDMA1_IRQ
10627. BCM_3368_ENETSW_TXDMA2_IRQ
10628. BCM_3368_ENETSW_TXDMA3_IRQ
10629. BCM_3368_ENET_PHY_IRQ
10630. BCM_3368_EXT_IRQ0
10631. BCM_3368_EXT_IRQ1
10632. BCM_3368_EXT_IRQ2
10633. BCM_3368_EXT_IRQ3
10634. BCM_3368_GPIO_BASE
10635. BCM_3368_HSSPI_BASE
10636. BCM_3368_HSSPI_IRQ
10637. BCM_3368_M2M_BASE
10638. BCM_3368_MEMC_BASE
10639. BCM_3368_MISC_BASE
10640. BCM_3368_MPI_BASE
10641. BCM_3368_OHCI0_BASE
10642. BCM_3368_OHCI0_IRQ
10643. BCM_3368_OHCI_PRIV_BASE
10644. BCM_3368_PCIE_BASE
10645. BCM_3368_PCI_IRQ
10646. BCM_3368_PCMCIA_BASE
10647. BCM_3368_PCMCIA_IRQ
10648. BCM_3368_PCMDMAC_BASE
10649. BCM_3368_PCMDMAS_BASE
10650. BCM_3368_PCMDMA_BASE
10651. BCM_3368_PCM_BASE
10652. BCM_3368_PERF_BASE
10653. BCM_3368_RNG_BASE
10654. BCM_3368_SDRAM_BASE
10655. BCM_3368_SDRAM_REGS_BASE
10656. BCM_3368_SPI_BASE
10657. BCM_3368_SPI_IRQ
10658. BCM_3368_TIMER_BASE
10659. BCM_3368_TIMER_IRQ
10660. BCM_3368_UART0_BASE
10661. BCM_3368_UART0_IRQ
10662. BCM_3368_UART1_BASE
10663. BCM_3368_UART1_IRQ
10664. BCM_3368_UBUS_BASE
10665. BCM_3368_UDC0_BASE
10666. BCM_3368_UDC0_IRQ
10667. BCM_3368_USBDMA_BASE
10668. BCM_3368_USBD_BASE
10669. BCM_3368_USBD_IRQ
10670. BCM_3368_USBD_RXDMA0_IRQ
10671. BCM_3368_USBD_RXDMA1_IRQ
10672. BCM_3368_USBD_RXDMA2_IRQ
10673. BCM_3368_USBD_TXDMA0_IRQ
10674. BCM_3368_USBD_TXDMA1_IRQ
10675. BCM_3368_USBD_TXDMA2_IRQ
10676. BCM_3368_USBH_PRIV_BASE
10677. BCM_3368_WDT_BASE
10678. BCM_3368_XTMDMAC_BASE
10679. BCM_3368_XTMDMAS_BASE
10680. BCM_3368_XTMDMA_BASE
10681. BCM_3368_XTM_BASE
10682. BCM_3368_XTM_DMA0_IRQ
10683. BCM_3368_XTM_IRQ
10684. BCM_5710_FW_COMPILE_FLAGS
10685. BCM_5710_FW_ENGINEERING_VERSION
10686. BCM_5710_FW_MAJOR_VERSION
10687. BCM_5710_FW_MINOR_VERSION
10688. BCM_5710_FW_REVISION_VERSION
10689. BCM_5710_UNDI_FW_MF_MAJOR
10690. BCM_5710_UNDI_FW_MF_MINOR
10691. BCM_5710_UNDI_FW_MF_VERS
10692. BCM_6328_ATM_BASE
10693. BCM_6328_ATM_IRQ
10694. BCM_6328_DDR_BASE
10695. BCM_6328_DSL_BASE
10696. BCM_6328_DSL_IRQ
10697. BCM_6328_DSL_LMEM_BASE
10698. BCM_6328_EHCI0_BASE
10699. BCM_6328_EHCI0_IRQ
10700. BCM_6328_ENET0_BASE
10701. BCM_6328_ENET0_IRQ
10702. BCM_6328_ENET0_RXDMA_IRQ
10703. BCM_6328_ENET0_TXDMA_IRQ
10704. BCM_6328_ENET1_BASE
10705. BCM_6328_ENET1_IRQ
10706. BCM_6328_ENET1_RXDMA_IRQ
10707. BCM_6328_ENET1_TXDMA_IRQ
10708. BCM_6328_ENETDMAC_BASE
10709. BCM_6328_ENETDMAS_BASE
10710. BCM_6328_ENETDMA_BASE
10711. BCM_6328_ENETSW_BASE
10712. BCM_6328_ENETSW_RXDMA0_IRQ
10713. BCM_6328_ENETSW_RXDMA1_IRQ
10714. BCM_6328_ENETSW_RXDMA2_IRQ
10715. BCM_6328_ENETSW_RXDMA3_IRQ
10716. BCM_6328_ENETSW_TXDMA0_IRQ
10717. BCM_6328_ENETSW_TXDMA1_IRQ
10718. BCM_6328_ENETSW_TXDMA2_IRQ
10719. BCM_6328_ENETSW_TXDMA3_IRQ
10720. BCM_6328_ENET_PHY_IRQ
10721. BCM_6328_EXT_IRQ0
10722. BCM_6328_EXT_IRQ1
10723. BCM_6328_EXT_IRQ2
10724. BCM_6328_EXT_IRQ3
10725. BCM_6328_GPIO_BASE
10726. BCM_6328_HIGH_IRQ_BASE
10727. BCM_6328_HSSPI_BASE
10728. BCM_6328_HSSPI_IRQ
10729. BCM_6328_M2M_BASE
10730. BCM_6328_MEMC_BASE
10731. BCM_6328_MISC_BASE
10732. BCM_6328_MPI_BASE
10733. BCM_6328_OHCI0_BASE
10734. BCM_6328_OHCI0_IRQ
10735. BCM_6328_OHCI_PRIV_BASE
10736. BCM_6328_OTP_BASE
10737. BCM_6328_PCIE_BASE
10738. BCM_6328_PCI_IRQ
10739. BCM_6328_PCMCIA_BASE
10740. BCM_6328_PCMCIA_IRQ
10741. BCM_6328_PCMDMAC_BASE
10742. BCM_6328_PCMDMAS_BASE
10743. BCM_6328_PCMDMA_BASE
10744. BCM_6328_PCM_BASE
10745. BCM_6328_PCM_DMA0_IRQ
10746. BCM_6328_PCM_DMA1_IRQ
10747. BCM_6328_PERF_BASE
10748. BCM_6328_RNG_BASE
10749. BCM_6328_SDRAM_BASE
10750. BCM_6328_SDRAM_REGS_BASE
10751. BCM_6328_SPI_BASE
10752. BCM_6328_SPI_IRQ
10753. BCM_6328_TIMER_BASE
10754. BCM_6328_TIMER_IRQ
10755. BCM_6328_UART0_BASE
10756. BCM_6328_UART0_IRQ
10757. BCM_6328_UART1_BASE
10758. BCM_6328_UART1_IRQ
10759. BCM_6328_UBUS_BASE
10760. BCM_6328_UDC0_BASE
10761. BCM_6328_UDC0_IRQ
10762. BCM_6328_USBDMA_BASE
10763. BCM_6328_USBD_BASE
10764. BCM_6328_USBD_IRQ
10765. BCM_6328_USBD_RXDMA0_IRQ
10766. BCM_6328_USBD_RXDMA1_IRQ
10767. BCM_6328_USBD_RXDMA2_IRQ
10768. BCM_6328_USBD_TXDMA0_IRQ
10769. BCM_6328_USBD_TXDMA1_IRQ
10770. BCM_6328_USBD_TXDMA2_IRQ
10771. BCM_6328_USBH_PRIV_BASE
10772. BCM_6328_WDT_BASE
10773. BCM_6328_XTMDMAC_BASE
10774. BCM_6328_XTMDMAS_BASE
10775. BCM_6328_XTMDMA_BASE
10776. BCM_6328_XTM_BASE
10777. BCM_6328_XTM_DMA0_IRQ
10778. BCM_6328_XTM_IRQ
10779. BCM_6338_ATM_BASE
10780. BCM_6338_ATM_IRQ
10781. BCM_6338_BB_BASE
10782. BCM_6338_DDR_BASE
10783. BCM_6338_DSL_BASE
10784. BCM_6338_DSL_IRQ
10785. BCM_6338_DSL_LMEM_BASE
10786. BCM_6338_EHCI0_BASE
10787. BCM_6338_EHCI0_IRQ
10788. BCM_6338_ENET0_BASE
10789. BCM_6338_ENET0_IRQ
10790. BCM_6338_ENET0_RXDMA_IRQ
10791. BCM_6338_ENET0_TXDMA_IRQ
10792. BCM_6338_ENET1_BASE
10793. BCM_6338_ENET1_IRQ
10794. BCM_6338_ENET1_RXDMA_IRQ
10795. BCM_6338_ENET1_TXDMA_IRQ
10796. BCM_6338_ENETDMAC_BASE
10797. BCM_6338_ENETDMAS_BASE
10798. BCM_6338_ENETDMA_BASE
10799. BCM_6338_ENETSW_BASE
10800. BCM_6338_ENETSW_RXDMA0_IRQ
10801. BCM_6338_ENETSW_RXDMA1_IRQ
10802. BCM_6338_ENETSW_RXDMA2_IRQ
10803. BCM_6338_ENETSW_RXDMA3_IRQ
10804. BCM_6338_ENETSW_TXDMA0_IRQ
10805. BCM_6338_ENETSW_TXDMA1_IRQ
10806. BCM_6338_ENETSW_TXDMA2_IRQ
10807. BCM_6338_ENETSW_TXDMA3_IRQ
10808. BCM_6338_ENET_PHY_IRQ
10809. BCM_6338_GPIO_BASE
10810. BCM_6338_HSSPI_BASE
10811. BCM_6338_HSSPI_IRQ
10812. BCM_6338_M2M_BASE
10813. BCM_6338_MEMC_BASE
10814. BCM_6338_MISC_BASE
10815. BCM_6338_MPI_BASE
10816. BCM_6338_OHCI0_BASE
10817. BCM_6338_OHCI0_IRQ
10818. BCM_6338_OHCI_PRIV_BASE
10819. BCM_6338_PCIE_BASE
10820. BCM_6338_PCI_IRQ
10821. BCM_6338_PCMCIA_BASE
10822. BCM_6338_PCMCIA_IRQ
10823. BCM_6338_PCMDMAC_BASE
10824. BCM_6338_PCMDMAS_BASE
10825. BCM_6338_PCMDMA_BASE
10826. BCM_6338_PCM_BASE
10827. BCM_6338_PERF_BASE
10828. BCM_6338_RNG_BASE
10829. BCM_6338_RSET_SPI_SIZE
10830. BCM_6338_SDRAM_BASE
10831. BCM_6338_SDRAM_REGS_BASE
10832. BCM_6338_SPI_BASE
10833. BCM_6338_SPI_IRQ
10834. BCM_6338_TIMER_BASE
10835. BCM_6338_TIMER_IRQ
10836. BCM_6338_UART0_BASE
10837. BCM_6338_UART0_IRQ
10838. BCM_6338_UART1_BASE
10839. BCM_6338_UART1_IRQ
10840. BCM_6338_UBUS_BASE
10841. BCM_6338_UDC0_BASE
10842. BCM_6338_USBDMA_BASE
10843. BCM_6338_USBD_BASE
10844. BCM_6338_USBD_IRQ
10845. BCM_6338_USBD_RXDMA0_IRQ
10846. BCM_6338_USBD_RXDMA1_IRQ
10847. BCM_6338_USBD_RXDMA2_IRQ
10848. BCM_6338_USBD_TXDMA0_IRQ
10849. BCM_6338_USBD_TXDMA1_IRQ
10850. BCM_6338_USBD_TXDMA2_IRQ
10851. BCM_6338_USBH_PRIV_BASE
10852. BCM_6338_WDT_BASE
10853. BCM_6338_XTMDMAC_BASE
10854. BCM_6338_XTMDMAS_BASE
10855. BCM_6338_XTMDMA_BASE
10856. BCM_6338_XTM_BASE
10857. BCM_6338_XTM_DMA0_IRQ
10858. BCM_6338_XTM_IRQ
10859. BCM_6345_ATM_BASE
10860. BCM_6345_ATM_IRQ
10861. BCM_6345_BB_BASE
10862. BCM_6345_DDR_BASE
10863. BCM_6345_DSL_BASE
10864. BCM_6345_DSL_IRQ
10865. BCM_6345_DSL_LMEM_BASE
10866. BCM_6345_EHCI0_BASE
10867. BCM_6345_EHCI0_IRQ
10868. BCM_6345_ENET0_BASE
10869. BCM_6345_ENET0_IRQ
10870. BCM_6345_ENET0_RXDMA_IRQ
10871. BCM_6345_ENET0_TXDMA_IRQ
10872. BCM_6345_ENET1_BASE
10873. BCM_6345_ENET1_IRQ
10874. BCM_6345_ENET1_RXDMA_IRQ
10875. BCM_6345_ENET1_TXDMA_IRQ
10876. BCM_6345_ENETDMAC_BASE
10877. BCM_6345_ENETDMAS_BASE
10878. BCM_6345_ENETDMA_BASE
10879. BCM_6345_ENETSW_BASE
10880. BCM_6345_ENETSW_RXDMA0_IRQ
10881. BCM_6345_ENETSW_RXDMA1_IRQ
10882. BCM_6345_ENETSW_RXDMA2_IRQ
10883. BCM_6345_ENETSW_RXDMA3_IRQ
10884. BCM_6345_ENETSW_TXDMA0_IRQ
10885. BCM_6345_ENETSW_TXDMA1_IRQ
10886. BCM_6345_ENETSW_TXDMA2_IRQ
10887. BCM_6345_ENETSW_TXDMA3_IRQ
10888. BCM_6345_ENET_PHY_IRQ
10889. BCM_6345_GPIO_BASE
10890. BCM_6345_HSSPI_BASE
10891. BCM_6345_HSSPI_IRQ
10892. BCM_6345_M2M_BASE
10893. BCM_6345_MEMC_BASE
10894. BCM_6345_MISC_BASE
10895. BCM_6345_MPI_BASE
10896. BCM_6345_OHCI0_BASE
10897. BCM_6345_OHCI0_IRQ
10898. BCM_6345_OHCI_PRIV_BASE
10899. BCM_6345_PCIE_BASE
10900. BCM_6345_PCI_IRQ
10901. BCM_6345_PCMCIA_BASE
10902. BCM_6345_PCMCIA_IRQ
10903. BCM_6345_PCMDMAC_BASE
10904. BCM_6345_PCMDMAS_BASE
10905. BCM_6345_PCMDMA_BASE
10906. BCM_6345_PCM_BASE
10907. BCM_6345_PERF_BASE
10908. BCM_6345_RNG_BASE
10909. BCM_6345_SDRAM_BASE
10910. BCM_6345_SDRAM_REGS_BASE
10911. BCM_6345_SPI_BASE
10912. BCM_6345_SPI_IRQ
10913. BCM_6345_TIMER_BASE
10914. BCM_6345_TIMER_IRQ
10915. BCM_6345_UART0_BASE
10916. BCM_6345_UART0_IRQ
10917. BCM_6345_UART1_BASE
10918. BCM_6345_UART1_IRQ
10919. BCM_6345_UBUS_BASE
10920. BCM_6345_UDC0_BASE
10921. BCM_6345_USBDMA_BASE
10922. BCM_6345_USBD_BASE
10923. BCM_6345_USBD_IRQ
10924. BCM_6345_USBD_RXDMA0_IRQ
10925. BCM_6345_USBD_RXDMA1_IRQ
10926. BCM_6345_USBD_RXDMA2_IRQ
10927. BCM_6345_USBD_TXDMA0_IRQ
10928. BCM_6345_USBD_TXDMA1_IRQ
10929. BCM_6345_USBD_TXDMA2_IRQ
10930. BCM_6345_USBH_PRIV_BASE
10931. BCM_6345_WDT_BASE
10932. BCM_6345_XTMDMAC_BASE
10933. BCM_6345_XTMDMAS_BASE
10934. BCM_6345_XTMDMA_BASE
10935. BCM_6345_XTM_BASE
10936. BCM_6345_XTM_DMA0_IRQ
10937. BCM_6345_XTM_IRQ
10938. BCM_6348_ATM_BASE
10939. BCM_6348_ATM_IRQ
10940. BCM_6348_DDR_BASE
10941. BCM_6348_DSL_BASE
10942. BCM_6348_DSL_IRQ
10943. BCM_6348_DSL_LMEM_BASE
10944. BCM_6348_EHCI0_BASE
10945. BCM_6348_EHCI0_IRQ
10946. BCM_6348_ENET0_BASE
10947. BCM_6348_ENET0_IRQ
10948. BCM_6348_ENET0_RXDMA_IRQ
10949. BCM_6348_ENET0_TXDMA_IRQ
10950. BCM_6348_ENET1_BASE
10951. BCM_6348_ENET1_IRQ
10952. BCM_6348_ENET1_RXDMA_IRQ
10953. BCM_6348_ENET1_TXDMA_IRQ
10954. BCM_6348_ENETDMAC_BASE
10955. BCM_6348_ENETDMAS_BASE
10956. BCM_6348_ENETDMA_BASE
10957. BCM_6348_ENETSW_BASE
10958. BCM_6348_ENETSW_RXDMA0_IRQ
10959. BCM_6348_ENETSW_RXDMA1_IRQ
10960. BCM_6348_ENETSW_RXDMA2_IRQ
10961. BCM_6348_ENETSW_RXDMA3_IRQ
10962. BCM_6348_ENETSW_TXDMA0_IRQ
10963. BCM_6348_ENETSW_TXDMA1_IRQ
10964. BCM_6348_ENETSW_TXDMA2_IRQ
10965. BCM_6348_ENETSW_TXDMA3_IRQ
10966. BCM_6348_ENET_PHY_IRQ
10967. BCM_6348_GPIO_BASE
10968. BCM_6348_HSSPI_BASE
10969. BCM_6348_HSSPI_IRQ
10970. BCM_6348_M2M_BASE
10971. BCM_6348_MEMC_BASE
10972. BCM_6348_MISC_BASE
10973. BCM_6348_MPI_BASE
10974. BCM_6348_OHCI0_BASE
10975. BCM_6348_OHCI0_IRQ
10976. BCM_6348_OHCI_PRIV_BASE
10977. BCM_6348_PCIE_BASE
10978. BCM_6348_PCI_IRQ
10979. BCM_6348_PCMCIA_BASE
10980. BCM_6348_PCMCIA_IRQ
10981. BCM_6348_PCMDMAC_BASE
10982. BCM_6348_PCMDMAS_BASE
10983. BCM_6348_PCMDMA_BASE
10984. BCM_6348_PCM_BASE
10985. BCM_6348_PERF_BASE
10986. BCM_6348_RNG_BASE
10987. BCM_6348_RSET_SPI_SIZE
10988. BCM_6348_SDRAM_BASE
10989. BCM_6348_SDRAM_REGS_BASE
10990. BCM_6348_SPI_BASE
10991. BCM_6348_SPI_IRQ
10992. BCM_6348_TIMER_BASE
10993. BCM_6348_TIMER_IRQ
10994. BCM_6348_UART0_BASE
10995. BCM_6348_UART0_IRQ
10996. BCM_6348_UART1_BASE
10997. BCM_6348_UART1_IRQ
10998. BCM_6348_UDC0_BASE
10999. BCM_6348_USBDMA_BASE
11000. BCM_6348_USBD_BASE
11001. BCM_6348_USBD_IRQ
11002. BCM_6348_USBD_RXDMA0_IRQ
11003. BCM_6348_USBD_RXDMA1_IRQ
11004. BCM_6348_USBD_RXDMA2_IRQ
11005. BCM_6348_USBD_TXDMA0_IRQ
11006. BCM_6348_USBD_TXDMA1_IRQ
11007. BCM_6348_USBD_TXDMA2_IRQ
11008. BCM_6348_USBH_PRIV_BASE
11009. BCM_6348_WDT_BASE
11010. BCM_6348_XTMDMAC_BASE
11011. BCM_6348_XTMDMAS_BASE
11012. BCM_6348_XTMDMA_BASE
11013. BCM_6348_XTM_BASE
11014. BCM_6348_XTM_DMA0_IRQ
11015. BCM_6348_XTM_IRQ
11016. BCM_6358_ATM_BASE
11017. BCM_6358_ATM_IRQ
11018. BCM_6358_DDR_BASE
11019. BCM_6358_DSL_BASE
11020. BCM_6358_DSL_IRQ
11021. BCM_6358_DSL_LMEM_BASE
11022. BCM_6358_EHCI0_BASE
11023. BCM_6358_EHCI0_IRQ
11024. BCM_6358_ENET0_BASE
11025. BCM_6358_ENET0_IRQ
11026. BCM_6358_ENET0_RXDMA_IRQ
11027. BCM_6358_ENET0_TXDMA_IRQ
11028. BCM_6358_ENET1_BASE
11029. BCM_6358_ENET1_IRQ
11030. BCM_6358_ENET1_RXDMA_IRQ
11031. BCM_6358_ENET1_TXDMA_IRQ
11032. BCM_6358_ENETDMAC_BASE
11033. BCM_6358_ENETDMAS_BASE
11034. BCM_6358_ENETDMA_BASE
11035. BCM_6358_ENETSW_BASE
11036. BCM_6358_ENETSW_RXDMA0_IRQ
11037. BCM_6358_ENETSW_RXDMA1_IRQ
11038. BCM_6358_ENETSW_RXDMA2_IRQ
11039. BCM_6358_ENETSW_RXDMA3_IRQ
11040. BCM_6358_ENETSW_TXDMA0_IRQ
11041. BCM_6358_ENETSW_TXDMA1_IRQ
11042. BCM_6358_ENETSW_TXDMA2_IRQ
11043. BCM_6358_ENETSW_TXDMA3_IRQ
11044. BCM_6358_ENET_PHY_IRQ
11045. BCM_6358_EXT_IRQ0
11046. BCM_6358_EXT_IRQ1
11047. BCM_6358_EXT_IRQ2
11048. BCM_6358_EXT_IRQ3
11049. BCM_6358_GPIO_BASE
11050. BCM_6358_HSSPI_BASE
11051. BCM_6358_HSSPI_IRQ
11052. BCM_6358_M2M_BASE
11053. BCM_6358_MEMC_BASE
11054. BCM_6358_MISC_BASE
11055. BCM_6358_MPI_BASE
11056. BCM_6358_OHCI0_BASE
11057. BCM_6358_OHCI0_IRQ
11058. BCM_6358_OHCI_PRIV_BASE
11059. BCM_6358_PCIE_BASE
11060. BCM_6358_PCI_IRQ
11061. BCM_6358_PCMCIA_BASE
11062. BCM_6358_PCMCIA_IRQ
11063. BCM_6358_PCMDMAC_BASE
11064. BCM_6358_PCMDMAS_BASE
11065. BCM_6358_PCMDMA_BASE
11066. BCM_6358_PCM_BASE
11067. BCM_6358_PCM_DMA0_IRQ
11068. BCM_6358_PCM_DMA1_IRQ
11069. BCM_6358_PERF_BASE
11070. BCM_6358_RNG_BASE
11071. BCM_6358_RSET_SPI_SIZE
11072. BCM_6358_SDRAM_BASE
11073. BCM_6358_SDRAM_REGS_BASE
11074. BCM_6358_SPI_BASE
11075. BCM_6358_SPI_IRQ
11076. BCM_6358_TIMER_BASE
11077. BCM_6358_TIMER_IRQ
11078. BCM_6358_UART0_BASE
11079. BCM_6358_UART0_IRQ
11080. BCM_6358_UART1_BASE
11081. BCM_6358_UART1_IRQ
11082. BCM_6358_UDC0_BASE
11083. BCM_6358_USBDMA_BASE
11084. BCM_6358_USBD_BASE
11085. BCM_6358_USBD_IRQ
11086. BCM_6358_USBD_RXDMA0_IRQ
11087. BCM_6358_USBD_RXDMA1_IRQ
11088. BCM_6358_USBD_RXDMA2_IRQ
11089. BCM_6358_USBD_TXDMA0_IRQ
11090. BCM_6358_USBD_TXDMA1_IRQ
11091. BCM_6358_USBD_TXDMA2_IRQ
11092. BCM_6358_USBH_PRIV_BASE
11093. BCM_6358_WDT_BASE
11094. BCM_6358_XTMDMAC_BASE
11095. BCM_6358_XTMDMAS_BASE
11096. BCM_6358_XTMDMA_BASE
11097. BCM_6358_XTM_BASE
11098. BCM_6358_XTM_DMA0_IRQ
11099. BCM_6358_XTM_IRQ
11100. BCM_6362_ATM_BASE
11101. BCM_6362_ATM_IRQ
11102. BCM_6362_DDR_BASE
11103. BCM_6362_DECT0_IRQ
11104. BCM_6362_DECT1_IRQ
11105. BCM_6362_DG_IRQ
11106. BCM_6362_DSL_BASE
11107. BCM_6362_DSL_IRQ
11108. BCM_6362_DSL_LMEM_BASE
11109. BCM_6362_EHCI0_BASE
11110. BCM_6362_EHCI0_IRQ
11111. BCM_6362_ENET0_BASE
11112. BCM_6362_ENET0_IRQ
11113. BCM_6362_ENET0_RXDMA_IRQ
11114. BCM_6362_ENET0_TXDMA_IRQ
11115. BCM_6362_ENET1_BASE
11116. BCM_6362_ENET1_IRQ
11117. BCM_6362_ENET1_RXDMA_IRQ
11118. BCM_6362_ENET1_TXDMA_IRQ
11119. BCM_6362_ENETDMAC_BASE
11120. BCM_6362_ENETDMAS_BASE
11121. BCM_6362_ENETDMA_BASE
11122. BCM_6362_ENETSW_BASE
11123. BCM_6362_ENETSW_RXDMA0_IRQ
11124. BCM_6362_ENETSW_RXDMA1_IRQ
11125. BCM_6362_ENETSW_RXDMA2_IRQ
11126. BCM_6362_ENETSW_RXDMA3_IRQ
11127. BCM_6362_ENETSW_TXDMA0_IRQ
11128. BCM_6362_ENETSW_TXDMA1_IRQ
11129. BCM_6362_ENETSW_TXDMA2_IRQ
11130. BCM_6362_ENETSW_TXDMA3_IRQ
11131. BCM_6362_ENET_PHY_IRQ
11132. BCM_6362_EPHY_ENERGY0_IRQ
11133. BCM_6362_EPHY_ENERGY1_IRQ
11134. BCM_6362_EPHY_ENERGY2_IRQ
11135. BCM_6362_EPHY_ENERGY3_IRQ
11136. BCM_6362_EXT_IRQ0
11137. BCM_6362_EXT_IRQ1
11138. BCM_6362_EXT_IRQ2
11139. BCM_6362_EXT_IRQ3
11140. BCM_6362_FAP0_IRQ
11141. BCM_6362_GPIO_BASE
11142. BCM_6362_HIGH_IRQ_BASE
11143. BCM_6362_HSSPI_BASE
11144. BCM_6362_HSSPI_IRQ
11145. BCM_6362_IPSEC_BASE
11146. BCM_6362_IPSEC_DMA0_IRQ
11147. BCM_6362_IPSEC_DMA1_IRQ
11148. BCM_6362_IPSEC_DMA_BASE
11149. BCM_6362_IPSEC_IRQ
11150. BCM_6362_LED_BASE
11151. BCM_6362_M2M_BASE
11152. BCM_6362_MEMC_BASE
11153. BCM_6362_MISC_BASE
11154. BCM_6362_MPI_BASE
11155. BCM_6362_NAND_CACHE_BASE
11156. BCM_6362_NAND_IRQ
11157. BCM_6362_NAND_REG_BASE
11158. BCM_6362_OHCI0_BASE
11159. BCM_6362_OHCI0_IRQ
11160. BCM_6362_OHCI_PRIV_BASE
11161. BCM_6362_PCIE_BASE
11162. BCM_6362_PCI_IRQ
11163. BCM_6362_PCMCIA_BASE
11164. BCM_6362_PCMCIA_IRQ
11165. BCM_6362_PCMDMAC_BASE
11166. BCM_6362_PCMDMAS_BASE
11167. BCM_6362_PCMDMA_BASE
11168. BCM_6362_PCM_BASE
11169. BCM_6362_PCM_DMA0_IRQ
11170. BCM_6362_PCM_DMA1_IRQ
11171. BCM_6362_PCM_IRQ
11172. BCM_6362_PERF_BASE
11173. BCM_6362_RING_OSC_IRQ
11174. BCM_6362_RNG_BASE
11175. BCM_6362_SDRAM_BASE
11176. BCM_6362_SDRAM_REGS_BASE
11177. BCM_6362_SPI_BASE
11178. BCM_6362_SPI_IRQ
11179. BCM_6362_TIMER_BASE
11180. BCM_6362_TIMER_IRQ
11181. BCM_6362_UART0_BASE
11182. BCM_6362_UART0_IRQ
11183. BCM_6362_UART1_BASE
11184. BCM_6362_UART1_IRQ
11185. BCM_6362_UBUS_BASE
11186. BCM_6362_UDC0_BASE
11187. BCM_6362_UDC0_IRQ
11188. BCM_6362_USBDMA_BASE
11189. BCM_6362_USBD_BASE
11190. BCM_6362_USBD_IRQ
11191. BCM_6362_USBD_RXDMA0_IRQ
11192. BCM_6362_USBD_RXDMA1_IRQ
11193. BCM_6362_USBD_RXDMA2_IRQ
11194. BCM_6362_USBD_TXDMA0_IRQ
11195. BCM_6362_USBD_TXDMA1_IRQ
11196. BCM_6362_USBD_TXDMA2_IRQ
11197. BCM_6362_USBH_PRIV_BASE
11198. BCM_6362_WDT_BASE
11199. BCM_6362_WLAN_CHIPCOMMON_BASE
11200. BCM_6362_WLAN_D11_BASE
11201. BCM_6362_WLAN_GPIO_IRQ
11202. BCM_6362_WLAN_IRQ
11203. BCM_6362_WLAN_SHIM_BASE
11204. BCM_6362_XTMDMAC_BASE
11205. BCM_6362_XTMDMAS_BASE
11206. BCM_6362_XTMDMA_BASE
11207. BCM_6362_XTM_BASE
11208. BCM_6362_XTM_DMA0_IRQ
11209. BCM_6362_XTM_IRQ
11210. BCM_6368_ATM_BASE
11211. BCM_6368_ATM_IRQ
11212. BCM_6368_DDR_BASE
11213. BCM_6368_DSL_BASE
11214. BCM_6368_DSL_IRQ
11215. BCM_6368_DSL_LMEM_BASE
11216. BCM_6368_EHCI0_BASE
11217. BCM_6368_EHCI0_IRQ
11218. BCM_6368_ENET0_BASE
11219. BCM_6368_ENET0_IRQ
11220. BCM_6368_ENET0_RXDMA_IRQ
11221. BCM_6368_ENET0_TXDMA_IRQ
11222. BCM_6368_ENET1_BASE
11223. BCM_6368_ENET1_IRQ
11224. BCM_6368_ENET1_RXDMA_IRQ
11225. BCM_6368_ENET1_TXDMA_IRQ
11226. BCM_6368_ENETDMAC_BASE
11227. BCM_6368_ENETDMAS_BASE
11228. BCM_6368_ENETDMA_BASE
11229. BCM_6368_ENETSW_BASE
11230. BCM_6368_ENETSW_RXDMA0_IRQ
11231. BCM_6368_ENETSW_RXDMA1_IRQ
11232. BCM_6368_ENETSW_RXDMA2_IRQ
11233. BCM_6368_ENETSW_RXDMA3_IRQ
11234. BCM_6368_ENETSW_TXDMA0_IRQ
11235. BCM_6368_ENETSW_TXDMA1_IRQ
11236. BCM_6368_ENETSW_TXDMA2_IRQ
11237. BCM_6368_ENETSW_TXDMA3_IRQ
11238. BCM_6368_ENET_PHY_IRQ
11239. BCM_6368_EXT_IRQ0
11240. BCM_6368_EXT_IRQ1
11241. BCM_6368_EXT_IRQ2
11242. BCM_6368_EXT_IRQ3
11243. BCM_6368_EXT_IRQ4
11244. BCM_6368_EXT_IRQ5
11245. BCM_6368_GPIO_BASE
11246. BCM_6368_HIGH_IRQ_BASE
11247. BCM_6368_HSSPI_BASE
11248. BCM_6368_HSSPI_IRQ
11249. BCM_6368_M2M_BASE
11250. BCM_6368_MEMC_BASE
11251. BCM_6368_MISC_BASE
11252. BCM_6368_MPI_BASE
11253. BCM_6368_OHCI0_BASE
11254. BCM_6368_OHCI0_IRQ
11255. BCM_6368_OHCI_PRIV_BASE
11256. BCM_6368_PCIE_BASE
11257. BCM_6368_PCI_IRQ
11258. BCM_6368_PCMCIA_BASE
11259. BCM_6368_PCMCIA_IRQ
11260. BCM_6368_PCMDMAC_BASE
11261. BCM_6368_PCMDMAS_BASE
11262. BCM_6368_PCMDMA_BASE
11263. BCM_6368_PCM_BASE
11264. BCM_6368_PCM_DMA0_IRQ
11265. BCM_6368_PCM_DMA1_IRQ
11266. BCM_6368_PERF_BASE
11267. BCM_6368_RNG_BASE
11268. BCM_6368_RSET_SPI_SIZE
11269. BCM_6368_SDRAM_BASE
11270. BCM_6368_SDRAM_REGS_BASE
11271. BCM_6368_SPI_BASE
11272. BCM_6368_SPI_IRQ
11273. BCM_6368_TIMER_BASE
11274. BCM_6368_TIMER_IRQ
11275. BCM_6368_UART0_BASE
11276. BCM_6368_UART0_IRQ
11277. BCM_6368_UART1_BASE
11278. BCM_6368_UART1_IRQ
11279. BCM_6368_UDC0_BASE
11280. BCM_6368_USBDMA_BASE
11281. BCM_6368_USBD_BASE
11282. BCM_6368_USBD_IRQ
11283. BCM_6368_USBD_RXDMA0_IRQ
11284. BCM_6368_USBD_RXDMA1_IRQ
11285. BCM_6368_USBD_RXDMA2_IRQ
11286. BCM_6368_USBD_TXDMA0_IRQ
11287. BCM_6368_USBD_TXDMA1_IRQ
11288. BCM_6368_USBD_TXDMA2_IRQ
11289. BCM_6368_USBH_PRIV_BASE
11290. BCM_6368_WDT_BASE
11291. BCM_6368_XTMDMAC_BASE
11292. BCM_6368_XTMDMAS_BASE
11293. BCM_6368_XTMDMA_BASE
11294. BCM_6368_XTM_BASE
11295. BCM_6368_XTM_DMA0_IRQ
11296. BCM_6368_XTM_IRQ
11297. BCM_APD_CLR_MASK
11298. BCM_APD_SINGLELP_EN
11299. BCM_AUTOSUSPEND_DELAY
11300. BCM_CAN_FLAGS_MASK
11301. BCM_CB_MEM_BASE_PA
11302. BCM_CB_MEM_END_PA
11303. BCM_CB_MEM_SIZE
11304. BCM_CHIP_LEN
11305. BCM_CL45VEN_EEE_ADV
11306. BCM_CLK_DIV_FLAGS_EXISTS
11307. BCM_CLK_DIV_FLAGS_FIXED
11308. BCM_CLK_GATE_FLAGS_ENABLED
11309. BCM_CLK_GATE_FLAGS_EXISTS
11310. BCM_CLK_GATE_FLAGS_HW
11311. BCM_CLK_GATE_FLAGS_NO_DISABLE
11312. BCM_CLK_GATE_FLAGS_SW
11313. BCM_CLK_GATE_FLAGS_SW_MANAGED
11314. BCM_CLK_TRIG_FLAGS_EXISTS
11315. BCM_CMD_NOACTION
11316. BCM_CMD_RESTART
11317. BCM_CMD_START
11318. BCM_CMD_STOP
11319. BCM_CNIC
11320. BCM_CYGNUS_ASIU_ADC_CLK
11321. BCM_CYGNUS_ASIU_KEYPAD_CLK
11322. BCM_CYGNUS_ASIU_PWM_CLK
11323. BCM_CYGNUS_AUDIOPLL
11324. BCM_CYGNUS_AUDIOPLL_CH0
11325. BCM_CYGNUS_AUDIOPLL_CH1
11326. BCM_CYGNUS_AUDIOPLL_CH2
11327. BCM_CYGNUS_GENPLL
11328. BCM_CYGNUS_GENPLL_250MHZ_CLK
11329. BCM_CYGNUS_GENPLL_AUDIO_125_CLK
11330. BCM_CYGNUS_GENPLL_AXI21_CLK
11331. BCM_CYGNUS_GENPLL_CAN_CLK
11332. BCM_CYGNUS_GENPLL_ENET_SW_CLK
11333. BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
11334. BCM_CYGNUS_LCPLL0
11335. BCM_CYGNUS_LCPLL0_CH5_UNUSED
11336. BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
11337. BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
11338. BCM_CYGNUS_LCPLL0_SDIO_CLK
11339. BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
11340. BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
11341. BCM_CYGNUS_MIPIPLL
11342. BCM_CYGNUS_MIPIPLL_CH0_UNUSED
11343. BCM_CYGNUS_MIPIPLL_CH1_LCD
11344. BCM_CYGNUS_MIPIPLL_CH2_V3D
11345. BCM_CYGNUS_MIPIPLL_CH3_UNUSED
11346. BCM_CYGNUS_MIPIPLL_CH4_UNUSED
11347. BCM_CYGNUS_MIPIPLL_CH5_UNUSED
11348. BCM_DCBNL
11349. BCM_ENETSW_STATS_LEN
11350. BCM_ENET_STATS_LEN
11351. BCM_EXP_MULTICOLOR
11352. BCM_GPIO_PASSWD
11353. BCM_HDR_LEN
11354. BCM_IPROC_I2C_PM_OPS
11355. BCM_KONA_SMC_H
11356. BCM_KONA_WDT_NAME
11357. BCM_LED_MULTICOLOR_ACT
11358. BCM_LED_MULTICOLOR_ACT_FLASH
11359. BCM_LED_MULTICOLOR_ALT
11360. BCM_LED_MULTICOLOR_FDX
11361. BCM_LED_MULTICOLOR_FLASH
11362. BCM_LED_MULTICOLOR_IN_PHASE
11363. BCM_LED_MULTICOLOR_LINK
11364. BCM_LED_MULTICOLOR_LINK_ACT
11365. BCM_LED_MULTICOLOR_OFF
11366. BCM_LED_MULTICOLOR_ON
11367. BCM_LED_MULTICOLOR_PROGRAM
11368. BCM_LED_MULTICOLOR_SPEED
11369. BCM_LED_SRC_ACTIVITYLED
11370. BCM_LED_SRC_FDXLED
11371. BCM_LED_SRC_INTR
11372. BCM_LED_SRC_LINKSPD1
11373. BCM_LED_SRC_LINKSPD2
11374. BCM_LED_SRC_MULTICOLOR1
11375. BCM_LED_SRC_OFF
11376. BCM_LED_SRC_ON
11377. BCM_LED_SRC_OPENSHORT
11378. BCM_LED_SRC_QUALITY
11379. BCM_LED_SRC_RCVLED
11380. BCM_LED_SRC_SLAVE
11381. BCM_LED_SRC_WIRESPEED
11382. BCM_LED_SRC_XMITLED
11383. BCM_LM_DIAG_PKT
11384. BCM_LM_DIAG_SIZE
11385. BCM_MAC_ADDR_OFFSET
11386. BCM_NO_ANEG_APD_EN
11387. BCM_NS2_GENPLL_SCR
11388. BCM_NS2_GENPLL_SCR_AUDIO_CLK
11389. BCM_NS2_GENPLL_SCR_CH3_UNUSED
11390. BCM_NS2_GENPLL_SCR_CH4_UNUSED
11391. BCM_NS2_GENPLL_SCR_CH5_UNUSED
11392. BCM_NS2_GENPLL_SCR_FS_CLK
11393. BCM_NS2_GENPLL_SCR_SCR_CLK
11394. BCM_NS2_GENPLL_SW
11395. BCM_NS2_GENPLL_SW_250_CLK
11396. BCM_NS2_GENPLL_SW_CHIMP_CLK
11397. BCM_NS2_GENPLL_SW_NIC_CLK
11398. BCM_NS2_GENPLL_SW_PORT_CLK
11399. BCM_NS2_GENPLL_SW_RPE_CLK
11400. BCM_NS2_GENPLL_SW_SDIO_CLK
11401. BCM_NS2_GICV2M_MSI_IIDR
11402. BCM_NS2_LCPLL_DDR
11403. BCM_NS2_LCPLL_DDR_CH2_UNUSED
11404. BCM_NS2_LCPLL_DDR_CH3_UNUSED
11405. BCM_NS2_LCPLL_DDR_CH4_UNUSED
11406. BCM_NS2_LCPLL_DDR_CH5_UNUSED
11407. BCM_NS2_LCPLL_DDR_DDR_CLK
11408. BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
11409. BCM_NS2_LCPLL_PORTS
11410. BCM_NS2_LCPLL_PORTS_CH2_UNUSED
11411. BCM_NS2_LCPLL_PORTS_CH3_UNUSED
11412. BCM_NS2_LCPLL_PORTS_CH4_UNUSED
11413. BCM_NS2_LCPLL_PORTS_CH5_UNUSED
11414. BCM_NS2_LCPLL_PORTS_RGMII_CLK
11415. BCM_NS2_LCPLL_PORTS_WAN_CLK
11416. BCM_NSP_GENPLL
11417. BCM_NSP_GENPLL_ENET_SW_CLK
11418. BCM_NSP_GENPLL_IPROCFAST_CLK
11419. BCM_NSP_GENPLL_PHY_CLK
11420. BCM_NSP_GENPLL_SATA1_CLK
11421. BCM_NSP_GENPLL_SATA2_CLK
11422. BCM_NSP_GENPLL_USB_PHY_REF_CLK
11423. BCM_NSP_LCPLL0
11424. BCM_NSP_LCPLL0_DDR_PHY_CLK
11425. BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
11426. BCM_NSP_LCPLL0_SDIO_CLK
11427. BCM_NS_AX
11428. BCM_NS_BX
11429. BCM_NS_UNKNOWN
11430. BCM_NS_USB3_LFPS_CMP
11431. BCM_NS_USB3_LFPS_DEGLITCH
11432. BCM_NS_USB3_MII_MNG_TIMEOUT_US
11433. BCM_NS_USB3_PHY_BASE_ADDR_REG
11434. BCM_NS_USB3_PHY_PIPE_BLOCK
11435. BCM_NS_USB3_PHY_PLL30_BLOCK
11436. BCM_NS_USB3_PHY_TX_PMD_BLOCK
11437. BCM_NS_USB3_PLLA_CONTROL0
11438. BCM_NS_USB3_PLLA_CONTROL1
11439. BCM_NS_USB3_PLL_CONTROL
11440. BCM_NS_USB3_TX_PMD_CONTROL1
11441. BCM_NULL_PKT
11442. BCM_NULL_SIZE
11443. BCM_NUM_SUPPLIES
11444. BCM_PAGE_ALIGN
11445. BCM_PAGE_MASK
11446. BCM_PAGE_SHIFT
11447. BCM_PAGE_SIZE
11448. BCM_PCIE_MEM_BASE_PA
11449. BCM_PCIE_MEM_END_PA
11450. BCM_PCIE_MEM_SIZE
11451. BCM_PCI_IO_BASE_PA
11452. BCM_PCI_IO_END_PA
11453. BCM_PCI_IO_HALF_PA
11454. BCM_PCI_IO_SIZE
11455. BCM_PCI_MEM_BASE_PA
11456. BCM_PCI_MEM_END_PA
11457. BCM_PCI_MEM_SIZE
11458. BCM_PCMCIA_ATTR_BASE_PA
11459. BCM_PCMCIA_ATTR_END_PA
11460. BCM_PCMCIA_ATTR_SIZE
11461. BCM_PCMCIA_COMMON_BASE_PA
11462. BCM_PCMCIA_COMMON_END_PA
11463. BCM_PCMCIA_COMMON_SIZE
11464. BCM_PCMCIA_IO_BASE_PA
11465. BCM_PCMCIA_IO_END_PA
11466. BCM_PCMCIA_IO_SIZE
11467. BCM_RECV_LM_DIAG
11468. BCM_RECV_NULL
11469. BCM_RECV_TYPE49
11470. BCM_RECV_TYPE52
11471. BCM_REGS_VA
11472. BCM_SF2_REGS_NAME
11473. BCM_SF2_REGS_NUM
11474. BCM_SPD_100K
11475. BCM_SPD_1MHZ
11476. BCM_SPD_3P4MHZ
11477. BCM_SPD_400K
11478. BCM_SR_EMEMPLL0
11479. BCM_SR_EMEMPLL0_EMEM_CLK
11480. BCM_SR_EMEMPLL1
11481. BCM_SR_EMEMPLL1_EMEM_CLK
11482. BCM_SR_EMEMPLL2
11483. BCM_SR_EMEMPLL2_EMEM_CLK
11484. BCM_SR_GENPLL0
11485. BCM_SR_GENPLL0_125M_CLK
11486. BCM_SR_GENPLL0_250M_CLK
11487. BCM_SR_GENPLL0_PAXC_AXI_CLK
11488. BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
11489. BCM_SR_GENPLL0_PCIE_AXI_CLK
11490. BCM_SR_GENPLL0_SCR_CLK
11491. BCM_SR_GENPLL1
11492. BCM_SR_GENPLL1_MHB_APB_CLK
11493. BCM_SR_GENPLL1_PCIE_TL_CLK
11494. BCM_SR_GENPLL2
11495. BCM_SR_GENPLL2_125_NITRO_CLK
11496. BCM_SR_GENPLL2_CHIMP_CLK
11497. BCM_SR_GENPLL2_FS4_CLK
11498. BCM_SR_GENPLL2_NIC_CLK
11499. BCM_SR_GENPLL2_NIC_FLASH_CLK
11500. BCM_SR_GENPLL2_TS_500_CLK
11501. BCM_SR_GENPLL3
11502. BCM_SR_GENPLL3_HSLS_CLK
11503. BCM_SR_GENPLL3_SDIO_CLK
11504. BCM_SR_GENPLL4
11505. BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
11506. BCM_SR_GENPLL4_CCN_CLK
11507. BCM_SR_GENPLL4_CHCLK_FS4_CLK
11508. BCM_SR_GENPLL4_NOC_CLK
11509. BCM_SR_GENPLL4_TPIU_PLL_CLK
11510. BCM_SR_GENPLL5
11511. BCM_SR_GENPLL5_CRYPTO_AE_CLK
11512. BCM_SR_GENPLL5_FS4_HF_CLK
11513. BCM_SR_GENPLL5_RAID_AE_CLK
11514. BCM_SR_GENPLL6
11515. BCM_SR_GENPLL6_48_USB_CLK
11516. BCM_SR_LCPLL0
11517. BCM_SR_LCPLL0_SATA_350_CLK
11518. BCM_SR_LCPLL0_SATA_500_CLK
11519. BCM_SR_LCPLL0_SATA_REFN_CLK
11520. BCM_SR_LCPLL0_SATA_REFP_CLK
11521. BCM_SR_LCPLL1
11522. BCM_SR_LCPLL1_CRMU_TS_CLK
11523. BCM_SR_LCPLL1_USB_REF_CLK
11524. BCM_SR_LCPLL1_WAN_CLK
11525. BCM_SR_LCPLL_PCIE
11526. BCM_SR_LCPLL_PCIE_PHY_REF_CLK
11527. BCM_SR_USB_COMBO_PHY
11528. BCM_SR_USB_HS_PHY
11529. BCM_SYSPORT_INTR_L2
11530. BCM_SYSPORT_IO_MACRO
11531. BCM_SYSPORT_STATS_LEN
11532. BCM_SYSPORT_STAT_MIB_RX
11533. BCM_SYSPORT_STAT_MIB_TX
11534. BCM_SYSPORT_STAT_NETDEV
11535. BCM_SYSPORT_STAT_NETDEV64
11536. BCM_SYSPORT_STAT_RBUF
11537. BCM_SYSPORT_STAT_RUNT
11538. BCM_SYSPORT_STAT_RXCHK
11539. BCM_SYSPORT_STAT_SOFT
11540. BCM_SYS_EMI_OFFSET
11541. BCM_SYS_EMI_START_ADDR
11542. BCM_TCS_CMD
11543. BCM_TCS_CMD_COMMIT_MASK
11544. BCM_TCS_CMD_COMMIT_SHFT
11545. BCM_TCS_CMD_VALID_MASK
11546. BCM_TCS_CMD_VALID_SHFT
11547. BCM_TCS_CMD_VOTE_MASK
11548. BCM_TCS_CMD_VOTE_X_SHFT
11549. BCM_TCS_CMD_VOTE_Y_MASK
11550. BCM_TCS_CMD_VOTE_Y_SHFT
11551. BCM_TIMER_SEC_MAX
11552. BCM_TYPE49_PKT
11553. BCM_TYPE49_SIZE
11554. BCM_TYPE52_PKT
11555. BCM_TYPE52_SIZE
11556. BCM_UART_CLOCK_24MHZ
11557. BCM_UART_CLOCK_48MHZ
11558. BCM_VC_EMI_OFFSET
11559. BCM_VC_EMI_SEC3_START_ADDR
11560. BCM_VLAN
11561. BCNCSR
11562. BCNCSR1
11563. BCNCSR1_BEACON_CWMIN
11564. BCNCSR1_PRELOAD
11565. BCNCSR_CHANGE
11566. BCNCSR_DELTATIME
11567. BCNCSR_MODE
11568. BCNCSR_NUM_BEACON
11569. BCNCSR_PLUS
11570. BCNDMATIM
11571. BCNERRTH
11572. BCNITV
11573. BCNQ1_PAGE_NUM_8723B
11574. BCNQ_CTRL
11575. BCNQ_PAGE_NUM_8723B
11576. BCNTCFG
11577. BCNUM
11578. BCN_DMATIME
11579. BCN_DMA_ATIME_INT_TIME
11580. BCN_DMA_ATIME_INT_TIME_8723B
11581. BCN_DRV_EARLY_INT
11582. BCN_DRV_EARLY_INT_SWBCN_SHIFT
11583. BCN_DRV_EARLY_INT_TIME_SHIFT
11584. BCN_ERR_THRESH
11585. BCN_FILTER
11586. BCN_FLT_MAX_ELEMS_IE_LIST
11587. BCN_FLT_MAX_SUPPORTED_IES
11588. BCN_HEAD
11589. BCN_HEAD_MASK
11590. BCN_IE_FLT_DELTA
11591. BCN_INTERVAL
11592. BCN_MISS_OFFLOAD
11593. BCN_MODE_AP
11594. BCN_MODE_IBSS
11595. BCN_OFFSET0
11596. BCN_OFFSET0_BCN0
11597. BCN_OFFSET0_BCN1
11598. BCN_OFFSET0_BCN2
11599. BCN_OFFSET0_BCN3
11600. BCN_OFFSET1
11601. BCN_OFFSET1_BCN4
11602. BCN_OFFSET1_BCN5
11603. BCN_OFFSET1_BCN6
11604. BCN_OFFSET1_BCN7
11605. BCN_QID
11606. BCN_QUEUE_INX
11607. BCN_RX_TIMEOUT_DEF_VALUE
11608. BCN_TBTT_OFFSET
11609. BCN_TCFG
11610. BCN_TCFG_CW_SHIFT
11611. BCN_TCFG_IFS
11612. BCN_TIME_CFG
11613. BCN_TIME_CFG_BEACON_GEN
11614. BCN_TIME_CFG_BEACON_INTERVAL
11615. BCN_TIME_CFG_TBTT_ENABLE
11616. BCN_TIME_CFG_TSF_SYNC
11617. BCN_TIME_CFG_TSF_TICKING
11618. BCN_TIME_CFG_TX_TIME_COMPENSATE
11619. BCN_TMPL_LEN
11620. BCN_TX_ESTIMATE_TIME
11621. BCN_VALID
11622. BCOM_ATA_PRAGMA
11623. BCOM_BD_READY
11624. BCOM_CH_CFO
11625. BCOM_CRC16_DP_0_PRAGMA
11626. BCOM_CRC16_DP_1_PRAGMA
11627. BCOM_CTX_ALIGN
11628. BCOM_CTX_SIZE
11629. BCOM_DESC_NOP
11630. BCOM_DRD_EXTENDED
11631. BCOM_DRD_INITIATOR_SHIFT
11632. BCOM_FDT_ALIGN
11633. BCOM_FDT_SIZE
11634. BCOM_FEC_RX_BD_BC
11635. BCOM_FEC_RX_BD_CR
11636. BCOM_FEC_RX_BD_ERRORS
11637. BCOM_FEC_RX_BD_L
11638. BCOM_FEC_RX_BD_LEN_MASK
11639. BCOM_FEC_RX_BD_LG
11640. BCOM_FEC_RX_BD_MC
11641. BCOM_FEC_RX_BD_NO
11642. BCOM_FEC_RX_BD_OV
11643. BCOM_FEC_RX_BD_PRAGMA
11644. BCOM_FEC_RX_BD_TR
11645. BCOM_FEC_TX_BD_ABC
11646. BCOM_FEC_TX_BD_PRAGMA
11647. BCOM_FEC_TX_BD_TC
11648. BCOM_FEC_TX_BD_TFD
11649. BCOM_FLAGS_ENABLE_TASK
11650. BCOM_FLAGS_NONE
11651. BCOM_GEN_DP_0_PRAGMA
11652. BCOM_GEN_DP_1_PRAGMA
11653. BCOM_GEN_DP_2_PRAGMA
11654. BCOM_GEN_DP_3_PRAGMA
11655. BCOM_GEN_DP_BD_0_PRAGMA
11656. BCOM_GEN_DP_BD_1_PRAGMA
11657. BCOM_GEN_LPC_PRAGMA
11658. BCOM_GEN_RX_BD_PRAGMA
11659. BCOM_GEN_TX_BD_PRAGMA
11660. BCOM_INC_SIZE
11661. BCOM_INITIATOR_ALWAYS
11662. BCOM_INITIATOR_ATA_RX
11663. BCOM_INITIATOR_ATA_TX
11664. BCOM_INITIATOR_FEC_RX
11665. BCOM_INITIATOR_FEC_TX
11666. BCOM_INITIATOR_I2C1_RX
11667. BCOM_INITIATOR_I2C1_TX
11668. BCOM_INITIATOR_I2C2_RX
11669. BCOM_INITIATOR_I2C2_TX
11670. BCOM_INITIATOR_IRDA_RX
11671. BCOM_INITIATOR_IRDA_TX
11672. BCOM_INITIATOR_PSC1_RX
11673. BCOM_INITIATOR_PSC1_TX
11674. BCOM_INITIATOR_PSC2_RX
11675. BCOM_INITIATOR_PSC2_TX
11676. BCOM_INITIATOR_PSC3_RX
11677. BCOM_INITIATOR_PSC3_TX
11678. BCOM_INITIATOR_PSC4_RX
11679. BCOM_INITIATOR_PSC4_TX
11680. BCOM_INITIATOR_PSC5_RX
11681. BCOM_INITIATOR_PSC5_TX
11682. BCOM_INITIATOR_PSC6_RX
11683. BCOM_INITIATOR_PSC6_TX
11684. BCOM_INITIATOR_SCLPC
11685. BCOM_INITIATOR_SCPCI_RX
11686. BCOM_INITIATOR_SCPCI_TX
11687. BCOM_INITIATOR_SCTMR_0
11688. BCOM_INITIATOR_SCTMR_1
11689. BCOM_INITIATOR_SCTMR_2
11690. BCOM_INITIATOR_SCTMR_3
11691. BCOM_INITIATOR_SCTMR_4
11692. BCOM_INITIATOR_SCTMR_5
11693. BCOM_INITIATOR_SCTMR_6
11694. BCOM_INITIATOR_SCTMR_7
11695. BCOM_IPR_ALWAYS
11696. BCOM_IPR_ATA_RX
11697. BCOM_IPR_ATA_TX
11698. BCOM_IPR_FEC_RX
11699. BCOM_IPR_FEC_TX
11700. BCOM_IPR_I2C1_RX
11701. BCOM_IPR_I2C1_TX
11702. BCOM_IPR_I2C2_RX
11703. BCOM_IPR_I2C2_TX
11704. BCOM_IPR_IRDA_RX
11705. BCOM_IPR_IRDA_TX
11706. BCOM_IPR_PSC1_RX
11707. BCOM_IPR_PSC1_TX
11708. BCOM_IPR_PSC2_RX
11709. BCOM_IPR_PSC2_TX
11710. BCOM_IPR_PSC3_RX
11711. BCOM_IPR_PSC3_TX
11712. BCOM_IPR_PSC4_RX
11713. BCOM_IPR_PSC4_TX
11714. BCOM_IPR_PSC5_RX
11715. BCOM_IPR_PSC5_TX
11716. BCOM_IPR_PSC6_RX
11717. BCOM_IPR_PSC6_TX
11718. BCOM_IPR_SCLPC
11719. BCOM_IPR_SCPCI_RX
11720. BCOM_IPR_SCPCI_TX
11721. BCOM_IPR_SCTMR_0
11722. BCOM_IPR_SCTMR_1
11723. BCOM_IPR_SCTMR_2
11724. BCOM_IPR_SCTMR_3
11725. BCOM_IPR_SCTMR_4
11726. BCOM_IPR_SCTMR_5
11727. BCOM_IPR_SCTMR_6
11728. BCOM_IPR_SCTMR_7
11729. BCOM_LCD_MASK
11730. BCOM_MAX_CTX
11731. BCOM_MAX_FDT
11732. BCOM_MAX_INC
11733. BCOM_MAX_TASKS
11734. BCOM_MAX_VAR
11735. BCOM_PCI_PRAGMA
11736. BCOM_PCI_RX_PRAGMA
11737. BCOM_PCI_TX_PRAGMA
11738. BCOM_PRAGMA_BIT_CW
11739. BCOM_PRAGMA_BIT_INTEGER
11740. BCOM_PRAGMA_BIT_PACK
11741. BCOM_PRAGMA_BIT_PRECISE_INC
11742. BCOM_PRAGMA_BIT_RL
11743. BCOM_PRAGMA_BIT_RST_ERROR_NO
11744. BCOM_PRAGMA_BIT_RSV
11745. BCOM_PRAGMA_BIT_SPECREAD
11746. BCOM_STD_PRAGMA
11747. BCOM_TASK_MAGIC
11748. BCOM_VAR_ALIGN
11749. BCOM_VAR_SIZE
11750. BCONTXHSSI
11751. BCOUNTERRESET
11752. BCOUNTER_CCA
11753. BCOUNTER_CRC8FAIL
11754. BCOUNTER_FASTSYNC
11755. BCOUNTER_MCSNOSUPPORT
11756. BCOUNTER_PARITYFAIL
11757. BCOUNTER_RATEILLEGAL
11758. BCOVE_ADCIRQ
11759. BCOVE_ADCIRQ_BATTEMP
11760. BCOVE_ADCIRQ_BATTID
11761. BCOVE_ADCIRQ_CCTICK
11762. BCOVE_ADCIRQ_SYSTEMP
11763. BCOVE_ADCIRQ_VIBATT
11764. BCOVE_BCUIRQ
11765. BCOVE_CHGRCTRL0
11766. BCOVE_CHGRCTRL0_BIT_5
11767. BCOVE_CHGRCTRL0_BIT_6
11768. BCOVE_CHGRCTRL0_CHGRRESET
11769. BCOVE_CHGRCTRL0_CHR_WDT_NOKICK
11770. BCOVE_CHGRCTRL0_EMRGCHREN
11771. BCOVE_CHGRCTRL0_EXTCHRDIS
11772. BCOVE_CHGRCTRL0_SWCONTROL
11773. BCOVE_CHGRCTRL0_TTLCK
11774. BCOVE_CHGRIRQ0
11775. BCOVE_CHGRIRQ1
11776. BCOVE_CHGRIRQ_ALL
11777. BCOVE_CHGRIRQ_BAT0ALRT
11778. BCOVE_CHGRIRQ_BAT1ALRT
11779. BCOVE_CHGRIRQ_BATCRIT
11780. BCOVE_CHGRIRQ_BATTDET
11781. BCOVE_CHGRIRQ_DCDET
11782. BCOVE_CHGRIRQ_USBIDDET
11783. BCOVE_CHGRIRQ_VBUSDET
11784. BCOVE_CRITIRQ
11785. BCOVE_GPIOIRQ
11786. BCOVE_ID
11787. BCOVE_ID_MAJREV0
11788. BCOVE_ID_MINREV0
11789. BCOVE_ID_VENDID0
11790. BCOVE_IRQLVL1
11791. BCOVE_IRQLVL1MSK
11792. BCOVE_LVL1_ADC
11793. BCOVE_LVL1_BCU
11794. BCOVE_LVL1_CHGR
11795. BCOVE_LVL1_CRIT
11796. BCOVE_LVL1_GPIO
11797. BCOVE_LVL1_PWRBTN
11798. BCOVE_LVL1_THRM
11799. BCOVE_LVL1_TMU
11800. BCOVE_MADCIRQ
11801. BCOVE_MAJOR
11802. BCOVE_MBCUIRQ
11803. BCOVE_MCHGRIRQ0
11804. BCOVE_MCHGRIRQ1
11805. BCOVE_MCRITIRQ
11806. BCOVE_MGPIOIRQ
11807. BCOVE_MINOR
11808. BCOVE_MIRQLVL1
11809. BCOVE_MPBIRQ
11810. BCOVE_MTHRMIRQ
11811. BCOVE_MTMUIRQ
11812. BCOVE_PBIRQ
11813. BCOVE_PBIRQMASK
11814. BCOVE_PBIRQ_PBTN
11815. BCOVE_PBIRQ_UBTN
11816. BCOVE_PBSTATUS
11817. BCOVE_PBSTATUS_PBLVL
11818. BCOVE_PB_LEVEL
11819. BCOVE_SCHGRIRQ0
11820. BCOVE_SCHGRIRQ1
11821. BCOVE_THRMIRQ
11822. BCOVE_TMUIRQ
11823. BCOVE_USBIDCTRL
11824. BCOVE_USBIDCTRL_ACA
11825. BCOVE_USBIDCTRL_ALL
11826. BCOVE_USBIDCTRL_ID
11827. BCOVE_USBIDSTS
11828. BCOVE_USBIDSTS_FLOAT
11829. BCOVE_USBIDSTS_GND
11830. BCOVE_USBIDSTS_NO_ACA
11831. BCOVE_USBIDSTS_RARBRC_MASK
11832. BCOVE_USBIDSTS_RARBRC_SHIFT
11833. BCOVE_USBIDSTS_R_ID_A
11834. BCOVE_USBIDSTS_R_ID_B
11835. BCOVE_USBIDSTS_R_ID_C
11836. BCOVE_USBIDSTS_SHORT
11837. BCOVE_VENDOR
11838. BCR
11839. BCR1_CTFT0
11840. BCR1_CTFT1
11841. BCR1_CTSF
11842. BCR1_MED0
11843. BCR1_MED1
11844. BCR1_POT0
11845. BCR1_POT1
11846. BCR1_POT2
11847. BCR1_TXQNOBK
11848. BCR1_VIDFR
11849. BCR2
11850. BCRC32DEBUG
11851. BCRH
11852. BCRL
11853. BCR_DEFAULT
11854. BCR_ILCRA
11855. BCR_ILCRB
11856. BCR_ILCRC
11857. BCR_ILCRD
11858. BCR_ILCRE
11859. BCR_ILCRF
11860. BCR_ILCRG
11861. BCR_P2V
11862. BCR_V2P
11863. BCR_WPD
11864. BCR_writew
11865. BCS0
11866. BCS0_HW
11867. BCSI1ST
11868. BCSI2ND
11869. BCSI_ESTI_MODE
11870. BCSI_SCHEME
11871. BCSP_ACK_PKT
11872. BCSP_CRC_INIT
11873. BCSP_ESCSTATE_ESC
11874. BCSP_ESCSTATE_NOESC
11875. BCSP_LE_PKT
11876. BCSP_TXWINSIZE
11877. BCSP_W4_BCSP_HDR
11878. BCSP_W4_CRC
11879. BCSP_W4_DATA
11880. BCSP_W4_PKT_DELIMITER
11881. BCSP_W4_PKT_START
11882. BCSR0_LED0
11883. BCSR0_LED1
11884. BCSR11_ENET_MICRST
11885. BCSR12_USB_SER_DEVICE
11886. BCSR12_USB_SER_MASK
11887. BCSR12_USB_SER_PIN
11888. BCSR13_USBMASK
11889. BCSR13_USBMODE
11890. BCSR13_USBSPEED
11891. BCSR13_nUSBEN
11892. BCSR13_nUSBVCC
11893. BCSR15_I2C_BUS0_SEG2
11894. BCSR15_I2C_BUS0_SEG_CLR
11895. BCSR1_ETHEN
11896. BCSR1_FETHIEN
11897. BCSR1_FETH_RST
11898. BCSR1_IRDAEN
11899. BCSR1_PCCEN
11900. BCSR1_PCCVCC0
11901. BCSR1_PCCVCC1
11902. BCSR1_PCCVCC_MASK
11903. BCSR1_PCCVPP0
11904. BCSR1_PCCVPP1
11905. BCSR1_PCCVPP_MASK
11906. BCSR1_RS232EN_1
11907. BCSR1_RS232EN_2
11908. BCSR1_RS232_EN1
11909. BCSR1_RS232_EN2
11910. BCSR3_FETH2_RST
11911. BCSR3_FETHIEN2
11912. BCSR3_USB_nEN
11913. BCSR4_ETH10_RST
11914. BCSR4_USB_EN
11915. BCSR4_USB_FULL_SPD
11916. BCSR4_USB_LO_SPD
11917. BCSR4_USB_VCC
11918. BCSR5_ATM155_RST
11919. BCSR5_ATM25_RST
11920. BCSR5_INT_USB
11921. BCSR5_MII1_EN
11922. BCSR5_MII1_RST
11923. BCSR5_MII2_EN
11924. BCSR5_MII2_RST
11925. BCSR5_T1_RST
11926. BCSR7_SCC2_ENABLE
11927. BCSR7_UCC12_GETHnRST
11928. BCSR8_FETH_RST
11929. BCSR8_MDIO_CLOCK
11930. BCSR8_MDIO_DATA
11931. BCSR8_MDIO_READ
11932. BCSR8_PHY1_ENABLE
11933. BCSR8_PHY1_POWER
11934. BCSR8_PHY2_ENABLE
11935. BCSR8_PHY2_POWER
11936. BCSR8_TSEC1M_MASK
11937. BCSR8_TSEC1M_RGMII
11938. BCSR8_TSEC2M_MASK
11939. BCSR8_TSEC2M_RGMII
11940. BCSR8_UEM_MARVELL_RST
11941. BCSR9_GETHRST
11942. BCSR9_USB_ENABLE
11943. BCSR9_USB_FULL_SPEED_TARGET
11944. BCSR9_USB_HOST
11945. BCSR9_USB_POWER
11946. BCSR_BOARD
11947. BCSR_BOARD_CAMCS
11948. BCSR_BOARD_CAMPWR
11949. BCSR_BOARD_CAMSNAP
11950. BCSR_BOARD_GPIO200RST
11951. BCSR_BOARD_HDMI_DE
11952. BCSR_BOARD_LCDBL
11953. BCSR_BOARD_LCDVDD
11954. BCSR_BOARD_LCDVEE
11955. BCSR_BOARD_PB1100_SD0PWR
11956. BCSR_BOARD_PB1100_SD1PWR
11957. BCSR_BOARD_PCICFG
11958. BCSR_BOARD_PCICLKOUT
11959. BCSR_BOARD_PCIEXTARB
11960. BCSR_BOARD_PCIM33
11961. BCSR_BOARD_PCIM66EN
11962. BCSR_BOARD_SD0PWR
11963. BCSR_BOARD_SD0WP
11964. BCSR_BOARD_SD1PWR
11965. BCSR_BOARD_SD1WP
11966. BCSR_BOARD_SPISEL
11967. BCSR_CNT
11968. BCSR_FENET_UART_CTRL
11969. BCSR_FLASH_NV_POR_CTRL
11970. BCSR_GPIO_IRQ_PAR_CTRL
11971. BCSR_HEXCLEAR
11972. BCSR_HEXLEDS
11973. BCSR_ID
11974. BCSR_INTCLR
11975. BCSR_INTSET
11976. BCSR_INTSTAT
11977. BCSR_INT_DC
11978. BCSR_INT_ETH
11979. BCSR_INT_FLASHBUSY
11980. BCSR_INT_IDE
11981. BCSR_INT_PC0
11982. BCSR_INT_PC0EJECT
11983. BCSR_INT_PC0INSERT
11984. BCSR_INT_PC0STSCHG
11985. BCSR_INT_PC1
11986. BCSR_INT_PC1EJECT
11987. BCSR_INT_PC1INSERT
11988. BCSR_INT_PC1STSCHG
11989. BCSR_INT_SD0EJECT
11990. BCSR_INT_SD0INSERT
11991. BCSR_INT_SD1EJECT
11992. BCSR_INT_SD1INSERT
11993. BCSR_LEDS
11994. BCSR_LEDS_DECIMALS
11995. BCSR_LEDS_LED0
11996. BCSR_LEDS_LED1
11997. BCSR_LEDS_LED2
11998. BCSR_LEDS_LED3
11999. BCSR_MASKCLR
12000. BCSR_MASKSET
12001. BCSR_PCI_CTRL
12002. BCSR_PCI_IRQ
12003. BCSR_PCMCIA
12004. BCSR_PCMCIA_PC0DRVEN
12005. BCSR_PCMCIA_PC0RST
12006. BCSR_PCMCIA_PC0VCC
12007. BCSR_PCMCIA_PC0VPP
12008. BCSR_PCMCIA_PC1DRVEN
12009. BCSR_PCMCIA_PC1RST
12010. BCSR_PCMCIA_PC1VCC
12011. BCSR_PCMCIA_PC1VPP
12012. BCSR_REG_BOARD
12013. BCSR_REG_HEXCLEAR
12014. BCSR_REG_HEXLEDS
12015. BCSR_REG_INTCLR
12016. BCSR_REG_INTSET
12017. BCSR_REG_INTSTAT
12018. BCSR_REG_LEDS
12019. BCSR_REG_MASKCLR
12020. BCSR_REG_MASKSET
12021. BCSR_REG_PCMCIA
12022. BCSR_REG_RESETS
12023. BCSR_REG_SIGSTAT
12024. BCSR_REG_STATUS
12025. BCSR_REG_SWITCHES
12026. BCSR_REG_SYSTEM
12027. BCSR_REG_WHOAMI
12028. BCSR_RESETS
12029. BCSR_RESETS_CAMERA
12030. BCSR_RESETS_DC
12031. BCSR_RESETS_DMAREQ
12032. BCSR_RESETS_ETH
12033. BCSR_RESETS_FIR_SEL
12034. BCSR_RESETS_IDE
12035. BCSR_RESETS_IRDA_MODE_1_3
12036. BCSR_RESETS_IRDA_MODE_2_3
12037. BCSR_RESETS_IRDA_MODE_FULL
12038. BCSR_RESETS_IRDA_MODE_MASK
12039. BCSR_RESETS_IRDA_MODE_OFF
12040. BCSR_RESETS_OTGPWR
12041. BCSR_RESETS_OTPCSB
12042. BCSR_RESETS_OTPPGM
12043. BCSR_RESETS_OTPSCLK
12044. BCSR_RESETS_OTPWRPROT
12045. BCSR_RESETS_PB1200_WSCFSM
12046. BCSR_RESETS_PB1550_WSCFSM
12047. BCSR_RESETS_PHY0
12048. BCSR_RESETS_PHY1
12049. BCSR_RESETS_PSC0MUX
12050. BCSR_RESETS_PSC1MUX
12051. BCSR_RESETS_PWMR1MUX
12052. BCSR_RESETS_SD1MUX
12053. BCSR_RESETS_SPISEL
12054. BCSR_RESETS_TV
12055. BCSR_RESETS_USBHPWR
12056. BCSR_RESETS_VDDQSHDN
12057. BCSR_RSVD1
12058. BCSR_SIGSTAT
12059. BCSR_STATUS
12060. BCSR_STATUS_CFWP
12061. BCSR_STATUS_DB1000_SWAPBOOT
12062. BCSR_STATUS_DB1200_SWAPBOOT
12063. BCSR_STATUS_DB1200_U0RXD
12064. BCSR_STATUS_DB1200_U1RXD
12065. BCSR_STATUS_DB1550_U0RXD
12066. BCSR_STATUS_DB1550_U3RXD
12067. BCSR_STATUS_DCDMARQ
12068. BCSR_STATUS_FLASHBUSY
12069. BCSR_STATUS_FLASHDEN
12070. BCSR_STATUS_IDECBLID
12071. BCSR_STATUS_IDEDMARQ
12072. BCSR_STATUS_OTGOCn
12073. BCSR_STATUS_PB1550_SWAPBOOT
12074. BCSR_STATUS_PB1550_U0RXD
12075. BCSR_STATUS_PB1550_U1RXD
12076. BCSR_STATUS_PB1550_U3RXD
12077. BCSR_STATUS_PC0FI
12078. BCSR_STATUS_PC0VS
12079. BCSR_STATUS_PC1FI
12080. BCSR_STATUS_PC1VS
12081. BCSR_STATUS_ROMBUSY
12082. BCSR_STATUS_SD0WP
12083. BCSR_STATUS_SD1WP
12084. BCSR_STATUS_SRAMWIDTH
12085. BCSR_STATUS_USBOCn
12086. BCSR_STATUS_USBOTGID
12087. BCSR_SWITCHES
12088. BCSR_SWITCHES_DIP
12089. BCSR_SWITCHES_DIP_1
12090. BCSR_SWITCHES_DIP_2
12091. BCSR_SWITCHES_DIP_3
12092. BCSR_SWITCHES_DIP_4
12093. BCSR_SWITCHES_DIP_5
12094. BCSR_SWITCHES_DIP_6
12095. BCSR_SWITCHES_DIP_7
12096. BCSR_SWITCHES_DIP_8
12097. BCSR_SWITCHES_ROTARY
12098. BCSR_SW_STAT_LED_CTRL
12099. BCSR_SYSTEM
12100. BCSR_SYSTEM_DEBUGCSMASK
12101. BCSR_SYSTEM_PWROFF
12102. BCSR_SYSTEM_RESET
12103. BCSR_SYSTEM_UDMAMODE
12104. BCSR_SYSTEM_VDDI
12105. BCSR_SYSTEM_VDDI1300
12106. BCSR_SYSTEM_WAKEONIRQ
12107. BCSR_UCC1_GETH_EN
12108. BCSR_UCC1_MODE_MSK
12109. BCSR_UCC2_GETH_EN
12110. BCSR_UCC2_MODE_MSK
12111. BCSR_UCC_RGMII
12112. BCSR_UCC_RTBI
12113. BCSR_USB_EN
12114. BCSR_WHOAMI
12115. BCSR_WHOAMI_BOARD
12116. BCSR_WHOAMI_CPLD
12117. BCSR_WHOAMI_DB1000
12118. BCSR_WHOAMI_DB1100
12119. BCSR_WHOAMI_DB1200
12120. BCSR_WHOAMI_DB1300
12121. BCSR_WHOAMI_DB1500
12122. BCSR_WHOAMI_DB1550
12123. BCSR_WHOAMI_DCID
12124. BCSR_WHOAMI_PB1100
12125. BCSR_WHOAMI_PB1200
12126. BCSR_WHOAMI_PB1200_DDR1
12127. BCSR_WHOAMI_PB1200_DDR2
12128. BCSR_WHOAMI_PB1500
12129. BCSR_WHOAMI_PB1500R2
12130. BCSR_WHOAMI_PB1550
12131. BCSR_WHOAMI_PB1550_DDR
12132. BCSR_WHOAMI_PB1550_SDR
12133. BCSR_XIRQ_ROUTING
12134. BCSR_XIRQ_SELECT
12135. BCSR_XIRQ_STATUS
12136. BCSR_XIRQ_STATUS2
12137. BCS_10
12138. BCS_12
12139. BCS_16
12140. BCS_6
12141. BCS_8
12142. BCS_AS_CONTEXT_SWITCH
12143. BCS_CMD_STREAMER_ERR
12144. BCS_CTRL
12145. BCS_GPR
12146. BCS_GPR_UDW
12147. BCS_MI_FLUSH_DW
12148. BCS_MI_USER_INTERRUPT
12149. BCS_MMIO_SYNC_FLUSH
12150. BCS_PAGE_DIRECTORY_FAULT
12151. BCS_SWCTRL
12152. BCT
12153. BCTL
12154. BCTL_ATN
12155. BCTL_BSY
12156. BCTL_BUSEN
12157. BCTL_CMD
12158. BCTL_IO
12159. BCTL_MSG
12160. BCTL_RST
12161. BCTL_SEL
12162. BCT_FORMAT
12163. BCUINTR
12164. BCUINTREG
12165. BCULR
12166. BCU_IRQ
12167. BCW_CMD_SHIFT
12168. BCW_LEN_MASK
12169. BCW_LEN_SHIFT
12170. BCW_OFFSET_MASK
12171. BC_ACQUIRE
12172. BC_ACQUIRE_DONE
12173. BC_ACQUIRE_RESULT
12174. BC_ATTEMPT_ACQUIRE
12175. BC_BCC_UNKNOWN_MSG
12176. BC_BIOS_PRESENT
12177. BC_CLEAR_DEATH_NOTIFICATION
12178. BC_CNTENCLR_RESET
12179. BC_DEAD_BINDER_DONE
12180. BC_DECREFS
12181. BC_ENABLE
12182. BC_ENTER_LOOPER
12183. BC_EXIT_LOOPER
12184. BC_FFP
12185. BC_FILTER_MAGIC_IP
12186. BC_FILTER_MAGIC_MAC
12187. BC_FILTER_MAGIC_NONE
12188. BC_FREE_BUFFER
12189. BC_GANG_RESET
12190. BC_GLOBAL_DBP_TOUT
12191. BC_GLOBAL_DCD_DET_SEL
12192. BC_GLOBAL_DCD_TOUT_100MS
12193. BC_GLOBAL_DCD_TOUT_300MS
12194. BC_GLOBAL_DCD_TOUT_500MS
12195. BC_GLOBAL_DCD_TOUT_900MS
12196. BC_GLOBAL_DCD_TOUT_MASK
12197. BC_GLOBAL_DET_STAT
12198. BC_GLOBAL_RUN
12199. BC_GLOBAL_VLGC_COM_SEL
12200. BC_HT1000_FEATURE_REG
12201. BC_HT1000_MAP_DATA
12202. BC_HT1000_MAP_IDX
12203. BC_HT1000_PIC_REGS_ENABLE
12204. BC_HWRM_STR_LEN
12205. BC_IDLE_UNKNOWN_MSG
12206. BC_IMPLEMENTED
12207. BC_INCREFS
12208. BC_INCREFS_DONE
12209. BC_INTENCLR_RESET
12210. BC_IRQCTL_RESET
12211. BC_LOWER_PORT
12212. BC_MAX_SLOTS
12213. BC_NACK_SND_CONDITIONAL
12214. BC_NACK_SND_SUPPRESS
12215. BC_NACK_SND_UNCONDITIONAL
12216. BC_PORT_MASK
12217. BC_PWR_MGM_MSG
12218. BC_REGISTER_LOOPER
12219. BC_RELEASE
12220. BC_REPLY
12221. BC_REPLY_SG
12222. BC_REQUEST_DEATH_NOTIFICATION
12223. BC_RESET
12224. BC_SATROLL_CR_RESET
12225. BC_SMA_MSG
12226. BC_SUPPORTS_DCBX_MSG_NON_PMF
12227. BC_SUPPORTS_FCOE_FEATURES
12228. BC_SUPPORTS_PFC_STATS
12229. BC_SUPPORTS_RMMOD_CMD
12230. BC_TEST_OFF
12231. BC_TEST_ON
12232. BC_THRESH_ENB
12233. BC_TRANSACTION
12234. BC_TRANSACTION_SG
12235. BC_UNIMPLEMENTED
12236. BC_UNKNOWN
12237. BC_USB_CHNG_IRQ
12238. BC_WRITE
12239. BD
12240. BD15
12241. BD15_MASK
12242. BD24
12243. BD24_MASK
12244. BD2802_BLINK
12245. BD2802_COLOR_OFFSET
12246. BD2802_CONTROL_ATTR
12247. BD2802_CONTROL_RGBS
12248. BD2802_CURRENT_000
12249. BD2802_CURRENT_032
12250. BD2802_LED_OFFSET
12251. BD2802_OFF
12252. BD2802_ON
12253. BD2802_PATTERN_FULL
12254. BD2802_PATTERN_HALF
12255. BD2802_REG_CLKSETUP
12256. BD2802_REG_CONTROL
12257. BD2802_REG_CURRENT1SETUP
12258. BD2802_REG_CURRENT2SETUP
12259. BD2802_REG_HOURSETUP
12260. BD2802_REG_WAVEPATTERN
12261. BD2802_SET_REGISTER
12262. BD28623_NUM_SUPPLIES
12263. BD50
12264. BD50_50HZ_BANDING_AEC_LSBS_SET
12265. BD50_MAX_AEC_STEP_MASK
12266. BD50_MAX_AEC_STEP_SET
12267. BD60
12268. BD60_60HZ_BANDING_AEC_LSBS_SET
12269. BD60_MAX_AEC_STEP_MASK
12270. BD60_MAX_AEC_STEP_SET
12271. BD6107_CLRFACT1
12272. BD6107_CLRFACT2
12273. BD6107_DCDCCNT
12274. BD6107_FACTOR1
12275. BD6107_FACTOR2
12276. BD6107_GRPSEL
12277. BD6107_IOSEL
12278. BD6107_LEDCNT1
12279. BD6107_LEDCNT1_LEDONOFF1
12280. BD6107_LEDCNT1_LEDONOFF2
12281. BD6107_LEDCNT2
12282. BD6107_LEDCNT3
12283. BD6107_LSIVER
12284. BD6107_MAINCNT1
12285. BD6107_MAINCNT2
12286. BD6107_MASK1
12287. BD6107_MASK2
12288. BD6107_MCURRENT
12289. BD6107_MSLOPE
12290. BD6107_OUT1
12291. BD6107_OUT2
12292. BD6107_PORTSEL
12293. BD6107_PORTSEL_LEDM
12294. BD6107_PSCNT1
12295. BD6107_PSCNT1_PSCNTREG1
12296. BD6107_PSCNT1_PSCNTREG2
12297. BD6107_PSCONT3
12298. BD6107_REGVSET
12299. BD6107_REGVSET_REG1VSET_2_80V
12300. BD6107_REGVSET_REG1VSET_2_85V
12301. BD6107_RGB1CNT1
12302. BD6107_RGB1CNT2
12303. BD6107_RGB1CNT3
12304. BD6107_RGB1CNT4
12305. BD6107_RGB1CNT5
12306. BD6107_RGB1FLM
12307. BD6107_RGB2CNT1
12308. BD6107_RGB2CNT2
12309. BD6107_RGB2CNT3
12310. BD6107_RGB2CNT4
12311. BD6107_RGB2CNT5
12312. BD6107_RGB2FLM
12313. BD6107_RGBSLOPE
12314. BD6107_SFTRST
12315. BD6107_SFTRSTGD
12316. BD6107_SLOPECNT
12317. BD6107_SMMONCNT
12318. BD6107_STATE1
12319. BD6107_TEST
12320. BD70528_BUCK1
12321. BD70528_BUCK2
12322. BD70528_BUCK3
12323. BD70528_BUCK_VOLTS
12324. BD70528_CLK_OUT_EN_MASK
12325. BD70528_DEBOUNCE_15MS
12326. BD70528_DEBOUNCE_30MS
12327. BD70528_DEBOUNCE_50MS
12328. BD70528_DEBOUNCE_DISABLE
12329. BD70528_DEBOUNCE_MASK
12330. BD70528_ELAPSED_STATE_BIT
12331. BD70528_GPIO_DRIVE_MASK
12332. BD70528_GPIO_IN_STATE_BASE
12333. BD70528_GPIO_OPEN_DRAIN
12334. BD70528_GPIO_OUT_DISABLE
12335. BD70528_GPIO_OUT_ENABLE
12336. BD70528_GPIO_OUT_EN_MASK
12337. BD70528_GPIO_OUT_HI
12338. BD70528_GPIO_OUT_LO
12339. BD70528_GPIO_OUT_MASK
12340. BD70528_GPIO_PUSH_PULL
12341. BD70528_INT_AUTO_WAKEUP
12342. BD70528_INT_AUTO_WAKEUP_MASK
12343. BD70528_INT_BAT1
12344. BD70528_INT_BAT1_MASK
12345. BD70528_INT_BATTSD_COLD_DET
12346. BD70528_INT_BATTSD_COLD_DET_MASK
12347. BD70528_INT_BATTSD_COLD_RES
12348. BD70528_INT_BATTSD_COLD_RES_MASK
12349. BD70528_INT_BATTSD_HOT_DET
12350. BD70528_INT_BATTSD_HOT_DET_MASK
12351. BD70528_INT_BATTSD_HOT_RES
12352. BD70528_INT_BATTSD_HOT_RES_MASK
12353. BD70528_INT_BAT_DET
12354. BD70528_INT_BAT_DET_MASK
12355. BD70528_INT_BAT_OV_DET
12356. BD70528_INT_BAT_OV_DET_MASK
12357. BD70528_INT_BAT_OV_RES
12358. BD70528_INT_BAT_OV_RES_MASK
12359. BD70528_INT_BAT_RMV
12360. BD70528_INT_BAT_RMV_MASK
12361. BD70528_INT_BUCK1_DVS_OPFAIL
12362. BD70528_INT_BUCK1_DVS_OPFAIL_MASK
12363. BD70528_INT_BUCK1_FAULT
12364. BD70528_INT_BUCK1_FAULT_MASK
12365. BD70528_INT_BUCK1_FULLON
12366. BD70528_INT_BUCK1_FULLON_MASK
12367. BD70528_INT_BUCK1_OCP
12368. BD70528_INT_BUCK1_OCP_MASK
12369. BD70528_INT_BUCK2_DVS_OPFAIL
12370. BD70528_INT_BUCK2_DVS_OPFAIL_MASK
12371. BD70528_INT_BUCK2_FAULT
12372. BD70528_INT_BUCK2_FAULT_MASK
12373. BD70528_INT_BUCK2_FULLON
12374. BD70528_INT_BUCK2_FULLON_MASK
12375. BD70528_INT_BUCK2_OCP
12376. BD70528_INT_BUCK2_OCP_MASK
12377. BD70528_INT_BUCK3_DVS_OPFAIL
12378. BD70528_INT_BUCK3_DVS_OPFAIL_MASK
12379. BD70528_INT_BUCK3_FAULT
12380. BD70528_INT_BUCK3_FAULT_MASK
12381. BD70528_INT_BUCK3_OCP
12382. BD70528_INT_BUCK3_OCP_MASK
12383. BD70528_INT_CHG_TSD
12384. BD70528_INT_CHG_TSD_MASK
12385. BD70528_INT_DBAT_DET
12386. BD70528_INT_DBAT_DET_MASK
12387. BD70528_INT_DCIN1_DET
12388. BD70528_INT_DCIN1_DET_MASK
12389. BD70528_INT_DCIN1_RMV
12390. BD70528_INT_DCIN1_RMV_MASK
12391. BD70528_INT_DCIN2_DET
12392. BD70528_INT_DCIN2_DET_MASK
12393. BD70528_INT_DCIN2_OV_DET
12394. BD70528_INT_DCIN2_OV_DET_MASK
12395. BD70528_INT_DCIN2_OV_RES
12396. BD70528_INT_DCIN2_OV_RES_MASK
12397. BD70528_INT_DCIN2_RMV
12398. BD70528_INT_DCIN2_RMV_MASK
12399. BD70528_INT_ELPS_TIM
12400. BD70528_INT_ELPS_TIM_MASK
12401. BD70528_INT_GPIO
12402. BD70528_INT_GPIO0
12403. BD70528_INT_GPIO0_MASK
12404. BD70528_INT_GPIO1
12405. BD70528_INT_GPIO1_MASK
12406. BD70528_INT_GPIO2
12407. BD70528_INT_GPIO2_MASK
12408. BD70528_INT_GPIO3
12409. BD70528_INT_GPIO3_MASK
12410. BD70528_INT_GPIO_MASK
12411. BD70528_INT_HWRESET
12412. BD70528_INT_HWRESET_MASK
12413. BD70528_INT_LDO1_FAULT
12414. BD70528_INT_LDO1_FAULT_MASK
12415. BD70528_INT_LDO2_FAULT
12416. BD70528_INT_LDO2_FAULT_MASK
12417. BD70528_INT_LDO3_FAULT
12418. BD70528_INT_LDO3_FAULT_MASK
12419. BD70528_INT_LED1_FAULT
12420. BD70528_INT_LED1_FAULT_MASK
12421. BD70528_INT_LED1_OCP
12422. BD70528_INT_LED1_OCP_MASK
12423. BD70528_INT_LED1_VOLT_OPFAIL
12424. BD70528_INT_LED1_VOLT_OPFAIL_MASK
12425. BD70528_INT_LED2_FAULT
12426. BD70528_INT_LED2_FAULT_MASK
12427. BD70528_INT_LED2_OCP
12428. BD70528_INT_LED2_OCP_MASK
12429. BD70528_INT_LED2_VOLT_OPFAIL
12430. BD70528_INT_LED2_VOLT_OPFAIL_MASK
12431. BD70528_INT_LONGPUSH
12432. BD70528_INT_LONGPUSH_MASK
12433. BD70528_INT_MASK_AUTO_WAKE
12434. BD70528_INT_MASK_POWER_STATE
12435. BD70528_INT_MASK_SHORT_PUSH
12436. BD70528_INT_MISC
12437. BD70528_INT_MISC_MASK
12438. BD70528_INT_OP_FAIL
12439. BD70528_INT_OP_FAIL_MASK
12440. BD70528_INT_PWR_FLT
12441. BD70528_INT_PWR_FLT_MASK
12442. BD70528_INT_RSTB_FAULT
12443. BD70528_INT_RSTB_FAULT_MASK
12444. BD70528_INT_RSTIN
12445. BD70528_INT_RSTIN_MASK
12446. BD70528_INT_RTC
12447. BD70528_INT_RTC_ALARM
12448. BD70528_INT_RTC_ALARM_MASK
12449. BD70528_INT_RTC_MASK
12450. BD70528_INT_SHDN
12451. BD70528_INT_SHDN_MASK
12452. BD70528_INT_SHORTPUSH
12453. BD70528_INT_SHORTPUSH_MASK
12454. BD70528_INT_STATE_CHANGE
12455. BD70528_INT_STATE_CHANGE_MASK
12456. BD70528_INT_TSD
12457. BD70528_INT_TSD_MASK
12458. BD70528_INT_VBAT_UVLO
12459. BD70528_INT_VBAT_UVLO_MASK
12460. BD70528_INT_VR_FLT
12461. BD70528_INT_VR_FLT_MASK
12462. BD70528_INT_WDT
12463. BD70528_INT_WDT_MASK
12464. BD70528_LDO1
12465. BD70528_LDO2
12466. BD70528_LDO3
12467. BD70528_LDO_VOLTS
12468. BD70528_LED1
12469. BD70528_LED2
12470. BD70528_MASK_ALM_EN
12471. BD70528_MASK_BUCK_RAMP
12472. BD70528_MASK_BUCK_VOLT
12473. BD70528_MASK_CHG_BAT_DETECT
12474. BD70528_MASK_CHG_BAT_OVERVOLT
12475. BD70528_MASK_CHG_BAT_TIMER
12476. BD70528_MASK_CHG_CHG_CURR
12477. BD70528_MASK_CHG_DCIN1_UVLO
12478. BD70528_MASK_CHG_DCIN_ILIM
12479. BD70528_MASK_CHG_STAT
12480. BD70528_MASK_CHG_TRICKLE_CURR
12481. BD70528_MASK_ELAPSED_TIMER_EN
12482. BD70528_MASK_IDLE_EN
12483. BD70528_MASK_LDO_VOLT
12484. BD70528_MASK_LED1_EN
12485. BD70528_MASK_LED1_VOLT
12486. BD70528_MASK_LED2_EN
12487. BD70528_MASK_LED2_VOLT
12488. BD70528_MASK_RTC_COUNT_L
12489. BD70528_MASK_RTC_DAY
12490. BD70528_MASK_RTC_HOUR
12491. BD70528_MASK_RTC_HOUR_24H
12492. BD70528_MASK_RTC_HOUR_PM
12493. BD70528_MASK_RTC_MINUTE
12494. BD70528_MASK_RTC_MONTH
12495. BD70528_MASK_RTC_SEC
12496. BD70528_MASK_RTC_WEEK
12497. BD70528_MASK_RTC_YEAR
12498. BD70528_MASK_RUN_EN
12499. BD70528_MASK_STBY_EN
12500. BD70528_MASK_WAKE_EN
12501. BD70528_MASK_WDT_EN
12502. BD70528_MASK_WDT_HOUR
12503. BD70528_MASK_WDT_MINUTE
12504. BD70528_MASK_WDT_SEC
12505. BD70528_MAX_REGISTER
12506. BD70528_NUM_OF_GPIOS
12507. BD70528_REG_BUCK1_EN
12508. BD70528_REG_BUCK1_VOLT
12509. BD70528_REG_BUCK2_EN
12510. BD70528_REG_BUCK2_VOLT
12511. BD70528_REG_BUCK3_EN
12512. BD70528_REG_BUCK3_VOLT
12513. BD70528_REG_CHG_BAT_STAT
12514. BD70528_REG_CHG_BAT_TEMP
12515. BD70528_REG_CHG_CHG_CURR_COLD
12516. BD70528_REG_CHG_CHG_CURR_WARM
12517. BD70528_REG_CHG_CURR_STAT
12518. BD70528_REG_CHG_DCIN_ILIM
12519. BD70528_REG_CHG_IN_STAT
12520. BD70528_REG_CLK_OUT
12521. BD70528_REG_ELAPSED_TIMER_EN
12522. BD70528_REG_GPIO1_IN
12523. BD70528_REG_GPIO1_OUT
12524. BD70528_REG_GPIO2_IN
12525. BD70528_REG_GPIO2_OUT
12526. BD70528_REG_GPIO3_IN
12527. BD70528_REG_GPIO3_OUT
12528. BD70528_REG_GPIO4_IN
12529. BD70528_REG_GPIO4_OUT
12530. BD70528_REG_GPIO_STATE
12531. BD70528_REG_HWRESET
12532. BD70528_REG_INT_BAT1
12533. BD70528_REG_INT_BAT1_MASK
12534. BD70528_REG_INT_BAT2
12535. BD70528_REG_INT_BAT2_MASK
12536. BD70528_REG_INT_GPIO
12537. BD70528_REG_INT_GPIO_MASK
12538. BD70528_REG_INT_MAIN
12539. BD70528_REG_INT_MAIN_MASK
12540. BD70528_REG_INT_MISC
12541. BD70528_REG_INT_MISC_MASK
12542. BD70528_REG_INT_OP_FAIL
12543. BD70528_REG_INT_OP_FAIL_MASK
12544. BD70528_REG_INT_PWR_FLT
12545. BD70528_REG_INT_PWR_FLT_MASK
12546. BD70528_REG_INT_RTC
12547. BD70528_REG_INT_RTC_MASK
12548. BD70528_REG_INT_SHDN
12549. BD70528_REG_INT_SHDN_MASK
12550. BD70528_REG_INT_VR_FLT
12551. BD70528_REG_INT_VR_FLT_MASK
12552. BD70528_REG_LDO1_EN
12553. BD70528_REG_LDO1_VOLT
12554. BD70528_REG_LDO2_EN
12555. BD70528_REG_LDO2_VOLT
12556. BD70528_REG_LDO3_EN
12557. BD70528_REG_LDO3_VOLT
12558. BD70528_REG_LED_CTRL
12559. BD70528_REG_LED_EN
12560. BD70528_REG_LED_VOLT
12561. BD70528_REG_RTC_ALM_DAY
12562. BD70528_REG_RTC_ALM_HOUR
12563. BD70528_REG_RTC_ALM_MASK
12564. BD70528_REG_RTC_ALM_MINUTE
12565. BD70528_REG_RTC_ALM_MONTH
12566. BD70528_REG_RTC_ALM_REPEAT
12567. BD70528_REG_RTC_ALM_SEC
12568. BD70528_REG_RTC_ALM_START
12569. BD70528_REG_RTC_ALM_WEEK
12570. BD70528_REG_RTC_ALM_YEAR
12571. BD70528_REG_RTC_COUNT_H
12572. BD70528_REG_RTC_COUNT_L
12573. BD70528_REG_RTC_DAY
12574. BD70528_REG_RTC_HOUR
12575. BD70528_REG_RTC_MINUTE
12576. BD70528_REG_RTC_MONTH
12577. BD70528_REG_RTC_SEC
12578. BD70528_REG_RTC_START
12579. BD70528_REG_RTC_WAKE_CTRL
12580. BD70528_REG_RTC_WAKE_HOUR
12581. BD70528_REG_RTC_WAKE_MIN
12582. BD70528_REG_RTC_WAKE_SEC
12583. BD70528_REG_RTC_WAKE_START
12584. BD70528_REG_RTC_WEEK
12585. BD70528_REG_RTC_YEAR
12586. BD70528_REG_SHIPMODE
12587. BD70528_REG_STANDBY
12588. BD70528_REG_WAKE_EN
12589. BD70528_REG_WARMRESET
12590. BD70528_REG_WDT_CTRL
12591. BD70528_REG_WDT_HOUR
12592. BD70528_REG_WDT_MINUTE
12593. BD70528_REG_WDT_SEC
12594. BD70528_SIFT_BUCK_RAMP
12595. BD70528_WAKE_STATE_BIT
12596. BD70528_WDT_STATE_BIT
12597. BD71837_BUCK3_VRMON130
12598. BD71837_BUCK3_VRMON80
12599. BD71837_BUCK4_VRMON130
12600. BD71837_BUCK4_VRMON80
12601. BD71837_BUCK5_MASK
12602. BD71837_BUCK5_RANGE_MASK
12603. BD71837_BUCK5_VOLTAGE_NUM
12604. BD71837_BUCK6_MASK
12605. BD71837_BUCK6_VOLTAGE_NUM
12606. BD71837_BUCK7_VOLTAGE_NUM
12607. BD71837_LDO5_MASK
12608. BD71837_LDO5_VOLTAGE_NUM
12609. BD71837_LDO7_MASK
12610. BD71837_LDO7_VOLTAGE_NUM
12611. BD71837_LDO7_VRMON80
12612. BD71837_REG_BUCK3_CTRL
12613. BD71837_REG_BUCK3_VOLT_RUN
12614. BD71837_REG_BUCK4_CTRL
12615. BD71837_REG_BUCK4_VOLT_RUN
12616. BD71837_REG_LDO7_VOLT
12617. BD71847_BUCK3_MASK
12618. BD71847_BUCK3_RANGE_MASK
12619. BD71847_BUCK3_VOLTAGE_NUM
12620. BD71847_BUCK4_MASK
12621. BD71847_BUCK4_RANGE_MASK
12622. BD71847_BUCK4_VOLTAGE_NUM
12623. BD71847_LDO5_MASK
12624. BD71847_LDO5_RANGE_MASK
12625. BD71847_LDO5_VOLTAGE_NUM
12626. BD718XX_1ST_NODVS_BUCK_MASK
12627. BD718XX_1ST_NODVS_BUCK_VRMON130
12628. BD718XX_1ST_NODVS_BUCK_VRMON80
12629. BD718XX_2ND_NODVS_BUCK_VRMON130
12630. BD718XX_2ND_NODVS_BUCK_VRMON80
12631. BD718XX_3RD_NODVS_BUCK_MASK
12632. BD718XX_3RD_NODVS_BUCK_VRMON130
12633. BD718XX_3RD_NODVS_BUCK_VRMON80
12634. BD718XX_4TH_NODVS_BUCK_MASK
12635. BD718XX_4TH_NODVS_BUCK_VOLTAGE_NUM
12636. BD718XX_4TH_NODVS_BUCK_VRMON130
12637. BD718XX_4TH_NODVS_BUCK_VRMON80
12638. BD718XX_BUCK1
12639. BD718XX_BUCK1_VRMON130
12640. BD718XX_BUCK1_VRMON80
12641. BD718XX_BUCK2
12642. BD718XX_BUCK2_VRMON130
12643. BD718XX_BUCK2_VRMON80
12644. BD718XX_BUCK3
12645. BD718XX_BUCK4
12646. BD718XX_BUCK5
12647. BD718XX_BUCK6
12648. BD718XX_BUCK7
12649. BD718XX_BUCK8
12650. BD718XX_BUCK_EN
12651. BD718XX_BUCK_RUN_ON
12652. BD718XX_BUCK_SEL
12653. BD718XX_CLK_RATE
12654. BD718XX_DVS_BUCK_VOLTAGE_NUM
12655. BD718XX_INT_ON_REQ
12656. BD718XX_INT_ON_REQ_MASK
12657. BD718XX_INT_PWRBTN
12658. BD718XX_INT_PWRBTN_L
12659. BD718XX_INT_PWRBTN_L_MASK
12660. BD718XX_INT_PWRBTN_MASK
12661. BD718XX_INT_PWRBTN_S
12662. BD718XX_INT_PWRBTN_S_MASK
12663. BD718XX_INT_STBY_REQ
12664. BD718XX_INT_STBY_REQ_MASK
12665. BD718XX_INT_SWRST
12666. BD718XX_INT_SWRST_MASK
12667. BD718XX_INT_WDOG
12668. BD718XX_INT_WDOG_MASK
12669. BD718XX_KEY_L_POWEROFF_MASK
12670. BD718XX_LDO1
12671. BD718XX_LDO1_MASK
12672. BD718XX_LDO1_RANGE_MASK
12673. BD718XX_LDO1_VOLTAGE_NUM
12674. BD718XX_LDO1_VRMON80
12675. BD718XX_LDO2
12676. BD718XX_LDO2_MASK
12677. BD718XX_LDO2_VOLTAGE_NUM
12678. BD718XX_LDO2_VRMON80
12679. BD718XX_LDO3
12680. BD718XX_LDO3_MASK
12681. BD718XX_LDO3_VOLTAGE_NUM
12682. BD718XX_LDO3_VRMON80
12683. BD718XX_LDO4
12684. BD718XX_LDO4_MASK
12685. BD718XX_LDO4_VOLTAGE_NUM
12686. BD718XX_LDO4_VRMON80
12687. BD718XX_LDO5
12688. BD718XX_LDO5_VRMON80
12689. BD718XX_LDO6
12690. BD718XX_LDO6_MASK
12691. BD718XX_LDO6_VOLTAGE_NUM
12692. BD718XX_LDO6_VRMON80
12693. BD718XX_LDO7
12694. BD718XX_LDO_EN
12695. BD718XX_LDO_SEL
12696. BD718XX_MAX_REGISTER
12697. BD718XX_ON_REQ_POWEROFF_MASK
12698. BD718XX_OUT32K_EN
12699. BD718XX_POWOFF_TIME_100MS
12700. BD718XX_POWOFF_TIME_10MS
12701. BD718XX_POWOFF_TIME_1500MS
12702. BD718XX_POWOFF_TIME_15MS
12703. BD718XX_POWOFF_TIME_20MS
12704. BD718XX_POWOFF_TIME_250MS
12705. BD718XX_POWOFF_TIME_25MS
12706. BD718XX_POWOFF_TIME_30MS
12707. BD718XX_POWOFF_TIME_35MS
12708. BD718XX_POWOFF_TIME_40MS
12709. BD718XX_POWOFF_TIME_45MS
12710. BD718XX_POWOFF_TIME_500MS
12711. BD718XX_POWOFF_TIME_50MS
12712. BD718XX_POWOFF_TIME_5MS
12713. BD718XX_POWOFF_TIME_750MS
12714. BD718XX_POWOFF_TIME_75MS
12715. BD718XX_POWOFF_TIME_MASK
12716. BD718XX_POWOFF_TO_RDY
12717. BD718XX_POWOFF_TO_SNVS
12718. BD718XX_PWRBTN_LONG_PRESS_10MS
12719. BD718XX_PWRBTN_LONG_PRESS_10S
12720. BD718XX_PWRBTN_LONG_PRESS_11S
12721. BD718XX_PWRBTN_LONG_PRESS_12S
12722. BD718XX_PWRBTN_LONG_PRESS_13S
12723. BD718XX_PWRBTN_LONG_PRESS_14S
12724. BD718XX_PWRBTN_LONG_PRESS_15S
12725. BD718XX_PWRBTN_LONG_PRESS_1S
12726. BD718XX_PWRBTN_LONG_PRESS_2S
12727. BD718XX_PWRBTN_LONG_PRESS_3S
12728. BD718XX_PWRBTN_LONG_PRESS_4S
12729. BD718XX_PWRBTN_LONG_PRESS_5S
12730. BD718XX_PWRBTN_LONG_PRESS_6S
12731. BD718XX_PWRBTN_LONG_PRESS_7S
12732. BD718XX_PWRBTN_LONG_PRESS_8S
12733. BD718XX_PWRBTN_LONG_PRESS_9S
12734. BD718XX_PWRBTN_PRESS_DURATION_MASK
12735. BD718XX_PWRBTN_SHORT_PRESS_1000MS
12736. BD718XX_PWRBTN_SHORT_PRESS_10MS
12737. BD718XX_PWRBTN_SHORT_PRESS_1500MS
12738. BD718XX_PWRBTN_SHORT_PRESS_2000MS
12739. BD718XX_PWRBTN_SHORT_PRESS_2500MS
12740. BD718XX_PWRBTN_SHORT_PRESS_3000MS
12741. BD718XX_PWRBTN_SHORT_PRESS_3500MS
12742. BD718XX_PWRBTN_SHORT_PRESS_4000MS
12743. BD718XX_PWRBTN_SHORT_PRESS_4500MS
12744. BD718XX_PWRBTN_SHORT_PRESS_5000MS
12745. BD718XX_PWRBTN_SHORT_PRESS_500MS
12746. BD718XX_PWRBTN_SHORT_PRESS_5500MS
12747. BD718XX_PWRBTN_SHORT_PRESS_6000MS
12748. BD718XX_PWRBTN_SHORT_PRESS_6500MS
12749. BD718XX_PWRBTN_SHORT_PRESS_7000MS
12750. BD718XX_PWRBTN_SHORT_PRESS_7500MS
12751. BD718XX_PWR_TRIG_KEY_L
12752. BD718XX_PWR_TRIG_KEY_S
12753. BD718XX_PWR_TRIG_PMIC_ON
12754. BD718XX_PWR_TRIG_VSYS_UVLO
12755. BD718XX_RDY_TO_SNVS_MASK
12756. BD718XX_RDY_TO_SNVS_SIFT
12757. BD718XX_REGULATOR_AMOUNT
12758. BD718XX_REG_1ST_NODVS_BUCK_CTRL
12759. BD718XX_REG_1ST_NODVS_BUCK_VOLT
12760. BD718XX_REG_2ND_NODVS_BUCK_CTRL
12761. BD718XX_REG_2ND_NODVS_BUCK_VOLT
12762. BD718XX_REG_3RD_NODVS_BUCK_CTRL
12763. BD718XX_REG_3RD_NODVS_BUCK_VOLT
12764. BD718XX_REG_4TH_NODVS_BUCK_CTRL
12765. BD718XX_REG_4TH_NODVS_BUCK_VOLT
12766. BD718XX_REG_BUCK1_CTRL
12767. BD718XX_REG_BUCK1_VOLT_IDLE
12768. BD718XX_REG_BUCK1_VOLT_RUN
12769. BD718XX_REG_BUCK1_VOLT_SUSP
12770. BD718XX_REG_BUCK2_CTRL
12771. BD718XX_REG_BUCK2_VOLT_IDLE
12772. BD718XX_REG_BUCK2_VOLT_RUN
12773. BD718XX_REG_I2C_DEV
12774. BD718XX_REG_IN_MON
12775. BD718XX_REG_IRQ
12776. BD718XX_REG_LDO1_VOLT
12777. BD718XX_REG_LDO2_VOLT
12778. BD718XX_REG_LDO3_VOLT
12779. BD718XX_REG_LDO4_VOLT
12780. BD718XX_REG_LDO5_VOLT
12781. BD718XX_REG_LDO6_VOLT
12782. BD718XX_REG_MIRQ
12783. BD718XX_REG_MVRFLTMASK0
12784. BD718XX_REG_MVRFLTMASK1
12785. BD718XX_REG_MVRFLTMASK2
12786. BD718XX_REG_OTPVER
12787. BD718XX_REG_OUT32K
12788. BD718XX_REG_POW_STATE
12789. BD718XX_REG_PWRCTRL0
12790. BD718XX_REG_PWRCTRL1
12791. BD718XX_REG_PWRONCONFIG0
12792. BD718XX_REG_PWRONCONFIG1
12793. BD718XX_REG_RCVCFG
12794. BD718XX_REG_RCVNUM
12795. BD718XX_REG_REGLOCK
12796. BD718XX_REG_RESETSRC
12797. BD718XX_REG_REV
12798. BD718XX_REG_SWRESET
12799. BD718XX_REG_TRANS_COND0
12800. BD718XX_REG_TRANS_COND1
12801. BD718XX_REG_VRFAULTEN
12802. BD718XX_SNVS_TO_RUN_MASK
12803. BD718XX_SNVS_TO_RUN_SIFT
12804. BD718XX_SWRESET_POWEROFF_MASK
12805. BD718XX_SWRESET_RESET
12806. BD718XX_SWRESET_RESET_MASK
12807. BD718XX_SWRESET_TYPE_COLD
12808. BD718XX_SWRESET_TYPE_DISABLED
12809. BD718XX_SWRESET_TYPE_MASK
12810. BD718XX_SWRESET_TYPE_WARM
12811. BD718XX_WDOG_POWEROFF_MASK
12812. BD8
12813. BD8IO
12814. BD8IO_MASK
12815. BD8_MASK
12816. BD9571MWV_128H_TIM_CNT
12817. BD9571MWV_ACCESS_KEY
12818. BD9571MWV_AVS_DVFS_VID
12819. BD9571MWV_AVS_SET_MONI
12820. BD9571MWV_AVS_SET_MONI_MASK
12821. BD9571MWV_AVS_VD09_VID
12822. BD9571MWV_BKUP_CTRL_TIM_CNT
12823. BD9571MWV_BKUP_MODE_CNT
12824. BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0
12825. BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0C
12826. BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1
12827. BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1C
12828. BD9571MWV_BKUP_MODE_CNT_KEEPON_MASK
12829. BD9571MWV_BKUP_MODE_STATUS
12830. BD9571MWV_BKUP_RECOVERY_CNT
12831. BD9571MWV_DVFS_BOOSTVID
12832. BD9571MWV_DVFS_MONIVDAC
12833. BD9571MWV_DVFS_PGD_CNT
12834. BD9571MWV_DVFS_SETVID
12835. BD9571MWV_DVFS_SETVMAX
12836. BD9571MWV_DVFS_VINIT
12837. BD9571MWV_GPIO_DEB
12838. BD9571MWV_GPIO_DIR
12839. BD9571MWV_GPIO_IN
12840. BD9571MWV_GPIO_INT
12841. BD9571MWV_GPIO_INTMASK
12842. BD9571MWV_GPIO_INT_SET
12843. BD9571MWV_GPIO_OUT
12844. BD9571MWV_I2C_FUSA_MODE
12845. BD9571MWV_I2C_MD2_E1_BIT_1
12846. BD9571MWV_I2C_MD2_E1_BIT_2
12847. BD9571MWV_INT_INTMASK
12848. BD9571MWV_INT_INTREQ
12849. BD9571MWV_INT_INTREQ_128H_OF_INT
12850. BD9571MWV_INT_INTREQ_BKUP_TRG_INT
12851. BD9571MWV_INT_INTREQ_GP_INT
12852. BD9571MWV_INT_INTREQ_MD1_INT
12853. BD9571MWV_INT_INTREQ_MD2_E1_INT
12854. BD9571MWV_INT_INTREQ_MD2_E2_INT
12855. BD9571MWV_INT_INTREQ_PROT_ERR_INT
12856. BD9571MWV_INT_INTREQ_WDT_OF_INT
12857. BD9571MWV_IRQ_128H_OF
12858. BD9571MWV_IRQ_BKUP_TRG
12859. BD9571MWV_IRQ_GP
12860. BD9571MWV_IRQ_MD1
12861. BD9571MWV_IRQ_MD2_E1
12862. BD9571MWV_IRQ_MD2_E2
12863. BD9571MWV_IRQ_PROT_ERR
12864. BD9571MWV_IRQ_WDT_OF
12865. BD9571MWV_PMIC_INTERNAL_STATUS
12866. BD9571MWV_PRODUCT_CODE
12867. BD9571MWV_PRODUCT_CODE_VAL
12868. BD9571MWV_PRODUCT_REVISION
12869. BD9571MWV_PROT_ERROR_STATUS0
12870. BD9571MWV_PROT_ERROR_STATUS1
12871. BD9571MWV_PROT_ERROR_STATUS2
12872. BD9571MWV_PROT_ERROR_STATUS3
12873. BD9571MWV_PROT_ERROR_STATUS4
12874. BD9571MWV_QLLM_CNT
12875. BD9571MWV_REG
12876. BD9571MWV_REG_KEEP
12877. BD9571MWV_VD18_VID
12878. BD9571MWV_VD25_VID
12879. BD9571MWV_VD33_VID
12880. BD9571MWV_VENDOR_CODE
12881. BD9571MWV_VENDOR_CODE_VAL
12882. BD9571MWV_WAITBKUP_WDT_CNT
12883. BDA
12884. BDA10POWERUP
12885. BDA10PS_ATRX
12886. BDA10PS_ATTX
12887. BDA10_REVERSE
12888. BDA10_SWING
12889. BDA6DEBUGMODE
12890. BDA6POWERUP
12891. BDA6SWING
12892. BDA7CURRENT
12893. BDA7INPUT_CM_MODE
12894. BDA7INPUT_RANGE
12895. BDA7OUTPUT_CM_MODE
12896. BDA7_GAIN
12897. BDADDR_ANY
12898. BDADDR_BCM20702A0
12899. BDADDR_BCM20702A1
12900. BDADDR_BCM2076B1
12901. BDADDR_BCM4324B3
12902. BDADDR_BCM4330B1
12903. BDADDR_BCM43341B
12904. BDADDR_BCM43430A0
12905. BDADDR_BCM4345C5
12906. BDADDR_BREDR
12907. BDADDR_INTEL
12908. BDADDR_IS_DIR
12909. BDADDR_IS_PRT
12910. BDADDR_LE_PUBLIC
12911. BDADDR_LE_RANDOM
12912. BDADDR_NONE
12913. BDAFORMAT
12914. BDAGCENABLE
12915. BDA_CLK_SOURCE
12916. BDBASE
12917. BDB_BACKLIGHT_TYPE_NONE
12918. BDB_BACKLIGHT_TYPE_PWM
12919. BDB_CHILD_DEVICE_TABLE
12920. BDB_DISPLAY_REMOVE
12921. BDB_DISPLAY_SELECT
12922. BDB_DOT_CLOCK_OVERRIDE
12923. BDB_DOT_CLOCK_TABLE
12924. BDB_DRIVER_FEATURES
12925. BDB_DRIVER_FEATURE_EDP
12926. BDB_DRIVER_FEATURE_INT_LVDS
12927. BDB_DRIVER_FEATURE_INT_SDVO_LVDS
12928. BDB_DRIVER_FEATURE_NO_LVDS
12929. BDB_DRIVER_FEATURE_SDVO_LVDS
12930. BDB_DRIVER_PERSISTENCE
12931. BDB_DRIVER_ROTATION
12932. BDB_EDP
12933. BDB_EFP_LIST
12934. BDB_EXT_MMIO_REGS
12935. BDB_EXT_TABLE_PTRS
12936. BDB_GENERAL_DEFINITIONS
12937. BDB_GENERAL_FEATURES
12938. BDB_GENERIC_MODE_TABLE
12939. BDB_LVDS_BACKLIGHT
12940. BDB_LVDS_LFP_DATA
12941. BDB_LVDS_LFP_DATA_PTRS
12942. BDB_LVDS_OPTIONS
12943. BDB_LVDS_POWER
12944. BDB_MIPI_CONFIG
12945. BDB_MIPI_SEQUENCE
12946. BDB_MODE_REMOVAL_TABLE
12947. BDB_MODE_SUPPORT_LIST
12948. BDB_OEM_CUSTOM
12949. BDB_OLD_TOGGLE_LIST
12950. BDB_PSR
12951. BDB_SDVO_LVDS_OPTIONS
12952. BDB_SDVO_LVDS_PNP_IDS
12953. BDB_SDVO_LVDS_POWER_SEQ
12954. BDB_SDVO_PANEL_DTDS
12955. BDB_SKIP
12956. BDB_SWF_IO
12957. BDB_SWF_MMIO
12958. BDB_TV_OPTIONS
12959. BDCR
12960. BDC_BDCCAP0
12961. BDC_BDCCAP1
12962. BDC_BDCCFG0
12963. BDC_BDCCFG1
12964. BDC_BDCSC
12965. BDC_CFC
12966. BDC_CMDPAR0
12967. BDC_CMDPAR1
12968. BDC_CMDPAR2
12969. BDC_CMDSC
12970. BDC_CMDS_BUSY
12971. BDC_CMDS_FAIL
12972. BDC_CMDS_INTL
12973. BDC_CMDS_PARA
12974. BDC_CMDS_STAT
12975. BDC_CMDS_SUCC
12976. BDC_CMD_BLA
12977. BDC_CMD_CST
12978. BDC_CMD_CWS
12979. BDC_CMD_DNC
12980. BDC_CMD_DVC
12981. BDC_CMD_EP0_XSD
12982. BDC_CMD_EPC
12983. BDC_CMD_EPN
12984. BDC_CMD_EPO
12985. BDC_CMD_EPO_RST_SN
12986. BDC_CMD_FH
12987. BDC_CMD_SRD
12988. BDC_CMD_TIMEOUT
12989. BDC_COP_MASK
12990. BDC_COP_RST
12991. BDC_COP_RUN
12992. BDC_COP_STP
12993. BDC_COP_TIMEOUT
12994. BDC_COS
12995. BDC_CSTS
12996. BDC_DC_NOTCH
12997. BDC_DVCSA
12998. BDC_DVCSB
12999. BDC_EPSTS0
13000. BDC_EPSTS1
13001. BDC_EPSTS2
13002. BDC_EPSTS3
13003. BDC_EPSTS4
13004. BDC_EPSTS5
13005. BDC_EPSTS6
13006. BDC_EPSTS7
13007. BDC_EP_ENABLED
13008. BDC_EP_STALL
13009. BDC_EP_STOP
13010. BDC_FSCNIC
13011. BDC_FSCNOC
13012. BDC_GIE
13013. BDC_GIP
13014. BDC_HLE
13015. BDC_HLT
13016. BDC_INTCTLS
13017. BDC_LINK_STATE_RESUME
13018. BDC_LINK_STATE_RX_DET
13019. BDC_LINK_STATE_U0
13020. BDC_LINK_STATE_U3
13021. BDC_MASK_MCW
13022. BDC_NOR
13023. BDC_OIP
13024. BDC_P64
13025. BDC_PCC
13026. BDC_PCE
13027. BDC_PCI_PID
13028. BDC_PCS
13029. BDC_PGS
13030. BDC_PORT_W1S
13031. BDC_PRC
13032. BDC_PRS
13033. BDC_PSC
13034. BDC_PSP
13035. BDC_PST
13036. BDC_PST_MASK
13037. BDC_PTC_MASK
13038. BDC_SCN
13039. BDC_SDC
13040. BDC_SLOPE_CHECK
13041. BDC_SPB
13042. BDC_SPBBAH
13043. BDC_SPBBAL
13044. BDC_SPEED_FS
13045. BDC_SPEED_HS
13046. BDC_SPEED_LS
13047. BDC_SPEED_SS
13048. BDC_SRRBAH
13049. BDC_SRRBAL
13050. BDC_SRRINT
13051. BDC_SRR_DPI
13052. BDC_SRR_DPI_MASK
13053. BDC_SRR_EPI
13054. BDC_SRR_IE
13055. BDC_SRR_IP
13056. BDC_SRR_ISR
13057. BDC_SRR_RST
13058. BDC_SRR_RWS
13059. BDC_SUB_CMD_ADD
13060. BDC_SUB_CMD_ADD_EP
13061. BDC_SUB_CMD_DRP_EP
13062. BDC_SUB_CMD_EP_RST
13063. BDC_SUB_CMD_EP_STL
13064. BDC_SUB_CMD_EP_STP
13065. BDC_SUB_CMD_FWK
13066. BDC_SWS
13067. BDC_TNOTIFY
13068. BDC_U1E
13069. BDC_U1T
13070. BDC_U1T_MASK
13071. BDC_U2A
13072. BDC_U2E
13073. BDC_U2T
13074. BDC_USPC
13075. BDC_USPPM2
13076. BDC_USPPMS
13077. BDC_USPSC_RW
13078. BDC_VBC
13079. BDC_VBS
13080. BDC_XSFNTF
13081. BDDIR_ENTRY_HI
13082. BDDIR_ENTRY_LO
13083. BDDIR_TO_MEM
13084. BDDIR_UPPER_MASK
13085. BDEBUG_ITEM
13086. BDEBUG_PAGE
13087. BDECC_ENTRY
13088. BDECC_TO_MEM
13089. BDECC_UPPER_MASK
13090. BDESC_HEADER
13091. BDEVFS_MAGIC
13092. BDEVNAME_SIZE
13093. BDEVT_SIZE
13094. BDEV_DATA_START_DEFAULT
13095. BDEV_I
13096. BDEV_STATE_CLEAN
13097. BDEV_STATE_DIRTY
13098. BDEV_STATE_NONE
13099. BDEV_STATE_STALE
13100. BDFIR_BACKOFF
13101. BDFSCNT0
13102. BDFSCNT1
13103. BDFSFLAG
13104. BDINFO_FLAGS_DISABLED
13105. BDINFO_FLAGS_MAXLEN_MASK
13106. BDINFO_FLAGS_MAXLEN_SHIFT
13107. BDINFO_FLAGS_USE_EXT_RECV
13108. BDIS
13109. BDISABLE
13110. BDISP_ARGB8888
13111. BDISP_CBCR
13112. BDISP_CTX_ABORT
13113. BDISP_CTX_STOP_REQ
13114. BDISP_DEF_HEIGHT
13115. BDISP_DEF_WIDTH
13116. BDISP_DST_FMT
13117. BDISP_HF_NB
13118. BDISP_MAX_CTRL_NUM
13119. BDISP_MAX_H
13120. BDISP_MAX_W
13121. BDISP_MIN_H
13122. BDISP_MIN_W
13123. BDISP_NAME
13124. BDISP_NV12
13125. BDISP_PARAMS
13126. BDISP_RGB
13127. BDISP_RGB565
13128. BDISP_RGB888
13129. BDISP_SRC_FMT
13130. BDISP_VF_NB
13131. BDISP_WORK_TIMEOUT
13132. BDISP_XRGB8888
13133. BDISP_Y
13134. BDISP_YUV_3B
13135. BDI_CAP_CGROUP_WRITEBACK
13136. BDI_CAP_NO_ACCT_AND_WRITEBACK
13137. BDI_CAP_NO_ACCT_DIRTY
13138. BDI_CAP_NO_ACCT_WB
13139. BDI_CAP_NO_WRITEBACK
13140. BDI_CAP_STABLE_WRITES
13141. BDI_CAP_STRICTLIMIT
13142. BDI_CAP_SYNCHRONOUS_IO
13143. BDI_SHOW
13144. BDL_ALIGN
13145. BDL_SIZE
13146. BDM
13147. BDMA
13148. BDMA_CK
13149. BDMA_DESC_BLKPAD
13150. BDMA_DESC_BUFLEN
13151. BDMA_DESC_BUFLEN_EXT
13152. BDMA_DESC_CHECKSUM
13153. BDMA_DESC_DWPAD
13154. BDMA_DESC_EOL
13155. BDMA_DESC_NEXT_H4
13156. BDMA_DESC_PTR_H4
13157. BDMR_OFS
13158. BDO_MODE_CARRIER0
13159. BDO_MODE_CARRIER1
13160. BDO_MODE_CARRIER2
13161. BDO_MODE_CARRIER3
13162. BDO_MODE_COUNTERS
13163. BDO_MODE_EYE
13164. BDO_MODE_MASK
13165. BDO_MODE_RECV
13166. BDO_MODE_TESTDATA
13167. BDO_MODE_TRANSMIT
13168. BDP
13169. BDPA
13170. BDPLLPOWERUP
13171. BDPRT_ENTRY
13172. BDPRT_ENTRY_ADDR
13173. BDPRT_ENTRY_L
13174. BDPRT_ENTRY_S
13175. BDPRT_TO_MEM
13176. BDQ_ID_IMM_DATA
13177. BDQ_ID_RQ
13178. BDQ_ID_TQ
13179. BDQ_MAX_EXTERNAL_RING_SIZE
13180. BDQ_NUM_IDS
13181. BDQ_NUM_RESOURCES
13182. BDR
13183. BDRL
13184. BDRM
13185. BDS_PER_TX_PKT
13186. BDW
13187. BDWORD
13188. BDW_DISABLE_HDC_INVALIDATION
13189. BDW_DISPLAY_POWER_DOMAINS
13190. BDW_DPRS_MASK_VBLANK_SRD
13191. BDW_DRAM_SIZE
13192. BDW_DSP_BAR
13193. BDW_EDP_PSR_BASE
13194. BDW_FBC_COMP_SEG_MASK
13195. BDW_GMCH_GGMS_MASK
13196. BDW_GMCH_GGMS_SHIFT
13197. BDW_GMCH_GMS_MASK
13198. BDW_GMCH_GMS_SHIFT
13199. BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE
13200. BDW_IRAM_SIZE
13201. BDW_L3_MISS
13202. BDW_L3_MISS_LOCAL
13203. BDW_PANIC_OFFSET
13204. BDW_PCI_BAR
13205. BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
13206. BDW_PLATFORM
13207. BDW_PSR_SINGLE_FRAME
13208. BDW_SCRATCH1
13209. BDW_SIZE
13210. BDW_STACK_DUMP_SIZE
13211. BDX_ASSERT
13212. BDX_COPYBREAK
13213. BDX_DEF_MSG_ENABLE
13214. BDX_DELAY_WPTR
13215. BDX_DRV_DESC
13216. BDX_DRV_NAME
13217. BDX_DRV_VERSION
13218. BDX_IRQ_TYPE
13219. BDX_LLTX
13220. BDX_MAX_MTU
13221. BDX_MAX_RX_DONE
13222. BDX_MAX_TX_LEVEL
13223. BDX_MIN_TX_LEVEL
13224. BDX_MSI
13225. BDX_MSI_STRING
13226. BDX_MSR_UNCORE_SBOX
13227. BDX_NDEV_TXQ_LEN
13228. BDX_NIC2PORT_NAME
13229. BDX_NIC_NAME
13230. BDX_NO_UPD_PACKETS
13231. BDX_OP_READ
13232. BDX_OP_WRITE
13233. BDX_PCI_QPI_PORT2_FILTER
13234. BDX_PCI_UNCORE_HA
13235. BDX_PCI_UNCORE_IMC
13236. BDX_PCI_UNCORE_IRP
13237. BDX_PCI_UNCORE_QPI
13238. BDX_PCI_UNCORE_R2PCIE
13239. BDX_PCI_UNCORE_R3QPI
13240. BDX_REGS_SIZE
13241. BDX_TSO
13242. BDX_TXF_DESC_SZ
13243. BD_ALLOCATED
13244. BD_BADKME
13245. BD_BUFLEN
13246. BD_BuffLength_MASK
13247. BD_CBD_INT_EN
13248. BD_CHAIN
13249. BD_CHAMP2
13250. BD_CHAN_BDCNT
13251. BD_CHAN_BDCNT_BIT
13252. BD_CHAN_EN
13253. BD_CHAN_EN_BIT
13254. BD_CHAN_TYPE
13255. BD_CHAN_TYPE_BIT
13256. BD_CONT
13257. BD_CPUFREQ
13258. BD_CS_DEASSERT
13259. BD_CTL_REPEAT_VALID_MASK
13260. BD_CTL_REPEAT_VALID_SHIFT
13261. BD_CTL_SHADOW_INDEX_MASK
13262. BD_CTL_SHADOW_INDEX_SHIFT
13263. BD_CownsBD
13264. BD_DATA_DR
13265. BD_DATA_DR_BIT
13266. BD_DATA_EN
13267. BD_DATA_EN_BIT
13268. BD_DATA_ER
13269. BD_DATA_ER_BIT
13270. BD_DATA_IE
13271. BD_DATA_IE_BIT
13272. BD_DATA_LEN
13273. BD_DATA_LEN_BIT
13274. BD_DATA_RECV
13275. BD_DATA_TYPE
13276. BD_DATA_TYPE_BIT
13277. BD_DDR
13278. BD_DEVSEL_SHIFT
13279. BD_DIR_IN
13280. BD_DISWATCHDOG
13281. BD_DONE
13282. BD_DUAL
13283. BD_EMUFRAME_NONE
13284. BD_EN
13285. BD_ENET0
13286. BD_ENET1
13287. BD_ENET_RX_BC
13288. BD_ENET_RX_CL
13289. BD_ENET_RX_CR
13290. BD_ENET_RX_EMPTY
13291. BD_ENET_RX_FIRST
13292. BD_ENET_RX_ICE
13293. BD_ENET_RX_INT
13294. BD_ENET_RX_INTR
13295. BD_ENET_RX_LAST
13296. BD_ENET_RX_LG
13297. BD_ENET_RX_MC
13298. BD_ENET_RX_MISS
13299. BD_ENET_RX_NO
13300. BD_ENET_RX_OV
13301. BD_ENET_RX_PCR
13302. BD_ENET_RX_PTP
13303. BD_ENET_RX_SH
13304. BD_ENET_RX_STATS
13305. BD_ENET_RX_VLAN
13306. BD_ENET_RX_WRAP
13307. BD_ENET_TX_CSL
13308. BD_ENET_TX_DEF
13309. BD_ENET_TX_HB
13310. BD_ENET_TX_IINS
13311. BD_ENET_TX_INT
13312. BD_ENET_TX_INTR
13313. BD_ENET_TX_LAST
13314. BD_ENET_TX_LC
13315. BD_ENET_TX_PAD
13316. BD_ENET_TX_PINS
13317. BD_ENET_TX_RCMASK
13318. BD_ENET_TX_READY
13319. BD_ENET_TX_RL
13320. BD_ENET_TX_STATS
13321. BD_ENET_TX_TC
13322. BD_ENET_TX_TS
13323. BD_ENET_TX_UN
13324. BD_ENET_TX_WRAP
13325. BD_EOT
13326. BD_ERGO
13327. BD_ERR_IRQ_HND
13328. BD_EXTD
13329. BD_EXTUARTCLK
13330. BD_FAILED
13331. BD_FLG_BCAST
13332. BD_FLG_COAL_NOW
13333. BD_FLG_END
13334. BD_FLG_FRAME_ERROR
13335. BD_FLG_IP_FRAG
13336. BD_FLG_IP_FRAG_END
13337. BD_FLG_IP_SUM
13338. BD_FLG_JUMBO
13339. BD_FLG_MCAST
13340. BD_FLG_MINI
13341. BD_FLG_MORE
13342. BD_FLG_TCP_UDP_SUM
13343. BD_FLG_TYP_MASK
13344. BD_FLG_UCAST
13345. BD_FLG_VLAN_TAG
13346. BD_HCI_SEL
13347. BD_HEADER
13348. BD_I2C_START
13349. BD_INFO_IRQ_HND
13350. BD_INTR
13351. BD_INTR_TARGET
13352. BD_IOC
13353. BD_IPCV2_END_OF_FRAME
13354. BD_IRQ_HND
13355. BD_ISCASPER
13356. BD_ISP
13357. BD_LAST
13358. BD_LAST_UPDATE_HW_MASK
13359. BD_LAST_UPDATE_HW_SHIFT
13360. BD_LEN
13361. BD_LENGTH_MASK
13362. BD_LFLAG
13363. BD_LIFM
13364. BD_LIST_MAX_NUM
13365. BD_LSBF
13366. BD_LTF
13367. BD_MAC1
13368. BD_MAC2
13369. BD_MASK
13370. BD_MAX_BUFF_SIZE
13371. BD_MAX_SEND_SIZE
13372. BD_MEMCAP
13373. BD_METRO
13374. BD_NOBIOS
13375. BD_NOFEP
13376. BD_NOIOPORT
13377. BD_NOMEM
13378. BD_NONE
13379. BD_NOTFOUND
13380. BD_PART_WRITTEN
13381. BD_PCCARD
13382. BD_PERFORMANCE
13383. BD_PKG_SEL
13384. BD_PKT_INT_EN
13385. BD_PLEXUS
13386. BD_QUAD
13387. BD_READ_DATA
13388. BD_READ_PTR_DDR_ENABLE_MASK
13389. BD_READ_PTR_DDR_ENABLE_SHIFT
13390. BD_READ_PTR_DDR_TIMER_VAL_MASK
13391. BD_READ_PTR_DDR_TIMER_VAL_SHIFT
13392. BD_REASON
13393. BD_REV
13394. BD_RROR
13395. BD_RSTFACTORY
13396. BD_RUNNING
13397. BD_RxBDID_MASK
13398. BD_RxBDID_SHIFT
13399. BD_RxBDSeqN_MASK
13400. BD_RxBDSeqN_SHIFT
13401. BD_SBF
13402. BD_SCC_TX_LAST
13403. BD_SC_BR
13404. BD_SC_CD
13405. BD_SC_CL
13406. BD_SC_CM
13407. BD_SC_EMPTY
13408. BD_SC_FR
13409. BD_SC_ID
13410. BD_SC_INTRPT
13411. BD_SC_LAST
13412. BD_SC_NAK
13413. BD_SC_OV
13414. BD_SC_P
13415. BD_SC_PR
13416. BD_SC_READY
13417. BD_SC_TC
13418. BD_SC_UN
13419. BD_SC_WRAP
13420. BD_SET_UNMAP_ADDR_LEN
13421. BD_SIZE_2048_MAX_MTU
13422. BD_SOT
13423. BD_SPLIT_SIZE
13424. BD_START_ADDR_DECODE
13425. BD_START_ADDR_VALUE
13426. BD_STATUS_MASK
13427. BD_STAT_CHECK
13428. BD_SUPPRESS
13429. BD_SUPPRESS_SHIFT
13430. BD_SYSFREQ
13431. BD_SYSLED
13432. BD_TFS_SHIFT
13433. BD_TH_HI
13434. BD_TH_LO
13435. BD_TRIBOOT
13436. BD_TYPE_BITMASK
13437. BD_TYPE_DS
13438. BD_TYPE_SS
13439. BD_UART0
13440. BD_UART1
13441. BD_UNMAP_ADDR
13442. BD_UNMAP_LEN
13443. BD_VALUE
13444. BD_WLAN0
13445. BD_WLAN0_2G_EN
13446. BD_WLAN0_5G_EN
13447. BD_WLAN1
13448. BD_WLAN1_2G_EN
13449. BD_WLAN1_5G_EN
13450. BD_WRAP
13451. BD_WRAP_BACK
13452. BD_WRITE_DATA
13453. BDesc
13454. BE
13455. BE0
13456. BE1
13457. BE2
13458. BE2ISCSI_LINK_SPEED_100MBPS
13459. BE2ISCSI_LINK_SPEED_10GBPS
13460. BE2ISCSI_LINK_SPEED_10MBPS
13461. BE2ISCSI_LINK_SPEED_1GBPS
13462. BE2ISCSI_LINK_SPEED_25GBPS
13463. BE2ISCSI_LINK_SPEED_40GBPS
13464. BE2_BIOS_COMP_MAX_SIZE
13465. BE2_COMP_MAX_SIZE
13466. BE2_DEFPDU_DATA_SZ
13467. BE2_DEFPDU_HDR_SZ
13468. BE2_FCOE_BACKUP_IMAGE_START
13469. BE2_FCOE_BIOS_START
13470. BE2_FCOE_PRIMARY_IMAGE_START
13471. BE2_IO_DEPTH
13472. BE2_ISCSI_BACKUP_IMAGE_START
13473. BE2_ISCSI_BIOS_START
13474. BE2_ISCSI_PRIMARY_IMAGE_START
13475. BE2_MAX_NUM_CQ_PROC
13476. BE2_MAX_RSS_QS
13477. BE2_MAX_SESSIONS
13478. BE2_NOPOUT_REQ
13479. BE2_PXE_BIOS_START
13480. BE2_REDBOOT_COMP_MAX_SIZE
13481. BE2_REDBOOT_START
13482. BE2_SGE
13483. BE2_TMFS
13484. BE2_chip
13485. BE3
13486. BE3_BIOS_COMP_MAX_SIZE
13487. BE3_COMP_MAX_SIZE
13488. BE3_FCOE_BACKUP_IMAGE_START
13489. BE3_FCOE_BIOS_START
13490. BE3_FCOE_PRIMARY_IMAGE_START
13491. BE3_ISCSI_BACKUP_IMAGE_START
13492. BE3_ISCSI_BIOS_START
13493. BE3_ISCSI_PRIMARY_IMAGE_START
13494. BE3_MAX_EVT_QS
13495. BE3_MAX_RSS_QS
13496. BE3_MAX_TX_QS
13497. BE3_NAME
13498. BE3_NCSI_COMP_MAX_SIZE
13499. BE3_NCSI_START
13500. BE3_PHY_FW_COMP_MAX_SIZE
13501. BE3_PHY_FW_START
13502. BE3_PXE_BIOS_START
13503. BE3_REDBOOT_COMP_MAX_SIZE
13504. BE3_REDBOOT_START
13505. BE3_SRIOV_MAX_EVT_QS
13506. BE3_chip
13507. BEACON
13508. BEACON_ATIM
13509. BEACON_BASE_TO_OFFSET
13510. BEACON_CTRL_MBSSID
13511. BEACON_CTRL_TX_BEACON_RPT
13512. BEACON_DISABLE_TSF_UPDATE
13513. BEACON_DMA_ATIME_INT_TIME
13514. BEACON_EVENT_IND
13515. BEACON_FILTER_IE_ID_CHANNEL_SWITCH_ANN
13516. BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE
13517. BEACON_FILTER_TABLE_IE_ENTRY_SIZE
13518. BEACON_FILTER_TABLE_MAX_IE_NUM
13519. BEACON_FILTER_TABLE_MAX_SIZE
13520. BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM
13521. BEACON_FRAME_OFF
13522. BEACON_FTYPE
13523. BEACON_FUNCTION_ENABLE
13524. BEACON_HW_Q
13525. BEACON_INFO
13526. BEACON_INTERVAL
13527. BEACON_INTERVAL_DEFAULT
13528. BEACON_LOST_COUNT_MAX
13529. BEACON_NOTIFICATION
13530. BEACON_OFFLOAD
13531. BEACON_PG
13532. BEACON_PRIORITY
13533. BEACON_PROBE_SSID_ID_POSITION
13534. BEACON_QUEUE
13535. BEACON_READY
13536. BEACON_RSSI
13537. BEACON_RULE_PASS_ON_APPEARANCE
13538. BEACON_RULE_PASS_ON_CHANGE
13539. BEACON_STATE_DISABLED
13540. BEACON_STATE_ENABLED
13541. BEACON_TEMPLATE_CMD
13542. BEACON_TEMPLATE_SIZE
13543. BEACON_THRESHOLD
13544. BEACON_TIMEOUT_VAL
13545. BEACON_TYPE
13546. BEACON_VERSION_V0
13547. BEACON_VERSION_V1
13548. BEACON_WATCHDOG_DELAY
13549. BEAMFORMING_HT_BEAMFORMEE_ENABLE
13550. BEAMFORMING_HT_BEAMFORMER_ENABLE
13551. BEAMFORMING_HT_BEAMFORMER_TEST
13552. BEAMFORMING_SUPPORT
13553. BEAMFORMING_WK_CID
13554. BEAdmTime
13555. BEBITS
13556. BEBOB_ADDR_REG_INFO
13557. BEBOB_ADDR_REG_REQ
13558. BEDCCA_H
13559. BEDCCA_L
13560. BED_TH2
13561. BEEPER_MODNAME
13562. BEEPR
13563. BEEP_BUFLEN
13564. BEEP_ENABLE
13565. BEEP_ENABLE_BASE
13566. BEEP_FREQ
13567. BEEP_MASK_FROM_REG
13568. BEEP_MASK_TO_REG
13569. BEEP_SRATE
13570. BEEP_VOLUME
13571. BEFS_ATTR_INODE
13572. BEFS_BAD_INODE
13573. BEFS_BTREE_MAGIC
13574. BEFS_BT_EMPTY
13575. BEFS_BT_END
13576. BEFS_BT_MATCH
13577. BEFS_BT_NOT_FOUND
13578. BEFS_BT_OVERFLOW
13579. BEFS_BYTEORDER_NATIVE
13580. BEFS_BYTEORDER_NATIVE_BE
13581. BEFS_BYTEORDER_NATIVE_LE
13582. BEFS_BYTESEX_BE
13583. BEFS_BYTESEX_LE
13584. BEFS_CLEAN
13585. BEFS_DBLINDIR_BRUN_LEN
13586. BEFS_DIRTY
13587. BEFS_ERR
13588. BEFS_I
13589. BEFS_INODE_DELETED
13590. BEFS_INODE_IN_USE
13591. BEFS_INODE_LOGGED
13592. BEFS_INODE_MAGIC1
13593. BEFS_INODE_NO_CREATE
13594. BEFS_INODE_WAS_WRITTEN
13595. BEFS_LONG_SYMLINK
13596. BEFS_NAME_LEN
13597. BEFS_NO_TRANSACTION
13598. BEFS_NUM_DIRECT_BLOCKS
13599. BEFS_OK
13600. BEFS_PERMANENT_FLAG
13601. BEFS_SUPER_MAGIC
13602. BEFS_SUPER_MAGIC1
13603. BEFS_SUPER_MAGIC1_BE
13604. BEFS_SUPER_MAGIC1_LE
13605. BEFS_SUPER_MAGIC2
13606. BEFS_SUPER_MAGIC3
13607. BEFS_SYMLINK_LEN
13608. BEFS_VERSION
13609. BEF_CONTINUATION
13610. BEF_EVEN_FIELD
13611. BEF_MORE_DATA
13612. BEF_OVERFLOW
13613. BEGIN
13614. BEGIN_BCI
13615. BEGIN_DMA
13616. BEGIN_DMA_WRAP
13617. BEGIN_FTR_SECTION
13618. BEGIN_FTR_SECTION_NESTED
13619. BEGIN_FW_FTR_SECTION
13620. BEGIN_FW_FTR_SECTION_NESTED
13621. BEGIN_IMC0
13622. BEGIN_LP_RING
13623. BEGIN_MMU_FTR_SECTION
13624. BEGIN_MMU_FTR_SECTION_NESTED
13625. BEGIN_NI04
13626. BEGIN_NIC0
13627. BEGIN_NV04
13628. BEGIN_NVC0
13629. BEGIN_RING
13630. BEH_NEVR
13631. BEH_TRAN_FLT
13632. BEH_TRAN_RNG
13633. BEISCSI_ASYNC_HDQ_SIZE
13634. BEISCSI_BIND_Q_TO_ULP_BIT
13635. BEISCSI_BOOT_CREATE_KSET
13636. BEISCSI_BOOT_GET_SHANDLE
13637. BEISCSI_BOOT_GET_SINFO
13638. BEISCSI_BOOT_LOGOUT_SESS
13639. BEISCSI_BOOT_REOPEN_SESS
13640. BEISCSI_CMDS_H
13641. BEISCSI_CMD_PER_LUN
13642. BEISCSI_DEFQ_DATA
13643. BEISCSI_DEFQ_HDR
13644. BEISCSI_DUAL_ULP_AWARE_BIT
13645. BEISCSI_EQD_UPDATE_INTERVAL
13646. BEISCSI_EQ_DELAY_DEF
13647. BEISCSI_EQ_DELAY_MAX
13648. BEISCSI_EQ_DELAY_MIN
13649. BEISCSI_FUNC_DUA_MODE
13650. BEISCSI_FUNC_ISCSI_INI_MODE
13651. BEISCSI_FW_MBX_TIMEOUT
13652. BEISCSI_GET_CID_COUNT
13653. BEISCSI_GET_ULP_FROM_CRI
13654. BEISCSI_H
13655. BEISCSI_HBA_BOOT_FOUND
13656. BEISCSI_HBA_BOOT_WORK
13657. BEISCSI_HBA_FW_TIMEOUT
13658. BEISCSI_HBA_IN_ERR
13659. BEISCSI_HBA_IN_TPE
13660. BEISCSI_HBA_IN_UE
13661. BEISCSI_HBA_LINK_UP
13662. BEISCSI_HBA_ONLINE
13663. BEISCSI_HBA_PCI_ERR
13664. BEISCSI_HBA_UER_SUPP
13665. BEISCSI_HOST_MBX_TIMEOUT
13666. BEISCSI_IP_TYPE_AUTO_V6
13667. BEISCSI_IP_TYPE_DHCP_V4
13668. BEISCSI_IP_TYPE_LINK_LOCAL_V6
13669. BEISCSI_IP_TYPE_ROUTABLE_V6
13670. BEISCSI_IP_TYPE_STATIC_V4
13671. BEISCSI_IP_TYPE_V4
13672. BEISCSI_IP_TYPE_V6
13673. BEISCSI_LOG_CONFIG
13674. BEISCSI_LOG_EH
13675. BEISCSI_LOG_INIT
13676. BEISCSI_LOG_IO
13677. BEISCSI_LOG_ISCSI
13678. BEISCSI_LOG_MBOX
13679. BEISCSI_LOG_MISC
13680. BEISCSI_MAX_CMD_LEN
13681. BEISCSI_MAX_CXNS
13682. BEISCSI_MAX_FRAGS_INIT
13683. BEISCSI_MAX_NUM_CPUS
13684. BEISCSI_MAX_RECV_DATASEG_LEN
13685. BEISCSI_MAX_SECTORS
13686. BEISCSI_MBX_RDY_BIT_TIMEOUT
13687. BEISCSI_NUM_MAX_LUN
13688. BEISCSI_PHYS_PORT_MAX
13689. BEISCSI_READ_FLASH
13690. BEISCSI_RW_ATTR
13691. BEISCSI_SGLIST_ELEMENTS
13692. BEISCSI_SYSFS_ISCSI_BOOT_FLAGS
13693. BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE
13694. BEISCSI_TEMPLATE_HDR_TYPE_ISCSI
13695. BEISCSI_UE_DETECT_INTERVAL
13696. BEISCSI_ULP0
13697. BEISCSI_ULP0_AVLBL_CID
13698. BEISCSI_ULP0_LOADED
13699. BEISCSI_ULP1
13700. BEISCSI_ULP1_AVLBL_CID
13701. BEISCSI_ULP1_LOADED
13702. BEISCSI_ULP_AVLBL_CID
13703. BEISCSI_ULP_COUNT
13704. BEISCSI_ULP_ISCSI_INI_MODE
13705. BEISCSI_VER_STRLEN
13706. BEISCSI_VLAN_DISABLE
13707. BEISCSI_WRITE_FLASH
13708. BELKIN_DOCKSTATION_PID
13709. BELKIN_DOCKSTATION_VID
13710. BELKIN_HIDDEV
13711. BELKIN_OLD_PID
13712. BELKIN_OLD_VID
13713. BELKIN_PRODUCT_ID
13714. BELKIN_SA_BAUD
13715. BELKIN_SA_DATA_BITS
13716. BELKIN_SA_FLOW_ERRSUB
13717. BELKIN_SA_FLOW_IDSR
13718. BELKIN_SA_FLOW_IDTR
13719. BELKIN_SA_FLOW_IRTS
13720. BELKIN_SA_FLOW_IXON
13721. BELKIN_SA_FLOW_NONE
13722. BELKIN_SA_FLOW_OCTS
13723. BELKIN_SA_FLOW_ODSR
13724. BELKIN_SA_FLOW_ORTS
13725. BELKIN_SA_FLOW_OXON
13726. BELKIN_SA_GET_MODEM_STATUS
13727. BELKIN_SA_LSR_BI
13728. BELKIN_SA_LSR_ERR
13729. BELKIN_SA_LSR_FE
13730. BELKIN_SA_LSR_INDEX
13731. BELKIN_SA_LSR_OE
13732. BELKIN_SA_LSR_PE
13733. BELKIN_SA_LSR_RDR
13734. BELKIN_SA_LSR_TE
13735. BELKIN_SA_LSR_THE
13736. BELKIN_SA_MSR_CD
13737. BELKIN_SA_MSR_CTS
13738. BELKIN_SA_MSR_DCD
13739. BELKIN_SA_MSR_DCTS
13740. BELKIN_SA_MSR_DDSR
13741. BELKIN_SA_MSR_DRI
13742. BELKIN_SA_MSR_DSR
13743. BELKIN_SA_MSR_INDEX
13744. BELKIN_SA_MSR_RI
13745. BELKIN_SA_PARITY_EVEN
13746. BELKIN_SA_PARITY_MARK
13747. BELKIN_SA_PARITY_NONE
13748. BELKIN_SA_PARITY_ODD
13749. BELKIN_SA_PARITY_SPACE
13750. BELKIN_SA_PID
13751. BELKIN_SA_RESET
13752. BELKIN_SA_SET_BAUDRATE_REQUEST
13753. BELKIN_SA_SET_BREAK_REQUEST
13754. BELKIN_SA_SET_DATA_BITS_REQUEST
13755. BELKIN_SA_SET_DTR_REQUEST
13756. BELKIN_SA_SET_FLOW_CTRL_REQUEST
13757. BELKIN_SA_SET_MAGIC_REQUEST
13758. BELKIN_SA_SET_PARITY_REQUEST
13759. BELKIN_SA_SET_REQUEST_TYPE
13760. BELKIN_SA_SET_RTS_REQUEST
13761. BELKIN_SA_SET_STOP_BITS_REQUEST
13762. BELKIN_SA_STOP_BITS
13763. BELKIN_SA_VID
13764. BELKIN_USB_VIDEOBUS_II
13765. BELKIN_VENDOR_ID
13766. BELKIN_VIDEOBUS
13767. BELKIN_VIDEOBUS_II
13768. BELKIN_WKBD
13769. BELL0
13770. BELL2
13771. BELL_POS
13772. BELT_AND_BRACES
13773. BELT_MULTIPLIER
13774. BEM
13775. BEMP
13776. BEMP0
13777. BEMP1
13778. BEMP2
13779. BEMP3
13780. BEMP4
13781. BEMP5
13782. BEMP6
13783. BEMP7
13784. BEMP8
13785. BEMP9
13786. BEMPE
13787. BEMPENB
13788. BEMPSTS
13789. BENABLE
13790. BENCHMARKING
13791. BENCHMARK_EVENT_STRLEN
13792. BENCH_FORMAT_DEFAULT
13793. BENCH_FORMAT_DEFAULT_STR
13794. BENCH_FORMAT_SIMPLE
13795. BENCH_FORMAT_SIMPLE_STR
13796. BENCH_FORMAT_UNKNOWN
13797. BENCH_H
13798. BENCH_L2FWD
13799. BENCH_RXDROP
13800. BENCH_SIZE
13801. BENCH_TXONLY
13802. BEND_IDX
13803. BENQ_PRODUCT_H10
13804. BENQ_PRODUCT_ID_S81
13805. BENQ_VENDOR_ID
13806. BEQDA
13807. BEQUIET
13808. BERCNFLG_S
13809. BERCNFLG_S_BERDCHK
13810. BERCNFLG_S_BERDRDY
13811. BERCNFLG_S_BERVCHK
13812. BERCNFLG_S_BERVRDY
13813. BERFLG_T
13814. BERFLG_T_BERDCHK
13815. BERFLG_T_BERDRDY
13816. BERFLG_T_BERVCHKA
13817. BERFLG_T_BERVCHKB
13818. BERFLG_T_BERVCHKC
13819. BERFLG_T_BERVRDYA
13820. BERFLG_T_BERVRDYB
13821. BERFLG_T_BERVRDYC
13822. BERLENRDL_T
13823. BERLENRDU_T
13824. BERLIN2_ADC_CHANNEL
13825. BERLIN2_AVPLL_BIT_QUIRK
13826. BERLIN2_AVPLL_SCRAMBLE_QUIRK
13827. BERLIN2_DIV_D3SWITCH
13828. BERLIN2_DIV_GATE
13829. BERLIN2_DIV_HAS_GATE
13830. BERLIN2_DIV_HAS_MUX
13831. BERLIN2_DIV_SELECT
13832. BERLIN2_DIV_SWITCH
13833. BERLIN2_PLL_SELECT
13834. BERLIN2_PLL_SWITCH
13835. BERLIN2_SINGLE_DIV
13836. BERLIN2_SM_ADC_DATA
13837. BERLIN2_SM_ADC_MASK
13838. BERLIN2_SM_ADC_STATUS
13839. BERLIN2_SM_ADC_STATUS_DATA_RDY
13840. BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK
13841. BERLIN2_SM_ADC_STATUS_INT_EN
13842. BERLIN2_SM_ADC_STATUS_INT_EN_MASK
13843. BERLIN2_SM_CTRL
13844. BERLIN2_SM_CTRL_ADC_BANDGAP_RDY
13845. BERLIN2_SM_CTRL_ADC_BUFFER_EN
13846. BERLIN2_SM_CTRL_ADC_CLKSEL_DIV2
13847. BERLIN2_SM_CTRL_ADC_CLKSEL_DIV3
13848. BERLIN2_SM_CTRL_ADC_CLKSEL_DIV4
13849. BERLIN2_SM_CTRL_ADC_CLKSEL_DIV8
13850. BERLIN2_SM_CTRL_ADC_CLKSEL_MASK
13851. BERLIN2_SM_CTRL_ADC_CONT_CONTINUOUS
13852. BERLIN2_SM_CTRL_ADC_CONT_SINGLE
13853. BERLIN2_SM_CTRL_ADC_POWER
13854. BERLIN2_SM_CTRL_ADC_RESET
13855. BERLIN2_SM_CTRL_ADC_ROTATE
13856. BERLIN2_SM_CTRL_ADC_SEL
13857. BERLIN2_SM_CTRL_ADC_SEL_MASK
13858. BERLIN2_SM_CTRL_ADC_START
13859. BERLIN2_SM_CTRL_ADC_VREF_EXT
13860. BERLIN2_SM_CTRL_ADC_VREF_INT
13861. BERLIN2_SM_CTRL_SM_SOC_INT
13862. BERLIN2_SM_CTRL_SOC_SM_INT
13863. BERLIN2_SM_CTRL_TSEN_CLK_SEL_125
13864. BERLIN2_SM_CTRL_TSEN_CLK_SEL_250
13865. BERLIN2_SM_CTRL_TSEN_EN
13866. BERLIN2_SM_CTRL_TSEN_MODE_0_125
13867. BERLIN2_SM_CTRL_TSEN_MODE_10_50
13868. BERLIN2_SM_CTRL_TSEN_RESET
13869. BERLIN2_SM_TSEN_CTRL
13870. BERLIN2_SM_TSEN_CTRL_SETTLING_12
13871. BERLIN2_SM_TSEN_CTRL_SETTLING_4
13872. BERLIN2_SM_TSEN_CTRL_SETTLING_MASK
13873. BERLIN2_SM_TSEN_CTRL_START
13874. BERLIN2_SM_TSEN_CTRL_TRIM
13875. BERLIN2_SM_TSEN_CTRL_TRIM_MASK
13876. BERLIN2_SM_TSEN_DATA
13877. BERLIN2_SM_TSEN_MASK
13878. BERLIN2_SM_TSEN_STATUS
13879. BERLIN2_SM_TSEN_STATUS_DATA_RDY
13880. BERLIN2_SM_TSEN_STATUS_INT_EN
13881. BERLIN_MAX_RESETS
13882. BERLIN_PINCTRL_FUNCTION
13883. BERLIN_PINCTRL_FUNCTION_UNKNOWN
13884. BERLIN_PINCTRL_GROUP
13885. BERLIN_PWM_CONTROL
13886. BERLIN_PWM_DUTY
13887. BERLIN_PWM_EN
13888. BERLIN_PWM_ENABLE
13889. BERLIN_PWM_INVERT_POLARITY
13890. BERLIN_PWM_MAX_TCNT
13891. BERLIN_PWM_PRESCALE_4096
13892. BERLIN_PWM_TCNT
13893. BERRDL_T
13894. BERRDM_T
13895. BERRDU_T
13896. BERREN
13897. BERVRDL_S
13898. BERVRDU_S
13899. BER_CONTROL
13900. BER_CTRL
13901. BER_DONE
13902. BER_ENABLE
13903. BER_OVERFLOW
13904. BER_PAY
13905. BER_PKTOVERFLOW
13906. BER_PKT_L
13907. BER_RESET
13908. BER_SAMPLING_RATE
13909. BER_SRC_S
13910. BER_SRC_S2
13911. BESCR_GE
13912. BESCR_PME
13913. BESCR_PMEO
13914. BEST
13915. BEST_EFFORT_LATENCY_TOLERANCE
13916. BETA_BASE
13917. BETA_MAX
13918. BETA_MIN
13919. BETA_SCALE
13920. BETA_SHIFT
13921. BETID0_CTRL
13922. BETID3_CTRL
13923. BETTER_THAN_486
13924. BETWEEN
13925. BEU1
13926. BEXTSIGCLKENABLE
13927. BEXT_LNA_GAIN
13928. BE_ADMTIME
13929. BE_ADMTM
13930. BE_AN_EN
13931. BE_ASYNC_LINK_UP_MASK
13932. BE_BOOT_INVALID_SHANDLE
13933. BE_BROADCAST_PACKET
13934. BE_CLEANUP_TYPE_INVALIDATE
13935. BE_CLEANUP_TYPE_ISSUE_TCP_RST
13936. BE_CLEAR_ALL
13937. BE_CMD_MAX_DRV_VERSION
13938. BE_CMD_SET_FEATURE_UER
13939. BE_CMD_SET_HOST_PARAM_ID
13940. BE_CMD_UER_SUPP_BIT
13941. BE_DEVICE_ID1
13942. BE_DEVICE_ID2
13943. BE_DEV_SHUTDOWN
13944. BE_DISABLE_TPE_RECOVERY
13945. BE_ERROR_ANY
13946. BE_ERROR_EEH
13947. BE_ERROR_FW
13948. BE_ERROR_HW
13949. BE_ERROR_TX
13950. BE_ERROR_UE
13951. BE_ETH_TX_RING_TYPE_STANDARD
13952. BE_FEATURE_UE_RECOVERY
13953. BE_FLAGS_ERR_DETECTION_SCHEDULED
13954. BE_FLAGS_LINK_STATUS_INIT
13955. BE_FLAGS_NAPI_ENABLED
13956. BE_FLAGS_OS2BMC
13957. BE_FLAGS_PHY_MISCONFIGURED
13958. BE_FLAGS_QNQ_ASYNC_EVT_RCVD
13959. BE_FLAGS_SETUP_DONE
13960. BE_FLAGS_SRIOV_ENABLED
13961. BE_FLAGS_TRY_RECOVERY
13962. BE_FLAGS_VXLAN_OFFLOADS
13963. BE_FLAGS_WORKER_SCHEDULED
13964. BE_FUNCTION_CAPS_RSS
13965. BE_FUNCTION_CAPS_SUPER_NIC
13966. BE_GEN2
13967. BE_GEN3
13968. BE_GEN4
13969. BE_GET_ASYNC_CRI_FROM_CID
13970. BE_GET_CRI_FROM_CID
13971. BE_GET_WOL_CAP
13972. BE_H
13973. BE_HDR_LEN
13974. BE_HOUR
13975. BE_IF_ALL_FILT_FLAGS
13976. BE_IF_CAP_FLAGS_WANT
13977. BE_IF_FILT_FLAGS_BASIC
13978. BE_IF_FLAGS_ALL_PROMISCUOUS
13979. BE_IF_FLAGS_BROADCAST
13980. BE_IF_FLAGS_DEFQ_RSS
13981. BE_IF_FLAGS_MCAST_PROMISCUOUS
13982. BE_IF_FLAGS_MULTICAST
13983. BE_IF_FLAGS_PASS_L2_ERRORS
13984. BE_IF_FLAGS_PASS_L3L4_ERRORS
13985. BE_IF_FLAGS_PROMISCUOUS
13986. BE_IF_FLAGS_RSS
13987. BE_IF_FLAGS_ULP
13988. BE_IF_FLAGS_UNTAGGED
13989. BE_IF_FLAGS_VLAN
13990. BE_IF_FLAGS_VLAN_PROMISCUOUS
13991. BE_INI_ALIAS_LEN
13992. BE_INTERRUPT_MODE_INTX
13993. BE_INTERRUPT_MODE_MSI
13994. BE_INTERRUPT_MODE_MSIX
13995. BE_INVALID_CID
13996. BE_INVALID_DIE_TEMP
13997. BE_INVLDT_CMD_TBL_SZ
13998. BE_ISCSI_PDU_HEADER_SIZE
13999. BE_MAC_LOOPBACK
14000. BE_MASK
14001. BE_MAX_EQD
14002. BE_MAX_GSO_SIZE
14003. BE_MAX_JUMBO_FRAME_SIZE
14004. BE_MAX_MAC
14005. BE_MAX_MC
14006. BE_MAX_MTU
14007. BE_MAX_SESSION
14008. BE_MAX_TX_FRAG_COUNT
14009. BE_MIN
14010. BE_MIN_MEM_SIZE
14011. BE_MIN_MTU
14012. BE_MULTICAST_PACKET
14013. BE_NAME
14014. BE_NAPI_WEIGHT
14015. BE_NO_LOOPBACK
14016. BE_NUMBER_OF_FIELD
14017. BE_NUM_VLANS_SUPPORTED
14018. BE_ONE_PORT_EXT_LOOPBACK
14019. BE_PAUSE_SYM_EN
14020. BE_PHY_DIFF_MEDIA
14021. BE_PHY_FUNCTIONAL
14022. BE_PHY_INCOMPATIBLE
14023. BE_PHY_LOOPBACK
14024. BE_PHY_NOT_PRESENT
14025. BE_PHY_UNCERTIFIED
14026. BE_PHY_UNQUALIFIED
14027. BE_PME_D0_CAP
14028. BE_PME_D1_CAP
14029. BE_PME_D2_CAP
14030. BE_PME_D3COLD_CAP
14031. BE_PME_D3HOT_CAP
14032. BE_PRIORITY
14033. BE_PRIV_DEFAULT
14034. BE_PRIV_DEVCFG
14035. BE_PRIV_DEVSEC
14036. BE_PRIV_FILTMGMT
14037. BE_PRIV_IFACEMGMT
14038. BE_PRIV_LNKDIAG
14039. BE_PRIV_LNKMGMT
14040. BE_PRIV_LNKQUERY
14041. BE_PRIV_LNKSTATS
14042. BE_PRIV_UTILQUERY
14043. BE_PRIV_VHADM
14044. BE_PTR
14045. BE_Q
14046. BE_QID_01
14047. BE_QID_02
14048. BE_QOS_BITS_NIC
14049. BE_QUEUE
14050. BE_QUEUE_INX
14051. BE_READ_SEEPROM_LEN
14052. BE_REOPEN_ALL_SESSIONS
14053. BE_REOPEN_A_SESSION
14054. BE_REOPEN_BOOT_SESSIONS
14055. BE_RESET_VLAN_TAG_ID
14056. BE_ROCE_ABI_VERSION
14057. BE_ROCE_H
14058. BE_RSVD_PACKET
14059. BE_RX_RING_MAX
14060. BE_RX_RING_MIN
14061. BE_RX_RING_SIZE
14062. BE_RX_SKB_ALLOC_SIZE
14063. BE_SEC
14064. BE_SENSE_INFO_SIZE
14065. BE_SESS_STATUS_CLOSE
14066. BE_SET_CID_TO_CRI
14067. BE_SHIFT
14068. BE_SUPPORTED_SPEED_100MBPS
14069. BE_SUPPORTED_SPEED_10GBPS
14070. BE_SUPPORTED_SPEED_10MBPS
14071. BE_SUPPORTED_SPEED_1GBPS
14072. BE_SUPPORTED_SPEED_20GBPS
14073. BE_SUPPORTED_SPEED_40GBPS
14074. BE_SUPPORTED_SPEED_NONE
14075. BE_TABLE_ROWS
14076. BE_TABLE_SIZE
14077. BE_TGT_CTX_UPDT_CMD
14078. BE_TXP_SW_SZ
14079. BE_TX_COMP_ACL_ERR
14080. BE_TX_COMP_HDR_PARSE_ERR
14081. BE_TX_COMP_NDMA_ERR
14082. BE_TX_RING_MAX
14083. BE_TX_RING_MIN
14084. BE_TX_RING_SIZE
14085. BE_TYPE_b1
14086. BE_TYPE_b2
14087. BE_TYPE_b4
14088. BE_TYPE_b8
14089. BE_UC_PMAC_COUNT
14090. BE_UE_RECOVERY_UER_MASK
14091. BE_ULP1_NUM
14092. BE_UNICAST_PACKET
14093. BE_UNKNOWN_PHY_STATE
14094. BE_UPLOAD_TYPE_ABORT
14095. BE_UPLOAD_TYPE_ABORT_RESET
14096. BE_UPLOAD_TYPE_ABORT_WITH_SEQ
14097. BE_UPLOAD_TYPE_GRACEFUL
14098. BE_VENDOR_ID
14099. BE_VERBOSE
14100. BE_VF_IF_EN_FLAGS
14101. BE_VF_UC_PMAC_COUNT
14102. BE_WOL_CAP
14103. BE_WRB_F_BIT
14104. BE_WRB_F_CRC_BIT
14105. BE_WRB_F_GET
14106. BE_WRB_F_IPCS_BIT
14107. BE_WRB_F_LSO6_BIT
14108. BE_WRB_F_LSO_BIT
14109. BE_WRB_F_MASK
14110. BE_WRB_F_OS2BMC_BIT
14111. BE_WRB_F_SET
14112. BE_WRB_F_TCPCS_BIT
14113. BE_WRB_F_UDPCS_BIT
14114. BE_WRB_F_VLAN_BIT
14115. BE_WRB_F_VLAN_SKIP_HW_BIT
14116. BE_WRB_TYPE_OFFSET
14117. BEx_chip
14118. BEx_get_resources
14119. BF
14120. BF1_CA
14121. BF1_PAXCA
14122. BF2_1CA
14123. BF2_1PAXCA
14124. BFA
14125. BFAD_BSG_H
14126. BFAD_CFG_PPORT_DONE
14127. BFAD_DRIVER_NAME
14128. BFAD_DRIVER_VERSION
14129. BFAD_DRV_INIT_DONE
14130. BFAD_EEH_BUSY
14131. BFAD_EEH_PCI_CHANNEL_IO_PERM_FAILURE
14132. BFAD_E_CREATE
14133. BFAD_E_EXIT_COMP
14134. BFAD_E_FCS_EXIT_COMP
14135. BFAD_E_HAL_INIT_FAILED
14136. BFAD_E_INIT
14137. BFAD_E_INIT_FAILED
14138. BFAD_E_INIT_SUCCESS
14139. BFAD_E_KTHREAD_CREATE_FAILED
14140. BFAD_E_STOP
14141. BFAD_FC4_PROBE_DONE
14142. BFAD_FCS_INIT_DONE
14143. BFAD_FW_FILE_CB
14144. BFAD_FW_FILE_CT
14145. BFAD_FW_FILE_CT2
14146. BFAD_HAL_INIT_DONE
14147. BFAD_HAL_INIT_FAIL
14148. BFAD_HAL_START_DONE
14149. BFAD_INTX_ON
14150. BFAD_IO_MAX_SGE
14151. BFAD_IRQ_FLAGS
14152. BFAD_LUN_QUEUE_DEPTH
14153. BFAD_LUN_RESET_TMO
14154. BFAD_MAX_SECTORS
14155. BFAD_MIN_SECTORS
14156. BFAD_MSIX_ON
14157. BFAD_NL_VENDOR_ID
14158. BFAD_PORT_DELETE
14159. BFAD_PORT_ONLINE
14160. BFAD_PORT_PHYS_BASE
14161. BFAD_PORT_PHYS_VPORT
14162. BFAD_PORT_VF_BASE
14163. BFAD_PORT_VF_VPORT
14164. BFAD_PROTO_NAME
14165. BFAD_RPORT_ONLINE
14166. BFAD_STOP_TIMEOUT
14167. BFAD_SUSPEND_TIMEOUT
14168. BFAD_TARGET_RESET_TMO
14169. BFA_ABLK_MAX
14170. BFA_ABLK_MAX_PFS
14171. BFA_ABLK_MAX_PORTS
14172. BFA_ADAPTER_AEN_ADD
14173. BFA_ADAPTER_AEN_REMOVE
14174. BFA_ADAPTER_MFG_NAME_LEN
14175. BFA_ADAPTER_MODEL_DESCR_LEN
14176. BFA_ADAPTER_MODEL_NAME_LEN
14177. BFA_ADAPTER_OS_TYPE_LEN
14178. BFA_ADAPTER_SERIAL_NUM_LEN
14179. BFA_ADAPTER_SYM_NAME_LEN
14180. BFA_ADAPTER_UUID_LEN
14181. BFA_AEN_CAT_ADAPTER
14182. BFA_AEN_CAT_AUDIT
14183. BFA_AEN_CAT_IOC
14184. BFA_AEN_CAT_ITNIM
14185. BFA_AEN_CAT_LPORT
14186. BFA_AEN_CAT_PORT
14187. BFA_AEN_CAT_RPORT
14188. BFA_AEN_MAX_ENTRY
14189. BFA_AUDIT_AEN_AUTH_DISABLE
14190. BFA_AUDIT_AEN_AUTH_ENABLE
14191. BFA_AUDIT_AEN_FLASH_ERASE
14192. BFA_AUDIT_AEN_FLASH_UPDATE
14193. BFA_BBCR_DISABLED
14194. BFA_BBCR_ERR_REASON_FLOGI_RJT
14195. BFA_BBCR_ERR_REASON_NONE
14196. BFA_BBCR_ERR_REASON_NON_BRCD_SW
14197. BFA_BBCR_ERR_REASON_PEER_UNSUP
14198. BFA_BBCR_ERR_REASON_SPEED_UNSUP
14199. BFA_BBCR_OFFLINE
14200. BFA_BBCR_ONLINE
14201. BFA_BB_SCN_DEF
14202. BFA_BB_SCN_MAX
14203. BFA_BOOT_AUTO_DISCOVER
14204. BFA_BOOT_BOOTLUN_MAX
14205. BFA_BOOT_FIRST_LUN
14206. BFA_BOOT_PBC
14207. BFA_BOOT_STORED_BLUN
14208. BFA_CACHELINE_SZ
14209. BFA_CEE_DCBX_MAX_PGID
14210. BFA_CEE_DCBX_MAX_PRIORITY
14211. BFA_CEE_LLDP_MAX_STRING_LEN
14212. BFA_CEE_LLDP_SYS_CAP_CVLAN
14213. BFA_CEE_LLDP_SYS_CAP_DOCSIS_CD
14214. BFA_CEE_LLDP_SYS_CAP_MAC_BRIDGE
14215. BFA_CEE_LLDP_SYS_CAP_OTHER
14216. BFA_CEE_LLDP_SYS_CAP_REPEATER
14217. BFA_CEE_LLDP_SYS_CAP_ROUTER
14218. BFA_CEE_LLDP_SYS_CAP_STATION
14219. BFA_CEE_LLDP_SYS_CAP_SVLAN
14220. BFA_CEE_LLDP_SYS_CAP_TELEPHONE
14221. BFA_CEE_LLDP_SYS_CAP_TPMR
14222. BFA_CEE_LLDP_SYS_CAP_WLAN_AP
14223. BFA_CM_CNA
14224. BFA_CM_FC16G
14225. BFA_CM_HBA
14226. BFA_CM_MEZZ
14227. BFA_CM_NIC
14228. BFA_CM_SRIOV
14229. BFA_DBG_FWTRC_ENTS
14230. BFA_DBG_FWTRC_LEN
14231. BFA_DBG_FWTRC_OFF
14232. BFA_DCONF_MOD
14233. BFA_DCONF_SM_EXIT
14234. BFA_DCONF_SM_FLASH_COMP
14235. BFA_DCONF_SM_INIT
14236. BFA_DCONF_SM_IOCDISABLE
14237. BFA_DCONF_SM_TIMEOUT
14238. BFA_DCONF_SM_WR
14239. BFA_DCONF_UPDATE_TOV
14240. BFA_DEBUG_FW_CORE_CHUNK_SZ
14241. BFA_DIAG_MEMTEST_TOV
14242. BFA_DIAG_MOD
14243. BFA_DIAG_QTEST_TOV
14244. BFA_DMA_ALIGN_SZ
14245. BFA_DPORT_OPMODE_AUTO
14246. BFA_DPORT_OPMODE_MANU
14247. BFA_DPORT_SM_DISABLE
14248. BFA_DPORT_SM_ENABLE
14249. BFA_DPORT_SM_FWRSP
14250. BFA_DPORT_SM_HWFAIL
14251. BFA_DPORT_SM_QRESUME
14252. BFA_DPORT_SM_REQFAIL
14253. BFA_DPORT_SM_SCN
14254. BFA_DPORT_SM_START
14255. BFA_DPORT_ST_COMP
14256. BFA_DPORT_ST_DISABLED
14257. BFA_DPORT_ST_INP
14258. BFA_DPORT_ST_NOTSTART
14259. BFA_DPORT_ST_NO_SFP
14260. BFA_EPROTO_BAD_ACCEPT
14261. BFA_EPROTO_UNKNOWN_RSP
14262. BFA_FAA_DISABLED
14263. BFA_FAA_ENABLED
14264. BFA_FALSE
14265. BFA_FCDIAG_MOD
14266. BFA_FCPIM
14267. BFA_FCPIM_PATHTOV_DEF
14268. BFA_FCPIM_PATHTOV_MAX
14269. BFA_FCPORT
14270. BFA_FCPORT_LN_SM_LINKDOWN
14271. BFA_FCPORT_LN_SM_LINKUP
14272. BFA_FCPORT_LN_SM_NOTIFICATION
14273. BFA_FCPORT_MOD
14274. BFA_FCPORT_SM_DDPORTDISABLE
14275. BFA_FCPORT_SM_DDPORTENABLE
14276. BFA_FCPORT_SM_DISABLE
14277. BFA_FCPORT_SM_DPORTDISABLE
14278. BFA_FCPORT_SM_DPORTENABLE
14279. BFA_FCPORT_SM_ENABLE
14280. BFA_FCPORT_SM_FAA_MISCONFIG
14281. BFA_FCPORT_SM_FWRSP
14282. BFA_FCPORT_SM_HWFAIL
14283. BFA_FCPORT_SM_LINKDOWN
14284. BFA_FCPORT_SM_LINKUP
14285. BFA_FCPORT_SM_QRESUME
14286. BFA_FCPORT_SM_START
14287. BFA_FCPORT_SM_STOP
14288. BFA_FCPORT_STATS_TOV
14289. BFA_FCP_DMA_SEGS
14290. BFA_FCP_MOD
14291. BFA_FCS_BRCD_SWITCH_OUI
14292. BFA_FCS_FABRIC_CLEANUP_DELAY
14293. BFA_FCS_FABRIC_IPADDR_SZ
14294. BFA_FCS_FABRIC_LOOP
14295. BFA_FCS_FABRIC_N2N
14296. BFA_FCS_FABRIC_RETRY_DELAY
14297. BFA_FCS_FABRIC_SM_AUTH_FAILED
14298. BFA_FCS_FABRIC_SM_AUTH_SUCCESS
14299. BFA_FCS_FABRIC_SM_CONT_OP
14300. BFA_FCS_FABRIC_SM_CREATE
14301. BFA_FCS_FABRIC_SM_DELAYED
14302. BFA_FCS_FABRIC_SM_DELCOMP
14303. BFA_FCS_FABRIC_SM_DELETE
14304. BFA_FCS_FABRIC_SM_ISOLATE
14305. BFA_FCS_FABRIC_SM_LINK_DOWN
14306. BFA_FCS_FABRIC_SM_LINK_UP
14307. BFA_FCS_FABRIC_SM_LOGOCOMP
14308. BFA_FCS_FABRIC_SM_LOOPBACK
14309. BFA_FCS_FABRIC_SM_NO_FABRIC
14310. BFA_FCS_FABRIC_SM_NO_TAGGING
14311. BFA_FCS_FABRIC_SM_PERF_EVFP
14312. BFA_FCS_FABRIC_SM_RETRY_OP
14313. BFA_FCS_FABRIC_SM_START
14314. BFA_FCS_FABRIC_SM_STOP
14315. BFA_FCS_FABRIC_SM_STOPCOMP
14316. BFA_FCS_FABRIC_SWITCHED
14317. BFA_FCS_FABRIC_UNKNOWN
14318. BFA_FCS_FDMI_CMD_MAX_RETRIES
14319. BFA_FCS_FDMI_FC4_TYPE_LEN
14320. BFA_FCS_FDMI_SUPP_SPEEDS_10G
14321. BFA_FCS_FDMI_SUPP_SPEEDS_16G
14322. BFA_FCS_FDMI_SUPP_SPEEDS_4G
14323. BFA_FCS_FDMI_SUPP_SPEEDS_8G
14324. BFA_FCS_FDMI_VENDOR_INFO_LEN
14325. BFA_FCS_GET_FDMI_FROM_PORT
14326. BFA_FCS_GET_HAL_FROM_PORT
14327. BFA_FCS_GET_MS_FROM_PORT
14328. BFA_FCS_GET_NS_FROM_PORT
14329. BFA_FCS_GET_SCN_FROM_PORT
14330. BFA_FCS_ITNIM_SM_DELETE
14331. BFA_FCS_ITNIM_SM_FCS_ONLINE
14332. BFA_FCS_ITNIM_SM_FRMSENT
14333. BFA_FCS_ITNIM_SM_HAL_ONLINE
14334. BFA_FCS_ITNIM_SM_HCB_OFFLINE
14335. BFA_FCS_ITNIM_SM_HCB_ONLINE
14336. BFA_FCS_ITNIM_SM_INITIATOR
14337. BFA_FCS_ITNIM_SM_OFFLINE
14338. BFA_FCS_ITNIM_SM_PRLO
14339. BFA_FCS_ITNIM_SM_RSP_ERROR
14340. BFA_FCS_ITNIM_SM_RSP_NOT_SUPP
14341. BFA_FCS_ITNIM_SM_RSP_OK
14342. BFA_FCS_ITNIM_SM_TIMEOUT
14343. BFA_FCS_MAX_LPORTS
14344. BFA_FCS_MAX_NS_RETRIES
14345. BFA_FCS_MAX_RPORTS_SUPP
14346. BFA_FCS_MAX_RPORT_LOGINS
14347. BFA_FCS_MS_CMD_MAX_RETRIES
14348. BFA_FCS_OS_STR_LEN
14349. BFA_FCS_PID_IS_WKA
14350. BFA_FCS_PORT_SM_CREATE
14351. BFA_FCS_PORT_SM_DELETE
14352. BFA_FCS_PORT_SM_DELRPORT
14353. BFA_FCS_PORT_SM_OFFLINE
14354. BFA_FCS_PORT_SM_ONLINE
14355. BFA_FCS_PORT_SM_STOP
14356. BFA_FCS_PORT_SYMBNAME_MACHINENAME_SZ
14357. BFA_FCS_PORT_SYMBNAME_MODEL_SZ
14358. BFA_FCS_PORT_SYMBNAME_OSINFO_SZ
14359. BFA_FCS_PORT_SYMBNAME_OSPATCH_SZ
14360. BFA_FCS_PORT_SYMBNAME_SEPARATOR
14361. BFA_FCS_PORT_SYMBNAME_VERSION_SZ
14362. BFA_FCS_RETRY_TIMEOUT
14363. BFA_FCS_RPF_RETRIES
14364. BFA_FCS_RPF_RETRY_TIMEOUT
14365. BFA_FCS_RPORT_DEF_DEL_TIMEOUT
14366. BFA_FCS_RPORT_MAX_RETRIES
14367. BFA_FCS_VPORT_CLEANUP
14368. BFA_FCS_VPORT_CREATED
14369. BFA_FCS_VPORT_DELETING
14370. BFA_FCS_VPORT_ERROR
14371. BFA_FCS_VPORT_FDISC
14372. BFA_FCS_VPORT_FDISC_RETRY
14373. BFA_FCS_VPORT_FDISC_RSP_WAIT
14374. BFA_FCS_VPORT_FDISC_SEND
14375. BFA_FCS_VPORT_IS_INITIATOR_MODE
14376. BFA_FCS_VPORT_LOGO
14377. BFA_FCS_VPORT_LOGO_SEND
14378. BFA_FCS_VPORT_MAX_RETRIES
14379. BFA_FCS_VPORT_MAX_STATE
14380. BFA_FCS_VPORT_OFFLINE
14381. BFA_FCS_VPORT_ONLINE
14382. BFA_FCS_VPORT_SM_CREATE
14383. BFA_FCS_VPORT_SM_DELCOMP
14384. BFA_FCS_VPORT_SM_DELETE
14385. BFA_FCS_VPORT_SM_FABRIC_MAX
14386. BFA_FCS_VPORT_SM_FRMSENT
14387. BFA_FCS_VPORT_SM_OFFLINE
14388. BFA_FCS_VPORT_SM_ONLINE
14389. BFA_FCS_VPORT_SM_RSP_DUP_WWN
14390. BFA_FCS_VPORT_SM_RSP_ERROR
14391. BFA_FCS_VPORT_SM_RSP_FAILED
14392. BFA_FCS_VPORT_SM_RSP_OK
14393. BFA_FCS_VPORT_SM_START
14394. BFA_FCS_VPORT_SM_STOP
14395. BFA_FCS_VPORT_SM_STOPCOMP
14396. BFA_FCS_VPORT_SM_TIMEOUT
14397. BFA_FCS_VPORT_UNINIT
14398. BFA_FCXP_DMA_SEGS
14399. BFA_FCXP_FROM_TAG
14400. BFA_FCXP_MAX
14401. BFA_FCXP_MAX_IBUF_SZ
14402. BFA_FCXP_MAX_LBUF_SZ
14403. BFA_FCXP_MAX_SGES
14404. BFA_FCXP_MIN
14405. BFA_FCXP_MOD
14406. BFA_FCXP_REQ_PLD
14407. BFA_FCXP_REQ_PLD_PA
14408. BFA_FCXP_RSP_FCHS
14409. BFA_FCXP_RSP_PLD
14410. BFA_FCXP_RSP_PLD_PA
14411. BFA_FEC_OFFLINE
14412. BFA_FEC_OFFLINE_NOT_16G
14413. BFA_FEC_ONLINE
14414. BFA_FLASH
14415. BFA_FLASH_BAD
14416. BFA_FLASH_BLOCKING_OP_MAX
14417. BFA_FLASH_BUSY
14418. BFA_FLASH_CHECK_MAX
14419. BFA_FLASH_DMA_BUF_SZ
14420. BFA_FLASH_ERR_CMD_ACT
14421. BFA_FLASH_ERR_FIFO_CNT
14422. BFA_FLASH_ERR_LEN
14423. BFA_FLASH_ERR_TIMEOUT
14424. BFA_FLASH_ERR_WIP
14425. BFA_FLASH_FAST_READ
14426. BFA_FLASH_FIFO_SIZE
14427. BFA_FLASH_NOT_PRESENT
14428. BFA_FLASH_PART_ASIC
14429. BFA_FLASH_PART_ASICBK
14430. BFA_FLASH_PART_BOOT
14431. BFA_FLASH_PART_BOOTOVL
14432. BFA_FLASH_PART_DRV
14433. BFA_FLASH_PART_ENTRY_SIZE
14434. BFA_FLASH_PART_FWCFG
14435. BFA_FLASH_PART_FWIMG
14436. BFA_FLASH_PART_FWIMG_ADDR
14437. BFA_FLASH_PART_LOG
14438. BFA_FLASH_PART_MAX
14439. BFA_FLASH_PART_MFG
14440. BFA_FLASH_PART_OPTROM
14441. BFA_FLASH_PART_OPTROM2
14442. BFA_FLASH_PART_PBC
14443. BFA_FLASH_PART_PORTCFG
14444. BFA_FLASH_PART_PXECFG
14445. BFA_FLASH_PART_PXEOVL
14446. BFA_FLASH_PART_VPD
14447. BFA_FLASH_READ_STATUS
14448. BFA_FLASH_SECTOR_ERASE
14449. BFA_FLASH_SEG_SZ
14450. BFA_FLASH_UNINIT
14451. BFA_FLASH_WIP_MASK
14452. BFA_FLASH_WRITE
14453. BFA_FLASH_WRITE_ENABLE
14454. BFA_FRU
14455. BFA_FRU_CHINOOK_MAX_SIZE
14456. BFA_FRU_DMA_BUF_SZ
14457. BFA_FRU_LIGHTNING_MAX_SIZE
14458. BFA_FWTIO_MAX
14459. BFA_FW_USE_COUNT
14460. BFA_I2HM
14461. BFA_IOBUCKET_MAX
14462. BFA_IOC0_HBEAT_REG
14463. BFA_IOC0_STATE_REG
14464. BFA_IOC1_HBEAT_REG
14465. BFA_IOC1_STATE_REG
14466. BFA_IOCFCOE_INTR_DELAY
14467. BFA_IOCFCOE_INTR_LATENCY
14468. BFA_IOCFC_ACT_DISABLE
14469. BFA_IOCFC_ACT_ENABLE
14470. BFA_IOCFC_ACT_INIT
14471. BFA_IOCFC_ACT_NONE
14472. BFA_IOCFC_ACT_STOP
14473. BFA_IOCFC_INTR_DELAY
14474. BFA_IOCFC_INTR_LATENCY
14475. BFA_IOCFC_PATHTOV_MAX
14476. BFA_IOCFC_QDEPTH_MAX
14477. BFA_IOCFC_TOV
14478. BFA_IOCPF_DISABLED
14479. BFA_IOCPF_DISABLING
14480. BFA_IOCPF_FAIL
14481. BFA_IOCPF_FWMISMATCH
14482. BFA_IOCPF_HWINIT
14483. BFA_IOCPF_INITFAIL
14484. BFA_IOCPF_READY
14485. BFA_IOCPF_RESET
14486. BFA_IOCPF_SEMWAIT
14487. BFA_IOC_ACQ_ADDR
14488. BFA_IOC_AEN_DISABLE
14489. BFA_IOC_AEN_ENABLE
14490. BFA_IOC_AEN_FWCFG_ERROR
14491. BFA_IOC_AEN_FWMISMATCH
14492. BFA_IOC_AEN_HBFAIL
14493. BFA_IOC_AEN_HBGOOD
14494. BFA_IOC_AEN_INVALID_NWWN
14495. BFA_IOC_AEN_INVALID_PWWN
14496. BFA_IOC_AEN_INVALID_VENDOR
14497. BFA_IOC_CB_FWSTATE_MASK
14498. BFA_IOC_CB_JOIN_MASK
14499. BFA_IOC_CB_JOIN_SH
14500. BFA_IOC_CHIP_REV_LEN
14501. BFA_IOC_DISABLED
14502. BFA_IOC_DISABLING
14503. BFA_IOC_DRIVER_LEN
14504. BFA_IOC_ENABLING
14505. BFA_IOC_E_DISABLED
14506. BFA_IOC_E_ENABLED
14507. BFA_IOC_E_FAILED
14508. BFA_IOC_FAIL
14509. BFA_IOC_FAIL_SYNC
14510. BFA_IOC_FLASH_CHUNK_ADDR
14511. BFA_IOC_FLASH_CHUNK_NO
14512. BFA_IOC_FLASH_OFFSET_IN_CHUNK
14513. BFA_IOC_FWIMG_MINSZ
14514. BFA_IOC_FWMISMATCH
14515. BFA_IOC_FW_INV_SIGN
14516. BFA_IOC_FW_SMEM_SIZE
14517. BFA_IOC_GETATTR
14518. BFA_IOC_HB_TOV
14519. BFA_IOC_HWFAIL
14520. BFA_IOC_HWINIT
14521. BFA_IOC_HWSEM_TOV
14522. BFA_IOC_INITFAIL
14523. BFA_IOC_OPERATIONAL
14524. BFA_IOC_PLL_POLL
14525. BFA_IOC_POLL_TOV
14526. BFA_IOC_RESET
14527. BFA_IOC_SEMWAIT
14528. BFA_IOC_SYNC_REQD_SH
14529. BFA_IOC_TOV
14530. BFA_IOC_TOV_RECOVER
14531. BFA_IOC_TYPE_FC
14532. BFA_IOC_TYPE_FCoE
14533. BFA_IOC_TYPE_LL
14534. BFA_IOC_UNINIT
14535. BFA_IOIM_FROM_TAG
14536. BFA_IOIM_IOTAG_MASK
14537. BFA_IOIM_LM_UA_RESET
14538. BFA_IOIM_LM_UA_SET
14539. BFA_IOIM_LUN_MASK_ACTIVE
14540. BFA_IOIM_LUN_MASK_FETCHED
14541. BFA_IOIM_LUN_MASK_INACTIVE
14542. BFA_IOIM_MAX
14543. BFA_IOIM_MIN
14544. BFA_IOIM_RETRY_MAX
14545. BFA_IOIM_RETRY_TAG_OFFSET
14546. BFA_IOIM_SM_ABORT
14547. BFA_IOIM_SM_ABORT_COMP
14548. BFA_IOIM_SM_ABORT_DONE
14549. BFA_IOIM_SM_CLEANUP
14550. BFA_IOIM_SM_COMP
14551. BFA_IOIM_SM_COMP_GOOD
14552. BFA_IOIM_SM_COMP_UTAG
14553. BFA_IOIM_SM_DONE
14554. BFA_IOIM_SM_FREE
14555. BFA_IOIM_SM_HCB
14556. BFA_IOIM_SM_HWFAIL
14557. BFA_IOIM_SM_IOTOV
14558. BFA_IOIM_SM_QRESUME
14559. BFA_IOIM_SM_SGALLOCED
14560. BFA_IOIM_SM_SQRETRY
14561. BFA_IOIM_SM_START
14562. BFA_IOIM_SM_TMDONE
14563. BFA_IOIM_SM_TMSTART
14564. BFA_IOIM_TAG_2_ID
14565. BFA_IOTAG_FROM_TAG
14566. BFA_IO_MAX
14567. BFA_ITNIM_AEN_DISCONNECT
14568. BFA_ITNIM_AEN_OFFLINE
14569. BFA_ITNIM_AEN_ONLINE
14570. BFA_ITNIM_FROM_TAG
14571. BFA_ITNIM_HCB_OFFLINE
14572. BFA_ITNIM_HCB_ONLINE
14573. BFA_ITNIM_INITIATIOR
14574. BFA_ITNIM_MAX
14575. BFA_ITNIM_MIN
14576. BFA_ITNIM_OFFLINE
14577. BFA_ITNIM_ONLINE
14578. BFA_ITNIM_PRLI_RETRY
14579. BFA_ITNIM_PRLI_SEND
14580. BFA_ITNIM_PRLI_SENT
14581. BFA_ITNIM_SM_CLEANUP
14582. BFA_ITNIM_SM_CREATE
14583. BFA_ITNIM_SM_DELETE
14584. BFA_ITNIM_SM_FWRSP
14585. BFA_ITNIM_SM_HWFAIL
14586. BFA_ITNIM_SM_OFFLINE
14587. BFA_ITNIM_SM_ONLINE
14588. BFA_ITNIM_SM_QRESUME
14589. BFA_ITNIM_SM_SLER
14590. BFA_ITN_FROM_TAG
14591. BFA_LOG
14592. BFA_LPORT_AEN_DELETE
14593. BFA_LPORT_AEN_DELETE_PROP
14594. BFA_LPORT_AEN_DELETE_STANDARD
14595. BFA_LPORT_AEN_DISCONNECT
14596. BFA_LPORT_AEN_NEW
14597. BFA_LPORT_AEN_NEW_PROP
14598. BFA_LPORT_AEN_NEW_STANDARD
14599. BFA_LPORT_AEN_NPIV_DUP_WWN
14600. BFA_LPORT_AEN_NPIV_FABRIC_MAX
14601. BFA_LPORT_AEN_NPIV_UNKNOWN
14602. BFA_LPORT_AEN_OFFLINE
14603. BFA_LPORT_AEN_ONLINE
14604. BFA_LPORT_FDISC
14605. BFA_LPORT_OFFLINE
14606. BFA_LPORT_OFFLINE_FAB_LOGOUT
14607. BFA_LPORT_OFFLINE_FAB_NORESOURCES
14608. BFA_LPORT_OFFLINE_FAB_UNSUPPORTED
14609. BFA_LPORT_OFFLINE_LINKDOWN
14610. BFA_LPORT_OFFLINE_UNKNOWN
14611. BFA_LPORT_ONLINE
14612. BFA_LPORT_ROLE_FCP_IM
14613. BFA_LPORT_ROLE_FCP_MAX
14614. BFA_LPORT_TYPE_PHYSICAL
14615. BFA_LPORT_TYPE_VIRTUAL
14616. BFA_LPORT_UNINIT
14617. BFA_LPS_FROM_TAG
14618. BFA_LPS_MAX_LPORTS
14619. BFA_LPS_MAX_VPORTS_SUPP_CB
14620. BFA_LPS_MAX_VPORTS_SUPP_CT
14621. BFA_LPS_MIN_LPORTS
14622. BFA_LPS_MOD
14623. BFA_LPS_SM_DELETE
14624. BFA_LPS_SM_FWRSP
14625. BFA_LPS_SM_LOGIN
14626. BFA_LPS_SM_LOGOUT
14627. BFA_LPS_SM_OFFLINE
14628. BFA_LPS_SM_RESUME
14629. BFA_LPS_SM_RX_CVL
14630. BFA_LPS_SM_SET_N2N_PID
14631. BFA_LP_TAG_INVALID
14632. BFA_LUNMASK_DISABLED
14633. BFA_LUNMASK_ENABLED
14634. BFA_LUNMASK_MINCFG
14635. BFA_LUNMASK_UNINITIALIZED
14636. BFA_MAX_FRUVPD_TRANSFER_SIZE
14637. BFA_MAX_IO_INDEX
14638. BFA_MEM_ABLK_DMA
14639. BFA_MEM_CEE_DMA
14640. BFA_MEM_DCONF_KVA
14641. BFA_MEM_DIAG_DMA
14642. BFA_MEM_FCPORT_DMA
14643. BFA_MEM_FCP_KVA
14644. BFA_MEM_FCXP_KVA
14645. BFA_MEM_FLASH_DMA
14646. BFA_MEM_FRU_DMA
14647. BFA_MEM_IOCFC_DMA
14648. BFA_MEM_IOCFC_KVA
14649. BFA_MEM_IOC_DMA
14650. BFA_MEM_LPS_KVA
14651. BFA_MEM_PHY_DMA
14652. BFA_MEM_PORT_DMA
14653. BFA_MEM_REQQ_DMA
14654. BFA_MEM_RPORT_KVA
14655. BFA_MEM_RSPQ_DMA
14656. BFA_MEM_SFP_DMA
14657. BFA_MEM_SGPG_KVA
14658. BFA_MEM_UF_KVA
14659. BFA_MFG_CHKSUM_SIZE
14660. BFA_MFG_ENC_VER
14661. BFA_MFG_HDR_LEN
14662. BFA_MFG_IC_ETH
14663. BFA_MFG_IC_FC
14664. BFA_MFG_NAME
14665. BFA_MFG_PARTNUM_SIZE
14666. BFA_MFG_SERIALNUM_SIZE
14667. BFA_MFG_SUPPLIER_ID_SIZE
14668. BFA_MFG_SUPPLIER_PARTNUM_SIZE
14669. BFA_MFG_SUPPLIER_REVISION_SIZE
14670. BFA_MFG_SUPPLIER_SERIALNUM_SIZE
14671. BFA_MFG_TYPE_ASTRA
14672. BFA_MFG_TYPE_CB_MAX
14673. BFA_MFG_TYPE_CHINOOK
14674. BFA_MFG_TYPE_CHINOOK2
14675. BFA_MFG_TYPE_CNA10P1
14676. BFA_MFG_TYPE_CNA10P2
14677. BFA_MFG_TYPE_FC4P1
14678. BFA_MFG_TYPE_FC4P2
14679. BFA_MFG_TYPE_FC8P1
14680. BFA_MFG_TYPE_FC8P2
14681. BFA_MFG_TYPE_INVALID
14682. BFA_MFG_TYPE_JAYHAWK
14683. BFA_MFG_TYPE_LIGHTNING
14684. BFA_MFG_TYPE_LIGHTNING_P0
14685. BFA_MFG_TYPE_PROWLER_C
14686. BFA_MFG_TYPE_PROWLER_D
14687. BFA_MFG_TYPE_PROWLER_F
14688. BFA_MFG_TYPE_PROWLER_N
14689. BFA_MFG_TYPE_WANCHESE
14690. BFA_MFG_VER1_LEN
14691. BFA_MFG_VERSION
14692. BFA_MFG_VERSION_UNINIT
14693. BFA_MFG_VPD_DELL
14694. BFA_MFG_VPD_HP
14695. BFA_MFG_VPD_IBM
14696. BFA_MFG_VPD_LEN
14697. BFA_MFG_VPD_LEN_INVALID
14698. BFA_MFG_VPD_PCI_BRCD
14699. BFA_MFG_VPD_PCI_DELL
14700. BFA_MFG_VPD_PCI_HDR_OFF
14701. BFA_MFG_VPD_PCI_HP
14702. BFA_MFG_VPD_PCI_IBM
14703. BFA_MFG_VPD_PCI_VDR_MASK
14704. BFA_MFG_VPD_PCI_VER_MASK
14705. BFA_MFG_VPD_UNKNOWN
14706. BFA_MODE_CNA
14707. BFA_MODE_HBA
14708. BFA_MODE_NIC
14709. BFA_MSGQ_CMDQ_F_DB_UPDATE
14710. BFA_MSGQ_CMDQ_NUM_ENTRY
14711. BFA_MSGQ_CMDQ_SIZE
14712. BFA_MSGQ_FREE_CNT
14713. BFA_MSGQ_INDX_ADD
14714. BFA_MSGQ_RSPQ_F_DB_UPDATE
14715. BFA_MSGQ_RSPQ_NUM_ENTRY
14716. BFA_MSGQ_RSPQ_SIZE
14717. BFA_MSIX_MAX_VECTORS
14718. BFA_NO_IO_INDEX
14719. BFA_PCI_ACCESS_RANGES
14720. BFA_PCI_CT2_SSID_ETH
14721. BFA_PCI_CT2_SSID_FC
14722. BFA_PCI_CT2_SSID_FCoE
14723. BFA_PCI_DEVICE_ID_CT
14724. BFA_PCI_DEVICE_ID_CT2
14725. BFA_PCI_DEVICE_ID_CT2_QUAD
14726. BFA_PCI_DEVICE_ID_CT_FC
14727. BFA_PCI_DEVICE_ID_FC_8G1P
14728. BFA_PCI_DEVICE_ID_FC_8G2P
14729. BFA_PCI_FCOE_SSDEVICE_ID
14730. BFA_PCI_VENDOR_ID_BROCADE
14731. BFA_PER_UF_DMA_SZ
14732. BFA_PHY
14733. BFA_PHY_DMA_BUF_SZ
14734. BFA_PHY_LOCK_STATUS
14735. BFA_PHY_STATUS_BAD
14736. BFA_PHY_STATUS_GOOD
14737. BFA_PHY_STATUS_NOT_PRESENT
14738. BFA_PL_EID_CT_IN
14739. BFA_PL_EID_CT_OUT
14740. BFA_PL_EID_DEBUG
14741. BFA_PL_EID_DRIVER_START
14742. BFA_PL_EID_FIP_FCF_CVL
14743. BFA_PL_EID_FIP_FCF_DISC
14744. BFA_PL_EID_INVALID
14745. BFA_PL_EID_IOC_DISABLE
14746. BFA_PL_EID_IOC_ENABLE
14747. BFA_PL_EID_LOGIN
14748. BFA_PL_EID_LOGO
14749. BFA_PL_EID_MAX
14750. BFA_PL_EID_MISC
14751. BFA_PL_EID_PORT_DISABLE
14752. BFA_PL_EID_PORT_ENABLE
14753. BFA_PL_EID_PORT_ST_CHANGE
14754. BFA_PL_EID_RSCN
14755. BFA_PL_EID_RX
14756. BFA_PL_EID_RX_ACK1
14757. BFA_PL_EID_RX_BSY
14758. BFA_PL_EID_RX_RJT
14759. BFA_PL_EID_TRUNK_SCN
14760. BFA_PL_EID_TX
14761. BFA_PL_EID_TX_ACK1
14762. BFA_PL_EID_TX_BSY
14763. BFA_PL_EID_TX_RJT
14764. BFA_PL_ENAME_STRLEN
14765. BFA_PL_INT_LOG_SZ
14766. BFA_PL_LOG_REC_INCR
14767. BFA_PL_LOG_TYPE_INT
14768. BFA_PL_LOG_TYPE_INVALID
14769. BFA_PL_LOG_TYPE_STRING
14770. BFA_PL_MID_DEBUG
14771. BFA_PL_MID_DRVR
14772. BFA_PL_MID_FCS
14773. BFA_PL_MID_HAL
14774. BFA_PL_MID_HAL_FCXP
14775. BFA_PL_MID_HAL_UF
14776. BFA_PL_MID_INVALID
14777. BFA_PL_MID_LPS
14778. BFA_PL_MID_MAX
14779. BFA_PL_MID_STRLEN
14780. BFA_PL_NLOG_ENTS
14781. BFA_PL_SIG_LEN
14782. BFA_PL_SIG_STR
14783. BFA_PL_STRING_LOG_SZ
14784. BFA_PORT_AEN_AUTH_OFF
14785. BFA_PORT_AEN_AUTH_ON
14786. BFA_PORT_AEN_DISABLE
14787. BFA_PORT_AEN_DISCONNECT
14788. BFA_PORT_AEN_ENABLE
14789. BFA_PORT_AEN_FABRIC_NAME_CHANGE
14790. BFA_PORT_AEN_OFFLINE
14791. BFA_PORT_AEN_ONLINE
14792. BFA_PORT_AEN_QOS_NEG
14793. BFA_PORT_AEN_RLIR
14794. BFA_PORT_AEN_SFP_ACCESS_ERROR
14795. BFA_PORT_AEN_SFP_INSERT
14796. BFA_PORT_AEN_SFP_POM
14797. BFA_PORT_AEN_SFP_POM_AMBER
14798. BFA_PORT_AEN_SFP_POM_GREEN
14799. BFA_PORT_AEN_SFP_POM_MAX
14800. BFA_PORT_AEN_SFP_POM_RED
14801. BFA_PORT_AEN_SFP_REMOVE
14802. BFA_PORT_AEN_SFP_UNSUPPORT
14803. BFA_PORT_IS_DISABLED
14804. BFA_PORT_LINKDOWN
14805. BFA_PORT_LINKSTATE_RSN_DISABLED
14806. BFA_PORT_LINKSTATE_RSN_FAA_MISCONFIG
14807. BFA_PORT_LINKSTATE_RSN_LOCAL_FAULT
14808. BFA_PORT_LINKSTATE_RSN_NONE
14809. BFA_PORT_LINKSTATE_RSN_PORT_FAULT
14810. BFA_PORT_LINKSTATE_RSN_REMOTE_FAULT
14811. BFA_PORT_LINKSTATE_RSN_RX_LIP
14812. BFA_PORT_LINKSTATE_RSN_RX_LIPF7
14813. BFA_PORT_LINKSTATE_RSN_RX_LOS
14814. BFA_PORT_LINKSTATE_RSN_RX_NOS
14815. BFA_PORT_LINKSTATE_RSN_RX_OLS
14816. BFA_PORT_LINKSTATE_RSN_SFP_REMOVED
14817. BFA_PORT_LINKSTATE_RSN_TIMEOUT
14818. BFA_PORT_LINKUP
14819. BFA_PORT_OPMODE_LB_CBL
14820. BFA_PORT_OPMODE_LB_EXT
14821. BFA_PORT_OPMODE_LB_HARD
14822. BFA_PORT_OPMODE_LB_INT
14823. BFA_PORT_OPMODE_LB_NLINT
14824. BFA_PORT_OPMODE_LB_SLW
14825. BFA_PORT_OPMODE_NORMAL
14826. BFA_PORT_SPEED_10GBPS
14827. BFA_PORT_SPEED_16GBPS
14828. BFA_PORT_SPEED_1GBPS
14829. BFA_PORT_SPEED_2GBPS
14830. BFA_PORT_SPEED_4GBPS
14831. BFA_PORT_SPEED_8GBPS
14832. BFA_PORT_SPEED_AUTO
14833. BFA_PORT_SPEED_UNKNOWN
14834. BFA_PORT_ST_DDPORT
14835. BFA_PORT_ST_DISABLED
14836. BFA_PORT_ST_DISABLING
14837. BFA_PORT_ST_DISABLING_QWAIT
14838. BFA_PORT_ST_DPORT
14839. BFA_PORT_ST_ENABLING
14840. BFA_PORT_ST_ENABLING_QWAIT
14841. BFA_PORT_ST_FAA_MISCONFIG
14842. BFA_PORT_ST_FWMISMATCH
14843. BFA_PORT_ST_IOCDIS
14844. BFA_PORT_ST_IOCDOWN
14845. BFA_PORT_ST_LINKDOWN
14846. BFA_PORT_ST_LINKUP
14847. BFA_PORT_ST_MAX_STATE
14848. BFA_PORT_ST_PREBOOT_DISABLED
14849. BFA_PORT_ST_STOPPED
14850. BFA_PORT_ST_TOGGLING_QWAIT
14851. BFA_PORT_ST_UNINIT
14852. BFA_PORT_TOPOLOGY_AUTO
14853. BFA_PORT_TOPOLOGY_AUTO_OLD_VER
14854. BFA_PORT_TOPOLOGY_LOOP
14855. BFA_PORT_TOPOLOGY_NONE
14856. BFA_PORT_TOPOLOGY_P2P
14857. BFA_PORT_TOPOLOGY_P2P_OLD_VER
14858. BFA_PORT_TYPE_LPORT
14859. BFA_PORT_TYPE_NLPORT
14860. BFA_PORT_TYPE_NPORT
14861. BFA_PORT_TYPE_P2P
14862. BFA_PORT_TYPE_UNKNOWN
14863. BFA_PORT_TYPE_VPORT
14864. BFA_PREBOOT_BOOTLUN_MAX
14865. BFA_QOS_BW_HIGH
14866. BFA_QOS_BW_LOW
14867. BFA_QOS_BW_MED
14868. BFA_QOS_DISABLED
14869. BFA_QOS_HIGH
14870. BFA_QOS_LOW
14871. BFA_QOS_MAX_VC
14872. BFA_QOS_MED
14873. BFA_QOS_OFFLINE
14874. BFA_QOS_ONLINE
14875. BFA_QOS_UNKNOWN
14876. BFA_QUEUE_FULL_RAMP_UP_TIME
14877. BFA_REG_ADDRMSK
14878. BFA_REG_ADDRSZ
14879. BFA_REG_CB_ADDRSZ
14880. BFA_REG_CT_ADDRSZ
14881. BFA_REQQ_DIAG
14882. BFA_REQQ_FCXP
14883. BFA_REQQ_FLASH
14884. BFA_REQQ_IOC
14885. BFA_REQQ_LPS
14886. BFA_REQQ_NELEMS_MIN
14887. BFA_REQQ_PORT
14888. BFA_REQQ_QOS_HI
14889. BFA_REQQ_QOS_LO
14890. BFA_REQQ_QOS_MD
14891. BFA_REQQ_RPORT
14892. BFA_REQQ_SBOOT
14893. BFA_ROUNDUP
14894. BFA_RPORT_ADISC
14895. BFA_RPORT_AEN_DISCONNECT
14896. BFA_RPORT_AEN_OFFLINE
14897. BFA_RPORT_AEN_ONLINE
14898. BFA_RPORT_AEN_QOS_FLOWID
14899. BFA_RPORT_AEN_QOS_PRIO
14900. BFA_RPORT_FC_COS
14901. BFA_RPORT_FROM_TAG
14902. BFA_RPORT_INITIATOR
14903. BFA_RPORT_LOGO
14904. BFA_RPORT_LOGORCV
14905. BFA_RPORT_MIN
14906. BFA_RPORT_MOD
14907. BFA_RPORT_NSDISC
14908. BFA_RPORT_NSQUERY
14909. BFA_RPORT_OFFLINE
14910. BFA_RPORT_ONLINE
14911. BFA_RPORT_PLOGI
14912. BFA_RPORT_PLOGI_RETRY
14913. BFA_RPORT_SM_CREATE
14914. BFA_RPORT_SM_DELETE
14915. BFA_RPORT_SM_FWRSP
14916. BFA_RPORT_SM_HWFAIL
14917. BFA_RPORT_SM_OFFLINE
14918. BFA_RPORT_SM_ONLINE
14919. BFA_RPORT_SM_QOS_SCN
14920. BFA_RPORT_SM_QRESUME
14921. BFA_RPORT_SM_SET_SPEED
14922. BFA_RPORT_SYMNAME_MAXLEN
14923. BFA_RPORT_TAG_INVALID
14924. BFA_RPORT_TARGET
14925. BFA_RPORT_UNINIT
14926. BFA_RSPQ_NELEMS_MIN
14927. BFA_SEM_SPINCNT
14928. BFA_SFP_MEDIA_CU
14929. BFA_SFP_MEDIA_EL
14930. BFA_SFP_MEDIA_LW
14931. BFA_SFP_MEDIA_SW
14932. BFA_SFP_MEDIA_UNKNOWN
14933. BFA_SFP_MEDIA_UNSUPPORT
14934. BFA_SFP_MOD
14935. BFA_SFP_SCN_FAILED
14936. BFA_SFP_SCN_INSERTED
14937. BFA_SFP_SCN_POM
14938. BFA_SFP_SCN_REMOVED
14939. BFA_SFP_SCN_UNSUPPORT
14940. BFA_SFP_SCN_VALID
14941. BFA_SFP_STATE_FAILED
14942. BFA_SFP_STATE_INIT
14943. BFA_SFP_STATE_INSERTED
14944. BFA_SFP_STATE_REMOVED
14945. BFA_SFP_STATE_UNSUPPORT
14946. BFA_SFP_STATE_VALID
14947. BFA_SGPG_DMA_SEGS
14948. BFA_SGPG_MAX
14949. BFA_SGPG_MIN
14950. BFA_SGPG_MOD
14951. BFA_SGPG_NPAGE
14952. BFA_SGPG_ROUNDUP
14953. BFA_SM
14954. BFA_SNSINFO_FROM_TAG
14955. BFA_STATUS_10G_SPD
14956. BFA_STATUS_4G_SPD
14957. BFA_STATUS_8G_SPD
14958. BFA_STATUS_ABORTED
14959. BFA_STATUS_ADAPTER_DISABLED
14960. BFA_STATUS_ADAPTER_ENABLED
14961. BFA_STATUS_ADDR_MAP_FAILURE
14962. BFA_STATUS_AD_IS_ENABLE
14963. BFA_STATUS_AUTH_DISABLED
14964. BFA_STATUS_AUTH_ENABLED
14965. BFA_STATUS_BADFLASH
14966. BFA_STATUS_BADFRMHDR
14967. BFA_STATUS_BADFRMSZ
14968. BFA_STATUS_BAD_ASICBLK
14969. BFA_STATUS_BAD_FILE
14970. BFA_STATUS_BAD_FWCFG
14971. BFA_STATUS_BAD_LUNS
14972. BFA_STATUS_BBCR_CFG_NO_CHANGE
14973. BFA_STATUS_BBCR_FC_ONLY
14974. BFA_STATUS_BEACON_OFF
14975. BFA_STATUS_BEACON_ON
14976. BFA_STATUS_BIOS_DISABLED
14977. BFA_STATUS_BOOT_CODE_TIMEDOUT
14978. BFA_STATUS_BOOT_CODE_UPDATED
14979. BFA_STATUS_BOOT_VERSION
14980. BFA_STATUS_CARDTYPE_MISSING
14981. BFA_STATUS_CARD_TYPE_MISMATCH
14982. BFA_STATUS_CEE_NOT_DN
14983. BFA_STATUS_CHECKSUM_FAIL
14984. BFA_STATUS_CMD_NOTSUPP
14985. BFA_STATUS_CMD_NOTSUPP_CNA
14986. BFA_STATUS_CMD_NOTSUPP_MEZZ
14987. BFA_STATUS_CNA_NO_BOOT
14988. BFA_STATUS_CNFG_FAILED
14989. BFA_STATUS_CREATE_FILE
14990. BFA_STATUS_CT_SPD
14991. BFA_STATUS_DATACORRUPTED
14992. BFA_STATUS_DDPORT_ERR
14993. BFA_STATUS_DEVBUSY
14994. BFA_STATUS_DEVID_MISSING
14995. BFA_STATUS_DIAG_BUSY
14996. BFA_STATUS_DPORT_CANT_PERF
14997. BFA_STATUS_DPORT_CMD_NOTSUPP
14998. BFA_STATUS_DPORT_DISABLED
14999. BFA_STATUS_DPORT_ENABLED
15000. BFA_STATUS_DPORT_ENOSYS
15001. BFA_STATUS_DPORT_ERR
15002. BFA_STATUS_DPORT_INV_SFP
15003. BFA_STATUS_DPORT_LOGICALERR
15004. BFA_STATUS_DPORT_NO_SFP
15005. BFA_STATUS_DPORT_SFPWRAP_ERR
15006. BFA_STATUS_DPORT_SWBUSY
15007. BFA_STATUS_DPORT_SW_NOTREADY
15008. BFA_STATUS_EBADF
15009. BFA_STATUS_EFOPEN
15010. BFA_STATUS_EINTR
15011. BFA_STATUS_EINVAL
15012. BFA_STATUS_EINVAL_QDEPTH
15013. BFA_STATUS_EINVAL_TOV
15014. BFA_STATUS_EIO
15015. BFA_STATUS_ENOFCPORTS
15016. BFA_STATUS_ENOFSAVE
15017. BFA_STATUS_ENOMEM
15018. BFA_STATUS_ENOSYS
15019. BFA_STATUS_ENOTTY
15020. BFA_STATUS_ENTRY_EXISTS
15021. BFA_STATUS_ENTRY_NOT_EXISTS
15022. BFA_STATUS_ENXIO
15023. BFA_STATUS_EPROTOCOL
15024. BFA_STATUS_ERROR_BBCR_ENABLED
15025. BFA_STATUS_ERROR_QOS_ENABLED
15026. BFA_STATUS_ERROR_TRL_ENABLED
15027. BFA_STATUS_ERROR_TRUNK_ENABLED
15028. BFA_STATUS_ERR_BBCR_SPEED_UNSUPPORT
15029. BFA_STATUS_ETHBOOT_DISABLED
15030. BFA_STATUS_ETHBOOT_ENABLED
15031. BFA_STATUS_ETIMER
15032. BFA_STATUS_FAA_ACQUIRED
15033. BFA_STATUS_FAA_ACQ_ADDR
15034. BFA_STATUS_FAA_DISABLED
15035. BFA_STATUS_FAA_ENABLED
15036. BFA_STATUS_FABRIC_RJT
15037. BFA_STATUS_FAILED
15038. BFA_STATUS_FCPT_LS_RJT
15039. BFA_STATUS_FEATURE_NOT_SUPPORTED
15040. BFA_STATUS_FILE_NOT_FOUND
15041. BFA_STATUS_FLASH_BAD_LEN
15042. BFA_STATUS_FLASH_CKFAIL
15043. BFA_STATUS_FLASH_EMPTY
15044. BFA_STATUS_FLASH_UNINIT
15045. BFA_STATUS_FRU_NOT_PRESENT
15046. BFA_STATUS_GZME_FAILED
15047. BFA_STATUS_HDMA_FAILED
15048. BFA_STATUS_IM_ADAPT_ALREADY_IN_TEAM
15049. BFA_STATUS_IM_ADAPT_HAS_VLANS
15050. BFA_STATUS_IM_BIND_FAILED
15051. BFA_STATUS_IM_CANNOT_REM_PRI
15052. BFA_STATUS_IM_DUP_TEAM_NAME
15053. BFA_STATUS_IM_ETH_LB_FAILED
15054. BFA_STATUS_IM_FW_UPDATE_FAIL
15055. BFA_STATUS_IM_GET_INETCFG_FAILED
15056. BFA_STATUS_IM_HDS_MISMATCH
15057. BFA_STATUS_IM_INETCFG_LOCK_FAILED
15058. BFA_STATUS_IM_INV_ADAPT_NAME
15059. BFA_STATUS_IM_INV_CODE
15060. BFA_STATUS_IM_INV_TEAM_NAME
15061. BFA_STATUS_IM_INV_VLAN
15062. BFA_STATUS_IM_INV_VLAN_NAME
15063. BFA_STATUS_IM_LAST_PORT_DELETE
15064. BFA_STATUS_IM_LINK_SPEED_MISMATCH
15065. BFA_STATUS_IM_LOW_RESOURCES
15066. BFA_STATUS_IM_MAX_PORTS_REACHED
15067. BFA_STATUS_IM_MAX_VLANS_REACHED
15068. BFA_STATUS_IM_MTU_MISMATCH
15069. BFA_STATUS_IM_NOT_BOUND
15070. BFA_STATUS_IM_NO_DRIVER
15071. BFA_STATUS_IM_NO_VLAN
15072. BFA_STATUS_IM_OFFLOAD_MISMATCH
15073. BFA_STATUS_IM_PASSTHRU_EDIT
15074. BFA_STATUS_IM_PORT_IN_TEAM
15075. BFA_STATUS_IM_PORT_NOT_IN_TEAM
15076. BFA_STATUS_IM_PORT_PARAMS
15077. BFA_STATUS_IM_PVID_EDIT
15078. BFA_STATUS_IM_PVID_MISMATCH
15079. BFA_STATUS_IM_PVID_NON_ZERO
15080. BFA_STATUS_IM_PVID_REMOVE
15081. BFA_STATUS_IM_RSS_MISMATCH
15082. BFA_STATUS_IM_TEAM_CFG_NOT_ALLOWED
15083. BFA_STATUS_IM_TEAM_NOT_FOUND
15084. BFA_STATUS_IM_UNBIND_FAILED
15085. BFA_STATUS_IM_VLANID_EXISTS
15086. BFA_STATUS_IM_VLANID_IS_PVID
15087. BFA_STATUS_IM_VLAN_NOT_FOUND
15088. BFA_STATUS_IM_VLAN_OVER_TEAM_DELETE_FAILED
15089. BFA_STATUS_INCORRECT_DRV_CONFIG
15090. BFA_STATUS_INSUFFICIENT_PERMS
15091. BFA_STATUS_INVALID_BBSCN
15092. BFA_STATUS_INVALID_BW
15093. BFA_STATUS_INVALID_CARDTYPE
15094. BFA_STATUS_INVALID_DEVID
15095. BFA_STATUS_INVALID_MAC
15096. BFA_STATUS_INVALID_VENDOR
15097. BFA_STATUS_INVALID_WWN
15098. BFA_STATUS_INVLD_DFSZ
15099. BFA_STATUS_IOC_DISABLED
15100. BFA_STATUS_IOC_ENABLED
15101. BFA_STATUS_IOC_FAILURE
15102. BFA_STATUS_IOC_NON_OP
15103. BFA_STATUS_IOPROFILE_OFF
15104. BFA_STATUS_IO_FAILURE
15105. BFA_STATUS_LBEACON_OFF
15106. BFA_STATUS_LBEACON_ON
15107. BFA_STATUS_LEDTEST_OP
15108. BFA_STATUS_LINKDOWN
15109. BFA_STATUS_LINKTIMEOUT
15110. BFA_STATUS_LOOP_UNSUPP_MEZZ
15111. BFA_STATUS_MAX_ENTRY_REACHED
15112. BFA_STATUS_MAX_VAL
15113. BFA_STATUS_MEMTEST_FAILED
15114. BFA_STATUS_MISMATCH
15115. BFA_STATUS_MISSINGFRM
15116. BFA_STATUS_NODEV
15117. BFA_STATUS_NOFLASH
15118. BFA_STATUS_NO_ADAPTER
15119. BFA_STATUS_NO_CHANGE
15120. BFA_STATUS_NO_DRIVER
15121. BFA_STATUS_NO_FABRIC
15122. BFA_STATUS_NO_FCPIM_NEXUS
15123. BFA_STATUS_NO_MINPORT_DRIVER
15124. BFA_STATUS_NO_PORT_INSTANCE
15125. BFA_STATUS_NO_RPORTS
15126. BFA_STATUS_NO_SFP_DEV
15127. BFA_STATUS_NO_TOPOLOGY_FOR_CNA
15128. BFA_STATUS_NO_VPORT_LOCK
15129. BFA_STATUS_NSLOGIN_FAILED
15130. BFA_STATUS_NSQUERY_FAILED
15131. BFA_STATUS_OK
15132. BFA_STATUS_PBC
15133. BFA_STATUS_PENDING
15134. BFA_STATUS_PHY_NOT_PRESENT
15135. BFA_STATUS_PORTLOG_DISABLED
15136. BFA_STATUS_PORTLOG_ENABLED
15137. BFA_STATUS_PORT_NOT_DISABLED
15138. BFA_STATUS_PORT_NOT_INITED
15139. BFA_STATUS_PORT_OFFLINE
15140. BFA_STATUS_QOS_BW_INVALID
15141. BFA_STATUS_QOS_DISABLED
15142. BFA_STATUS_QOS_ENABLED
15143. BFA_STATUS_QOS_FC_ONLY
15144. BFA_STATUS_REG_FAIL
15145. BFA_STATUS_RLIM_DIS
15146. BFA_STATUS_RLIM_EN
15147. BFA_STATUS_RLIM_FC_ONLY
15148. BFA_STATUS_RPORT_OFFLINE
15149. BFA_STATUS_RPSC_ENABLED
15150. BFA_STATUS_SAME_NAME
15151. BFA_STATUS_SCSISTART_REQD
15152. BFA_STATUS_SFP_NOT_READY
15153. BFA_STATUS_SFP_UNSUPP
15154. BFA_STATUS_TGTOPEN_FAILED
15155. BFA_STATUS_TOMCAT_SPD_NOT_ALLOWED
15156. BFA_STATUS_TOPOLOGY_LOOP
15157. BFA_STATUS_TRUNK_DISABLED
15158. BFA_STATUS_TRUNK_ENABLED
15159. BFA_STATUS_TRUNK_ERROR_TRL_ENABLED
15160. BFA_STATUS_TRUNK_UNSUPP
15161. BFA_STATUS_UNKNOWN_LWWN
15162. BFA_STATUS_UNKNOWN_RWWN
15163. BFA_STATUS_UNKNOWN_VFID
15164. BFA_STATUS_UNKNOWN_VWWN
15165. BFA_STATUS_UNSUPP_SPEED
15166. BFA_STATUS_VERSION_FAIL
15167. BFA_STATUS_VPORT_EXISTS
15168. BFA_STATUS_VPORT_MAX
15169. BFA_STATUS_VPORT_NO_CNFG
15170. BFA_STATUS_VPORT_WWN_BP
15171. BFA_STRING_32
15172. BFA_SYMNAME_MAXLEN
15173. BFA_TFRU_DATA_SIZE
15174. BFA_TIMER_FREQ
15175. BFA_TOTAL_FLASH_SIZE
15176. BFA_TRC_CNA
15177. BFA_TRC_CNA_IOC
15178. BFA_TRC_CNA_IOC_CB
15179. BFA_TRC_CNA_IOC_CT
15180. BFA_TRC_CNA_PORT
15181. BFA_TRC_FCS
15182. BFA_TRC_FCS_FCPIM
15183. BFA_TRC_FCS_FCS
15184. BFA_TRC_FCS_PORT
15185. BFA_TRC_FCS_RPORT
15186. BFA_TRC_FILE
15187. BFA_TRC_HAL
15188. BFA_TRC_HAL_CORE
15189. BFA_TRC_HAL_FCPIM
15190. BFA_TRC_HAL_FCXP
15191. BFA_TRC_HAL_IOCFC_CB
15192. BFA_TRC_HAL_IOCFC_CT
15193. BFA_TRC_LDRV
15194. BFA_TRC_LDRV_BFAD
15195. BFA_TRC_LDRV_BSG
15196. BFA_TRC_LDRV_IM
15197. BFA_TRC_MAX
15198. BFA_TRC_MOD
15199. BFA_TRC_MOD_SH
15200. BFA_TRC_TS
15201. BFA_TRUE
15202. BFA_TRUNK_DISABLED
15203. BFA_TRUNK_LINK_FCTL_NORMAL
15204. BFA_TRUNK_LINK_FCTL_VC
15205. BFA_TRUNK_LINK_FCTL_VC_QOS
15206. BFA_TRUNK_LINK_STATE_DN_GRP_MIS
15207. BFA_TRUNK_LINK_STATE_DN_LINKDN
15208. BFA_TRUNK_LINK_STATE_DN_MODE_MIS
15209. BFA_TRUNK_LINK_STATE_DN_SPD_MIS
15210. BFA_TRUNK_LINK_STATE_UP
15211. BFA_TRUNK_MAX_PORTS
15212. BFA_TRUNK_OFFLINE
15213. BFA_TRUNK_ONLINE
15214. BFA_TSKIM_FROM_TAG
15215. BFA_TSKIM_MAX
15216. BFA_TSKIM_MIN
15217. BFA_TSKIM_SM_CLEANUP
15218. BFA_TSKIM_SM_CLEANUP_DONE
15219. BFA_TSKIM_SM_DONE
15220. BFA_TSKIM_SM_HCB
15221. BFA_TSKIM_SM_HWFAIL
15222. BFA_TSKIM_SM_IOS_DONE
15223. BFA_TSKIM_SM_QRESUME
15224. BFA_TSKIM_SM_START
15225. BFA_TSKIM_SM_UTAG
15226. BFA_UF_BUFSZ
15227. BFA_UF_DMA_SEGS
15228. BFA_UF_MAX
15229. BFA_UF_MAX_SGES
15230. BFA_UF_MIN
15231. BFA_UF_MOD
15232. BFA_VERSION_LEN
15233. BFA_VF_AUTH
15234. BFA_VF_EVFP
15235. BFA_VF_FLOGI
15236. BFA_VF_ISOLATED
15237. BFA_VF_LINK_DOWN
15238. BFA_VF_NOFABRIC
15239. BFA_VF_ONLINE
15240. BFA_VF_UNINIT
15241. BFBCR
15242. BFBDFE
15243. BFBDFE_MASK
15244. BFBDFE_SHIFT
15245. BFBSFE
15246. BFBSFE_MASK
15247. BFBSFE_SHIFT
15248. BFC
15249. BFCCODE
15250. BFCU
15251. BFEXT
15252. BFF
15253. BFGUARD_COUNTER_DC_L
15254. BFIELD
15255. BFINS
15256. BFIRST
15257. BFITNOENT
15258. BFI_ABLK_H2I_ADPT_CONFIG
15259. BFI_ABLK_H2I_OPTROM_DISABLE
15260. BFI_ABLK_H2I_OPTROM_ENABLE
15261. BFI_ABLK_H2I_PF_CREATE
15262. BFI_ABLK_H2I_PF_DELETE
15263. BFI_ABLK_H2I_PF_UPDATE
15264. BFI_ABLK_H2I_PORT_CONFIG
15265. BFI_ABLK_H2I_QUERY
15266. BFI_ABLK_I2H_ADPT_CONFIG
15267. BFI_ABLK_I2H_OPTROM_DISABLE
15268. BFI_ABLK_I2H_OPTROM_ENABLE
15269. BFI_ABLK_I2H_PF_CREATE
15270. BFI_ABLK_I2H_PF_DELETE
15271. BFI_ABLK_I2H_PF_UPDATE
15272. BFI_ABLK_I2H_PORT_CONFIG
15273. BFI_ABLK_I2H_QUERY
15274. BFI_ADAPTER_GETP
15275. BFI_ADAPTER_IS_PROTO
15276. BFI_ADAPTER_IS_SPECIAL
15277. BFI_ADAPTER_IS_TTV
15278. BFI_ADAPTER_IS_UNSUPP
15279. BFI_ADAPTER_NPORTS_MK
15280. BFI_ADAPTER_NPORTS_SH
15281. BFI_ADAPTER_PROTO
15282. BFI_ADAPTER_SETP
15283. BFI_ADAPTER_SPEED_MK
15284. BFI_ADAPTER_SPEED_SH
15285. BFI_ADAPTER_TTV
15286. BFI_ADAPTER_TYPE_FC
15287. BFI_ADAPTER_TYPE_MK
15288. BFI_ADAPTER_TYPE_SH
15289. BFI_ADAPTER_UNSUPP
15290. BFI_ASIC_GEN_CB
15291. BFI_ASIC_GEN_CT
15292. BFI_ASIC_GEN_CT2
15293. BFI_ASIC_MODE_COMBO
15294. BFI_ASIC_MODE_ETH
15295. BFI_ASIC_MODE_FC
15296. BFI_ASIC_MODE_FC16
15297. BFI_BOOT_MEMTEST_RES_ADDR
15298. BFI_BOOT_MEMTEST_RES_SIG
15299. BFI_CEE_H2I_GET_CFG_REQ
15300. BFI_CEE_H2I_GET_STATS_REQ
15301. BFI_CEE_H2I_RESET_STATS
15302. BFI_CEE_I2H_GET_CFG_RSP
15303. BFI_CEE_I2H_GET_STATS_RSP
15304. BFI_CEE_I2H_RESET_STATS_RSP
15305. BFI_CMD_COPY_SZ
15306. BFI_COALESCING_TIMER_UNIT
15307. BFI_CQ_WI_SIZE
15308. BFI_DCONF_SIGNATURE
15309. BFI_DCONF_VERSION
15310. BFI_DIAG_DMA_BUF_SZ
15311. BFI_DIAG_H2I_DPORT
15312. BFI_DIAG_H2I_FWPING
15313. BFI_DIAG_H2I_LEDTEST
15314. BFI_DIAG_H2I_LOOPBACK
15315. BFI_DIAG_H2I_PORTBEACON
15316. BFI_DIAG_H2I_QTEST
15317. BFI_DIAG_H2I_TEMPSENSOR
15318. BFI_DIAG_I2H_DPORT
15319. BFI_DIAG_I2H_DPORT_SCN
15320. BFI_DIAG_I2H_FWPING
15321. BFI_DIAG_I2H_LEDTEST
15322. BFI_DIAG_I2H_LOOPBACK
15323. BFI_DIAG_I2H_PORTBEACON
15324. BFI_DIAG_I2H_QTEST
15325. BFI_DIAG_I2H_TEMPSENSOR
15326. BFI_DIAG_MAX_SGES
15327. BFI_DPORT_DISABLE
15328. BFI_DPORT_DYN_DISABLE
15329. BFI_DPORT_ENABLE
15330. BFI_DPORT_SCN_DDPORT_DISABLE
15331. BFI_DPORT_SCN_DDPORT_DISABLED
15332. BFI_DPORT_SCN_DDPORT_ENABLE
15333. BFI_DPORT_SCN_FCPORT_DISABLE
15334. BFI_DPORT_SCN_SFP_REMOVED
15335. BFI_DPORT_SCN_SUBTESTSTART
15336. BFI_DPORT_SCN_TESTCOMP
15337. BFI_DPORT_SCN_TESTSKIP
15338. BFI_DPORT_SCN_TESTSTART
15339. BFI_DPORT_SHOW
15340. BFI_DPORT_START
15341. BFI_ENET_CFG_MAX
15342. BFI_ENET_CMD_CAM_FULL
15343. BFI_ENET_CMD_DUP_ENTRY
15344. BFI_ENET_CMD_FAIL
15345. BFI_ENET_CMD_NOT_EXEC
15346. BFI_ENET_CMD_NOT_OWNER
15347. BFI_ENET_CMD_OK
15348. BFI_ENET_CMD_PORT_DISABLED
15349. BFI_ENET_CMD_WAITING
15350. BFI_ENET_CQ_EF_BCAST
15351. BFI_ENET_CQ_EF_FCS_ERROR
15352. BFI_ENET_CQ_EF_FC_CRC_OK
15353. BFI_ENET_CQ_EF_HDS_HEADER
15354. BFI_ENET_CQ_EF_IPV4
15355. BFI_ENET_CQ_EF_IPV6
15356. BFI_ENET_CQ_EF_IP_OPTIONS
15357. BFI_ENET_CQ_EF_L3_CKSUM_OK
15358. BFI_ENET_CQ_EF_L4_CKSUM_OK
15359. BFI_ENET_CQ_EF_LOCAL
15360. BFI_ENET_CQ_EF_MAC_ERROR
15361. BFI_ENET_CQ_EF_MCAST
15362. BFI_ENET_CQ_EF_MCAST_MATCH
15363. BFI_ENET_CQ_EF_REMOTE
15364. BFI_ENET_CQ_EF_RSS
15365. BFI_ENET_CQ_EF_RSVD1
15366. BFI_ENET_CQ_EF_RSVD2
15367. BFI_ENET_CQ_EF_TCP
15368. BFI_ENET_CQ_EF_TOO_LONG
15369. BFI_ENET_CQ_EF_UDP
15370. BFI_ENET_CQ_EF_VLAN
15371. BFI_ENET_DEF_RITSZ
15372. BFI_ENET_DEF_RXP
15373. BFI_ENET_DEF_TXQ
15374. BFI_ENET_DEF_UCAM
15375. BFI_ENET_DIAG_LB_OPMODE_CBL
15376. BFI_ENET_DIAG_LB_OPMODE_EXT
15377. BFI_ENET_H2I_DIAG_LOOPBACK_REQ
15378. BFI_ENET_H2I_GET_ATTR_REQ
15379. BFI_ENET_H2I_MAC_MCAST_ADD_REQ
15380. BFI_ENET_H2I_MAC_MCAST_DEL_REQ
15381. BFI_ENET_H2I_MAC_MCAST_FILTER_REQ
15382. BFI_ENET_H2I_MAC_UCAST_ADD_REQ
15383. BFI_ENET_H2I_MAC_UCAST_CLR_REQ
15384. BFI_ENET_H2I_MAC_UCAST_DEL_REQ
15385. BFI_ENET_H2I_MAC_UCAST_SET_REQ
15386. BFI_ENET_H2I_MAX
15387. BFI_ENET_H2I_PORT_ADMIN_UP_REQ
15388. BFI_ENET_H2I_RIT_CFG_REQ
15389. BFI_ENET_H2I_RSS_CFG_REQ
15390. BFI_ENET_H2I_RSS_ENABLE_REQ
15391. BFI_ENET_H2I_RX_CFG_CLR_REQ
15392. BFI_ENET_H2I_RX_CFG_SET_REQ
15393. BFI_ENET_H2I_RX_DEFAULT_REQ
15394. BFI_ENET_H2I_RX_PROMISCUOUS_REQ
15395. BFI_ENET_H2I_RX_VLAN_SET_REQ
15396. BFI_ENET_H2I_RX_VLAN_STRIP_ENABLE_REQ
15397. BFI_ENET_H2I_SET_PAUSE_REQ
15398. BFI_ENET_H2I_STATS_CLR_REQ
15399. BFI_ENET_H2I_STATS_GET_REQ
15400. BFI_ENET_H2I_TX_CFG_CLR_REQ
15401. BFI_ENET_H2I_TX_CFG_SET_REQ
15402. BFI_ENET_H2I_WOL_FRAME_REQ
15403. BFI_ENET_H2I_WOL_MAGIC_REQ
15404. BFI_ENET_HDS_FORCED
15405. BFI_ENET_HDS_IPV4_TCP
15406. BFI_ENET_HDS_IPV4_UDP
15407. BFI_ENET_HDS_IPV6_TCP
15408. BFI_ENET_HDS_IPV6_UDP
15409. BFI_ENET_I2H_BW_UPDATE_AEN
15410. BFI_ENET_I2H_DIAG_LOOPBACK_RSP
15411. BFI_ENET_I2H_GET_ATTR_RSP
15412. BFI_ENET_I2H_LINK_DOWN_AEN
15413. BFI_ENET_I2H_LINK_UP_AEN
15414. BFI_ENET_I2H_MAC_MCAST_ADD_RSP
15415. BFI_ENET_I2H_MAC_MCAST_DEL_RSP
15416. BFI_ENET_I2H_MAC_MCAST_FILTER_RSP
15417. BFI_ENET_I2H_MAC_UCAST_ADD_RSP
15418. BFI_ENET_I2H_MAC_UCAST_CLR_RSP
15419. BFI_ENET_I2H_MAC_UCAST_DEL_RSP
15420. BFI_ENET_I2H_MAC_UCAST_SET_RSP
15421. BFI_ENET_I2H_PORT_ADMIN_RSP
15422. BFI_ENET_I2H_PORT_DISABLE_AEN
15423. BFI_ENET_I2H_PORT_ENABLE_AEN
15424. BFI_ENET_I2H_RIT_CFG_RSP
15425. BFI_ENET_I2H_RSS_CFG_RSP
15426. BFI_ENET_I2H_RSS_ENABLE_RSP
15427. BFI_ENET_I2H_RX_CFG_CLR_RSP
15428. BFI_ENET_I2H_RX_CFG_SET_RSP
15429. BFI_ENET_I2H_RX_DEFAULT_RSP
15430. BFI_ENET_I2H_RX_PROMISCUOUS_RSP
15431. BFI_ENET_I2H_RX_VLAN_SET_RSP
15432. BFI_ENET_I2H_RX_VLAN_STRIP_ENABLE_RSP
15433. BFI_ENET_I2H_SET_PAUSE_RSP
15434. BFI_ENET_I2H_STATS_CLR_RSP
15435. BFI_ENET_I2H_STATS_GET_RSP
15436. BFI_ENET_I2H_TX_CFG_CLR_RSP
15437. BFI_ENET_I2H_TX_CFG_SET_RSP
15438. BFI_ENET_I2H_WOL_FRAME_RSP
15439. BFI_ENET_I2H_WOL_MAGIC_RSP
15440. BFI_ENET_MAX_MCAM
15441. BFI_ENET_RSS_IPV4
15442. BFI_ENET_RSS_IPV4_TCP
15443. BFI_ENET_RSS_IPV6
15444. BFI_ENET_RSS_IPV6_TCP
15445. BFI_ENET_RSS_KEY_LEN
15446. BFI_ENET_RSS_RIT_MAX
15447. BFI_ENET_RXQ_HDS
15448. BFI_ENET_RXQ_HDS_OPT_BASED
15449. BFI_ENET_RXQ_LARGE_SMALL
15450. BFI_ENET_RXQ_SINGLE
15451. BFI_ENET_RX_QSET_MAX
15452. BFI_ENET_STATS_ALL
15453. BFI_ENET_STATS_BPC
15454. BFI_ENET_STATS_MAC
15455. BFI_ENET_STATS_RAD
15456. BFI_ENET_STATS_RX_FC
15457. BFI_ENET_STATS_TX_FC
15458. BFI_ENET_TXQ_PRIO_MAX
15459. BFI_ENET_TXQ_WI_CF_FCOE_CRC
15460. BFI_ENET_TXQ_WI_CF_INS_PRIO
15461. BFI_ENET_TXQ_WI_CF_INS_VLAN
15462. BFI_ENET_TXQ_WI_CF_IPID_MODE
15463. BFI_ENET_TXQ_WI_CF_IP_CKSUM
15464. BFI_ENET_TXQ_WI_CF_TCP_CKSUM
15465. BFI_ENET_TXQ_WI_CF_UDP_CKSUM
15466. BFI_ENET_TXQ_WI_EXTENSION
15467. BFI_ENET_TXQ_WI_L4_HDR_N_OFFSET
15468. BFI_ENET_TXQ_WI_SEND
15469. BFI_ENET_TXQ_WI_SEND_LSO
15470. BFI_ENET_TXQ_WI_VECT_MAX
15471. BFI_ENET_TX_VLAN_INS
15472. BFI_ENET_TX_VLAN_NOP
15473. BFI_ENET_TX_VLAN_WI
15474. BFI_ENET_VLAN_BLOCKS_MAX
15475. BFI_ENET_VLAN_BLOCK_SIZE
15476. BFI_ENET_VLAN_ID_MAX
15477. BFI_ENET_VLAN_WORDS_MAX
15478. BFI_ENET_VLAN_WORD_SIZE
15479. BFI_FCPORT_H2I_DISABLE_REQ
15480. BFI_FCPORT_H2I_ENABLE_REQ
15481. BFI_FCPORT_H2I_SET_SVC_PARAMS_REQ
15482. BFI_FCPORT_H2I_STATS_CLEAR_REQ
15483. BFI_FCPORT_H2I_STATS_GET_REQ
15484. BFI_FCPORT_I2H_DISABLE_AEN
15485. BFI_FCPORT_I2H_DISABLE_RSP
15486. BFI_FCPORT_I2H_ENABLE_AEN
15487. BFI_FCPORT_I2H_ENABLE_RSP
15488. BFI_FCPORT_I2H_EVENT
15489. BFI_FCPORT_I2H_SET_SVC_PARAMS_RSP
15490. BFI_FCPORT_I2H_STATS_CLEAR_RSP
15491. BFI_FCPORT_I2H_STATS_GET_RSP
15492. BFI_FCPORT_I2H_TRUNK_SCN
15493. BFI_FCPORT_MAX_LINKS
15494. BFI_FCXP_H2I_SEND_REQ
15495. BFI_FCXP_I2H_SEND_RSP
15496. BFI_FLASH_CHUNK_SZ
15497. BFI_FLASH_CHUNK_SZ_WORDS
15498. BFI_FLASH_H2I_BOOT_VER_REQ
15499. BFI_FLASH_H2I_ERASE_REQ
15500. BFI_FLASH_H2I_QUERY_REQ
15501. BFI_FLASH_H2I_READ_REQ
15502. BFI_FLASH_H2I_WRITE_REQ
15503. BFI_FLASH_I2H_BOOT_VER_RSP
15504. BFI_FLASH_I2H_ERASE_RSP
15505. BFI_FLASH_I2H_EVENT
15506. BFI_FLASH_I2H_QUERY_RSP
15507. BFI_FLASH_I2H_READ_RSP
15508. BFI_FLASH_I2H_WRITE_RSP
15509. BFI_FLASH_IMAGE_SZ
15510. BFI_FRUVPD_H2I_READ_REQ
15511. BFI_FRUVPD_H2I_WRITE_REQ
15512. BFI_FRUVPD_I2H_READ_RSP
15513. BFI_FRUVPD_I2H_WRITE_RSP
15514. BFI_FWBOOT_DEVMODE
15515. BFI_FWBOOT_DEVMODE_OFF
15516. BFI_FWBOOT_ENV_OFF
15517. BFI_FWBOOT_ENV_OS
15518. BFI_FWBOOT_TYPE_FLASH
15519. BFI_FWBOOT_TYPE_MEMTEST
15520. BFI_FWBOOT_TYPE_NORMAL
15521. BFI_FWBOOT_TYPE_OFF
15522. BFI_I2H_OPCODE_BASE
15523. BFI_IBIDX_SIZE
15524. BFI_INVALID_RID
15525. BFI_IOCFC_H2I_ADDR_REQ
15526. BFI_IOCFC_H2I_CFG_REQ
15527. BFI_IOCFC_H2I_FAA_QUERY_REQ
15528. BFI_IOCFC_H2I_SET_INTR_REQ
15529. BFI_IOCFC_H2I_UPDATEQ_REQ
15530. BFI_IOCFC_I2H_ADDR_MSG
15531. BFI_IOCFC_I2H_CFG_REPLY
15532. BFI_IOCFC_I2H_FAA_QUERY_RSP
15533. BFI_IOCFC_I2H_UPDATEQ_RSP
15534. BFI_IOC_ATTR_UUID_SZ
15535. BFI_IOC_CFG
15536. BFI_IOC_CFG_DISABLED
15537. BFI_IOC_DISABLED
15538. BFI_IOC_DISABLING
15539. BFI_IOC_ENDIAN_SIG
15540. BFI_IOC_FAIL
15541. BFI_IOC_FWSTATS_OFF
15542. BFI_IOC_FWSTATS_SZ
15543. BFI_IOC_FW_INV_SIGN
15544. BFI_IOC_FW_SIGNATURE
15545. BFI_IOC_H2I_DBG_DUMP
15546. BFI_IOC_H2I_DBG_SYNC
15547. BFI_IOC_H2I_DISABLE_REQ
15548. BFI_IOC_H2I_ENABLE_REQ
15549. BFI_IOC_H2I_GETATTR_REQ
15550. BFI_IOC_HWINIT
15551. BFI_IOC_I2H_ACQ_ADDR_REPLY
15552. BFI_IOC_I2H_DISABLE_REPLY
15553. BFI_IOC_I2H_ENABLE_REPLY
15554. BFI_IOC_I2H_GETATTR_REPLY
15555. BFI_IOC_I2H_HBEAT
15556. BFI_IOC_IMG_VER_BETTER
15557. BFI_IOC_IMG_VER_INCOMP
15558. BFI_IOC_IMG_VER_OLD
15559. BFI_IOC_IMG_VER_SAME
15560. BFI_IOC_INITING
15561. BFI_IOC_MAX_CQS
15562. BFI_IOC_MAX_CQS_ASIC
15563. BFI_IOC_MD5SUM_SZ
15564. BFI_IOC_MEMTEST
15565. BFI_IOC_MSGLEN_MAX
15566. BFI_IOC_MSGSZ
15567. BFI_IOC_OP
15568. BFI_IOC_SMEM_PG0_CB
15569. BFI_IOC_SMEM_PG0_CT
15570. BFI_IOC_TRC_ENTS
15571. BFI_IOC_TRC_ENT_SZ
15572. BFI_IOC_TRC_HDR_SZ
15573. BFI_IOC_TRC_OFF
15574. BFI_IOC_UNINIT
15575. BFI_IOIM_H2I_IOABORT_REQ
15576. BFI_IOIM_H2I_IOCLEANUP_REQ
15577. BFI_IOIM_I2H_IOABORT_RSP
15578. BFI_IOIM_I2H_IO_RSP
15579. BFI_IOIM_SNSBUF_SEGS
15580. BFI_IOIM_SNSLEN
15581. BFI_IOIM_STS_ABORTED
15582. BFI_IOIM_STS_HOST_ABORTED
15583. BFI_IOIM_STS_OK
15584. BFI_IOIM_STS_PATHTOV
15585. BFI_IOIM_STS_PROTO_ERR
15586. BFI_IOIM_STS_RES_FREE
15587. BFI_IOIM_STS_SQER_NEEDED
15588. BFI_IOIM_STS_TIMEDOUT
15589. BFI_IOIM_STS_UTAG
15590. BFI_IO_MAX
15591. BFI_ITN_H2I_CREATE_REQ
15592. BFI_ITN_H2I_DELETE_REQ
15593. BFI_ITN_I2H_CREATE_RSP
15594. BFI_ITN_I2H_DELETE_RSP
15595. BFI_ITN_I2H_SLER_EVENT
15596. BFI_LMSG_PL_WSZ
15597. BFI_LMSG_SZ
15598. BFI_LPS_H2I_LOGIN_REQ
15599. BFI_LPS_H2I_LOGOUT_REQ
15600. BFI_LPS_H2I_N2N_PID_REQ
15601. BFI_LPS_I2H_CVL_EVENT
15602. BFI_LPS_I2H_LOGIN_RSP
15603. BFI_LPS_I2H_LOGOUT_RSP
15604. BFI_MAX_COALESCING_TIMEO
15605. BFI_MAX_INTERPKT_COUNT
15606. BFI_MAX_INTERPKT_TIMEO
15607. BFI_MBMSG_SZ
15608. BFI_MC_ABLK
15609. BFI_MC_CEE
15610. BFI_MC_DIAG
15611. BFI_MC_EDMA
15612. BFI_MC_ENET
15613. BFI_MC_FCPORT
15614. BFI_MC_FCXP
15615. BFI_MC_FLASH
15616. BFI_MC_FRU
15617. BFI_MC_IOC
15618. BFI_MC_IOCFC
15619. BFI_MC_IOIM
15620. BFI_MC_IOIM_IO
15621. BFI_MC_IOIM_IOCOM
15622. BFI_MC_IOIM_READ
15623. BFI_MC_IOIM_WRITE
15624. BFI_MC_IPFC
15625. BFI_MC_ITN
15626. BFI_MC_ITNIM
15627. BFI_MC_LL
15628. BFI_MC_LPS
15629. BFI_MC_MAX
15630. BFI_MC_MFG
15631. BFI_MC_MSGQ
15632. BFI_MC_NBOOT
15633. BFI_MC_PHY
15634. BFI_MC_PORT
15635. BFI_MC_RPORT
15636. BFI_MC_SBOOT
15637. BFI_MC_SFP
15638. BFI_MC_TIO
15639. BFI_MC_TIO_DATA_XFERED
15640. BFI_MC_TIO_IO
15641. BFI_MC_TIO_READ
15642. BFI_MC_TIO_WRITE
15643. BFI_MC_TSKIM
15644. BFI_MC_UF
15645. BFI_MEM_DMA_NSEGS
15646. BFI_MEM_DMA_SEG_SZ
15647. BFI_MEM_NREQS_SEG
15648. BFI_MEM_SEG_FROM_TAG
15649. BFI_MEM_SEG_REQ_OFFSET
15650. BFI_MSGQ_CMD_ENTRY_SIZE
15651. BFI_MSGQ_EMPTY
15652. BFI_MSGQ_FREE_CNT
15653. BFI_MSGQ_FULL
15654. BFI_MSGQ_H2I_CMDQ_COPY_RSP
15655. BFI_MSGQ_H2I_DOORBELL
15656. BFI_MSGQ_H2I_DOORBELL_CI
15657. BFI_MSGQ_H2I_DOORBELL_PI
15658. BFI_MSGQ_H2I_INIT_REQ
15659. BFI_MSGQ_H2I_SHUTDOWN
15660. BFI_MSGQ_I2H_CMDQ_COPY_REQ
15661. BFI_MSGQ_I2H_DOORBELL
15662. BFI_MSGQ_I2H_DOORBELL_CI
15663. BFI_MSGQ_I2H_DOORBELL_PI
15664. BFI_MSGQ_I2H_INIT_RSP
15665. BFI_MSGQ_MSG_SIZE_MAX
15666. BFI_MSGQ_RSP_ENTRY_SIZE
15667. BFI_MSGQ_UPDATE_CI
15668. BFI_MSGQ_UPDATE_PI
15669. BFI_MSIX_CB_MAX
15670. BFI_MSIX_CPE_QMAX_CB
15671. BFI_MSIX_CPE_QMAX_CT
15672. BFI_MSIX_CPE_QMIN_CB
15673. BFI_MSIX_CPE_QMIN_CT
15674. BFI_MSIX_CT_MAX
15675. BFI_MSIX_LPU_ERR_CT
15676. BFI_MSIX_RME_QMAX_CB
15677. BFI_MSIX_RME_QMAX_CT
15678. BFI_MSIX_RME_QMIN_CB
15679. BFI_MSIX_RME_QMIN_CT
15680. BFI_PBC_MAX_BLUNS
15681. BFI_PBC_MAX_VPORTS
15682. BFI_PBC_PORT_DISABLED
15683. BFI_PCIFN_CLASS_ETH
15684. BFI_PCIFN_CLASS_FC
15685. BFI_PHY_H2I_QUERY_REQ
15686. BFI_PHY_H2I_READ_REQ
15687. BFI_PHY_H2I_STATS_REQ
15688. BFI_PHY_H2I_WRITE_REQ
15689. BFI_PHY_I2H_QUERY_RSP
15690. BFI_PHY_I2H_READ_RSP
15691. BFI_PHY_I2H_STATS_RSP
15692. BFI_PHY_I2H_WRITE_RSP
15693. BFI_PORT_H2I_CLEAR_STATS_REQ
15694. BFI_PORT_H2I_DISABLE_REQ
15695. BFI_PORT_H2I_ENABLE_REQ
15696. BFI_PORT_H2I_GET_STATS_REQ
15697. BFI_PORT_I2H_CLEAR_STATS_RSP
15698. BFI_PORT_I2H_DISABLE_RSP
15699. BFI_PORT_I2H_ENABLE_RSP
15700. BFI_PORT_I2H_GET_STATS_RSP
15701. BFI_PORT_MODE_ETH
15702. BFI_PORT_MODE_FC
15703. BFI_RPORT_H2I_CREATE_REQ
15704. BFI_RPORT_H2I_DELETE_REQ
15705. BFI_RPORT_H2I_SET_SPEED_REQ
15706. BFI_RPORT_I2H_CREATE_RSP
15707. BFI_RPORT_I2H_DELETE_RSP
15708. BFI_RPORT_I2H_LIP_SCN_OFFLINE
15709. BFI_RPORT_I2H_LIP_SCN_ONLINE
15710. BFI_RPORT_I2H_NO_DEV
15711. BFI_RPORT_I2H_QOS_SCN
15712. BFI_RXQ_WI_SIZE
15713. BFI_RX_COALESCING_TIMEO
15714. BFI_RX_INTERPKT_COUNT
15715. BFI_RX_INTERPKT_TIMEO
15716. BFI_SFP_H2I_SCN
15717. BFI_SFP_H2I_SHOW
15718. BFI_SFP_I2H_SCN
15719. BFI_SFP_I2H_SHOW
15720. BFI_SFP_MEM_ALL
15721. BFI_SFP_MEM_DIAGEXT
15722. BFI_SGE_DATA
15723. BFI_SGE_DATA_CPL
15724. BFI_SGE_DATA_LAST
15725. BFI_SGE_INLINE
15726. BFI_SGE_INLINE_MAX
15727. BFI_SGE_LINK
15728. BFI_SGE_PGDLEN
15729. BFI_SGPG_DATA_SGES
15730. BFI_SGPG_RSVD_WD_LEN
15731. BFI_SGPG_SGES_MAX
15732. BFI_SMALL_RXBUF_SIZE
15733. BFI_SMEM_CB_SIZE
15734. BFI_SMEM_CT_SIZE
15735. BFI_TFRU_H2I_READ_REQ
15736. BFI_TFRU_H2I_WRITE_REQ
15737. BFI_TFRU_I2H_READ_RSP
15738. BFI_TFRU_I2H_WRITE_RSP
15739. BFI_TSKIM_H2I_ABORT_REQ
15740. BFI_TSKIM_H2I_TM_REQ
15741. BFI_TSKIM_I2H_TM_RSP
15742. BFI_TSKIM_STS_ABORTED
15743. BFI_TSKIM_STS_FAILED
15744. BFI_TSKIM_STS_NOT_SUPP
15745. BFI_TSKIM_STS_OK
15746. BFI_TSKIM_STS_TIMEOUT
15747. BFI_TSKIM_STS_UTAG
15748. BFI_TXQ_WI_SIZE
15749. BFI_TX_COALESCING_TIMEO
15750. BFI_TX_INTERPKT_COUNT
15751. BFI_TX_INTERPKT_TIMEO
15752. BFI_TX_MAX_DATA_PER_PKT
15753. BFI_TX_MAX_DATA_PER_VECTOR
15754. BFI_TX_MAX_PRIO
15755. BFI_TX_MAX_VECTORS_PER_PKT
15756. BFI_TX_MAX_VECTORS_PER_WI
15757. BFI_TX_MAX_WRR_QUOTA
15758. BFI_TX_PRIO_MAP_ALL
15759. BFI_UF_H2I_BUF_POST
15760. BFI_UF_I2H_FRM_RCVD
15761. BFI_VLAN_BLOCK_SHIFT
15762. BFI_VLAN_BMASK_ALL
15763. BFI_VLAN_WORD_MASK
15764. BFI_VLAN_WORD_SHIFT
15765. BFL
15766. BFL2_2G_SPUR_WAR
15767. BFL2_2X4_DIV
15768. BFL2_5G_PWRGAIN
15769. BFL2_APLL_WAR
15770. BFL2_GPLL_WAR
15771. BFL2_GPLL_WAR2
15772. BFL2_INTERNDET_TXIQCAL
15773. BFL2_IPALVLSHIFT_3P3
15774. BFL2_LEGACY
15775. BFL2_PCIEWAR_OVR
15776. BFL2_RXBB_INT_REG_DIS
15777. BFL2_SINGLEANT_CCK
15778. BFL2_SKWRKFEM_BRD
15779. BFL2_SPUR_WAR
15780. BFL2_TXPWRCTRL_EN
15781. BFL2_XTALBUFOUTEN
15782. BFLH
15783. BFLL
15784. BFLTR_TC_MASK
15785. BFLTR_THR_MASK
15786. BFL_BUCKBOOST
15787. BFL_EXTLNA
15788. BFL_EXTLNA_5GHz
15789. BFL_FEM
15790. BFL_FEM_BT
15791. BFL_NOCBUCK
15792. BFL_NOPA
15793. BFL_NOPLLDOWN
15794. BFL_PACTRL
15795. BFL_PALDO
15796. BFM_BASE
15797. BFNAMESIZE
15798. BFPREG
15799. BFPT_DWORD
15800. BFPT_DWORD11_PAGE_SIZE_MASK
15801. BFPT_DWORD11_PAGE_SIZE_SHIFT
15802. BFPT_DWORD15_QER_MASK
15803. BFPT_DWORD15_QER_NONE
15804. BFPT_DWORD15_QER_SR1_BIT6
15805. BFPT_DWORD15_QER_SR2_BIT1
15806. BFPT_DWORD15_QER_SR2_BIT1_BUGGY
15807. BFPT_DWORD15_QER_SR2_BIT1_NO_RD
15808. BFPT_DWORD15_QER_SR2_BIT7
15809. BFPT_DWORD1_ADDRESS_BYTES_3_ONLY
15810. BFPT_DWORD1_ADDRESS_BYTES_3_OR_4
15811. BFPT_DWORD1_ADDRESS_BYTES_4_ONLY
15812. BFPT_DWORD1_ADDRESS_BYTES_MASK
15813. BFPT_DWORD1_DTR
15814. BFPT_DWORD1_FAST_READ_1_1_2
15815. BFPT_DWORD1_FAST_READ_1_1_4
15816. BFPT_DWORD1_FAST_READ_1_2_2
15817. BFPT_DWORD1_FAST_READ_1_4_4
15818. BFPT_DWORD5_FAST_READ_2_2_2
15819. BFPT_DWORD5_FAST_READ_4_4_4
15820. BFPT_DWORD_MAX
15821. BFPT_DWORD_MAX_JESD216
15822. BFQG_FLAG_FNS
15823. BFQG_stats_empty
15824. BFQG_stats_idling
15825. BFQG_stats_waiting
15826. BFQQE_BUDGET_EXHAUSTED
15827. BFQQE_BUDGET_TIMEOUT
15828. BFQQE_NO_MORE_REQUESTS
15829. BFQQE_PREEMPTED
15830. BFQQE_TOO_IDLE
15831. BFQQF_IO_bound
15832. BFQQF_busy
15833. BFQQF_coop
15834. BFQQF_fifo_expire
15835. BFQQF_has_short_ttime
15836. BFQQF_has_waker
15837. BFQQF_in_large_burst
15838. BFQQF_just_created
15839. BFQQF_non_blocking_wait_rq
15840. BFQQF_softrt_update
15841. BFQQF_split_coop
15842. BFQQF_sync
15843. BFQQF_wait_request
15844. BFQQ_CLOSE_THR
15845. BFQQ_SECT_THR_NONROT
15846. BFQQ_SEEKY
15847. BFQQ_SEEK_THR
15848. BFQQ_TOTALLY_SEEKY
15849. BFQ_ATTR
15850. BFQ_BFQQ_FNS
15851. BFQ_CL_IDLE_TIMEOUT
15852. BFQ_DEFAULT_GRP_CLASS
15853. BFQ_DEFAULT_GRP_IOPRIO
15854. BFQ_DEFAULT_QUEUE_IOPRIO
15855. BFQ_HW_QUEUE_SAMPLES
15856. BFQ_HW_QUEUE_THRESHOLD
15857. BFQ_IOPRIO_CLASSES
15858. BFQ_MAX_WEIGHT
15859. BFQ_MIN_TT
15860. BFQ_MIN_WEIGHT
15861. BFQ_RATE_MIN_INTERVAL
15862. BFQ_RATE_MIN_SAMPLES
15863. BFQ_RATE_REF_INTERVAL
15864. BFQ_RATE_SHIFT
15865. BFQ_RQ1_WRAP
15866. BFQ_RQ2_WRAP
15867. BFQ_RQ_SEEKY
15868. BFQ_SERVICE_TREE_INIT
15869. BFQ_SOFTRT_WEIGHT_FACTOR
15870. BFQ_WEIGHT_CONVERSION_COEFF
15871. BFQ_WEIGHT_LEGACY_DFL
15872. BFRAME_BIDIR
15873. BFRAME_DC_LENGTH
15874. BFRAME_EMPTY
15875. BFRAME_GI2_TH
15876. BFRAME_POST
15877. BFRAME_PRE
15878. BFRAME_TH
15879. BFRAME_TH_2
15880. BFRAME_WEIGHT_SHORT
15881. BFRCCLK
15882. BFRE
15883. BFS
15884. BFSCODE
15885. BFSU
15886. BFS_BSIZE
15887. BFS_BSIZE_BITS
15888. BFS_DIRENT_SIZE
15889. BFS_DIRS_PER_BLOCK
15890. BFS_FILEBLOCKS
15891. BFS_FILESIZE
15892. BFS_I
15893. BFS_INO2OFF
15894. BFS_INODES_PER_BLOCK
15895. BFS_MAGIC
15896. BFS_MAX_LASTI
15897. BFS_NAMELEN
15898. BFS_NZFILESIZE
15899. BFS_OFF2INO
15900. BFS_OPTION
15901. BFS_ROOT_INO
15902. BFS_SB
15903. BFS_UNCLEAN
15904. BFS_VDIR
15905. BFS_VREG
15906. BFUSB_BLOCK_TIMEOUT
15907. BFUSB_MAX_BLOCK_SIZE
15908. BFUSB_MAX_BULK_RX
15909. BFUSB_MAX_BULK_TX
15910. BFUSB_TX_PROCESS
15911. BFUSB_TX_WAKEUP
15912. BF_64BITS_ADR
15913. BF_ANA_ISO_CNTL_IND__BF_ANA_ISO_DIS_MASK_MASK
15914. BF_ANA_ISO_CNTL_IND__BF_ANA_ISO_DIS_MASK__SHIFT
15915. BF_ANA_ISO_CNTL_IND__BF_VDDC_ISO_DIS_MASK_MASK
15916. BF_ANA_ISO_CNTL_IND__BF_VDDC_ISO_DIS_MASK__SHIFT
15917. BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK
15918. BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT
15919. BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK
15920. BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT
15921. BF_BCH_FLASH0LAYOUT0_DATA0_SIZE
15922. BF_BCH_FLASH0LAYOUT0_ECC0
15923. BF_BCH_FLASH0LAYOUT0_GF
15924. BF_BCH_FLASH0LAYOUT0_META_SIZE
15925. BF_BCH_FLASH0LAYOUT0_NBLOCKS
15926. BF_BCH_FLASH0LAYOUT1_DATAN_SIZE
15927. BF_BCH_FLASH0LAYOUT1_ECCN
15928. BF_BCH_FLASH0LAYOUT1_GF
15929. BF_BCH_FLASH0LAYOUT1_PAGE_SIZE
15930. BF_BLOCK_SIZE
15931. BF_CCW
15932. BF_CIRCULAR
15933. BF_CURRENT
15934. BF_DST_CFG0_OFFSET
15935. BF_DST_CFG1_OFFSET
15936. BF_DST_CFG2_OFFSET
15937. BF_DST_CFGX_BUFFER_PAIR_ENABLE
15938. BF_DST_CFGX_CAP_ENA
15939. BF_DST_CFGX_CAP_MODE
15940. BF_DST_CFGX_DFIFO_SZ_DOUBLE
15941. BF_DST_CFGX_FCI_ID
15942. BF_DST_CFGX_NOT_PAUSE_WHEN_FULL
15943. BF_DST_CFGX_PROC_SEQ_ID_VALID
15944. BF_DST_CTRL0_OFFSET
15945. BF_DST_CTRL1_OFFSET
15946. BF_DST_CTRL2_OFFSET
15947. BF_EOB
15948. BF_GPMI_CTRL0_ADDRESS
15949. BF_GPMI_CTRL0_COMMAND_MODE
15950. BF_GPMI_CTRL0_CS
15951. BF_GPMI_CTRL0_LOCK_CS
15952. BF_GPMI_CTRL0_XFER_COUNT
15953. BF_GPMI_CTRL1_RDN_DELAY
15954. BF_GPMI_CTRL1_WRN_DLY_SEL
15955. BF_GPMI_ECCCTRL_BUFFER_MASK
15956. BF_GPMI_ECCCTRL_ECC_CMD
15957. BF_GPMI_TIMING0_ADDRESS_SETUP
15958. BF_GPMI_TIMING0_DATA_HOLD
15959. BF_GPMI_TIMING0_DATA_SETUP
15960. BF_GPMI_TIMING1_BUSY_TIMEOUT
15961. BF_MAX_KEY_SIZE
15962. BF_MIN_KEY_SIZE
15963. BF_NOTIFY_EOB
15964. BF_PAUSE
15965. BF_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE
15966. BF_PXP_ALPHA_A_CTRL_RSVD0
15967. BF_PXP_ALPHA_A_CTRL_RSVD1
15968. BF_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE
15969. BF_PXP_ALPHA_A_CTRL_S0_COLOR_MODE
15970. BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA
15971. BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE
15972. BF_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE
15973. BF_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE
15974. BF_PXP_ALPHA_A_CTRL_S1_COLOR_MODE
15975. BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA
15976. BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE
15977. BF_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE
15978. BF_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE
15979. BF_PXP_ALPHA_B_CTRL_1_ROP
15980. BF_PXP_ALPHA_B_CTRL_1_ROP_ENABLE
15981. BF_PXP_ALPHA_B_CTRL_1_RSVD0
15982. BF_PXP_ALPHA_B_CTRL_1_RSVD1
15983. BF_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE
15984. BF_PXP_ALPHA_B_CTRL_RSVD0
15985. BF_PXP_ALPHA_B_CTRL_RSVD1
15986. BF_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE
15987. BF_PXP_ALPHA_B_CTRL_S0_COLOR_MODE
15988. BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA
15989. BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE
15990. BF_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE
15991. BF_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE
15992. BF_PXP_ALPHA_B_CTRL_S1_COLOR_MODE
15993. BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA
15994. BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE
15995. BF_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE
15996. BF_PXP_AS_BUF_ADDR
15997. BF_PXP_AS_CLRKEYHIGH_0_PIXEL
15998. BF_PXP_AS_CLRKEYHIGH_0_RSVD1
15999. BF_PXP_AS_CLRKEYHIGH_1_PIXEL
16000. BF_PXP_AS_CLRKEYHIGH_1_RSVD1
16001. BF_PXP_AS_CLRKEYLOW_0_PIXEL
16002. BF_PXP_AS_CLRKEYLOW_0_RSVD1
16003. BF_PXP_AS_CLRKEYLOW_1_PIXEL
16004. BF_PXP_AS_CLRKEYLOW_1_RSVD1
16005. BF_PXP_AS_CTRL_ALPHA
16006. BF_PXP_AS_CTRL_ALPHA0_INVERT
16007. BF_PXP_AS_CTRL_ALPHA1_INVERT
16008. BF_PXP_AS_CTRL_ALPHA_CTRL
16009. BF_PXP_AS_CTRL_ENABLE_COLORKEY
16010. BF_PXP_AS_CTRL_FORMAT
16011. BF_PXP_AS_CTRL_ROP
16012. BF_PXP_AS_CTRL_RSVD0
16013. BF_PXP_AS_CTRL_RSVD1
16014. BF_PXP_AS_PITCH_PITCH
16015. BF_PXP_AS_PITCH_RSVD
16016. BF_PXP_CFA_DATA
16017. BF_PXP_CSC1_COEF0_BYPASS
16018. BF_PXP_CSC1_COEF0_C0
16019. BF_PXP_CSC1_COEF0_RSVD1
16020. BF_PXP_CSC1_COEF0_UV_OFFSET
16021. BF_PXP_CSC1_COEF0_YCBCR_MODE
16022. BF_PXP_CSC1_COEF0_Y_OFFSET
16023. BF_PXP_CSC1_COEF1_C1
16024. BF_PXP_CSC1_COEF1_C4
16025. BF_PXP_CSC1_COEF1_RSVD0
16026. BF_PXP_CSC1_COEF1_RSVD1
16027. BF_PXP_CSC1_COEF2_C2
16028. BF_PXP_CSC1_COEF2_C3
16029. BF_PXP_CSC1_COEF2_RSVD0
16030. BF_PXP_CSC1_COEF2_RSVD1
16031. BF_PXP_CSC2_COEF0_A1
16032. BF_PXP_CSC2_COEF0_A2
16033. BF_PXP_CSC2_COEF0_RSVD0
16034. BF_PXP_CSC2_COEF0_RSVD1
16035. BF_PXP_CSC2_COEF1_A3
16036. BF_PXP_CSC2_COEF1_B1
16037. BF_PXP_CSC2_COEF1_RSVD0
16038. BF_PXP_CSC2_COEF1_RSVD1
16039. BF_PXP_CSC2_COEF2_B2
16040. BF_PXP_CSC2_COEF2_B3
16041. BF_PXP_CSC2_COEF2_RSVD0
16042. BF_PXP_CSC2_COEF2_RSVD1
16043. BF_PXP_CSC2_COEF3_C1
16044. BF_PXP_CSC2_COEF3_C2
16045. BF_PXP_CSC2_COEF3_RSVD0
16046. BF_PXP_CSC2_COEF3_RSVD1
16047. BF_PXP_CSC2_COEF4_C3
16048. BF_PXP_CSC2_COEF4_D1
16049. BF_PXP_CSC2_COEF4_RSVD0
16050. BF_PXP_CSC2_COEF4_RSVD1
16051. BF_PXP_CSC2_COEF5_D2
16052. BF_PXP_CSC2_COEF5_D3
16053. BF_PXP_CSC2_COEF5_RSVD0
16054. BF_PXP_CSC2_COEF5_RSVD1
16055. BF_PXP_CSC2_CTRL_BYPASS
16056. BF_PXP_CSC2_CTRL_CSC_MODE
16057. BF_PXP_CSC2_CTRL_RSVD
16058. BF_PXP_CTRL2_BLOCK_SIZE
16059. BF_PXP_CTRL2_ENABLE
16060. BF_PXP_CTRL2_ENABLE_ALPHA_B
16061. BF_PXP_CTRL2_ENABLE_CSC2
16062. BF_PXP_CTRL2_ENABLE_DITHER
16063. BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE
16064. BF_PXP_CTRL2_ENABLE_LUT
16065. BF_PXP_CTRL2_ENABLE_ROTATE0
16066. BF_PXP_CTRL2_ENABLE_ROTATE1
16067. BF_PXP_CTRL2_ENABLE_WFE_A
16068. BF_PXP_CTRL2_ENABLE_WFE_B
16069. BF_PXP_CTRL2_HFLIP0
16070. BF_PXP_CTRL2_HFLIP1
16071. BF_PXP_CTRL2_ROTATE0
16072. BF_PXP_CTRL2_ROTATE1
16073. BF_PXP_CTRL2_RSVD0
16074. BF_PXP_CTRL2_RSVD1
16075. BF_PXP_CTRL2_RSVD2
16076. BF_PXP_CTRL2_RSVD3
16077. BF_PXP_CTRL2_VFLIP0
16078. BF_PXP_CTRL2_VFLIP1
16079. BF_PXP_CTRL_BLOCK_SIZE
16080. BF_PXP_CTRL_CLKGATE
16081. BF_PXP_CTRL_ENABLE
16082. BF_PXP_CTRL_ENABLE_ALPHA_B
16083. BF_PXP_CTRL_ENABLE_CSC2
16084. BF_PXP_CTRL_ENABLE_DITHER
16085. BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE
16086. BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE
16087. BF_PXP_CTRL_ENABLE_LUT
16088. BF_PXP_CTRL_ENABLE_PS_AS_OUT
16089. BF_PXP_CTRL_ENABLE_ROTATE0
16090. BF_PXP_CTRL_ENABLE_ROTATE1
16091. BF_PXP_CTRL_ENABLE_WFE_A
16092. BF_PXP_CTRL_ENABLE_WFE_B
16093. BF_PXP_CTRL_EN_REPEAT
16094. BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP
16095. BF_PXP_CTRL_HFLIP0
16096. BF_PXP_CTRL_HFLIP1
16097. BF_PXP_CTRL_IRQ_ENABLE
16098. BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE
16099. BF_PXP_CTRL_NEXT_IRQ_ENABLE
16100. BF_PXP_CTRL_ROTATE0
16101. BF_PXP_CTRL_ROTATE1
16102. BF_PXP_CTRL_RSVD0
16103. BF_PXP_CTRL_RSVD1
16104. BF_PXP_CTRL_RSVD4
16105. BF_PXP_CTRL_SFTRST
16106. BF_PXP_CTRL_VFLIP0
16107. BF_PXP_CTRL_VFLIP1
16108. BF_PXP_DATA_PATH_CTRL0_MUX0_SEL
16109. BF_PXP_DATA_PATH_CTRL0_MUX10_SEL
16110. BF_PXP_DATA_PATH_CTRL0_MUX11_SEL
16111. BF_PXP_DATA_PATH_CTRL0_MUX12_SEL
16112. BF_PXP_DATA_PATH_CTRL0_MUX13_SEL
16113. BF_PXP_DATA_PATH_CTRL0_MUX14_SEL
16114. BF_PXP_DATA_PATH_CTRL0_MUX15_SEL
16115. BF_PXP_DATA_PATH_CTRL0_MUX1_SEL
16116. BF_PXP_DATA_PATH_CTRL0_MUX2_SEL
16117. BF_PXP_DATA_PATH_CTRL0_MUX3_SEL
16118. BF_PXP_DATA_PATH_CTRL0_MUX4_SEL
16119. BF_PXP_DATA_PATH_CTRL0_MUX5_SEL
16120. BF_PXP_DATA_PATH_CTRL0_MUX6_SEL
16121. BF_PXP_DATA_PATH_CTRL0_MUX7_SEL
16122. BF_PXP_DATA_PATH_CTRL0_MUX8_SEL
16123. BF_PXP_DATA_PATH_CTRL0_MUX9_SEL
16124. BF_PXP_DATA_PATH_CTRL1_MUX16_SEL
16125. BF_PXP_DATA_PATH_CTRL1_MUX17_SEL
16126. BF_PXP_DATA_PATH_CTRL1_RSVD0
16127. BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT
16128. BF_PXP_DEBUGCTRL_RSVD
16129. BF_PXP_DEBUGCTRL_SELECT
16130. BF_PXP_DEBUG_DATA
16131. BF_PXP_INIT_MEM_CTRL_ADDR
16132. BF_PXP_INIT_MEM_CTRL_RSVD0
16133. BF_PXP_INIT_MEM_CTRL_SELECT
16134. BF_PXP_INIT_MEM_CTRL_START
16135. BF_PXP_INIT_MEM_DATA_DATA
16136. BF_PXP_INIT_MEM_DATA_HIGH_DATA
16137. BF_PXP_IRQ_COMPRESS_DONE_IRQ
16138. BF_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ
16139. BF_PXP_IRQ_DITHER_CH0_STORE_IRQ
16140. BF_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ
16141. BF_PXP_IRQ_DITHER_CH1_STORE_IRQ
16142. BF_PXP_IRQ_DITHER_STORE_IRQ
16143. BF_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ
16144. BF_PXP_IRQ_FIRST_CH0_STORE_IRQ
16145. BF_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ
16146. BF_PXP_IRQ_FIRST_CH1_STORE_IRQ
16147. BF_PXP_IRQ_FIRST_STORE_IRQ
16148. BF_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN
16149. BF_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN
16150. BF_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN
16151. BF_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN
16152. BF_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN
16153. BF_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN
16154. BF_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN
16155. BF_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN
16156. BF_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN
16157. BF_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN
16158. BF_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN
16159. BF_PXP_IRQ_MASK_RSVD1
16160. BF_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN
16161. BF_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN
16162. BF_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN
16163. BF_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN
16164. BF_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN
16165. BF_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN
16166. BF_PXP_IRQ_RSVD1
16167. BF_PXP_IRQ_WFE_A_CH0_STORE_IRQ
16168. BF_PXP_IRQ_WFE_A_CH1_STORE_IRQ
16169. BF_PXP_IRQ_WFE_A_STORE_IRQ
16170. BF_PXP_IRQ_WFE_B_CH0_STORE_IRQ
16171. BF_PXP_IRQ_WFE_B_CH1_STORE_IRQ
16172. BF_PXP_IRQ_WFE_B_STORE_IRQ
16173. BF_PXP_LUT_ADDR_ADDR
16174. BF_PXP_LUT_ADDR_NUM_BYTES
16175. BF_PXP_LUT_ADDR_RSVD1
16176. BF_PXP_LUT_ADDR_RSVD2
16177. BF_PXP_LUT_CTRL_BYPASS
16178. BF_PXP_LUT_CTRL_DMA_START
16179. BF_PXP_LUT_CTRL_INVALID
16180. BF_PXP_LUT_CTRL_LOOKUP_MODE
16181. BF_PXP_LUT_CTRL_LRU_UPD
16182. BF_PXP_LUT_CTRL_OUT_MODE
16183. BF_PXP_LUT_CTRL_RSVD0
16184. BF_PXP_LUT_CTRL_RSVD1
16185. BF_PXP_LUT_CTRL_RSVD2
16186. BF_PXP_LUT_CTRL_RSVD3
16187. BF_PXP_LUT_CTRL_SEL_8KB
16188. BF_PXP_LUT_DATA_DATA
16189. BF_PXP_LUT_EXTMEM_ADDR
16190. BF_PXP_NEXT_ENABLED
16191. BF_PXP_NEXT_POINTER
16192. BF_PXP_NEXT_RSVD
16193. BF_PXP_OUT_AS_LRC_RSVD0
16194. BF_PXP_OUT_AS_LRC_RSVD1
16195. BF_PXP_OUT_AS_LRC_X
16196. BF_PXP_OUT_AS_LRC_Y
16197. BF_PXP_OUT_AS_ULC_RSVD0
16198. BF_PXP_OUT_AS_ULC_RSVD1
16199. BF_PXP_OUT_AS_ULC_X
16200. BF_PXP_OUT_AS_ULC_Y
16201. BF_PXP_OUT_BUF2_ADDR
16202. BF_PXP_OUT_BUF_ADDR
16203. BF_PXP_OUT_CTRL_ALPHA
16204. BF_PXP_OUT_CTRL_ALPHA_OUTPUT
16205. BF_PXP_OUT_CTRL_FORMAT
16206. BF_PXP_OUT_CTRL_INTERLACED_OUTPUT
16207. BF_PXP_OUT_CTRL_RSVD0
16208. BF_PXP_OUT_CTRL_RSVD1
16209. BF_PXP_OUT_LRC_RSVD0
16210. BF_PXP_OUT_LRC_RSVD1
16211. BF_PXP_OUT_LRC_X
16212. BF_PXP_OUT_LRC_Y
16213. BF_PXP_OUT_PITCH_PITCH
16214. BF_PXP_OUT_PITCH_RSVD
16215. BF_PXP_OUT_PS_LRC_RSVD0
16216. BF_PXP_OUT_PS_LRC_RSVD1
16217. BF_PXP_OUT_PS_LRC_X
16218. BF_PXP_OUT_PS_LRC_Y
16219. BF_PXP_OUT_PS_ULC_RSVD0
16220. BF_PXP_OUT_PS_ULC_RSVD1
16221. BF_PXP_OUT_PS_ULC_X
16222. BF_PXP_OUT_PS_ULC_Y
16223. BF_PXP_POWER_REG0_CTRL
16224. BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0
16225. BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN
16226. BF_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN
16227. BF_PXP_POWER_REG0_ROT0_MEM_LP_STATE
16228. BF_PXP_POWER_REG1_ALU_A_MEM_LP_STATE
16229. BF_PXP_POWER_REG1_ALU_B_MEM_LP_STATE
16230. BF_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE
16231. BF_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE
16232. BF_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE
16233. BF_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE
16234. BF_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE
16235. BF_PXP_POWER_REG1_ROT1_MEM_LP_STATE
16236. BF_PXP_POWER_REG1_RSVD0
16237. BF_PXP_PS_BACKGROUND_0_COLOR
16238. BF_PXP_PS_BACKGROUND_0_RSVD
16239. BF_PXP_PS_BACKGROUND_1_COLOR
16240. BF_PXP_PS_BACKGROUND_1_RSVD
16241. BF_PXP_PS_BUF_ADDR
16242. BF_PXP_PS_CLRKEYHIGH_0_PIXEL
16243. BF_PXP_PS_CLRKEYHIGH_0_RSVD1
16244. BF_PXP_PS_CLRKEYHIGH_1_PIXEL
16245. BF_PXP_PS_CLRKEYHIGH_1_RSVD1
16246. BF_PXP_PS_CLRKEYLOW_0_PIXEL
16247. BF_PXP_PS_CLRKEYLOW_0_RSVD1
16248. BF_PXP_PS_CLRKEYLOW_1_PIXEL
16249. BF_PXP_PS_CLRKEYLOW_1_RSVD1
16250. BF_PXP_PS_CTRL_DECX
16251. BF_PXP_PS_CTRL_DECY
16252. BF_PXP_PS_CTRL_FORMAT
16253. BF_PXP_PS_CTRL_RSVD0
16254. BF_PXP_PS_CTRL_RSVD1
16255. BF_PXP_PS_CTRL_WB_SWAP
16256. BF_PXP_PS_OFFSET_RSVD1
16257. BF_PXP_PS_OFFSET_RSVD2
16258. BF_PXP_PS_OFFSET_XOFFSET
16259. BF_PXP_PS_OFFSET_YOFFSET
16260. BF_PXP_PS_PITCH_PITCH
16261. BF_PXP_PS_PITCH_RSVD
16262. BF_PXP_PS_SCALE_RSVD1
16263. BF_PXP_PS_SCALE_RSVD2
16264. BF_PXP_PS_SCALE_XSCALE
16265. BF_PXP_PS_SCALE_YSCALE
16266. BF_PXP_PS_UBUF_ADDR
16267. BF_PXP_PS_VBUF_ADDR
16268. BF_PXP_STAT_AXI_ERROR_ID_0
16269. BF_PXP_STAT_AXI_ERROR_ID_1
16270. BF_PXP_STAT_AXI_READ_ERROR_0
16271. BF_PXP_STAT_AXI_READ_ERROR_1
16272. BF_PXP_STAT_AXI_WRITE_ERROR_0
16273. BF_PXP_STAT_AXI_WRITE_ERROR_1
16274. BF_PXP_STAT_BLOCKX
16275. BF_PXP_STAT_BLOCKY
16276. BF_PXP_STAT_IRQ0
16277. BF_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ
16278. BF_PXP_STAT_NEXT_IRQ
16279. BF_PXP_STAT_RSVD2
16280. BF_PXP_VERSION_MAJOR
16281. BF_PXP_VERSION_MINOR
16282. BF_PXP_VERSION_STEP
16283. BF_REARM_FREE_MARK_OFFSET
16284. BF_REARM_FULL_MARK_OFFSET
16285. BF_RF_MARLON
16286. BF_RF_SPARROW
16287. BF_RF_TALYNA1
16288. BF_RF_TALYNA2
16289. BF_SAIF_CTRL_BITCLK_MULT_RATE
16290. BF_SAIF_CTRL_CHANNEL_NUM_SELECT
16291. BF_SAIF_CTRL_DMAWAIT_COUNT
16292. BF_SAIF_CTRL_WORD_LENGTH
16293. BF_SAIF_DATA_PCM_LEFT
16294. BF_SAIF_DATA_PCM_RIGHT
16295. BF_SAIF_STAT_RSRVD0
16296. BF_SAIF_STAT_RSRVD1
16297. BF_SAIF_STAT_RSRVD2
16298. BF_SAIF_VERSION_MAJOR
16299. BF_SAIF_VERSION_MINOR
16300. BF_SAIF_VERSION_STEP
16301. BF_SRC_CFG0_OFFSET
16302. BF_SRC_CFG1_OFFSET
16303. BF_SRC_CFG2_OFFSET
16304. BF_SRC_CFG3_OFFSET
16305. BF_SRC_CFGX_BIT_RES
16306. BF_SRC_CFGX_BUFFER_PAIR_ENABLE
16307. BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY
16308. BF_SRC_CFGX_PROCESS_SEQ_ID_VALID
16309. BF_SRC_CFGX_SAMPLE_CH_MODE
16310. BF_SRC_CFGX_SFIFO_ENA
16311. BF_SRC_CFGX_SFIFO_SZ_DOUBLE
16312. BF_SRC_CTRL0_OFFSET
16313. BF_SRC_CTRL1_OFFSET
16314. BF_SRC_CTRL2_OFFSET
16315. BF_SRC_CTRL3_OFFSET
16316. BF_SRC_GRP0_OFFSET
16317. BF_SRC_GRP1_OFFSET
16318. BF_SRC_GRP2_OFFSET
16319. BF_SRC_GRP3_OFFSET
16320. BF_SRC_GRP_EN_OFFSET
16321. BF_SRC_GRP_FLOWON_OFFSET
16322. BF_SRC_GRP_SYNC_DIS_OFFSET
16323. BF_SSP
16324. BF_SSP_CTRL1_SSP_MODE
16325. BF_SSP_CTRL1_WORD_LENGTH
16326. BF_SSP_TIMING_CLOCK_DIVIDE
16327. BF_SSP_TIMING_CLOCK_RATE
16328. BF_VALID
16329. BF_VS_VAL
16330. BF_ZERO
16331. BF_xx
16332. BG
16333. BG2Q_PHY_BASE
16334. BG2_PHY_BASE
16335. BGAIN_PAR_REG
16336. BGAP_TRIM
16337. BGCOLOR
16338. BGE
16339. BGEU
16340. BGI2_SYNC_EN
16341. BGI_TH
16342. BGLOBALRESETB
16343. BGMAC_ARCACHE
16344. BGMAC_ARUSER
16345. BGMAC_AWCACHE
16346. BGMAC_AWUSER
16347. BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ
16348. BGMAC_BCMA_CLKCTLST_MISC_PLL_ST
16349. BGMAC_BCMA_IOCTL_SW_CLKEN
16350. BGMAC_BCMA_IOCTL_SW_RESET
16351. BGMAC_BCMA_IOST_ATTACHED
16352. BGMAC_BFL_ENETADM
16353. BGMAC_BFL_ENETROBO
16354. BGMAC_BFL_ENETVLAN
16355. BGMAC_BIST_STATUS
16356. BGMAC_CHIPCTL_1_IF_TYPE_MASK
16357. BGMAC_CHIPCTL_1_IF_TYPE_MII
16358. BGMAC_CHIPCTL_1_IF_TYPE_RGMII
16359. BGMAC_CHIPCTL_1_IF_TYPE_RMII
16360. BGMAC_CHIPCTL_1_RXC_DLL_BYPASS
16361. BGMAC_CHIPCTL_1_SW_TYPE_EPHY
16362. BGMAC_CHIPCTL_1_SW_TYPE_EPHYMII
16363. BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII
16364. BGMAC_CHIPCTL_1_SW_TYPE_MASK
16365. BGMAC_CHIPCTL_1_SW_TYPE_RGMII
16366. BGMAC_CHIPCTL_4_IF_TYPE_MASK
16367. BGMAC_CHIPCTL_4_IF_TYPE_MII
16368. BGMAC_CHIPCTL_4_IF_TYPE_RGMII
16369. BGMAC_CHIPCTL_4_IF_TYPE_RMII
16370. BGMAC_CHIPCTL_4_SW_TYPE_EPHY
16371. BGMAC_CHIPCTL_4_SW_TYPE_EPHYMII
16372. BGMAC_CHIPCTL_4_SW_TYPE_EPHYRMII
16373. BGMAC_CHIPCTL_4_SW_TYPE_MASK
16374. BGMAC_CHIPCTL_4_SW_TYPE_RGMII
16375. BGMAC_CHIPCTL_7_IF_TYPE_MASK
16376. BGMAC_CHIPCTL_7_IF_TYPE_MII
16377. BGMAC_CHIPCTL_7_IF_TYPE_RGMII
16378. BGMAC_CHIPCTL_7_IF_TYPE_RMII
16379. BGMAC_CLK_250_SEL
16380. BGMAC_CLK_EN
16381. BGMAC_CMDCFG
16382. BGMAC_CMDCFG_AE
16383. BGMAC_CMDCFG_AT
16384. BGMAC_CMDCFG_CF
16385. BGMAC_CMDCFG_CFE
16386. BGMAC_CMDCFG_ES_10
16387. BGMAC_CMDCFG_ES_100
16388. BGMAC_CMDCFG_ES_1000
16389. BGMAC_CMDCFG_ES_2500
16390. BGMAC_CMDCFG_ES_MASK
16391. BGMAC_CMDCFG_HD
16392. BGMAC_CMDCFG_HD_SHIFT
16393. BGMAC_CMDCFG_ML
16394. BGMAC_CMDCFG_NLC
16395. BGMAC_CMDCFG_PAD_EN
16396. BGMAC_CMDCFG_PE
16397. BGMAC_CMDCFG_PF
16398. BGMAC_CMDCFG_PROM
16399. BGMAC_CMDCFG_RE
16400. BGMAC_CMDCFG_RED
16401. BGMAC_CMDCFG_RL
16402. BGMAC_CMDCFG_RPI
16403. BGMAC_CMDCFG_SR_REV0
16404. BGMAC_CMDCFG_SR_REV4
16405. BGMAC_CMDCFG_TAI
16406. BGMAC_CMDCFG_TE
16407. BGMAC_CMDCFG_TPI
16408. BGMAC_DC_CFCO
16409. BGMAC_DC_FCM_MASK
16410. BGMAC_DC_FCM_SHIFT
16411. BGMAC_DC_MROR
16412. BGMAC_DC_NAE
16413. BGMAC_DC_RDS_MASK
16414. BGMAC_DC_RDS_SHIFT
16415. BGMAC_DC_RLSS
16416. BGMAC_DC_TDS_MASK
16417. BGMAC_DC_TDS_SHIFT
16418. BGMAC_DC_TF
16419. BGMAC_DC_TSM
16420. BGMAC_DESC_CTL0_EOF
16421. BGMAC_DESC_CTL0_EOT
16422. BGMAC_DESC_CTL0_IOC
16423. BGMAC_DESC_CTL0_SOF
16424. BGMAC_DESC_CTL1_LEN
16425. BGMAC_DEST_SYNC_MODE_EN
16426. BGMAC_DEV_CTL
16427. BGMAC_DEV_STATUS
16428. BGMAC_DIRECT_GMII_MODE
16429. BGMAC_DMA_BASE0
16430. BGMAC_DMA_BASE1
16431. BGMAC_DMA_BASE2
16432. BGMAC_DMA_BASE3
16433. BGMAC_DMA_RING_RX
16434. BGMAC_DMA_RING_TX
16435. BGMAC_DMA_RX_ADDREXT_MASK
16436. BGMAC_DMA_RX_ADDREXT_SHIFT
16437. BGMAC_DMA_RX_BL_1024
16438. BGMAC_DMA_RX_BL_128
16439. BGMAC_DMA_RX_BL_16
16440. BGMAC_DMA_RX_BL_256
16441. BGMAC_DMA_RX_BL_32
16442. BGMAC_DMA_RX_BL_512
16443. BGMAC_DMA_RX_BL_64
16444. BGMAC_DMA_RX_BL_MASK
16445. BGMAC_DMA_RX_BL_SHIFT
16446. BGMAC_DMA_RX_CTL
16447. BGMAC_DMA_RX_DIRECT_FIFO
16448. BGMAC_DMA_RX_ENABLE
16449. BGMAC_DMA_RX_ERR
16450. BGMAC_DMA_RX_ERRDPTR
16451. BGMAC_DMA_RX_ERROR
16452. BGMAC_DMA_RX_ERR_CORE
16453. BGMAC_DMA_RX_ERR_DESCREAD
16454. BGMAC_DMA_RX_ERR_NOERR
16455. BGMAC_DMA_RX_ERR_PROT
16456. BGMAC_DMA_RX_ERR_TRANSFER
16457. BGMAC_DMA_RX_ERR_UNDERRUN
16458. BGMAC_DMA_RX_FRAME_OFFSET_MASK
16459. BGMAC_DMA_RX_FRAME_OFFSET_SHIFT
16460. BGMAC_DMA_RX_INDEX
16461. BGMAC_DMA_RX_MR_MASK
16462. BGMAC_DMA_RX_MR_SHIFT
16463. BGMAC_DMA_RX_OVERFLOW_CONT
16464. BGMAC_DMA_RX_PARITY_DISABLE
16465. BGMAC_DMA_RX_PC_0
16466. BGMAC_DMA_RX_PC_16
16467. BGMAC_DMA_RX_PC_4
16468. BGMAC_DMA_RX_PC_8
16469. BGMAC_DMA_RX_PC_MASK
16470. BGMAC_DMA_RX_PC_SHIFT
16471. BGMAC_DMA_RX_PT_1
16472. BGMAC_DMA_RX_PT_2
16473. BGMAC_DMA_RX_PT_4
16474. BGMAC_DMA_RX_PT_8
16475. BGMAC_DMA_RX_PT_MASK
16476. BGMAC_DMA_RX_PT_SHIFT
16477. BGMAC_DMA_RX_RINGHI
16478. BGMAC_DMA_RX_RINGLO
16479. BGMAC_DMA_RX_STAT
16480. BGMAC_DMA_RX_STATDPTR
16481. BGMAC_DMA_RX_STATUS
16482. BGMAC_DMA_RX_STAT_ACTIVE
16483. BGMAC_DMA_RX_STAT_DISABLED
16484. BGMAC_DMA_RX_STAT_IDLEWAIT
16485. BGMAC_DMA_RX_STAT_STOPPED
16486. BGMAC_DMA_RX_STAT_SUSP
16487. BGMAC_DMA_TX_ADDREXT_MASK
16488. BGMAC_DMA_TX_ADDREXT_SHIFT
16489. BGMAC_DMA_TX_BL_1024
16490. BGMAC_DMA_TX_BL_128
16491. BGMAC_DMA_TX_BL_16
16492. BGMAC_DMA_TX_BL_256
16493. BGMAC_DMA_TX_BL_32
16494. BGMAC_DMA_TX_BL_512
16495. BGMAC_DMA_TX_BL_64
16496. BGMAC_DMA_TX_BL_MASK
16497. BGMAC_DMA_TX_BL_SHIFT
16498. BGMAC_DMA_TX_CTL
16499. BGMAC_DMA_TX_ENABLE
16500. BGMAC_DMA_TX_ERR
16501. BGMAC_DMA_TX_ERRDPTR
16502. BGMAC_DMA_TX_ERROR
16503. BGMAC_DMA_TX_ERR_CORE
16504. BGMAC_DMA_TX_ERR_DESCREAD
16505. BGMAC_DMA_TX_ERR_NOERR
16506. BGMAC_DMA_TX_ERR_PROT
16507. BGMAC_DMA_TX_ERR_TRANSFER
16508. BGMAC_DMA_TX_ERR_UNDERRUN
16509. BGMAC_DMA_TX_FLUSH
16510. BGMAC_DMA_TX_INDEX
16511. BGMAC_DMA_TX_LOOPBACK
16512. BGMAC_DMA_TX_MR_1
16513. BGMAC_DMA_TX_MR_2
16514. BGMAC_DMA_TX_MR_MASK
16515. BGMAC_DMA_TX_MR_SHIFT
16516. BGMAC_DMA_TX_PARITY_DISABLE
16517. BGMAC_DMA_TX_PC_0
16518. BGMAC_DMA_TX_PC_16
16519. BGMAC_DMA_TX_PC_4
16520. BGMAC_DMA_TX_PC_8
16521. BGMAC_DMA_TX_PC_MASK
16522. BGMAC_DMA_TX_PC_SHIFT
16523. BGMAC_DMA_TX_PT_1
16524. BGMAC_DMA_TX_PT_2
16525. BGMAC_DMA_TX_PT_4
16526. BGMAC_DMA_TX_PT_8
16527. BGMAC_DMA_TX_PT_MASK
16528. BGMAC_DMA_TX_PT_SHIFT
16529. BGMAC_DMA_TX_RINGHI
16530. BGMAC_DMA_TX_RINGLO
16531. BGMAC_DMA_TX_STAT
16532. BGMAC_DMA_TX_STATDPTR
16533. BGMAC_DMA_TX_STATUS
16534. BGMAC_DMA_TX_STAT_ACTIVE
16535. BGMAC_DMA_TX_STAT_DISABLED
16536. BGMAC_DMA_TX_STAT_IDLEWAIT
16537. BGMAC_DMA_TX_STAT_STOPPED
16538. BGMAC_DMA_TX_STAT_SUSP
16539. BGMAC_DMA_TX_SUSPEND
16540. BGMAC_DS_MM_MASK
16541. BGMAC_DS_MM_SHIFT
16542. BGMAC_DS_PO
16543. BGMAC_DS_RBF
16544. BGMAC_DS_RDF
16545. BGMAC_DS_RIF
16546. BGMAC_DS_TBF
16547. BGMAC_DS_TDF
16548. BGMAC_DS_TIF
16549. BGMAC_FEAT_CC4_IF_SW_TYPE
16550. BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII
16551. BGMAC_FEAT_CC7_IF_TYPE_RGMII
16552. BGMAC_FEAT_CLKCTLST
16553. BGMAC_FEAT_CMDCFG_SR_REV4
16554. BGMAC_FEAT_CMN_PHY_CTL
16555. BGMAC_FEAT_FLW_CTRL1
16556. BGMAC_FEAT_FLW_CTRL2
16557. BGMAC_FEAT_FORCE_SPEED_2500
16558. BGMAC_FEAT_IDM_MASK
16559. BGMAC_FEAT_IOST_ATTACHED
16560. BGMAC_FEAT_IRQ_ID_OOB_6
16561. BGMAC_FEAT_MISC_PLL_REQ
16562. BGMAC_FEAT_NO_CLR_MIB
16563. BGMAC_FEAT_NO_RESET
16564. BGMAC_FEAT_RX_MASK_SETUP
16565. BGMAC_FEAT_SET_RXQ_CLK
16566. BGMAC_FEAT_SW_TYPE_EPHYRMII
16567. BGMAC_FEAT_SW_TYPE_PHY
16568. BGMAC_FEAT_SW_TYPE_RGMII
16569. BGMAC_FEAT_TX_MASK_SETUP
16570. BGMAC_FLOW_CTL_THRESH
16571. BGMAC_GMAC_IDLE_CNT_THRESH
16572. BGMAC_GPIO_OUTPUT_EN
16573. BGMAC_GPIO_SELECT
16574. BGMAC_GP_TIMER
16575. BGMAC_HDBKP_CTL
16576. BGMAC_HW_WAR
16577. BGMAC_INNERTAG
16578. BGMAC_INT_MASK
16579. BGMAC_INT_RECV_LAZY
16580. BGMAC_INT_STATUS
16581. BGMAC_IRL_FC_MASK
16582. BGMAC_IRL_FC_SHIFT
16583. BGMAC_IRL_TO_MASK
16584. BGMAC_IS_DATA_ERR
16585. BGMAC_IS_DESC_ERR
16586. BGMAC_IS_DESC_PROT_ERR
16587. BGMAC_IS_ERRMASK
16588. BGMAC_IS_INTMASK
16589. BGMAC_IS_LS
16590. BGMAC_IS_MDIO
16591. BGMAC_IS_MR
16592. BGMAC_IS_MRO
16593. BGMAC_IS_MT
16594. BGMAC_IS_MTO
16595. BGMAC_IS_RX
16596. BGMAC_IS_RX_DESC_UNDERF
16597. BGMAC_IS_RX_F_OVERF
16598. BGMAC_IS_TFD
16599. BGMAC_IS_TO
16600. BGMAC_IS_TX0
16601. BGMAC_IS_TX1
16602. BGMAC_IS_TX2
16603. BGMAC_IS_TX3
16604. BGMAC_IS_TX_F_UNDERF
16605. BGMAC_IS_TX_MASK
16606. BGMAC_MACADDR_HIGH
16607. BGMAC_MACADDR_LOW
16608. BGMAC_MAC_MODE
16609. BGMAC_MAX_RX_RINGS
16610. BGMAC_MAX_TX_RINGS
16611. BGMAC_NUM_MIB_RX_REGS
16612. BGMAC_NUM_MIB_TX_REGS
16613. BGMAC_OUTERTAG
16614. BGMAC_PAUSEQUANTA
16615. BGMAC_PAUSE_CTL
16616. BGMAC_PA_ADDR_MASK
16617. BGMAC_PA_ADDR_SHIFT
16618. BGMAC_PA_DATA_MASK
16619. BGMAC_PA_REG_MASK
16620. BGMAC_PA_REG_SHIFT
16621. BGMAC_PA_START
16622. BGMAC_PA_WRITE
16623. BGMAC_PC_EPA_MASK
16624. BGMAC_PC_MCT_MASK
16625. BGMAC_PC_MCT_SHIFT
16626. BGMAC_PC_MTE
16627. BGMAC_PHY_ACCESS
16628. BGMAC_PHY_CNTL
16629. BGMAC_PHY_MASK
16630. BGMAC_PHY_NOREGS
16631. BGMAC_PM_OPS
16632. BGMAC_PWR_CTL
16633. BGMAC_RESERVED
16634. BGMAC_RESERVED_0
16635. BGMAC_RESERVED_1
16636. BGMAC_RXMAX_LENGTH
16637. BGMAC_RXQ_CTL
16638. BGMAC_RXQ_CTL_DBT_MASK
16639. BGMAC_RXQ_CTL_DBT_SHIFT
16640. BGMAC_RXQ_CTL_MDP_MASK
16641. BGMAC_RXQ_CTL_MDP_SHIFT
16642. BGMAC_RXQ_CTL_PTE
16643. BGMAC_RX_ALIGN_ERRS
16644. BGMAC_RX_ALLOC_SIZE
16645. BGMAC_RX_BROADCAST_PKTS
16646. BGMAC_RX_BUF_OFFSET
16647. BGMAC_RX_BUF_SIZE
16648. BGMAC_RX_CRC_ALIGN_ERRS
16649. BGMAC_RX_CRC_ERRS
16650. BGMAC_RX_FRAGMENT_PKTS
16651. BGMAC_RX_FRAME_OFFSET
16652. BGMAC_RX_GOOD_OCTETS
16653. BGMAC_RX_GOOD_OCTETS_HIGH
16654. BGMAC_RX_GOOD_PKTS
16655. BGMAC_RX_HEADER_LEN
16656. BGMAC_RX_JABBER_PKTS
16657. BGMAC_RX_LEN_1024_TO_1522
16658. BGMAC_RX_LEN_128_TO_255
16659. BGMAC_RX_LEN_1523_TO_2047
16660. BGMAC_RX_LEN_2048_TO_4095
16661. BGMAC_RX_LEN_256_TO_511
16662. BGMAC_RX_LEN_4096_TO_8191
16663. BGMAC_RX_LEN_512_TO_1023
16664. BGMAC_RX_LEN_64
16665. BGMAC_RX_LEN_65_TO_127
16666. BGMAC_RX_LEN_8192_TO_MAX
16667. BGMAC_RX_MAX_FRAME_SIZE
16668. BGMAC_RX_MISSED_PKTS
16669. BGMAC_RX_MULTICAST_PKTS
16670. BGMAC_RX_NONPAUSE_PKTS
16671. BGMAC_RX_OCTETS
16672. BGMAC_RX_OCTETS_HIGH
16673. BGMAC_RX_OVERSIZE_PKTS
16674. BGMAC_RX_PAUSE_PKTS
16675. BGMAC_RX_PKTS
16676. BGMAC_RX_RING_SLOTS
16677. BGMAC_RX_SACHANGES
16678. BGMAC_RX_STATUS
16679. BGMAC_RX_SYMBOL_ERRS
16680. BGMAC_RX_UNDERSIZE
16681. BGMAC_RX_UNI_PKTS
16682. BGMAC_SOURCE_SYNC_MODE_EN
16683. BGMAC_STATS_LEN
16684. BGMAC_TXIPG
16685. BGMAC_TXQ_CTL
16686. BGMAC_TXQ_CTL_DBT_MASK
16687. BGMAC_TXQ_CTL_DBT_SHIFT
16688. BGMAC_TX_BROADCAST_PKTS
16689. BGMAC_TX_CARRIER_LOST
16690. BGMAC_TX_CLK_OUT_INVERT_EN
16691. BGMAC_TX_DEFERED
16692. BGMAC_TX_EXCESSIVE_COLS
16693. BGMAC_TX_FLUSH
16694. BGMAC_TX_FRAGMENT_PKTS
16695. BGMAC_TX_GOOD_OCTETS
16696. BGMAC_TX_GOOD_OCTETS_HIGH
16697. BGMAC_TX_GOOD_PKTS
16698. BGMAC_TX_JABBER_PKTS
16699. BGMAC_TX_LATE_COLS
16700. BGMAC_TX_LEN_1024_TO_1522
16701. BGMAC_TX_LEN_128_TO_255
16702. BGMAC_TX_LEN_1523_TO_2047
16703. BGMAC_TX_LEN_2048_TO_4095
16704. BGMAC_TX_LEN_256_TO_511
16705. BGMAC_TX_LEN_4096_TO_8191
16706. BGMAC_TX_LEN_512_TO_1023
16707. BGMAC_TX_LEN_64
16708. BGMAC_TX_LEN_65_TO_127
16709. BGMAC_TX_LEN_8192_TO_MAX
16710. BGMAC_TX_MULTICAST_PKTS
16711. BGMAC_TX_MULTIPLE_COLS
16712. BGMAC_TX_OCTETS
16713. BGMAC_TX_OCTETS_HIGH
16714. BGMAC_TX_OVERSIZE_PKTS
16715. BGMAC_TX_PAUSE_PKTS
16716. BGMAC_TX_PKTS
16717. BGMAC_TX_Q0_OCTETS
16718. BGMAC_TX_Q0_OCTETS_HIGH
16719. BGMAC_TX_Q0_PKTS
16720. BGMAC_TX_Q1_OCTETS
16721. BGMAC_TX_Q1_OCTETS_HIGH
16722. BGMAC_TX_Q1_PKTS
16723. BGMAC_TX_Q2_OCTETS
16724. BGMAC_TX_Q2_OCTETS_HIGH
16725. BGMAC_TX_Q2_PKTS
16726. BGMAC_TX_Q3_OCTETS
16727. BGMAC_TX_Q3_OCTETS_HIGH
16728. BGMAC_TX_Q3_PKTS
16729. BGMAC_TX_RING_SLOTS
16730. BGMAC_TX_SINGLE_COLS
16731. BGMAC_TX_STATUS
16732. BGMAC_TX_TOTAL_COLS
16733. BGMAC_TX_UNDERRUNS
16734. BGMAC_TX_UNI_PKTS
16735. BGMAC_UNIMAC_VERSION
16736. BGMAC_WEIGHT
16737. BGMAC_WRRTHRESH
16738. BGPIOF_BIG_ENDIAN
16739. BGPIOF_BIG_ENDIAN_BYTE_ORDER
16740. BGPIOF_NO_OUTPUT
16741. BGPIOF_READ_OUTPUT_REG_SET
16742. BGPIOF_UNREADABLE_REG_DIR
16743. BGPIOF_UNREADABLE_REG_SET
16744. BGR
16745. BGR101111_FIX
16746. BGR101111_FLOAT
16747. BGR565
16748. BGR565_2X8_BE
16749. BGR565_2X8_LE
16750. BGRA_TO_BG_G_RB_A
16751. BGREN
16752. BGR_TRANSMISSION
16753. BGS_APPTAG_ERR_MASK
16754. BGS_APPTAG_ERR_SHIFT
16755. BGS_BG_PROFILE_MASK
16756. BGS_BG_PROFILE_SHIFT
16757. BGS_BIDIR_BG_PROF_MASK
16758. BGS_BIDIR_BG_PROF_SHIFT
16759. BGS_BIDIR_ERR_COND_FLAGS_MASK
16760. BGS_BIDIR_ERR_COND_SHIFT
16761. BGS_GUARD_ERR_MASK
16762. BGS_GUARD_ERR_SHIFT
16763. BGS_HI_WATER_MARK_PRESENT_MASK
16764. BGS_HI_WATER_MARK_PRESENT_SHIFT
16765. BGS_INVALID_PROF_MASK
16766. BGS_INVALID_PROF_SHIFT
16767. BGS_REFTAG_ERR_MASK
16768. BGS_REFTAG_ERR_SHIFT
16769. BGS_UNINIT_DIF_BLOCK_MASK
16770. BGS_UNINIT_DIF_BLOCK_SHIFT
16771. BGT_NAME_PATTERN
16772. BGU
16773. BGX0_BLOCK
16774. BGX1_BLOCK
16775. BGX_CMRX_CFG
16776. BGX_CMRX_RX_BP_DROP
16777. BGX_CMRX_RX_DMAC_CTL
16778. BGX_CMRX_RX_FIFO_LEN
16779. BGX_CMRX_RX_ID_MAP
16780. BGX_CMRX_RX_STAT0
16781. BGX_CMRX_RX_STAT1
16782. BGX_CMRX_RX_STAT10
16783. BGX_CMRX_RX_STAT2
16784. BGX_CMRX_RX_STAT3
16785. BGX_CMRX_RX_STAT4
16786. BGX_CMRX_RX_STAT5
16787. BGX_CMRX_RX_STAT6
16788. BGX_CMRX_RX_STAT7
16789. BGX_CMRX_RX_STAT8
16790. BGX_CMRX_RX_STAT9
16791. BGX_CMRX_TX_FIFO_LEN
16792. BGX_CMRX_TX_STAT0
16793. BGX_CMRX_TX_STAT1
16794. BGX_CMRX_TX_STAT10
16795. BGX_CMRX_TX_STAT11
16796. BGX_CMRX_TX_STAT12
16797. BGX_CMRX_TX_STAT13
16798. BGX_CMRX_TX_STAT14
16799. BGX_CMRX_TX_STAT15
16800. BGX_CMRX_TX_STAT16
16801. BGX_CMRX_TX_STAT17
16802. BGX_CMRX_TX_STAT2
16803. BGX_CMRX_TX_STAT3
16804. BGX_CMRX_TX_STAT4
16805. BGX_CMRX_TX_STAT5
16806. BGX_CMRX_TX_STAT6
16807. BGX_CMRX_TX_STAT7
16808. BGX_CMRX_TX_STAT8
16809. BGX_CMRX_TX_STAT9
16810. BGX_CMR_BIST_STATUS
16811. BGX_CMR_CHAN_MSK_AND
16812. BGX_CMR_GLOBAL_CFG
16813. BGX_CMR_RX_DMACX_CAM
16814. BGX_CMR_RX_LMACS
16815. BGX_CMR_RX_STEERING
16816. BGX_CMR_TX_LMACS
16817. BGX_GMP_GMI_PRTX_CFG
16818. BGX_GMP_GMI_RXX_FRM_CTL
16819. BGX_GMP_GMI_RXX_JABBER
16820. BGX_GMP_GMI_TXX_APPEND
16821. BGX_GMP_GMI_TXX_BURST
16822. BGX_GMP_GMI_TXX_INT
16823. BGX_GMP_GMI_TXX_INT_ENA_W1C
16824. BGX_GMP_GMI_TXX_INT_ENA_W1S
16825. BGX_GMP_GMI_TXX_INT_W1S
16826. BGX_GMP_GMI_TXX_MIN_PKT
16827. BGX_GMP_GMI_TXX_SGMII_CTL
16828. BGX_GMP_GMI_TXX_SLOT
16829. BGX_GMP_GMI_TXX_THRESH
16830. BGX_GMP_PCS_ANX_ADV
16831. BGX_GMP_PCS_ANX_AN_RESULTS
16832. BGX_GMP_PCS_LINKX_TIMER
16833. BGX_GMP_PCS_MISCX_CTL
16834. BGX_GMP_PCS_MRX_CTL
16835. BGX_GMP_PCS_MRX_STATUS
16836. BGX_GMP_PCS_SGM_AN_ADV
16837. BGX_ID_MASK
16838. BGX_LMAC_VEC_OFFSET
16839. BGX_MCAST_MODE
16840. BGX_MODE_10G_KR
16841. BGX_MODE_40G_KR
16842. BGX_MODE_DXAUI
16843. BGX_MODE_INVALID
16844. BGX_MODE_QSGMII
16845. BGX_MODE_RGMII
16846. BGX_MODE_RXAUI
16847. BGX_MODE_SGMII
16848. BGX_MODE_XAUI
16849. BGX_MODE_XFI
16850. BGX_MODE_XLAUI
16851. BGX_MSIX_PBA_0
16852. BGX_MSIX_VECTORS
16853. BGX_MSIX_VEC_0_29_ADDR
16854. BGX_MSIX_VEC_0_29_CTL
16855. BGX_MSIX_VEC_SHIFT
16856. BGX_PKT_RX_PTP_EN
16857. BGX_RX_STATS_COUNT
16858. BGX_SMUX_CBFC_CTL
16859. BGX_SMUX_CTL
16860. BGX_SMUX_RX_CTL
16861. BGX_SMUX_RX_FRM_CTL
16862. BGX_SMUX_RX_INT
16863. BGX_SMUX_RX_JABBER
16864. BGX_SMUX_TX_APPEND
16865. BGX_SMUX_TX_CTL
16866. BGX_SMUX_TX_INT
16867. BGX_SMUX_TX_MIN_PKT
16868. BGX_SMUX_TX_PAUSE_PKT_INTERVAL
16869. BGX_SMUX_TX_PAUSE_PKT_TIME
16870. BGX_SMUX_TX_PAUSE_ZERO
16871. BGX_SMUX_TX_THRESH
16872. BGX_SPUX_AN_ADV
16873. BGX_SPUX_AN_CONTROL
16874. BGX_SPUX_BR_PMD_CRTL
16875. BGX_SPUX_BR_PMD_LD_CUP
16876. BGX_SPUX_BR_PMD_LD_REP
16877. BGX_SPUX_BR_PMD_LP_CUP
16878. BGX_SPUX_BR_STATUS1
16879. BGX_SPUX_BX_STATUS
16880. BGX_SPUX_CONTROL1
16881. BGX_SPUX_FEC_CONTROL
16882. BGX_SPUX_INT
16883. BGX_SPUX_INT_ENA_W1C
16884. BGX_SPUX_INT_ENA_W1S
16885. BGX_SPUX_INT_W1S
16886. BGX_SPUX_MISC_CONTROL
16887. BGX_SPUX_STATUS1
16888. BGX_SPUX_STATUS2
16889. BGX_SPU_DBG_CONTROL
16890. BGX_TX_STATS_COUNT
16891. BGX_XCAST_BCAST_ACCEPT
16892. BGX_XCAST_MCAST_ACCEPT
16893. BGX_XCAST_MCAST_FILTER
16894. BG_B
16895. BG_BOT
16896. BG_COLOR_REG
16897. BG_CONST
16898. BG_ENABLE
16899. BG_ERR_CHECK
16900. BG_ERR_INIT
16901. BG_ERR_SWAP
16902. BG_ERR_TGT
16903. BG_G
16904. BG_GC
16905. BG_INTERVAL_TIMER_PERIOD
16906. BG_LEFT
16907. BG_OP_IN_CRC_OUT_CRC
16908. BG_OP_IN_CRC_OUT_CSUM
16909. BG_OP_IN_CRC_OUT_NODIF
16910. BG_OP_IN_CSUM_OUT_CRC
16911. BG_OP_IN_CSUM_OUT_CSUM
16912. BG_OP_IN_CSUM_OUT_NODIF
16913. BG_OP_IN_NODIF_OUT_CRC
16914. BG_OP_IN_NODIF_OUT_CSUM
16915. BG_OP_RAW_MODE
16916. BG_PAL_A2
16917. BG_PAL_MONO
16918. BG_PAL_NICAM
16919. BG_PIXEL
16920. BG_R
16921. BG_REF_CTRL
16922. BG_RIGHT
16923. BG_SCAN_PARAMS
16924. BG_SCAN_PROBE_REQ
16925. BG_STACK
16926. BG_SUPPORTED_RATES
16927. BG_TOP
16928. BG_TREE_SCB_ADDR
16929. BGx
16930. BH
16931. BH1710
16932. BH1721
16933. BH1750
16934. BH1750_CHANGE_INT_TIME_H_BIT
16935. BH1750_CHANGE_INT_TIME_L_BIT
16936. BH1750_ONE_TIME_H_RES_MODE
16937. BH1750_POWER_DOWN
16938. BH1770_ALS_CONTROL
16939. BH1770_ALS_DATA_0
16940. BH1770_ALS_DATA_1
16941. BH1770_ALS_MEAS_RATE
16942. BH1770_ALS_PS_MEAS
16943. BH1770_ALS_PS_STATUS
16944. BH1770_ALS_TH_LOW_0
16945. BH1770_ALS_TH_LOW_1
16946. BH1770_ALS_TH_UP_0
16947. BH1770_ALS_TH_UP_1
16948. BH1770_ALS_TRIG_MEAS
16949. BH1770_CALIB_SCALER
16950. BH1770_COEF_SCALER
16951. BH1770_DEFAULT_PERSISTENCE
16952. BH1770_DISABLE
16953. BH1770_ENABLE
16954. BH1770_FORCED
16955. BH1770_INTERRUPT
16956. BH1770_INT_ALS_DATA
16957. BH1770_INT_ALS_ENA
16958. BH1770_INT_ALS_INT
16959. BH1770_INT_LED1_DATA
16960. BH1770_INT_LED1_INT
16961. BH1770_INT_LED2_DATA
16962. BH1770_INT_LED2_INT
16963. BH1770_INT_LED3_DATA
16964. BH1770_INT_LED3_INT
16965. BH1770_INT_LEDS_INT
16966. BH1770_INT_OUTPUT_MODE
16967. BH1770_INT_POLARITY
16968. BH1770_INT_PS_ENA
16969. BH1770_I_LED
16970. BH1770_I_LED3
16971. BH1770_LED1
16972. BH1770_LED_100mA
16973. BH1770_LED_10mA
16974. BH1770_LED_150mA
16975. BH1770_LED_200mA
16976. BH1770_LED_20mA
16977. BH1770_LED_50mA
16978. BH1770_LED_5mA
16979. BH1770_LUX_CF_SCALE
16980. BH1770_LUX_CORR_SCALE
16981. BH1770_LUX_DEFAULT_RATE
16982. BH1770_LUX_DEF_THRES
16983. BH1770_LUX_GA_SCALE
16984. BH1770_LUX_NEUTRAL_CALIB_VALUE
16985. BH1770_LUX_RANGE
16986. BH1770_MANUFACT_ID
16987. BH1770_MANUFACT_OSRAM
16988. BH1770_MANUFACT_ROHM
16989. BH1770_NEUTRAL_CF
16990. BH1770_NEUTRAL_GA
16991. BH1770_PART
16992. BH1770_PART_ID
16993. BH1770_PART_MASK
16994. BH1770_PROX_CHANNELS
16995. BH1770_PROX_DEFAULT_RATE
16996. BH1770_PROX_DEF_ABS_THRES
16997. BH1770_PROX_DEF_RATE_THRESH
16998. BH1770_PROX_DEF_THRES
16999. BH1770_PROX_MAX_PERSISTENCE
17000. BH1770_PROX_RANGE
17001. BH1770_PS_CONTROL
17002. BH1770_PS_DATA_LED1
17003. BH1770_PS_DATA_LED2
17004. BH1770_PS_DATA_LED3
17005. BH1770_PS_MEAS_RATE
17006. BH1770_PS_TH_LED1
17007. BH1770_PS_TH_LED2
17008. BH1770_PS_TH_LED3
17009. BH1770_PS_TRIG_MEAS
17010. BH1770_RESET_TIME
17011. BH1770_REV_0
17012. BH1770_REV_1
17013. BH1770_REV_MASK
17014. BH1770_REV_SHIFT
17015. BH1770_STANDALONE
17016. BH1770_STANDBY
17017. BH1770_STARTUP_DELAY
17018. BH1770_SWRESET
17019. BH1770_TIMEOUT
17020. BH1780_CMD_BIT
17021. BH1780_INTERVAL
17022. BH1780_POFF
17023. BH1780_PON
17024. BH1780_PON_DELAY
17025. BH1780_POWMASK
17026. BH1780_REG_CONTROL
17027. BH1780_REG_DHIGH
17028. BH1780_REG_DLOW
17029. BH1780_REG_MANFID
17030. BH1780_REG_PARTID
17031. BH1780_REVMASK
17032. BHASH0
17033. BHASH1
17034. BHASH2
17035. BHASH3
17036. BHDR
17037. BHRBE
17038. BHRB_EA
17039. BHRB_MAX_ENTRIES
17040. BHRB_PREDICTION
17041. BHRB_TARGET
17042. BHSSI_R2TDELAY
17043. BHSSI_T2RDELAY
17044. BHS_CNT_SHIFT
17045. BHS_EN
17046. BHS_EN_REST_ACK
17047. BHS_SEG_SHIFT
17048. BHTSIG1_BANDWIDTH
17049. BHTSIG1_HTLENGTH
17050. BHTSIG1_MCS
17051. BHTSIG2_ADVCODING
17052. BHTSIG2_AGGREATON
17053. BHTSIG2_CRC8
17054. BHTSIG2_GI
17055. BHTSIG2_NUMOFHTLTF
17056. BHTSIG2_SMOOTHING
17057. BHTSIG2_SOUNDING
17058. BHTSIG2_STBC
17059. BHT_DETECT
17060. BH_Async_Read
17061. BH_Async_Write
17062. BH_BITMAP_UPTODATE
17063. BH_Boundary
17064. BH_Defer_Completion
17065. BH_Delay
17066. BH_Dirty
17067. BH_ENTRY
17068. BH_Escaped
17069. BH_FLAGS
17070. BH_Freed
17071. BH_FullMapped
17072. BH_JBD
17073. BH_JBDDirty
17074. BH_JBDPrivateStart
17075. BH_JDirty
17076. BH_JDirty_wait
17077. BH_JNew
17078. BH_JPrepared
17079. BH_JRestore_dirty
17080. BH_JTest
17081. BH_JWrite
17082. BH_JournalHead
17083. BH_LRU_SIZE
17084. BH_Lock
17085. BH_Mapped
17086. BH_Meta
17087. BH_NILFS_Allocated
17088. BH_NILFS_Checked
17089. BH_NILFS_Node
17090. BH_NILFS_Redirected
17091. BH_NILFS_Volatile
17092. BH_NeedsValidate
17093. BH_New
17094. BH_Pinned
17095. BH_Prio
17096. BH_PrivateStart
17097. BH_Quiet
17098. BH_RECEIVE
17099. BH_Req
17100. BH_RevokeValid
17101. BH_Revoked
17102. BH_STATUS
17103. BH_Shadow
17104. BH_State
17105. BH_TRACE
17106. BH_TRANSMIT
17107. BH_Unwritten
17108. BH_Uptodate
17109. BH_Uptodate_Lock
17110. BH_Verified
17111. BH_Write_EIO
17112. BH_Zipped
17113. BI
17114. BI16
17115. BI32
17116. BIAS
17117. BIASEXTR_100
17118. BIASEXTR_105_94
17119. BIASEXTR_111_88
17120. BIASEXTR_118_8
17121. BIASEXTR_127_7
17122. BIASEXTR_87_1
17123. BIASEXTR_91_5
17124. BIASEXTR_95_9
17125. BIASEXTR_SEL
17126. BIASMOD_EN
17127. BIAS_BLOCK_ON
17128. BIAS_CTRL
17129. BIAS_EN
17130. BIAS_GEN_PDNB
17131. BIAS_MOD_LEVEL_MASK
17132. BIAS_MOD_LEVEL_SHIFT
17133. BIAS_PAD_PD
17134. BIAS_VOLTAGE_GRP_CONFIG
17135. BIAS_VOLTAGE_NONE
17136. BIAS_VOLTAGE_PIO_POW_MODE_SEL
17137. BIA_ADDRESS
17138. BIA_BASE
17139. BIB_BMC
17140. BIB_BUS_NAME
17141. BIB_CMC
17142. BIB_CRC
17143. BIB_CRC_LENGTH
17144. BIB_CYC_CLK_ACC
17145. BIB_GENERATION
17146. BIB_INFO_LENGTH
17147. BIB_IRMC
17148. BIB_ISC
17149. BIB_LINK_SPEED
17150. BIB_MAX_RECEIVE
17151. BIB_MAX_ROM
17152. BIB_PMC
17153. BICTCP_B
17154. BICTCP_BETA_SCALE
17155. BICTCP_HZ
17156. BIC_APIC
17157. BIC_Any_c0
17158. BIC_Avg_MHz
17159. BIC_Busy
17160. BIC_Bzy_MHz
17161. BIC_CPU
17162. BIC_CPUGFX
17163. BIC_CPU_LPI
17164. BIC_CPU_c1
17165. BIC_CPU_c3
17166. BIC_CPU_c6
17167. BIC_CPU_c7
17168. BIC_CorWatt
17169. BIC_Cor_J
17170. BIC_Core
17171. BIC_CoreCnt
17172. BIC_CoreTmp
17173. BIC_DISABLED_BY_DEFAULT
17174. BIC_Die
17175. BIC_GFXMHz
17176. BIC_GFXWatt
17177. BIC_GFX_J
17178. BIC_GFX_c0
17179. BIC_GFX_rc6
17180. BIC_IRQ
17181. BIC_Mod_c6
17182. BIC_NOT_PRESENT
17183. BIC_Node
17184. BIC_PKG__
17185. BIC_PRESENT
17186. BIC_Package
17187. BIC_PkgCnt
17188. BIC_PkgTmp
17189. BIC_PkgWatt
17190. BIC_Pkg_J
17191. BIC_Pkgpc10
17192. BIC_Pkgpc2
17193. BIC_Pkgpc3
17194. BIC_Pkgpc6
17195. BIC_Pkgpc7
17196. BIC_Pkgpc8
17197. BIC_Pkgpc9
17198. BIC_RAMWatt
17199. BIC_RAM_J
17200. BIC_RAM__
17201. BIC_SMI
17202. BIC_SYS_LPI
17203. BIC_TOD
17204. BIC_TSC_MHz
17205. BIC_ThreadC
17206. BIC_Totl_c0
17207. BIC_USEC
17208. BIC_X2APIC
17209. BIC_sysfs
17210. BIDIR
17211. BIDIRECTIONAL
17212. BIDIR_PU
17213. BIDIR_TRAFFIC
17214. BIDI_CHAP
17215. BIDR
17216. BID_SIL3124
17217. BID_SIL3131
17218. BID_SIL3132
17219. BIFC_A2S_CNTL_CL0__BLKLVL_MAP_MASK
17220. BIFC_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT
17221. BIFC_A2S_CNTL_CL0__DATERR_MAP_MASK
17222. BIFC_A2S_CNTL_CL0__DATERR_MAP__SHIFT
17223. BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK
17224. BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT
17225. BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK
17226. BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT
17227. BIFC_A2S_CNTL_CL0__NSNOOP_MAP_MASK
17228. BIFC_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT
17229. BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK
17230. BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT
17231. BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK
17232. BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT
17233. BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK
17234. BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT
17235. BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK
17236. BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT
17237. BIFC_A2S_CNTL_CL0__RESP_RD_MAP_MASK
17238. BIFC_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT
17239. BIFC_A2S_CNTL_CL0__RESP_WR_MAP_MASK
17240. BIFC_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT
17241. BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP_MASK
17242. BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP__SHIFT
17243. BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE_MASK
17244. BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE__SHIFT
17245. BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK
17246. BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT
17247. BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK
17248. BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT
17249. BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK
17250. BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT
17251. BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC0_RD_MASK
17252. BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC0_RD__SHIFT
17253. BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC5_RD_MASK
17254. BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC5_RD__SHIFT
17255. BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC6_RD_MASK
17256. BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC6_RD__SHIFT
17257. BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC7_RD_MASK
17258. BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC7_RD__SHIFT
17259. BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK
17260. BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT
17261. BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK
17262. BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT
17263. BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK
17264. BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT
17265. BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK
17266. BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT
17267. BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK
17268. BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT
17269. BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK
17270. BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT
17271. BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK
17272. BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT
17273. BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK
17274. BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT
17275. BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK
17276. BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT
17277. BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK
17278. BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT
17279. BIFC_A2S_MISC_CNTL__WRR_ARB_MODE_MASK
17280. BIFC_A2S_MISC_CNTL__WRR_ARB_MODE__SHIFT
17281. BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK
17282. BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT
17283. BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK
17284. BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT
17285. BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK
17286. BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT
17287. BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK
17288. BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT
17289. BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK
17290. BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT
17291. BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK
17292. BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT
17293. BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK
17294. BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT
17295. BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK
17296. BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT
17297. BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK
17298. BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT
17299. BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK
17300. BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT
17301. BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK
17302. BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT
17303. BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS_MASK
17304. BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS__SHIFT
17305. BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS_MASK
17306. BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS__SHIFT
17307. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK
17308. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__MASK
17309. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT
17310. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK
17311. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__MASK
17312. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT
17313. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK
17314. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__MASK
17315. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT
17316. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK
17317. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__MASK
17318. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT
17319. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4_MASK
17320. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__MASK
17321. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT
17322. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5_MASK
17323. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__MASK
17324. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT
17325. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6_MASK
17326. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__MASK
17327. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT
17328. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7_MASK
17329. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__MASK
17330. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT
17331. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F0_MASK
17332. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F0__SHIFT
17333. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F1_MASK
17334. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F1__SHIFT
17335. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F2_MASK
17336. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F2__SHIFT
17337. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F3_MASK
17338. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F3__SHIFT
17339. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F4_MASK
17340. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F4__SHIFT
17341. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F5_MASK
17342. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F5__SHIFT
17343. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F6_MASK
17344. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F6__SHIFT
17345. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F7_MASK
17346. BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F7__SHIFT
17347. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0_MASK
17348. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__MASK
17349. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT
17350. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1_MASK
17351. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__MASK
17352. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT
17353. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2_MASK
17354. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__MASK
17355. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT
17356. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3_MASK
17357. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__MASK
17358. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT
17359. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4_MASK
17360. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__MASK
17361. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT
17362. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5_MASK
17363. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__MASK
17364. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT
17365. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6_MASK
17366. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__MASK
17367. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT
17368. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7_MASK
17369. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__MASK
17370. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT
17371. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F0_MASK
17372. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F0__SHIFT
17373. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F1_MASK
17374. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F1__SHIFT
17375. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F2_MASK
17376. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F2__SHIFT
17377. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F3_MASK
17378. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F3__SHIFT
17379. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F4_MASK
17380. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F4__SHIFT
17381. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F5_MASK
17382. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F5__SHIFT
17383. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F6_MASK
17384. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F6__SHIFT
17385. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F7_MASK
17386. BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F7__SHIFT
17387. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK
17388. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT
17389. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK
17390. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT
17391. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK
17392. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT
17393. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK
17394. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT
17395. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK
17396. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT
17397. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK
17398. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT
17399. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK
17400. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT
17401. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK
17402. BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT
17403. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK
17404. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT
17405. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK
17406. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT
17407. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK
17408. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT
17409. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK
17410. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT
17411. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK
17412. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__MASK
17413. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT
17414. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK
17415. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__MASK
17416. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT
17417. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK
17418. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__MASK
17419. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT
17420. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK
17421. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__MASK
17422. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT
17423. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK
17424. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__MASK
17425. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT
17426. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK
17427. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__MASK
17428. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT
17429. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK
17430. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__MASK
17431. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT
17432. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK
17433. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__MASK
17434. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT
17435. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK
17436. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__MASK
17437. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT
17438. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK
17439. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__MASK
17440. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT
17441. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK
17442. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__MASK
17443. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT
17444. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK
17445. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__MASK
17446. BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT
17447. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK
17448. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT
17449. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK
17450. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT
17451. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK
17452. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT
17453. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK
17454. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT
17455. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK
17456. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__MASK
17457. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT
17458. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK
17459. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__MASK
17460. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT
17461. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK
17462. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__MASK
17463. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT
17464. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK
17465. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__MASK
17466. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT
17467. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK
17468. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__MASK
17469. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT
17470. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK
17471. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__MASK
17472. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT
17473. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK
17474. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__MASK
17475. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT
17476. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK
17477. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__MASK
17478. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT
17479. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK
17480. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__MASK
17481. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT
17482. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK
17483. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__MASK
17484. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT
17485. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK
17486. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__MASK
17487. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT
17488. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK
17489. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__MASK
17490. BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT
17491. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK
17492. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT
17493. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK
17494. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT
17495. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK
17496. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT
17497. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK
17498. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT
17499. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK
17500. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__MASK
17501. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT
17502. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK
17503. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__MASK
17504. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT
17505. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK
17506. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__MASK
17507. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT
17508. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK
17509. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__MASK
17510. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT
17511. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK
17512. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__MASK
17513. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT
17514. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK
17515. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__MASK
17516. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT
17517. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK
17518. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__MASK
17519. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT
17520. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK
17521. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__MASK
17522. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT
17523. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK
17524. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__MASK
17525. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT
17526. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK
17527. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__MASK
17528. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT
17529. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK
17530. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__MASK
17531. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT
17532. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK
17533. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__MASK
17534. BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT
17535. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK
17536. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT
17537. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK
17538. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT
17539. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK
17540. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT
17541. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK
17542. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT
17543. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK
17544. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__MASK
17545. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT
17546. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK
17547. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__MASK
17548. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT
17549. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK
17550. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__MASK
17551. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT
17552. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK
17553. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__MASK
17554. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT
17555. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK
17556. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__MASK
17557. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT
17558. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK
17559. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__MASK
17560. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT
17561. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK
17562. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__MASK
17563. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT
17564. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK
17565. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__MASK
17566. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT
17567. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK
17568. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__MASK
17569. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT
17570. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK
17571. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__MASK
17572. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT
17573. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK
17574. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__MASK
17575. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT
17576. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK
17577. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__MASK
17578. BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT
17579. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0_MASK
17580. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0__SHIFT
17581. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1_MASK
17582. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1__SHIFT
17583. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0_MASK
17584. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0__SHIFT
17585. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1_MASK
17586. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1__SHIFT
17587. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0_MASK
17588. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0__SHIFT
17589. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1_MASK
17590. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1__SHIFT
17591. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0_MASK
17592. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0__SHIFT
17593. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1_MASK
17594. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1__SHIFT
17595. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0_MASK
17596. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0__SHIFT
17597. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1_MASK
17598. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1__SHIFT
17599. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0_MASK
17600. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0__SHIFT
17601. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1_MASK
17602. BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1__SHIFT
17603. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2_MASK
17604. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2__SHIFT
17605. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3_MASK
17606. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3__SHIFT
17607. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2_MASK
17608. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2__SHIFT
17609. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3_MASK
17610. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3__SHIFT
17611. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2_MASK
17612. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2__SHIFT
17613. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3_MASK
17614. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3__SHIFT
17615. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2_MASK
17616. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2__SHIFT
17617. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3_MASK
17618. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3__SHIFT
17619. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2_MASK
17620. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2__SHIFT
17621. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3_MASK
17622. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3__SHIFT
17623. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2_MASK
17624. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2__SHIFT
17625. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3_MASK
17626. BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3__SHIFT
17627. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4_MASK
17628. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4__SHIFT
17629. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5_MASK
17630. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5__SHIFT
17631. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4_MASK
17632. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4__SHIFT
17633. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5_MASK
17634. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5__SHIFT
17635. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4_MASK
17636. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4__SHIFT
17637. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5_MASK
17638. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5__SHIFT
17639. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4_MASK
17640. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4__SHIFT
17641. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5_MASK
17642. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5__SHIFT
17643. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4_MASK
17644. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4__SHIFT
17645. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5_MASK
17646. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5__SHIFT
17647. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4_MASK
17648. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4__SHIFT
17649. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5_MASK
17650. BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5__SHIFT
17651. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6_MASK
17652. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6__SHIFT
17653. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7_MASK
17654. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7__SHIFT
17655. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6_MASK
17656. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6__SHIFT
17657. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7_MASK
17658. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7__SHIFT
17659. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6_MASK
17660. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6__SHIFT
17661. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7_MASK
17662. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7__SHIFT
17663. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6_MASK
17664. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6__SHIFT
17665. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7_MASK
17666. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7__SHIFT
17667. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6_MASK
17668. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6__SHIFT
17669. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7_MASK
17670. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7__SHIFT
17671. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6_MASK
17672. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6__SHIFT
17673. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7_MASK
17674. BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7__SHIFT
17675. BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK
17676. BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__MASK
17677. BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT
17678. BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK
17679. BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__MASK
17680. BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT
17681. BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK
17682. BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__MASK
17683. BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT
17684. BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK
17685. BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__MASK
17686. BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT
17687. BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK
17688. BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__MASK
17689. BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT
17690. BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK
17691. BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT
17692. BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK
17693. BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__MASK
17694. BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT
17695. BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK
17696. BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__MASK
17697. BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT
17698. BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK
17699. BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__MASK
17700. BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT
17701. BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK
17702. BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__MASK
17703. BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT
17704. BIFC_HSTARB_CNTL__SLVARB_MODE_MASK
17705. BIFC_HSTARB_CNTL__SLVARB_MODE__MASK
17706. BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT
17707. BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK
17708. BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__MASK
17709. BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT
17710. BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK
17711. BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT
17712. BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK
17713. BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__MASK
17714. BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT
17715. BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK
17716. BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__MASK
17717. BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT
17718. BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK
17719. BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__MASK
17720. BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT
17721. BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK
17722. BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT
17723. BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK
17724. BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT
17725. BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK
17726. BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT
17727. BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK
17728. BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT
17729. BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK
17730. BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT
17731. BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK
17732. BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__MASK
17733. BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT
17734. BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_MASK
17735. BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__MASK
17736. BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT
17737. BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK
17738. BIFC_MISC_CTRL0__PCIESWUS_SELECTION__MASK
17739. BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT
17740. BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK
17741. BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__MASK
17742. BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT
17743. BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK
17744. BIFC_MISC_CTRL0__PME_TURNOFF_MODE__MASK
17745. BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT
17746. BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK
17747. BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__MASK
17748. BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT
17749. BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK
17750. BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT
17751. BIFC_MISC_CTRL0__VC5_DMA_IOCFG_DIS_MASK
17752. BIFC_MISC_CTRL0__VC5_DMA_IOCFG_DIS__SHIFT
17753. BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK
17754. BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__MASK
17755. BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT
17756. BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK
17757. BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__MASK
17758. BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT
17759. BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK
17760. BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__MASK
17761. BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT
17762. BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK
17763. BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK
17764. BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__MASK
17765. BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT
17766. BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__MASK
17767. BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT
17768. BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK
17769. BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__MASK
17770. BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT
17771. BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK
17772. BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__MASK
17773. BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT
17774. BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK
17775. BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__MASK
17776. BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT
17777. BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK
17778. BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__MASK
17779. BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT
17780. BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK
17781. BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT
17782. BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK
17783. BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__MASK
17784. BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT
17785. BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK
17786. BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__MASK
17787. BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT
17788. BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK
17789. BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT
17790. BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK
17791. BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT
17792. BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK
17793. BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__MASK
17794. BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT
17795. BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK
17796. BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__MASK
17797. BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT
17798. BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK
17799. BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__MASK
17800. BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT
17801. BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK
17802. BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT
17803. BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK
17804. BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT
17805. BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK
17806. BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT
17807. BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK
17808. BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT
17809. BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK
17810. BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__MASK
17811. BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT
17812. BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK
17813. BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT
17814. BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK
17815. BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__MASK
17816. BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT
17817. BIFC_MISC_CTRL1__GSI_SMN_POSTWR_MULTI_EN_MASK
17818. BIFC_MISC_CTRL1__GSI_SMN_POSTWR_MULTI_EN__SHIFT
17819. BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK
17820. BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__MASK
17821. BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT
17822. BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK
17823. BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__MASK
17824. BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT
17825. BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK
17826. BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__MASK
17827. BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT
17828. BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK
17829. BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__MASK
17830. BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT
17831. BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK
17832. BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__MASK
17833. BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT
17834. BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK
17835. BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT
17836. BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK
17837. BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT
17838. BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2_MASK
17839. BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2__SHIFT
17840. BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3_MASK
17841. BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3__SHIFT
17842. BIFC_PASID_STS__PASID_STS_MASK
17843. BIFC_PASID_STS__PASID_STS__SHIFT
17844. BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK
17845. BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__MASK
17846. BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT
17847. BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK
17848. BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__MASK
17849. BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT
17850. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK
17851. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__MASK
17852. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT
17853. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK
17854. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__MASK
17855. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT
17856. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK
17857. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__MASK
17858. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT
17859. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK
17860. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__MASK
17861. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT
17862. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK
17863. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__MASK
17864. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT
17865. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK
17866. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__MASK
17867. BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT
17868. BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK
17869. BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__MASK
17870. BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT
17871. BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK
17872. BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__MASK
17873. BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT
17874. BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK
17875. BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__MASK
17876. BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT
17877. BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK
17878. BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__MASK
17879. BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT
17880. BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK
17881. BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__MASK
17882. BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT
17883. BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK
17884. BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__MASK
17885. BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT
17886. BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE_MASK
17887. BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__MASK
17888. BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT
17889. BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE_MASK
17890. BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__MASK
17891. BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT
17892. BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE_MASK
17893. BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__MASK
17894. BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT
17895. BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE_MASK
17896. BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__MASK
17897. BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT
17898. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK
17899. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT
17900. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK
17901. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT
17902. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK
17903. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT
17904. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK
17905. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT
17906. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK
17907. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT
17908. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK
17909. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT
17910. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK
17911. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT
17912. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK
17913. BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT
17914. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK
17915. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT
17916. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK
17917. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT
17918. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2_MASK
17919. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT
17920. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3_MASK
17921. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT
17922. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4_MASK
17923. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT
17924. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5_MASK
17925. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT
17926. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6_MASK
17927. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT
17928. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7_MASK
17929. BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT
17930. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK
17931. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__MASK
17932. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT
17933. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK
17934. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__MASK
17935. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT
17936. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK
17937. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__MASK
17938. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT
17939. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK
17940. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__MASK
17941. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT
17942. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK
17943. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__MASK
17944. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT
17945. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK
17946. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__MASK
17947. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT
17948. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK
17949. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__MASK
17950. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT
17951. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK
17952. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__MASK
17953. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT
17954. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0_MASK
17955. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT
17956. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1_MASK
17957. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT
17958. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F2_MASK
17959. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F2__SHIFT
17960. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F3_MASK
17961. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F3__SHIFT
17962. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F4_MASK
17963. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F4__SHIFT
17964. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F5_MASK
17965. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F5__SHIFT
17966. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F6_MASK
17967. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F6__SHIFT
17968. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F7_MASK
17969. BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F7__SHIFT
17970. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0_MASK
17971. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__MASK
17972. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT
17973. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1_MASK
17974. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__MASK
17975. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT
17976. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2_MASK
17977. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__MASK
17978. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT
17979. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3_MASK
17980. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__MASK
17981. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT
17982. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4_MASK
17983. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__MASK
17984. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT
17985. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5_MASK
17986. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__MASK
17987. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT
17988. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6_MASK
17989. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__MASK
17990. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT
17991. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7_MASK
17992. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__MASK
17993. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT
17994. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F0_MASK
17995. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT
17996. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F1_MASK
17997. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT
17998. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F2_MASK
17999. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F2__SHIFT
18000. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F3_MASK
18001. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F3__SHIFT
18002. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F4_MASK
18003. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F4__SHIFT
18004. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F5_MASK
18005. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F5__SHIFT
18006. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F6_MASK
18007. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F6__SHIFT
18008. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F7_MASK
18009. BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F7__SHIFT
18010. BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK
18011. BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__MASK
18012. BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT
18013. BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK
18014. BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__MASK
18015. BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT
18016. BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK
18017. BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__MASK
18018. BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT
18019. BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK
18020. BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__MASK
18021. BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT
18022. BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK
18023. BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT
18024. BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK
18025. BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT
18026. BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK
18027. BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT
18028. BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK
18029. BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT
18030. BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK
18031. BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT
18032. BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK
18033. BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT
18034. BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK
18035. BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__MASK
18036. BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT
18037. BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK
18038. BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__MASK
18039. BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT
18040. BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK
18041. BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__MASK
18042. BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT
18043. BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN_MASK
18044. BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT
18045. BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK
18046. BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT
18047. BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK
18048. BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT
18049. BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK
18050. BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT
18051. BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK
18052. BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT
18053. BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK
18054. BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT
18055. BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK
18056. BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT
18057. BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK
18058. BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT
18059. BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK
18060. BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT
18061. BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK
18062. BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT
18063. BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK
18064. BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT
18065. BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK
18066. BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT
18067. BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN_MASK
18068. BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN__SHIFT
18069. BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK
18070. BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT
18071. BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK
18072. BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT
18073. BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN_MASK
18074. BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN__SHIFT
18075. BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK
18076. BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT
18077. BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK
18078. BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT
18079. BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK
18080. BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT
18081. BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK
18082. BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT
18083. BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK
18084. BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT
18085. BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK
18086. BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT
18087. BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK
18088. BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT
18089. BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK
18090. BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT
18091. BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK
18092. BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT
18093. BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK
18094. BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT
18095. BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK
18096. BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT
18097. BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK
18098. BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT
18099. BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK
18100. BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT
18101. BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK
18102. BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT
18103. BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK
18104. BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT
18105. BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN_MASK
18106. BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN__SHIFT
18107. BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK
18108. BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT
18109. BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK
18110. BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT
18111. BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN_MASK
18112. BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN__SHIFT
18113. BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK
18114. BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT
18115. BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK
18116. BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT
18117. BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK
18118. BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT
18119. BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK
18120. BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT
18121. BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK
18122. BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT
18123. BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK
18124. BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT
18125. BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK
18126. BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT
18127. BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK
18128. BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT
18129. BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK
18130. BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT
18131. BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK
18132. BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT
18133. BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK
18134. BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT
18135. BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK
18136. BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT
18137. BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK
18138. BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT
18139. BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK
18140. BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT
18141. BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK
18142. BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT
18143. BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN_MASK
18144. BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN__SHIFT
18145. BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK
18146. BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT
18147. BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK
18148. BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT
18149. BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN_MASK
18150. BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN__SHIFT
18151. BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK
18152. BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT
18153. BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK
18154. BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT
18155. BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK
18156. BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT
18157. BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK
18158. BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT
18159. BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK
18160. BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT
18161. BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK
18162. BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT
18163. BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK
18164. BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT
18165. BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK
18166. BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT
18167. BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK
18168. BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT
18169. BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK
18170. BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT
18171. BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK
18172. BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT
18173. BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK
18174. BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT
18175. BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK
18176. BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT
18177. BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK
18178. BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT
18179. BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK
18180. BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT
18181. BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN_MASK
18182. BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN__SHIFT
18183. BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN_MASK
18184. BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN__SHIFT
18185. BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN_MASK
18186. BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN__SHIFT
18187. BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN_MASK
18188. BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN__SHIFT
18189. BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN_MASK
18190. BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN__SHIFT
18191. BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN_MASK
18192. BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT
18193. BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK
18194. BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT
18195. BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK
18196. BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT
18197. BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK
18198. BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT
18199. BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK
18200. BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT
18201. BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN_MASK
18202. BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT
18203. BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN_MASK
18204. BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN__SHIFT
18205. BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT_MASK
18206. BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT
18207. BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT_MASK
18208. BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT
18209. BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT_MASK
18210. BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT__SHIFT
18211. BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT_MASK
18212. BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT__SHIFT
18213. BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV_MASK
18214. BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV__SHIFT
18215. BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET_MASK
18216. BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET__SHIFT
18217. BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET_MASK
18218. BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET__SHIFT
18219. BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_GEN_EN_MASK
18220. BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_GEN_EN__SHIFT
18221. BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_PROP_EN_MASK
18222. BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_PROP_EN__SHIFT
18223. BIFL_RAS_LEAF4_CTRL__ERR_EVENT_DET_EN_MASK
18224. BIFL_RAS_LEAF4_CTRL__ERR_EVENT_DET_EN__SHIFT
18225. BIFL_RAS_LEAF4_CTRL__ERR_EVENT_GEN_EN_MASK
18226. BIFL_RAS_LEAF4_CTRL__ERR_EVENT_GEN_EN__SHIFT
18227. BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PROP_EN_MASK
18228. BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PROP_EN__SHIFT
18229. BIFL_RAS_LEAF4_CTRL__ERR_EVENT_RAS_INTR_EN_MASK
18230. BIFL_RAS_LEAF4_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT
18231. BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN_MASK
18232. BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT
18233. BIFL_RAS_LEAF4_CTRL__PARITY_STALL_EN_MASK
18234. BIFL_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT
18235. BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_EN_MASK
18236. BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT
18237. BIFL_RAS_LEAF4_CTRL__POISON_STALL_EN_MASK
18238. BIFL_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT
18239. BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_EN_MASK
18240. BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT
18241. BIFL_RAS_LEAF4_CTRL__RCVERREVENT_STALL_EN_MASK
18242. BIFL_RAS_LEAF4_CTRL__RCVERREVENT_STALL_EN__SHIFT
18243. BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_GENN_STAT_MASK
18244. BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT
18245. BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_PROP_STAT_MASK
18246. BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT
18247. BIFL_RAS_LEAF4_STATUS__ERR_EVENT_GENN_STAT_MASK
18248. BIFL_RAS_LEAF4_STATUS__ERR_EVENT_GENN_STAT__SHIFT
18249. BIFL_RAS_LEAF4_STATUS__ERR_EVENT_PROP_STAT_MASK
18250. BIFL_RAS_LEAF4_STATUS__ERR_EVENT_PROP_STAT__SHIFT
18251. BIFL_RAS_LEAF4_STATUS__ERR_EVENT_RECV_MASK
18252. BIFL_RAS_LEAF4_STATUS__ERR_EVENT_RECV__SHIFT
18253. BIFL_RAS_LEAF4_STATUS__PARITY_ERR_DET_MASK
18254. BIFL_RAS_LEAF4_STATUS__PARITY_ERR_DET__SHIFT
18255. BIFL_RAS_LEAF4_STATUS__POISON_ERR_DET_MASK
18256. BIFL_RAS_LEAF4_STATUS__POISON_ERR_DET__SHIFT
18257. BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK
18258. BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT
18259. BIFMF_WIN_L
18260. BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
18261. BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
18262. BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
18263. BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
18264. BIFP0_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
18265. BIFP0_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
18266. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
18267. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
18268. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
18269. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
18270. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
18271. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
18272. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
18273. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
18274. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
18275. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
18276. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
18277. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
18278. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
18279. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
18280. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
18281. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
18282. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
18283. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
18284. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
18285. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
18286. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
18287. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
18288. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
18289. BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
18290. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
18291. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
18292. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
18293. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
18294. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
18295. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
18296. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
18297. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
18298. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
18299. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
18300. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
18301. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
18302. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
18303. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
18304. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
18305. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
18306. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
18307. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
18308. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
18309. BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
18310. BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK
18311. BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT
18312. BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK
18313. BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT
18314. BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
18315. BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
18316. BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
18317. BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
18318. BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
18319. BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
18320. BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
18321. BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
18322. BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
18323. BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
18324. BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
18325. BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
18326. BIFP0_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
18327. BIFP0_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
18328. BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
18329. BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
18330. BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
18331. BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
18332. BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
18333. BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
18334. BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
18335. BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
18336. BIFP0_PCIEP_HPGI__REG_HPGI_HOOK_MASK
18337. BIFP0_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
18338. BIFP0_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
18339. BIFP0_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
18340. BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK
18341. BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT
18342. BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK
18343. BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT
18344. BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK
18345. BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT
18346. BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK
18347. BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT
18348. BIFP0_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
18349. BIFP0_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
18350. BIFP0_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
18351. BIFP0_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
18352. BIFP0_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
18353. BIFP0_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
18354. BIFP0_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK
18355. BIFP0_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT
18356. BIFP0_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
18357. BIFP0_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
18358. BIFP0_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
18359. BIFP0_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
18360. BIFP0_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
18361. BIFP0_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
18362. BIFP0_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
18363. BIFP0_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
18364. BIFP0_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
18365. BIFP0_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
18366. BIFP0_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
18367. BIFP0_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
18368. BIFP0_PCIEP_RESERVED__PCIEP_RESERVED_MASK
18369. BIFP0_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
18370. BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK
18371. BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT
18372. BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK
18373. BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT
18374. BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK
18375. BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT
18376. BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK
18377. BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT
18378. BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK
18379. BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT
18380. BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK
18381. BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT
18382. BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK
18383. BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT
18384. BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK
18385. BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT
18386. BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK
18387. BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT
18388. BIFP0_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
18389. BIFP0_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
18390. BIFP0_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
18391. BIFP0_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
18392. BIFP0_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
18393. BIFP0_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
18394. BIFP0_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
18395. BIFP0_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
18396. BIFP0_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
18397. BIFP0_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
18398. BIFP0_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
18399. BIFP0_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
18400. BIFP0_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
18401. BIFP0_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
18402. BIFP0_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
18403. BIFP0_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
18404. BIFP0_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
18405. BIFP0_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
18406. BIFP0_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
18407. BIFP0_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
18408. BIFP0_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
18409. BIFP0_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
18410. BIFP0_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
18411. BIFP0_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
18412. BIFP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
18413. BIFP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
18414. BIFP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
18415. BIFP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
18416. BIFP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
18417. BIFP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
18418. BIFP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
18419. BIFP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
18420. BIFP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
18421. BIFP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
18422. BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
18423. BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
18424. BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
18425. BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
18426. BIFP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
18427. BIFP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
18428. BIFP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
18429. BIFP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
18430. BIFP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
18431. BIFP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
18432. BIFP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
18433. BIFP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
18434. BIFP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
18435. BIFP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
18436. BIFP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
18437. BIFP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
18438. BIFP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
18439. BIFP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
18440. BIFP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
18441. BIFP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
18442. BIFP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
18443. BIFP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
18444. BIFP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
18445. BIFP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
18446. BIFP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
18447. BIFP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
18448. BIFP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
18449. BIFP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
18450. BIFP0_PCIE_FC_CPL__CPLD_CREDITS_MASK
18451. BIFP0_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
18452. BIFP0_PCIE_FC_CPL__CPLH_CREDITS_MASK
18453. BIFP0_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
18454. BIFP0_PCIE_FC_NP__NPD_CREDITS_MASK
18455. BIFP0_PCIE_FC_NP__NPD_CREDITS__SHIFT
18456. BIFP0_PCIE_FC_NP__NPH_CREDITS_MASK
18457. BIFP0_PCIE_FC_NP__NPH_CREDITS__SHIFT
18458. BIFP0_PCIE_FC_P__PD_CREDITS_MASK
18459. BIFP0_PCIE_FC_P__PD_CREDITS__SHIFT
18460. BIFP0_PCIE_FC_P__PH_CREDITS_MASK
18461. BIFP0_PCIE_FC_P__PH_CREDITS__SHIFT
18462. BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
18463. BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
18464. BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
18465. BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
18466. BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
18467. BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
18468. BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
18469. BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
18470. BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
18471. BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
18472. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
18473. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
18474. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
18475. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
18476. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
18477. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
18478. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
18479. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
18480. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
18481. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
18482. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
18483. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
18484. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
18485. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
18486. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
18487. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
18488. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
18489. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
18490. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
18491. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
18492. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK
18493. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT
18494. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
18495. BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
18496. BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
18497. BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
18498. BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
18499. BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
18500. BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
18501. BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
18502. BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
18503. BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
18504. BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
18505. BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
18506. BIFP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
18507. BIFP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
18508. BIFP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
18509. BIFP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
18510. BIFP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
18511. BIFP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
18512. BIFP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
18513. BIFP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
18514. BIFP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
18515. BIFP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
18516. BIFP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
18517. BIFP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
18518. BIFP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
18519. BIFP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
18520. BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
18521. BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
18522. BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
18523. BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
18524. BIFP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
18525. BIFP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
18526. BIFP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
18527. BIFP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
18528. BIFP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
18529. BIFP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
18530. BIFP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
18531. BIFP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
18532. BIFP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
18533. BIFP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
18534. BIFP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
18535. BIFP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
18536. BIFP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
18537. BIFP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
18538. BIFP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
18539. BIFP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
18540. BIFP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
18541. BIFP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
18542. BIFP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
18543. BIFP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
18544. BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
18545. BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
18546. BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
18547. BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
18548. BIFP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
18549. BIFP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
18550. BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
18551. BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
18552. BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
18553. BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
18554. BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
18555. BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
18556. BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
18557. BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
18558. BIFP0_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
18559. BIFP0_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
18560. BIFP0_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
18561. BIFP0_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
18562. BIFP0_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
18563. BIFP0_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
18564. BIFP0_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
18565. BIFP0_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
18566. BIFP0_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
18567. BIFP0_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
18568. BIFP0_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
18569. BIFP0_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
18570. BIFP0_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
18571. BIFP0_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
18572. BIFP0_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
18573. BIFP0_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
18574. BIFP0_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
18575. BIFP0_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
18576. BIFP0_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
18577. BIFP0_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
18578. BIFP0_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
18579. BIFP0_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
18580. BIFP0_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
18581. BIFP0_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
18582. BIFP0_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
18583. BIFP0_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
18584. BIFP0_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
18585. BIFP0_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
18586. BIFP0_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
18587. BIFP0_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
18588. BIFP0_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
18589. BIFP0_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
18590. BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
18591. BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
18592. BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
18593. BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
18594. BIFP0_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
18595. BIFP0_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
18596. BIFP0_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
18597. BIFP0_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
18598. BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
18599. BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
18600. BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
18601. BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
18602. BIFP0_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
18603. BIFP0_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
18604. BIFP0_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
18605. BIFP0_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
18606. BIFP0_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
18607. BIFP0_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
18608. BIFP0_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
18609. BIFP0_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
18610. BIFP0_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
18611. BIFP0_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
18612. BIFP0_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
18613. BIFP0_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
18614. BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
18615. BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
18616. BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
18617. BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
18618. BIFP0_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
18619. BIFP0_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
18620. BIFP0_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
18621. BIFP0_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
18622. BIFP0_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
18623. BIFP0_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
18624. BIFP0_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
18625. BIFP0_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
18626. BIFP0_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
18627. BIFP0_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
18628. BIFP0_PCIE_LC_CNTL4__LC_TX_SWING_MASK
18629. BIFP0_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT
18630. BIFP0_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
18631. BIFP0_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
18632. BIFP0_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
18633. BIFP0_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
18634. BIFP0_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
18635. BIFP0_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
18636. BIFP0_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
18637. BIFP0_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
18638. BIFP0_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
18639. BIFP0_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
18640. BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK
18641. BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK
18642. BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT
18643. BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT
18644. BIFP0_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
18645. BIFP0_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
18646. BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
18647. BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
18648. BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
18649. BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
18650. BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
18651. BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
18652. BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
18653. BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
18654. BIFP0_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK
18655. BIFP0_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT
18656. BIFP0_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK
18657. BIFP0_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT
18658. BIFP0_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK
18659. BIFP0_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT
18660. BIFP0_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK
18661. BIFP0_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT
18662. BIFP0_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK
18663. BIFP0_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT
18664. BIFP0_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK
18665. BIFP0_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT
18666. BIFP0_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK
18667. BIFP0_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT
18668. BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK
18669. BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT
18670. BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK
18671. BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT
18672. BIFP0_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK
18673. BIFP0_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT
18674. BIFP0_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK
18675. BIFP0_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT
18676. BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
18677. BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
18678. BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
18679. BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
18680. BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
18681. BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
18682. BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK
18683. BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT
18684. BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK
18685. BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT
18686. BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK
18687. BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT
18688. BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK
18689. BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT
18690. BIFP0_PCIE_LC_CNTL6__LC_SRIS_EN_MASK
18691. BIFP0_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT
18692. BIFP0_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK
18693. BIFP0_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT
18694. BIFP0_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK
18695. BIFP0_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT
18696. BIFP0_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK
18697. BIFP0_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT
18698. BIFP0_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK
18699. BIFP0_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT
18700. BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK
18701. BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT
18702. BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK
18703. BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT
18704. BIFP0_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK
18705. BIFP0_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT
18706. BIFP0_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK
18707. BIFP0_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT
18708. BIFP0_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK
18709. BIFP0_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT
18710. BIFP0_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK
18711. BIFP0_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT
18712. BIFP0_PCIE_LC_CNTL7__LC_FOM_TIME_MASK
18713. BIFP0_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT
18714. BIFP0_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK
18715. BIFP0_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT
18716. BIFP0_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK
18717. BIFP0_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT
18718. BIFP0_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK
18719. BIFP0_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT
18720. BIFP0_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK
18721. BIFP0_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT
18722. BIFP0_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK
18723. BIFP0_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT
18724. BIFP0_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK
18725. BIFP0_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT
18726. BIFP0_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK
18727. BIFP0_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT
18728. BIFP0_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK
18729. BIFP0_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT
18730. BIFP0_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK
18731. BIFP0_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT
18732. BIFP0_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK
18733. BIFP0_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT
18734. BIFP0_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK
18735. BIFP0_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT
18736. BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK
18737. BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT
18738. BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK
18739. BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT
18740. BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK
18741. BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT
18742. BIFP0_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK
18743. BIFP0_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT
18744. BIFP0_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
18745. BIFP0_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
18746. BIFP0_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
18747. BIFP0_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
18748. BIFP0_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
18749. BIFP0_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
18750. BIFP0_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
18751. BIFP0_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
18752. BIFP0_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
18753. BIFP0_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
18754. BIFP0_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
18755. BIFP0_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
18756. BIFP0_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
18757. BIFP0_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
18758. BIFP0_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
18759. BIFP0_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
18760. BIFP0_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
18761. BIFP0_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
18762. BIFP0_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
18763. BIFP0_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
18764. BIFP0_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
18765. BIFP0_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
18766. BIFP0_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
18767. BIFP0_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
18768. BIFP0_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
18769. BIFP0_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
18770. BIFP0_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
18771. BIFP0_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
18772. BIFP0_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
18773. BIFP0_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
18774. BIFP0_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
18775. BIFP0_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
18776. BIFP0_PCIE_LC_CNTL__LC_RESET_LINK_MASK
18777. BIFP0_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
18778. BIFP0_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
18779. BIFP0_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
18780. BIFP0_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
18781. BIFP0_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
18782. BIFP0_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
18783. BIFP0_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
18784. BIFP0_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
18785. BIFP0_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
18786. BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
18787. BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
18788. BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
18789. BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
18790. BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
18791. BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
18792. BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
18793. BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
18794. BIFP0_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
18795. BIFP0_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
18796. BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
18797. BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
18798. BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
18799. BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
18800. BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
18801. BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
18802. BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
18803. BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
18804. BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
18805. BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
18806. BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
18807. BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
18808. BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK
18809. BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT
18810. BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK
18811. BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT
18812. BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK
18813. BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT
18814. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK
18815. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT
18816. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK
18817. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT
18818. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK
18819. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT
18820. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK
18821. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT
18822. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK
18823. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT
18824. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK
18825. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT
18826. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK
18827. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT
18828. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK
18829. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT
18830. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK
18831. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT
18832. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK
18833. BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT
18834. BIFP0_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
18835. BIFP0_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
18836. BIFP0_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
18837. BIFP0_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
18838. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
18839. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
18840. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK
18841. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT
18842. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
18843. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
18844. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
18845. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
18846. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
18847. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
18848. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
18849. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
18850. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
18851. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
18852. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
18853. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
18854. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
18855. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
18856. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
18857. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
18858. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
18859. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
18860. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
18861. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
18862. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
18863. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
18864. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
18865. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
18866. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
18867. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
18868. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
18869. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
18870. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
18871. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
18872. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
18873. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
18874. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK
18875. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT
18876. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
18877. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
18878. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
18879. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
18880. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
18881. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
18882. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
18883. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
18884. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
18885. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
18886. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
18887. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
18888. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
18889. BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
18890. BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
18891. BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
18892. BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
18893. BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
18894. BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK
18895. BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT
18896. BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
18897. BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
18898. BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
18899. BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
18900. BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
18901. BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
18902. BIFP0_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK
18903. BIFP0_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT
18904. BIFP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
18905. BIFP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
18906. BIFP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
18907. BIFP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
18908. BIFP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
18909. BIFP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
18910. BIFP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
18911. BIFP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
18912. BIFP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
18913. BIFP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
18914. BIFP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
18915. BIFP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
18916. BIFP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
18917. BIFP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
18918. BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
18919. BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
18920. BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
18921. BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
18922. BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
18923. BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
18924. BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
18925. BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
18926. BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
18927. BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
18928. BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
18929. BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
18930. BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
18931. BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
18932. BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
18933. BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
18934. BIFP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
18935. BIFP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
18936. BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
18937. BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
18938. BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
18939. BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
18940. BIFP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
18941. BIFP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
18942. BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
18943. BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
18944. BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
18945. BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
18946. BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
18947. BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
18948. BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
18949. BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
18950. BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
18951. BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
18952. BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
18953. BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
18954. BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
18955. BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
18956. BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
18957. BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
18958. BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
18959. BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
18960. BIFP0_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
18961. BIFP0_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
18962. BIFP0_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
18963. BIFP0_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
18964. BIFP0_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
18965. BIFP0_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
18966. BIFP0_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
18967. BIFP0_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
18968. BIFP0_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
18969. BIFP0_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
18970. BIFP0_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
18971. BIFP0_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
18972. BIFP0_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
18973. BIFP0_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
18974. BIFP0_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
18975. BIFP0_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
18976. BIFP0_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
18977. BIFP0_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
18978. BIFP0_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
18979. BIFP0_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
18980. BIFP0_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
18981. BIFP0_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
18982. BIFP0_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
18983. BIFP0_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
18984. BIFP0_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
18985. BIFP0_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
18986. BIFP0_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
18987. BIFP0_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
18988. BIFP0_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
18989. BIFP0_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
18990. BIFP0_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
18991. BIFP0_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
18992. BIFP0_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
18993. BIFP0_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
18994. BIFP0_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
18995. BIFP0_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
18996. BIFP0_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
18997. BIFP0_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
18998. BIFP0_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
18999. BIFP0_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
19000. BIFP0_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
19001. BIFP0_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
19002. BIFP0_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
19003. BIFP0_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
19004. BIFP0_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
19005. BIFP0_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
19006. BIFP0_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
19007. BIFP0_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
19008. BIFP0_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
19009. BIFP0_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
19010. BIFP0_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
19011. BIFP0_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
19012. BIFP0_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
19013. BIFP0_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
19014. BIFP0_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
19015. BIFP0_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
19016. BIFP0_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
19017. BIFP0_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
19018. BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
19019. BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
19020. BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
19021. BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
19022. BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
19023. BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
19024. BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
19025. BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
19026. BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
19027. BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
19028. BIFP0_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
19029. BIFP0_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
19030. BIFP0_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
19031. BIFP0_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
19032. BIFP0_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
19033. BIFP0_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
19034. BIFP0_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
19035. BIFP0_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
19036. BIFP0_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
19037. BIFP0_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
19038. BIFP0_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
19039. BIFP0_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
19040. BIFP0_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
19041. BIFP0_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
19042. BIFP0_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
19043. BIFP0_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
19044. BIFP0_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
19045. BIFP0_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
19046. BIFP0_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
19047. BIFP0_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
19048. BIFP0_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
19049. BIFP0_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
19050. BIFP0_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
19051. BIFP0_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
19052. BIFP0_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
19053. BIFP0_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
19054. BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
19055. BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
19056. BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
19057. BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
19058. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK
19059. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT
19060. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK
19061. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT
19062. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK
19063. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT
19064. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK
19065. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT
19066. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK
19067. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT
19068. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK
19069. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT
19070. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK
19071. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT
19072. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK
19073. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT
19074. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK
19075. BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT
19076. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK
19077. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT
19078. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK
19079. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT
19080. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK
19081. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT
19082. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK
19083. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT
19084. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK
19085. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT
19086. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK
19087. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK
19088. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT
19089. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT
19090. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK
19091. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT
19092. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK
19093. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT
19094. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK
19095. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT
19096. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK
19097. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT
19098. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK
19099. BIFP0_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT
19100. BIFP0_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK
19101. BIFP0_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT
19102. BIFP0_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK
19103. BIFP0_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT
19104. BIFP0_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK
19105. BIFP0_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT
19106. BIFP0_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK
19107. BIFP0_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT
19108. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK
19109. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT
19110. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK
19111. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT
19112. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK
19113. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT
19114. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK
19115. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT
19116. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK
19117. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
19118. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK
19119. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT
19120. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK
19121. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
19122. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK
19123. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT
19124. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK
19125. BIFP0_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT
19126. BIFP0_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK
19127. BIFP0_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT
19128. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK
19129. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT
19130. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK
19131. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT
19132. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK
19133. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT
19134. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK
19135. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT
19136. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK
19137. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT
19138. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK
19139. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT
19140. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK
19141. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT
19142. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK
19143. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT
19144. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK
19145. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
19146. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK
19147. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT
19148. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK
19149. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT
19150. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK
19151. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT
19152. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK
19153. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT
19154. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK
19155. BIFP0_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT
19156. BIFP0_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
19157. BIFP0_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
19158. BIFP0_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
19159. BIFP0_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
19160. BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
19161. BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
19162. BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
19163. BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
19164. BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
19165. BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
19166. BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
19167. BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
19168. BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
19169. BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
19170. BIFP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
19171. BIFP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
19172. BIFP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
19173. BIFP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
19174. BIFP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
19175. BIFP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
19176. BIFP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
19177. BIFP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
19178. BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
19179. BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
19180. BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
19181. BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
19182. BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
19183. BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
19184. BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
19185. BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
19186. BIFP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
19187. BIFP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
19188. BIFP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
19189. BIFP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
19190. BIFP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
19191. BIFP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
19192. BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
19193. BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
19194. BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
19195. BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
19196. BIFP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
19197. BIFP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
19198. BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
19199. BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
19200. BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
19201. BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
19202. BIFP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
19203. BIFP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
19204. BIFP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
19205. BIFP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
19206. BIFP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
19207. BIFP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
19208. BIFP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
19209. BIFP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
19210. BIFP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
19211. BIFP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
19212. BIFP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
19213. BIFP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
19214. BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
19215. BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
19216. BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
19217. BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
19218. BIFP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
19219. BIFP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
19220. BIFP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK
19221. BIFP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
19222. BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
19223. BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
19224. BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
19225. BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
19226. BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
19227. BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
19228. BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
19229. BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
19230. BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
19231. BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
19232. BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
19233. BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
19234. BIFP0_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
19235. BIFP0_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
19236. BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
19237. BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
19238. BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
19239. BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
19240. BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
19241. BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
19242. BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
19243. BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
19244. BIFP0_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
19245. BIFP0_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
19246. BIFP0_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
19247. BIFP0_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
19248. BIFP0_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
19249. BIFP0_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
19250. BIFP0_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
19251. BIFP0_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
19252. BIFP0_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
19253. BIFP0_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
19254. BIFP0_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
19255. BIFP0_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
19256. BIFP0_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
19257. BIFP0_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
19258. BIFP0_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
19259. BIFP0_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
19260. BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
19261. BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
19262. BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
19263. BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
19264. BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
19265. BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
19266. BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
19267. BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
19268. BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
19269. BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
19270. BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
19271. BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
19272. BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
19273. BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
19274. BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
19275. BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
19276. BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
19277. BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
19278. BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
19279. BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
19280. BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
19281. BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
19282. BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
19283. BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
19284. BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
19285. BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
19286. BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
19287. BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
19288. BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
19289. BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
19290. BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
19291. BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
19292. BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
19293. BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
19294. BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
19295. BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
19296. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
19297. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
19298. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
19299. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
19300. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
19301. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
19302. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
19303. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
19304. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
19305. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
19306. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
19307. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
19308. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
19309. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
19310. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
19311. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
19312. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
19313. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
19314. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
19315. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
19316. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
19317. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
19318. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
19319. BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
19320. BIFP0_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
19321. BIFP0_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
19322. BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
19323. BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
19324. BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
19325. BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
19326. BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
19327. BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
19328. BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
19329. BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
19330. BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
19331. BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
19332. BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
19333. BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
19334. BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
19335. BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
19336. BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
19337. BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
19338. BIFP0_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
19339. BIFP0_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
19340. BIFP0_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
19341. BIFP0_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
19342. BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
19343. BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
19344. BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
19345. BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
19346. BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
19347. BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
19348. BIFP1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
19349. BIFP1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
19350. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
19351. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
19352. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
19353. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
19354. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
19355. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
19356. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
19357. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
19358. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
19359. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
19360. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
19361. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
19362. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
19363. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
19364. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
19365. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
19366. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
19367. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
19368. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
19369. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
19370. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
19371. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
19372. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
19373. BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
19374. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
19375. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
19376. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
19377. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
19378. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
19379. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
19380. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
19381. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
19382. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
19383. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
19384. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
19385. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
19386. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
19387. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
19388. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
19389. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
19390. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
19391. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
19392. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
19393. BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
19394. BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK
19395. BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT
19396. BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK
19397. BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT
19398. BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
19399. BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
19400. BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
19401. BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
19402. BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
19403. BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
19404. BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
19405. BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
19406. BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
19407. BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
19408. BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
19409. BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
19410. BIFP1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
19411. BIFP1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
19412. BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
19413. BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
19414. BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
19415. BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
19416. BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
19417. BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
19418. BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
19419. BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
19420. BIFP1_PCIEP_HPGI__REG_HPGI_HOOK_MASK
19421. BIFP1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
19422. BIFP1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
19423. BIFP1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
19424. BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK
19425. BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT
19426. BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK
19427. BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT
19428. BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK
19429. BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT
19430. BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK
19431. BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT
19432. BIFP1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
19433. BIFP1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
19434. BIFP1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
19435. BIFP1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
19436. BIFP1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
19437. BIFP1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
19438. BIFP1_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK
19439. BIFP1_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT
19440. BIFP1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
19441. BIFP1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
19442. BIFP1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
19443. BIFP1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
19444. BIFP1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
19445. BIFP1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
19446. BIFP1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
19447. BIFP1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
19448. BIFP1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
19449. BIFP1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
19450. BIFP1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
19451. BIFP1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
19452. BIFP1_PCIEP_RESERVED__PCIEP_RESERVED_MASK
19453. BIFP1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
19454. BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK
19455. BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT
19456. BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK
19457. BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT
19458. BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK
19459. BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT
19460. BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK
19461. BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT
19462. BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK
19463. BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT
19464. BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK
19465. BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT
19466. BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK
19467. BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT
19468. BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK
19469. BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT
19470. BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK
19471. BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT
19472. BIFP1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
19473. BIFP1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
19474. BIFP1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
19475. BIFP1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
19476. BIFP1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
19477. BIFP1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
19478. BIFP1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
19479. BIFP1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
19480. BIFP1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
19481. BIFP1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
19482. BIFP1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
19483. BIFP1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
19484. BIFP1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
19485. BIFP1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
19486. BIFP1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
19487. BIFP1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
19488. BIFP1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
19489. BIFP1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
19490. BIFP1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
19491. BIFP1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
19492. BIFP1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
19493. BIFP1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
19494. BIFP1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
19495. BIFP1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
19496. BIFP1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
19497. BIFP1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
19498. BIFP1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
19499. BIFP1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
19500. BIFP1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
19501. BIFP1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
19502. BIFP1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
19503. BIFP1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
19504. BIFP1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
19505. BIFP1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
19506. BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
19507. BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
19508. BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
19509. BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
19510. BIFP1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
19511. BIFP1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
19512. BIFP1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
19513. BIFP1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
19514. BIFP1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
19515. BIFP1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
19516. BIFP1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
19517. BIFP1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
19518. BIFP1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
19519. BIFP1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
19520. BIFP1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
19521. BIFP1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
19522. BIFP1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
19523. BIFP1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
19524. BIFP1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
19525. BIFP1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
19526. BIFP1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
19527. BIFP1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
19528. BIFP1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
19529. BIFP1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
19530. BIFP1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
19531. BIFP1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
19532. BIFP1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
19533. BIFP1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
19534. BIFP1_PCIE_FC_CPL__CPLD_CREDITS_MASK
19535. BIFP1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
19536. BIFP1_PCIE_FC_CPL__CPLH_CREDITS_MASK
19537. BIFP1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
19538. BIFP1_PCIE_FC_NP__NPD_CREDITS_MASK
19539. BIFP1_PCIE_FC_NP__NPD_CREDITS__SHIFT
19540. BIFP1_PCIE_FC_NP__NPH_CREDITS_MASK
19541. BIFP1_PCIE_FC_NP__NPH_CREDITS__SHIFT
19542. BIFP1_PCIE_FC_P__PD_CREDITS_MASK
19543. BIFP1_PCIE_FC_P__PD_CREDITS__SHIFT
19544. BIFP1_PCIE_FC_P__PH_CREDITS_MASK
19545. BIFP1_PCIE_FC_P__PH_CREDITS__SHIFT
19546. BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
19547. BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
19548. BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
19549. BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
19550. BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
19551. BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
19552. BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
19553. BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
19554. BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
19555. BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
19556. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
19557. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
19558. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
19559. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
19560. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
19561. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
19562. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
19563. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
19564. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
19565. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
19566. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
19567. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
19568. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
19569. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
19570. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
19571. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
19572. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
19573. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
19574. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
19575. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
19576. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK
19577. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT
19578. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
19579. BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
19580. BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
19581. BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
19582. BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
19583. BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
19584. BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
19585. BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
19586. BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
19587. BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
19588. BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
19589. BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
19590. BIFP1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
19591. BIFP1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
19592. BIFP1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
19593. BIFP1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
19594. BIFP1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
19595. BIFP1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
19596. BIFP1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
19597. BIFP1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
19598. BIFP1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
19599. BIFP1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
19600. BIFP1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
19601. BIFP1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
19602. BIFP1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
19603. BIFP1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
19604. BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
19605. BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
19606. BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
19607. BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
19608. BIFP1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
19609. BIFP1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
19610. BIFP1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
19611. BIFP1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
19612. BIFP1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
19613. BIFP1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
19614. BIFP1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
19615. BIFP1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
19616. BIFP1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
19617. BIFP1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
19618. BIFP1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
19619. BIFP1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
19620. BIFP1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
19621. BIFP1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
19622. BIFP1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
19623. BIFP1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
19624. BIFP1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
19625. BIFP1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
19626. BIFP1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
19627. BIFP1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
19628. BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
19629. BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
19630. BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
19631. BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
19632. BIFP1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
19633. BIFP1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
19634. BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
19635. BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
19636. BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
19637. BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
19638. BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
19639. BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
19640. BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
19641. BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
19642. BIFP1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
19643. BIFP1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
19644. BIFP1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
19645. BIFP1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
19646. BIFP1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
19647. BIFP1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
19648. BIFP1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
19649. BIFP1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
19650. BIFP1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
19651. BIFP1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
19652. BIFP1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
19653. BIFP1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
19654. BIFP1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
19655. BIFP1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
19656. BIFP1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
19657. BIFP1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
19658. BIFP1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
19659. BIFP1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
19660. BIFP1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
19661. BIFP1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
19662. BIFP1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
19663. BIFP1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
19664. BIFP1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
19665. BIFP1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
19666. BIFP1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
19667. BIFP1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
19668. BIFP1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
19669. BIFP1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
19670. BIFP1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
19671. BIFP1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
19672. BIFP1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
19673. BIFP1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
19674. BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
19675. BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
19676. BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
19677. BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
19678. BIFP1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
19679. BIFP1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
19680. BIFP1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
19681. BIFP1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
19682. BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
19683. BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
19684. BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
19685. BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
19686. BIFP1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
19687. BIFP1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
19688. BIFP1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
19689. BIFP1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
19690. BIFP1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
19691. BIFP1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
19692. BIFP1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
19693. BIFP1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
19694. BIFP1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
19695. BIFP1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
19696. BIFP1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
19697. BIFP1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
19698. BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
19699. BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
19700. BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
19701. BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
19702. BIFP1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
19703. BIFP1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
19704. BIFP1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
19705. BIFP1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
19706. BIFP1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
19707. BIFP1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
19708. BIFP1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
19709. BIFP1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
19710. BIFP1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
19711. BIFP1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
19712. BIFP1_PCIE_LC_CNTL4__LC_TX_SWING_MASK
19713. BIFP1_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT
19714. BIFP1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
19715. BIFP1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
19716. BIFP1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
19717. BIFP1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
19718. BIFP1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
19719. BIFP1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
19720. BIFP1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
19721. BIFP1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
19722. BIFP1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
19723. BIFP1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
19724. BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK
19725. BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK
19726. BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT
19727. BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT
19728. BIFP1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
19729. BIFP1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
19730. BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
19731. BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
19732. BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
19733. BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
19734. BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
19735. BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
19736. BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
19737. BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
19738. BIFP1_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK
19739. BIFP1_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT
19740. BIFP1_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK
19741. BIFP1_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT
19742. BIFP1_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK
19743. BIFP1_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT
19744. BIFP1_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK
19745. BIFP1_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT
19746. BIFP1_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK
19747. BIFP1_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT
19748. BIFP1_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK
19749. BIFP1_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT
19750. BIFP1_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK
19751. BIFP1_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT
19752. BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK
19753. BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT
19754. BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK
19755. BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT
19756. BIFP1_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK
19757. BIFP1_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT
19758. BIFP1_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK
19759. BIFP1_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT
19760. BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
19761. BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
19762. BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
19763. BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
19764. BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
19765. BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
19766. BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK
19767. BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT
19768. BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK
19769. BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT
19770. BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK
19771. BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT
19772. BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK
19773. BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT
19774. BIFP1_PCIE_LC_CNTL6__LC_SRIS_EN_MASK
19775. BIFP1_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT
19776. BIFP1_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK
19777. BIFP1_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT
19778. BIFP1_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK
19779. BIFP1_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT
19780. BIFP1_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK
19781. BIFP1_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT
19782. BIFP1_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK
19783. BIFP1_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT
19784. BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK
19785. BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT
19786. BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK
19787. BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT
19788. BIFP1_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK
19789. BIFP1_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT
19790. BIFP1_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK
19791. BIFP1_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT
19792. BIFP1_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK
19793. BIFP1_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT
19794. BIFP1_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK
19795. BIFP1_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT
19796. BIFP1_PCIE_LC_CNTL7__LC_FOM_TIME_MASK
19797. BIFP1_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT
19798. BIFP1_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK
19799. BIFP1_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT
19800. BIFP1_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK
19801. BIFP1_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT
19802. BIFP1_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK
19803. BIFP1_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT
19804. BIFP1_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK
19805. BIFP1_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT
19806. BIFP1_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK
19807. BIFP1_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT
19808. BIFP1_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK
19809. BIFP1_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT
19810. BIFP1_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK
19811. BIFP1_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT
19812. BIFP1_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK
19813. BIFP1_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT
19814. BIFP1_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK
19815. BIFP1_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT
19816. BIFP1_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK
19817. BIFP1_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT
19818. BIFP1_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK
19819. BIFP1_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT
19820. BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK
19821. BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT
19822. BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK
19823. BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT
19824. BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK
19825. BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT
19826. BIFP1_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK
19827. BIFP1_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT
19828. BIFP1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
19829. BIFP1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
19830. BIFP1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
19831. BIFP1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
19832. BIFP1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
19833. BIFP1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
19834. BIFP1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
19835. BIFP1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
19836. BIFP1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
19837. BIFP1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
19838. BIFP1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
19839. BIFP1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
19840. BIFP1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
19841. BIFP1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
19842. BIFP1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
19843. BIFP1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
19844. BIFP1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
19845. BIFP1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
19846. BIFP1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
19847. BIFP1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
19848. BIFP1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
19849. BIFP1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
19850. BIFP1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
19851. BIFP1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
19852. BIFP1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
19853. BIFP1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
19854. BIFP1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
19855. BIFP1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
19856. BIFP1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
19857. BIFP1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
19858. BIFP1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
19859. BIFP1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
19860. BIFP1_PCIE_LC_CNTL__LC_RESET_LINK_MASK
19861. BIFP1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
19862. BIFP1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
19863. BIFP1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
19864. BIFP1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
19865. BIFP1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
19866. BIFP1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
19867. BIFP1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
19868. BIFP1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
19869. BIFP1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
19870. BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
19871. BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
19872. BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
19873. BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
19874. BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
19875. BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
19876. BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
19877. BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
19878. BIFP1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
19879. BIFP1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
19880. BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
19881. BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
19882. BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
19883. BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
19884. BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
19885. BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
19886. BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
19887. BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
19888. BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
19889. BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
19890. BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
19891. BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
19892. BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK
19893. BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT
19894. BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK
19895. BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT
19896. BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK
19897. BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT
19898. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK
19899. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT
19900. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK
19901. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT
19902. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK
19903. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT
19904. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK
19905. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT
19906. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK
19907. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT
19908. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK
19909. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT
19910. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK
19911. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT
19912. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK
19913. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT
19914. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK
19915. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT
19916. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK
19917. BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT
19918. BIFP1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
19919. BIFP1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
19920. BIFP1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
19921. BIFP1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
19922. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
19923. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
19924. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK
19925. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT
19926. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
19927. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
19928. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
19929. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
19930. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
19931. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
19932. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
19933. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
19934. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
19935. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
19936. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
19937. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
19938. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
19939. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
19940. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
19941. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
19942. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
19943. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
19944. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
19945. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
19946. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
19947. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
19948. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
19949. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
19950. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
19951. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
19952. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
19953. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
19954. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
19955. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
19956. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
19957. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
19958. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK
19959. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT
19960. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
19961. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
19962. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
19963. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
19964. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
19965. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
19966. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
19967. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
19968. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
19969. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
19970. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
19971. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
19972. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
19973. BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
19974. BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
19975. BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
19976. BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
19977. BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
19978. BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK
19979. BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT
19980. BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
19981. BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
19982. BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
19983. BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
19984. BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
19985. BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
19986. BIFP1_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK
19987. BIFP1_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT
19988. BIFP1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
19989. BIFP1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
19990. BIFP1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
19991. BIFP1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
19992. BIFP1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
19993. BIFP1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
19994. BIFP1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
19995. BIFP1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
19996. BIFP1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
19997. BIFP1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
19998. BIFP1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
19999. BIFP1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
20000. BIFP1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
20001. BIFP1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
20002. BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
20003. BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
20004. BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
20005. BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
20006. BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
20007. BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
20008. BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
20009. BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
20010. BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
20011. BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
20012. BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
20013. BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
20014. BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
20015. BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
20016. BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
20017. BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
20018. BIFP1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
20019. BIFP1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
20020. BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
20021. BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
20022. BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
20023. BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
20024. BIFP1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
20025. BIFP1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
20026. BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
20027. BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
20028. BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
20029. BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
20030. BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
20031. BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
20032. BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
20033. BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
20034. BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
20035. BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
20036. BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
20037. BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
20038. BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
20039. BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
20040. BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
20041. BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
20042. BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
20043. BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
20044. BIFP1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
20045. BIFP1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
20046. BIFP1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
20047. BIFP1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
20048. BIFP1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
20049. BIFP1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
20050. BIFP1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
20051. BIFP1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
20052. BIFP1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
20053. BIFP1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
20054. BIFP1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
20055. BIFP1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
20056. BIFP1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
20057. BIFP1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
20058. BIFP1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
20059. BIFP1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
20060. BIFP1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
20061. BIFP1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
20062. BIFP1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
20063. BIFP1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
20064. BIFP1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
20065. BIFP1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
20066. BIFP1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
20067. BIFP1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
20068. BIFP1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
20069. BIFP1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
20070. BIFP1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
20071. BIFP1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
20072. BIFP1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
20073. BIFP1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
20074. BIFP1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
20075. BIFP1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
20076. BIFP1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
20077. BIFP1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
20078. BIFP1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
20079. BIFP1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
20080. BIFP1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
20081. BIFP1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
20082. BIFP1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
20083. BIFP1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
20084. BIFP1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
20085. BIFP1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
20086. BIFP1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
20087. BIFP1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
20088. BIFP1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
20089. BIFP1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
20090. BIFP1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
20091. BIFP1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
20092. BIFP1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
20093. BIFP1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
20094. BIFP1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
20095. BIFP1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
20096. BIFP1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
20097. BIFP1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
20098. BIFP1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
20099. BIFP1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
20100. BIFP1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
20101. BIFP1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
20102. BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
20103. BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
20104. BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
20105. BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
20106. BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
20107. BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
20108. BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
20109. BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
20110. BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
20111. BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
20112. BIFP1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
20113. BIFP1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
20114. BIFP1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
20115. BIFP1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
20116. BIFP1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
20117. BIFP1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
20118. BIFP1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
20119. BIFP1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
20120. BIFP1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
20121. BIFP1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
20122. BIFP1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
20123. BIFP1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
20124. BIFP1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
20125. BIFP1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
20126. BIFP1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
20127. BIFP1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
20128. BIFP1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
20129. BIFP1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
20130. BIFP1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
20131. BIFP1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
20132. BIFP1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
20133. BIFP1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
20134. BIFP1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
20135. BIFP1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
20136. BIFP1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
20137. BIFP1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
20138. BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
20139. BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
20140. BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
20141. BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
20142. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK
20143. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT
20144. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK
20145. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT
20146. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK
20147. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT
20148. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK
20149. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT
20150. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK
20151. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT
20152. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK
20153. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT
20154. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK
20155. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT
20156. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK
20157. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT
20158. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK
20159. BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT
20160. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK
20161. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT
20162. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK
20163. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT
20164. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK
20165. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT
20166. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK
20167. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT
20168. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK
20169. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT
20170. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK
20171. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK
20172. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT
20173. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT
20174. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK
20175. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT
20176. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK
20177. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT
20178. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK
20179. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT
20180. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK
20181. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT
20182. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK
20183. BIFP1_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT
20184. BIFP1_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK
20185. BIFP1_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT
20186. BIFP1_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK
20187. BIFP1_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT
20188. BIFP1_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK
20189. BIFP1_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT
20190. BIFP1_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK
20191. BIFP1_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT
20192. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK
20193. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT
20194. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK
20195. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT
20196. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK
20197. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT
20198. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK
20199. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT
20200. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK
20201. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
20202. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK
20203. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT
20204. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK
20205. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
20206. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK
20207. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT
20208. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK
20209. BIFP1_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT
20210. BIFP1_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK
20211. BIFP1_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT
20212. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK
20213. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT
20214. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK
20215. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT
20216. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK
20217. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT
20218. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK
20219. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT
20220. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK
20221. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT
20222. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK
20223. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT
20224. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK
20225. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT
20226. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK
20227. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT
20228. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK
20229. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
20230. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK
20231. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT
20232. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK
20233. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT
20234. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK
20235. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT
20236. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK
20237. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT
20238. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK
20239. BIFP1_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT
20240. BIFP1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
20241. BIFP1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
20242. BIFP1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
20243. BIFP1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
20244. BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
20245. BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
20246. BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
20247. BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
20248. BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
20249. BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
20250. BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
20251. BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
20252. BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
20253. BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
20254. BIFP1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
20255. BIFP1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
20256. BIFP1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
20257. BIFP1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
20258. BIFP1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
20259. BIFP1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
20260. BIFP1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
20261. BIFP1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
20262. BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
20263. BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
20264. BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
20265. BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
20266. BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
20267. BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
20268. BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
20269. BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
20270. BIFP1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
20271. BIFP1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
20272. BIFP1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
20273. BIFP1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
20274. BIFP1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
20275. BIFP1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
20276. BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
20277. BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
20278. BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
20279. BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
20280. BIFP1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
20281. BIFP1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
20282. BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
20283. BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
20284. BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
20285. BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
20286. BIFP1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
20287. BIFP1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
20288. BIFP1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
20289. BIFP1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
20290. BIFP1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
20291. BIFP1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
20292. BIFP1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
20293. BIFP1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
20294. BIFP1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
20295. BIFP1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
20296. BIFP1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
20297. BIFP1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
20298. BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
20299. BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
20300. BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
20301. BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
20302. BIFP1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
20303. BIFP1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
20304. BIFP1_PCIE_RX_CNTL__RX_TPH_DIS_MASK
20305. BIFP1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
20306. BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
20307. BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
20308. BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
20309. BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
20310. BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
20311. BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
20312. BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
20313. BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
20314. BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
20315. BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
20316. BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
20317. BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
20318. BIFP1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
20319. BIFP1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
20320. BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
20321. BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
20322. BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
20323. BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
20324. BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
20325. BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
20326. BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
20327. BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
20328. BIFP1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
20329. BIFP1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
20330. BIFP1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
20331. BIFP1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
20332. BIFP1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
20333. BIFP1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
20334. BIFP1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
20335. BIFP1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
20336. BIFP1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
20337. BIFP1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
20338. BIFP1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
20339. BIFP1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
20340. BIFP1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
20341. BIFP1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
20342. BIFP1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
20343. BIFP1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
20344. BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
20345. BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
20346. BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
20347. BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
20348. BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
20349. BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
20350. BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
20351. BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
20352. BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
20353. BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
20354. BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
20355. BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
20356. BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
20357. BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
20358. BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
20359. BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
20360. BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
20361. BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
20362. BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
20363. BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
20364. BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
20365. BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
20366. BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
20367. BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
20368. BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
20369. BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
20370. BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
20371. BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
20372. BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
20373. BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
20374. BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
20375. BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
20376. BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
20377. BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
20378. BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
20379. BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
20380. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
20381. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
20382. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
20383. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
20384. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
20385. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
20386. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
20387. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
20388. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
20389. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
20390. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
20391. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
20392. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
20393. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
20394. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
20395. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
20396. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
20397. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
20398. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
20399. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
20400. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
20401. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
20402. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
20403. BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
20404. BIFP1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
20405. BIFP1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
20406. BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
20407. BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
20408. BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
20409. BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
20410. BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
20411. BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
20412. BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
20413. BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
20414. BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
20415. BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
20416. BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
20417. BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
20418. BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
20419. BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
20420. BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
20421. BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
20422. BIFP1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
20423. BIFP1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
20424. BIFP1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
20425. BIFP1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
20426. BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
20427. BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
20428. BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
20429. BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
20430. BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
20431. BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
20432. BIFP2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
20433. BIFP2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
20434. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
20435. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
20436. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
20437. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
20438. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
20439. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
20440. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
20441. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
20442. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
20443. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
20444. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
20445. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
20446. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
20447. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
20448. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
20449. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
20450. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
20451. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
20452. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
20453. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
20454. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
20455. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
20456. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
20457. BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
20458. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
20459. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
20460. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
20461. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
20462. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
20463. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
20464. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
20465. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
20466. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
20467. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
20468. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
20469. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
20470. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
20471. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
20472. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
20473. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
20474. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
20475. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
20476. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
20477. BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
20478. BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK
20479. BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT
20480. BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK
20481. BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT
20482. BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
20483. BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
20484. BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
20485. BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
20486. BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
20487. BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
20488. BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
20489. BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
20490. BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
20491. BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
20492. BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
20493. BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
20494. BIFP2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
20495. BIFP2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
20496. BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
20497. BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
20498. BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
20499. BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
20500. BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
20501. BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
20502. BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
20503. BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
20504. BIFP2_PCIEP_HPGI__REG_HPGI_HOOK_MASK
20505. BIFP2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
20506. BIFP2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
20507. BIFP2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
20508. BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK
20509. BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT
20510. BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK
20511. BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT
20512. BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK
20513. BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT
20514. BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK
20515. BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT
20516. BIFP2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
20517. BIFP2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
20518. BIFP2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
20519. BIFP2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
20520. BIFP2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
20521. BIFP2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
20522. BIFP2_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK
20523. BIFP2_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT
20524. BIFP2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
20525. BIFP2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
20526. BIFP2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
20527. BIFP2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
20528. BIFP2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
20529. BIFP2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
20530. BIFP2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
20531. BIFP2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
20532. BIFP2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
20533. BIFP2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
20534. BIFP2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
20535. BIFP2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
20536. BIFP2_PCIEP_RESERVED__PCIEP_RESERVED_MASK
20537. BIFP2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
20538. BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK
20539. BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT
20540. BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK
20541. BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT
20542. BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK
20543. BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT
20544. BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK
20545. BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT
20546. BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK
20547. BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT
20548. BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK
20549. BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT
20550. BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK
20551. BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT
20552. BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK
20553. BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT
20554. BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK
20555. BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT
20556. BIFP2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
20557. BIFP2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
20558. BIFP2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
20559. BIFP2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
20560. BIFP2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
20561. BIFP2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
20562. BIFP2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
20563. BIFP2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
20564. BIFP2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
20565. BIFP2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
20566. BIFP2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
20567. BIFP2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
20568. BIFP2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
20569. BIFP2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
20570. BIFP2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
20571. BIFP2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
20572. BIFP2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
20573. BIFP2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
20574. BIFP2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
20575. BIFP2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
20576. BIFP2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
20577. BIFP2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
20578. BIFP2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
20579. BIFP2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
20580. BIFP2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
20581. BIFP2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
20582. BIFP2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
20583. BIFP2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
20584. BIFP2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
20585. BIFP2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
20586. BIFP2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
20587. BIFP2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
20588. BIFP2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
20589. BIFP2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
20590. BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
20591. BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
20592. BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
20593. BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
20594. BIFP2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
20595. BIFP2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
20596. BIFP2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
20597. BIFP2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
20598. BIFP2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
20599. BIFP2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
20600. BIFP2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
20601. BIFP2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
20602. BIFP2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
20603. BIFP2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
20604. BIFP2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
20605. BIFP2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
20606. BIFP2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
20607. BIFP2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
20608. BIFP2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
20609. BIFP2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
20610. BIFP2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
20611. BIFP2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
20612. BIFP2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
20613. BIFP2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
20614. BIFP2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
20615. BIFP2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
20616. BIFP2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
20617. BIFP2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
20618. BIFP2_PCIE_FC_CPL__CPLD_CREDITS_MASK
20619. BIFP2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
20620. BIFP2_PCIE_FC_CPL__CPLH_CREDITS_MASK
20621. BIFP2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
20622. BIFP2_PCIE_FC_NP__NPD_CREDITS_MASK
20623. BIFP2_PCIE_FC_NP__NPD_CREDITS__SHIFT
20624. BIFP2_PCIE_FC_NP__NPH_CREDITS_MASK
20625. BIFP2_PCIE_FC_NP__NPH_CREDITS__SHIFT
20626. BIFP2_PCIE_FC_P__PD_CREDITS_MASK
20627. BIFP2_PCIE_FC_P__PD_CREDITS__SHIFT
20628. BIFP2_PCIE_FC_P__PH_CREDITS_MASK
20629. BIFP2_PCIE_FC_P__PH_CREDITS__SHIFT
20630. BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
20631. BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
20632. BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
20633. BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
20634. BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
20635. BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
20636. BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
20637. BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
20638. BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
20639. BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
20640. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
20641. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
20642. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
20643. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
20644. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
20645. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
20646. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
20647. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
20648. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
20649. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
20650. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
20651. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
20652. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
20653. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
20654. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
20655. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
20656. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
20657. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
20658. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
20659. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
20660. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK
20661. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT
20662. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
20663. BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
20664. BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
20665. BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
20666. BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
20667. BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
20668. BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
20669. BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
20670. BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
20671. BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
20672. BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
20673. BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
20674. BIFP2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
20675. BIFP2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
20676. BIFP2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
20677. BIFP2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
20678. BIFP2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
20679. BIFP2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
20680. BIFP2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
20681. BIFP2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
20682. BIFP2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
20683. BIFP2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
20684. BIFP2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
20685. BIFP2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
20686. BIFP2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
20687. BIFP2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
20688. BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
20689. BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
20690. BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
20691. BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
20692. BIFP2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
20693. BIFP2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
20694. BIFP2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
20695. BIFP2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
20696. BIFP2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
20697. BIFP2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
20698. BIFP2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
20699. BIFP2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
20700. BIFP2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
20701. BIFP2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
20702. BIFP2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
20703. BIFP2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
20704. BIFP2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
20705. BIFP2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
20706. BIFP2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
20707. BIFP2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
20708. BIFP2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
20709. BIFP2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
20710. BIFP2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
20711. BIFP2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
20712. BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
20713. BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
20714. BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
20715. BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
20716. BIFP2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
20717. BIFP2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
20718. BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
20719. BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
20720. BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
20721. BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
20722. BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
20723. BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
20724. BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
20725. BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
20726. BIFP2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
20727. BIFP2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
20728. BIFP2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
20729. BIFP2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
20730. BIFP2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
20731. BIFP2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
20732. BIFP2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
20733. BIFP2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
20734. BIFP2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
20735. BIFP2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
20736. BIFP2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
20737. BIFP2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
20738. BIFP2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
20739. BIFP2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
20740. BIFP2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
20741. BIFP2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
20742. BIFP2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
20743. BIFP2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
20744. BIFP2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
20745. BIFP2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
20746. BIFP2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
20747. BIFP2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
20748. BIFP2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
20749. BIFP2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
20750. BIFP2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
20751. BIFP2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
20752. BIFP2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
20753. BIFP2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
20754. BIFP2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
20755. BIFP2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
20756. BIFP2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
20757. BIFP2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
20758. BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
20759. BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
20760. BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
20761. BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
20762. BIFP2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
20763. BIFP2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
20764. BIFP2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
20765. BIFP2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
20766. BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
20767. BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
20768. BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
20769. BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
20770. BIFP2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
20771. BIFP2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
20772. BIFP2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
20773. BIFP2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
20774. BIFP2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
20775. BIFP2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
20776. BIFP2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
20777. BIFP2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
20778. BIFP2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
20779. BIFP2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
20780. BIFP2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
20781. BIFP2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
20782. BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
20783. BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
20784. BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
20785. BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
20786. BIFP2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
20787. BIFP2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
20788. BIFP2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
20789. BIFP2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
20790. BIFP2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
20791. BIFP2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
20792. BIFP2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
20793. BIFP2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
20794. BIFP2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
20795. BIFP2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
20796. BIFP2_PCIE_LC_CNTL4__LC_TX_SWING_MASK
20797. BIFP2_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT
20798. BIFP2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
20799. BIFP2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
20800. BIFP2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
20801. BIFP2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
20802. BIFP2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
20803. BIFP2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
20804. BIFP2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
20805. BIFP2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
20806. BIFP2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
20807. BIFP2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
20808. BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK
20809. BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK
20810. BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT
20811. BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT
20812. BIFP2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
20813. BIFP2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
20814. BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
20815. BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
20816. BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
20817. BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
20818. BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
20819. BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
20820. BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
20821. BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
20822. BIFP2_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK
20823. BIFP2_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT
20824. BIFP2_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK
20825. BIFP2_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT
20826. BIFP2_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK
20827. BIFP2_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT
20828. BIFP2_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK
20829. BIFP2_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT
20830. BIFP2_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK
20831. BIFP2_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT
20832. BIFP2_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK
20833. BIFP2_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT
20834. BIFP2_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK
20835. BIFP2_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT
20836. BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK
20837. BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT
20838. BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK
20839. BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT
20840. BIFP2_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK
20841. BIFP2_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT
20842. BIFP2_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK
20843. BIFP2_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT
20844. BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
20845. BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
20846. BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
20847. BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
20848. BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
20849. BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
20850. BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK
20851. BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT
20852. BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK
20853. BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT
20854. BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK
20855. BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT
20856. BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK
20857. BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT
20858. BIFP2_PCIE_LC_CNTL6__LC_SRIS_EN_MASK
20859. BIFP2_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT
20860. BIFP2_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK
20861. BIFP2_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT
20862. BIFP2_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK
20863. BIFP2_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT
20864. BIFP2_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK
20865. BIFP2_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT
20866. BIFP2_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK
20867. BIFP2_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT
20868. BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK
20869. BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT
20870. BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK
20871. BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT
20872. BIFP2_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK
20873. BIFP2_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT
20874. BIFP2_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK
20875. BIFP2_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT
20876. BIFP2_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK
20877. BIFP2_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT
20878. BIFP2_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK
20879. BIFP2_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT
20880. BIFP2_PCIE_LC_CNTL7__LC_FOM_TIME_MASK
20881. BIFP2_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT
20882. BIFP2_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK
20883. BIFP2_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT
20884. BIFP2_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK
20885. BIFP2_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT
20886. BIFP2_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK
20887. BIFP2_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT
20888. BIFP2_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK
20889. BIFP2_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT
20890. BIFP2_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK
20891. BIFP2_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT
20892. BIFP2_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK
20893. BIFP2_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT
20894. BIFP2_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK
20895. BIFP2_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT
20896. BIFP2_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK
20897. BIFP2_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT
20898. BIFP2_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK
20899. BIFP2_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT
20900. BIFP2_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK
20901. BIFP2_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT
20902. BIFP2_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK
20903. BIFP2_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT
20904. BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK
20905. BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT
20906. BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK
20907. BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT
20908. BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK
20909. BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT
20910. BIFP2_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK
20911. BIFP2_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT
20912. BIFP2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
20913. BIFP2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
20914. BIFP2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
20915. BIFP2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
20916. BIFP2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
20917. BIFP2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
20918. BIFP2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
20919. BIFP2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
20920. BIFP2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
20921. BIFP2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
20922. BIFP2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
20923. BIFP2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
20924. BIFP2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
20925. BIFP2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
20926. BIFP2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
20927. BIFP2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
20928. BIFP2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
20929. BIFP2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
20930. BIFP2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
20931. BIFP2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
20932. BIFP2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
20933. BIFP2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
20934. BIFP2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
20935. BIFP2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
20936. BIFP2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
20937. BIFP2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
20938. BIFP2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
20939. BIFP2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
20940. BIFP2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
20941. BIFP2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
20942. BIFP2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
20943. BIFP2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
20944. BIFP2_PCIE_LC_CNTL__LC_RESET_LINK_MASK
20945. BIFP2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
20946. BIFP2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
20947. BIFP2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
20948. BIFP2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
20949. BIFP2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
20950. BIFP2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
20951. BIFP2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
20952. BIFP2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
20953. BIFP2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
20954. BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
20955. BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
20956. BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
20957. BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
20958. BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
20959. BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
20960. BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
20961. BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
20962. BIFP2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
20963. BIFP2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
20964. BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
20965. BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
20966. BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
20967. BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
20968. BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
20969. BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
20970. BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
20971. BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
20972. BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
20973. BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
20974. BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
20975. BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
20976. BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK
20977. BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT
20978. BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK
20979. BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT
20980. BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK
20981. BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT
20982. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK
20983. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT
20984. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK
20985. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT
20986. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK
20987. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT
20988. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK
20989. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT
20990. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK
20991. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT
20992. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK
20993. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT
20994. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK
20995. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT
20996. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK
20997. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT
20998. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK
20999. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT
21000. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK
21001. BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT
21002. BIFP2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
21003. BIFP2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
21004. BIFP2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
21005. BIFP2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
21006. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
21007. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
21008. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK
21009. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT
21010. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
21011. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
21012. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
21013. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
21014. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
21015. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
21016. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
21017. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
21018. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
21019. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
21020. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
21021. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
21022. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
21023. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
21024. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
21025. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
21026. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
21027. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
21028. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
21029. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
21030. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
21031. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
21032. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
21033. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
21034. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
21035. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
21036. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
21037. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
21038. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
21039. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
21040. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
21041. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
21042. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK
21043. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT
21044. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
21045. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
21046. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
21047. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
21048. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
21049. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
21050. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
21051. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
21052. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
21053. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
21054. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
21055. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
21056. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
21057. BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
21058. BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
21059. BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
21060. BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
21061. BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
21062. BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK
21063. BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT
21064. BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
21065. BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
21066. BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
21067. BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
21068. BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
21069. BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
21070. BIFP2_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK
21071. BIFP2_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT
21072. BIFP2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
21073. BIFP2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
21074. BIFP2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
21075. BIFP2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
21076. BIFP2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
21077. BIFP2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
21078. BIFP2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
21079. BIFP2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
21080. BIFP2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
21081. BIFP2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
21082. BIFP2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
21083. BIFP2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
21084. BIFP2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
21085. BIFP2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
21086. BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
21087. BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
21088. BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
21089. BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
21090. BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
21091. BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
21092. BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
21093. BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
21094. BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
21095. BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
21096. BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
21097. BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
21098. BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
21099. BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
21100. BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
21101. BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
21102. BIFP2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
21103. BIFP2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
21104. BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
21105. BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
21106. BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
21107. BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
21108. BIFP2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
21109. BIFP2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
21110. BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
21111. BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
21112. BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
21113. BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
21114. BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
21115. BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
21116. BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
21117. BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
21118. BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
21119. BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
21120. BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
21121. BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
21122. BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
21123. BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
21124. BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
21125. BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
21126. BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
21127. BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
21128. BIFP2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
21129. BIFP2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
21130. BIFP2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
21131. BIFP2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
21132. BIFP2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
21133. BIFP2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
21134. BIFP2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
21135. BIFP2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
21136. BIFP2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
21137. BIFP2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
21138. BIFP2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
21139. BIFP2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
21140. BIFP2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
21141. BIFP2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
21142. BIFP2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
21143. BIFP2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
21144. BIFP2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
21145. BIFP2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
21146. BIFP2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
21147. BIFP2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
21148. BIFP2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
21149. BIFP2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
21150. BIFP2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
21151. BIFP2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
21152. BIFP2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
21153. BIFP2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
21154. BIFP2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
21155. BIFP2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
21156. BIFP2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
21157. BIFP2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
21158. BIFP2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
21159. BIFP2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
21160. BIFP2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
21161. BIFP2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
21162. BIFP2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
21163. BIFP2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
21164. BIFP2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
21165. BIFP2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
21166. BIFP2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
21167. BIFP2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
21168. BIFP2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
21169. BIFP2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
21170. BIFP2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
21171. BIFP2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
21172. BIFP2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
21173. BIFP2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
21174. BIFP2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
21175. BIFP2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
21176. BIFP2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
21177. BIFP2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
21178. BIFP2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
21179. BIFP2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
21180. BIFP2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
21181. BIFP2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
21182. BIFP2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
21183. BIFP2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
21184. BIFP2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
21185. BIFP2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
21186. BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
21187. BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
21188. BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
21189. BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
21190. BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
21191. BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
21192. BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
21193. BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
21194. BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
21195. BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
21196. BIFP2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
21197. BIFP2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
21198. BIFP2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
21199. BIFP2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
21200. BIFP2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
21201. BIFP2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
21202. BIFP2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
21203. BIFP2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
21204. BIFP2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
21205. BIFP2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
21206. BIFP2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
21207. BIFP2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
21208. BIFP2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
21209. BIFP2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
21210. BIFP2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
21211. BIFP2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
21212. BIFP2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
21213. BIFP2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
21214. BIFP2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
21215. BIFP2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
21216. BIFP2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
21217. BIFP2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
21218. BIFP2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
21219. BIFP2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
21220. BIFP2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
21221. BIFP2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
21222. BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
21223. BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
21224. BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
21225. BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
21226. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK
21227. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT
21228. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK
21229. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT
21230. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK
21231. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT
21232. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK
21233. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT
21234. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK
21235. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT
21236. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK
21237. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT
21238. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK
21239. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT
21240. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK
21241. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT
21242. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK
21243. BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT
21244. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK
21245. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT
21246. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK
21247. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT
21248. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK
21249. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT
21250. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK
21251. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT
21252. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK
21253. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT
21254. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK
21255. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK
21256. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT
21257. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT
21258. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK
21259. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT
21260. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK
21261. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT
21262. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK
21263. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT
21264. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK
21265. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT
21266. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK
21267. BIFP2_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT
21268. BIFP2_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK
21269. BIFP2_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT
21270. BIFP2_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK
21271. BIFP2_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT
21272. BIFP2_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK
21273. BIFP2_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT
21274. BIFP2_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK
21275. BIFP2_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT
21276. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK
21277. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT
21278. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK
21279. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT
21280. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK
21281. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT
21282. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK
21283. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT
21284. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK
21285. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
21286. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK
21287. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT
21288. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK
21289. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
21290. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK
21291. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT
21292. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK
21293. BIFP2_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT
21294. BIFP2_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK
21295. BIFP2_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT
21296. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK
21297. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT
21298. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK
21299. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT
21300. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK
21301. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT
21302. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK
21303. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT
21304. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK
21305. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT
21306. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK
21307. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT
21308. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK
21309. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT
21310. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK
21311. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT
21312. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK
21313. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
21314. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK
21315. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT
21316. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK
21317. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT
21318. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK
21319. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT
21320. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK
21321. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT
21322. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK
21323. BIFP2_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT
21324. BIFP2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
21325. BIFP2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
21326. BIFP2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
21327. BIFP2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
21328. BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
21329. BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
21330. BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
21331. BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
21332. BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
21333. BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
21334. BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
21335. BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
21336. BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
21337. BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
21338. BIFP2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
21339. BIFP2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
21340. BIFP2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
21341. BIFP2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
21342. BIFP2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
21343. BIFP2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
21344. BIFP2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
21345. BIFP2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
21346. BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
21347. BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
21348. BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
21349. BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
21350. BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
21351. BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
21352. BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
21353. BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
21354. BIFP2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
21355. BIFP2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
21356. BIFP2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
21357. BIFP2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
21358. BIFP2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
21359. BIFP2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
21360. BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
21361. BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
21362. BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
21363. BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
21364. BIFP2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
21365. BIFP2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
21366. BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
21367. BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
21368. BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
21369. BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
21370. BIFP2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
21371. BIFP2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
21372. BIFP2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
21373. BIFP2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
21374. BIFP2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
21375. BIFP2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
21376. BIFP2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
21377. BIFP2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
21378. BIFP2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
21379. BIFP2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
21380. BIFP2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
21381. BIFP2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
21382. BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
21383. BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
21384. BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
21385. BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
21386. BIFP2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
21387. BIFP2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
21388. BIFP2_PCIE_RX_CNTL__RX_TPH_DIS_MASK
21389. BIFP2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
21390. BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
21391. BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
21392. BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
21393. BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
21394. BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
21395. BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
21396. BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
21397. BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
21398. BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
21399. BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
21400. BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
21401. BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
21402. BIFP2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
21403. BIFP2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
21404. BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
21405. BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
21406. BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
21407. BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
21408. BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
21409. BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
21410. BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
21411. BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
21412. BIFP2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
21413. BIFP2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
21414. BIFP2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
21415. BIFP2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
21416. BIFP2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
21417. BIFP2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
21418. BIFP2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
21419. BIFP2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
21420. BIFP2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
21421. BIFP2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
21422. BIFP2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
21423. BIFP2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
21424. BIFP2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
21425. BIFP2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
21426. BIFP2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
21427. BIFP2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
21428. BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
21429. BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
21430. BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
21431. BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
21432. BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
21433. BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
21434. BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
21435. BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
21436. BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
21437. BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
21438. BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
21439. BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
21440. BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
21441. BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
21442. BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
21443. BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
21444. BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
21445. BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
21446. BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
21447. BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
21448. BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
21449. BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
21450. BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
21451. BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
21452. BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
21453. BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
21454. BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
21455. BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
21456. BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
21457. BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
21458. BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
21459. BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
21460. BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
21461. BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
21462. BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
21463. BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
21464. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
21465. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
21466. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
21467. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
21468. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
21469. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
21470. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
21471. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
21472. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
21473. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
21474. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
21475. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
21476. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
21477. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
21478. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
21479. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
21480. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
21481. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
21482. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
21483. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
21484. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
21485. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
21486. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
21487. BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
21488. BIFP2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
21489. BIFP2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
21490. BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
21491. BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
21492. BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
21493. BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
21494. BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
21495. BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
21496. BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
21497. BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
21498. BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
21499. BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
21500. BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
21501. BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
21502. BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
21503. BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
21504. BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
21505. BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
21506. BIFP2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
21507. BIFP2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
21508. BIFP2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
21509. BIFP2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
21510. BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
21511. BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
21512. BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
21513. BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
21514. BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
21515. BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
21516. BIFP3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
21517. BIFP3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
21518. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
21519. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
21520. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
21521. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
21522. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
21523. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
21524. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
21525. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
21526. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
21527. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
21528. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
21529. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
21530. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
21531. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
21532. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
21533. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
21534. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
21535. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
21536. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
21537. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
21538. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
21539. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
21540. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
21541. BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
21542. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
21543. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
21544. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
21545. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
21546. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
21547. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
21548. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
21549. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
21550. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
21551. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
21552. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
21553. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
21554. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
21555. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
21556. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
21557. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
21558. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
21559. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
21560. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
21561. BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
21562. BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK
21563. BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT
21564. BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK
21565. BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT
21566. BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
21567. BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
21568. BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
21569. BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
21570. BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
21571. BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
21572. BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
21573. BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
21574. BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
21575. BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
21576. BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
21577. BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
21578. BIFP3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
21579. BIFP3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
21580. BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
21581. BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
21582. BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
21583. BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
21584. BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
21585. BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
21586. BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
21587. BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
21588. BIFP3_PCIEP_HPGI__REG_HPGI_HOOK_MASK
21589. BIFP3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
21590. BIFP3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
21591. BIFP3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
21592. BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK
21593. BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT
21594. BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK
21595. BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT
21596. BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK
21597. BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT
21598. BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK
21599. BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT
21600. BIFP3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
21601. BIFP3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
21602. BIFP3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
21603. BIFP3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
21604. BIFP3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
21605. BIFP3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
21606. BIFP3_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK
21607. BIFP3_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT
21608. BIFP3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
21609. BIFP3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
21610. BIFP3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
21611. BIFP3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
21612. BIFP3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
21613. BIFP3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
21614. BIFP3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
21615. BIFP3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
21616. BIFP3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
21617. BIFP3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
21618. BIFP3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
21619. BIFP3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
21620. BIFP3_PCIEP_RESERVED__PCIEP_RESERVED_MASK
21621. BIFP3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
21622. BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK
21623. BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT
21624. BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK
21625. BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT
21626. BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK
21627. BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT
21628. BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK
21629. BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT
21630. BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK
21631. BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT
21632. BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK
21633. BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT
21634. BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK
21635. BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT
21636. BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK
21637. BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT
21638. BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK
21639. BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT
21640. BIFP3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
21641. BIFP3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
21642. BIFP3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
21643. BIFP3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
21644. BIFP3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
21645. BIFP3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
21646. BIFP3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
21647. BIFP3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
21648. BIFP3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
21649. BIFP3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
21650. BIFP3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
21651. BIFP3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
21652. BIFP3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
21653. BIFP3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
21654. BIFP3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
21655. BIFP3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
21656. BIFP3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
21657. BIFP3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
21658. BIFP3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
21659. BIFP3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
21660. BIFP3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
21661. BIFP3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
21662. BIFP3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
21663. BIFP3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
21664. BIFP3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
21665. BIFP3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
21666. BIFP3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
21667. BIFP3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
21668. BIFP3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
21669. BIFP3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
21670. BIFP3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
21671. BIFP3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
21672. BIFP3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
21673. BIFP3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
21674. BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
21675. BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
21676. BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
21677. BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
21678. BIFP3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
21679. BIFP3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
21680. BIFP3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
21681. BIFP3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
21682. BIFP3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
21683. BIFP3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
21684. BIFP3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
21685. BIFP3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
21686. BIFP3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
21687. BIFP3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
21688. BIFP3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
21689. BIFP3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
21690. BIFP3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
21691. BIFP3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
21692. BIFP3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
21693. BIFP3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
21694. BIFP3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
21695. BIFP3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
21696. BIFP3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
21697. BIFP3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
21698. BIFP3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
21699. BIFP3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
21700. BIFP3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
21701. BIFP3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
21702. BIFP3_PCIE_FC_CPL__CPLD_CREDITS_MASK
21703. BIFP3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
21704. BIFP3_PCIE_FC_CPL__CPLH_CREDITS_MASK
21705. BIFP3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
21706. BIFP3_PCIE_FC_NP__NPD_CREDITS_MASK
21707. BIFP3_PCIE_FC_NP__NPD_CREDITS__SHIFT
21708. BIFP3_PCIE_FC_NP__NPH_CREDITS_MASK
21709. BIFP3_PCIE_FC_NP__NPH_CREDITS__SHIFT
21710. BIFP3_PCIE_FC_P__PD_CREDITS_MASK
21711. BIFP3_PCIE_FC_P__PD_CREDITS__SHIFT
21712. BIFP3_PCIE_FC_P__PH_CREDITS_MASK
21713. BIFP3_PCIE_FC_P__PH_CREDITS__SHIFT
21714. BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
21715. BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
21716. BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
21717. BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
21718. BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
21719. BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
21720. BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
21721. BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
21722. BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
21723. BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
21724. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
21725. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
21726. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
21727. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
21728. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
21729. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
21730. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
21731. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
21732. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
21733. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
21734. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
21735. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
21736. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
21737. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
21738. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
21739. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
21740. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
21741. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
21742. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
21743. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
21744. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK
21745. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT
21746. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
21747. BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
21748. BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
21749. BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
21750. BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
21751. BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
21752. BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
21753. BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
21754. BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
21755. BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
21756. BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
21757. BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
21758. BIFP3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
21759. BIFP3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
21760. BIFP3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
21761. BIFP3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
21762. BIFP3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
21763. BIFP3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
21764. BIFP3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
21765. BIFP3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
21766. BIFP3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
21767. BIFP3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
21768. BIFP3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
21769. BIFP3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
21770. BIFP3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
21771. BIFP3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
21772. BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
21773. BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
21774. BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
21775. BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
21776. BIFP3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
21777. BIFP3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
21778. BIFP3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
21779. BIFP3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
21780. BIFP3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
21781. BIFP3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
21782. BIFP3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
21783. BIFP3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
21784. BIFP3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
21785. BIFP3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
21786. BIFP3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
21787. BIFP3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
21788. BIFP3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
21789. BIFP3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
21790. BIFP3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
21791. BIFP3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
21792. BIFP3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
21793. BIFP3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
21794. BIFP3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
21795. BIFP3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
21796. BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
21797. BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
21798. BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
21799. BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
21800. BIFP3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
21801. BIFP3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
21802. BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
21803. BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
21804. BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
21805. BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
21806. BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
21807. BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
21808. BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
21809. BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
21810. BIFP3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
21811. BIFP3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
21812. BIFP3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
21813. BIFP3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
21814. BIFP3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
21815. BIFP3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
21816. BIFP3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
21817. BIFP3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
21818. BIFP3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
21819. BIFP3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
21820. BIFP3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
21821. BIFP3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
21822. BIFP3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
21823. BIFP3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
21824. BIFP3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
21825. BIFP3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
21826. BIFP3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
21827. BIFP3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
21828. BIFP3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
21829. BIFP3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
21830. BIFP3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
21831. BIFP3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
21832. BIFP3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
21833. BIFP3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
21834. BIFP3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
21835. BIFP3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
21836. BIFP3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
21837. BIFP3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
21838. BIFP3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
21839. BIFP3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
21840. BIFP3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
21841. BIFP3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
21842. BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
21843. BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
21844. BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
21845. BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
21846. BIFP3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
21847. BIFP3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
21848. BIFP3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
21849. BIFP3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
21850. BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
21851. BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
21852. BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
21853. BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
21854. BIFP3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
21855. BIFP3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
21856. BIFP3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
21857. BIFP3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
21858. BIFP3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
21859. BIFP3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
21860. BIFP3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
21861. BIFP3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
21862. BIFP3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
21863. BIFP3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
21864. BIFP3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
21865. BIFP3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
21866. BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
21867. BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
21868. BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
21869. BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
21870. BIFP3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
21871. BIFP3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
21872. BIFP3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
21873. BIFP3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
21874. BIFP3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
21875. BIFP3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
21876. BIFP3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
21877. BIFP3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
21878. BIFP3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
21879. BIFP3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
21880. BIFP3_PCIE_LC_CNTL4__LC_TX_SWING_MASK
21881. BIFP3_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT
21882. BIFP3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
21883. BIFP3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
21884. BIFP3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
21885. BIFP3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
21886. BIFP3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
21887. BIFP3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
21888. BIFP3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
21889. BIFP3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
21890. BIFP3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
21891. BIFP3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
21892. BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK
21893. BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK
21894. BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT
21895. BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT
21896. BIFP3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
21897. BIFP3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
21898. BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
21899. BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
21900. BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
21901. BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
21902. BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
21903. BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
21904. BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
21905. BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
21906. BIFP3_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK
21907. BIFP3_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT
21908. BIFP3_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK
21909. BIFP3_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT
21910. BIFP3_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK
21911. BIFP3_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT
21912. BIFP3_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK
21913. BIFP3_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT
21914. BIFP3_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK
21915. BIFP3_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT
21916. BIFP3_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK
21917. BIFP3_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT
21918. BIFP3_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK
21919. BIFP3_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT
21920. BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK
21921. BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT
21922. BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK
21923. BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT
21924. BIFP3_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK
21925. BIFP3_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT
21926. BIFP3_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK
21927. BIFP3_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT
21928. BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
21929. BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
21930. BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
21931. BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
21932. BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
21933. BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
21934. BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK
21935. BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT
21936. BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK
21937. BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT
21938. BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK
21939. BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT
21940. BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK
21941. BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT
21942. BIFP3_PCIE_LC_CNTL6__LC_SRIS_EN_MASK
21943. BIFP3_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT
21944. BIFP3_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK
21945. BIFP3_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT
21946. BIFP3_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK
21947. BIFP3_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT
21948. BIFP3_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK
21949. BIFP3_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT
21950. BIFP3_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK
21951. BIFP3_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT
21952. BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK
21953. BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT
21954. BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK
21955. BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT
21956. BIFP3_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK
21957. BIFP3_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT
21958. BIFP3_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK
21959. BIFP3_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT
21960. BIFP3_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK
21961. BIFP3_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT
21962. BIFP3_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK
21963. BIFP3_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT
21964. BIFP3_PCIE_LC_CNTL7__LC_FOM_TIME_MASK
21965. BIFP3_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT
21966. BIFP3_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK
21967. BIFP3_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT
21968. BIFP3_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK
21969. BIFP3_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT
21970. BIFP3_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK
21971. BIFP3_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT
21972. BIFP3_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK
21973. BIFP3_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT
21974. BIFP3_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK
21975. BIFP3_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT
21976. BIFP3_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK
21977. BIFP3_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT
21978. BIFP3_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK
21979. BIFP3_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT
21980. BIFP3_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK
21981. BIFP3_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT
21982. BIFP3_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK
21983. BIFP3_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT
21984. BIFP3_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK
21985. BIFP3_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT
21986. BIFP3_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK
21987. BIFP3_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT
21988. BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK
21989. BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT
21990. BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK
21991. BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT
21992. BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK
21993. BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT
21994. BIFP3_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK
21995. BIFP3_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT
21996. BIFP3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
21997. BIFP3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
21998. BIFP3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
21999. BIFP3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
22000. BIFP3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
22001. BIFP3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
22002. BIFP3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
22003. BIFP3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
22004. BIFP3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
22005. BIFP3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
22006. BIFP3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
22007. BIFP3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
22008. BIFP3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
22009. BIFP3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
22010. BIFP3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
22011. BIFP3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
22012. BIFP3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
22013. BIFP3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
22014. BIFP3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
22015. BIFP3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
22016. BIFP3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
22017. BIFP3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
22018. BIFP3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
22019. BIFP3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
22020. BIFP3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
22021. BIFP3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
22022. BIFP3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
22023. BIFP3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
22024. BIFP3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
22025. BIFP3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
22026. BIFP3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
22027. BIFP3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
22028. BIFP3_PCIE_LC_CNTL__LC_RESET_LINK_MASK
22029. BIFP3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
22030. BIFP3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
22031. BIFP3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
22032. BIFP3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
22033. BIFP3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
22034. BIFP3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
22035. BIFP3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
22036. BIFP3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
22037. BIFP3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
22038. BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
22039. BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
22040. BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
22041. BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
22042. BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
22043. BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
22044. BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
22045. BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
22046. BIFP3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
22047. BIFP3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
22048. BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
22049. BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
22050. BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
22051. BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
22052. BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
22053. BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
22054. BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
22055. BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
22056. BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
22057. BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
22058. BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
22059. BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
22060. BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK
22061. BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT
22062. BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK
22063. BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT
22064. BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK
22065. BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT
22066. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK
22067. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT
22068. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK
22069. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT
22070. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK
22071. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT
22072. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK
22073. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT
22074. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK
22075. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT
22076. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK
22077. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT
22078. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK
22079. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT
22080. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK
22081. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT
22082. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK
22083. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT
22084. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK
22085. BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT
22086. BIFP3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
22087. BIFP3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
22088. BIFP3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
22089. BIFP3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
22090. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
22091. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
22092. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK
22093. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT
22094. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
22095. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
22096. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
22097. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
22098. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
22099. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
22100. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
22101. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
22102. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
22103. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
22104. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
22105. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
22106. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
22107. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
22108. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
22109. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
22110. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
22111. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
22112. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
22113. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
22114. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
22115. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
22116. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
22117. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
22118. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
22119. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
22120. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
22121. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
22122. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
22123. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
22124. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
22125. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
22126. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK
22127. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT
22128. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
22129. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
22130. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
22131. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
22132. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
22133. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
22134. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
22135. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
22136. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
22137. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
22138. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
22139. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
22140. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
22141. BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
22142. BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
22143. BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
22144. BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
22145. BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
22146. BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK
22147. BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT
22148. BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
22149. BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
22150. BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
22151. BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
22152. BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
22153. BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
22154. BIFP3_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK
22155. BIFP3_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT
22156. BIFP3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
22157. BIFP3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
22158. BIFP3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
22159. BIFP3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
22160. BIFP3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
22161. BIFP3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
22162. BIFP3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
22163. BIFP3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
22164. BIFP3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
22165. BIFP3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
22166. BIFP3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
22167. BIFP3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
22168. BIFP3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
22169. BIFP3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
22170. BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
22171. BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
22172. BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
22173. BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
22174. BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
22175. BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
22176. BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
22177. BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
22178. BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
22179. BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
22180. BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
22181. BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
22182. BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
22183. BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
22184. BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
22185. BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
22186. BIFP3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
22187. BIFP3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
22188. BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
22189. BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
22190. BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
22191. BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
22192. BIFP3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
22193. BIFP3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
22194. BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
22195. BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
22196. BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
22197. BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
22198. BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
22199. BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
22200. BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
22201. BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
22202. BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
22203. BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
22204. BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
22205. BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
22206. BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
22207. BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
22208. BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
22209. BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
22210. BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
22211. BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
22212. BIFP3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
22213. BIFP3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
22214. BIFP3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
22215. BIFP3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
22216. BIFP3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
22217. BIFP3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
22218. BIFP3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
22219. BIFP3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
22220. BIFP3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
22221. BIFP3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
22222. BIFP3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
22223. BIFP3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
22224. BIFP3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
22225. BIFP3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
22226. BIFP3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
22227. BIFP3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
22228. BIFP3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
22229. BIFP3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
22230. BIFP3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
22231. BIFP3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
22232. BIFP3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
22233. BIFP3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
22234. BIFP3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
22235. BIFP3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
22236. BIFP3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
22237. BIFP3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
22238. BIFP3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
22239. BIFP3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
22240. BIFP3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
22241. BIFP3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
22242. BIFP3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
22243. BIFP3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
22244. BIFP3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
22245. BIFP3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
22246. BIFP3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
22247. BIFP3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
22248. BIFP3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
22249. BIFP3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
22250. BIFP3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
22251. BIFP3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
22252. BIFP3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
22253. BIFP3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
22254. BIFP3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
22255. BIFP3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
22256. BIFP3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
22257. BIFP3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
22258. BIFP3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
22259. BIFP3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
22260. BIFP3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
22261. BIFP3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
22262. BIFP3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
22263. BIFP3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
22264. BIFP3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
22265. BIFP3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
22266. BIFP3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
22267. BIFP3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
22268. BIFP3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
22269. BIFP3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
22270. BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
22271. BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
22272. BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
22273. BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
22274. BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
22275. BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
22276. BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
22277. BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
22278. BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
22279. BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
22280. BIFP3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
22281. BIFP3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
22282. BIFP3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
22283. BIFP3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
22284. BIFP3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
22285. BIFP3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
22286. BIFP3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
22287. BIFP3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
22288. BIFP3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
22289. BIFP3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
22290. BIFP3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
22291. BIFP3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
22292. BIFP3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
22293. BIFP3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
22294. BIFP3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
22295. BIFP3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
22296. BIFP3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
22297. BIFP3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
22298. BIFP3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
22299. BIFP3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
22300. BIFP3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
22301. BIFP3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
22302. BIFP3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
22303. BIFP3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
22304. BIFP3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
22305. BIFP3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
22306. BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
22307. BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
22308. BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
22309. BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
22310. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK
22311. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT
22312. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK
22313. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT
22314. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK
22315. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT
22316. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK
22317. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT
22318. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK
22319. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT
22320. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK
22321. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT
22322. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK
22323. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT
22324. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK
22325. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT
22326. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK
22327. BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT
22328. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK
22329. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT
22330. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK
22331. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT
22332. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK
22333. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT
22334. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK
22335. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT
22336. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK
22337. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT
22338. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK
22339. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK
22340. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT
22341. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT
22342. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK
22343. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT
22344. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK
22345. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT
22346. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK
22347. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT
22348. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK
22349. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT
22350. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK
22351. BIFP3_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT
22352. BIFP3_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK
22353. BIFP3_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT
22354. BIFP3_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK
22355. BIFP3_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT
22356. BIFP3_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK
22357. BIFP3_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT
22358. BIFP3_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK
22359. BIFP3_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT
22360. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK
22361. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT
22362. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK
22363. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT
22364. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK
22365. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT
22366. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK
22367. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT
22368. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK
22369. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
22370. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK
22371. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT
22372. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK
22373. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
22374. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK
22375. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT
22376. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK
22377. BIFP3_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT
22378. BIFP3_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK
22379. BIFP3_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT
22380. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK
22381. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT
22382. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK
22383. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT
22384. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK
22385. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT
22386. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK
22387. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT
22388. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK
22389. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT
22390. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK
22391. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT
22392. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK
22393. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT
22394. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK
22395. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT
22396. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK
22397. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
22398. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK
22399. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT
22400. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK
22401. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT
22402. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK
22403. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT
22404. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK
22405. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT
22406. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK
22407. BIFP3_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT
22408. BIFP3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
22409. BIFP3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
22410. BIFP3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
22411. BIFP3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
22412. BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
22413. BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
22414. BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
22415. BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
22416. BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
22417. BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
22418. BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
22419. BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
22420. BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
22421. BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
22422. BIFP3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
22423. BIFP3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
22424. BIFP3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
22425. BIFP3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
22426. BIFP3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
22427. BIFP3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
22428. BIFP3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
22429. BIFP3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
22430. BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
22431. BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
22432. BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
22433. BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
22434. BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
22435. BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
22436. BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
22437. BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
22438. BIFP3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
22439. BIFP3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
22440. BIFP3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
22441. BIFP3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
22442. BIFP3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
22443. BIFP3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
22444. BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
22445. BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
22446. BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
22447. BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
22448. BIFP3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
22449. BIFP3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
22450. BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
22451. BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
22452. BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
22453. BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
22454. BIFP3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
22455. BIFP3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
22456. BIFP3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
22457. BIFP3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
22458. BIFP3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
22459. BIFP3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
22460. BIFP3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
22461. BIFP3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
22462. BIFP3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
22463. BIFP3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
22464. BIFP3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
22465. BIFP3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
22466. BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
22467. BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
22468. BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
22469. BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
22470. BIFP3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
22471. BIFP3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
22472. BIFP3_PCIE_RX_CNTL__RX_TPH_DIS_MASK
22473. BIFP3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
22474. BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
22475. BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
22476. BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
22477. BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
22478. BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
22479. BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
22480. BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
22481. BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
22482. BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
22483. BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
22484. BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
22485. BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
22486. BIFP3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
22487. BIFP3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
22488. BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
22489. BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
22490. BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
22491. BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
22492. BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
22493. BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
22494. BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
22495. BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
22496. BIFP3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
22497. BIFP3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
22498. BIFP3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
22499. BIFP3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
22500. BIFP3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
22501. BIFP3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
22502. BIFP3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
22503. BIFP3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
22504. BIFP3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
22505. BIFP3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
22506. BIFP3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
22507. BIFP3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
22508. BIFP3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
22509. BIFP3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
22510. BIFP3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
22511. BIFP3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
22512. BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
22513. BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
22514. BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
22515. BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
22516. BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
22517. BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
22518. BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
22519. BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
22520. BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
22521. BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
22522. BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
22523. BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
22524. BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
22525. BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
22526. BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
22527. BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
22528. BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
22529. BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
22530. BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
22531. BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
22532. BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
22533. BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
22534. BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
22535. BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
22536. BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
22537. BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
22538. BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
22539. BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
22540. BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
22541. BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
22542. BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
22543. BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
22544. BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
22545. BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
22546. BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
22547. BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
22548. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
22549. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
22550. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
22551. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
22552. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
22553. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
22554. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
22555. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
22556. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
22557. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
22558. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
22559. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
22560. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
22561. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
22562. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
22563. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
22564. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
22565. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
22566. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
22567. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
22568. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
22569. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
22570. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
22571. BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
22572. BIFP3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
22573. BIFP3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
22574. BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
22575. BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
22576. BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
22577. BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
22578. BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
22579. BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
22580. BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
22581. BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
22582. BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
22583. BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
22584. BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
22585. BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
22586. BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
22587. BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
22588. BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
22589. BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
22590. BIFP3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
22591. BIFP3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
22592. BIFP3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
22593. BIFP3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
22594. BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
22595. BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
22596. BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
22597. BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
22598. BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
22599. BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
22600. BIFP4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
22601. BIFP4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
22602. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
22603. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
22604. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
22605. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
22606. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
22607. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
22608. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
22609. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
22610. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
22611. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
22612. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
22613. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
22614. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
22615. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
22616. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
22617. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
22618. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
22619. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
22620. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
22621. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
22622. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
22623. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
22624. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
22625. BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
22626. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
22627. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
22628. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
22629. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
22630. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
22631. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
22632. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
22633. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
22634. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
22635. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
22636. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
22637. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
22638. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
22639. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
22640. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
22641. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
22642. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
22643. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
22644. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
22645. BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
22646. BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK
22647. BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT
22648. BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK
22649. BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT
22650. BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
22651. BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
22652. BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
22653. BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
22654. BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
22655. BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
22656. BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
22657. BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
22658. BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
22659. BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
22660. BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
22661. BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
22662. BIFP4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
22663. BIFP4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
22664. BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
22665. BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
22666. BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
22667. BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
22668. BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
22669. BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
22670. BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
22671. BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
22672. BIFP4_PCIEP_HPGI__REG_HPGI_HOOK_MASK
22673. BIFP4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
22674. BIFP4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
22675. BIFP4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
22676. BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK
22677. BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT
22678. BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK
22679. BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT
22680. BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK
22681. BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT
22682. BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK
22683. BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT
22684. BIFP4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
22685. BIFP4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
22686. BIFP4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
22687. BIFP4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
22688. BIFP4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
22689. BIFP4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
22690. BIFP4_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK
22691. BIFP4_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT
22692. BIFP4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
22693. BIFP4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
22694. BIFP4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
22695. BIFP4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
22696. BIFP4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
22697. BIFP4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
22698. BIFP4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
22699. BIFP4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
22700. BIFP4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
22701. BIFP4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
22702. BIFP4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
22703. BIFP4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
22704. BIFP4_PCIEP_RESERVED__PCIEP_RESERVED_MASK
22705. BIFP4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
22706. BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK
22707. BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT
22708. BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK
22709. BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT
22710. BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK
22711. BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT
22712. BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK
22713. BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT
22714. BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK
22715. BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT
22716. BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK
22717. BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT
22718. BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK
22719. BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT
22720. BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK
22721. BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT
22722. BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK
22723. BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT
22724. BIFP4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
22725. BIFP4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
22726. BIFP4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
22727. BIFP4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
22728. BIFP4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
22729. BIFP4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
22730. BIFP4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
22731. BIFP4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
22732. BIFP4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
22733. BIFP4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
22734. BIFP4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
22735. BIFP4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
22736. BIFP4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
22737. BIFP4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
22738. BIFP4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
22739. BIFP4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
22740. BIFP4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
22741. BIFP4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
22742. BIFP4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
22743. BIFP4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
22744. BIFP4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
22745. BIFP4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
22746. BIFP4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
22747. BIFP4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
22748. BIFP4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
22749. BIFP4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
22750. BIFP4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
22751. BIFP4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
22752. BIFP4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
22753. BIFP4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
22754. BIFP4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
22755. BIFP4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
22756. BIFP4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
22757. BIFP4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
22758. BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
22759. BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
22760. BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
22761. BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
22762. BIFP4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
22763. BIFP4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
22764. BIFP4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
22765. BIFP4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
22766. BIFP4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
22767. BIFP4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
22768. BIFP4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
22769. BIFP4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
22770. BIFP4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
22771. BIFP4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
22772. BIFP4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
22773. BIFP4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
22774. BIFP4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
22775. BIFP4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
22776. BIFP4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
22777. BIFP4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
22778. BIFP4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
22779. BIFP4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
22780. BIFP4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
22781. BIFP4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
22782. BIFP4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
22783. BIFP4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
22784. BIFP4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
22785. BIFP4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
22786. BIFP4_PCIE_FC_CPL__CPLD_CREDITS_MASK
22787. BIFP4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
22788. BIFP4_PCIE_FC_CPL__CPLH_CREDITS_MASK
22789. BIFP4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
22790. BIFP4_PCIE_FC_NP__NPD_CREDITS_MASK
22791. BIFP4_PCIE_FC_NP__NPD_CREDITS__SHIFT
22792. BIFP4_PCIE_FC_NP__NPH_CREDITS_MASK
22793. BIFP4_PCIE_FC_NP__NPH_CREDITS__SHIFT
22794. BIFP4_PCIE_FC_P__PD_CREDITS_MASK
22795. BIFP4_PCIE_FC_P__PD_CREDITS__SHIFT
22796. BIFP4_PCIE_FC_P__PH_CREDITS_MASK
22797. BIFP4_PCIE_FC_P__PH_CREDITS__SHIFT
22798. BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
22799. BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
22800. BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
22801. BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
22802. BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
22803. BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
22804. BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
22805. BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
22806. BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
22807. BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
22808. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
22809. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
22810. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
22811. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
22812. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
22813. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
22814. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
22815. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
22816. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
22817. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
22818. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
22819. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
22820. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
22821. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
22822. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
22823. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
22824. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
22825. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
22826. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
22827. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
22828. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK
22829. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT
22830. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
22831. BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
22832. BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
22833. BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
22834. BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
22835. BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
22836. BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
22837. BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
22838. BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
22839. BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
22840. BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
22841. BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
22842. BIFP4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
22843. BIFP4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
22844. BIFP4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
22845. BIFP4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
22846. BIFP4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
22847. BIFP4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
22848. BIFP4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
22849. BIFP4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
22850. BIFP4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
22851. BIFP4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
22852. BIFP4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
22853. BIFP4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
22854. BIFP4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
22855. BIFP4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
22856. BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
22857. BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
22858. BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
22859. BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
22860. BIFP4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
22861. BIFP4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
22862. BIFP4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
22863. BIFP4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
22864. BIFP4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
22865. BIFP4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
22866. BIFP4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
22867. BIFP4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
22868. BIFP4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
22869. BIFP4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
22870. BIFP4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
22871. BIFP4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
22872. BIFP4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
22873. BIFP4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
22874. BIFP4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
22875. BIFP4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
22876. BIFP4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
22877. BIFP4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
22878. BIFP4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
22879. BIFP4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
22880. BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
22881. BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
22882. BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
22883. BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
22884. BIFP4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
22885. BIFP4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
22886. BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
22887. BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
22888. BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
22889. BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
22890. BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
22891. BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
22892. BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
22893. BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
22894. BIFP4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
22895. BIFP4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
22896. BIFP4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
22897. BIFP4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
22898. BIFP4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
22899. BIFP4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
22900. BIFP4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
22901. BIFP4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
22902. BIFP4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
22903. BIFP4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
22904. BIFP4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
22905. BIFP4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
22906. BIFP4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
22907. BIFP4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
22908. BIFP4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
22909. BIFP4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
22910. BIFP4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
22911. BIFP4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
22912. BIFP4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
22913. BIFP4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
22914. BIFP4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
22915. BIFP4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
22916. BIFP4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
22917. BIFP4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
22918. BIFP4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
22919. BIFP4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
22920. BIFP4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
22921. BIFP4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
22922. BIFP4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
22923. BIFP4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
22924. BIFP4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
22925. BIFP4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
22926. BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
22927. BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
22928. BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
22929. BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
22930. BIFP4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
22931. BIFP4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
22932. BIFP4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
22933. BIFP4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
22934. BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
22935. BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
22936. BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
22937. BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
22938. BIFP4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
22939. BIFP4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
22940. BIFP4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
22941. BIFP4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
22942. BIFP4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
22943. BIFP4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
22944. BIFP4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
22945. BIFP4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
22946. BIFP4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
22947. BIFP4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
22948. BIFP4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
22949. BIFP4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
22950. BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
22951. BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
22952. BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
22953. BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
22954. BIFP4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
22955. BIFP4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
22956. BIFP4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
22957. BIFP4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
22958. BIFP4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
22959. BIFP4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
22960. BIFP4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
22961. BIFP4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
22962. BIFP4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
22963. BIFP4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
22964. BIFP4_PCIE_LC_CNTL4__LC_TX_SWING_MASK
22965. BIFP4_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT
22966. BIFP4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
22967. BIFP4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
22968. BIFP4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
22969. BIFP4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
22970. BIFP4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
22971. BIFP4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
22972. BIFP4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
22973. BIFP4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
22974. BIFP4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
22975. BIFP4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
22976. BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK
22977. BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK
22978. BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT
22979. BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT
22980. BIFP4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
22981. BIFP4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
22982. BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
22983. BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
22984. BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
22985. BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
22986. BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
22987. BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
22988. BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
22989. BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
22990. BIFP4_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK
22991. BIFP4_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT
22992. BIFP4_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK
22993. BIFP4_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT
22994. BIFP4_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK
22995. BIFP4_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT
22996. BIFP4_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK
22997. BIFP4_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT
22998. BIFP4_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK
22999. BIFP4_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT
23000. BIFP4_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK
23001. BIFP4_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT
23002. BIFP4_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK
23003. BIFP4_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT
23004. BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK
23005. BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT
23006. BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK
23007. BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT
23008. BIFP4_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK
23009. BIFP4_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT
23010. BIFP4_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK
23011. BIFP4_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT
23012. BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
23013. BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
23014. BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
23015. BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
23016. BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
23017. BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
23018. BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK
23019. BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT
23020. BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK
23021. BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT
23022. BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK
23023. BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT
23024. BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK
23025. BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT
23026. BIFP4_PCIE_LC_CNTL6__LC_SRIS_EN_MASK
23027. BIFP4_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT
23028. BIFP4_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK
23029. BIFP4_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT
23030. BIFP4_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK
23031. BIFP4_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT
23032. BIFP4_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK
23033. BIFP4_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT
23034. BIFP4_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK
23035. BIFP4_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT
23036. BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK
23037. BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT
23038. BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK
23039. BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT
23040. BIFP4_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK
23041. BIFP4_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT
23042. BIFP4_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK
23043. BIFP4_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT
23044. BIFP4_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK
23045. BIFP4_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT
23046. BIFP4_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK
23047. BIFP4_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT
23048. BIFP4_PCIE_LC_CNTL7__LC_FOM_TIME_MASK
23049. BIFP4_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT
23050. BIFP4_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK
23051. BIFP4_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT
23052. BIFP4_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK
23053. BIFP4_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT
23054. BIFP4_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK
23055. BIFP4_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT
23056. BIFP4_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK
23057. BIFP4_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT
23058. BIFP4_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK
23059. BIFP4_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT
23060. BIFP4_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK
23061. BIFP4_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT
23062. BIFP4_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK
23063. BIFP4_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT
23064. BIFP4_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK
23065. BIFP4_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT
23066. BIFP4_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK
23067. BIFP4_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT
23068. BIFP4_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK
23069. BIFP4_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT
23070. BIFP4_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK
23071. BIFP4_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT
23072. BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK
23073. BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT
23074. BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK
23075. BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT
23076. BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK
23077. BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT
23078. BIFP4_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK
23079. BIFP4_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT
23080. BIFP4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
23081. BIFP4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
23082. BIFP4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
23083. BIFP4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
23084. BIFP4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
23085. BIFP4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
23086. BIFP4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
23087. BIFP4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
23088. BIFP4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
23089. BIFP4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
23090. BIFP4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
23091. BIFP4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
23092. BIFP4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
23093. BIFP4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
23094. BIFP4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
23095. BIFP4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
23096. BIFP4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
23097. BIFP4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
23098. BIFP4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
23099. BIFP4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
23100. BIFP4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
23101. BIFP4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
23102. BIFP4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
23103. BIFP4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
23104. BIFP4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
23105. BIFP4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
23106. BIFP4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
23107. BIFP4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
23108. BIFP4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
23109. BIFP4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
23110. BIFP4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
23111. BIFP4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
23112. BIFP4_PCIE_LC_CNTL__LC_RESET_LINK_MASK
23113. BIFP4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
23114. BIFP4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
23115. BIFP4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
23116. BIFP4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
23117. BIFP4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
23118. BIFP4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
23119. BIFP4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
23120. BIFP4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
23121. BIFP4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
23122. BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
23123. BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
23124. BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
23125. BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
23126. BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
23127. BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
23128. BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
23129. BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
23130. BIFP4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
23131. BIFP4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
23132. BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
23133. BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
23134. BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
23135. BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
23136. BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
23137. BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
23138. BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
23139. BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
23140. BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
23141. BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
23142. BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
23143. BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
23144. BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK
23145. BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT
23146. BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK
23147. BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT
23148. BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK
23149. BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT
23150. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK
23151. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT
23152. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK
23153. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT
23154. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK
23155. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT
23156. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK
23157. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT
23158. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK
23159. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT
23160. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK
23161. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT
23162. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK
23163. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT
23164. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK
23165. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT
23166. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK
23167. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT
23168. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK
23169. BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT
23170. BIFP4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
23171. BIFP4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
23172. BIFP4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
23173. BIFP4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
23174. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
23175. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
23176. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK
23177. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT
23178. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
23179. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
23180. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
23181. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
23182. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
23183. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
23184. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
23185. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
23186. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
23187. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
23188. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
23189. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
23190. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
23191. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
23192. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
23193. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
23194. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
23195. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
23196. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
23197. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
23198. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
23199. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
23200. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
23201. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
23202. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
23203. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
23204. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
23205. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
23206. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
23207. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
23208. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
23209. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
23210. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK
23211. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT
23212. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
23213. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
23214. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
23215. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
23216. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
23217. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
23218. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
23219. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
23220. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
23221. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
23222. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
23223. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
23224. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
23225. BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
23226. BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
23227. BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
23228. BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
23229. BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
23230. BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK
23231. BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT
23232. BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
23233. BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
23234. BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
23235. BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
23236. BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
23237. BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
23238. BIFP4_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK
23239. BIFP4_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT
23240. BIFP4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
23241. BIFP4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
23242. BIFP4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
23243. BIFP4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
23244. BIFP4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
23245. BIFP4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
23246. BIFP4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
23247. BIFP4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
23248. BIFP4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
23249. BIFP4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
23250. BIFP4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
23251. BIFP4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
23252. BIFP4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
23253. BIFP4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
23254. BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
23255. BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
23256. BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
23257. BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
23258. BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
23259. BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
23260. BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
23261. BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
23262. BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
23263. BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
23264. BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
23265. BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
23266. BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
23267. BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
23268. BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
23269. BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
23270. BIFP4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
23271. BIFP4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
23272. BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
23273. BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
23274. BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
23275. BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
23276. BIFP4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
23277. BIFP4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
23278. BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
23279. BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
23280. BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
23281. BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
23282. BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
23283. BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
23284. BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
23285. BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
23286. BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
23287. BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
23288. BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
23289. BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
23290. BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
23291. BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
23292. BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
23293. BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
23294. BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
23295. BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
23296. BIFP4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
23297. BIFP4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
23298. BIFP4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
23299. BIFP4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
23300. BIFP4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
23301. BIFP4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
23302. BIFP4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
23303. BIFP4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
23304. BIFP4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
23305. BIFP4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
23306. BIFP4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
23307. BIFP4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
23308. BIFP4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
23309. BIFP4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
23310. BIFP4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
23311. BIFP4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
23312. BIFP4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
23313. BIFP4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
23314. BIFP4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
23315. BIFP4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
23316. BIFP4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
23317. BIFP4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
23318. BIFP4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
23319. BIFP4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
23320. BIFP4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
23321. BIFP4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
23322. BIFP4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
23323. BIFP4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
23324. BIFP4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
23325. BIFP4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
23326. BIFP4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
23327. BIFP4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
23328. BIFP4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
23329. BIFP4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
23330. BIFP4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
23331. BIFP4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
23332. BIFP4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
23333. BIFP4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
23334. BIFP4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
23335. BIFP4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
23336. BIFP4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
23337. BIFP4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
23338. BIFP4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
23339. BIFP4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
23340. BIFP4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
23341. BIFP4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
23342. BIFP4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
23343. BIFP4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
23344. BIFP4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
23345. BIFP4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
23346. BIFP4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
23347. BIFP4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
23348. BIFP4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
23349. BIFP4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
23350. BIFP4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
23351. BIFP4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
23352. BIFP4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
23353. BIFP4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
23354. BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
23355. BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
23356. BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
23357. BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
23358. BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
23359. BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
23360. BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
23361. BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
23362. BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
23363. BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
23364. BIFP4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
23365. BIFP4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
23366. BIFP4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
23367. BIFP4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
23368. BIFP4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
23369. BIFP4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
23370. BIFP4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
23371. BIFP4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
23372. BIFP4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
23373. BIFP4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
23374. BIFP4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
23375. BIFP4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
23376. BIFP4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
23377. BIFP4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
23378. BIFP4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
23379. BIFP4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
23380. BIFP4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
23381. BIFP4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
23382. BIFP4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
23383. BIFP4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
23384. BIFP4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
23385. BIFP4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
23386. BIFP4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
23387. BIFP4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
23388. BIFP4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
23389. BIFP4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
23390. BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
23391. BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
23392. BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
23393. BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
23394. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK
23395. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT
23396. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK
23397. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT
23398. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK
23399. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT
23400. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK
23401. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT
23402. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK
23403. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT
23404. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK
23405. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT
23406. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK
23407. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT
23408. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK
23409. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT
23410. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK
23411. BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT
23412. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK
23413. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT
23414. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK
23415. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT
23416. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK
23417. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT
23418. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK
23419. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT
23420. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK
23421. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT
23422. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK
23423. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK
23424. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT
23425. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT
23426. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK
23427. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT
23428. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK
23429. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT
23430. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK
23431. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT
23432. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK
23433. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT
23434. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK
23435. BIFP4_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT
23436. BIFP4_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK
23437. BIFP4_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT
23438. BIFP4_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK
23439. BIFP4_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT
23440. BIFP4_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK
23441. BIFP4_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT
23442. BIFP4_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK
23443. BIFP4_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT
23444. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK
23445. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT
23446. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK
23447. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT
23448. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK
23449. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT
23450. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK
23451. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT
23452. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK
23453. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
23454. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK
23455. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT
23456. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK
23457. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
23458. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK
23459. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT
23460. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK
23461. BIFP4_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT
23462. BIFP4_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK
23463. BIFP4_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT
23464. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK
23465. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT
23466. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK
23467. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT
23468. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK
23469. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT
23470. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK
23471. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT
23472. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK
23473. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT
23474. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK
23475. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT
23476. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK
23477. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT
23478. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK
23479. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT
23480. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK
23481. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
23482. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK
23483. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT
23484. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK
23485. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT
23486. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK
23487. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT
23488. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK
23489. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT
23490. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK
23491. BIFP4_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT
23492. BIFP4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
23493. BIFP4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
23494. BIFP4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
23495. BIFP4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
23496. BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
23497. BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
23498. BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
23499. BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
23500. BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
23501. BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
23502. BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
23503. BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
23504. BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
23505. BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
23506. BIFP4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
23507. BIFP4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
23508. BIFP4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
23509. BIFP4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
23510. BIFP4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
23511. BIFP4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
23512. BIFP4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
23513. BIFP4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
23514. BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
23515. BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
23516. BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
23517. BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
23518. BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
23519. BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
23520. BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
23521. BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
23522. BIFP4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
23523. BIFP4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
23524. BIFP4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
23525. BIFP4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
23526. BIFP4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
23527. BIFP4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
23528. BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
23529. BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
23530. BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
23531. BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
23532. BIFP4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
23533. BIFP4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
23534. BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
23535. BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
23536. BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
23537. BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
23538. BIFP4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
23539. BIFP4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
23540. BIFP4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
23541. BIFP4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
23542. BIFP4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
23543. BIFP4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
23544. BIFP4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
23545. BIFP4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
23546. BIFP4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
23547. BIFP4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
23548. BIFP4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
23549. BIFP4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
23550. BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
23551. BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
23552. BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
23553. BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
23554. BIFP4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
23555. BIFP4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
23556. BIFP4_PCIE_RX_CNTL__RX_TPH_DIS_MASK
23557. BIFP4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
23558. BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
23559. BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
23560. BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
23561. BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
23562. BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
23563. BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
23564. BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
23565. BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
23566. BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
23567. BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
23568. BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
23569. BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
23570. BIFP4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
23571. BIFP4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
23572. BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
23573. BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
23574. BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
23575. BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
23576. BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
23577. BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
23578. BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
23579. BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
23580. BIFP4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
23581. BIFP4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
23582. BIFP4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
23583. BIFP4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
23584. BIFP4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
23585. BIFP4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
23586. BIFP4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
23587. BIFP4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
23588. BIFP4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
23589. BIFP4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
23590. BIFP4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
23591. BIFP4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
23592. BIFP4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
23593. BIFP4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
23594. BIFP4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
23595. BIFP4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
23596. BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
23597. BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
23598. BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
23599. BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
23600. BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
23601. BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
23602. BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
23603. BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
23604. BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
23605. BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
23606. BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
23607. BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
23608. BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
23609. BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
23610. BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
23611. BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
23612. BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
23613. BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
23614. BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
23615. BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
23616. BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
23617. BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
23618. BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
23619. BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
23620. BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
23621. BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
23622. BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
23623. BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
23624. BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
23625. BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
23626. BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
23627. BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
23628. BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
23629. BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
23630. BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
23631. BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
23632. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
23633. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
23634. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
23635. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
23636. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
23637. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
23638. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
23639. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
23640. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
23641. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
23642. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
23643. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
23644. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
23645. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
23646. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
23647. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
23648. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
23649. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
23650. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
23651. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
23652. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
23653. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
23654. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
23655. BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
23656. BIFP4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
23657. BIFP4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
23658. BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
23659. BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
23660. BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
23661. BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
23662. BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
23663. BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
23664. BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
23665. BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
23666. BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
23667. BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
23668. BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
23669. BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
23670. BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
23671. BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
23672. BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
23673. BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
23674. BIFP4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
23675. BIFP4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
23676. BIFP4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
23677. BIFP4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
23678. BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
23679. BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
23680. BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
23681. BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
23682. BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
23683. BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
23684. BIFP5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
23685. BIFP5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
23686. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
23687. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
23688. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
23689. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
23690. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
23691. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
23692. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
23693. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
23694. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
23695. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
23696. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
23697. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
23698. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
23699. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
23700. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
23701. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
23702. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
23703. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
23704. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
23705. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
23706. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
23707. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
23708. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
23709. BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
23710. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
23711. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
23712. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
23713. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
23714. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
23715. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
23716. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
23717. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
23718. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
23719. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
23720. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
23721. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
23722. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
23723. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
23724. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
23725. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
23726. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
23727. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
23728. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
23729. BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
23730. BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK
23731. BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT
23732. BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK
23733. BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT
23734. BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
23735. BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
23736. BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
23737. BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
23738. BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
23739. BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
23740. BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
23741. BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
23742. BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
23743. BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
23744. BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
23745. BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
23746. BIFP5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
23747. BIFP5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
23748. BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
23749. BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
23750. BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
23751. BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
23752. BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
23753. BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
23754. BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
23755. BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
23756. BIFP5_PCIEP_HPGI__REG_HPGI_HOOK_MASK
23757. BIFP5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
23758. BIFP5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
23759. BIFP5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
23760. BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK
23761. BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT
23762. BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK
23763. BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT
23764. BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK
23765. BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT
23766. BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK
23767. BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT
23768. BIFP5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
23769. BIFP5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
23770. BIFP5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
23771. BIFP5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
23772. BIFP5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
23773. BIFP5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
23774. BIFP5_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK
23775. BIFP5_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT
23776. BIFP5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
23777. BIFP5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
23778. BIFP5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
23779. BIFP5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
23780. BIFP5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
23781. BIFP5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
23782. BIFP5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
23783. BIFP5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
23784. BIFP5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
23785. BIFP5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
23786. BIFP5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
23787. BIFP5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
23788. BIFP5_PCIEP_RESERVED__PCIEP_RESERVED_MASK
23789. BIFP5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
23790. BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK
23791. BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT
23792. BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK
23793. BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT
23794. BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK
23795. BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT
23796. BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK
23797. BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT
23798. BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK
23799. BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT
23800. BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK
23801. BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT
23802. BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK
23803. BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT
23804. BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK
23805. BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT
23806. BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK
23807. BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT
23808. BIFP5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
23809. BIFP5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
23810. BIFP5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
23811. BIFP5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
23812. BIFP5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
23813. BIFP5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
23814. BIFP5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
23815. BIFP5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
23816. BIFP5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
23817. BIFP5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
23818. BIFP5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
23819. BIFP5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
23820. BIFP5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
23821. BIFP5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
23822. BIFP5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
23823. BIFP5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
23824. BIFP5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
23825. BIFP5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
23826. BIFP5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
23827. BIFP5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
23828. BIFP5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
23829. BIFP5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
23830. BIFP5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
23831. BIFP5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
23832. BIFP5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
23833. BIFP5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
23834. BIFP5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
23835. BIFP5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
23836. BIFP5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
23837. BIFP5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
23838. BIFP5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
23839. BIFP5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
23840. BIFP5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
23841. BIFP5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
23842. BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
23843. BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
23844. BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
23845. BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
23846. BIFP5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
23847. BIFP5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
23848. BIFP5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
23849. BIFP5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
23850. BIFP5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
23851. BIFP5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
23852. BIFP5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
23853. BIFP5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
23854. BIFP5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
23855. BIFP5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
23856. BIFP5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
23857. BIFP5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
23858. BIFP5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
23859. BIFP5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
23860. BIFP5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
23861. BIFP5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
23862. BIFP5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
23863. BIFP5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
23864. BIFP5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
23865. BIFP5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
23866. BIFP5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
23867. BIFP5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
23868. BIFP5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
23869. BIFP5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
23870. BIFP5_PCIE_FC_CPL__CPLD_CREDITS_MASK
23871. BIFP5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
23872. BIFP5_PCIE_FC_CPL__CPLH_CREDITS_MASK
23873. BIFP5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
23874. BIFP5_PCIE_FC_NP__NPD_CREDITS_MASK
23875. BIFP5_PCIE_FC_NP__NPD_CREDITS__SHIFT
23876. BIFP5_PCIE_FC_NP__NPH_CREDITS_MASK
23877. BIFP5_PCIE_FC_NP__NPH_CREDITS__SHIFT
23878. BIFP5_PCIE_FC_P__PD_CREDITS_MASK
23879. BIFP5_PCIE_FC_P__PD_CREDITS__SHIFT
23880. BIFP5_PCIE_FC_P__PH_CREDITS_MASK
23881. BIFP5_PCIE_FC_P__PH_CREDITS__SHIFT
23882. BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
23883. BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
23884. BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
23885. BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
23886. BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
23887. BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
23888. BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
23889. BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
23890. BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
23891. BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
23892. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
23893. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
23894. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
23895. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
23896. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
23897. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
23898. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
23899. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
23900. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
23901. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
23902. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
23903. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
23904. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
23905. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
23906. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
23907. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
23908. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
23909. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
23910. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
23911. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
23912. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK
23913. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT
23914. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
23915. BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
23916. BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
23917. BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
23918. BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
23919. BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
23920. BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
23921. BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
23922. BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
23923. BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
23924. BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
23925. BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
23926. BIFP5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
23927. BIFP5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
23928. BIFP5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
23929. BIFP5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
23930. BIFP5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
23931. BIFP5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
23932. BIFP5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
23933. BIFP5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
23934. BIFP5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
23935. BIFP5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
23936. BIFP5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
23937. BIFP5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
23938. BIFP5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
23939. BIFP5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
23940. BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
23941. BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
23942. BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
23943. BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
23944. BIFP5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
23945. BIFP5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
23946. BIFP5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
23947. BIFP5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
23948. BIFP5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
23949. BIFP5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
23950. BIFP5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
23951. BIFP5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
23952. BIFP5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
23953. BIFP5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
23954. BIFP5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
23955. BIFP5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
23956. BIFP5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
23957. BIFP5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
23958. BIFP5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
23959. BIFP5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
23960. BIFP5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
23961. BIFP5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
23962. BIFP5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
23963. BIFP5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
23964. BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
23965. BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
23966. BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
23967. BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
23968. BIFP5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
23969. BIFP5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
23970. BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
23971. BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
23972. BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
23973. BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
23974. BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
23975. BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
23976. BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
23977. BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
23978. BIFP5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
23979. BIFP5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
23980. BIFP5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
23981. BIFP5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
23982. BIFP5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
23983. BIFP5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
23984. BIFP5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
23985. BIFP5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
23986. BIFP5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
23987. BIFP5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
23988. BIFP5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
23989. BIFP5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
23990. BIFP5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
23991. BIFP5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
23992. BIFP5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
23993. BIFP5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
23994. BIFP5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
23995. BIFP5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
23996. BIFP5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
23997. BIFP5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
23998. BIFP5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
23999. BIFP5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
24000. BIFP5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
24001. BIFP5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
24002. BIFP5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
24003. BIFP5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
24004. BIFP5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
24005. BIFP5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
24006. BIFP5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
24007. BIFP5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
24008. BIFP5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
24009. BIFP5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
24010. BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
24011. BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
24012. BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
24013. BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
24014. BIFP5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
24015. BIFP5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
24016. BIFP5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
24017. BIFP5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
24018. BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
24019. BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
24020. BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
24021. BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
24022. BIFP5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
24023. BIFP5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
24024. BIFP5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
24025. BIFP5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
24026. BIFP5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
24027. BIFP5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
24028. BIFP5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
24029. BIFP5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
24030. BIFP5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
24031. BIFP5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
24032. BIFP5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
24033. BIFP5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
24034. BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
24035. BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
24036. BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
24037. BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
24038. BIFP5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
24039. BIFP5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
24040. BIFP5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
24041. BIFP5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
24042. BIFP5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
24043. BIFP5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
24044. BIFP5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
24045. BIFP5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
24046. BIFP5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
24047. BIFP5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
24048. BIFP5_PCIE_LC_CNTL4__LC_TX_SWING_MASK
24049. BIFP5_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT
24050. BIFP5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
24051. BIFP5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
24052. BIFP5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
24053. BIFP5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
24054. BIFP5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
24055. BIFP5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
24056. BIFP5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
24057. BIFP5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
24058. BIFP5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
24059. BIFP5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
24060. BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK
24061. BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK
24062. BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT
24063. BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT
24064. BIFP5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
24065. BIFP5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
24066. BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
24067. BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
24068. BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
24069. BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
24070. BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
24071. BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
24072. BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
24073. BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
24074. BIFP5_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK
24075. BIFP5_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT
24076. BIFP5_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK
24077. BIFP5_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT
24078. BIFP5_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK
24079. BIFP5_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT
24080. BIFP5_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK
24081. BIFP5_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT
24082. BIFP5_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK
24083. BIFP5_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT
24084. BIFP5_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK
24085. BIFP5_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT
24086. BIFP5_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK
24087. BIFP5_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT
24088. BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK
24089. BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT
24090. BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK
24091. BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT
24092. BIFP5_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK
24093. BIFP5_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT
24094. BIFP5_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK
24095. BIFP5_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT
24096. BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
24097. BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
24098. BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
24099. BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
24100. BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
24101. BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
24102. BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK
24103. BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT
24104. BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK
24105. BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT
24106. BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK
24107. BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT
24108. BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK
24109. BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT
24110. BIFP5_PCIE_LC_CNTL6__LC_SRIS_EN_MASK
24111. BIFP5_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT
24112. BIFP5_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK
24113. BIFP5_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT
24114. BIFP5_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK
24115. BIFP5_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT
24116. BIFP5_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK
24117. BIFP5_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT
24118. BIFP5_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK
24119. BIFP5_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT
24120. BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK
24121. BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT
24122. BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK
24123. BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT
24124. BIFP5_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK
24125. BIFP5_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT
24126. BIFP5_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK
24127. BIFP5_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT
24128. BIFP5_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK
24129. BIFP5_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT
24130. BIFP5_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK
24131. BIFP5_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT
24132. BIFP5_PCIE_LC_CNTL7__LC_FOM_TIME_MASK
24133. BIFP5_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT
24134. BIFP5_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK
24135. BIFP5_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT
24136. BIFP5_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK
24137. BIFP5_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT
24138. BIFP5_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK
24139. BIFP5_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT
24140. BIFP5_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK
24141. BIFP5_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT
24142. BIFP5_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK
24143. BIFP5_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT
24144. BIFP5_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK
24145. BIFP5_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT
24146. BIFP5_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK
24147. BIFP5_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT
24148. BIFP5_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK
24149. BIFP5_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT
24150. BIFP5_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK
24151. BIFP5_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT
24152. BIFP5_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK
24153. BIFP5_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT
24154. BIFP5_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK
24155. BIFP5_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT
24156. BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK
24157. BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT
24158. BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK
24159. BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT
24160. BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK
24161. BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT
24162. BIFP5_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK
24163. BIFP5_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT
24164. BIFP5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
24165. BIFP5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
24166. BIFP5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
24167. BIFP5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
24168. BIFP5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
24169. BIFP5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
24170. BIFP5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
24171. BIFP5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
24172. BIFP5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
24173. BIFP5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
24174. BIFP5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
24175. BIFP5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
24176. BIFP5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
24177. BIFP5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
24178. BIFP5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
24179. BIFP5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
24180. BIFP5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
24181. BIFP5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
24182. BIFP5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
24183. BIFP5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
24184. BIFP5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
24185. BIFP5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
24186. BIFP5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
24187. BIFP5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
24188. BIFP5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
24189. BIFP5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
24190. BIFP5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
24191. BIFP5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
24192. BIFP5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
24193. BIFP5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
24194. BIFP5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
24195. BIFP5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
24196. BIFP5_PCIE_LC_CNTL__LC_RESET_LINK_MASK
24197. BIFP5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
24198. BIFP5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
24199. BIFP5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
24200. BIFP5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
24201. BIFP5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
24202. BIFP5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
24203. BIFP5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
24204. BIFP5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
24205. BIFP5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
24206. BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
24207. BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
24208. BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
24209. BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
24210. BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
24211. BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
24212. BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
24213. BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
24214. BIFP5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
24215. BIFP5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
24216. BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
24217. BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
24218. BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
24219. BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
24220. BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
24221. BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
24222. BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
24223. BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
24224. BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
24225. BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
24226. BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
24227. BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
24228. BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK
24229. BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT
24230. BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK
24231. BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT
24232. BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK
24233. BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT
24234. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK
24235. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT
24236. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK
24237. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT
24238. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK
24239. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT
24240. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK
24241. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT
24242. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK
24243. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT
24244. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK
24245. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT
24246. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK
24247. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT
24248. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK
24249. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT
24250. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK
24251. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT
24252. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK
24253. BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT
24254. BIFP5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
24255. BIFP5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
24256. BIFP5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
24257. BIFP5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
24258. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
24259. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
24260. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK
24261. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT
24262. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
24263. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
24264. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
24265. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
24266. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
24267. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
24268. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
24269. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
24270. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
24271. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
24272. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
24273. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
24274. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
24275. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
24276. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
24277. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
24278. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
24279. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
24280. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
24281. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
24282. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
24283. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
24284. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
24285. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
24286. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
24287. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
24288. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
24289. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
24290. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
24291. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
24292. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
24293. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
24294. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK
24295. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT
24296. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
24297. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
24298. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
24299. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
24300. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
24301. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
24302. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
24303. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
24304. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
24305. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
24306. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
24307. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
24308. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
24309. BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
24310. BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
24311. BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
24312. BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
24313. BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
24314. BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK
24315. BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT
24316. BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
24317. BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
24318. BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
24319. BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
24320. BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
24321. BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
24322. BIFP5_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK
24323. BIFP5_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT
24324. BIFP5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
24325. BIFP5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
24326. BIFP5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
24327. BIFP5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
24328. BIFP5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
24329. BIFP5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
24330. BIFP5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
24331. BIFP5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
24332. BIFP5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
24333. BIFP5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
24334. BIFP5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
24335. BIFP5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
24336. BIFP5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
24337. BIFP5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
24338. BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
24339. BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
24340. BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
24341. BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
24342. BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
24343. BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
24344. BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
24345. BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
24346. BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
24347. BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
24348. BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
24349. BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
24350. BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
24351. BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
24352. BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
24353. BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
24354. BIFP5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
24355. BIFP5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
24356. BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
24357. BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
24358. BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
24359. BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
24360. BIFP5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
24361. BIFP5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
24362. BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
24363. BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
24364. BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
24365. BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
24366. BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
24367. BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
24368. BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
24369. BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
24370. BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
24371. BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
24372. BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
24373. BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
24374. BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
24375. BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
24376. BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
24377. BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
24378. BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
24379. BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
24380. BIFP5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
24381. BIFP5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
24382. BIFP5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
24383. BIFP5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
24384. BIFP5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
24385. BIFP5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
24386. BIFP5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
24387. BIFP5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
24388. BIFP5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
24389. BIFP5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
24390. BIFP5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
24391. BIFP5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
24392. BIFP5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
24393. BIFP5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
24394. BIFP5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
24395. BIFP5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
24396. BIFP5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
24397. BIFP5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
24398. BIFP5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
24399. BIFP5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
24400. BIFP5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
24401. BIFP5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
24402. BIFP5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
24403. BIFP5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
24404. BIFP5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
24405. BIFP5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
24406. BIFP5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
24407. BIFP5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
24408. BIFP5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
24409. BIFP5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
24410. BIFP5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
24411. BIFP5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
24412. BIFP5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
24413. BIFP5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
24414. BIFP5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
24415. BIFP5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
24416. BIFP5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
24417. BIFP5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
24418. BIFP5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
24419. BIFP5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
24420. BIFP5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
24421. BIFP5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
24422. BIFP5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
24423. BIFP5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
24424. BIFP5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
24425. BIFP5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
24426. BIFP5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
24427. BIFP5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
24428. BIFP5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
24429. BIFP5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
24430. BIFP5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
24431. BIFP5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
24432. BIFP5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
24433. BIFP5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
24434. BIFP5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
24435. BIFP5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
24436. BIFP5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
24437. BIFP5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
24438. BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
24439. BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
24440. BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
24441. BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
24442. BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
24443. BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
24444. BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
24445. BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
24446. BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
24447. BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
24448. BIFP5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
24449. BIFP5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
24450. BIFP5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
24451. BIFP5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
24452. BIFP5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
24453. BIFP5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
24454. BIFP5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
24455. BIFP5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
24456. BIFP5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
24457. BIFP5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
24458. BIFP5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
24459. BIFP5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
24460. BIFP5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
24461. BIFP5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
24462. BIFP5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
24463. BIFP5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
24464. BIFP5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
24465. BIFP5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
24466. BIFP5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
24467. BIFP5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
24468. BIFP5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
24469. BIFP5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
24470. BIFP5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
24471. BIFP5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
24472. BIFP5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
24473. BIFP5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
24474. BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
24475. BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
24476. BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
24477. BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
24478. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK
24479. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT
24480. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK
24481. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT
24482. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK
24483. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT
24484. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK
24485. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT
24486. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK
24487. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT
24488. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK
24489. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT
24490. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK
24491. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT
24492. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK
24493. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT
24494. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK
24495. BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT
24496. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK
24497. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT
24498. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK
24499. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT
24500. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK
24501. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT
24502. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK
24503. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT
24504. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK
24505. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT
24506. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK
24507. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK
24508. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT
24509. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT
24510. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK
24511. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT
24512. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK
24513. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT
24514. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK
24515. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT
24516. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK
24517. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT
24518. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK
24519. BIFP5_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT
24520. BIFP5_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK
24521. BIFP5_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT
24522. BIFP5_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK
24523. BIFP5_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT
24524. BIFP5_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK
24525. BIFP5_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT
24526. BIFP5_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK
24527. BIFP5_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT
24528. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK
24529. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT
24530. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK
24531. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT
24532. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK
24533. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT
24534. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK
24535. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT
24536. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK
24537. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
24538. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK
24539. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT
24540. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK
24541. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
24542. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK
24543. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT
24544. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK
24545. BIFP5_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT
24546. BIFP5_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK
24547. BIFP5_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT
24548. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK
24549. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT
24550. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK
24551. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT
24552. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK
24553. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT
24554. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK
24555. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT
24556. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK
24557. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT
24558. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK
24559. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT
24560. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK
24561. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT
24562. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK
24563. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT
24564. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK
24565. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
24566. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK
24567. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT
24568. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK
24569. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT
24570. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK
24571. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT
24572. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK
24573. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT
24574. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK
24575. BIFP5_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT
24576. BIFP5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
24577. BIFP5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
24578. BIFP5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
24579. BIFP5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
24580. BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
24581. BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
24582. BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
24583. BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
24584. BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
24585. BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
24586. BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
24587. BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
24588. BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
24589. BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
24590. BIFP5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
24591. BIFP5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
24592. BIFP5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
24593. BIFP5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
24594. BIFP5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
24595. BIFP5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
24596. BIFP5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
24597. BIFP5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
24598. BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
24599. BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
24600. BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
24601. BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
24602. BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
24603. BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
24604. BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
24605. BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
24606. BIFP5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
24607. BIFP5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
24608. BIFP5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
24609. BIFP5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
24610. BIFP5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
24611. BIFP5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
24612. BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
24613. BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
24614. BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
24615. BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
24616. BIFP5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
24617. BIFP5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
24618. BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
24619. BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
24620. BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
24621. BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
24622. BIFP5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
24623. BIFP5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
24624. BIFP5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
24625. BIFP5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
24626. BIFP5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
24627. BIFP5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
24628. BIFP5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
24629. BIFP5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
24630. BIFP5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
24631. BIFP5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
24632. BIFP5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
24633. BIFP5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
24634. BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
24635. BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
24636. BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
24637. BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
24638. BIFP5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
24639. BIFP5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
24640. BIFP5_PCIE_RX_CNTL__RX_TPH_DIS_MASK
24641. BIFP5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
24642. BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
24643. BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
24644. BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
24645. BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
24646. BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
24647. BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
24648. BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
24649. BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
24650. BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
24651. BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
24652. BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
24653. BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
24654. BIFP5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
24655. BIFP5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
24656. BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
24657. BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
24658. BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
24659. BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
24660. BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
24661. BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
24662. BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
24663. BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
24664. BIFP5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
24665. BIFP5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
24666. BIFP5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
24667. BIFP5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
24668. BIFP5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
24669. BIFP5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
24670. BIFP5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
24671. BIFP5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
24672. BIFP5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
24673. BIFP5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
24674. BIFP5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
24675. BIFP5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
24676. BIFP5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
24677. BIFP5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
24678. BIFP5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
24679. BIFP5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
24680. BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
24681. BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
24682. BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
24683. BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
24684. BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
24685. BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
24686. BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
24687. BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
24688. BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
24689. BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
24690. BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
24691. BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
24692. BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
24693. BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
24694. BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
24695. BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
24696. BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
24697. BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
24698. BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
24699. BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
24700. BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
24701. BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
24702. BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
24703. BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
24704. BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
24705. BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
24706. BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
24707. BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
24708. BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
24709. BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
24710. BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
24711. BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
24712. BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
24713. BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
24714. BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
24715. BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
24716. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
24717. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
24718. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
24719. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
24720. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
24721. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
24722. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
24723. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
24724. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
24725. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
24726. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
24727. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
24728. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
24729. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
24730. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
24731. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
24732. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
24733. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
24734. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
24735. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
24736. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
24737. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
24738. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
24739. BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
24740. BIFP5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
24741. BIFP5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
24742. BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
24743. BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
24744. BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
24745. BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
24746. BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
24747. BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
24748. BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
24749. BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
24750. BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
24751. BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
24752. BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
24753. BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
24754. BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
24755. BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
24756. BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
24757. BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
24758. BIFP5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
24759. BIFP5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
24760. BIFP5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
24761. BIFP5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
24762. BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
24763. BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
24764. BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
24765. BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
24766. BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
24767. BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
24768. BIFP6_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
24769. BIFP6_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
24770. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
24771. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
24772. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
24773. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
24774. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
24775. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
24776. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
24777. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
24778. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
24779. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
24780. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
24781. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
24782. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
24783. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
24784. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
24785. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
24786. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
24787. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
24788. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
24789. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
24790. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
24791. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
24792. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
24793. BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
24794. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
24795. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
24796. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
24797. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
24798. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
24799. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
24800. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
24801. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
24802. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
24803. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
24804. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
24805. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
24806. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
24807. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
24808. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
24809. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
24810. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
24811. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
24812. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
24813. BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
24814. BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK
24815. BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT
24816. BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK
24817. BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT
24818. BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
24819. BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
24820. BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
24821. BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
24822. BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
24823. BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
24824. BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
24825. BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
24826. BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
24827. BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
24828. BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
24829. BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
24830. BIFP6_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
24831. BIFP6_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
24832. BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
24833. BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
24834. BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
24835. BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
24836. BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
24837. BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
24838. BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
24839. BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
24840. BIFP6_PCIEP_HPGI__REG_HPGI_HOOK_MASK
24841. BIFP6_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
24842. BIFP6_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
24843. BIFP6_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
24844. BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK
24845. BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT
24846. BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK
24847. BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT
24848. BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK
24849. BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT
24850. BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK
24851. BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT
24852. BIFP6_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
24853. BIFP6_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
24854. BIFP6_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
24855. BIFP6_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
24856. BIFP6_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
24857. BIFP6_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
24858. BIFP6_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK
24859. BIFP6_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT
24860. BIFP6_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
24861. BIFP6_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
24862. BIFP6_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
24863. BIFP6_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
24864. BIFP6_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
24865. BIFP6_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
24866. BIFP6_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
24867. BIFP6_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
24868. BIFP6_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
24869. BIFP6_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
24870. BIFP6_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
24871. BIFP6_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
24872. BIFP6_PCIEP_RESERVED__PCIEP_RESERVED_MASK
24873. BIFP6_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
24874. BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK
24875. BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT
24876. BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK
24877. BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT
24878. BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK
24879. BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT
24880. BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK
24881. BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT
24882. BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK
24883. BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT
24884. BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK
24885. BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT
24886. BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK
24887. BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT
24888. BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK
24889. BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT
24890. BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK
24891. BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT
24892. BIFP6_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
24893. BIFP6_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
24894. BIFP6_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
24895. BIFP6_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
24896. BIFP6_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
24897. BIFP6_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
24898. BIFP6_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
24899. BIFP6_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
24900. BIFP6_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
24901. BIFP6_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
24902. BIFP6_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
24903. BIFP6_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
24904. BIFP6_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
24905. BIFP6_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
24906. BIFP6_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
24907. BIFP6_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
24908. BIFP6_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
24909. BIFP6_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
24910. BIFP6_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
24911. BIFP6_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
24912. BIFP6_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
24913. BIFP6_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
24914. BIFP6_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
24915. BIFP6_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
24916. BIFP6_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
24917. BIFP6_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
24918. BIFP6_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
24919. BIFP6_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
24920. BIFP6_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
24921. BIFP6_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
24922. BIFP6_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
24923. BIFP6_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
24924. BIFP6_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
24925. BIFP6_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
24926. BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
24927. BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
24928. BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
24929. BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
24930. BIFP6_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
24931. BIFP6_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
24932. BIFP6_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
24933. BIFP6_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
24934. BIFP6_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
24935. BIFP6_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
24936. BIFP6_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
24937. BIFP6_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
24938. BIFP6_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
24939. BIFP6_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
24940. BIFP6_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
24941. BIFP6_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
24942. BIFP6_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
24943. BIFP6_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
24944. BIFP6_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
24945. BIFP6_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
24946. BIFP6_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
24947. BIFP6_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
24948. BIFP6_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
24949. BIFP6_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
24950. BIFP6_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
24951. BIFP6_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
24952. BIFP6_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
24953. BIFP6_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
24954. BIFP6_PCIE_FC_CPL__CPLD_CREDITS_MASK
24955. BIFP6_PCIE_FC_CPL__CPLD_CREDITS__SHIFT
24956. BIFP6_PCIE_FC_CPL__CPLH_CREDITS_MASK
24957. BIFP6_PCIE_FC_CPL__CPLH_CREDITS__SHIFT
24958. BIFP6_PCIE_FC_NP__NPD_CREDITS_MASK
24959. BIFP6_PCIE_FC_NP__NPD_CREDITS__SHIFT
24960. BIFP6_PCIE_FC_NP__NPH_CREDITS_MASK
24961. BIFP6_PCIE_FC_NP__NPH_CREDITS__SHIFT
24962. BIFP6_PCIE_FC_P__PD_CREDITS_MASK
24963. BIFP6_PCIE_FC_P__PD_CREDITS__SHIFT
24964. BIFP6_PCIE_FC_P__PH_CREDITS_MASK
24965. BIFP6_PCIE_FC_P__PH_CREDITS__SHIFT
24966. BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
24967. BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
24968. BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
24969. BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
24970. BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
24971. BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
24972. BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
24973. BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
24974. BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
24975. BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
24976. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
24977. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
24978. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
24979. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
24980. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
24981. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
24982. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
24983. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
24984. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
24985. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
24986. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
24987. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
24988. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
24989. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
24990. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
24991. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
24992. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
24993. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
24994. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
24995. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
24996. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK
24997. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT
24998. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
24999. BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
25000. BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
25001. BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
25002. BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
25003. BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
25004. BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
25005. BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
25006. BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
25007. BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
25008. BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
25009. BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
25010. BIFP6_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
25011. BIFP6_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
25012. BIFP6_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
25013. BIFP6_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
25014. BIFP6_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
25015. BIFP6_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
25016. BIFP6_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
25017. BIFP6_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
25018. BIFP6_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
25019. BIFP6_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
25020. BIFP6_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
25021. BIFP6_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
25022. BIFP6_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
25023. BIFP6_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
25024. BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
25025. BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
25026. BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
25027. BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
25028. BIFP6_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
25029. BIFP6_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
25030. BIFP6_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
25031. BIFP6_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
25032. BIFP6_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
25033. BIFP6_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
25034. BIFP6_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
25035. BIFP6_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
25036. BIFP6_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
25037. BIFP6_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
25038. BIFP6_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
25039. BIFP6_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
25040. BIFP6_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
25041. BIFP6_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
25042. BIFP6_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
25043. BIFP6_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
25044. BIFP6_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
25045. BIFP6_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
25046. BIFP6_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
25047. BIFP6_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
25048. BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
25049. BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
25050. BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
25051. BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
25052. BIFP6_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
25053. BIFP6_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
25054. BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
25055. BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
25056. BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
25057. BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
25058. BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
25059. BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
25060. BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
25061. BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
25062. BIFP6_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
25063. BIFP6_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
25064. BIFP6_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
25065. BIFP6_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
25066. BIFP6_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
25067. BIFP6_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
25068. BIFP6_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
25069. BIFP6_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
25070. BIFP6_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
25071. BIFP6_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
25072. BIFP6_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
25073. BIFP6_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
25074. BIFP6_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
25075. BIFP6_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
25076. BIFP6_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
25077. BIFP6_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
25078. BIFP6_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
25079. BIFP6_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
25080. BIFP6_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
25081. BIFP6_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
25082. BIFP6_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
25083. BIFP6_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
25084. BIFP6_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
25085. BIFP6_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
25086. BIFP6_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
25087. BIFP6_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
25088. BIFP6_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
25089. BIFP6_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
25090. BIFP6_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
25091. BIFP6_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
25092. BIFP6_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
25093. BIFP6_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
25094. BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
25095. BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
25096. BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
25097. BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
25098. BIFP6_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
25099. BIFP6_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
25100. BIFP6_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
25101. BIFP6_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
25102. BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
25103. BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
25104. BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
25105. BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
25106. BIFP6_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
25107. BIFP6_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
25108. BIFP6_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
25109. BIFP6_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
25110. BIFP6_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
25111. BIFP6_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
25112. BIFP6_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
25113. BIFP6_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
25114. BIFP6_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
25115. BIFP6_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
25116. BIFP6_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
25117. BIFP6_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
25118. BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
25119. BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
25120. BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
25121. BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
25122. BIFP6_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
25123. BIFP6_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
25124. BIFP6_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
25125. BIFP6_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
25126. BIFP6_PCIE_LC_CNTL4__LC_REDO_EQ_MASK
25127. BIFP6_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
25128. BIFP6_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
25129. BIFP6_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
25130. BIFP6_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
25131. BIFP6_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
25132. BIFP6_PCIE_LC_CNTL4__LC_TX_SWING_MASK
25133. BIFP6_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT
25134. BIFP6_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
25135. BIFP6_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
25136. BIFP6_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
25137. BIFP6_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
25138. BIFP6_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
25139. BIFP6_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
25140. BIFP6_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
25141. BIFP6_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
25142. BIFP6_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
25143. BIFP6_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
25144. BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK
25145. BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK
25146. BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT
25147. BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT
25148. BIFP6_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
25149. BIFP6_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
25150. BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
25151. BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
25152. BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
25153. BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
25154. BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
25155. BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
25156. BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
25157. BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
25158. BIFP6_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK
25159. BIFP6_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT
25160. BIFP6_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK
25161. BIFP6_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT
25162. BIFP6_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK
25163. BIFP6_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT
25164. BIFP6_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK
25165. BIFP6_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT
25166. BIFP6_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK
25167. BIFP6_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT
25168. BIFP6_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK
25169. BIFP6_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT
25170. BIFP6_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK
25171. BIFP6_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT
25172. BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK
25173. BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT
25174. BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK
25175. BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT
25176. BIFP6_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK
25177. BIFP6_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT
25178. BIFP6_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK
25179. BIFP6_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT
25180. BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
25181. BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
25182. BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
25183. BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
25184. BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
25185. BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
25186. BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK
25187. BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT
25188. BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK
25189. BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT
25190. BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK
25191. BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT
25192. BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK
25193. BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT
25194. BIFP6_PCIE_LC_CNTL6__LC_SRIS_EN_MASK
25195. BIFP6_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT
25196. BIFP6_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK
25197. BIFP6_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT
25198. BIFP6_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK
25199. BIFP6_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT
25200. BIFP6_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK
25201. BIFP6_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT
25202. BIFP6_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK
25203. BIFP6_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT
25204. BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK
25205. BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT
25206. BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK
25207. BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT
25208. BIFP6_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK
25209. BIFP6_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT
25210. BIFP6_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK
25211. BIFP6_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT
25212. BIFP6_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK
25213. BIFP6_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT
25214. BIFP6_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK
25215. BIFP6_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT
25216. BIFP6_PCIE_LC_CNTL7__LC_FOM_TIME_MASK
25217. BIFP6_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT
25218. BIFP6_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK
25219. BIFP6_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT
25220. BIFP6_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK
25221. BIFP6_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT
25222. BIFP6_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK
25223. BIFP6_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT
25224. BIFP6_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK
25225. BIFP6_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT
25226. BIFP6_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK
25227. BIFP6_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT
25228. BIFP6_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK
25229. BIFP6_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT
25230. BIFP6_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK
25231. BIFP6_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT
25232. BIFP6_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK
25233. BIFP6_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT
25234. BIFP6_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK
25235. BIFP6_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT
25236. BIFP6_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK
25237. BIFP6_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT
25238. BIFP6_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK
25239. BIFP6_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT
25240. BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK
25241. BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT
25242. BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK
25243. BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT
25244. BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK
25245. BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT
25246. BIFP6_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK
25247. BIFP6_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT
25248. BIFP6_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
25249. BIFP6_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
25250. BIFP6_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
25251. BIFP6_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
25252. BIFP6_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
25253. BIFP6_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
25254. BIFP6_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
25255. BIFP6_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
25256. BIFP6_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
25257. BIFP6_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
25258. BIFP6_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
25259. BIFP6_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
25260. BIFP6_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
25261. BIFP6_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
25262. BIFP6_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
25263. BIFP6_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
25264. BIFP6_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
25265. BIFP6_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
25266. BIFP6_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
25267. BIFP6_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
25268. BIFP6_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
25269. BIFP6_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
25270. BIFP6_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
25271. BIFP6_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
25272. BIFP6_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
25273. BIFP6_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
25274. BIFP6_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
25275. BIFP6_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
25276. BIFP6_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
25277. BIFP6_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
25278. BIFP6_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
25279. BIFP6_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
25280. BIFP6_PCIE_LC_CNTL__LC_RESET_LINK_MASK
25281. BIFP6_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
25282. BIFP6_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
25283. BIFP6_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
25284. BIFP6_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
25285. BIFP6_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
25286. BIFP6_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
25287. BIFP6_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
25288. BIFP6_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
25289. BIFP6_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
25290. BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
25291. BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
25292. BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
25293. BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
25294. BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
25295. BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
25296. BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
25297. BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
25298. BIFP6_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
25299. BIFP6_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
25300. BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
25301. BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
25302. BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
25303. BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
25304. BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
25305. BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
25306. BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
25307. BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
25308. BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
25309. BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
25310. BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
25311. BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
25312. BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK
25313. BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT
25314. BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK
25315. BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT
25316. BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK
25317. BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT
25318. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK
25319. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT
25320. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK
25321. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT
25322. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK
25323. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT
25324. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK
25325. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT
25326. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK
25327. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT
25328. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK
25329. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT
25330. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK
25331. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT
25332. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK
25333. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT
25334. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK
25335. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT
25336. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK
25337. BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT
25338. BIFP6_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
25339. BIFP6_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
25340. BIFP6_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
25341. BIFP6_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
25342. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
25343. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
25344. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK
25345. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT
25346. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
25347. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
25348. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
25349. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
25350. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
25351. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
25352. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
25353. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
25354. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
25355. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
25356. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
25357. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
25358. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
25359. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
25360. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
25361. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
25362. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
25363. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
25364. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
25365. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
25366. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
25367. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
25368. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
25369. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
25370. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
25371. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
25372. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
25373. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
25374. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
25375. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
25376. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
25377. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
25378. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK
25379. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT
25380. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
25381. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
25382. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
25383. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
25384. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
25385. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
25386. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
25387. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
25388. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
25389. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
25390. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
25391. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
25392. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
25393. BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
25394. BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
25395. BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
25396. BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
25397. BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
25398. BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK
25399. BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT
25400. BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
25401. BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
25402. BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
25403. BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
25404. BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
25405. BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
25406. BIFP6_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK
25407. BIFP6_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT
25408. BIFP6_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
25409. BIFP6_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
25410. BIFP6_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
25411. BIFP6_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
25412. BIFP6_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
25413. BIFP6_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
25414. BIFP6_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
25415. BIFP6_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
25416. BIFP6_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
25417. BIFP6_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
25418. BIFP6_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
25419. BIFP6_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
25420. BIFP6_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
25421. BIFP6_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
25422. BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
25423. BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
25424. BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
25425. BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
25426. BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
25427. BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
25428. BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
25429. BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
25430. BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
25431. BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
25432. BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
25433. BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
25434. BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
25435. BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
25436. BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
25437. BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
25438. BIFP6_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
25439. BIFP6_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
25440. BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
25441. BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
25442. BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
25443. BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
25444. BIFP6_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
25445. BIFP6_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
25446. BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
25447. BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
25448. BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
25449. BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
25450. BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
25451. BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
25452. BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
25453. BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
25454. BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
25455. BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
25456. BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
25457. BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
25458. BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
25459. BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
25460. BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
25461. BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
25462. BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
25463. BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
25464. BIFP6_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
25465. BIFP6_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
25466. BIFP6_PCIE_LC_STATE0__LC_PREV_STATE1_MASK
25467. BIFP6_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
25468. BIFP6_PCIE_LC_STATE0__LC_PREV_STATE2_MASK
25469. BIFP6_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
25470. BIFP6_PCIE_LC_STATE0__LC_PREV_STATE3_MASK
25471. BIFP6_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
25472. BIFP6_PCIE_LC_STATE1__LC_PREV_STATE4_MASK
25473. BIFP6_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
25474. BIFP6_PCIE_LC_STATE1__LC_PREV_STATE5_MASK
25475. BIFP6_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
25476. BIFP6_PCIE_LC_STATE1__LC_PREV_STATE6_MASK
25477. BIFP6_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
25478. BIFP6_PCIE_LC_STATE1__LC_PREV_STATE7_MASK
25479. BIFP6_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
25480. BIFP6_PCIE_LC_STATE2__LC_PREV_STATE10_MASK
25481. BIFP6_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
25482. BIFP6_PCIE_LC_STATE2__LC_PREV_STATE11_MASK
25483. BIFP6_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
25484. BIFP6_PCIE_LC_STATE2__LC_PREV_STATE8_MASK
25485. BIFP6_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
25486. BIFP6_PCIE_LC_STATE2__LC_PREV_STATE9_MASK
25487. BIFP6_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
25488. BIFP6_PCIE_LC_STATE3__LC_PREV_STATE12_MASK
25489. BIFP6_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
25490. BIFP6_PCIE_LC_STATE3__LC_PREV_STATE13_MASK
25491. BIFP6_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
25492. BIFP6_PCIE_LC_STATE3__LC_PREV_STATE14_MASK
25493. BIFP6_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
25494. BIFP6_PCIE_LC_STATE3__LC_PREV_STATE15_MASK
25495. BIFP6_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
25496. BIFP6_PCIE_LC_STATE4__LC_PREV_STATE16_MASK
25497. BIFP6_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
25498. BIFP6_PCIE_LC_STATE4__LC_PREV_STATE17_MASK
25499. BIFP6_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
25500. BIFP6_PCIE_LC_STATE4__LC_PREV_STATE18_MASK
25501. BIFP6_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
25502. BIFP6_PCIE_LC_STATE4__LC_PREV_STATE19_MASK
25503. BIFP6_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
25504. BIFP6_PCIE_LC_STATE5__LC_PREV_STATE20_MASK
25505. BIFP6_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
25506. BIFP6_PCIE_LC_STATE5__LC_PREV_STATE21_MASK
25507. BIFP6_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
25508. BIFP6_PCIE_LC_STATE5__LC_PREV_STATE22_MASK
25509. BIFP6_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
25510. BIFP6_PCIE_LC_STATE5__LC_PREV_STATE23_MASK
25511. BIFP6_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
25512. BIFP6_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
25513. BIFP6_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
25514. BIFP6_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
25515. BIFP6_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
25516. BIFP6_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
25517. BIFP6_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
25518. BIFP6_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
25519. BIFP6_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
25520. BIFP6_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
25521. BIFP6_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
25522. BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
25523. BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
25524. BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
25525. BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
25526. BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
25527. BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
25528. BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
25529. BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
25530. BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
25531. BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
25532. BIFP6_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
25533. BIFP6_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
25534. BIFP6_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
25535. BIFP6_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
25536. BIFP6_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
25537. BIFP6_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
25538. BIFP6_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
25539. BIFP6_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
25540. BIFP6_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
25541. BIFP6_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
25542. BIFP6_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
25543. BIFP6_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
25544. BIFP6_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
25545. BIFP6_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
25546. BIFP6_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
25547. BIFP6_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
25548. BIFP6_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
25549. BIFP6_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
25550. BIFP6_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
25551. BIFP6_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
25552. BIFP6_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
25553. BIFP6_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
25554. BIFP6_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
25555. BIFP6_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
25556. BIFP6_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
25557. BIFP6_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
25558. BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
25559. BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
25560. BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
25561. BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
25562. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK
25563. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT
25564. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK
25565. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT
25566. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK
25567. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT
25568. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK
25569. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT
25570. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK
25571. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT
25572. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK
25573. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT
25574. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK
25575. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT
25576. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK
25577. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT
25578. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK
25579. BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT
25580. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK
25581. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT
25582. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK
25583. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT
25584. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK
25585. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT
25586. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK
25587. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT
25588. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK
25589. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT
25590. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK
25591. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK
25592. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT
25593. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT
25594. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK
25595. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT
25596. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK
25597. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT
25598. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK
25599. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT
25600. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK
25601. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT
25602. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK
25603. BIFP6_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT
25604. BIFP6_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK
25605. BIFP6_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT
25606. BIFP6_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK
25607. BIFP6_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT
25608. BIFP6_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK
25609. BIFP6_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT
25610. BIFP6_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK
25611. BIFP6_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT
25612. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK
25613. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT
25614. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK
25615. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT
25616. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK
25617. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT
25618. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK
25619. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT
25620. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK
25621. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
25622. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK
25623. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT
25624. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK
25625. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
25626. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK
25627. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT
25628. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK
25629. BIFP6_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT
25630. BIFP6_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK
25631. BIFP6_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT
25632. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK
25633. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT
25634. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK
25635. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT
25636. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK
25637. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT
25638. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK
25639. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT
25640. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK
25641. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT
25642. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK
25643. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT
25644. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK
25645. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT
25646. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK
25647. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT
25648. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK
25649. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
25650. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK
25651. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT
25652. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK
25653. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT
25654. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK
25655. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT
25656. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK
25657. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT
25658. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK
25659. BIFP6_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT
25660. BIFP6_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
25661. BIFP6_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
25662. BIFP6_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
25663. BIFP6_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
25664. BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
25665. BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
25666. BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
25667. BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
25668. BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
25669. BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
25670. BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
25671. BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
25672. BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
25673. BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
25674. BIFP6_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
25675. BIFP6_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
25676. BIFP6_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
25677. BIFP6_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
25678. BIFP6_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
25679. BIFP6_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
25680. BIFP6_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
25681. BIFP6_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
25682. BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
25683. BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
25684. BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
25685. BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
25686. BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
25687. BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
25688. BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
25689. BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
25690. BIFP6_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
25691. BIFP6_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
25692. BIFP6_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
25693. BIFP6_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
25694. BIFP6_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
25695. BIFP6_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
25696. BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
25697. BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
25698. BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
25699. BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
25700. BIFP6_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
25701. BIFP6_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
25702. BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
25703. BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
25704. BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
25705. BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
25706. BIFP6_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
25707. BIFP6_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
25708. BIFP6_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
25709. BIFP6_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
25710. BIFP6_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
25711. BIFP6_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
25712. BIFP6_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
25713. BIFP6_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
25714. BIFP6_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
25715. BIFP6_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
25716. BIFP6_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
25717. BIFP6_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
25718. BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
25719. BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
25720. BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
25721. BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
25722. BIFP6_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
25723. BIFP6_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
25724. BIFP6_PCIE_RX_CNTL__RX_TPH_DIS_MASK
25725. BIFP6_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
25726. BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
25727. BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
25728. BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
25729. BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
25730. BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
25731. BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
25732. BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
25733. BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
25734. BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
25735. BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
25736. BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
25737. BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
25738. BIFP6_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
25739. BIFP6_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
25740. BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
25741. BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
25742. BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
25743. BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
25744. BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
25745. BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
25746. BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
25747. BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
25748. BIFP6_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
25749. BIFP6_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
25750. BIFP6_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
25751. BIFP6_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
25752. BIFP6_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
25753. BIFP6_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
25754. BIFP6_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
25755. BIFP6_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
25756. BIFP6_PCIE_TX_CNTL__TX_NP_PASS_P_MASK
25757. BIFP6_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
25758. BIFP6_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
25759. BIFP6_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
25760. BIFP6_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
25761. BIFP6_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
25762. BIFP6_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
25763. BIFP6_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
25764. BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
25765. BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
25766. BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
25767. BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
25768. BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
25769. BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
25770. BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
25771. BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
25772. BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
25773. BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
25774. BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
25775. BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
25776. BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
25777. BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
25778. BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
25779. BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
25780. BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
25781. BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
25782. BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
25783. BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
25784. BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
25785. BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
25786. BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
25787. BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
25788. BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
25789. BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
25790. BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
25791. BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
25792. BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
25793. BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
25794. BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
25795. BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
25796. BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
25797. BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
25798. BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
25799. BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
25800. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
25801. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
25802. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
25803. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
25804. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
25805. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
25806. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
25807. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
25808. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
25809. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
25810. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
25811. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
25812. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
25813. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
25814. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
25815. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
25816. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
25817. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
25818. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
25819. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
25820. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
25821. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
25822. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
25823. BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
25824. BIFP6_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
25825. BIFP6_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
25826. BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
25827. BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
25828. BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
25829. BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
25830. BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
25831. BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
25832. BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
25833. BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
25834. BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
25835. BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
25836. BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
25837. BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
25838. BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
25839. BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
25840. BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
25841. BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
25842. BIFP6_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
25843. BIFP6_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
25844. BIFP6_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
25845. BIFP6_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
25846. BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
25847. BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
25848. BIFPLR0_0_BASE_CLASS__BASE_CLASS_MASK
25849. BIFPLR0_0_BASE_CLASS__BASE_CLASS__SHIFT
25850. BIFPLR0_0_BIST__BIST_CAP_MASK
25851. BIFPLR0_0_BIST__BIST_CAP__SHIFT
25852. BIFPLR0_0_BIST__BIST_COMP_MASK
25853. BIFPLR0_0_BIST__BIST_COMP__SHIFT
25854. BIFPLR0_0_BIST__BIST_STRT_MASK
25855. BIFPLR0_0_BIST__BIST_STRT__SHIFT
25856. BIFPLR0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
25857. BIFPLR0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
25858. BIFPLR0_0_CAP_PTR__CAP_PTR_MASK
25859. BIFPLR0_0_CAP_PTR__CAP_PTR__SHIFT
25860. BIFPLR0_0_COMMAND__AD_STEPPING_MASK
25861. BIFPLR0_0_COMMAND__AD_STEPPING__SHIFT
25862. BIFPLR0_0_COMMAND__BUS_MASTER_EN_MASK
25863. BIFPLR0_0_COMMAND__BUS_MASTER_EN__SHIFT
25864. BIFPLR0_0_COMMAND__FAST_B2B_EN_MASK
25865. BIFPLR0_0_COMMAND__FAST_B2B_EN__SHIFT
25866. BIFPLR0_0_COMMAND__INT_DIS_MASK
25867. BIFPLR0_0_COMMAND__INT_DIS__SHIFT
25868. BIFPLR0_0_COMMAND__IO_ACCESS_EN_MASK
25869. BIFPLR0_0_COMMAND__IO_ACCESS_EN__SHIFT
25870. BIFPLR0_0_COMMAND__MEM_ACCESS_EN_MASK
25871. BIFPLR0_0_COMMAND__MEM_ACCESS_EN__SHIFT
25872. BIFPLR0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
25873. BIFPLR0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
25874. BIFPLR0_0_COMMAND__PAL_SNOOP_EN_MASK
25875. BIFPLR0_0_COMMAND__PAL_SNOOP_EN__SHIFT
25876. BIFPLR0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
25877. BIFPLR0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
25878. BIFPLR0_0_COMMAND__SERR_EN_MASK
25879. BIFPLR0_0_COMMAND__SERR_EN__SHIFT
25880. BIFPLR0_0_COMMAND__SPECIAL_CYCLE_EN_MASK
25881. BIFPLR0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
25882. BIFPLR0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
25883. BIFPLR0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
25884. BIFPLR0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
25885. BIFPLR0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
25886. BIFPLR0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
25887. BIFPLR0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
25888. BIFPLR0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
25889. BIFPLR0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
25890. BIFPLR0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
25891. BIFPLR0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
25892. BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
25893. BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
25894. BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
25895. BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
25896. BIFPLR0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
25897. BIFPLR0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
25898. BIFPLR0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
25899. BIFPLR0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
25900. BIFPLR0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
25901. BIFPLR0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
25902. BIFPLR0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
25903. BIFPLR0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
25904. BIFPLR0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
25905. BIFPLR0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
25906. BIFPLR0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
25907. BIFPLR0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
25908. BIFPLR0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
25909. BIFPLR0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
25910. BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
25911. BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
25912. BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
25913. BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
25914. BIFPLR0_0_DEVICE_CAP__EXTENDED_TAG_MASK
25915. BIFPLR0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
25916. BIFPLR0_0_DEVICE_CAP__FLR_CAPABLE_MASK
25917. BIFPLR0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
25918. BIFPLR0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
25919. BIFPLR0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
25920. BIFPLR0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
25921. BIFPLR0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
25922. BIFPLR0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
25923. BIFPLR0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
25924. BIFPLR0_0_DEVICE_CAP__PHANTOM_FUNC_MASK
25925. BIFPLR0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
25926. BIFPLR0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
25927. BIFPLR0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
25928. BIFPLR0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
25929. BIFPLR0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
25930. BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
25931. BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
25932. BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
25933. BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
25934. BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
25935. BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
25936. BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
25937. BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
25938. BIFPLR0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
25939. BIFPLR0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
25940. BIFPLR0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
25941. BIFPLR0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
25942. BIFPLR0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
25943. BIFPLR0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
25944. BIFPLR0_0_DEVICE_CNTL2__LTR_EN_MASK
25945. BIFPLR0_0_DEVICE_CNTL2__LTR_EN__SHIFT
25946. BIFPLR0_0_DEVICE_CNTL2__OBFF_EN_MASK
25947. BIFPLR0_0_DEVICE_CNTL2__OBFF_EN__SHIFT
25948. BIFPLR0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
25949. BIFPLR0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
25950. BIFPLR0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
25951. BIFPLR0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
25952. BIFPLR0_0_DEVICE_CNTL__CORR_ERR_EN_MASK
25953. BIFPLR0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
25954. BIFPLR0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
25955. BIFPLR0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
25956. BIFPLR0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
25957. BIFPLR0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
25958. BIFPLR0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
25959. BIFPLR0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
25960. BIFPLR0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
25961. BIFPLR0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
25962. BIFPLR0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
25963. BIFPLR0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
25964. BIFPLR0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
25965. BIFPLR0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
25966. BIFPLR0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
25967. BIFPLR0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
25968. BIFPLR0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
25969. BIFPLR0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
25970. BIFPLR0_0_DEVICE_CNTL__USR_REPORT_EN_MASK
25971. BIFPLR0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
25972. BIFPLR0_0_DEVICE_ID__DEVICE_ID_MASK
25973. BIFPLR0_0_DEVICE_ID__DEVICE_ID__SHIFT
25974. BIFPLR0_0_DEVICE_STATUS2__RESERVED_MASK
25975. BIFPLR0_0_DEVICE_STATUS2__RESERVED__SHIFT
25976. BIFPLR0_0_DEVICE_STATUS__AUX_PWR_MASK
25977. BIFPLR0_0_DEVICE_STATUS__AUX_PWR__SHIFT
25978. BIFPLR0_0_DEVICE_STATUS__CORR_ERR_MASK
25979. BIFPLR0_0_DEVICE_STATUS__CORR_ERR__SHIFT
25980. BIFPLR0_0_DEVICE_STATUS__FATAL_ERR_MASK
25981. BIFPLR0_0_DEVICE_STATUS__FATAL_ERR__SHIFT
25982. BIFPLR0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
25983. BIFPLR0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
25984. BIFPLR0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
25985. BIFPLR0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
25986. BIFPLR0_0_DEVICE_STATUS__USR_DETECTED_MASK
25987. BIFPLR0_0_DEVICE_STATUS__USR_DETECTED__SHIFT
25988. BIFPLR0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
25989. BIFPLR0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
25990. BIFPLR0_0_HEADER__DEVICE_TYPE_MASK
25991. BIFPLR0_0_HEADER__DEVICE_TYPE__SHIFT
25992. BIFPLR0_0_HEADER__HEADER_TYPE_MASK
25993. BIFPLR0_0_HEADER__HEADER_TYPE__SHIFT
25994. BIFPLR0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
25995. BIFPLR0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
25996. BIFPLR0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
25997. BIFPLR0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
25998. BIFPLR0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
25999. BIFPLR0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
26000. BIFPLR0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
26001. BIFPLR0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
26002. BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_MASK
26003. BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
26004. BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
26005. BIFPLR0_0_IO_BASE_LIMIT__IO_BASE__SHIFT
26006. BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_MASK
26007. BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
26008. BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
26009. BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT
26010. BIFPLR0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
26011. BIFPLR0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
26012. BIFPLR0_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK
26013. BIFPLR0_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
26014. BIFPLR0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
26015. BIFPLR0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
26016. BIFPLR0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
26017. BIFPLR0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
26018. BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
26019. BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
26020. BIFPLR0_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK
26021. BIFPLR0_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
26022. BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
26023. BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
26024. BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK
26025. BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
26026. BIFPLR0_0_LATENCY__LATENCY_TIMER_MASK
26027. BIFPLR0_0_LATENCY__LATENCY_TIMER__SHIFT
26028. BIFPLR0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
26029. BIFPLR0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
26030. BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
26031. BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
26032. BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
26033. BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
26034. BIFPLR0_0_LINK_CAP2__RESERVED_MASK
26035. BIFPLR0_0_LINK_CAP2__RESERVED__SHIFT
26036. BIFPLR0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
26037. BIFPLR0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
26038. BIFPLR0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
26039. BIFPLR0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
26040. BIFPLR0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
26041. BIFPLR0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
26042. BIFPLR0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
26043. BIFPLR0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
26044. BIFPLR0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
26045. BIFPLR0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
26046. BIFPLR0_0_LINK_CAP__L1_EXIT_LATENCY_MASK
26047. BIFPLR0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
26048. BIFPLR0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
26049. BIFPLR0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
26050. BIFPLR0_0_LINK_CAP__LINK_SPEED_MASK
26051. BIFPLR0_0_LINK_CAP__LINK_SPEED__SHIFT
26052. BIFPLR0_0_LINK_CAP__LINK_WIDTH_MASK
26053. BIFPLR0_0_LINK_CAP__LINK_WIDTH__SHIFT
26054. BIFPLR0_0_LINK_CAP__PM_SUPPORT_MASK
26055. BIFPLR0_0_LINK_CAP__PM_SUPPORT__SHIFT
26056. BIFPLR0_0_LINK_CAP__PORT_NUMBER_MASK
26057. BIFPLR0_0_LINK_CAP__PORT_NUMBER__SHIFT
26058. BIFPLR0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
26059. BIFPLR0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
26060. BIFPLR0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
26061. BIFPLR0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
26062. BIFPLR0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
26063. BIFPLR0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
26064. BIFPLR0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
26065. BIFPLR0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
26066. BIFPLR0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
26067. BIFPLR0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
26068. BIFPLR0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
26069. BIFPLR0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
26070. BIFPLR0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
26071. BIFPLR0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
26072. BIFPLR0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
26073. BIFPLR0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
26074. BIFPLR0_0_LINK_CNTL2__XMIT_MARGIN_MASK
26075. BIFPLR0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
26076. BIFPLR0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
26077. BIFPLR0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
26078. BIFPLR0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
26079. BIFPLR0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
26080. BIFPLR0_0_LINK_CNTL__EXTENDED_SYNC_MASK
26081. BIFPLR0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
26082. BIFPLR0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
26083. BIFPLR0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
26084. BIFPLR0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
26085. BIFPLR0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
26086. BIFPLR0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
26087. BIFPLR0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
26088. BIFPLR0_0_LINK_CNTL__LINK_DIS_MASK
26089. BIFPLR0_0_LINK_CNTL__LINK_DIS__SHIFT
26090. BIFPLR0_0_LINK_CNTL__PM_CONTROL_MASK
26091. BIFPLR0_0_LINK_CNTL__PM_CONTROL__SHIFT
26092. BIFPLR0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
26093. BIFPLR0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
26094. BIFPLR0_0_LINK_CNTL__RETRAIN_LINK_MASK
26095. BIFPLR0_0_LINK_CNTL__RETRAIN_LINK__SHIFT
26096. BIFPLR0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
26097. BIFPLR0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
26098. BIFPLR0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
26099. BIFPLR0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
26100. BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
26101. BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
26102. BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
26103. BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
26104. BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
26105. BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
26106. BIFPLR0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
26107. BIFPLR0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
26108. BIFPLR0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
26109. BIFPLR0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
26110. BIFPLR0_0_LINK_STATUS__DL_ACTIVE_MASK
26111. BIFPLR0_0_LINK_STATUS__DL_ACTIVE__SHIFT
26112. BIFPLR0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
26113. BIFPLR0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
26114. BIFPLR0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
26115. BIFPLR0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
26116. BIFPLR0_0_LINK_STATUS__LINK_TRAINING_MASK
26117. BIFPLR0_0_LINK_STATUS__LINK_TRAINING__SHIFT
26118. BIFPLR0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
26119. BIFPLR0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
26120. BIFPLR0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
26121. BIFPLR0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
26122. BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
26123. BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
26124. BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
26125. BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
26126. BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
26127. BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
26128. BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
26129. BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
26130. BIFPLR0_0_MSI_CAP_LIST__CAP_ID_MASK
26131. BIFPLR0_0_MSI_CAP_LIST__CAP_ID__SHIFT
26132. BIFPLR0_0_MSI_CAP_LIST__NEXT_PTR_MASK
26133. BIFPLR0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
26134. BIFPLR0_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
26135. BIFPLR0_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
26136. BIFPLR0_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
26137. BIFPLR0_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
26138. BIFPLR0_0_MSI_MAP_CAP_LIST__CAP_ID_MASK
26139. BIFPLR0_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
26140. BIFPLR0_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
26141. BIFPLR0_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
26142. BIFPLR0_0_MSI_MAP_CAP__CAP_TYPE_MASK
26143. BIFPLR0_0_MSI_MAP_CAP__CAP_TYPE__SHIFT
26144. BIFPLR0_0_MSI_MAP_CAP__EN_MASK
26145. BIFPLR0_0_MSI_MAP_CAP__EN__SHIFT
26146. BIFPLR0_0_MSI_MAP_CAP__FIXD_MASK
26147. BIFPLR0_0_MSI_MAP_CAP__FIXD__SHIFT
26148. BIFPLR0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
26149. BIFPLR0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
26150. BIFPLR0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
26151. BIFPLR0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
26152. BIFPLR0_0_MSI_MSG_CNTL__MSI_64BIT_MASK
26153. BIFPLR0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
26154. BIFPLR0_0_MSI_MSG_CNTL__MSI_EN_MASK
26155. BIFPLR0_0_MSI_MSG_CNTL__MSI_EN__SHIFT
26156. BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
26157. BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
26158. BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
26159. BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
26160. BIFPLR0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
26161. BIFPLR0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
26162. BIFPLR0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
26163. BIFPLR0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
26164. BIFPLR0_0_MSI_MSG_DATA__MSI_DATA_MASK
26165. BIFPLR0_0_MSI_MSG_DATA__MSI_DATA__SHIFT
26166. BIFPLR0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
26167. BIFPLR0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
26168. BIFPLR0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
26169. BIFPLR0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
26170. BIFPLR0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
26171. BIFPLR0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
26172. BIFPLR0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
26173. BIFPLR0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
26174. BIFPLR0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
26175. BIFPLR0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
26176. BIFPLR0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
26177. BIFPLR0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
26178. BIFPLR0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
26179. BIFPLR0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
26180. BIFPLR0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
26181. BIFPLR0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
26182. BIFPLR0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
26183. BIFPLR0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
26184. BIFPLR0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
26185. BIFPLR0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
26186. BIFPLR0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
26187. BIFPLR0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
26188. BIFPLR0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
26189. BIFPLR0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
26190. BIFPLR0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
26191. BIFPLR0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
26192. BIFPLR0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
26193. BIFPLR0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
26194. BIFPLR0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
26195. BIFPLR0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
26196. BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
26197. BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
26198. BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
26199. BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
26200. BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
26201. BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
26202. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
26203. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
26204. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
26205. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
26206. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
26207. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
26208. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
26209. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
26210. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
26211. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
26212. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
26213. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
26214. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
26215. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
26216. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
26217. BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
26218. BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
26219. BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
26220. BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
26221. BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
26222. BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
26223. BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
26224. BIFPLR0_0_PCIE_CAP_LIST__CAP_ID_MASK
26225. BIFPLR0_0_PCIE_CAP_LIST__CAP_ID__SHIFT
26226. BIFPLR0_0_PCIE_CAP_LIST__NEXT_PTR_MASK
26227. BIFPLR0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
26228. BIFPLR0_0_PCIE_CAP__DEVICE_TYPE_MASK
26229. BIFPLR0_0_PCIE_CAP__DEVICE_TYPE__SHIFT
26230. BIFPLR0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
26231. BIFPLR0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
26232. BIFPLR0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
26233. BIFPLR0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
26234. BIFPLR0_0_PCIE_CAP__VERSION_MASK
26235. BIFPLR0_0_PCIE_CAP__VERSION__SHIFT
26236. BIFPLR0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
26237. BIFPLR0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
26238. BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
26239. BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
26240. BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
26241. BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
26242. BIFPLR0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
26243. BIFPLR0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
26244. BIFPLR0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
26245. BIFPLR0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
26246. BIFPLR0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
26247. BIFPLR0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
26248. BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
26249. BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
26250. BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
26251. BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
26252. BIFPLR0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
26253. BIFPLR0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
26254. BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
26255. BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
26256. BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
26257. BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
26258. BIFPLR0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
26259. BIFPLR0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
26260. BIFPLR0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
26261. BIFPLR0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
26262. BIFPLR0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
26263. BIFPLR0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
26264. BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
26265. BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
26266. BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
26267. BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
26268. BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
26269. BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
26270. BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
26271. BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
26272. BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
26273. BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
26274. BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
26275. BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
26276. BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
26277. BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
26278. BIFPLR0_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
26279. BIFPLR0_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
26280. BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
26281. BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
26282. BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
26283. BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
26284. BIFPLR0_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
26285. BIFPLR0_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
26286. BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
26287. BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
26288. BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
26289. BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
26290. BIFPLR0_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
26291. BIFPLR0_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
26292. BIFPLR0_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
26293. BIFPLR0_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
26294. BIFPLR0_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
26295. BIFPLR0_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
26296. BIFPLR0_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
26297. BIFPLR0_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
26298. BIFPLR0_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
26299. BIFPLR0_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
26300. BIFPLR0_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
26301. BIFPLR0_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
26302. BIFPLR0_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
26303. BIFPLR0_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
26304. BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
26305. BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
26306. BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
26307. BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
26308. BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
26309. BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
26310. BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
26311. BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
26312. BIFPLR0_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
26313. BIFPLR0_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
26314. BIFPLR0_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
26315. BIFPLR0_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
26316. BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
26317. BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
26318. BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
26319. BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
26320. BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
26321. BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
26322. BIFPLR0_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
26323. BIFPLR0_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
26324. BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
26325. BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
26326. BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
26327. BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
26328. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK
26329. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
26330. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK
26331. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
26332. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK
26333. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
26334. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK
26335. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
26336. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK
26337. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
26338. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK
26339. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
26340. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK
26341. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
26342. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK
26343. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
26344. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK
26345. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
26346. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK
26347. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
26348. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK
26349. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
26350. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK
26351. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
26352. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK
26353. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
26354. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK
26355. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
26356. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK
26357. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
26358. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK
26359. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
26360. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK
26361. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
26362. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK
26363. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
26364. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK
26365. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
26366. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK
26367. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
26368. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK
26369. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
26370. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK
26371. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
26372. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK
26373. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
26374. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK
26375. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
26376. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK
26377. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
26378. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK
26379. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
26380. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK
26381. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
26382. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK
26383. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
26384. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK
26385. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
26386. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK
26387. BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
26388. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK
26389. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
26390. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK
26391. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
26392. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK
26393. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
26394. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK
26395. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
26396. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK
26397. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
26398. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK
26399. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
26400. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK
26401. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
26402. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK
26403. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
26404. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK
26405. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
26406. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK
26407. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
26408. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK
26409. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
26410. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK
26411. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
26412. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK
26413. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
26414. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK
26415. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
26416. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK
26417. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
26418. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK
26419. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
26420. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK
26421. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
26422. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK
26423. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
26424. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK
26425. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
26426. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK
26427. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
26428. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK
26429. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
26430. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK
26431. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
26432. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK
26433. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
26434. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK
26435. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
26436. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK
26437. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
26438. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK
26439. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
26440. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK
26441. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
26442. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK
26443. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
26444. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK
26445. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
26446. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK
26447. BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
26448. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK
26449. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
26450. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK
26451. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
26452. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK
26453. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
26454. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK
26455. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
26456. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK
26457. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
26458. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK
26459. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
26460. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK
26461. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
26462. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK
26463. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
26464. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK
26465. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
26466. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK
26467. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
26468. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK
26469. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
26470. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK
26471. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
26472. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK
26473. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
26474. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK
26475. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
26476. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK
26477. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
26478. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK
26479. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
26480. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK
26481. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
26482. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK
26483. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
26484. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK
26485. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
26486. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK
26487. BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
26488. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK
26489. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
26490. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK
26491. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
26492. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK
26493. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
26494. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK
26495. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
26496. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK
26497. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
26498. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK
26499. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
26500. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK
26501. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
26502. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK
26503. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
26504. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK
26505. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
26506. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK
26507. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
26508. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK
26509. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
26510. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK
26511. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
26512. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK
26513. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
26514. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK
26515. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
26516. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK
26517. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
26518. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK
26519. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
26520. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK
26521. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
26522. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK
26523. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
26524. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK
26525. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
26526. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK
26527. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
26528. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK
26529. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
26530. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK
26531. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
26532. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK
26533. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
26534. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK
26535. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
26536. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK
26537. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
26538. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK
26539. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
26540. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK
26541. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
26542. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK
26543. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
26544. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK
26545. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
26546. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK
26547. BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
26548. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK
26549. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
26550. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK
26551. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
26552. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK
26553. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
26554. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK
26555. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
26556. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK
26557. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
26558. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK
26559. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
26560. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK
26561. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
26562. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK
26563. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
26564. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK
26565. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
26566. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK
26567. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
26568. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK
26569. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
26570. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK
26571. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
26572. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK
26573. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
26574. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK
26575. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
26576. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK
26577. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
26578. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK
26579. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
26580. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK
26581. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
26582. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK
26583. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
26584. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK
26585. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
26586. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK
26587. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
26588. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK
26589. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
26590. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK
26591. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
26592. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK
26593. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
26594. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK
26595. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
26596. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK
26597. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
26598. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK
26599. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
26600. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK
26601. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
26602. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK
26603. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
26604. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK
26605. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
26606. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK
26607. BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
26608. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK
26609. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
26610. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK
26611. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
26612. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK
26613. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
26614. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK
26615. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
26616. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK
26617. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
26618. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK
26619. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
26620. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK
26621. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
26622. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK
26623. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
26624. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK
26625. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
26626. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK
26627. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
26628. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK
26629. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
26630. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK
26631. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
26632. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK
26633. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
26634. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK
26635. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
26636. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK
26637. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
26638. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK
26639. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
26640. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK
26641. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
26642. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK
26643. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
26644. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK
26645. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
26646. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK
26647. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
26648. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK
26649. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
26650. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK
26651. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
26652. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK
26653. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
26654. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK
26655. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
26656. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK
26657. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
26658. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK
26659. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
26660. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK
26661. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
26662. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK
26663. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
26664. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK
26665. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
26666. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK
26667. BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
26668. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK
26669. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
26670. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK
26671. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
26672. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK
26673. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
26674. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK
26675. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
26676. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK
26677. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
26678. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK
26679. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
26680. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK
26681. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
26682. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK
26683. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
26684. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK
26685. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
26686. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK
26687. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
26688. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK
26689. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
26690. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK
26691. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
26692. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK
26693. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
26694. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK
26695. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
26696. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK
26697. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
26698. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK
26699. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
26700. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK
26701. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
26702. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK
26703. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
26704. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK
26705. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
26706. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK
26707. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
26708. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK
26709. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
26710. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK
26711. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
26712. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK
26713. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
26714. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK
26715. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
26716. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK
26717. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
26718. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK
26719. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
26720. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK
26721. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
26722. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK
26723. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
26724. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK
26725. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
26726. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK
26727. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
26728. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK
26729. BIFPLR0_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
26730. BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK
26731. BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
26732. BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK
26733. BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
26734. BIFPLR0_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
26735. BIFPLR0_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
26736. BIFPLR0_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK
26737. BIFPLR0_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
26738. BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
26739. BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
26740. BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
26741. BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
26742. BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
26743. BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
26744. BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
26745. BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
26746. BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
26747. BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
26748. BIFPLR0_0_PCIE_ESM_HEADER_2__CAP_ID_MASK
26749. BIFPLR0_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
26750. BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
26751. BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
26752. BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
26753. BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
26754. BIFPLR0_0_PCIE_HDR_LOG0__TLP_HDR_MASK
26755. BIFPLR0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
26756. BIFPLR0_0_PCIE_HDR_LOG1__TLP_HDR_MASK
26757. BIFPLR0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
26758. BIFPLR0_0_PCIE_HDR_LOG2__TLP_HDR_MASK
26759. BIFPLR0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
26760. BIFPLR0_0_PCIE_HDR_LOG3__TLP_HDR_MASK
26761. BIFPLR0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
26762. BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
26763. BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
26764. BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
26765. BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
26766. BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
26767. BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
26768. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
26769. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
26770. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
26771. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
26772. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
26773. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
26774. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
26775. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
26776. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
26777. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
26778. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
26779. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
26780. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
26781. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
26782. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
26783. BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
26784. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
26785. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
26786. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
26787. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
26788. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
26789. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
26790. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
26791. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
26792. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
26793. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
26794. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
26795. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
26796. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
26797. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
26798. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
26799. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
26800. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
26801. BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
26802. BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26803. BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26804. BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26805. BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26806. BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26807. BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26808. BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26809. BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26810. BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26811. BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26812. BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26813. BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26814. BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26815. BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26816. BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26817. BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26818. BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26819. BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26820. BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26821. BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26822. BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26823. BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26824. BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26825. BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26826. BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26827. BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26828. BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26829. BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26830. BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26831. BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26832. BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26833. BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26834. BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26835. BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26836. BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26837. BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26838. BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26839. BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26840. BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26841. BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26842. BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26843. BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26844. BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26845. BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26846. BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26847. BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26848. BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26849. BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26850. BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26851. BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26852. BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26853. BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26854. BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26855. BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26856. BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26857. BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26858. BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26859. BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26860. BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26861. BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26862. BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26863. BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26864. BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26865. BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26866. BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26867. BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26868. BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26869. BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26870. BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26871. BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26872. BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26873. BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26874. BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26875. BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26876. BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26877. BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26878. BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26879. BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26880. BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26881. BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26882. BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26883. BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26884. BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26885. BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26886. BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26887. BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26888. BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26889. BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26890. BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26891. BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26892. BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26893. BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26894. BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26895. BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26896. BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26897. BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26898. BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26899. BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26900. BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26901. BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26902. BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26903. BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26904. BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26905. BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26906. BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26907. BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26908. BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26909. BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26910. BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26911. BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26912. BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26913. BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26914. BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26915. BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26916. BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26917. BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26918. BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26919. BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26920. BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26921. BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26922. BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
26923. BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
26924. BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
26925. BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
26926. BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
26927. BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
26928. BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
26929. BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
26930. BIFPLR0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
26931. BIFPLR0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
26932. BIFPLR0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
26933. BIFPLR0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
26934. BIFPLR0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
26935. BIFPLR0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
26936. BIFPLR0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
26937. BIFPLR0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
26938. BIFPLR0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
26939. BIFPLR0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
26940. BIFPLR0_0_PCIE_LINK_CNTL3__RESERVED_MASK
26941. BIFPLR0_0_PCIE_LINK_CNTL3__RESERVED__SHIFT
26942. BIFPLR0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
26943. BIFPLR0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
26944. BIFPLR0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
26945. BIFPLR0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
26946. BIFPLR0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
26947. BIFPLR0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
26948. BIFPLR0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
26949. BIFPLR0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
26950. BIFPLR0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
26951. BIFPLR0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
26952. BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
26953. BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
26954. BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
26955. BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
26956. BIFPLR0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
26957. BIFPLR0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
26958. BIFPLR0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK
26959. BIFPLR0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
26960. BIFPLR0_0_PCIE_MC_CNTL__MC_ENABLE_MASK
26961. BIFPLR0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT
26962. BIFPLR0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
26963. BIFPLR0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
26964. BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
26965. BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
26966. BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
26967. BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
26968. BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
26969. BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
26970. BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
26971. BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
26972. BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
26973. BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
26974. BIFPLR0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
26975. BIFPLR0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
26976. BIFPLR0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
26977. BIFPLR0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
26978. BIFPLR0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
26979. BIFPLR0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
26980. BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
26981. BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
26982. BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
26983. BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
26984. BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
26985. BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
26986. BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
26987. BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
26988. BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
26989. BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
26990. BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
26991. BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
26992. BIFPLR0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
26993. BIFPLR0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
26994. BIFPLR0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
26995. BIFPLR0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
26996. BIFPLR0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
26997. BIFPLR0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
26998. BIFPLR0_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
26999. BIFPLR0_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
27000. BIFPLR0_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
27001. BIFPLR0_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
27002. BIFPLR0_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
27003. BIFPLR0_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
27004. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
27005. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
27006. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
27007. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
27008. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
27009. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
27010. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
27011. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
27012. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
27013. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
27014. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
27015. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
27016. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
27017. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
27018. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
27019. BIFPLR0_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
27020. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
27021. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
27022. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
27023. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
27024. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
27025. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
27026. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
27027. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
27028. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
27029. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
27030. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
27031. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
27032. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
27033. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
27034. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
27035. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
27036. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
27037. BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
27038. BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
27039. BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
27040. BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
27041. BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
27042. BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
27043. BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
27044. BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
27045. BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
27046. BIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
27047. BIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
27048. BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
27049. BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
27050. BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK
27051. BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
27052. BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
27053. BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
27054. BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
27055. BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
27056. BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CTO_MASK
27057. BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
27058. BIFPLR0_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
27059. BIFPLR0_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
27060. BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
27061. BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
27062. BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK
27063. BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
27064. BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
27065. BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
27066. BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
27067. BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
27068. BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
27069. BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
27070. BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
27071. BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
27072. BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
27073. BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
27074. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
27075. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
27076. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
27077. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
27078. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
27079. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
27080. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
27081. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
27082. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
27083. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
27084. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
27085. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
27086. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
27087. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
27088. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
27089. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
27090. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
27091. BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
27092. BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
27093. BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
27094. BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
27095. BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
27096. BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
27097. BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
27098. BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
27099. BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
27100. BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK
27101. BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
27102. BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
27103. BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
27104. BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
27105. BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
27106. BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
27107. BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
27108. BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
27109. BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
27110. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
27111. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
27112. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
27113. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
27114. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
27115. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
27116. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
27117. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
27118. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
27119. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
27120. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
27121. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
27122. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
27123. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
27124. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
27125. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
27126. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
27127. BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
27128. BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
27129. BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
27130. BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
27131. BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
27132. BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
27133. BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
27134. BIFPLR0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
27135. BIFPLR0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
27136. BIFPLR0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
27137. BIFPLR0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
27138. BIFPLR0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
27139. BIFPLR0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
27140. BIFPLR0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
27141. BIFPLR0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
27142. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
27143. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
27144. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
27145. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
27146. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
27147. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
27148. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
27149. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
27150. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
27151. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
27152. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
27153. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
27154. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
27155. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
27156. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
27157. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
27158. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
27159. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
27160. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
27161. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
27162. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
27163. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
27164. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
27165. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
27166. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
27167. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
27168. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
27169. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
27170. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
27171. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
27172. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
27173. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
27174. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
27175. BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
27176. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
27177. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
27178. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
27179. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
27180. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
27181. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
27182. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
27183. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
27184. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
27185. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
27186. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
27187. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
27188. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
27189. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
27190. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
27191. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
27192. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
27193. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
27194. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
27195. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
27196. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
27197. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
27198. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
27199. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
27200. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
27201. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
27202. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
27203. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
27204. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
27205. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
27206. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
27207. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
27208. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
27209. BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
27210. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
27211. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
27212. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
27213. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
27214. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
27215. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
27216. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
27217. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
27218. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
27219. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
27220. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
27221. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
27222. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
27223. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
27224. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
27225. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
27226. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
27227. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
27228. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
27229. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
27230. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
27231. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
27232. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
27233. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
27234. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
27235. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
27236. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
27237. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
27238. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
27239. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
27240. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
27241. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
27242. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
27243. BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
27244. BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
27245. BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
27246. BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
27247. BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
27248. BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
27249. BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
27250. BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
27251. BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
27252. BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
27253. BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
27254. BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
27255. BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
27256. BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
27257. BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
27258. BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
27259. BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
27260. BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
27261. BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
27262. BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
27263. BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
27264. BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
27265. BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
27266. BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
27267. BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
27268. BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
27269. BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
27270. BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
27271. BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
27272. BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
27273. BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
27274. BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
27275. BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
27276. BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
27277. BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
27278. BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
27279. BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
27280. BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
27281. BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
27282. BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
27283. BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
27284. BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
27285. BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
27286. BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
27287. BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
27288. BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
27289. BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
27290. BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
27291. BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
27292. BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
27293. BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
27294. BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
27295. BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
27296. BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
27297. BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
27298. BIFPLR0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
27299. BIFPLR0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
27300. BIFPLR0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
27301. BIFPLR0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
27302. BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
27303. BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
27304. BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
27305. BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
27306. BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
27307. BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
27308. BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
27309. BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
27310. BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
27311. BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
27312. BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
27313. BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
27314. BIFPLR0_0_PMI_CAP_LIST__CAP_ID_MASK
27315. BIFPLR0_0_PMI_CAP_LIST__CAP_ID__SHIFT
27316. BIFPLR0_0_PMI_CAP_LIST__NEXT_PTR_MASK
27317. BIFPLR0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
27318. BIFPLR0_0_PMI_CAP__AUX_CURRENT_MASK
27319. BIFPLR0_0_PMI_CAP__AUX_CURRENT__SHIFT
27320. BIFPLR0_0_PMI_CAP__D1_SUPPORT_MASK
27321. BIFPLR0_0_PMI_CAP__D1_SUPPORT__SHIFT
27322. BIFPLR0_0_PMI_CAP__D2_SUPPORT_MASK
27323. BIFPLR0_0_PMI_CAP__D2_SUPPORT__SHIFT
27324. BIFPLR0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
27325. BIFPLR0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
27326. BIFPLR0_0_PMI_CAP__PME_CLOCK_MASK
27327. BIFPLR0_0_PMI_CAP__PME_CLOCK__SHIFT
27328. BIFPLR0_0_PMI_CAP__PME_SUPPORT_MASK
27329. BIFPLR0_0_PMI_CAP__PME_SUPPORT__SHIFT
27330. BIFPLR0_0_PMI_CAP__VERSION_MASK
27331. BIFPLR0_0_PMI_CAP__VERSION__SHIFT
27332. BIFPLR0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
27333. BIFPLR0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
27334. BIFPLR0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
27335. BIFPLR0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
27336. BIFPLR0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
27337. BIFPLR0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
27338. BIFPLR0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
27339. BIFPLR0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
27340. BIFPLR0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
27341. BIFPLR0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
27342. BIFPLR0_0_PMI_STATUS_CNTL__PME_EN_MASK
27343. BIFPLR0_0_PMI_STATUS_CNTL__PME_EN__SHIFT
27344. BIFPLR0_0_PMI_STATUS_CNTL__PME_STATUS_MASK
27345. BIFPLR0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
27346. BIFPLR0_0_PMI_STATUS_CNTL__PMI_DATA_MASK
27347. BIFPLR0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
27348. BIFPLR0_0_PMI_STATUS_CNTL__POWER_STATE_MASK
27349. BIFPLR0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
27350. BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
27351. BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
27352. BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
27353. BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
27354. BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
27355. BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
27356. BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
27357. BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
27358. BIFPLR0_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
27359. BIFPLR0_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
27360. BIFPLR0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
27361. BIFPLR0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
27362. BIFPLR0_0_PROG_INTERFACE__PROG_INTERFACE_MASK
27363. BIFPLR0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
27364. BIFPLR0_0_REVISION_ID__MAJOR_REV_ID_MASK
27365. BIFPLR0_0_REVISION_ID__MAJOR_REV_ID__SHIFT
27366. BIFPLR0_0_REVISION_ID__MINOR_REV_ID_MASK
27367. BIFPLR0_0_REVISION_ID__MINOR_REV_ID__SHIFT
27368. BIFPLR0_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
27369. BIFPLR0_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
27370. BIFPLR0_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
27371. BIFPLR0_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
27372. BIFPLR0_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK
27373. BIFPLR0_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
27374. BIFPLR0_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
27375. BIFPLR0_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
27376. BIFPLR0_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
27377. BIFPLR0_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
27378. BIFPLR0_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
27379. BIFPLR0_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
27380. BIFPLR0_0_ROOT_STATUS__PME_PENDING_MASK
27381. BIFPLR0_0_ROOT_STATUS__PME_PENDING__SHIFT
27382. BIFPLR0_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK
27383. BIFPLR0_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
27384. BIFPLR0_0_ROOT_STATUS__PME_STATUS_MASK
27385. BIFPLR0_0_ROOT_STATUS__PME_STATUS__SHIFT
27386. BIFPLR0_0_SECONDARY_STATUS__CAP_LIST_MASK
27387. BIFPLR0_0_SECONDARY_STATUS__CAP_LIST__SHIFT
27388. BIFPLR0_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK
27389. BIFPLR0_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
27390. BIFPLR0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
27391. BIFPLR0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
27392. BIFPLR0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
27393. BIFPLR0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
27394. BIFPLR0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
27395. BIFPLR0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
27396. BIFPLR0_0_SECONDARY_STATUS__PCI_66_EN_MASK
27397. BIFPLR0_0_SECONDARY_STATUS__PCI_66_EN__SHIFT
27398. BIFPLR0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
27399. BIFPLR0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
27400. BIFPLR0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
27401. BIFPLR0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
27402. BIFPLR0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
27403. BIFPLR0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
27404. BIFPLR0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
27405. BIFPLR0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
27406. BIFPLR0_0_SLOT_CAP2__RESERVED_MASK
27407. BIFPLR0_0_SLOT_CAP2__RESERVED__SHIFT
27408. BIFPLR0_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
27409. BIFPLR0_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
27410. BIFPLR0_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
27411. BIFPLR0_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
27412. BIFPLR0_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
27413. BIFPLR0_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
27414. BIFPLR0_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK
27415. BIFPLR0_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
27416. BIFPLR0_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK
27417. BIFPLR0_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
27418. BIFPLR0_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
27419. BIFPLR0_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
27420. BIFPLR0_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
27421. BIFPLR0_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
27422. BIFPLR0_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
27423. BIFPLR0_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
27424. BIFPLR0_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
27425. BIFPLR0_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
27426. BIFPLR0_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
27427. BIFPLR0_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
27428. BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
27429. BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
27430. BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
27431. BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
27432. BIFPLR0_0_SLOT_CNTL2__RESERVED_MASK
27433. BIFPLR0_0_SLOT_CNTL2__RESERVED__SHIFT
27434. BIFPLR0_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
27435. BIFPLR0_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
27436. BIFPLR0_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
27437. BIFPLR0_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
27438. BIFPLR0_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
27439. BIFPLR0_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
27440. BIFPLR0_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
27441. BIFPLR0_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
27442. BIFPLR0_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
27443. BIFPLR0_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
27444. BIFPLR0_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
27445. BIFPLR0_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
27446. BIFPLR0_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
27447. BIFPLR0_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
27448. BIFPLR0_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
27449. BIFPLR0_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
27450. BIFPLR0_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
27451. BIFPLR0_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
27452. BIFPLR0_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
27453. BIFPLR0_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
27454. BIFPLR0_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
27455. BIFPLR0_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
27456. BIFPLR0_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
27457. BIFPLR0_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
27458. BIFPLR0_0_SLOT_STATUS2__RESERVED_MASK
27459. BIFPLR0_0_SLOT_STATUS2__RESERVED__SHIFT
27460. BIFPLR0_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
27461. BIFPLR0_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
27462. BIFPLR0_0_SLOT_STATUS__COMMAND_COMPLETED_MASK
27463. BIFPLR0_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
27464. BIFPLR0_0_SLOT_STATUS__DL_STATE_CHANGED_MASK
27465. BIFPLR0_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
27466. BIFPLR0_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
27467. BIFPLR0_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
27468. BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
27469. BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
27470. BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK
27471. BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
27472. BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
27473. BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
27474. BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
27475. BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
27476. BIFPLR0_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
27477. BIFPLR0_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
27478. BIFPLR0_0_SSID_CAP_LIST__CAP_ID_MASK
27479. BIFPLR0_0_SSID_CAP_LIST__CAP_ID__SHIFT
27480. BIFPLR0_0_SSID_CAP_LIST__NEXT_PTR_MASK
27481. BIFPLR0_0_SSID_CAP_LIST__NEXT_PTR__SHIFT
27482. BIFPLR0_0_SSID_CAP__SUBSYSTEM_ID_MASK
27483. BIFPLR0_0_SSID_CAP__SUBSYSTEM_ID__SHIFT
27484. BIFPLR0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
27485. BIFPLR0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
27486. BIFPLR0_0_STATUS__CAP_LIST_MASK
27487. BIFPLR0_0_STATUS__CAP_LIST__SHIFT
27488. BIFPLR0_0_STATUS__DEVSEL_TIMING_MASK
27489. BIFPLR0_0_STATUS__DEVSEL_TIMING__SHIFT
27490. BIFPLR0_0_STATUS__FAST_BACK_CAPABLE_MASK
27491. BIFPLR0_0_STATUS__FAST_BACK_CAPABLE__SHIFT
27492. BIFPLR0_0_STATUS__INT_STATUS_MASK
27493. BIFPLR0_0_STATUS__INT_STATUS__SHIFT
27494. BIFPLR0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
27495. BIFPLR0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
27496. BIFPLR0_0_STATUS__PARITY_ERROR_DETECTED_MASK
27497. BIFPLR0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
27498. BIFPLR0_0_STATUS__PCI_66_EN_MASK
27499. BIFPLR0_0_STATUS__PCI_66_EN__SHIFT
27500. BIFPLR0_0_STATUS__RECEIVED_MASTER_ABORT_MASK
27501. BIFPLR0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
27502. BIFPLR0_0_STATUS__RECEIVED_TARGET_ABORT_MASK
27503. BIFPLR0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
27504. BIFPLR0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
27505. BIFPLR0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
27506. BIFPLR0_0_STATUS__SIGNAL_TARGET_ABORT_MASK
27507. BIFPLR0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
27508. BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
27509. BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
27510. BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
27511. BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
27512. BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
27513. BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
27514. BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
27515. BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
27516. BIFPLR0_0_SUB_CLASS__SUB_CLASS_MASK
27517. BIFPLR0_0_SUB_CLASS__SUB_CLASS__SHIFT
27518. BIFPLR0_0_VENDOR_ID__VENDOR_ID_MASK
27519. BIFPLR0_0_VENDOR_ID__VENDOR_ID__SHIFT
27520. BIFPLR0_1_BASE_CLASS__BASE_CLASS_MASK
27521. BIFPLR0_1_BASE_CLASS__BASE_CLASS__SHIFT
27522. BIFPLR0_1_BIST__BIST_CAP_MASK
27523. BIFPLR0_1_BIST__BIST_CAP__SHIFT
27524. BIFPLR0_1_BIST__BIST_COMP_MASK
27525. BIFPLR0_1_BIST__BIST_COMP__SHIFT
27526. BIFPLR0_1_BIST__BIST_STRT_MASK
27527. BIFPLR0_1_BIST__BIST_STRT__SHIFT
27528. BIFPLR0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
27529. BIFPLR0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
27530. BIFPLR0_1_CAP_PTR__CAP_PTR_MASK
27531. BIFPLR0_1_CAP_PTR__CAP_PTR__SHIFT
27532. BIFPLR0_1_COMMAND__AD_STEPPING_MASK
27533. BIFPLR0_1_COMMAND__AD_STEPPING__SHIFT
27534. BIFPLR0_1_COMMAND__BUS_MASTER_EN_MASK
27535. BIFPLR0_1_COMMAND__BUS_MASTER_EN__SHIFT
27536. BIFPLR0_1_COMMAND__FAST_B2B_EN_MASK
27537. BIFPLR0_1_COMMAND__FAST_B2B_EN__SHIFT
27538. BIFPLR0_1_COMMAND__INT_DIS_MASK
27539. BIFPLR0_1_COMMAND__INT_DIS__SHIFT
27540. BIFPLR0_1_COMMAND__IO_ACCESS_EN_MASK
27541. BIFPLR0_1_COMMAND__IO_ACCESS_EN__SHIFT
27542. BIFPLR0_1_COMMAND__MEM_ACCESS_EN_MASK
27543. BIFPLR0_1_COMMAND__MEM_ACCESS_EN__SHIFT
27544. BIFPLR0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
27545. BIFPLR0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
27546. BIFPLR0_1_COMMAND__PAL_SNOOP_EN_MASK
27547. BIFPLR0_1_COMMAND__PAL_SNOOP_EN__SHIFT
27548. BIFPLR0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
27549. BIFPLR0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
27550. BIFPLR0_1_COMMAND__SERR_EN_MASK
27551. BIFPLR0_1_COMMAND__SERR_EN__SHIFT
27552. BIFPLR0_1_COMMAND__SPECIAL_CYCLE_EN_MASK
27553. BIFPLR0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
27554. BIFPLR0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
27555. BIFPLR0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
27556. BIFPLR0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
27557. BIFPLR0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
27558. BIFPLR0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
27559. BIFPLR0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
27560. BIFPLR0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
27561. BIFPLR0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
27562. BIFPLR0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
27563. BIFPLR0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
27564. BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
27565. BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
27566. BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
27567. BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
27568. BIFPLR0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
27569. BIFPLR0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
27570. BIFPLR0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
27571. BIFPLR0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
27572. BIFPLR0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
27573. BIFPLR0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
27574. BIFPLR0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
27575. BIFPLR0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
27576. BIFPLR0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
27577. BIFPLR0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
27578. BIFPLR0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
27579. BIFPLR0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
27580. BIFPLR0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
27581. BIFPLR0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
27582. BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
27583. BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
27584. BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
27585. BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
27586. BIFPLR0_1_DEVICE_CAP__EXTENDED_TAG_MASK
27587. BIFPLR0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
27588. BIFPLR0_1_DEVICE_CAP__FLR_CAPABLE_MASK
27589. BIFPLR0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
27590. BIFPLR0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
27591. BIFPLR0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
27592. BIFPLR0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
27593. BIFPLR0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
27594. BIFPLR0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
27595. BIFPLR0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
27596. BIFPLR0_1_DEVICE_CAP__PHANTOM_FUNC_MASK
27597. BIFPLR0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
27598. BIFPLR0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
27599. BIFPLR0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
27600. BIFPLR0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
27601. BIFPLR0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
27602. BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
27603. BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
27604. BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
27605. BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
27606. BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
27607. BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
27608. BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
27609. BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
27610. BIFPLR0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
27611. BIFPLR0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
27612. BIFPLR0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
27613. BIFPLR0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
27614. BIFPLR0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
27615. BIFPLR0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
27616. BIFPLR0_1_DEVICE_CNTL2__LTR_EN_MASK
27617. BIFPLR0_1_DEVICE_CNTL2__LTR_EN__SHIFT
27618. BIFPLR0_1_DEVICE_CNTL2__OBFF_EN_MASK
27619. BIFPLR0_1_DEVICE_CNTL2__OBFF_EN__SHIFT
27620. BIFPLR0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
27621. BIFPLR0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
27622. BIFPLR0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
27623. BIFPLR0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
27624. BIFPLR0_1_DEVICE_CNTL__CORR_ERR_EN_MASK
27625. BIFPLR0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
27626. BIFPLR0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
27627. BIFPLR0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
27628. BIFPLR0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
27629. BIFPLR0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
27630. BIFPLR0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
27631. BIFPLR0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
27632. BIFPLR0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
27633. BIFPLR0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
27634. BIFPLR0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
27635. BIFPLR0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
27636. BIFPLR0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
27637. BIFPLR0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
27638. BIFPLR0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
27639. BIFPLR0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
27640. BIFPLR0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
27641. BIFPLR0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
27642. BIFPLR0_1_DEVICE_CNTL__USR_REPORT_EN_MASK
27643. BIFPLR0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
27644. BIFPLR0_1_DEVICE_ID__DEVICE_ID_MASK
27645. BIFPLR0_1_DEVICE_ID__DEVICE_ID__SHIFT
27646. BIFPLR0_1_DEVICE_STATUS2__RESERVED_MASK
27647. BIFPLR0_1_DEVICE_STATUS2__RESERVED__SHIFT
27648. BIFPLR0_1_DEVICE_STATUS__AUX_PWR_MASK
27649. BIFPLR0_1_DEVICE_STATUS__AUX_PWR__SHIFT
27650. BIFPLR0_1_DEVICE_STATUS__CORR_ERR_MASK
27651. BIFPLR0_1_DEVICE_STATUS__CORR_ERR__SHIFT
27652. BIFPLR0_1_DEVICE_STATUS__FATAL_ERR_MASK
27653. BIFPLR0_1_DEVICE_STATUS__FATAL_ERR__SHIFT
27654. BIFPLR0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
27655. BIFPLR0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
27656. BIFPLR0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
27657. BIFPLR0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
27658. BIFPLR0_1_DEVICE_STATUS__USR_DETECTED_MASK
27659. BIFPLR0_1_DEVICE_STATUS__USR_DETECTED__SHIFT
27660. BIFPLR0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
27661. BIFPLR0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
27662. BIFPLR0_1_HEADER__DEVICE_TYPE_MASK
27663. BIFPLR0_1_HEADER__DEVICE_TYPE__SHIFT
27664. BIFPLR0_1_HEADER__HEADER_TYPE_MASK
27665. BIFPLR0_1_HEADER__HEADER_TYPE__SHIFT
27666. BIFPLR0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
27667. BIFPLR0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
27668. BIFPLR0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
27669. BIFPLR0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
27670. BIFPLR0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
27671. BIFPLR0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
27672. BIFPLR0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
27673. BIFPLR0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
27674. BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_MASK
27675. BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
27676. BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
27677. BIFPLR0_1_IO_BASE_LIMIT__IO_BASE__SHIFT
27678. BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_MASK
27679. BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
27680. BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
27681. BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT
27682. BIFPLR0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
27683. BIFPLR0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
27684. BIFPLR0_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK
27685. BIFPLR0_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
27686. BIFPLR0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
27687. BIFPLR0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
27688. BIFPLR0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
27689. BIFPLR0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
27690. BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
27691. BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
27692. BIFPLR0_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK
27693. BIFPLR0_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
27694. BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
27695. BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
27696. BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK
27697. BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
27698. BIFPLR0_1_LATENCY__LATENCY_TIMER_MASK
27699. BIFPLR0_1_LATENCY__LATENCY_TIMER__SHIFT
27700. BIFPLR0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
27701. BIFPLR0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
27702. BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
27703. BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
27704. BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
27705. BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
27706. BIFPLR0_1_LINK_CAP2__RESERVED_MASK
27707. BIFPLR0_1_LINK_CAP2__RESERVED__SHIFT
27708. BIFPLR0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
27709. BIFPLR0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
27710. BIFPLR0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
27711. BIFPLR0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
27712. BIFPLR0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
27713. BIFPLR0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
27714. BIFPLR0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
27715. BIFPLR0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
27716. BIFPLR0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
27717. BIFPLR0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
27718. BIFPLR0_1_LINK_CAP__L1_EXIT_LATENCY_MASK
27719. BIFPLR0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
27720. BIFPLR0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
27721. BIFPLR0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
27722. BIFPLR0_1_LINK_CAP__LINK_SPEED_MASK
27723. BIFPLR0_1_LINK_CAP__LINK_SPEED__SHIFT
27724. BIFPLR0_1_LINK_CAP__LINK_WIDTH_MASK
27725. BIFPLR0_1_LINK_CAP__LINK_WIDTH__SHIFT
27726. BIFPLR0_1_LINK_CAP__PM_SUPPORT_MASK
27727. BIFPLR0_1_LINK_CAP__PM_SUPPORT__SHIFT
27728. BIFPLR0_1_LINK_CAP__PORT_NUMBER_MASK
27729. BIFPLR0_1_LINK_CAP__PORT_NUMBER__SHIFT
27730. BIFPLR0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
27731. BIFPLR0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
27732. BIFPLR0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
27733. BIFPLR0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
27734. BIFPLR0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
27735. BIFPLR0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
27736. BIFPLR0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
27737. BIFPLR0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
27738. BIFPLR0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
27739. BIFPLR0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
27740. BIFPLR0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
27741. BIFPLR0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
27742. BIFPLR0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
27743. BIFPLR0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
27744. BIFPLR0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
27745. BIFPLR0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
27746. BIFPLR0_1_LINK_CNTL2__XMIT_MARGIN_MASK
27747. BIFPLR0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
27748. BIFPLR0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
27749. BIFPLR0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
27750. BIFPLR0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
27751. BIFPLR0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
27752. BIFPLR0_1_LINK_CNTL__EXTENDED_SYNC_MASK
27753. BIFPLR0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
27754. BIFPLR0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
27755. BIFPLR0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
27756. BIFPLR0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
27757. BIFPLR0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
27758. BIFPLR0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
27759. BIFPLR0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
27760. BIFPLR0_1_LINK_CNTL__LINK_DIS_MASK
27761. BIFPLR0_1_LINK_CNTL__LINK_DIS__SHIFT
27762. BIFPLR0_1_LINK_CNTL__PM_CONTROL_MASK
27763. BIFPLR0_1_LINK_CNTL__PM_CONTROL__SHIFT
27764. BIFPLR0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
27765. BIFPLR0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
27766. BIFPLR0_1_LINK_CNTL__RETRAIN_LINK_MASK
27767. BIFPLR0_1_LINK_CNTL__RETRAIN_LINK__SHIFT
27768. BIFPLR0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
27769. BIFPLR0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
27770. BIFPLR0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
27771. BIFPLR0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
27772. BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
27773. BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
27774. BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
27775. BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
27776. BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
27777. BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
27778. BIFPLR0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
27779. BIFPLR0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
27780. BIFPLR0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
27781. BIFPLR0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
27782. BIFPLR0_1_LINK_STATUS__DL_ACTIVE_MASK
27783. BIFPLR0_1_LINK_STATUS__DL_ACTIVE__SHIFT
27784. BIFPLR0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
27785. BIFPLR0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
27786. BIFPLR0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
27787. BIFPLR0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
27788. BIFPLR0_1_LINK_STATUS__LINK_TRAINING_MASK
27789. BIFPLR0_1_LINK_STATUS__LINK_TRAINING__SHIFT
27790. BIFPLR0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
27791. BIFPLR0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
27792. BIFPLR0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
27793. BIFPLR0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
27794. BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
27795. BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
27796. BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
27797. BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
27798. BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
27799. BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
27800. BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
27801. BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
27802. BIFPLR0_1_MSI_CAP_LIST__CAP_ID_MASK
27803. BIFPLR0_1_MSI_CAP_LIST__CAP_ID__SHIFT
27804. BIFPLR0_1_MSI_CAP_LIST__NEXT_PTR_MASK
27805. BIFPLR0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
27806. BIFPLR0_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
27807. BIFPLR0_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
27808. BIFPLR0_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
27809. BIFPLR0_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
27810. BIFPLR0_1_MSI_MAP_CAP_LIST__CAP_ID_MASK
27811. BIFPLR0_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
27812. BIFPLR0_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
27813. BIFPLR0_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
27814. BIFPLR0_1_MSI_MAP_CAP__CAP_TYPE_MASK
27815. BIFPLR0_1_MSI_MAP_CAP__CAP_TYPE__SHIFT
27816. BIFPLR0_1_MSI_MAP_CAP__EN_MASK
27817. BIFPLR0_1_MSI_MAP_CAP__EN__SHIFT
27818. BIFPLR0_1_MSI_MAP_CAP__FIXD_MASK
27819. BIFPLR0_1_MSI_MAP_CAP__FIXD__SHIFT
27820. BIFPLR0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
27821. BIFPLR0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
27822. BIFPLR0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
27823. BIFPLR0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
27824. BIFPLR0_1_MSI_MSG_CNTL__MSI_64BIT_MASK
27825. BIFPLR0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
27826. BIFPLR0_1_MSI_MSG_CNTL__MSI_EN_MASK
27827. BIFPLR0_1_MSI_MSG_CNTL__MSI_EN__SHIFT
27828. BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
27829. BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
27830. BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
27831. BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
27832. BIFPLR0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
27833. BIFPLR0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
27834. BIFPLR0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
27835. BIFPLR0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
27836. BIFPLR0_1_MSI_MSG_DATA__MSI_DATA_MASK
27837. BIFPLR0_1_MSI_MSG_DATA__MSI_DATA__SHIFT
27838. BIFPLR0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
27839. BIFPLR0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
27840. BIFPLR0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
27841. BIFPLR0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
27842. BIFPLR0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
27843. BIFPLR0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
27844. BIFPLR0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
27845. BIFPLR0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
27846. BIFPLR0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
27847. BIFPLR0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
27848. BIFPLR0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
27849. BIFPLR0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
27850. BIFPLR0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
27851. BIFPLR0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
27852. BIFPLR0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
27853. BIFPLR0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
27854. BIFPLR0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
27855. BIFPLR0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
27856. BIFPLR0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
27857. BIFPLR0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
27858. BIFPLR0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
27859. BIFPLR0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
27860. BIFPLR0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
27861. BIFPLR0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
27862. BIFPLR0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
27863. BIFPLR0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
27864. BIFPLR0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
27865. BIFPLR0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
27866. BIFPLR0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
27867. BIFPLR0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
27868. BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
27869. BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
27870. BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
27871. BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
27872. BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
27873. BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
27874. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
27875. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
27876. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
27877. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
27878. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
27879. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
27880. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
27881. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
27882. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
27883. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
27884. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
27885. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
27886. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
27887. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
27888. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
27889. BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
27890. BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
27891. BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
27892. BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
27893. BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
27894. BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
27895. BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
27896. BIFPLR0_1_PCIE_CAP_LIST__CAP_ID_MASK
27897. BIFPLR0_1_PCIE_CAP_LIST__CAP_ID__SHIFT
27898. BIFPLR0_1_PCIE_CAP_LIST__NEXT_PTR_MASK
27899. BIFPLR0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
27900. BIFPLR0_1_PCIE_CAP__DEVICE_TYPE_MASK
27901. BIFPLR0_1_PCIE_CAP__DEVICE_TYPE__SHIFT
27902. BIFPLR0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
27903. BIFPLR0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
27904. BIFPLR0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
27905. BIFPLR0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
27906. BIFPLR0_1_PCIE_CAP__VERSION_MASK
27907. BIFPLR0_1_PCIE_CAP__VERSION__SHIFT
27908. BIFPLR0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
27909. BIFPLR0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
27910. BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
27911. BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
27912. BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
27913. BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
27914. BIFPLR0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
27915. BIFPLR0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
27916. BIFPLR0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
27917. BIFPLR0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
27918. BIFPLR0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
27919. BIFPLR0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
27920. BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
27921. BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
27922. BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
27923. BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
27924. BIFPLR0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
27925. BIFPLR0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
27926. BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
27927. BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
27928. BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
27929. BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
27930. BIFPLR0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
27931. BIFPLR0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
27932. BIFPLR0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
27933. BIFPLR0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
27934. BIFPLR0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
27935. BIFPLR0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
27936. BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
27937. BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
27938. BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
27939. BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
27940. BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
27941. BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
27942. BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
27943. BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
27944. BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
27945. BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
27946. BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
27947. BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
27948. BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
27949. BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
27950. BIFPLR0_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
27951. BIFPLR0_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
27952. BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
27953. BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
27954. BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
27955. BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
27956. BIFPLR0_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
27957. BIFPLR0_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
27958. BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
27959. BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
27960. BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
27961. BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
27962. BIFPLR0_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
27963. BIFPLR0_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
27964. BIFPLR0_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
27965. BIFPLR0_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
27966. BIFPLR0_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
27967. BIFPLR0_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
27968. BIFPLR0_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
27969. BIFPLR0_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
27970. BIFPLR0_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
27971. BIFPLR0_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
27972. BIFPLR0_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
27973. BIFPLR0_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
27974. BIFPLR0_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
27975. BIFPLR0_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
27976. BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
27977. BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
27978. BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
27979. BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
27980. BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
27981. BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
27982. BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
27983. BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
27984. BIFPLR0_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
27985. BIFPLR0_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
27986. BIFPLR0_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
27987. BIFPLR0_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
27988. BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
27989. BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
27990. BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
27991. BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
27992. BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
27993. BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
27994. BIFPLR0_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
27995. BIFPLR0_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
27996. BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
27997. BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
27998. BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
27999. BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
28000. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK
28001. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
28002. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK
28003. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
28004. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK
28005. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
28006. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK
28007. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
28008. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK
28009. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
28010. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK
28011. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
28012. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK
28013. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
28014. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK
28015. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
28016. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK
28017. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
28018. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK
28019. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
28020. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK
28021. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
28022. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK
28023. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
28024. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK
28025. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
28026. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK
28027. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
28028. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK
28029. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
28030. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK
28031. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
28032. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK
28033. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
28034. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK
28035. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
28036. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK
28037. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
28038. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK
28039. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
28040. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK
28041. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
28042. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK
28043. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
28044. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK
28045. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
28046. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK
28047. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
28048. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK
28049. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
28050. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK
28051. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
28052. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK
28053. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
28054. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK
28055. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
28056. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK
28057. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
28058. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK
28059. BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
28060. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK
28061. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
28062. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK
28063. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
28064. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK
28065. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
28066. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK
28067. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
28068. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK
28069. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
28070. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK
28071. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
28072. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK
28073. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
28074. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK
28075. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
28076. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK
28077. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
28078. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK
28079. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
28080. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK
28081. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
28082. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK
28083. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
28084. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK
28085. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
28086. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK
28087. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
28088. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK
28089. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
28090. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK
28091. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
28092. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK
28093. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
28094. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK
28095. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
28096. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK
28097. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
28098. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK
28099. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
28100. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK
28101. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
28102. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK
28103. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
28104. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK
28105. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
28106. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK
28107. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
28108. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK
28109. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
28110. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK
28111. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
28112. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK
28113. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
28114. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK
28115. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
28116. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK
28117. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
28118. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK
28119. BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
28120. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK
28121. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
28122. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK
28123. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
28124. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK
28125. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
28126. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK
28127. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
28128. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK
28129. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
28130. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK
28131. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
28132. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK
28133. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
28134. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK
28135. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
28136. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK
28137. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
28138. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK
28139. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
28140. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK
28141. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
28142. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK
28143. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
28144. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK
28145. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
28146. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK
28147. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
28148. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK
28149. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
28150. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK
28151. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
28152. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK
28153. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
28154. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK
28155. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
28156. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK
28157. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
28158. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK
28159. BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
28160. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK
28161. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
28162. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK
28163. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
28164. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK
28165. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
28166. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK
28167. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
28168. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK
28169. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
28170. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK
28171. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
28172. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK
28173. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
28174. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK
28175. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
28176. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK
28177. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
28178. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK
28179. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
28180. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK
28181. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
28182. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK
28183. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
28184. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK
28185. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
28186. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK
28187. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
28188. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK
28189. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
28190. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK
28191. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
28192. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK
28193. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
28194. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK
28195. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
28196. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK
28197. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
28198. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK
28199. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
28200. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK
28201. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
28202. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK
28203. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
28204. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK
28205. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
28206. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK
28207. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
28208. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK
28209. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
28210. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK
28211. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
28212. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK
28213. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
28214. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK
28215. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
28216. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK
28217. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
28218. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK
28219. BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
28220. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK
28221. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
28222. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK
28223. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
28224. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK
28225. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
28226. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK
28227. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
28228. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK
28229. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
28230. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK
28231. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
28232. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK
28233. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
28234. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK
28235. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
28236. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK
28237. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
28238. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK
28239. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
28240. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK
28241. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
28242. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK
28243. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
28244. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK
28245. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
28246. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK
28247. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
28248. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK
28249. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
28250. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK
28251. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
28252. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK
28253. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
28254. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK
28255. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
28256. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK
28257. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
28258. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK
28259. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
28260. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK
28261. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
28262. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK
28263. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
28264. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK
28265. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
28266. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK
28267. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
28268. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK
28269. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
28270. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK
28271. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
28272. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK
28273. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
28274. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK
28275. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
28276. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK
28277. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
28278. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK
28279. BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
28280. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK
28281. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
28282. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK
28283. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
28284. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK
28285. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
28286. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK
28287. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
28288. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK
28289. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
28290. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK
28291. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
28292. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK
28293. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
28294. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK
28295. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
28296. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK
28297. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
28298. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK
28299. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
28300. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK
28301. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
28302. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK
28303. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
28304. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK
28305. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
28306. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK
28307. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
28308. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK
28309. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
28310. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK
28311. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
28312. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK
28313. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
28314. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK
28315. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
28316. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK
28317. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
28318. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK
28319. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
28320. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK
28321. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
28322. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK
28323. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
28324. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK
28325. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
28326. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK
28327. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
28328. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK
28329. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
28330. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK
28331. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
28332. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK
28333. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
28334. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK
28335. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
28336. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK
28337. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
28338. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK
28339. BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
28340. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK
28341. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
28342. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK
28343. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
28344. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK
28345. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
28346. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK
28347. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
28348. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK
28349. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
28350. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK
28351. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
28352. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK
28353. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
28354. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK
28355. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
28356. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK
28357. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
28358. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK
28359. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
28360. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK
28361. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
28362. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK
28363. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
28364. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK
28365. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
28366. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK
28367. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
28368. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK
28369. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
28370. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK
28371. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
28372. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK
28373. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
28374. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK
28375. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
28376. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK
28377. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
28378. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK
28379. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
28380. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK
28381. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
28382. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK
28383. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
28384. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK
28385. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
28386. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK
28387. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
28388. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK
28389. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
28390. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK
28391. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
28392. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK
28393. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
28394. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK
28395. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
28396. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK
28397. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
28398. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK
28399. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
28400. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK
28401. BIFPLR0_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
28402. BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK
28403. BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
28404. BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK
28405. BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
28406. BIFPLR0_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
28407. BIFPLR0_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
28408. BIFPLR0_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK
28409. BIFPLR0_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
28410. BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
28411. BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
28412. BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
28413. BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
28414. BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
28415. BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
28416. BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
28417. BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
28418. BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
28419. BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
28420. BIFPLR0_1_PCIE_ESM_HEADER_2__CAP_ID_MASK
28421. BIFPLR0_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
28422. BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
28423. BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
28424. BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
28425. BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
28426. BIFPLR0_1_PCIE_HDR_LOG0__TLP_HDR_MASK
28427. BIFPLR0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
28428. BIFPLR0_1_PCIE_HDR_LOG1__TLP_HDR_MASK
28429. BIFPLR0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
28430. BIFPLR0_1_PCIE_HDR_LOG2__TLP_HDR_MASK
28431. BIFPLR0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
28432. BIFPLR0_1_PCIE_HDR_LOG3__TLP_HDR_MASK
28433. BIFPLR0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
28434. BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
28435. BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
28436. BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
28437. BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
28438. BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
28439. BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
28440. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
28441. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
28442. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
28443. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
28444. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
28445. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
28446. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
28447. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
28448. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
28449. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
28450. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
28451. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
28452. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
28453. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
28454. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
28455. BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
28456. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
28457. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
28458. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
28459. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
28460. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
28461. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
28462. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
28463. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
28464. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
28465. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
28466. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
28467. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
28468. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
28469. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
28470. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
28471. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
28472. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
28473. BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
28474. BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28475. BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28476. BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28477. BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28478. BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28479. BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28480. BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28481. BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28482. BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28483. BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28484. BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28485. BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28486. BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28487. BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28488. BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28489. BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28490. BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28491. BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28492. BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28493. BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28494. BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28495. BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28496. BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28497. BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28498. BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28499. BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28500. BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28501. BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28502. BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28503. BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28504. BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28505. BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28506. BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28507. BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28508. BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28509. BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28510. BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28511. BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28512. BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28513. BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28514. BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28515. BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28516. BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28517. BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28518. BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28519. BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28520. BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28521. BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28522. BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28523. BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28524. BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28525. BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28526. BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28527. BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28528. BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28529. BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28530. BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28531. BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28532. BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28533. BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28534. BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28535. BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28536. BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28537. BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28538. BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28539. BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28540. BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28541. BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28542. BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28543. BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28544. BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28545. BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28546. BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28547. BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28548. BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28549. BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28550. BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28551. BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28552. BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28553. BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28554. BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28555. BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28556. BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28557. BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28558. BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28559. BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28560. BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28561. BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28562. BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28563. BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28564. BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28565. BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28566. BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28567. BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28568. BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28569. BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28570. BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28571. BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28572. BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28573. BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28574. BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28575. BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28576. BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28577. BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28578. BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28579. BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28580. BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28581. BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28582. BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28583. BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28584. BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28585. BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28586. BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28587. BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28588. BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28589. BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28590. BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28591. BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28592. BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28593. BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28594. BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
28595. BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
28596. BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
28597. BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
28598. BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
28599. BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
28600. BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
28601. BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
28602. BIFPLR0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
28603. BIFPLR0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
28604. BIFPLR0_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
28605. BIFPLR0_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
28606. BIFPLR0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
28607. BIFPLR0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
28608. BIFPLR0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
28609. BIFPLR0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
28610. BIFPLR0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
28611. BIFPLR0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
28612. BIFPLR0_1_PCIE_LINK_CNTL3__RESERVED_MASK
28613. BIFPLR0_1_PCIE_LINK_CNTL3__RESERVED__SHIFT
28614. BIFPLR0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
28615. BIFPLR0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
28616. BIFPLR0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
28617. BIFPLR0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
28618. BIFPLR0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
28619. BIFPLR0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
28620. BIFPLR0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
28621. BIFPLR0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
28622. BIFPLR0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
28623. BIFPLR0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
28624. BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
28625. BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
28626. BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
28627. BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
28628. BIFPLR0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
28629. BIFPLR0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
28630. BIFPLR0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK
28631. BIFPLR0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
28632. BIFPLR0_1_PCIE_MC_CNTL__MC_ENABLE_MASK
28633. BIFPLR0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT
28634. BIFPLR0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
28635. BIFPLR0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
28636. BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
28637. BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
28638. BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
28639. BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
28640. BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
28641. BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
28642. BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
28643. BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
28644. BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
28645. BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
28646. BIFPLR0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
28647. BIFPLR0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
28648. BIFPLR0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
28649. BIFPLR0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
28650. BIFPLR0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
28651. BIFPLR0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
28652. BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
28653. BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
28654. BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
28655. BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
28656. BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
28657. BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
28658. BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
28659. BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
28660. BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
28661. BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
28662. BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
28663. BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
28664. BIFPLR0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
28665. BIFPLR0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
28666. BIFPLR0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
28667. BIFPLR0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
28668. BIFPLR0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
28669. BIFPLR0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
28670. BIFPLR0_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
28671. BIFPLR0_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
28672. BIFPLR0_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
28673. BIFPLR0_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
28674. BIFPLR0_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
28675. BIFPLR0_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
28676. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
28677. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
28678. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
28679. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
28680. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
28681. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
28682. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
28683. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
28684. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
28685. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
28686. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
28687. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
28688. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
28689. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
28690. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
28691. BIFPLR0_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
28692. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
28693. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
28694. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
28695. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
28696. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
28697. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
28698. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
28699. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
28700. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
28701. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
28702. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
28703. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
28704. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
28705. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
28706. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
28707. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
28708. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
28709. BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
28710. BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
28711. BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
28712. BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
28713. BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
28714. BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
28715. BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
28716. BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
28717. BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
28718. BIFPLR0_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
28719. BIFPLR0_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
28720. BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
28721. BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
28722. BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK
28723. BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
28724. BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
28725. BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
28726. BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
28727. BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
28728. BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CTO_MASK
28729. BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
28730. BIFPLR0_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
28731. BIFPLR0_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
28732. BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
28733. BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
28734. BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK
28735. BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
28736. BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
28737. BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
28738. BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
28739. BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
28740. BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
28741. BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
28742. BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
28743. BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
28744. BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
28745. BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
28746. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
28747. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
28748. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
28749. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
28750. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
28751. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
28752. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
28753. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
28754. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
28755. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
28756. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
28757. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
28758. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
28759. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
28760. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
28761. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
28762. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
28763. BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
28764. BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
28765. BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
28766. BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
28767. BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
28768. BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
28769. BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
28770. BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
28771. BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
28772. BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK
28773. BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
28774. BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
28775. BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
28776. BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
28777. BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
28778. BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
28779. BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
28780. BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
28781. BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
28782. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
28783. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
28784. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
28785. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
28786. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
28787. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
28788. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
28789. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
28790. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
28791. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
28792. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
28793. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
28794. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
28795. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
28796. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
28797. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
28798. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
28799. BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
28800. BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
28801. BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
28802. BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
28803. BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
28804. BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
28805. BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
28806. BIFPLR0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
28807. BIFPLR0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
28808. BIFPLR0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
28809. BIFPLR0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
28810. BIFPLR0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
28811. BIFPLR0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
28812. BIFPLR0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
28813. BIFPLR0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
28814. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
28815. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
28816. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
28817. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
28818. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
28819. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
28820. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
28821. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
28822. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
28823. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
28824. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
28825. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
28826. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
28827. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
28828. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
28829. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
28830. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
28831. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
28832. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
28833. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
28834. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
28835. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
28836. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
28837. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
28838. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
28839. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
28840. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
28841. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
28842. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
28843. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
28844. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
28845. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
28846. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
28847. BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
28848. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
28849. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
28850. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
28851. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
28852. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
28853. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
28854. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
28855. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
28856. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
28857. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
28858. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
28859. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
28860. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
28861. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
28862. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
28863. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
28864. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
28865. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
28866. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
28867. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
28868. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
28869. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
28870. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
28871. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
28872. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
28873. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
28874. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
28875. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
28876. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
28877. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
28878. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
28879. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
28880. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
28881. BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
28882. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
28883. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
28884. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
28885. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
28886. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
28887. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
28888. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
28889. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
28890. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
28891. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
28892. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
28893. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
28894. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
28895. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
28896. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
28897. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
28898. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
28899. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
28900. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
28901. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
28902. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
28903. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
28904. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
28905. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
28906. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
28907. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
28908. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
28909. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
28910. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
28911. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
28912. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
28913. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
28914. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
28915. BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
28916. BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
28917. BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
28918. BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
28919. BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
28920. BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
28921. BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
28922. BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
28923. BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
28924. BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
28925. BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
28926. BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
28927. BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
28928. BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
28929. BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
28930. BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
28931. BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
28932. BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
28933. BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
28934. BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
28935. BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
28936. BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
28937. BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
28938. BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
28939. BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
28940. BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
28941. BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
28942. BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
28943. BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
28944. BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
28945. BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
28946. BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
28947. BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
28948. BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
28949. BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
28950. BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
28951. BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
28952. BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
28953. BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
28954. BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
28955. BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
28956. BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
28957. BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
28958. BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
28959. BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
28960. BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
28961. BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
28962. BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
28963. BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
28964. BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
28965. BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
28966. BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
28967. BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
28968. BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
28969. BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
28970. BIFPLR0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
28971. BIFPLR0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
28972. BIFPLR0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
28973. BIFPLR0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
28974. BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
28975. BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
28976. BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
28977. BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
28978. BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
28979. BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
28980. BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
28981. BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
28982. BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
28983. BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
28984. BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
28985. BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
28986. BIFPLR0_1_PMI_CAP_LIST__CAP_ID_MASK
28987. BIFPLR0_1_PMI_CAP_LIST__CAP_ID__SHIFT
28988. BIFPLR0_1_PMI_CAP_LIST__NEXT_PTR_MASK
28989. BIFPLR0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
28990. BIFPLR0_1_PMI_CAP__AUX_CURRENT_MASK
28991. BIFPLR0_1_PMI_CAP__AUX_CURRENT__SHIFT
28992. BIFPLR0_1_PMI_CAP__D1_SUPPORT_MASK
28993. BIFPLR0_1_PMI_CAP__D1_SUPPORT__SHIFT
28994. BIFPLR0_1_PMI_CAP__D2_SUPPORT_MASK
28995. BIFPLR0_1_PMI_CAP__D2_SUPPORT__SHIFT
28996. BIFPLR0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
28997. BIFPLR0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
28998. BIFPLR0_1_PMI_CAP__PME_CLOCK_MASK
28999. BIFPLR0_1_PMI_CAP__PME_CLOCK__SHIFT
29000. BIFPLR0_1_PMI_CAP__PME_SUPPORT_MASK
29001. BIFPLR0_1_PMI_CAP__PME_SUPPORT__SHIFT
29002. BIFPLR0_1_PMI_CAP__VERSION_MASK
29003. BIFPLR0_1_PMI_CAP__VERSION__SHIFT
29004. BIFPLR0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
29005. BIFPLR0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
29006. BIFPLR0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
29007. BIFPLR0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
29008. BIFPLR0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
29009. BIFPLR0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
29010. BIFPLR0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
29011. BIFPLR0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
29012. BIFPLR0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
29013. BIFPLR0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
29014. BIFPLR0_1_PMI_STATUS_CNTL__PME_EN_MASK
29015. BIFPLR0_1_PMI_STATUS_CNTL__PME_EN__SHIFT
29016. BIFPLR0_1_PMI_STATUS_CNTL__PME_STATUS_MASK
29017. BIFPLR0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
29018. BIFPLR0_1_PMI_STATUS_CNTL__PMI_DATA_MASK
29019. BIFPLR0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
29020. BIFPLR0_1_PMI_STATUS_CNTL__POWER_STATE_MASK
29021. BIFPLR0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
29022. BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
29023. BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
29024. BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
29025. BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
29026. BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
29027. BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
29028. BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
29029. BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
29030. BIFPLR0_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
29031. BIFPLR0_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
29032. BIFPLR0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
29033. BIFPLR0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
29034. BIFPLR0_1_PROG_INTERFACE__PROG_INTERFACE_MASK
29035. BIFPLR0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
29036. BIFPLR0_1_REVISION_ID__MAJOR_REV_ID_MASK
29037. BIFPLR0_1_REVISION_ID__MAJOR_REV_ID__SHIFT
29038. BIFPLR0_1_REVISION_ID__MINOR_REV_ID_MASK
29039. BIFPLR0_1_REVISION_ID__MINOR_REV_ID__SHIFT
29040. BIFPLR0_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
29041. BIFPLR0_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
29042. BIFPLR0_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
29043. BIFPLR0_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
29044. BIFPLR0_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK
29045. BIFPLR0_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
29046. BIFPLR0_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
29047. BIFPLR0_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
29048. BIFPLR0_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
29049. BIFPLR0_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
29050. BIFPLR0_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
29051. BIFPLR0_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
29052. BIFPLR0_1_ROOT_STATUS__PME_PENDING_MASK
29053. BIFPLR0_1_ROOT_STATUS__PME_PENDING__SHIFT
29054. BIFPLR0_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK
29055. BIFPLR0_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
29056. BIFPLR0_1_ROOT_STATUS__PME_STATUS_MASK
29057. BIFPLR0_1_ROOT_STATUS__PME_STATUS__SHIFT
29058. BIFPLR0_1_SECONDARY_STATUS__CAP_LIST_MASK
29059. BIFPLR0_1_SECONDARY_STATUS__CAP_LIST__SHIFT
29060. BIFPLR0_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK
29061. BIFPLR0_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
29062. BIFPLR0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
29063. BIFPLR0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
29064. BIFPLR0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
29065. BIFPLR0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
29066. BIFPLR0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
29067. BIFPLR0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
29068. BIFPLR0_1_SECONDARY_STATUS__PCI_66_EN_MASK
29069. BIFPLR0_1_SECONDARY_STATUS__PCI_66_EN__SHIFT
29070. BIFPLR0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
29071. BIFPLR0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
29072. BIFPLR0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
29073. BIFPLR0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
29074. BIFPLR0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
29075. BIFPLR0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
29076. BIFPLR0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
29077. BIFPLR0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
29078. BIFPLR0_1_SLOT_CAP2__RESERVED_MASK
29079. BIFPLR0_1_SLOT_CAP2__RESERVED__SHIFT
29080. BIFPLR0_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
29081. BIFPLR0_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
29082. BIFPLR0_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
29083. BIFPLR0_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
29084. BIFPLR0_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
29085. BIFPLR0_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
29086. BIFPLR0_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK
29087. BIFPLR0_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
29088. BIFPLR0_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK
29089. BIFPLR0_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
29090. BIFPLR0_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
29091. BIFPLR0_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
29092. BIFPLR0_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
29093. BIFPLR0_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
29094. BIFPLR0_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
29095. BIFPLR0_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
29096. BIFPLR0_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
29097. BIFPLR0_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
29098. BIFPLR0_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
29099. BIFPLR0_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
29100. BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
29101. BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
29102. BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
29103. BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
29104. BIFPLR0_1_SLOT_CNTL2__RESERVED_MASK
29105. BIFPLR0_1_SLOT_CNTL2__RESERVED__SHIFT
29106. BIFPLR0_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
29107. BIFPLR0_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
29108. BIFPLR0_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
29109. BIFPLR0_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
29110. BIFPLR0_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
29111. BIFPLR0_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
29112. BIFPLR0_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
29113. BIFPLR0_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
29114. BIFPLR0_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
29115. BIFPLR0_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
29116. BIFPLR0_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
29117. BIFPLR0_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
29118. BIFPLR0_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
29119. BIFPLR0_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
29120. BIFPLR0_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
29121. BIFPLR0_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
29122. BIFPLR0_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
29123. BIFPLR0_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
29124. BIFPLR0_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
29125. BIFPLR0_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
29126. BIFPLR0_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
29127. BIFPLR0_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
29128. BIFPLR0_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
29129. BIFPLR0_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
29130. BIFPLR0_1_SLOT_STATUS2__RESERVED_MASK
29131. BIFPLR0_1_SLOT_STATUS2__RESERVED__SHIFT
29132. BIFPLR0_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
29133. BIFPLR0_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
29134. BIFPLR0_1_SLOT_STATUS__COMMAND_COMPLETED_MASK
29135. BIFPLR0_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
29136. BIFPLR0_1_SLOT_STATUS__DL_STATE_CHANGED_MASK
29137. BIFPLR0_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
29138. BIFPLR0_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
29139. BIFPLR0_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
29140. BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
29141. BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
29142. BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK
29143. BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
29144. BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
29145. BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
29146. BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
29147. BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
29148. BIFPLR0_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
29149. BIFPLR0_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
29150. BIFPLR0_1_SSID_CAP_LIST__CAP_ID_MASK
29151. BIFPLR0_1_SSID_CAP_LIST__CAP_ID__SHIFT
29152. BIFPLR0_1_SSID_CAP_LIST__NEXT_PTR_MASK
29153. BIFPLR0_1_SSID_CAP_LIST__NEXT_PTR__SHIFT
29154. BIFPLR0_1_SSID_CAP__SUBSYSTEM_ID_MASK
29155. BIFPLR0_1_SSID_CAP__SUBSYSTEM_ID__SHIFT
29156. BIFPLR0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
29157. BIFPLR0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
29158. BIFPLR0_1_STATUS__CAP_LIST_MASK
29159. BIFPLR0_1_STATUS__CAP_LIST__SHIFT
29160. BIFPLR0_1_STATUS__DEVSEL_TIMING_MASK
29161. BIFPLR0_1_STATUS__DEVSEL_TIMING__SHIFT
29162. BIFPLR0_1_STATUS__FAST_BACK_CAPABLE_MASK
29163. BIFPLR0_1_STATUS__FAST_BACK_CAPABLE__SHIFT
29164. BIFPLR0_1_STATUS__INT_STATUS_MASK
29165. BIFPLR0_1_STATUS__INT_STATUS__SHIFT
29166. BIFPLR0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
29167. BIFPLR0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
29168. BIFPLR0_1_STATUS__PARITY_ERROR_DETECTED_MASK
29169. BIFPLR0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
29170. BIFPLR0_1_STATUS__PCI_66_EN_MASK
29171. BIFPLR0_1_STATUS__PCI_66_EN__SHIFT
29172. BIFPLR0_1_STATUS__RECEIVED_MASTER_ABORT_MASK
29173. BIFPLR0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
29174. BIFPLR0_1_STATUS__RECEIVED_TARGET_ABORT_MASK
29175. BIFPLR0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
29176. BIFPLR0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
29177. BIFPLR0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
29178. BIFPLR0_1_STATUS__SIGNAL_TARGET_ABORT_MASK
29179. BIFPLR0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
29180. BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
29181. BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
29182. BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
29183. BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
29184. BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
29185. BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
29186. BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
29187. BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
29188. BIFPLR0_1_SUB_CLASS__SUB_CLASS_MASK
29189. BIFPLR0_1_SUB_CLASS__SUB_CLASS__SHIFT
29190. BIFPLR0_1_VENDOR_ID__VENDOR_ID_MASK
29191. BIFPLR0_1_VENDOR_ID__VENDOR_ID__SHIFT
29192. BIFPLR0_2_BASE_CLASS__BASE_CLASS_MASK
29193. BIFPLR0_2_BASE_CLASS__BASE_CLASS__SHIFT
29194. BIFPLR0_2_BIST__BIST_CAP_MASK
29195. BIFPLR0_2_BIST__BIST_CAP__SHIFT
29196. BIFPLR0_2_BIST__BIST_COMP_MASK
29197. BIFPLR0_2_BIST__BIST_COMP__SHIFT
29198. BIFPLR0_2_BIST__BIST_STRT_MASK
29199. BIFPLR0_2_BIST__BIST_STRT__SHIFT
29200. BIFPLR0_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
29201. BIFPLR0_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
29202. BIFPLR0_2_CAP_PTR__CAP_PTR_MASK
29203. BIFPLR0_2_CAP_PTR__CAP_PTR__SHIFT
29204. BIFPLR0_2_COMMAND__AD_STEPPING_MASK
29205. BIFPLR0_2_COMMAND__AD_STEPPING__SHIFT
29206. BIFPLR0_2_COMMAND__BUS_MASTER_EN_MASK
29207. BIFPLR0_2_COMMAND__BUS_MASTER_EN__SHIFT
29208. BIFPLR0_2_COMMAND__FAST_B2B_EN_MASK
29209. BIFPLR0_2_COMMAND__FAST_B2B_EN__SHIFT
29210. BIFPLR0_2_COMMAND__INT_DIS_MASK
29211. BIFPLR0_2_COMMAND__INT_DIS__SHIFT
29212. BIFPLR0_2_COMMAND__IO_ACCESS_EN_MASK
29213. BIFPLR0_2_COMMAND__IO_ACCESS_EN__SHIFT
29214. BIFPLR0_2_COMMAND__MEM_ACCESS_EN_MASK
29215. BIFPLR0_2_COMMAND__MEM_ACCESS_EN__SHIFT
29216. BIFPLR0_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
29217. BIFPLR0_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
29218. BIFPLR0_2_COMMAND__PAL_SNOOP_EN_MASK
29219. BIFPLR0_2_COMMAND__PAL_SNOOP_EN__SHIFT
29220. BIFPLR0_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
29221. BIFPLR0_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
29222. BIFPLR0_2_COMMAND__SERR_EN_MASK
29223. BIFPLR0_2_COMMAND__SERR_EN__SHIFT
29224. BIFPLR0_2_COMMAND__SPECIAL_CYCLE_EN_MASK
29225. BIFPLR0_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
29226. BIFPLR0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
29227. BIFPLR0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
29228. BIFPLR0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
29229. BIFPLR0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
29230. BIFPLR0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
29231. BIFPLR0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
29232. BIFPLR0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
29233. BIFPLR0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
29234. BIFPLR0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
29235. BIFPLR0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
29236. BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
29237. BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
29238. BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
29239. BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
29240. BIFPLR0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
29241. BIFPLR0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
29242. BIFPLR0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
29243. BIFPLR0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
29244. BIFPLR0_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
29245. BIFPLR0_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
29246. BIFPLR0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
29247. BIFPLR0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
29248. BIFPLR0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
29249. BIFPLR0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
29250. BIFPLR0_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
29251. BIFPLR0_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
29252. BIFPLR0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
29253. BIFPLR0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
29254. BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
29255. BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
29256. BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
29257. BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
29258. BIFPLR0_2_DEVICE_CAP__EXTENDED_TAG_MASK
29259. BIFPLR0_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
29260. BIFPLR0_2_DEVICE_CAP__FLR_CAPABLE_MASK
29261. BIFPLR0_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
29262. BIFPLR0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
29263. BIFPLR0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
29264. BIFPLR0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
29265. BIFPLR0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
29266. BIFPLR0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
29267. BIFPLR0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
29268. BIFPLR0_2_DEVICE_CAP__PHANTOM_FUNC_MASK
29269. BIFPLR0_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
29270. BIFPLR0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
29271. BIFPLR0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
29272. BIFPLR0_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
29273. BIFPLR0_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
29274. BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
29275. BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
29276. BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
29277. BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
29278. BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
29279. BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
29280. BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
29281. BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
29282. BIFPLR0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
29283. BIFPLR0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
29284. BIFPLR0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
29285. BIFPLR0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
29286. BIFPLR0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
29287. BIFPLR0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
29288. BIFPLR0_2_DEVICE_CNTL2__LTR_EN_MASK
29289. BIFPLR0_2_DEVICE_CNTL2__LTR_EN__SHIFT
29290. BIFPLR0_2_DEVICE_CNTL2__OBFF_EN_MASK
29291. BIFPLR0_2_DEVICE_CNTL2__OBFF_EN__SHIFT
29292. BIFPLR0_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
29293. BIFPLR0_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
29294. BIFPLR0_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
29295. BIFPLR0_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
29296. BIFPLR0_2_DEVICE_CNTL__CORR_ERR_EN_MASK
29297. BIFPLR0_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
29298. BIFPLR0_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
29299. BIFPLR0_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
29300. BIFPLR0_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
29301. BIFPLR0_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
29302. BIFPLR0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
29303. BIFPLR0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
29304. BIFPLR0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
29305. BIFPLR0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
29306. BIFPLR0_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
29307. BIFPLR0_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
29308. BIFPLR0_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
29309. BIFPLR0_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
29310. BIFPLR0_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
29311. BIFPLR0_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
29312. BIFPLR0_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
29313. BIFPLR0_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
29314. BIFPLR0_2_DEVICE_CNTL__USR_REPORT_EN_MASK
29315. BIFPLR0_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
29316. BIFPLR0_2_DEVICE_ID__DEVICE_ID_MASK
29317. BIFPLR0_2_DEVICE_ID__DEVICE_ID__SHIFT
29318. BIFPLR0_2_DEVICE_STATUS2__RESERVED_MASK
29319. BIFPLR0_2_DEVICE_STATUS2__RESERVED__SHIFT
29320. BIFPLR0_2_DEVICE_STATUS__AUX_PWR_MASK
29321. BIFPLR0_2_DEVICE_STATUS__AUX_PWR__SHIFT
29322. BIFPLR0_2_DEVICE_STATUS__CORR_ERR_MASK
29323. BIFPLR0_2_DEVICE_STATUS__CORR_ERR__SHIFT
29324. BIFPLR0_2_DEVICE_STATUS__FATAL_ERR_MASK
29325. BIFPLR0_2_DEVICE_STATUS__FATAL_ERR__SHIFT
29326. BIFPLR0_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
29327. BIFPLR0_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
29328. BIFPLR0_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
29329. BIFPLR0_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
29330. BIFPLR0_2_DEVICE_STATUS__USR_DETECTED_MASK
29331. BIFPLR0_2_DEVICE_STATUS__USR_DETECTED__SHIFT
29332. BIFPLR0_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
29333. BIFPLR0_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
29334. BIFPLR0_2_HEADER__DEVICE_TYPE_MASK
29335. BIFPLR0_2_HEADER__DEVICE_TYPE__SHIFT
29336. BIFPLR0_2_HEADER__HEADER_TYPE_MASK
29337. BIFPLR0_2_HEADER__HEADER_TYPE__SHIFT
29338. BIFPLR0_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
29339. BIFPLR0_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
29340. BIFPLR0_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
29341. BIFPLR0_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
29342. BIFPLR0_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
29343. BIFPLR0_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
29344. BIFPLR0_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
29345. BIFPLR0_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
29346. BIFPLR0_2_IO_BASE_LIMIT__IO_BASE_MASK
29347. BIFPLR0_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
29348. BIFPLR0_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
29349. BIFPLR0_2_IO_BASE_LIMIT__IO_BASE__SHIFT
29350. BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT_MASK
29351. BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
29352. BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
29353. BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT
29354. BIFPLR0_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
29355. BIFPLR0_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
29356. BIFPLR0_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK
29357. BIFPLR0_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
29358. BIFPLR0_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
29359. BIFPLR0_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
29360. BIFPLR0_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
29361. BIFPLR0_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
29362. BIFPLR0_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
29363. BIFPLR0_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
29364. BIFPLR0_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK
29365. BIFPLR0_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
29366. BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
29367. BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
29368. BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK
29369. BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
29370. BIFPLR0_2_LATENCY__LATENCY_TIMER_MASK
29371. BIFPLR0_2_LATENCY__LATENCY_TIMER__SHIFT
29372. BIFPLR0_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
29373. BIFPLR0_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
29374. BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
29375. BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
29376. BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
29377. BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
29378. BIFPLR0_2_LINK_CAP2__RESERVED_MASK
29379. BIFPLR0_2_LINK_CAP2__RESERVED__SHIFT
29380. BIFPLR0_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
29381. BIFPLR0_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
29382. BIFPLR0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
29383. BIFPLR0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
29384. BIFPLR0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
29385. BIFPLR0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
29386. BIFPLR0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
29387. BIFPLR0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
29388. BIFPLR0_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
29389. BIFPLR0_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
29390. BIFPLR0_2_LINK_CAP__L1_EXIT_LATENCY_MASK
29391. BIFPLR0_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
29392. BIFPLR0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
29393. BIFPLR0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
29394. BIFPLR0_2_LINK_CAP__LINK_SPEED_MASK
29395. BIFPLR0_2_LINK_CAP__LINK_SPEED__SHIFT
29396. BIFPLR0_2_LINK_CAP__LINK_WIDTH_MASK
29397. BIFPLR0_2_LINK_CAP__LINK_WIDTH__SHIFT
29398. BIFPLR0_2_LINK_CAP__PM_SUPPORT_MASK
29399. BIFPLR0_2_LINK_CAP__PM_SUPPORT__SHIFT
29400. BIFPLR0_2_LINK_CAP__PORT_NUMBER_MASK
29401. BIFPLR0_2_LINK_CAP__PORT_NUMBER__SHIFT
29402. BIFPLR0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
29403. BIFPLR0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
29404. BIFPLR0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
29405. BIFPLR0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
29406. BIFPLR0_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
29407. BIFPLR0_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
29408. BIFPLR0_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
29409. BIFPLR0_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
29410. BIFPLR0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
29411. BIFPLR0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
29412. BIFPLR0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
29413. BIFPLR0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
29414. BIFPLR0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
29415. BIFPLR0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
29416. BIFPLR0_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
29417. BIFPLR0_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
29418. BIFPLR0_2_LINK_CNTL2__XMIT_MARGIN_MASK
29419. BIFPLR0_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
29420. BIFPLR0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
29421. BIFPLR0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
29422. BIFPLR0_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
29423. BIFPLR0_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
29424. BIFPLR0_2_LINK_CNTL__EXTENDED_SYNC_MASK
29425. BIFPLR0_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
29426. BIFPLR0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
29427. BIFPLR0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
29428. BIFPLR0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
29429. BIFPLR0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
29430. BIFPLR0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
29431. BIFPLR0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
29432. BIFPLR0_2_LINK_CNTL__LINK_DIS_MASK
29433. BIFPLR0_2_LINK_CNTL__LINK_DIS__SHIFT
29434. BIFPLR0_2_LINK_CNTL__PM_CONTROL_MASK
29435. BIFPLR0_2_LINK_CNTL__PM_CONTROL__SHIFT
29436. BIFPLR0_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
29437. BIFPLR0_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
29438. BIFPLR0_2_LINK_CNTL__RETRAIN_LINK_MASK
29439. BIFPLR0_2_LINK_CNTL__RETRAIN_LINK__SHIFT
29440. BIFPLR0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
29441. BIFPLR0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
29442. BIFPLR0_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
29443. BIFPLR0_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
29444. BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
29445. BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
29446. BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
29447. BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
29448. BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
29449. BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
29450. BIFPLR0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
29451. BIFPLR0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
29452. BIFPLR0_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
29453. BIFPLR0_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
29454. BIFPLR0_2_LINK_STATUS__DL_ACTIVE_MASK
29455. BIFPLR0_2_LINK_STATUS__DL_ACTIVE__SHIFT
29456. BIFPLR0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
29457. BIFPLR0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
29458. BIFPLR0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
29459. BIFPLR0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
29460. BIFPLR0_2_LINK_STATUS__LINK_TRAINING_MASK
29461. BIFPLR0_2_LINK_STATUS__LINK_TRAINING__SHIFT
29462. BIFPLR0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
29463. BIFPLR0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
29464. BIFPLR0_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
29465. BIFPLR0_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
29466. BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
29467. BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
29468. BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
29469. BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
29470. BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
29471. BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
29472. BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
29473. BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
29474. BIFPLR0_2_MSI_CAP_LIST__CAP_ID_MASK
29475. BIFPLR0_2_MSI_CAP_LIST__CAP_ID__SHIFT
29476. BIFPLR0_2_MSI_CAP_LIST__NEXT_PTR_MASK
29477. BIFPLR0_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
29478. BIFPLR0_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
29479. BIFPLR0_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
29480. BIFPLR0_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
29481. BIFPLR0_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
29482. BIFPLR0_2_MSI_MAP_CAP_LIST__CAP_ID_MASK
29483. BIFPLR0_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
29484. BIFPLR0_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
29485. BIFPLR0_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
29486. BIFPLR0_2_MSI_MAP_CAP__CAP_TYPE_MASK
29487. BIFPLR0_2_MSI_MAP_CAP__CAP_TYPE__SHIFT
29488. BIFPLR0_2_MSI_MAP_CAP__EN_MASK
29489. BIFPLR0_2_MSI_MAP_CAP__EN__SHIFT
29490. BIFPLR0_2_MSI_MAP_CAP__FIXD_MASK
29491. BIFPLR0_2_MSI_MAP_CAP__FIXD__SHIFT
29492. BIFPLR0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
29493. BIFPLR0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
29494. BIFPLR0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
29495. BIFPLR0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
29496. BIFPLR0_2_MSI_MSG_CNTL__MSI_64BIT_MASK
29497. BIFPLR0_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
29498. BIFPLR0_2_MSI_MSG_CNTL__MSI_EN_MASK
29499. BIFPLR0_2_MSI_MSG_CNTL__MSI_EN__SHIFT
29500. BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
29501. BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
29502. BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
29503. BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
29504. BIFPLR0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
29505. BIFPLR0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
29506. BIFPLR0_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
29507. BIFPLR0_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
29508. BIFPLR0_2_MSI_MSG_DATA__MSI_DATA_MASK
29509. BIFPLR0_2_MSI_MSG_DATA__MSI_DATA__SHIFT
29510. BIFPLR0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
29511. BIFPLR0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
29512. BIFPLR0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
29513. BIFPLR0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
29514. BIFPLR0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
29515. BIFPLR0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
29516. BIFPLR0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
29517. BIFPLR0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
29518. BIFPLR0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
29519. BIFPLR0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
29520. BIFPLR0_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
29521. BIFPLR0_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
29522. BIFPLR0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
29523. BIFPLR0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
29524. BIFPLR0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
29525. BIFPLR0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
29526. BIFPLR0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
29527. BIFPLR0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
29528. BIFPLR0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
29529. BIFPLR0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
29530. BIFPLR0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
29531. BIFPLR0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
29532. BIFPLR0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
29533. BIFPLR0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
29534. BIFPLR0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
29535. BIFPLR0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
29536. BIFPLR0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
29537. BIFPLR0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
29538. BIFPLR0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
29539. BIFPLR0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
29540. BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
29541. BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
29542. BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
29543. BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
29544. BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
29545. BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
29546. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
29547. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
29548. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
29549. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
29550. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
29551. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
29552. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
29553. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
29554. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
29555. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
29556. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
29557. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
29558. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
29559. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
29560. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
29561. BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
29562. BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
29563. BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
29564. BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
29565. BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
29566. BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
29567. BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
29568. BIFPLR0_2_PCIE_CAP_LIST__CAP_ID_MASK
29569. BIFPLR0_2_PCIE_CAP_LIST__CAP_ID__SHIFT
29570. BIFPLR0_2_PCIE_CAP_LIST__NEXT_PTR_MASK
29571. BIFPLR0_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
29572. BIFPLR0_2_PCIE_CAP__DEVICE_TYPE_MASK
29573. BIFPLR0_2_PCIE_CAP__DEVICE_TYPE__SHIFT
29574. BIFPLR0_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
29575. BIFPLR0_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
29576. BIFPLR0_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
29577. BIFPLR0_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
29578. BIFPLR0_2_PCIE_CAP__VERSION_MASK
29579. BIFPLR0_2_PCIE_CAP__VERSION__SHIFT
29580. BIFPLR0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
29581. BIFPLR0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
29582. BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
29583. BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
29584. BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
29585. BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
29586. BIFPLR0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
29587. BIFPLR0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
29588. BIFPLR0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
29589. BIFPLR0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
29590. BIFPLR0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
29591. BIFPLR0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
29592. BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
29593. BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
29594. BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
29595. BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
29596. BIFPLR0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
29597. BIFPLR0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
29598. BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
29599. BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
29600. BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
29601. BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
29602. BIFPLR0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
29603. BIFPLR0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
29604. BIFPLR0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
29605. BIFPLR0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
29606. BIFPLR0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
29607. BIFPLR0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
29608. BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
29609. BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
29610. BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
29611. BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
29612. BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
29613. BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
29614. BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
29615. BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
29616. BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
29617. BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
29618. BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
29619. BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
29620. BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
29621. BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
29622. BIFPLR0_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
29623. BIFPLR0_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
29624. BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
29625. BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
29626. BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
29627. BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
29628. BIFPLR0_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
29629. BIFPLR0_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
29630. BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
29631. BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
29632. BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
29633. BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
29634. BIFPLR0_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
29635. BIFPLR0_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
29636. BIFPLR0_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
29637. BIFPLR0_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
29638. BIFPLR0_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
29639. BIFPLR0_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
29640. BIFPLR0_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
29641. BIFPLR0_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
29642. BIFPLR0_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
29643. BIFPLR0_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
29644. BIFPLR0_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
29645. BIFPLR0_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
29646. BIFPLR0_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
29647. BIFPLR0_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
29648. BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
29649. BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
29650. BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
29651. BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
29652. BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
29653. BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
29654. BIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
29655. BIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
29656. BIFPLR0_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
29657. BIFPLR0_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
29658. BIFPLR0_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
29659. BIFPLR0_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
29660. BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
29661. BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
29662. BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
29663. BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
29664. BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
29665. BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
29666. BIFPLR0_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
29667. BIFPLR0_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
29668. BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
29669. BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
29670. BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
29671. BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
29672. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK
29673. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
29674. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK
29675. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
29676. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK
29677. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
29678. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK
29679. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
29680. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK
29681. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
29682. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK
29683. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
29684. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK
29685. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
29686. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK
29687. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
29688. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK
29689. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
29690. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK
29691. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
29692. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK
29693. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
29694. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK
29695. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
29696. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK
29697. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
29698. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK
29699. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
29700. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK
29701. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
29702. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK
29703. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
29704. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK
29705. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
29706. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK
29707. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
29708. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK
29709. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
29710. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK
29711. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
29712. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK
29713. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
29714. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK
29715. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
29716. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK
29717. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
29718. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK
29719. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
29720. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK
29721. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
29722. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK
29723. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
29724. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK
29725. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
29726. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK
29727. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
29728. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK
29729. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
29730. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK
29731. BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
29732. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK
29733. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
29734. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK
29735. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
29736. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK
29737. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
29738. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK
29739. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
29740. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK
29741. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
29742. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK
29743. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
29744. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK
29745. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
29746. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK
29747. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
29748. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK
29749. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
29750. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK
29751. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
29752. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK
29753. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
29754. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK
29755. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
29756. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK
29757. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
29758. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK
29759. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
29760. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK
29761. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
29762. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK
29763. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
29764. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK
29765. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
29766. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK
29767. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
29768. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK
29769. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
29770. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK
29771. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
29772. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK
29773. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
29774. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK
29775. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
29776. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK
29777. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
29778. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK
29779. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
29780. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK
29781. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
29782. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK
29783. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
29784. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK
29785. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
29786. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK
29787. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
29788. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK
29789. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
29790. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK
29791. BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
29792. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK
29793. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
29794. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK
29795. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
29796. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK
29797. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
29798. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK
29799. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
29800. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK
29801. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
29802. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK
29803. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
29804. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK
29805. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
29806. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK
29807. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
29808. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK
29809. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
29810. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK
29811. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
29812. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK
29813. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
29814. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK
29815. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
29816. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK
29817. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
29818. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK
29819. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
29820. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK
29821. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
29822. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK
29823. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
29824. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK
29825. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
29826. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK
29827. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
29828. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK
29829. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
29830. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK
29831. BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
29832. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK
29833. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
29834. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK
29835. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
29836. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK
29837. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
29838. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK
29839. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
29840. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK
29841. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
29842. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK
29843. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
29844. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK
29845. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
29846. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK
29847. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
29848. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK
29849. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
29850. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK
29851. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
29852. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK
29853. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
29854. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK
29855. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
29856. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK
29857. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
29858. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK
29859. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
29860. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK
29861. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
29862. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK
29863. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
29864. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK
29865. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
29866. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK
29867. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
29868. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK
29869. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
29870. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK
29871. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
29872. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK
29873. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
29874. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK
29875. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
29876. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK
29877. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
29878. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK
29879. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
29880. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK
29881. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
29882. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK
29883. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
29884. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK
29885. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
29886. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK
29887. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
29888. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK
29889. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
29890. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK
29891. BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
29892. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK
29893. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
29894. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK
29895. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
29896. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK
29897. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
29898. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK
29899. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
29900. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK
29901. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
29902. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK
29903. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
29904. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK
29905. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
29906. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK
29907. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
29908. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK
29909. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
29910. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK
29911. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
29912. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK
29913. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
29914. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK
29915. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
29916. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK
29917. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
29918. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK
29919. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
29920. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK
29921. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
29922. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK
29923. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
29924. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK
29925. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
29926. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK
29927. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
29928. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK
29929. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
29930. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK
29931. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
29932. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK
29933. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
29934. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK
29935. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
29936. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK
29937. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
29938. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK
29939. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
29940. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK
29941. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
29942. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK
29943. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
29944. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK
29945. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
29946. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK
29947. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
29948. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK
29949. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
29950. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK
29951. BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
29952. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK
29953. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
29954. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK
29955. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
29956. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK
29957. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
29958. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK
29959. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
29960. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK
29961. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
29962. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK
29963. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
29964. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK
29965. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
29966. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK
29967. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
29968. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK
29969. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
29970. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK
29971. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
29972. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK
29973. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
29974. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK
29975. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
29976. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK
29977. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
29978. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK
29979. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
29980. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK
29981. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
29982. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK
29983. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
29984. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK
29985. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
29986. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK
29987. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
29988. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK
29989. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
29990. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK
29991. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
29992. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK
29993. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
29994. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK
29995. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
29996. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK
29997. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
29998. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK
29999. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
30000. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK
30001. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
30002. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK
30003. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
30004. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK
30005. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
30006. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK
30007. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
30008. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK
30009. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
30010. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK
30011. BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
30012. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK
30013. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
30014. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK
30015. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
30016. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK
30017. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
30018. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK
30019. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
30020. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK
30021. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
30022. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK
30023. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
30024. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK
30025. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
30026. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK
30027. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
30028. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK
30029. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
30030. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK
30031. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
30032. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK
30033. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
30034. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK
30035. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
30036. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK
30037. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
30038. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK
30039. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
30040. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK
30041. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
30042. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK
30043. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
30044. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK
30045. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
30046. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK
30047. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
30048. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK
30049. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
30050. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK
30051. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
30052. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK
30053. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
30054. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK
30055. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
30056. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK
30057. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
30058. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK
30059. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
30060. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK
30061. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
30062. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK
30063. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
30064. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK
30065. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
30066. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK
30067. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
30068. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK
30069. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
30070. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK
30071. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
30072. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK
30073. BIFPLR0_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
30074. BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK
30075. BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
30076. BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK
30077. BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
30078. BIFPLR0_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
30079. BIFPLR0_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
30080. BIFPLR0_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK
30081. BIFPLR0_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
30082. BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
30083. BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
30084. BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
30085. BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
30086. BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
30087. BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
30088. BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
30089. BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
30090. BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
30091. BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
30092. BIFPLR0_2_PCIE_ESM_HEADER_2__CAP_ID_MASK
30093. BIFPLR0_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
30094. BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
30095. BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
30096. BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
30097. BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
30098. BIFPLR0_2_PCIE_HDR_LOG0__TLP_HDR_MASK
30099. BIFPLR0_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
30100. BIFPLR0_2_PCIE_HDR_LOG1__TLP_HDR_MASK
30101. BIFPLR0_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
30102. BIFPLR0_2_PCIE_HDR_LOG2__TLP_HDR_MASK
30103. BIFPLR0_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
30104. BIFPLR0_2_PCIE_HDR_LOG3__TLP_HDR_MASK
30105. BIFPLR0_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
30106. BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
30107. BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
30108. BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
30109. BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
30110. BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
30111. BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
30112. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
30113. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
30114. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
30115. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
30116. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
30117. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
30118. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
30119. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
30120. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
30121. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
30122. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
30123. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
30124. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
30125. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
30126. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
30127. BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
30128. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
30129. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
30130. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
30131. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
30132. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
30133. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
30134. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
30135. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
30136. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
30137. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
30138. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
30139. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
30140. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
30141. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
30142. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
30143. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
30144. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
30145. BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
30146. BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30147. BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30148. BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30149. BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30150. BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30151. BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30152. BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30153. BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30154. BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30155. BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30156. BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30157. BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30158. BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30159. BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30160. BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30161. BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30162. BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30163. BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30164. BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30165. BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30166. BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30167. BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30168. BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30169. BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30170. BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30171. BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30172. BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30173. BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30174. BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30175. BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30176. BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30177. BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30178. BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30179. BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30180. BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30181. BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30182. BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30183. BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30184. BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30185. BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30186. BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30187. BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30188. BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30189. BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30190. BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30191. BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30192. BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30193. BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30194. BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30195. BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30196. BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30197. BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30198. BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30199. BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30200. BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30201. BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30202. BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30203. BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30204. BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30205. BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30206. BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30207. BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30208. BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30209. BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30210. BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30211. BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30212. BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30213. BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30214. BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30215. BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30216. BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30217. BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30218. BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30219. BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30220. BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30221. BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30222. BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30223. BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30224. BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30225. BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30226. BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30227. BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30228. BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30229. BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30230. BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30231. BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30232. BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30233. BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30234. BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30235. BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30236. BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30237. BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30238. BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30239. BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30240. BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30241. BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30242. BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30243. BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30244. BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30245. BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30246. BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30247. BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30248. BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30249. BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30250. BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30251. BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30252. BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30253. BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30254. BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30255. BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30256. BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30257. BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30258. BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30259. BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30260. BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30261. BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30262. BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30263. BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30264. BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30265. BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30266. BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
30267. BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
30268. BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
30269. BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
30270. BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
30271. BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
30272. BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
30273. BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
30274. BIFPLR0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
30275. BIFPLR0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
30276. BIFPLR0_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
30277. BIFPLR0_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
30278. BIFPLR0_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
30279. BIFPLR0_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
30280. BIFPLR0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
30281. BIFPLR0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
30282. BIFPLR0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
30283. BIFPLR0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
30284. BIFPLR0_2_PCIE_LINK_CNTL3__RESERVED_MASK
30285. BIFPLR0_2_PCIE_LINK_CNTL3__RESERVED__SHIFT
30286. BIFPLR0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
30287. BIFPLR0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
30288. BIFPLR0_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
30289. BIFPLR0_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
30290. BIFPLR0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
30291. BIFPLR0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
30292. BIFPLR0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
30293. BIFPLR0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
30294. BIFPLR0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
30295. BIFPLR0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
30296. BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
30297. BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
30298. BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
30299. BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
30300. BIFPLR0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
30301. BIFPLR0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
30302. BIFPLR0_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK
30303. BIFPLR0_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
30304. BIFPLR0_2_PCIE_MC_CNTL__MC_ENABLE_MASK
30305. BIFPLR0_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT
30306. BIFPLR0_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
30307. BIFPLR0_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
30308. BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
30309. BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
30310. BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
30311. BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
30312. BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
30313. BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
30314. BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
30315. BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
30316. BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
30317. BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
30318. BIFPLR0_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
30319. BIFPLR0_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
30320. BIFPLR0_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
30321. BIFPLR0_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
30322. BIFPLR0_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
30323. BIFPLR0_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
30324. BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
30325. BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
30326. BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
30327. BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
30328. BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
30329. BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
30330. BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
30331. BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
30332. BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
30333. BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
30334. BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
30335. BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
30336. BIFPLR0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
30337. BIFPLR0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
30338. BIFPLR0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
30339. BIFPLR0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
30340. BIFPLR0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
30341. BIFPLR0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
30342. BIFPLR0_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
30343. BIFPLR0_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
30344. BIFPLR0_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
30345. BIFPLR0_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
30346. BIFPLR0_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
30347. BIFPLR0_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
30348. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
30349. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
30350. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
30351. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
30352. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
30353. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
30354. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
30355. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
30356. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
30357. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
30358. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
30359. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
30360. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
30361. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
30362. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
30363. BIFPLR0_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
30364. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
30365. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
30366. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
30367. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
30368. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
30369. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
30370. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
30371. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
30372. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
30373. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
30374. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
30375. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
30376. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
30377. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
30378. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
30379. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
30380. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
30381. BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
30382. BIFPLR0_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
30383. BIFPLR0_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
30384. BIFPLR0_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
30385. BIFPLR0_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
30386. BIFPLR0_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
30387. BIFPLR0_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
30388. BIFPLR0_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
30389. BIFPLR0_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
30390. BIFPLR0_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
30391. BIFPLR0_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
30392. BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
30393. BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
30394. BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK
30395. BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
30396. BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
30397. BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
30398. BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
30399. BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
30400. BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CTO_MASK
30401. BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
30402. BIFPLR0_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
30403. BIFPLR0_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
30404. BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
30405. BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
30406. BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK
30407. BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
30408. BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
30409. BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
30410. BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
30411. BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
30412. BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
30413. BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
30414. BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
30415. BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
30416. BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
30417. BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
30418. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
30419. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
30420. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
30421. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
30422. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
30423. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
30424. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
30425. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
30426. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
30427. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
30428. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
30429. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
30430. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
30431. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
30432. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
30433. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
30434. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
30435. BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
30436. BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
30437. BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
30438. BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
30439. BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
30440. BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
30441. BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
30442. BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
30443. BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
30444. BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK
30445. BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
30446. BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
30447. BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
30448. BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
30449. BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
30450. BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
30451. BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
30452. BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
30453. BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
30454. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
30455. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
30456. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
30457. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
30458. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
30459. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
30460. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
30461. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
30462. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
30463. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
30464. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
30465. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
30466. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
30467. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
30468. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
30469. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
30470. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
30471. BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
30472. BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
30473. BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
30474. BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
30475. BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
30476. BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
30477. BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
30478. BIFPLR0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
30479. BIFPLR0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
30480. BIFPLR0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
30481. BIFPLR0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
30482. BIFPLR0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
30483. BIFPLR0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
30484. BIFPLR0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
30485. BIFPLR0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
30486. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
30487. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
30488. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
30489. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
30490. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
30491. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
30492. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
30493. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
30494. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
30495. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
30496. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
30497. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
30498. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
30499. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
30500. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
30501. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
30502. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
30503. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
30504. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
30505. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
30506. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
30507. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
30508. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
30509. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
30510. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
30511. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
30512. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
30513. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
30514. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
30515. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
30516. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
30517. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
30518. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
30519. BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
30520. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
30521. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
30522. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
30523. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
30524. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
30525. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
30526. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
30527. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
30528. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
30529. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
30530. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
30531. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
30532. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
30533. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
30534. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
30535. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
30536. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
30537. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
30538. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
30539. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
30540. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
30541. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
30542. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
30543. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
30544. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
30545. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
30546. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
30547. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
30548. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
30549. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
30550. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
30551. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
30552. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
30553. BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
30554. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
30555. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
30556. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
30557. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
30558. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
30559. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
30560. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
30561. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
30562. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
30563. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
30564. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
30565. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
30566. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
30567. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
30568. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
30569. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
30570. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
30571. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
30572. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
30573. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
30574. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
30575. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
30576. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
30577. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
30578. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
30579. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
30580. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
30581. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
30582. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
30583. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
30584. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
30585. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
30586. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
30587. BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
30588. BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
30589. BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
30590. BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
30591. BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
30592. BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
30593. BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
30594. BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
30595. BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
30596. BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
30597. BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
30598. BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
30599. BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
30600. BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
30601. BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
30602. BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
30603. BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
30604. BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
30605. BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
30606. BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
30607. BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
30608. BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
30609. BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
30610. BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
30611. BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
30612. BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
30613. BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
30614. BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
30615. BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
30616. BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
30617. BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
30618. BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
30619. BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
30620. BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
30621. BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
30622. BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
30623. BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
30624. BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
30625. BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
30626. BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
30627. BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
30628. BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
30629. BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
30630. BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
30631. BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
30632. BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
30633. BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
30634. BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
30635. BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
30636. BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
30637. BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
30638. BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
30639. BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
30640. BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
30641. BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
30642. BIFPLR0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
30643. BIFPLR0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
30644. BIFPLR0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
30645. BIFPLR0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
30646. BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
30647. BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
30648. BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
30649. BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
30650. BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
30651. BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
30652. BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
30653. BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
30654. BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
30655. BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
30656. BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
30657. BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
30658. BIFPLR0_2_PMI_CAP_LIST__CAP_ID_MASK
30659. BIFPLR0_2_PMI_CAP_LIST__CAP_ID__SHIFT
30660. BIFPLR0_2_PMI_CAP_LIST__NEXT_PTR_MASK
30661. BIFPLR0_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
30662. BIFPLR0_2_PMI_CAP__AUX_CURRENT_MASK
30663. BIFPLR0_2_PMI_CAP__AUX_CURRENT__SHIFT
30664. BIFPLR0_2_PMI_CAP__D1_SUPPORT_MASK
30665. BIFPLR0_2_PMI_CAP__D1_SUPPORT__SHIFT
30666. BIFPLR0_2_PMI_CAP__D2_SUPPORT_MASK
30667. BIFPLR0_2_PMI_CAP__D2_SUPPORT__SHIFT
30668. BIFPLR0_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
30669. BIFPLR0_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
30670. BIFPLR0_2_PMI_CAP__PME_CLOCK_MASK
30671. BIFPLR0_2_PMI_CAP__PME_CLOCK__SHIFT
30672. BIFPLR0_2_PMI_CAP__PME_SUPPORT_MASK
30673. BIFPLR0_2_PMI_CAP__PME_SUPPORT__SHIFT
30674. BIFPLR0_2_PMI_CAP__VERSION_MASK
30675. BIFPLR0_2_PMI_CAP__VERSION__SHIFT
30676. BIFPLR0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
30677. BIFPLR0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
30678. BIFPLR0_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
30679. BIFPLR0_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
30680. BIFPLR0_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
30681. BIFPLR0_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
30682. BIFPLR0_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
30683. BIFPLR0_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
30684. BIFPLR0_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
30685. BIFPLR0_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
30686. BIFPLR0_2_PMI_STATUS_CNTL__PME_EN_MASK
30687. BIFPLR0_2_PMI_STATUS_CNTL__PME_EN__SHIFT
30688. BIFPLR0_2_PMI_STATUS_CNTL__PME_STATUS_MASK
30689. BIFPLR0_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
30690. BIFPLR0_2_PMI_STATUS_CNTL__PMI_DATA_MASK
30691. BIFPLR0_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
30692. BIFPLR0_2_PMI_STATUS_CNTL__POWER_STATE_MASK
30693. BIFPLR0_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
30694. BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
30695. BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
30696. BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
30697. BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
30698. BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
30699. BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
30700. BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
30701. BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
30702. BIFPLR0_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
30703. BIFPLR0_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
30704. BIFPLR0_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
30705. BIFPLR0_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
30706. BIFPLR0_2_PROG_INTERFACE__PROG_INTERFACE_MASK
30707. BIFPLR0_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
30708. BIFPLR0_2_REVISION_ID__MAJOR_REV_ID_MASK
30709. BIFPLR0_2_REVISION_ID__MAJOR_REV_ID__SHIFT
30710. BIFPLR0_2_REVISION_ID__MINOR_REV_ID_MASK
30711. BIFPLR0_2_REVISION_ID__MINOR_REV_ID__SHIFT
30712. BIFPLR0_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
30713. BIFPLR0_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
30714. BIFPLR0_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
30715. BIFPLR0_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
30716. BIFPLR0_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK
30717. BIFPLR0_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
30718. BIFPLR0_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
30719. BIFPLR0_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
30720. BIFPLR0_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
30721. BIFPLR0_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
30722. BIFPLR0_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
30723. BIFPLR0_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
30724. BIFPLR0_2_ROOT_STATUS__PME_PENDING_MASK
30725. BIFPLR0_2_ROOT_STATUS__PME_PENDING__SHIFT
30726. BIFPLR0_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK
30727. BIFPLR0_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
30728. BIFPLR0_2_ROOT_STATUS__PME_STATUS_MASK
30729. BIFPLR0_2_ROOT_STATUS__PME_STATUS__SHIFT
30730. BIFPLR0_2_SECONDARY_STATUS__CAP_LIST_MASK
30731. BIFPLR0_2_SECONDARY_STATUS__CAP_LIST__SHIFT
30732. BIFPLR0_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK
30733. BIFPLR0_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
30734. BIFPLR0_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
30735. BIFPLR0_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
30736. BIFPLR0_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
30737. BIFPLR0_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
30738. BIFPLR0_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
30739. BIFPLR0_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
30740. BIFPLR0_2_SECONDARY_STATUS__PCI_66_EN_MASK
30741. BIFPLR0_2_SECONDARY_STATUS__PCI_66_EN__SHIFT
30742. BIFPLR0_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
30743. BIFPLR0_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
30744. BIFPLR0_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
30745. BIFPLR0_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
30746. BIFPLR0_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
30747. BIFPLR0_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
30748. BIFPLR0_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
30749. BIFPLR0_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
30750. BIFPLR0_2_SLOT_CAP2__RESERVED_MASK
30751. BIFPLR0_2_SLOT_CAP2__RESERVED__SHIFT
30752. BIFPLR0_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
30753. BIFPLR0_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
30754. BIFPLR0_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
30755. BIFPLR0_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
30756. BIFPLR0_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
30757. BIFPLR0_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
30758. BIFPLR0_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK
30759. BIFPLR0_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
30760. BIFPLR0_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK
30761. BIFPLR0_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
30762. BIFPLR0_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
30763. BIFPLR0_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
30764. BIFPLR0_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
30765. BIFPLR0_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
30766. BIFPLR0_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
30767. BIFPLR0_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
30768. BIFPLR0_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
30769. BIFPLR0_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
30770. BIFPLR0_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
30771. BIFPLR0_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
30772. BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
30773. BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
30774. BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
30775. BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
30776. BIFPLR0_2_SLOT_CNTL2__RESERVED_MASK
30777. BIFPLR0_2_SLOT_CNTL2__RESERVED__SHIFT
30778. BIFPLR0_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
30779. BIFPLR0_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
30780. BIFPLR0_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
30781. BIFPLR0_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
30782. BIFPLR0_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
30783. BIFPLR0_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
30784. BIFPLR0_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
30785. BIFPLR0_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
30786. BIFPLR0_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
30787. BIFPLR0_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
30788. BIFPLR0_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
30789. BIFPLR0_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
30790. BIFPLR0_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
30791. BIFPLR0_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
30792. BIFPLR0_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
30793. BIFPLR0_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
30794. BIFPLR0_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
30795. BIFPLR0_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
30796. BIFPLR0_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
30797. BIFPLR0_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
30798. BIFPLR0_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
30799. BIFPLR0_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
30800. BIFPLR0_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
30801. BIFPLR0_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
30802. BIFPLR0_2_SLOT_STATUS2__RESERVED_MASK
30803. BIFPLR0_2_SLOT_STATUS2__RESERVED__SHIFT
30804. BIFPLR0_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
30805. BIFPLR0_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
30806. BIFPLR0_2_SLOT_STATUS__COMMAND_COMPLETED_MASK
30807. BIFPLR0_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
30808. BIFPLR0_2_SLOT_STATUS__DL_STATE_CHANGED_MASK
30809. BIFPLR0_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
30810. BIFPLR0_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
30811. BIFPLR0_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
30812. BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
30813. BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
30814. BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK
30815. BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
30816. BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
30817. BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
30818. BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
30819. BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
30820. BIFPLR0_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
30821. BIFPLR0_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
30822. BIFPLR0_2_SSID_CAP_LIST__CAP_ID_MASK
30823. BIFPLR0_2_SSID_CAP_LIST__CAP_ID__SHIFT
30824. BIFPLR0_2_SSID_CAP_LIST__NEXT_PTR_MASK
30825. BIFPLR0_2_SSID_CAP_LIST__NEXT_PTR__SHIFT
30826. BIFPLR0_2_SSID_CAP__SUBSYSTEM_ID_MASK
30827. BIFPLR0_2_SSID_CAP__SUBSYSTEM_ID__SHIFT
30828. BIFPLR0_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
30829. BIFPLR0_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
30830. BIFPLR0_2_STATUS__CAP_LIST_MASK
30831. BIFPLR0_2_STATUS__CAP_LIST__SHIFT
30832. BIFPLR0_2_STATUS__DEVSEL_TIMING_MASK
30833. BIFPLR0_2_STATUS__DEVSEL_TIMING__SHIFT
30834. BIFPLR0_2_STATUS__FAST_BACK_CAPABLE_MASK
30835. BIFPLR0_2_STATUS__FAST_BACK_CAPABLE__SHIFT
30836. BIFPLR0_2_STATUS__INT_STATUS_MASK
30837. BIFPLR0_2_STATUS__INT_STATUS__SHIFT
30838. BIFPLR0_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
30839. BIFPLR0_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
30840. BIFPLR0_2_STATUS__PARITY_ERROR_DETECTED_MASK
30841. BIFPLR0_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
30842. BIFPLR0_2_STATUS__PCI_66_EN_MASK
30843. BIFPLR0_2_STATUS__PCI_66_EN__SHIFT
30844. BIFPLR0_2_STATUS__RECEIVED_MASTER_ABORT_MASK
30845. BIFPLR0_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
30846. BIFPLR0_2_STATUS__RECEIVED_TARGET_ABORT_MASK
30847. BIFPLR0_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
30848. BIFPLR0_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
30849. BIFPLR0_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
30850. BIFPLR0_2_STATUS__SIGNAL_TARGET_ABORT_MASK
30851. BIFPLR0_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
30852. BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
30853. BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
30854. BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
30855. BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
30856. BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
30857. BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
30858. BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
30859. BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
30860. BIFPLR0_2_SUB_CLASS__SUB_CLASS_MASK
30861. BIFPLR0_2_SUB_CLASS__SUB_CLASS__SHIFT
30862. BIFPLR0_2_VENDOR_ID__VENDOR_ID_MASK
30863. BIFPLR0_2_VENDOR_ID__VENDOR_ID__SHIFT
30864. BIFPLR1_0_BASE_CLASS__BASE_CLASS_MASK
30865. BIFPLR1_0_BASE_CLASS__BASE_CLASS__SHIFT
30866. BIFPLR1_0_BIST__BIST_CAP_MASK
30867. BIFPLR1_0_BIST__BIST_CAP__SHIFT
30868. BIFPLR1_0_BIST__BIST_COMP_MASK
30869. BIFPLR1_0_BIST__BIST_COMP__SHIFT
30870. BIFPLR1_0_BIST__BIST_STRT_MASK
30871. BIFPLR1_0_BIST__BIST_STRT__SHIFT
30872. BIFPLR1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
30873. BIFPLR1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
30874. BIFPLR1_0_CAP_PTR__CAP_PTR_MASK
30875. BIFPLR1_0_CAP_PTR__CAP_PTR__SHIFT
30876. BIFPLR1_0_COMMAND__AD_STEPPING_MASK
30877. BIFPLR1_0_COMMAND__AD_STEPPING__SHIFT
30878. BIFPLR1_0_COMMAND__BUS_MASTER_EN_MASK
30879. BIFPLR1_0_COMMAND__BUS_MASTER_EN__SHIFT
30880. BIFPLR1_0_COMMAND__FAST_B2B_EN_MASK
30881. BIFPLR1_0_COMMAND__FAST_B2B_EN__SHIFT
30882. BIFPLR1_0_COMMAND__INT_DIS_MASK
30883. BIFPLR1_0_COMMAND__INT_DIS__SHIFT
30884. BIFPLR1_0_COMMAND__IO_ACCESS_EN_MASK
30885. BIFPLR1_0_COMMAND__IO_ACCESS_EN__SHIFT
30886. BIFPLR1_0_COMMAND__MEM_ACCESS_EN_MASK
30887. BIFPLR1_0_COMMAND__MEM_ACCESS_EN__SHIFT
30888. BIFPLR1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
30889. BIFPLR1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
30890. BIFPLR1_0_COMMAND__PAL_SNOOP_EN_MASK
30891. BIFPLR1_0_COMMAND__PAL_SNOOP_EN__SHIFT
30892. BIFPLR1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
30893. BIFPLR1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
30894. BIFPLR1_0_COMMAND__SERR_EN_MASK
30895. BIFPLR1_0_COMMAND__SERR_EN__SHIFT
30896. BIFPLR1_0_COMMAND__SPECIAL_CYCLE_EN_MASK
30897. BIFPLR1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
30898. BIFPLR1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
30899. BIFPLR1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
30900. BIFPLR1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
30901. BIFPLR1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
30902. BIFPLR1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
30903. BIFPLR1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
30904. BIFPLR1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
30905. BIFPLR1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
30906. BIFPLR1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
30907. BIFPLR1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
30908. BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
30909. BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
30910. BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
30911. BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
30912. BIFPLR1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
30913. BIFPLR1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
30914. BIFPLR1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
30915. BIFPLR1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
30916. BIFPLR1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
30917. BIFPLR1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
30918. BIFPLR1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
30919. BIFPLR1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
30920. BIFPLR1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
30921. BIFPLR1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
30922. BIFPLR1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
30923. BIFPLR1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
30924. BIFPLR1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
30925. BIFPLR1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
30926. BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
30927. BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
30928. BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
30929. BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
30930. BIFPLR1_0_DEVICE_CAP__EXTENDED_TAG_MASK
30931. BIFPLR1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
30932. BIFPLR1_0_DEVICE_CAP__FLR_CAPABLE_MASK
30933. BIFPLR1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
30934. BIFPLR1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
30935. BIFPLR1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
30936. BIFPLR1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
30937. BIFPLR1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
30938. BIFPLR1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
30939. BIFPLR1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
30940. BIFPLR1_0_DEVICE_CAP__PHANTOM_FUNC_MASK
30941. BIFPLR1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
30942. BIFPLR1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
30943. BIFPLR1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
30944. BIFPLR1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
30945. BIFPLR1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
30946. BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
30947. BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
30948. BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
30949. BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
30950. BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
30951. BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
30952. BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
30953. BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
30954. BIFPLR1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
30955. BIFPLR1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
30956. BIFPLR1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
30957. BIFPLR1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
30958. BIFPLR1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
30959. BIFPLR1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
30960. BIFPLR1_0_DEVICE_CNTL2__LTR_EN_MASK
30961. BIFPLR1_0_DEVICE_CNTL2__LTR_EN__SHIFT
30962. BIFPLR1_0_DEVICE_CNTL2__OBFF_EN_MASK
30963. BIFPLR1_0_DEVICE_CNTL2__OBFF_EN__SHIFT
30964. BIFPLR1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
30965. BIFPLR1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
30966. BIFPLR1_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
30967. BIFPLR1_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
30968. BIFPLR1_0_DEVICE_CNTL__CORR_ERR_EN_MASK
30969. BIFPLR1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
30970. BIFPLR1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
30971. BIFPLR1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
30972. BIFPLR1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
30973. BIFPLR1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
30974. BIFPLR1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
30975. BIFPLR1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
30976. BIFPLR1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
30977. BIFPLR1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
30978. BIFPLR1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
30979. BIFPLR1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
30980. BIFPLR1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
30981. BIFPLR1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
30982. BIFPLR1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
30983. BIFPLR1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
30984. BIFPLR1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
30985. BIFPLR1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
30986. BIFPLR1_0_DEVICE_CNTL__USR_REPORT_EN_MASK
30987. BIFPLR1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
30988. BIFPLR1_0_DEVICE_ID__DEVICE_ID_MASK
30989. BIFPLR1_0_DEVICE_ID__DEVICE_ID__SHIFT
30990. BIFPLR1_0_DEVICE_STATUS2__RESERVED_MASK
30991. BIFPLR1_0_DEVICE_STATUS2__RESERVED__SHIFT
30992. BIFPLR1_0_DEVICE_STATUS__AUX_PWR_MASK
30993. BIFPLR1_0_DEVICE_STATUS__AUX_PWR__SHIFT
30994. BIFPLR1_0_DEVICE_STATUS__CORR_ERR_MASK
30995. BIFPLR1_0_DEVICE_STATUS__CORR_ERR__SHIFT
30996. BIFPLR1_0_DEVICE_STATUS__FATAL_ERR_MASK
30997. BIFPLR1_0_DEVICE_STATUS__FATAL_ERR__SHIFT
30998. BIFPLR1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
30999. BIFPLR1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
31000. BIFPLR1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
31001. BIFPLR1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
31002. BIFPLR1_0_DEVICE_STATUS__USR_DETECTED_MASK
31003. BIFPLR1_0_DEVICE_STATUS__USR_DETECTED__SHIFT
31004. BIFPLR1_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
31005. BIFPLR1_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
31006. BIFPLR1_0_HEADER__DEVICE_TYPE_MASK
31007. BIFPLR1_0_HEADER__DEVICE_TYPE__SHIFT
31008. BIFPLR1_0_HEADER__HEADER_TYPE_MASK
31009. BIFPLR1_0_HEADER__HEADER_TYPE__SHIFT
31010. BIFPLR1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
31011. BIFPLR1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
31012. BIFPLR1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
31013. BIFPLR1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
31014. BIFPLR1_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
31015. BIFPLR1_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
31016. BIFPLR1_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
31017. BIFPLR1_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
31018. BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_MASK
31019. BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
31020. BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
31021. BIFPLR1_0_IO_BASE_LIMIT__IO_BASE__SHIFT
31022. BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_MASK
31023. BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
31024. BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
31025. BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT
31026. BIFPLR1_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
31027. BIFPLR1_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
31028. BIFPLR1_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK
31029. BIFPLR1_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
31030. BIFPLR1_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
31031. BIFPLR1_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
31032. BIFPLR1_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
31033. BIFPLR1_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
31034. BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
31035. BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
31036. BIFPLR1_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK
31037. BIFPLR1_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
31038. BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
31039. BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
31040. BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK
31041. BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
31042. BIFPLR1_0_LATENCY__LATENCY_TIMER_MASK
31043. BIFPLR1_0_LATENCY__LATENCY_TIMER__SHIFT
31044. BIFPLR1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
31045. BIFPLR1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
31046. BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
31047. BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
31048. BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
31049. BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
31050. BIFPLR1_0_LINK_CAP2__RESERVED_MASK
31051. BIFPLR1_0_LINK_CAP2__RESERVED__SHIFT
31052. BIFPLR1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
31053. BIFPLR1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
31054. BIFPLR1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
31055. BIFPLR1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
31056. BIFPLR1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
31057. BIFPLR1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
31058. BIFPLR1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
31059. BIFPLR1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
31060. BIFPLR1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
31061. BIFPLR1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
31062. BIFPLR1_0_LINK_CAP__L1_EXIT_LATENCY_MASK
31063. BIFPLR1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
31064. BIFPLR1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
31065. BIFPLR1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
31066. BIFPLR1_0_LINK_CAP__LINK_SPEED_MASK
31067. BIFPLR1_0_LINK_CAP__LINK_SPEED__SHIFT
31068. BIFPLR1_0_LINK_CAP__LINK_WIDTH_MASK
31069. BIFPLR1_0_LINK_CAP__LINK_WIDTH__SHIFT
31070. BIFPLR1_0_LINK_CAP__PM_SUPPORT_MASK
31071. BIFPLR1_0_LINK_CAP__PM_SUPPORT__SHIFT
31072. BIFPLR1_0_LINK_CAP__PORT_NUMBER_MASK
31073. BIFPLR1_0_LINK_CAP__PORT_NUMBER__SHIFT
31074. BIFPLR1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
31075. BIFPLR1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
31076. BIFPLR1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
31077. BIFPLR1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
31078. BIFPLR1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
31079. BIFPLR1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
31080. BIFPLR1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
31081. BIFPLR1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
31082. BIFPLR1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
31083. BIFPLR1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
31084. BIFPLR1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
31085. BIFPLR1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
31086. BIFPLR1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
31087. BIFPLR1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
31088. BIFPLR1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
31089. BIFPLR1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
31090. BIFPLR1_0_LINK_CNTL2__XMIT_MARGIN_MASK
31091. BIFPLR1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
31092. BIFPLR1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
31093. BIFPLR1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
31094. BIFPLR1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
31095. BIFPLR1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
31096. BIFPLR1_0_LINK_CNTL__EXTENDED_SYNC_MASK
31097. BIFPLR1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
31098. BIFPLR1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
31099. BIFPLR1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
31100. BIFPLR1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
31101. BIFPLR1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
31102. BIFPLR1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
31103. BIFPLR1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
31104. BIFPLR1_0_LINK_CNTL__LINK_DIS_MASK
31105. BIFPLR1_0_LINK_CNTL__LINK_DIS__SHIFT
31106. BIFPLR1_0_LINK_CNTL__PM_CONTROL_MASK
31107. BIFPLR1_0_LINK_CNTL__PM_CONTROL__SHIFT
31108. BIFPLR1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
31109. BIFPLR1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
31110. BIFPLR1_0_LINK_CNTL__RETRAIN_LINK_MASK
31111. BIFPLR1_0_LINK_CNTL__RETRAIN_LINK__SHIFT
31112. BIFPLR1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
31113. BIFPLR1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
31114. BIFPLR1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
31115. BIFPLR1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
31116. BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
31117. BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
31118. BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
31119. BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
31120. BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
31121. BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
31122. BIFPLR1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
31123. BIFPLR1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
31124. BIFPLR1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
31125. BIFPLR1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
31126. BIFPLR1_0_LINK_STATUS__DL_ACTIVE_MASK
31127. BIFPLR1_0_LINK_STATUS__DL_ACTIVE__SHIFT
31128. BIFPLR1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
31129. BIFPLR1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
31130. BIFPLR1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
31131. BIFPLR1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
31132. BIFPLR1_0_LINK_STATUS__LINK_TRAINING_MASK
31133. BIFPLR1_0_LINK_STATUS__LINK_TRAINING__SHIFT
31134. BIFPLR1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
31135. BIFPLR1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
31136. BIFPLR1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
31137. BIFPLR1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
31138. BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
31139. BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
31140. BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
31141. BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
31142. BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
31143. BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
31144. BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
31145. BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
31146. BIFPLR1_0_MSI_CAP_LIST__CAP_ID_MASK
31147. BIFPLR1_0_MSI_CAP_LIST__CAP_ID__SHIFT
31148. BIFPLR1_0_MSI_CAP_LIST__NEXT_PTR_MASK
31149. BIFPLR1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
31150. BIFPLR1_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
31151. BIFPLR1_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
31152. BIFPLR1_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
31153. BIFPLR1_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
31154. BIFPLR1_0_MSI_MAP_CAP_LIST__CAP_ID_MASK
31155. BIFPLR1_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
31156. BIFPLR1_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
31157. BIFPLR1_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
31158. BIFPLR1_0_MSI_MAP_CAP__CAP_TYPE_MASK
31159. BIFPLR1_0_MSI_MAP_CAP__CAP_TYPE__SHIFT
31160. BIFPLR1_0_MSI_MAP_CAP__EN_MASK
31161. BIFPLR1_0_MSI_MAP_CAP__EN__SHIFT
31162. BIFPLR1_0_MSI_MAP_CAP__FIXD_MASK
31163. BIFPLR1_0_MSI_MAP_CAP__FIXD__SHIFT
31164. BIFPLR1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
31165. BIFPLR1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
31166. BIFPLR1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
31167. BIFPLR1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
31168. BIFPLR1_0_MSI_MSG_CNTL__MSI_64BIT_MASK
31169. BIFPLR1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
31170. BIFPLR1_0_MSI_MSG_CNTL__MSI_EN_MASK
31171. BIFPLR1_0_MSI_MSG_CNTL__MSI_EN__SHIFT
31172. BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
31173. BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
31174. BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
31175. BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
31176. BIFPLR1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
31177. BIFPLR1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
31178. BIFPLR1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
31179. BIFPLR1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
31180. BIFPLR1_0_MSI_MSG_DATA__MSI_DATA_MASK
31181. BIFPLR1_0_MSI_MSG_DATA__MSI_DATA__SHIFT
31182. BIFPLR1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
31183. BIFPLR1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
31184. BIFPLR1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
31185. BIFPLR1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
31186. BIFPLR1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
31187. BIFPLR1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
31188. BIFPLR1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
31189. BIFPLR1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
31190. BIFPLR1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
31191. BIFPLR1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
31192. BIFPLR1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
31193. BIFPLR1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
31194. BIFPLR1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
31195. BIFPLR1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
31196. BIFPLR1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
31197. BIFPLR1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
31198. BIFPLR1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
31199. BIFPLR1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
31200. BIFPLR1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
31201. BIFPLR1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
31202. BIFPLR1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
31203. BIFPLR1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
31204. BIFPLR1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
31205. BIFPLR1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
31206. BIFPLR1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
31207. BIFPLR1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
31208. BIFPLR1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
31209. BIFPLR1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
31210. BIFPLR1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
31211. BIFPLR1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
31212. BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
31213. BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
31214. BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
31215. BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
31216. BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
31217. BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
31218. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
31219. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
31220. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
31221. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
31222. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
31223. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
31224. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
31225. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
31226. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
31227. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
31228. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
31229. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
31230. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
31231. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
31232. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
31233. BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
31234. BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
31235. BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
31236. BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
31237. BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
31238. BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
31239. BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
31240. BIFPLR1_0_PCIE_CAP_LIST__CAP_ID_MASK
31241. BIFPLR1_0_PCIE_CAP_LIST__CAP_ID__SHIFT
31242. BIFPLR1_0_PCIE_CAP_LIST__NEXT_PTR_MASK
31243. BIFPLR1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
31244. BIFPLR1_0_PCIE_CAP__DEVICE_TYPE_MASK
31245. BIFPLR1_0_PCIE_CAP__DEVICE_TYPE__SHIFT
31246. BIFPLR1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
31247. BIFPLR1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
31248. BIFPLR1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
31249. BIFPLR1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
31250. BIFPLR1_0_PCIE_CAP__VERSION_MASK
31251. BIFPLR1_0_PCIE_CAP__VERSION__SHIFT
31252. BIFPLR1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
31253. BIFPLR1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
31254. BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
31255. BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
31256. BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
31257. BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
31258. BIFPLR1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
31259. BIFPLR1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
31260. BIFPLR1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
31261. BIFPLR1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
31262. BIFPLR1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
31263. BIFPLR1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
31264. BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
31265. BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
31266. BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
31267. BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
31268. BIFPLR1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
31269. BIFPLR1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
31270. BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
31271. BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
31272. BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
31273. BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
31274. BIFPLR1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
31275. BIFPLR1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
31276. BIFPLR1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
31277. BIFPLR1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
31278. BIFPLR1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
31279. BIFPLR1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
31280. BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
31281. BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
31282. BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
31283. BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
31284. BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
31285. BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
31286. BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
31287. BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
31288. BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
31289. BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
31290. BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
31291. BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
31292. BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
31293. BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
31294. BIFPLR1_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
31295. BIFPLR1_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
31296. BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
31297. BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
31298. BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
31299. BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
31300. BIFPLR1_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
31301. BIFPLR1_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
31302. BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
31303. BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
31304. BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
31305. BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
31306. BIFPLR1_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
31307. BIFPLR1_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
31308. BIFPLR1_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
31309. BIFPLR1_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
31310. BIFPLR1_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
31311. BIFPLR1_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
31312. BIFPLR1_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
31313. BIFPLR1_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
31314. BIFPLR1_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
31315. BIFPLR1_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
31316. BIFPLR1_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
31317. BIFPLR1_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
31318. BIFPLR1_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
31319. BIFPLR1_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
31320. BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
31321. BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
31322. BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
31323. BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
31324. BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
31325. BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
31326. BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
31327. BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
31328. BIFPLR1_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
31329. BIFPLR1_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
31330. BIFPLR1_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
31331. BIFPLR1_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
31332. BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
31333. BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
31334. BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
31335. BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
31336. BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
31337. BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
31338. BIFPLR1_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
31339. BIFPLR1_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
31340. BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
31341. BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
31342. BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
31343. BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
31344. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK
31345. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
31346. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK
31347. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
31348. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK
31349. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
31350. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK
31351. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
31352. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK
31353. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
31354. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK
31355. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
31356. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK
31357. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
31358. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK
31359. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
31360. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK
31361. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
31362. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK
31363. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
31364. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK
31365. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
31366. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK
31367. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
31368. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK
31369. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
31370. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK
31371. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
31372. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK
31373. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
31374. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK
31375. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
31376. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK
31377. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
31378. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK
31379. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
31380. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK
31381. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
31382. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK
31383. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
31384. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK
31385. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
31386. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK
31387. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
31388. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK
31389. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
31390. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK
31391. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
31392. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK
31393. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
31394. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK
31395. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
31396. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK
31397. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
31398. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK
31399. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
31400. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK
31401. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
31402. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK
31403. BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
31404. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK
31405. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
31406. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK
31407. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
31408. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK
31409. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
31410. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK
31411. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
31412. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK
31413. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
31414. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK
31415. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
31416. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK
31417. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
31418. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK
31419. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
31420. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK
31421. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
31422. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK
31423. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
31424. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK
31425. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
31426. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK
31427. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
31428. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK
31429. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
31430. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK
31431. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
31432. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK
31433. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
31434. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK
31435. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
31436. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK
31437. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
31438. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK
31439. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
31440. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK
31441. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
31442. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK
31443. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
31444. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK
31445. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
31446. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK
31447. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
31448. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK
31449. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
31450. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK
31451. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
31452. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK
31453. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
31454. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK
31455. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
31456. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK
31457. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
31458. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK
31459. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
31460. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK
31461. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
31462. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK
31463. BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
31464. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK
31465. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
31466. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK
31467. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
31468. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK
31469. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
31470. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK
31471. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
31472. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK
31473. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
31474. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK
31475. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
31476. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK
31477. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
31478. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK
31479. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
31480. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK
31481. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
31482. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK
31483. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
31484. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK
31485. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
31486. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK
31487. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
31488. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK
31489. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
31490. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK
31491. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
31492. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK
31493. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
31494. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK
31495. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
31496. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK
31497. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
31498. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK
31499. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
31500. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK
31501. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
31502. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK
31503. BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
31504. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK
31505. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
31506. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK
31507. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
31508. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK
31509. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
31510. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK
31511. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
31512. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK
31513. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
31514. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK
31515. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
31516. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK
31517. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
31518. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK
31519. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
31520. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK
31521. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
31522. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK
31523. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
31524. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK
31525. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
31526. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK
31527. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
31528. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK
31529. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
31530. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK
31531. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
31532. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK
31533. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
31534. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK
31535. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
31536. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK
31537. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
31538. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK
31539. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
31540. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK
31541. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
31542. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK
31543. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
31544. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK
31545. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
31546. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK
31547. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
31548. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK
31549. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
31550. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK
31551. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
31552. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK
31553. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
31554. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK
31555. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
31556. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK
31557. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
31558. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK
31559. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
31560. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK
31561. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
31562. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK
31563. BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
31564. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK
31565. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
31566. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK
31567. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
31568. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK
31569. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
31570. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK
31571. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
31572. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK
31573. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
31574. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK
31575. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
31576. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK
31577. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
31578. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK
31579. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
31580. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK
31581. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
31582. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK
31583. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
31584. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK
31585. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
31586. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK
31587. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
31588. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK
31589. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
31590. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK
31591. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
31592. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK
31593. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
31594. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK
31595. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
31596. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK
31597. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
31598. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK
31599. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
31600. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK
31601. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
31602. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK
31603. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
31604. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK
31605. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
31606. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK
31607. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
31608. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK
31609. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
31610. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK
31611. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
31612. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK
31613. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
31614. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK
31615. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
31616. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK
31617. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
31618. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK
31619. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
31620. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK
31621. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
31622. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK
31623. BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
31624. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK
31625. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
31626. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK
31627. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
31628. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK
31629. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
31630. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK
31631. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
31632. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK
31633. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
31634. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK
31635. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
31636. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK
31637. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
31638. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK
31639. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
31640. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK
31641. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
31642. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK
31643. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
31644. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK
31645. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
31646. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK
31647. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
31648. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK
31649. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
31650. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK
31651. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
31652. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK
31653. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
31654. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK
31655. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
31656. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK
31657. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
31658. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK
31659. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
31660. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK
31661. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
31662. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK
31663. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
31664. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK
31665. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
31666. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK
31667. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
31668. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK
31669. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
31670. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK
31671. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
31672. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK
31673. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
31674. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK
31675. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
31676. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK
31677. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
31678. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK
31679. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
31680. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK
31681. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
31682. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK
31683. BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
31684. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK
31685. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
31686. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK
31687. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
31688. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK
31689. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
31690. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK
31691. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
31692. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK
31693. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
31694. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK
31695. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
31696. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK
31697. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
31698. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK
31699. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
31700. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK
31701. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
31702. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK
31703. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
31704. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK
31705. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
31706. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK
31707. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
31708. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK
31709. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
31710. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK
31711. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
31712. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK
31713. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
31714. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK
31715. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
31716. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK
31717. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
31718. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK
31719. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
31720. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK
31721. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
31722. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK
31723. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
31724. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK
31725. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
31726. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK
31727. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
31728. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK
31729. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
31730. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK
31731. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
31732. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK
31733. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
31734. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK
31735. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
31736. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK
31737. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
31738. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK
31739. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
31740. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK
31741. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
31742. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK
31743. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
31744. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK
31745. BIFPLR1_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
31746. BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK
31747. BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
31748. BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK
31749. BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
31750. BIFPLR1_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
31751. BIFPLR1_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
31752. BIFPLR1_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK
31753. BIFPLR1_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
31754. BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
31755. BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
31756. BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
31757. BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
31758. BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
31759. BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
31760. BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
31761. BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
31762. BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
31763. BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
31764. BIFPLR1_0_PCIE_ESM_HEADER_2__CAP_ID_MASK
31765. BIFPLR1_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
31766. BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
31767. BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
31768. BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
31769. BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
31770. BIFPLR1_0_PCIE_HDR_LOG0__TLP_HDR_MASK
31771. BIFPLR1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
31772. BIFPLR1_0_PCIE_HDR_LOG1__TLP_HDR_MASK
31773. BIFPLR1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
31774. BIFPLR1_0_PCIE_HDR_LOG2__TLP_HDR_MASK
31775. BIFPLR1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
31776. BIFPLR1_0_PCIE_HDR_LOG3__TLP_HDR_MASK
31777. BIFPLR1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
31778. BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
31779. BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
31780. BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
31781. BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
31782. BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
31783. BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
31784. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
31785. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
31786. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
31787. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
31788. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
31789. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
31790. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
31791. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
31792. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
31793. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
31794. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
31795. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
31796. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
31797. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
31798. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
31799. BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
31800. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
31801. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
31802. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
31803. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
31804. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
31805. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
31806. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
31807. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
31808. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
31809. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
31810. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
31811. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
31812. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
31813. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
31814. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
31815. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
31816. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
31817. BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
31818. BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31819. BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31820. BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31821. BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31822. BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31823. BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31824. BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31825. BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31826. BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31827. BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31828. BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31829. BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31830. BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31831. BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31832. BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31833. BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31834. BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31835. BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31836. BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31837. BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31838. BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31839. BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31840. BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31841. BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31842. BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31843. BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31844. BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31845. BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31846. BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31847. BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31848. BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31849. BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31850. BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31851. BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31852. BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31853. BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31854. BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31855. BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31856. BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31857. BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31858. BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31859. BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31860. BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31861. BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31862. BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31863. BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31864. BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31865. BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31866. BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31867. BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31868. BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31869. BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31870. BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31871. BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31872. BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31873. BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31874. BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31875. BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31876. BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31877. BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31878. BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31879. BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31880. BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31881. BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31882. BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31883. BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31884. BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31885. BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31886. BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31887. BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31888. BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31889. BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31890. BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31891. BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31892. BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31893. BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31894. BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31895. BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31896. BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31897. BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31898. BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31899. BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31900. BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31901. BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31902. BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31903. BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31904. BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31905. BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31906. BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31907. BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31908. BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31909. BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31910. BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31911. BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31912. BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31913. BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31914. BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31915. BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31916. BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31917. BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31918. BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31919. BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31920. BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31921. BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31922. BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31923. BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31924. BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31925. BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31926. BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31927. BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31928. BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31929. BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31930. BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31931. BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31932. BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31933. BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31934. BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31935. BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31936. BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31937. BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31938. BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
31939. BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
31940. BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
31941. BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
31942. BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
31943. BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
31944. BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
31945. BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
31946. BIFPLR1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
31947. BIFPLR1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
31948. BIFPLR1_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
31949. BIFPLR1_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
31950. BIFPLR1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
31951. BIFPLR1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
31952. BIFPLR1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
31953. BIFPLR1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
31954. BIFPLR1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
31955. BIFPLR1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
31956. BIFPLR1_0_PCIE_LINK_CNTL3__RESERVED_MASK
31957. BIFPLR1_0_PCIE_LINK_CNTL3__RESERVED__SHIFT
31958. BIFPLR1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
31959. BIFPLR1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
31960. BIFPLR1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
31961. BIFPLR1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
31962. BIFPLR1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
31963. BIFPLR1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
31964. BIFPLR1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
31965. BIFPLR1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
31966. BIFPLR1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
31967. BIFPLR1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
31968. BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
31969. BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
31970. BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
31971. BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
31972. BIFPLR1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
31973. BIFPLR1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
31974. BIFPLR1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK
31975. BIFPLR1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
31976. BIFPLR1_0_PCIE_MC_CNTL__MC_ENABLE_MASK
31977. BIFPLR1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT
31978. BIFPLR1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
31979. BIFPLR1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
31980. BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
31981. BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
31982. BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
31983. BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
31984. BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
31985. BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
31986. BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
31987. BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
31988. BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
31989. BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
31990. BIFPLR1_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
31991. BIFPLR1_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
31992. BIFPLR1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
31993. BIFPLR1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
31994. BIFPLR1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
31995. BIFPLR1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
31996. BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
31997. BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
31998. BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
31999. BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
32000. BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
32001. BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
32002. BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
32003. BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
32004. BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
32005. BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
32006. BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
32007. BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
32008. BIFPLR1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
32009. BIFPLR1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
32010. BIFPLR1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
32011. BIFPLR1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
32012. BIFPLR1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
32013. BIFPLR1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
32014. BIFPLR1_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
32015. BIFPLR1_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
32016. BIFPLR1_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
32017. BIFPLR1_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
32018. BIFPLR1_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
32019. BIFPLR1_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
32020. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
32021. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
32022. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
32023. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
32024. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
32025. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
32026. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
32027. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
32028. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
32029. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
32030. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
32031. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
32032. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
32033. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
32034. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
32035. BIFPLR1_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
32036. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
32037. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
32038. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
32039. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
32040. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
32041. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
32042. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
32043. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
32044. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
32045. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
32046. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
32047. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
32048. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
32049. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
32050. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
32051. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
32052. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
32053. BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
32054. BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
32055. BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
32056. BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
32057. BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
32058. BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
32059. BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
32060. BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
32061. BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
32062. BIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
32063. BIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
32064. BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
32065. BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
32066. BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK
32067. BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
32068. BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
32069. BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
32070. BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
32071. BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
32072. BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CTO_MASK
32073. BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
32074. BIFPLR1_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
32075. BIFPLR1_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
32076. BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
32077. BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
32078. BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK
32079. BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
32080. BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
32081. BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
32082. BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
32083. BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
32084. BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
32085. BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
32086. BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
32087. BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
32088. BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
32089. BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
32090. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
32091. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
32092. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
32093. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
32094. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
32095. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
32096. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
32097. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
32098. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
32099. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
32100. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
32101. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
32102. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
32103. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
32104. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
32105. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
32106. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
32107. BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
32108. BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
32109. BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
32110. BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
32111. BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
32112. BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
32113. BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
32114. BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
32115. BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
32116. BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK
32117. BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
32118. BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
32119. BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
32120. BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
32121. BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
32122. BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
32123. BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
32124. BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
32125. BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
32126. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
32127. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
32128. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
32129. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
32130. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
32131. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
32132. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
32133. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
32134. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
32135. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
32136. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
32137. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
32138. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
32139. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
32140. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
32141. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
32142. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
32143. BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
32144. BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
32145. BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
32146. BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
32147. BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
32148. BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
32149. BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
32150. BIFPLR1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
32151. BIFPLR1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
32152. BIFPLR1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
32153. BIFPLR1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
32154. BIFPLR1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
32155. BIFPLR1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
32156. BIFPLR1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
32157. BIFPLR1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
32158. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
32159. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
32160. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
32161. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
32162. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
32163. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
32164. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
32165. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
32166. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
32167. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
32168. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
32169. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
32170. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
32171. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
32172. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
32173. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
32174. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
32175. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
32176. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
32177. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
32178. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
32179. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
32180. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
32181. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
32182. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
32183. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
32184. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
32185. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
32186. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
32187. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
32188. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
32189. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
32190. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
32191. BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
32192. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
32193. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
32194. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
32195. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
32196. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
32197. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
32198. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
32199. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
32200. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
32201. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
32202. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
32203. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
32204. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
32205. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
32206. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
32207. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
32208. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
32209. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
32210. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
32211. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
32212. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
32213. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
32214. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
32215. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
32216. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
32217. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
32218. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
32219. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
32220. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
32221. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
32222. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
32223. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
32224. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
32225. BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
32226. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
32227. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
32228. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
32229. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
32230. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
32231. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
32232. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
32233. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
32234. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
32235. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
32236. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
32237. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
32238. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
32239. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
32240. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
32241. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
32242. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
32243. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
32244. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
32245. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
32246. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
32247. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
32248. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
32249. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
32250. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
32251. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
32252. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
32253. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
32254. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
32255. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
32256. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
32257. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
32258. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
32259. BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
32260. BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
32261. BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
32262. BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
32263. BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
32264. BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
32265. BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
32266. BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
32267. BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
32268. BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
32269. BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
32270. BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
32271. BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
32272. BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
32273. BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
32274. BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
32275. BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
32276. BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
32277. BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
32278. BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
32279. BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
32280. BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
32281. BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
32282. BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
32283. BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
32284. BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
32285. BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
32286. BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
32287. BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
32288. BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
32289. BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
32290. BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
32291. BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
32292. BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
32293. BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
32294. BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
32295. BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
32296. BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
32297. BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
32298. BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
32299. BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
32300. BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
32301. BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
32302. BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
32303. BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
32304. BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
32305. BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
32306. BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
32307. BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
32308. BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
32309. BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
32310. BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
32311. BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
32312. BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
32313. BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
32314. BIFPLR1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
32315. BIFPLR1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
32316. BIFPLR1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
32317. BIFPLR1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
32318. BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
32319. BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
32320. BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
32321. BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
32322. BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
32323. BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
32324. BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
32325. BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
32326. BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
32327. BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
32328. BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
32329. BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
32330. BIFPLR1_0_PMI_CAP_LIST__CAP_ID_MASK
32331. BIFPLR1_0_PMI_CAP_LIST__CAP_ID__SHIFT
32332. BIFPLR1_0_PMI_CAP_LIST__NEXT_PTR_MASK
32333. BIFPLR1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
32334. BIFPLR1_0_PMI_CAP__AUX_CURRENT_MASK
32335. BIFPLR1_0_PMI_CAP__AUX_CURRENT__SHIFT
32336. BIFPLR1_0_PMI_CAP__D1_SUPPORT_MASK
32337. BIFPLR1_0_PMI_CAP__D1_SUPPORT__SHIFT
32338. BIFPLR1_0_PMI_CAP__D2_SUPPORT_MASK
32339. BIFPLR1_0_PMI_CAP__D2_SUPPORT__SHIFT
32340. BIFPLR1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
32341. BIFPLR1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
32342. BIFPLR1_0_PMI_CAP__PME_CLOCK_MASK
32343. BIFPLR1_0_PMI_CAP__PME_CLOCK__SHIFT
32344. BIFPLR1_0_PMI_CAP__PME_SUPPORT_MASK
32345. BIFPLR1_0_PMI_CAP__PME_SUPPORT__SHIFT
32346. BIFPLR1_0_PMI_CAP__VERSION_MASK
32347. BIFPLR1_0_PMI_CAP__VERSION__SHIFT
32348. BIFPLR1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
32349. BIFPLR1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
32350. BIFPLR1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
32351. BIFPLR1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
32352. BIFPLR1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
32353. BIFPLR1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
32354. BIFPLR1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
32355. BIFPLR1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
32356. BIFPLR1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
32357. BIFPLR1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
32358. BIFPLR1_0_PMI_STATUS_CNTL__PME_EN_MASK
32359. BIFPLR1_0_PMI_STATUS_CNTL__PME_EN__SHIFT
32360. BIFPLR1_0_PMI_STATUS_CNTL__PME_STATUS_MASK
32361. BIFPLR1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
32362. BIFPLR1_0_PMI_STATUS_CNTL__PMI_DATA_MASK
32363. BIFPLR1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
32364. BIFPLR1_0_PMI_STATUS_CNTL__POWER_STATE_MASK
32365. BIFPLR1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
32366. BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
32367. BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
32368. BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
32369. BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
32370. BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
32371. BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
32372. BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
32373. BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
32374. BIFPLR1_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
32375. BIFPLR1_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
32376. BIFPLR1_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
32377. BIFPLR1_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
32378. BIFPLR1_0_PROG_INTERFACE__PROG_INTERFACE_MASK
32379. BIFPLR1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
32380. BIFPLR1_0_REVISION_ID__MAJOR_REV_ID_MASK
32381. BIFPLR1_0_REVISION_ID__MAJOR_REV_ID__SHIFT
32382. BIFPLR1_0_REVISION_ID__MINOR_REV_ID_MASK
32383. BIFPLR1_0_REVISION_ID__MINOR_REV_ID__SHIFT
32384. BIFPLR1_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
32385. BIFPLR1_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
32386. BIFPLR1_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
32387. BIFPLR1_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
32388. BIFPLR1_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK
32389. BIFPLR1_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
32390. BIFPLR1_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
32391. BIFPLR1_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
32392. BIFPLR1_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
32393. BIFPLR1_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
32394. BIFPLR1_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
32395. BIFPLR1_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
32396. BIFPLR1_0_ROOT_STATUS__PME_PENDING_MASK
32397. BIFPLR1_0_ROOT_STATUS__PME_PENDING__SHIFT
32398. BIFPLR1_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK
32399. BIFPLR1_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
32400. BIFPLR1_0_ROOT_STATUS__PME_STATUS_MASK
32401. BIFPLR1_0_ROOT_STATUS__PME_STATUS__SHIFT
32402. BIFPLR1_0_SECONDARY_STATUS__CAP_LIST_MASK
32403. BIFPLR1_0_SECONDARY_STATUS__CAP_LIST__SHIFT
32404. BIFPLR1_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK
32405. BIFPLR1_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
32406. BIFPLR1_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
32407. BIFPLR1_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
32408. BIFPLR1_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
32409. BIFPLR1_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
32410. BIFPLR1_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
32411. BIFPLR1_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
32412. BIFPLR1_0_SECONDARY_STATUS__PCI_66_EN_MASK
32413. BIFPLR1_0_SECONDARY_STATUS__PCI_66_EN__SHIFT
32414. BIFPLR1_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
32415. BIFPLR1_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
32416. BIFPLR1_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
32417. BIFPLR1_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
32418. BIFPLR1_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
32419. BIFPLR1_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
32420. BIFPLR1_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
32421. BIFPLR1_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
32422. BIFPLR1_0_SLOT_CAP2__RESERVED_MASK
32423. BIFPLR1_0_SLOT_CAP2__RESERVED__SHIFT
32424. BIFPLR1_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
32425. BIFPLR1_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
32426. BIFPLR1_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
32427. BIFPLR1_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
32428. BIFPLR1_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
32429. BIFPLR1_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
32430. BIFPLR1_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK
32431. BIFPLR1_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
32432. BIFPLR1_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK
32433. BIFPLR1_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
32434. BIFPLR1_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
32435. BIFPLR1_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
32436. BIFPLR1_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
32437. BIFPLR1_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
32438. BIFPLR1_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
32439. BIFPLR1_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
32440. BIFPLR1_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
32441. BIFPLR1_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
32442. BIFPLR1_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
32443. BIFPLR1_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
32444. BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
32445. BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
32446. BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
32447. BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
32448. BIFPLR1_0_SLOT_CNTL2__RESERVED_MASK
32449. BIFPLR1_0_SLOT_CNTL2__RESERVED__SHIFT
32450. BIFPLR1_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
32451. BIFPLR1_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
32452. BIFPLR1_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
32453. BIFPLR1_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
32454. BIFPLR1_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
32455. BIFPLR1_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
32456. BIFPLR1_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
32457. BIFPLR1_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
32458. BIFPLR1_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
32459. BIFPLR1_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
32460. BIFPLR1_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
32461. BIFPLR1_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
32462. BIFPLR1_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
32463. BIFPLR1_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
32464. BIFPLR1_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
32465. BIFPLR1_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
32466. BIFPLR1_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
32467. BIFPLR1_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
32468. BIFPLR1_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
32469. BIFPLR1_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
32470. BIFPLR1_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
32471. BIFPLR1_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
32472. BIFPLR1_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
32473. BIFPLR1_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
32474. BIFPLR1_0_SLOT_STATUS2__RESERVED_MASK
32475. BIFPLR1_0_SLOT_STATUS2__RESERVED__SHIFT
32476. BIFPLR1_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
32477. BIFPLR1_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
32478. BIFPLR1_0_SLOT_STATUS__COMMAND_COMPLETED_MASK
32479. BIFPLR1_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
32480. BIFPLR1_0_SLOT_STATUS__DL_STATE_CHANGED_MASK
32481. BIFPLR1_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
32482. BIFPLR1_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
32483. BIFPLR1_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
32484. BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
32485. BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
32486. BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK
32487. BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
32488. BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
32489. BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
32490. BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
32491. BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
32492. BIFPLR1_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
32493. BIFPLR1_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
32494. BIFPLR1_0_SSID_CAP_LIST__CAP_ID_MASK
32495. BIFPLR1_0_SSID_CAP_LIST__CAP_ID__SHIFT
32496. BIFPLR1_0_SSID_CAP_LIST__NEXT_PTR_MASK
32497. BIFPLR1_0_SSID_CAP_LIST__NEXT_PTR__SHIFT
32498. BIFPLR1_0_SSID_CAP__SUBSYSTEM_ID_MASK
32499. BIFPLR1_0_SSID_CAP__SUBSYSTEM_ID__SHIFT
32500. BIFPLR1_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
32501. BIFPLR1_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
32502. BIFPLR1_0_STATUS__CAP_LIST_MASK
32503. BIFPLR1_0_STATUS__CAP_LIST__SHIFT
32504. BIFPLR1_0_STATUS__DEVSEL_TIMING_MASK
32505. BIFPLR1_0_STATUS__DEVSEL_TIMING__SHIFT
32506. BIFPLR1_0_STATUS__FAST_BACK_CAPABLE_MASK
32507. BIFPLR1_0_STATUS__FAST_BACK_CAPABLE__SHIFT
32508. BIFPLR1_0_STATUS__INT_STATUS_MASK
32509. BIFPLR1_0_STATUS__INT_STATUS__SHIFT
32510. BIFPLR1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
32511. BIFPLR1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
32512. BIFPLR1_0_STATUS__PARITY_ERROR_DETECTED_MASK
32513. BIFPLR1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
32514. BIFPLR1_0_STATUS__PCI_66_EN_MASK
32515. BIFPLR1_0_STATUS__PCI_66_EN__SHIFT
32516. BIFPLR1_0_STATUS__RECEIVED_MASTER_ABORT_MASK
32517. BIFPLR1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
32518. BIFPLR1_0_STATUS__RECEIVED_TARGET_ABORT_MASK
32519. BIFPLR1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
32520. BIFPLR1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
32521. BIFPLR1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
32522. BIFPLR1_0_STATUS__SIGNAL_TARGET_ABORT_MASK
32523. BIFPLR1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
32524. BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
32525. BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
32526. BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
32527. BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
32528. BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
32529. BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
32530. BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
32531. BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
32532. BIFPLR1_0_SUB_CLASS__SUB_CLASS_MASK
32533. BIFPLR1_0_SUB_CLASS__SUB_CLASS__SHIFT
32534. BIFPLR1_0_VENDOR_ID__VENDOR_ID_MASK
32535. BIFPLR1_0_VENDOR_ID__VENDOR_ID__SHIFT
32536. BIFPLR1_1_BASE_CLASS__BASE_CLASS_MASK
32537. BIFPLR1_1_BASE_CLASS__BASE_CLASS__SHIFT
32538. BIFPLR1_1_BIST__BIST_CAP_MASK
32539. BIFPLR1_1_BIST__BIST_CAP__SHIFT
32540. BIFPLR1_1_BIST__BIST_COMP_MASK
32541. BIFPLR1_1_BIST__BIST_COMP__SHIFT
32542. BIFPLR1_1_BIST__BIST_STRT_MASK
32543. BIFPLR1_1_BIST__BIST_STRT__SHIFT
32544. BIFPLR1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
32545. BIFPLR1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
32546. BIFPLR1_1_CAP_PTR__CAP_PTR_MASK
32547. BIFPLR1_1_CAP_PTR__CAP_PTR__SHIFT
32548. BIFPLR1_1_COMMAND__AD_STEPPING_MASK
32549. BIFPLR1_1_COMMAND__AD_STEPPING__SHIFT
32550. BIFPLR1_1_COMMAND__BUS_MASTER_EN_MASK
32551. BIFPLR1_1_COMMAND__BUS_MASTER_EN__SHIFT
32552. BIFPLR1_1_COMMAND__FAST_B2B_EN_MASK
32553. BIFPLR1_1_COMMAND__FAST_B2B_EN__SHIFT
32554. BIFPLR1_1_COMMAND__INT_DIS_MASK
32555. BIFPLR1_1_COMMAND__INT_DIS__SHIFT
32556. BIFPLR1_1_COMMAND__IO_ACCESS_EN_MASK
32557. BIFPLR1_1_COMMAND__IO_ACCESS_EN__SHIFT
32558. BIFPLR1_1_COMMAND__MEM_ACCESS_EN_MASK
32559. BIFPLR1_1_COMMAND__MEM_ACCESS_EN__SHIFT
32560. BIFPLR1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
32561. BIFPLR1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
32562. BIFPLR1_1_COMMAND__PAL_SNOOP_EN_MASK
32563. BIFPLR1_1_COMMAND__PAL_SNOOP_EN__SHIFT
32564. BIFPLR1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
32565. BIFPLR1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
32566. BIFPLR1_1_COMMAND__SERR_EN_MASK
32567. BIFPLR1_1_COMMAND__SERR_EN__SHIFT
32568. BIFPLR1_1_COMMAND__SPECIAL_CYCLE_EN_MASK
32569. BIFPLR1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
32570. BIFPLR1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
32571. BIFPLR1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
32572. BIFPLR1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
32573. BIFPLR1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
32574. BIFPLR1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
32575. BIFPLR1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
32576. BIFPLR1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
32577. BIFPLR1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
32578. BIFPLR1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
32579. BIFPLR1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
32580. BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
32581. BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
32582. BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
32583. BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
32584. BIFPLR1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
32585. BIFPLR1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
32586. BIFPLR1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
32587. BIFPLR1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
32588. BIFPLR1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
32589. BIFPLR1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
32590. BIFPLR1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
32591. BIFPLR1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
32592. BIFPLR1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
32593. BIFPLR1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
32594. BIFPLR1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
32595. BIFPLR1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
32596. BIFPLR1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
32597. BIFPLR1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
32598. BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
32599. BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
32600. BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
32601. BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
32602. BIFPLR1_1_DEVICE_CAP__EXTENDED_TAG_MASK
32603. BIFPLR1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
32604. BIFPLR1_1_DEVICE_CAP__FLR_CAPABLE_MASK
32605. BIFPLR1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
32606. BIFPLR1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
32607. BIFPLR1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
32608. BIFPLR1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
32609. BIFPLR1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
32610. BIFPLR1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
32611. BIFPLR1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
32612. BIFPLR1_1_DEVICE_CAP__PHANTOM_FUNC_MASK
32613. BIFPLR1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
32614. BIFPLR1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
32615. BIFPLR1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
32616. BIFPLR1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
32617. BIFPLR1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
32618. BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
32619. BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
32620. BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
32621. BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
32622. BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
32623. BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
32624. BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
32625. BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
32626. BIFPLR1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
32627. BIFPLR1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
32628. BIFPLR1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
32629. BIFPLR1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
32630. BIFPLR1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
32631. BIFPLR1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
32632. BIFPLR1_1_DEVICE_CNTL2__LTR_EN_MASK
32633. BIFPLR1_1_DEVICE_CNTL2__LTR_EN__SHIFT
32634. BIFPLR1_1_DEVICE_CNTL2__OBFF_EN_MASK
32635. BIFPLR1_1_DEVICE_CNTL2__OBFF_EN__SHIFT
32636. BIFPLR1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
32637. BIFPLR1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
32638. BIFPLR1_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
32639. BIFPLR1_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
32640. BIFPLR1_1_DEVICE_CNTL__CORR_ERR_EN_MASK
32641. BIFPLR1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
32642. BIFPLR1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
32643. BIFPLR1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
32644. BIFPLR1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
32645. BIFPLR1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
32646. BIFPLR1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
32647. BIFPLR1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
32648. BIFPLR1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
32649. BIFPLR1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
32650. BIFPLR1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
32651. BIFPLR1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
32652. BIFPLR1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
32653. BIFPLR1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
32654. BIFPLR1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
32655. BIFPLR1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
32656. BIFPLR1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
32657. BIFPLR1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
32658. BIFPLR1_1_DEVICE_CNTL__USR_REPORT_EN_MASK
32659. BIFPLR1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
32660. BIFPLR1_1_DEVICE_ID__DEVICE_ID_MASK
32661. BIFPLR1_1_DEVICE_ID__DEVICE_ID__SHIFT
32662. BIFPLR1_1_DEVICE_STATUS2__RESERVED_MASK
32663. BIFPLR1_1_DEVICE_STATUS2__RESERVED__SHIFT
32664. BIFPLR1_1_DEVICE_STATUS__AUX_PWR_MASK
32665. BIFPLR1_1_DEVICE_STATUS__AUX_PWR__SHIFT
32666. BIFPLR1_1_DEVICE_STATUS__CORR_ERR_MASK
32667. BIFPLR1_1_DEVICE_STATUS__CORR_ERR__SHIFT
32668. BIFPLR1_1_DEVICE_STATUS__FATAL_ERR_MASK
32669. BIFPLR1_1_DEVICE_STATUS__FATAL_ERR__SHIFT
32670. BIFPLR1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
32671. BIFPLR1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
32672. BIFPLR1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
32673. BIFPLR1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
32674. BIFPLR1_1_DEVICE_STATUS__USR_DETECTED_MASK
32675. BIFPLR1_1_DEVICE_STATUS__USR_DETECTED__SHIFT
32676. BIFPLR1_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
32677. BIFPLR1_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
32678. BIFPLR1_1_HEADER__DEVICE_TYPE_MASK
32679. BIFPLR1_1_HEADER__DEVICE_TYPE__SHIFT
32680. BIFPLR1_1_HEADER__HEADER_TYPE_MASK
32681. BIFPLR1_1_HEADER__HEADER_TYPE__SHIFT
32682. BIFPLR1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
32683. BIFPLR1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
32684. BIFPLR1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
32685. BIFPLR1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
32686. BIFPLR1_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
32687. BIFPLR1_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
32688. BIFPLR1_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
32689. BIFPLR1_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
32690. BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_MASK
32691. BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
32692. BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
32693. BIFPLR1_1_IO_BASE_LIMIT__IO_BASE__SHIFT
32694. BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_MASK
32695. BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
32696. BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
32697. BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT
32698. BIFPLR1_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
32699. BIFPLR1_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
32700. BIFPLR1_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK
32701. BIFPLR1_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
32702. BIFPLR1_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
32703. BIFPLR1_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
32704. BIFPLR1_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
32705. BIFPLR1_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
32706. BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
32707. BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
32708. BIFPLR1_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK
32709. BIFPLR1_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
32710. BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
32711. BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
32712. BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK
32713. BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
32714. BIFPLR1_1_LATENCY__LATENCY_TIMER_MASK
32715. BIFPLR1_1_LATENCY__LATENCY_TIMER__SHIFT
32716. BIFPLR1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
32717. BIFPLR1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
32718. BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
32719. BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
32720. BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
32721. BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
32722. BIFPLR1_1_LINK_CAP2__RESERVED_MASK
32723. BIFPLR1_1_LINK_CAP2__RESERVED__SHIFT
32724. BIFPLR1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
32725. BIFPLR1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
32726. BIFPLR1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
32727. BIFPLR1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
32728. BIFPLR1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
32729. BIFPLR1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
32730. BIFPLR1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
32731. BIFPLR1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
32732. BIFPLR1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
32733. BIFPLR1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
32734. BIFPLR1_1_LINK_CAP__L1_EXIT_LATENCY_MASK
32735. BIFPLR1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
32736. BIFPLR1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
32737. BIFPLR1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
32738. BIFPLR1_1_LINK_CAP__LINK_SPEED_MASK
32739. BIFPLR1_1_LINK_CAP__LINK_SPEED__SHIFT
32740. BIFPLR1_1_LINK_CAP__LINK_WIDTH_MASK
32741. BIFPLR1_1_LINK_CAP__LINK_WIDTH__SHIFT
32742. BIFPLR1_1_LINK_CAP__PM_SUPPORT_MASK
32743. BIFPLR1_1_LINK_CAP__PM_SUPPORT__SHIFT
32744. BIFPLR1_1_LINK_CAP__PORT_NUMBER_MASK
32745. BIFPLR1_1_LINK_CAP__PORT_NUMBER__SHIFT
32746. BIFPLR1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
32747. BIFPLR1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
32748. BIFPLR1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
32749. BIFPLR1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
32750. BIFPLR1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
32751. BIFPLR1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
32752. BIFPLR1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
32753. BIFPLR1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
32754. BIFPLR1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
32755. BIFPLR1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
32756. BIFPLR1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
32757. BIFPLR1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
32758. BIFPLR1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
32759. BIFPLR1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
32760. BIFPLR1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
32761. BIFPLR1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
32762. BIFPLR1_1_LINK_CNTL2__XMIT_MARGIN_MASK
32763. BIFPLR1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
32764. BIFPLR1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
32765. BIFPLR1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
32766. BIFPLR1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
32767. BIFPLR1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
32768. BIFPLR1_1_LINK_CNTL__EXTENDED_SYNC_MASK
32769. BIFPLR1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
32770. BIFPLR1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
32771. BIFPLR1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
32772. BIFPLR1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
32773. BIFPLR1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
32774. BIFPLR1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
32775. BIFPLR1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
32776. BIFPLR1_1_LINK_CNTL__LINK_DIS_MASK
32777. BIFPLR1_1_LINK_CNTL__LINK_DIS__SHIFT
32778. BIFPLR1_1_LINK_CNTL__PM_CONTROL_MASK
32779. BIFPLR1_1_LINK_CNTL__PM_CONTROL__SHIFT
32780. BIFPLR1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
32781. BIFPLR1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
32782. BIFPLR1_1_LINK_CNTL__RETRAIN_LINK_MASK
32783. BIFPLR1_1_LINK_CNTL__RETRAIN_LINK__SHIFT
32784. BIFPLR1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
32785. BIFPLR1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
32786. BIFPLR1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
32787. BIFPLR1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
32788. BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
32789. BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
32790. BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
32791. BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
32792. BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
32793. BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
32794. BIFPLR1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
32795. BIFPLR1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
32796. BIFPLR1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
32797. BIFPLR1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
32798. BIFPLR1_1_LINK_STATUS__DL_ACTIVE_MASK
32799. BIFPLR1_1_LINK_STATUS__DL_ACTIVE__SHIFT
32800. BIFPLR1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
32801. BIFPLR1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
32802. BIFPLR1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
32803. BIFPLR1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
32804. BIFPLR1_1_LINK_STATUS__LINK_TRAINING_MASK
32805. BIFPLR1_1_LINK_STATUS__LINK_TRAINING__SHIFT
32806. BIFPLR1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
32807. BIFPLR1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
32808. BIFPLR1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
32809. BIFPLR1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
32810. BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
32811. BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
32812. BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
32813. BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
32814. BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
32815. BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
32816. BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
32817. BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
32818. BIFPLR1_1_MSI_CAP_LIST__CAP_ID_MASK
32819. BIFPLR1_1_MSI_CAP_LIST__CAP_ID__SHIFT
32820. BIFPLR1_1_MSI_CAP_LIST__NEXT_PTR_MASK
32821. BIFPLR1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
32822. BIFPLR1_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
32823. BIFPLR1_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
32824. BIFPLR1_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
32825. BIFPLR1_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
32826. BIFPLR1_1_MSI_MAP_CAP_LIST__CAP_ID_MASK
32827. BIFPLR1_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
32828. BIFPLR1_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
32829. BIFPLR1_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
32830. BIFPLR1_1_MSI_MAP_CAP__CAP_TYPE_MASK
32831. BIFPLR1_1_MSI_MAP_CAP__CAP_TYPE__SHIFT
32832. BIFPLR1_1_MSI_MAP_CAP__EN_MASK
32833. BIFPLR1_1_MSI_MAP_CAP__EN__SHIFT
32834. BIFPLR1_1_MSI_MAP_CAP__FIXD_MASK
32835. BIFPLR1_1_MSI_MAP_CAP__FIXD__SHIFT
32836. BIFPLR1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
32837. BIFPLR1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
32838. BIFPLR1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
32839. BIFPLR1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
32840. BIFPLR1_1_MSI_MSG_CNTL__MSI_64BIT_MASK
32841. BIFPLR1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
32842. BIFPLR1_1_MSI_MSG_CNTL__MSI_EN_MASK
32843. BIFPLR1_1_MSI_MSG_CNTL__MSI_EN__SHIFT
32844. BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
32845. BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
32846. BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
32847. BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
32848. BIFPLR1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
32849. BIFPLR1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
32850. BIFPLR1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
32851. BIFPLR1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
32852. BIFPLR1_1_MSI_MSG_DATA__MSI_DATA_MASK
32853. BIFPLR1_1_MSI_MSG_DATA__MSI_DATA__SHIFT
32854. BIFPLR1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
32855. BIFPLR1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
32856. BIFPLR1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
32857. BIFPLR1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
32858. BIFPLR1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
32859. BIFPLR1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
32860. BIFPLR1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
32861. BIFPLR1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
32862. BIFPLR1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
32863. BIFPLR1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
32864. BIFPLR1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
32865. BIFPLR1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
32866. BIFPLR1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
32867. BIFPLR1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
32868. BIFPLR1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
32869. BIFPLR1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
32870. BIFPLR1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
32871. BIFPLR1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
32872. BIFPLR1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
32873. BIFPLR1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
32874. BIFPLR1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
32875. BIFPLR1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
32876. BIFPLR1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
32877. BIFPLR1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
32878. BIFPLR1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
32879. BIFPLR1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
32880. BIFPLR1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
32881. BIFPLR1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
32882. BIFPLR1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
32883. BIFPLR1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
32884. BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
32885. BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
32886. BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
32887. BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
32888. BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
32889. BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
32890. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
32891. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
32892. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
32893. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
32894. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
32895. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
32896. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
32897. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
32898. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
32899. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
32900. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
32901. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
32902. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
32903. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
32904. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
32905. BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
32906. BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
32907. BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
32908. BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
32909. BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
32910. BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
32911. BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
32912. BIFPLR1_1_PCIE_CAP_LIST__CAP_ID_MASK
32913. BIFPLR1_1_PCIE_CAP_LIST__CAP_ID__SHIFT
32914. BIFPLR1_1_PCIE_CAP_LIST__NEXT_PTR_MASK
32915. BIFPLR1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
32916. BIFPLR1_1_PCIE_CAP__DEVICE_TYPE_MASK
32917. BIFPLR1_1_PCIE_CAP__DEVICE_TYPE__SHIFT
32918. BIFPLR1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
32919. BIFPLR1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
32920. BIFPLR1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
32921. BIFPLR1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
32922. BIFPLR1_1_PCIE_CAP__VERSION_MASK
32923. BIFPLR1_1_PCIE_CAP__VERSION__SHIFT
32924. BIFPLR1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
32925. BIFPLR1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
32926. BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
32927. BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
32928. BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
32929. BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
32930. BIFPLR1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
32931. BIFPLR1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
32932. BIFPLR1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
32933. BIFPLR1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
32934. BIFPLR1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
32935. BIFPLR1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
32936. BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
32937. BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
32938. BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
32939. BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
32940. BIFPLR1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
32941. BIFPLR1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
32942. BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
32943. BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
32944. BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
32945. BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
32946. BIFPLR1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
32947. BIFPLR1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
32948. BIFPLR1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
32949. BIFPLR1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
32950. BIFPLR1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
32951. BIFPLR1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
32952. BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
32953. BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
32954. BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
32955. BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
32956. BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
32957. BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
32958. BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
32959. BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
32960. BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
32961. BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
32962. BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
32963. BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
32964. BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
32965. BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
32966. BIFPLR1_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
32967. BIFPLR1_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
32968. BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
32969. BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
32970. BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
32971. BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
32972. BIFPLR1_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
32973. BIFPLR1_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
32974. BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
32975. BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
32976. BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
32977. BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
32978. BIFPLR1_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
32979. BIFPLR1_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
32980. BIFPLR1_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
32981. BIFPLR1_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
32982. BIFPLR1_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
32983. BIFPLR1_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
32984. BIFPLR1_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
32985. BIFPLR1_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
32986. BIFPLR1_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
32987. BIFPLR1_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
32988. BIFPLR1_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
32989. BIFPLR1_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
32990. BIFPLR1_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
32991. BIFPLR1_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
32992. BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
32993. BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
32994. BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
32995. BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
32996. BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
32997. BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
32998. BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
32999. BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
33000. BIFPLR1_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
33001. BIFPLR1_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
33002. BIFPLR1_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
33003. BIFPLR1_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
33004. BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
33005. BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
33006. BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
33007. BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
33008. BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
33009. BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
33010. BIFPLR1_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
33011. BIFPLR1_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
33012. BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
33013. BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
33014. BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
33015. BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
33016. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK
33017. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
33018. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK
33019. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
33020. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK
33021. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
33022. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK
33023. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
33024. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK
33025. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
33026. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK
33027. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
33028. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK
33029. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
33030. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK
33031. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
33032. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK
33033. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
33034. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK
33035. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
33036. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK
33037. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
33038. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK
33039. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
33040. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK
33041. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
33042. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK
33043. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
33044. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK
33045. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
33046. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK
33047. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
33048. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK
33049. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
33050. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK
33051. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
33052. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK
33053. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
33054. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK
33055. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
33056. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK
33057. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
33058. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK
33059. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
33060. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK
33061. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
33062. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK
33063. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
33064. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK
33065. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
33066. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK
33067. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
33068. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK
33069. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
33070. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK
33071. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
33072. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK
33073. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
33074. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK
33075. BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
33076. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK
33077. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
33078. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK
33079. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
33080. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK
33081. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
33082. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK
33083. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
33084. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK
33085. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
33086. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK
33087. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
33088. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK
33089. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
33090. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK
33091. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
33092. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK
33093. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
33094. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK
33095. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
33096. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK
33097. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
33098. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK
33099. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
33100. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK
33101. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
33102. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK
33103. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
33104. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK
33105. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
33106. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK
33107. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
33108. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK
33109. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
33110. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK
33111. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
33112. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK
33113. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
33114. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK
33115. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
33116. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK
33117. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
33118. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK
33119. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
33120. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK
33121. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
33122. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK
33123. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
33124. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK
33125. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
33126. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK
33127. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
33128. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK
33129. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
33130. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK
33131. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
33132. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK
33133. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
33134. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK
33135. BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
33136. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK
33137. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
33138. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK
33139. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
33140. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK
33141. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
33142. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK
33143. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
33144. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK
33145. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
33146. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK
33147. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
33148. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK
33149. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
33150. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK
33151. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
33152. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK
33153. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
33154. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK
33155. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
33156. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK
33157. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
33158. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK
33159. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
33160. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK
33161. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
33162. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK
33163. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
33164. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK
33165. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
33166. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK
33167. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
33168. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK
33169. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
33170. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK
33171. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
33172. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK
33173. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
33174. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK
33175. BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
33176. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK
33177. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
33178. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK
33179. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
33180. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK
33181. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
33182. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK
33183. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
33184. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK
33185. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
33186. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK
33187. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
33188. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK
33189. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
33190. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK
33191. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
33192. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK
33193. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
33194. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK
33195. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
33196. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK
33197. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
33198. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK
33199. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
33200. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK
33201. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
33202. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK
33203. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
33204. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK
33205. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
33206. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK
33207. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
33208. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK
33209. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
33210. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK
33211. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
33212. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK
33213. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
33214. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK
33215. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
33216. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK
33217. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
33218. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK
33219. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
33220. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK
33221. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
33222. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK
33223. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
33224. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK
33225. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
33226. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK
33227. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
33228. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK
33229. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
33230. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK
33231. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
33232. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK
33233. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
33234. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK
33235. BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
33236. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK
33237. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
33238. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK
33239. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
33240. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK
33241. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
33242. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK
33243. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
33244. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK
33245. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
33246. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK
33247. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
33248. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK
33249. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
33250. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK
33251. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
33252. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK
33253. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
33254. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK
33255. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
33256. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK
33257. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
33258. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK
33259. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
33260. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK
33261. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
33262. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK
33263. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
33264. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK
33265. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
33266. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK
33267. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
33268. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK
33269. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
33270. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK
33271. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
33272. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK
33273. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
33274. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK
33275. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
33276. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK
33277. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
33278. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK
33279. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
33280. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK
33281. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
33282. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK
33283. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
33284. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK
33285. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
33286. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK
33287. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
33288. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK
33289. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
33290. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK
33291. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
33292. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK
33293. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
33294. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK
33295. BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
33296. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK
33297. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
33298. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK
33299. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
33300. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK
33301. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
33302. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK
33303. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
33304. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK
33305. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
33306. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK
33307. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
33308. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK
33309. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
33310. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK
33311. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
33312. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK
33313. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
33314. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK
33315. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
33316. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK
33317. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
33318. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK
33319. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
33320. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK
33321. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
33322. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK
33323. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
33324. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK
33325. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
33326. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK
33327. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
33328. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK
33329. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
33330. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK
33331. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
33332. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK
33333. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
33334. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK
33335. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
33336. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK
33337. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
33338. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK
33339. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
33340. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK
33341. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
33342. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK
33343. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
33344. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK
33345. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
33346. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK
33347. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
33348. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK
33349. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
33350. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK
33351. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
33352. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK
33353. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
33354. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK
33355. BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
33356. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK
33357. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
33358. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK
33359. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
33360. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK
33361. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
33362. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK
33363. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
33364. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK
33365. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
33366. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK
33367. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
33368. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK
33369. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
33370. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK
33371. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
33372. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK
33373. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
33374. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK
33375. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
33376. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK
33377. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
33378. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK
33379. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
33380. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK
33381. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
33382. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK
33383. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
33384. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK
33385. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
33386. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK
33387. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
33388. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK
33389. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
33390. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK
33391. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
33392. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK
33393. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
33394. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK
33395. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
33396. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK
33397. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
33398. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK
33399. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
33400. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK
33401. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
33402. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK
33403. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
33404. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK
33405. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
33406. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK
33407. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
33408. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK
33409. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
33410. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK
33411. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
33412. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK
33413. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
33414. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK
33415. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
33416. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK
33417. BIFPLR1_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
33418. BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK
33419. BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
33420. BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK
33421. BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
33422. BIFPLR1_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
33423. BIFPLR1_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
33424. BIFPLR1_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK
33425. BIFPLR1_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
33426. BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
33427. BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
33428. BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
33429. BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
33430. BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
33431. BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
33432. BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
33433. BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
33434. BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
33435. BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
33436. BIFPLR1_1_PCIE_ESM_HEADER_2__CAP_ID_MASK
33437. BIFPLR1_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
33438. BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
33439. BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
33440. BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
33441. BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
33442. BIFPLR1_1_PCIE_HDR_LOG0__TLP_HDR_MASK
33443. BIFPLR1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
33444. BIFPLR1_1_PCIE_HDR_LOG1__TLP_HDR_MASK
33445. BIFPLR1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
33446. BIFPLR1_1_PCIE_HDR_LOG2__TLP_HDR_MASK
33447. BIFPLR1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
33448. BIFPLR1_1_PCIE_HDR_LOG3__TLP_HDR_MASK
33449. BIFPLR1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
33450. BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
33451. BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
33452. BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
33453. BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
33454. BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
33455. BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
33456. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
33457. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
33458. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
33459. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
33460. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
33461. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
33462. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
33463. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
33464. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
33465. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
33466. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
33467. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
33468. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
33469. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
33470. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
33471. BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
33472. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
33473. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
33474. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
33475. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
33476. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
33477. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
33478. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
33479. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
33480. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
33481. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
33482. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
33483. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
33484. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
33485. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
33486. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
33487. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
33488. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
33489. BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
33490. BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33491. BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33492. BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33493. BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33494. BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33495. BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33496. BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33497. BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33498. BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33499. BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33500. BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33501. BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33502. BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33503. BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33504. BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33505. BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33506. BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33507. BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33508. BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33509. BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33510. BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33511. BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33512. BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33513. BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33514. BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33515. BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33516. BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33517. BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33518. BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33519. BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33520. BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33521. BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33522. BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33523. BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33524. BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33525. BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33526. BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33527. BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33528. BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33529. BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33530. BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33531. BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33532. BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33533. BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33534. BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33535. BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33536. BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33537. BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33538. BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33539. BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33540. BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33541. BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33542. BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33543. BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33544. BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33545. BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33546. BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33547. BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33548. BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33549. BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33550. BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33551. BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33552. BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33553. BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33554. BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33555. BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33556. BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33557. BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33558. BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33559. BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33560. BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33561. BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33562. BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33563. BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33564. BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33565. BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33566. BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33567. BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33568. BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33569. BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33570. BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33571. BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33572. BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33573. BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33574. BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33575. BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33576. BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33577. BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33578. BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33579. BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33580. BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33581. BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33582. BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33583. BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33584. BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33585. BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33586. BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33587. BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33588. BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33589. BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33590. BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33591. BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33592. BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33593. BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33594. BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33595. BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33596. BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33597. BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33598. BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33599. BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33600. BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33601. BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33602. BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33603. BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33604. BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33605. BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33606. BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33607. BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33608. BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33609. BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33610. BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
33611. BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
33612. BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
33613. BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
33614. BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
33615. BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
33616. BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
33617. BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
33618. BIFPLR1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
33619. BIFPLR1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
33620. BIFPLR1_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
33621. BIFPLR1_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
33622. BIFPLR1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
33623. BIFPLR1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
33624. BIFPLR1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
33625. BIFPLR1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
33626. BIFPLR1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
33627. BIFPLR1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
33628. BIFPLR1_1_PCIE_LINK_CNTL3__RESERVED_MASK
33629. BIFPLR1_1_PCIE_LINK_CNTL3__RESERVED__SHIFT
33630. BIFPLR1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
33631. BIFPLR1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
33632. BIFPLR1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
33633. BIFPLR1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
33634. BIFPLR1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
33635. BIFPLR1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
33636. BIFPLR1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
33637. BIFPLR1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
33638. BIFPLR1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
33639. BIFPLR1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
33640. BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
33641. BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
33642. BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
33643. BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
33644. BIFPLR1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
33645. BIFPLR1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
33646. BIFPLR1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK
33647. BIFPLR1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
33648. BIFPLR1_1_PCIE_MC_CNTL__MC_ENABLE_MASK
33649. BIFPLR1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT
33650. BIFPLR1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
33651. BIFPLR1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
33652. BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
33653. BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
33654. BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
33655. BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
33656. BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
33657. BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
33658. BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
33659. BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
33660. BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
33661. BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
33662. BIFPLR1_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
33663. BIFPLR1_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
33664. BIFPLR1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
33665. BIFPLR1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
33666. BIFPLR1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
33667. BIFPLR1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
33668. BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
33669. BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
33670. BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
33671. BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
33672. BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
33673. BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
33674. BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
33675. BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
33676. BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
33677. BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
33678. BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
33679. BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
33680. BIFPLR1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
33681. BIFPLR1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
33682. BIFPLR1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
33683. BIFPLR1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
33684. BIFPLR1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
33685. BIFPLR1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
33686. BIFPLR1_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
33687. BIFPLR1_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
33688. BIFPLR1_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
33689. BIFPLR1_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
33690. BIFPLR1_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
33691. BIFPLR1_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
33692. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
33693. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
33694. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
33695. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
33696. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
33697. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
33698. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
33699. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
33700. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
33701. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
33702. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
33703. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
33704. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
33705. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
33706. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
33707. BIFPLR1_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
33708. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
33709. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
33710. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
33711. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
33712. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
33713. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
33714. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
33715. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
33716. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
33717. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
33718. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
33719. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
33720. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
33721. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
33722. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
33723. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
33724. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
33725. BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
33726. BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
33727. BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
33728. BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
33729. BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
33730. BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
33731. BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
33732. BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
33733. BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
33734. BIFPLR1_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
33735. BIFPLR1_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
33736. BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
33737. BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
33738. BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK
33739. BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
33740. BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
33741. BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
33742. BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
33743. BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
33744. BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CTO_MASK
33745. BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
33746. BIFPLR1_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
33747. BIFPLR1_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
33748. BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
33749. BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
33750. BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK
33751. BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
33752. BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
33753. BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
33754. BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
33755. BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
33756. BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
33757. BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
33758. BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
33759. BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
33760. BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
33761. BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
33762. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
33763. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
33764. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
33765. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
33766. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
33767. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
33768. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
33769. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
33770. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
33771. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
33772. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
33773. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
33774. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
33775. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
33776. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
33777. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
33778. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
33779. BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
33780. BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
33781. BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
33782. BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
33783. BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
33784. BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
33785. BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
33786. BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
33787. BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
33788. BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK
33789. BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
33790. BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
33791. BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
33792. BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
33793. BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
33794. BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
33795. BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
33796. BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
33797. BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
33798. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
33799. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
33800. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
33801. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
33802. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
33803. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
33804. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
33805. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
33806. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
33807. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
33808. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
33809. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
33810. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
33811. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
33812. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
33813. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
33814. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
33815. BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
33816. BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
33817. BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
33818. BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
33819. BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
33820. BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
33821. BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
33822. BIFPLR1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
33823. BIFPLR1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
33824. BIFPLR1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
33825. BIFPLR1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
33826. BIFPLR1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
33827. BIFPLR1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
33828. BIFPLR1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
33829. BIFPLR1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
33830. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
33831. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
33832. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
33833. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
33834. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
33835. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
33836. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
33837. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
33838. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
33839. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
33840. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
33841. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
33842. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
33843. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
33844. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
33845. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
33846. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
33847. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
33848. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
33849. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
33850. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
33851. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
33852. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
33853. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
33854. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
33855. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
33856. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
33857. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
33858. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
33859. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
33860. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
33861. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
33862. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
33863. BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
33864. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
33865. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
33866. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
33867. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
33868. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
33869. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
33870. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
33871. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
33872. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
33873. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
33874. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
33875. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
33876. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
33877. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
33878. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
33879. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
33880. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
33881. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
33882. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
33883. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
33884. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
33885. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
33886. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
33887. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
33888. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
33889. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
33890. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
33891. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
33892. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
33893. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
33894. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
33895. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
33896. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
33897. BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
33898. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
33899. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
33900. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
33901. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
33902. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
33903. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
33904. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
33905. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
33906. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
33907. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
33908. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
33909. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
33910. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
33911. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
33912. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
33913. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
33914. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
33915. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
33916. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
33917. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
33918. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
33919. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
33920. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
33921. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
33922. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
33923. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
33924. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
33925. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
33926. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
33927. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
33928. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
33929. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
33930. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
33931. BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
33932. BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
33933. BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
33934. BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
33935. BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
33936. BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
33937. BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
33938. BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
33939. BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
33940. BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
33941. BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
33942. BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
33943. BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
33944. BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
33945. BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
33946. BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
33947. BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
33948. BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
33949. BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
33950. BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
33951. BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
33952. BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
33953. BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
33954. BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
33955. BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
33956. BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
33957. BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
33958. BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
33959. BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
33960. BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
33961. BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
33962. BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
33963. BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
33964. BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
33965. BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
33966. BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
33967. BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
33968. BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
33969. BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
33970. BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
33971. BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
33972. BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
33973. BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
33974. BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
33975. BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
33976. BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
33977. BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
33978. BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
33979. BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
33980. BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
33981. BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
33982. BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
33983. BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
33984. BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
33985. BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
33986. BIFPLR1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
33987. BIFPLR1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
33988. BIFPLR1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
33989. BIFPLR1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
33990. BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
33991. BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
33992. BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
33993. BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
33994. BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
33995. BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
33996. BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
33997. BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
33998. BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
33999. BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
34000. BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
34001. BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
34002. BIFPLR1_1_PMI_CAP_LIST__CAP_ID_MASK
34003. BIFPLR1_1_PMI_CAP_LIST__CAP_ID__SHIFT
34004. BIFPLR1_1_PMI_CAP_LIST__NEXT_PTR_MASK
34005. BIFPLR1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
34006. BIFPLR1_1_PMI_CAP__AUX_CURRENT_MASK
34007. BIFPLR1_1_PMI_CAP__AUX_CURRENT__SHIFT
34008. BIFPLR1_1_PMI_CAP__D1_SUPPORT_MASK
34009. BIFPLR1_1_PMI_CAP__D1_SUPPORT__SHIFT
34010. BIFPLR1_1_PMI_CAP__D2_SUPPORT_MASK
34011. BIFPLR1_1_PMI_CAP__D2_SUPPORT__SHIFT
34012. BIFPLR1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
34013. BIFPLR1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
34014. BIFPLR1_1_PMI_CAP__PME_CLOCK_MASK
34015. BIFPLR1_1_PMI_CAP__PME_CLOCK__SHIFT
34016. BIFPLR1_1_PMI_CAP__PME_SUPPORT_MASK
34017. BIFPLR1_1_PMI_CAP__PME_SUPPORT__SHIFT
34018. BIFPLR1_1_PMI_CAP__VERSION_MASK
34019. BIFPLR1_1_PMI_CAP__VERSION__SHIFT
34020. BIFPLR1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
34021. BIFPLR1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
34022. BIFPLR1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
34023. BIFPLR1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
34024. BIFPLR1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
34025. BIFPLR1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
34026. BIFPLR1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
34027. BIFPLR1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
34028. BIFPLR1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
34029. BIFPLR1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
34030. BIFPLR1_1_PMI_STATUS_CNTL__PME_EN_MASK
34031. BIFPLR1_1_PMI_STATUS_CNTL__PME_EN__SHIFT
34032. BIFPLR1_1_PMI_STATUS_CNTL__PME_STATUS_MASK
34033. BIFPLR1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
34034. BIFPLR1_1_PMI_STATUS_CNTL__PMI_DATA_MASK
34035. BIFPLR1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
34036. BIFPLR1_1_PMI_STATUS_CNTL__POWER_STATE_MASK
34037. BIFPLR1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
34038. BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
34039. BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
34040. BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
34041. BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
34042. BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
34043. BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
34044. BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
34045. BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
34046. BIFPLR1_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
34047. BIFPLR1_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
34048. BIFPLR1_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
34049. BIFPLR1_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
34050. BIFPLR1_1_PROG_INTERFACE__PROG_INTERFACE_MASK
34051. BIFPLR1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
34052. BIFPLR1_1_REVISION_ID__MAJOR_REV_ID_MASK
34053. BIFPLR1_1_REVISION_ID__MAJOR_REV_ID__SHIFT
34054. BIFPLR1_1_REVISION_ID__MINOR_REV_ID_MASK
34055. BIFPLR1_1_REVISION_ID__MINOR_REV_ID__SHIFT
34056. BIFPLR1_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
34057. BIFPLR1_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
34058. BIFPLR1_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
34059. BIFPLR1_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
34060. BIFPLR1_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK
34061. BIFPLR1_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
34062. BIFPLR1_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
34063. BIFPLR1_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
34064. BIFPLR1_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
34065. BIFPLR1_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
34066. BIFPLR1_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
34067. BIFPLR1_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
34068. BIFPLR1_1_ROOT_STATUS__PME_PENDING_MASK
34069. BIFPLR1_1_ROOT_STATUS__PME_PENDING__SHIFT
34070. BIFPLR1_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK
34071. BIFPLR1_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
34072. BIFPLR1_1_ROOT_STATUS__PME_STATUS_MASK
34073. BIFPLR1_1_ROOT_STATUS__PME_STATUS__SHIFT
34074. BIFPLR1_1_SECONDARY_STATUS__CAP_LIST_MASK
34075. BIFPLR1_1_SECONDARY_STATUS__CAP_LIST__SHIFT
34076. BIFPLR1_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK
34077. BIFPLR1_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
34078. BIFPLR1_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
34079. BIFPLR1_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
34080. BIFPLR1_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
34081. BIFPLR1_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
34082. BIFPLR1_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
34083. BIFPLR1_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
34084. BIFPLR1_1_SECONDARY_STATUS__PCI_66_EN_MASK
34085. BIFPLR1_1_SECONDARY_STATUS__PCI_66_EN__SHIFT
34086. BIFPLR1_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
34087. BIFPLR1_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
34088. BIFPLR1_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
34089. BIFPLR1_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
34090. BIFPLR1_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
34091. BIFPLR1_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
34092. BIFPLR1_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
34093. BIFPLR1_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
34094. BIFPLR1_1_SLOT_CAP2__RESERVED_MASK
34095. BIFPLR1_1_SLOT_CAP2__RESERVED__SHIFT
34096. BIFPLR1_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
34097. BIFPLR1_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
34098. BIFPLR1_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
34099. BIFPLR1_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
34100. BIFPLR1_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
34101. BIFPLR1_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
34102. BIFPLR1_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK
34103. BIFPLR1_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
34104. BIFPLR1_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK
34105. BIFPLR1_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
34106. BIFPLR1_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
34107. BIFPLR1_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
34108. BIFPLR1_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
34109. BIFPLR1_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
34110. BIFPLR1_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
34111. BIFPLR1_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
34112. BIFPLR1_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
34113. BIFPLR1_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
34114. BIFPLR1_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
34115. BIFPLR1_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
34116. BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
34117. BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
34118. BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
34119. BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
34120. BIFPLR1_1_SLOT_CNTL2__RESERVED_MASK
34121. BIFPLR1_1_SLOT_CNTL2__RESERVED__SHIFT
34122. BIFPLR1_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
34123. BIFPLR1_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
34124. BIFPLR1_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
34125. BIFPLR1_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
34126. BIFPLR1_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
34127. BIFPLR1_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
34128. BIFPLR1_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
34129. BIFPLR1_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
34130. BIFPLR1_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
34131. BIFPLR1_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
34132. BIFPLR1_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
34133. BIFPLR1_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
34134. BIFPLR1_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
34135. BIFPLR1_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
34136. BIFPLR1_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
34137. BIFPLR1_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
34138. BIFPLR1_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
34139. BIFPLR1_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
34140. BIFPLR1_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
34141. BIFPLR1_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
34142. BIFPLR1_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
34143. BIFPLR1_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
34144. BIFPLR1_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
34145. BIFPLR1_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
34146. BIFPLR1_1_SLOT_STATUS2__RESERVED_MASK
34147. BIFPLR1_1_SLOT_STATUS2__RESERVED__SHIFT
34148. BIFPLR1_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
34149. BIFPLR1_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
34150. BIFPLR1_1_SLOT_STATUS__COMMAND_COMPLETED_MASK
34151. BIFPLR1_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
34152. BIFPLR1_1_SLOT_STATUS__DL_STATE_CHANGED_MASK
34153. BIFPLR1_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
34154. BIFPLR1_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
34155. BIFPLR1_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
34156. BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
34157. BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
34158. BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK
34159. BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
34160. BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
34161. BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
34162. BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
34163. BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
34164. BIFPLR1_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
34165. BIFPLR1_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
34166. BIFPLR1_1_SSID_CAP_LIST__CAP_ID_MASK
34167. BIFPLR1_1_SSID_CAP_LIST__CAP_ID__SHIFT
34168. BIFPLR1_1_SSID_CAP_LIST__NEXT_PTR_MASK
34169. BIFPLR1_1_SSID_CAP_LIST__NEXT_PTR__SHIFT
34170. BIFPLR1_1_SSID_CAP__SUBSYSTEM_ID_MASK
34171. BIFPLR1_1_SSID_CAP__SUBSYSTEM_ID__SHIFT
34172. BIFPLR1_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
34173. BIFPLR1_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
34174. BIFPLR1_1_STATUS__CAP_LIST_MASK
34175. BIFPLR1_1_STATUS__CAP_LIST__SHIFT
34176. BIFPLR1_1_STATUS__DEVSEL_TIMING_MASK
34177. BIFPLR1_1_STATUS__DEVSEL_TIMING__SHIFT
34178. BIFPLR1_1_STATUS__FAST_BACK_CAPABLE_MASK
34179. BIFPLR1_1_STATUS__FAST_BACK_CAPABLE__SHIFT
34180. BIFPLR1_1_STATUS__INT_STATUS_MASK
34181. BIFPLR1_1_STATUS__INT_STATUS__SHIFT
34182. BIFPLR1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
34183. BIFPLR1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
34184. BIFPLR1_1_STATUS__PARITY_ERROR_DETECTED_MASK
34185. BIFPLR1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
34186. BIFPLR1_1_STATUS__PCI_66_EN_MASK
34187. BIFPLR1_1_STATUS__PCI_66_EN__SHIFT
34188. BIFPLR1_1_STATUS__RECEIVED_MASTER_ABORT_MASK
34189. BIFPLR1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
34190. BIFPLR1_1_STATUS__RECEIVED_TARGET_ABORT_MASK
34191. BIFPLR1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
34192. BIFPLR1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
34193. BIFPLR1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
34194. BIFPLR1_1_STATUS__SIGNAL_TARGET_ABORT_MASK
34195. BIFPLR1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
34196. BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
34197. BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
34198. BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
34199. BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
34200. BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
34201. BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
34202. BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
34203. BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
34204. BIFPLR1_1_SUB_CLASS__SUB_CLASS_MASK
34205. BIFPLR1_1_SUB_CLASS__SUB_CLASS__SHIFT
34206. BIFPLR1_1_VENDOR_ID__VENDOR_ID_MASK
34207. BIFPLR1_1_VENDOR_ID__VENDOR_ID__SHIFT
34208. BIFPLR1_2_BASE_CLASS__BASE_CLASS_MASK
34209. BIFPLR1_2_BASE_CLASS__BASE_CLASS__SHIFT
34210. BIFPLR1_2_BIST__BIST_CAP_MASK
34211. BIFPLR1_2_BIST__BIST_CAP__SHIFT
34212. BIFPLR1_2_BIST__BIST_COMP_MASK
34213. BIFPLR1_2_BIST__BIST_COMP__SHIFT
34214. BIFPLR1_2_BIST__BIST_STRT_MASK
34215. BIFPLR1_2_BIST__BIST_STRT__SHIFT
34216. BIFPLR1_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
34217. BIFPLR1_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
34218. BIFPLR1_2_CAP_PTR__CAP_PTR_MASK
34219. BIFPLR1_2_CAP_PTR__CAP_PTR__SHIFT
34220. BIFPLR1_2_COMMAND__AD_STEPPING_MASK
34221. BIFPLR1_2_COMMAND__AD_STEPPING__SHIFT
34222. BIFPLR1_2_COMMAND__BUS_MASTER_EN_MASK
34223. BIFPLR1_2_COMMAND__BUS_MASTER_EN__SHIFT
34224. BIFPLR1_2_COMMAND__FAST_B2B_EN_MASK
34225. BIFPLR1_2_COMMAND__FAST_B2B_EN__SHIFT
34226. BIFPLR1_2_COMMAND__INT_DIS_MASK
34227. BIFPLR1_2_COMMAND__INT_DIS__SHIFT
34228. BIFPLR1_2_COMMAND__IO_ACCESS_EN_MASK
34229. BIFPLR1_2_COMMAND__IO_ACCESS_EN__SHIFT
34230. BIFPLR1_2_COMMAND__MEM_ACCESS_EN_MASK
34231. BIFPLR1_2_COMMAND__MEM_ACCESS_EN__SHIFT
34232. BIFPLR1_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
34233. BIFPLR1_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
34234. BIFPLR1_2_COMMAND__PAL_SNOOP_EN_MASK
34235. BIFPLR1_2_COMMAND__PAL_SNOOP_EN__SHIFT
34236. BIFPLR1_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
34237. BIFPLR1_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
34238. BIFPLR1_2_COMMAND__SERR_EN_MASK
34239. BIFPLR1_2_COMMAND__SERR_EN__SHIFT
34240. BIFPLR1_2_COMMAND__SPECIAL_CYCLE_EN_MASK
34241. BIFPLR1_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
34242. BIFPLR1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
34243. BIFPLR1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
34244. BIFPLR1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
34245. BIFPLR1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
34246. BIFPLR1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
34247. BIFPLR1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
34248. BIFPLR1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
34249. BIFPLR1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
34250. BIFPLR1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
34251. BIFPLR1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
34252. BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
34253. BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
34254. BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
34255. BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
34256. BIFPLR1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
34257. BIFPLR1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
34258. BIFPLR1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
34259. BIFPLR1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
34260. BIFPLR1_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
34261. BIFPLR1_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
34262. BIFPLR1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
34263. BIFPLR1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
34264. BIFPLR1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
34265. BIFPLR1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
34266. BIFPLR1_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
34267. BIFPLR1_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
34268. BIFPLR1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
34269. BIFPLR1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
34270. BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
34271. BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
34272. BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
34273. BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
34274. BIFPLR1_2_DEVICE_CAP__EXTENDED_TAG_MASK
34275. BIFPLR1_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
34276. BIFPLR1_2_DEVICE_CAP__FLR_CAPABLE_MASK
34277. BIFPLR1_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
34278. BIFPLR1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
34279. BIFPLR1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
34280. BIFPLR1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
34281. BIFPLR1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
34282. BIFPLR1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
34283. BIFPLR1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
34284. BIFPLR1_2_DEVICE_CAP__PHANTOM_FUNC_MASK
34285. BIFPLR1_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
34286. BIFPLR1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
34287. BIFPLR1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
34288. BIFPLR1_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
34289. BIFPLR1_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
34290. BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
34291. BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
34292. BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
34293. BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
34294. BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
34295. BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
34296. BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
34297. BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
34298. BIFPLR1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
34299. BIFPLR1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
34300. BIFPLR1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
34301. BIFPLR1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
34302. BIFPLR1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
34303. BIFPLR1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
34304. BIFPLR1_2_DEVICE_CNTL2__LTR_EN_MASK
34305. BIFPLR1_2_DEVICE_CNTL2__LTR_EN__SHIFT
34306. BIFPLR1_2_DEVICE_CNTL2__OBFF_EN_MASK
34307. BIFPLR1_2_DEVICE_CNTL2__OBFF_EN__SHIFT
34308. BIFPLR1_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
34309. BIFPLR1_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
34310. BIFPLR1_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
34311. BIFPLR1_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
34312. BIFPLR1_2_DEVICE_CNTL__CORR_ERR_EN_MASK
34313. BIFPLR1_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
34314. BIFPLR1_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
34315. BIFPLR1_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
34316. BIFPLR1_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
34317. BIFPLR1_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
34318. BIFPLR1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
34319. BIFPLR1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
34320. BIFPLR1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
34321. BIFPLR1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
34322. BIFPLR1_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
34323. BIFPLR1_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
34324. BIFPLR1_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
34325. BIFPLR1_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
34326. BIFPLR1_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
34327. BIFPLR1_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
34328. BIFPLR1_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
34329. BIFPLR1_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
34330. BIFPLR1_2_DEVICE_CNTL__USR_REPORT_EN_MASK
34331. BIFPLR1_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
34332. BIFPLR1_2_DEVICE_ID__DEVICE_ID_MASK
34333. BIFPLR1_2_DEVICE_ID__DEVICE_ID__SHIFT
34334. BIFPLR1_2_DEVICE_STATUS2__RESERVED_MASK
34335. BIFPLR1_2_DEVICE_STATUS2__RESERVED__SHIFT
34336. BIFPLR1_2_DEVICE_STATUS__AUX_PWR_MASK
34337. BIFPLR1_2_DEVICE_STATUS__AUX_PWR__SHIFT
34338. BIFPLR1_2_DEVICE_STATUS__CORR_ERR_MASK
34339. BIFPLR1_2_DEVICE_STATUS__CORR_ERR__SHIFT
34340. BIFPLR1_2_DEVICE_STATUS__FATAL_ERR_MASK
34341. BIFPLR1_2_DEVICE_STATUS__FATAL_ERR__SHIFT
34342. BIFPLR1_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
34343. BIFPLR1_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
34344. BIFPLR1_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
34345. BIFPLR1_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
34346. BIFPLR1_2_DEVICE_STATUS__USR_DETECTED_MASK
34347. BIFPLR1_2_DEVICE_STATUS__USR_DETECTED__SHIFT
34348. BIFPLR1_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
34349. BIFPLR1_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
34350. BIFPLR1_2_HEADER__DEVICE_TYPE_MASK
34351. BIFPLR1_2_HEADER__DEVICE_TYPE__SHIFT
34352. BIFPLR1_2_HEADER__HEADER_TYPE_MASK
34353. BIFPLR1_2_HEADER__HEADER_TYPE__SHIFT
34354. BIFPLR1_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
34355. BIFPLR1_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
34356. BIFPLR1_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
34357. BIFPLR1_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
34358. BIFPLR1_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
34359. BIFPLR1_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
34360. BIFPLR1_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
34361. BIFPLR1_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
34362. BIFPLR1_2_IO_BASE_LIMIT__IO_BASE_MASK
34363. BIFPLR1_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
34364. BIFPLR1_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
34365. BIFPLR1_2_IO_BASE_LIMIT__IO_BASE__SHIFT
34366. BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT_MASK
34367. BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
34368. BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
34369. BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT
34370. BIFPLR1_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
34371. BIFPLR1_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
34372. BIFPLR1_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK
34373. BIFPLR1_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
34374. BIFPLR1_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
34375. BIFPLR1_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
34376. BIFPLR1_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
34377. BIFPLR1_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
34378. BIFPLR1_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
34379. BIFPLR1_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
34380. BIFPLR1_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK
34381. BIFPLR1_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
34382. BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
34383. BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
34384. BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK
34385. BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
34386. BIFPLR1_2_LATENCY__LATENCY_TIMER_MASK
34387. BIFPLR1_2_LATENCY__LATENCY_TIMER__SHIFT
34388. BIFPLR1_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
34389. BIFPLR1_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
34390. BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
34391. BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
34392. BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
34393. BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
34394. BIFPLR1_2_LINK_CAP2__RESERVED_MASK
34395. BIFPLR1_2_LINK_CAP2__RESERVED__SHIFT
34396. BIFPLR1_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
34397. BIFPLR1_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
34398. BIFPLR1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
34399. BIFPLR1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
34400. BIFPLR1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
34401. BIFPLR1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
34402. BIFPLR1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
34403. BIFPLR1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
34404. BIFPLR1_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
34405. BIFPLR1_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
34406. BIFPLR1_2_LINK_CAP__L1_EXIT_LATENCY_MASK
34407. BIFPLR1_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
34408. BIFPLR1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
34409. BIFPLR1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
34410. BIFPLR1_2_LINK_CAP__LINK_SPEED_MASK
34411. BIFPLR1_2_LINK_CAP__LINK_SPEED__SHIFT
34412. BIFPLR1_2_LINK_CAP__LINK_WIDTH_MASK
34413. BIFPLR1_2_LINK_CAP__LINK_WIDTH__SHIFT
34414. BIFPLR1_2_LINK_CAP__PM_SUPPORT_MASK
34415. BIFPLR1_2_LINK_CAP__PM_SUPPORT__SHIFT
34416. BIFPLR1_2_LINK_CAP__PORT_NUMBER_MASK
34417. BIFPLR1_2_LINK_CAP__PORT_NUMBER__SHIFT
34418. BIFPLR1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
34419. BIFPLR1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
34420. BIFPLR1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
34421. BIFPLR1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
34422. BIFPLR1_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
34423. BIFPLR1_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
34424. BIFPLR1_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
34425. BIFPLR1_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
34426. BIFPLR1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
34427. BIFPLR1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
34428. BIFPLR1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
34429. BIFPLR1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
34430. BIFPLR1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
34431. BIFPLR1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
34432. BIFPLR1_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
34433. BIFPLR1_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
34434. BIFPLR1_2_LINK_CNTL2__XMIT_MARGIN_MASK
34435. BIFPLR1_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
34436. BIFPLR1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
34437. BIFPLR1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
34438. BIFPLR1_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
34439. BIFPLR1_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
34440. BIFPLR1_2_LINK_CNTL__EXTENDED_SYNC_MASK
34441. BIFPLR1_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
34442. BIFPLR1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
34443. BIFPLR1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
34444. BIFPLR1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
34445. BIFPLR1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
34446. BIFPLR1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
34447. BIFPLR1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
34448. BIFPLR1_2_LINK_CNTL__LINK_DIS_MASK
34449. BIFPLR1_2_LINK_CNTL__LINK_DIS__SHIFT
34450. BIFPLR1_2_LINK_CNTL__PM_CONTROL_MASK
34451. BIFPLR1_2_LINK_CNTL__PM_CONTROL__SHIFT
34452. BIFPLR1_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
34453. BIFPLR1_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
34454. BIFPLR1_2_LINK_CNTL__RETRAIN_LINK_MASK
34455. BIFPLR1_2_LINK_CNTL__RETRAIN_LINK__SHIFT
34456. BIFPLR1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
34457. BIFPLR1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
34458. BIFPLR1_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
34459. BIFPLR1_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
34460. BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
34461. BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
34462. BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
34463. BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
34464. BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
34465. BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
34466. BIFPLR1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
34467. BIFPLR1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
34468. BIFPLR1_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
34469. BIFPLR1_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
34470. BIFPLR1_2_LINK_STATUS__DL_ACTIVE_MASK
34471. BIFPLR1_2_LINK_STATUS__DL_ACTIVE__SHIFT
34472. BIFPLR1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
34473. BIFPLR1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
34474. BIFPLR1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
34475. BIFPLR1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
34476. BIFPLR1_2_LINK_STATUS__LINK_TRAINING_MASK
34477. BIFPLR1_2_LINK_STATUS__LINK_TRAINING__SHIFT
34478. BIFPLR1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
34479. BIFPLR1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
34480. BIFPLR1_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
34481. BIFPLR1_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
34482. BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
34483. BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
34484. BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
34485. BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
34486. BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
34487. BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
34488. BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
34489. BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
34490. BIFPLR1_2_MSI_CAP_LIST__CAP_ID_MASK
34491. BIFPLR1_2_MSI_CAP_LIST__CAP_ID__SHIFT
34492. BIFPLR1_2_MSI_CAP_LIST__NEXT_PTR_MASK
34493. BIFPLR1_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
34494. BIFPLR1_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
34495. BIFPLR1_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
34496. BIFPLR1_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
34497. BIFPLR1_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
34498. BIFPLR1_2_MSI_MAP_CAP_LIST__CAP_ID_MASK
34499. BIFPLR1_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
34500. BIFPLR1_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
34501. BIFPLR1_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
34502. BIFPLR1_2_MSI_MAP_CAP__CAP_TYPE_MASK
34503. BIFPLR1_2_MSI_MAP_CAP__CAP_TYPE__SHIFT
34504. BIFPLR1_2_MSI_MAP_CAP__EN_MASK
34505. BIFPLR1_2_MSI_MAP_CAP__EN__SHIFT
34506. BIFPLR1_2_MSI_MAP_CAP__FIXD_MASK
34507. BIFPLR1_2_MSI_MAP_CAP__FIXD__SHIFT
34508. BIFPLR1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
34509. BIFPLR1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
34510. BIFPLR1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
34511. BIFPLR1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
34512. BIFPLR1_2_MSI_MSG_CNTL__MSI_64BIT_MASK
34513. BIFPLR1_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
34514. BIFPLR1_2_MSI_MSG_CNTL__MSI_EN_MASK
34515. BIFPLR1_2_MSI_MSG_CNTL__MSI_EN__SHIFT
34516. BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
34517. BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
34518. BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
34519. BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
34520. BIFPLR1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
34521. BIFPLR1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
34522. BIFPLR1_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
34523. BIFPLR1_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
34524. BIFPLR1_2_MSI_MSG_DATA__MSI_DATA_MASK
34525. BIFPLR1_2_MSI_MSG_DATA__MSI_DATA__SHIFT
34526. BIFPLR1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
34527. BIFPLR1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
34528. BIFPLR1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
34529. BIFPLR1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
34530. BIFPLR1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
34531. BIFPLR1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
34532. BIFPLR1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
34533. BIFPLR1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
34534. BIFPLR1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
34535. BIFPLR1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
34536. BIFPLR1_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
34537. BIFPLR1_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
34538. BIFPLR1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
34539. BIFPLR1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
34540. BIFPLR1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
34541. BIFPLR1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
34542. BIFPLR1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
34543. BIFPLR1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
34544. BIFPLR1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
34545. BIFPLR1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
34546. BIFPLR1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
34547. BIFPLR1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
34548. BIFPLR1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
34549. BIFPLR1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
34550. BIFPLR1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
34551. BIFPLR1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
34552. BIFPLR1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
34553. BIFPLR1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
34554. BIFPLR1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
34555. BIFPLR1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
34556. BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
34557. BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
34558. BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
34559. BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
34560. BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
34561. BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
34562. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
34563. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
34564. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
34565. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
34566. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
34567. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
34568. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
34569. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
34570. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
34571. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
34572. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
34573. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
34574. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
34575. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
34576. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
34577. BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
34578. BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
34579. BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
34580. BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
34581. BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
34582. BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
34583. BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
34584. BIFPLR1_2_PCIE_CAP_LIST__CAP_ID_MASK
34585. BIFPLR1_2_PCIE_CAP_LIST__CAP_ID__SHIFT
34586. BIFPLR1_2_PCIE_CAP_LIST__NEXT_PTR_MASK
34587. BIFPLR1_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
34588. BIFPLR1_2_PCIE_CAP__DEVICE_TYPE_MASK
34589. BIFPLR1_2_PCIE_CAP__DEVICE_TYPE__SHIFT
34590. BIFPLR1_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
34591. BIFPLR1_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
34592. BIFPLR1_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
34593. BIFPLR1_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
34594. BIFPLR1_2_PCIE_CAP__VERSION_MASK
34595. BIFPLR1_2_PCIE_CAP__VERSION__SHIFT
34596. BIFPLR1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
34597. BIFPLR1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
34598. BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
34599. BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
34600. BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
34601. BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
34602. BIFPLR1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
34603. BIFPLR1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
34604. BIFPLR1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
34605. BIFPLR1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
34606. BIFPLR1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
34607. BIFPLR1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
34608. BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
34609. BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
34610. BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
34611. BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
34612. BIFPLR1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
34613. BIFPLR1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
34614. BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
34615. BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
34616. BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
34617. BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
34618. BIFPLR1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
34619. BIFPLR1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
34620. BIFPLR1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
34621. BIFPLR1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
34622. BIFPLR1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
34623. BIFPLR1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
34624. BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
34625. BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
34626. BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
34627. BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
34628. BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
34629. BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
34630. BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
34631. BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
34632. BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
34633. BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
34634. BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
34635. BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
34636. BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
34637. BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
34638. BIFPLR1_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
34639. BIFPLR1_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
34640. BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
34641. BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
34642. BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
34643. BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
34644. BIFPLR1_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
34645. BIFPLR1_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
34646. BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
34647. BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
34648. BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
34649. BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
34650. BIFPLR1_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
34651. BIFPLR1_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
34652. BIFPLR1_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
34653. BIFPLR1_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
34654. BIFPLR1_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
34655. BIFPLR1_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
34656. BIFPLR1_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
34657. BIFPLR1_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
34658. BIFPLR1_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
34659. BIFPLR1_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
34660. BIFPLR1_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
34661. BIFPLR1_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
34662. BIFPLR1_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
34663. BIFPLR1_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
34664. BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
34665. BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
34666. BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
34667. BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
34668. BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
34669. BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
34670. BIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
34671. BIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
34672. BIFPLR1_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
34673. BIFPLR1_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
34674. BIFPLR1_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
34675. BIFPLR1_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
34676. BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
34677. BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
34678. BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
34679. BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
34680. BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
34681. BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
34682. BIFPLR1_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
34683. BIFPLR1_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
34684. BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
34685. BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
34686. BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
34687. BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
34688. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK
34689. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
34690. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK
34691. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
34692. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK
34693. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
34694. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK
34695. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
34696. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK
34697. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
34698. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK
34699. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
34700. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK
34701. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
34702. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK
34703. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
34704. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK
34705. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
34706. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK
34707. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
34708. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK
34709. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
34710. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK
34711. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
34712. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK
34713. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
34714. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK
34715. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
34716. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK
34717. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
34718. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK
34719. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
34720. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK
34721. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
34722. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK
34723. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
34724. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK
34725. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
34726. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK
34727. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
34728. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK
34729. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
34730. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK
34731. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
34732. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK
34733. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
34734. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK
34735. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
34736. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK
34737. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
34738. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK
34739. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
34740. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK
34741. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
34742. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK
34743. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
34744. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK
34745. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
34746. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK
34747. BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
34748. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK
34749. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
34750. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK
34751. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
34752. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK
34753. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
34754. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK
34755. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
34756. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK
34757. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
34758. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK
34759. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
34760. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK
34761. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
34762. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK
34763. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
34764. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK
34765. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
34766. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK
34767. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
34768. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK
34769. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
34770. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK
34771. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
34772. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK
34773. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
34774. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK
34775. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
34776. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK
34777. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
34778. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK
34779. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
34780. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK
34781. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
34782. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK
34783. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
34784. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK
34785. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
34786. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK
34787. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
34788. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK
34789. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
34790. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK
34791. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
34792. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK
34793. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
34794. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK
34795. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
34796. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK
34797. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
34798. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK
34799. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
34800. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK
34801. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
34802. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK
34803. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
34804. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK
34805. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
34806. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK
34807. BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
34808. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK
34809. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
34810. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK
34811. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
34812. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK
34813. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
34814. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK
34815. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
34816. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK
34817. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
34818. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK
34819. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
34820. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK
34821. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
34822. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK
34823. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
34824. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK
34825. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
34826. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK
34827. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
34828. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK
34829. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
34830. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK
34831. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
34832. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK
34833. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
34834. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK
34835. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
34836. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK
34837. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
34838. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK
34839. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
34840. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK
34841. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
34842. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK
34843. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
34844. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK
34845. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
34846. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK
34847. BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
34848. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK
34849. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
34850. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK
34851. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
34852. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK
34853. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
34854. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK
34855. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
34856. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK
34857. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
34858. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK
34859. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
34860. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK
34861. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
34862. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK
34863. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
34864. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK
34865. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
34866. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK
34867. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
34868. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK
34869. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
34870. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK
34871. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
34872. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK
34873. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
34874. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK
34875. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
34876. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK
34877. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
34878. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK
34879. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
34880. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK
34881. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
34882. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK
34883. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
34884. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK
34885. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
34886. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK
34887. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
34888. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK
34889. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
34890. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK
34891. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
34892. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK
34893. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
34894. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK
34895. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
34896. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK
34897. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
34898. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK
34899. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
34900. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK
34901. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
34902. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK
34903. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
34904. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK
34905. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
34906. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK
34907. BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
34908. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK
34909. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
34910. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK
34911. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
34912. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK
34913. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
34914. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK
34915. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
34916. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK
34917. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
34918. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK
34919. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
34920. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK
34921. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
34922. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK
34923. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
34924. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK
34925. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
34926. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK
34927. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
34928. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK
34929. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
34930. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK
34931. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
34932. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK
34933. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
34934. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK
34935. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
34936. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK
34937. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
34938. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK
34939. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
34940. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK
34941. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
34942. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK
34943. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
34944. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK
34945. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
34946. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK
34947. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
34948. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK
34949. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
34950. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK
34951. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
34952. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK
34953. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
34954. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK
34955. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
34956. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK
34957. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
34958. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK
34959. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
34960. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK
34961. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
34962. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK
34963. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
34964. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK
34965. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
34966. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK
34967. BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
34968. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK
34969. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
34970. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK
34971. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
34972. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK
34973. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
34974. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK
34975. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
34976. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK
34977. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
34978. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK
34979. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
34980. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK
34981. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
34982. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK
34983. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
34984. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK
34985. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
34986. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK
34987. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
34988. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK
34989. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
34990. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK
34991. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
34992. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK
34993. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
34994. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK
34995. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
34996. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK
34997. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
34998. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK
34999. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
35000. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK
35001. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
35002. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK
35003. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
35004. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK
35005. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
35006. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK
35007. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
35008. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK
35009. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
35010. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK
35011. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
35012. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK
35013. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
35014. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK
35015. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
35016. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK
35017. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
35018. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK
35019. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
35020. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK
35021. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
35022. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK
35023. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
35024. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK
35025. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
35026. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK
35027. BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
35028. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK
35029. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
35030. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK
35031. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
35032. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK
35033. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
35034. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK
35035. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
35036. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK
35037. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
35038. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK
35039. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
35040. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK
35041. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
35042. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK
35043. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
35044. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK
35045. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
35046. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK
35047. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
35048. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK
35049. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
35050. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK
35051. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
35052. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK
35053. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
35054. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK
35055. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
35056. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK
35057. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
35058. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK
35059. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
35060. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK
35061. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
35062. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK
35063. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
35064. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK
35065. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
35066. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK
35067. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
35068. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK
35069. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
35070. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK
35071. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
35072. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK
35073. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
35074. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK
35075. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
35076. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK
35077. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
35078. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK
35079. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
35080. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK
35081. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
35082. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK
35083. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
35084. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK
35085. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
35086. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK
35087. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
35088. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK
35089. BIFPLR1_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
35090. BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK
35091. BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
35092. BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK
35093. BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
35094. BIFPLR1_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
35095. BIFPLR1_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
35096. BIFPLR1_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK
35097. BIFPLR1_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
35098. BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
35099. BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
35100. BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
35101. BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
35102. BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
35103. BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
35104. BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
35105. BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
35106. BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
35107. BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
35108. BIFPLR1_2_PCIE_ESM_HEADER_2__CAP_ID_MASK
35109. BIFPLR1_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
35110. BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
35111. BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
35112. BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
35113. BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
35114. BIFPLR1_2_PCIE_HDR_LOG0__TLP_HDR_MASK
35115. BIFPLR1_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
35116. BIFPLR1_2_PCIE_HDR_LOG1__TLP_HDR_MASK
35117. BIFPLR1_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
35118. BIFPLR1_2_PCIE_HDR_LOG2__TLP_HDR_MASK
35119. BIFPLR1_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
35120. BIFPLR1_2_PCIE_HDR_LOG3__TLP_HDR_MASK
35121. BIFPLR1_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
35122. BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
35123. BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
35124. BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
35125. BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
35126. BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
35127. BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
35128. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
35129. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
35130. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
35131. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
35132. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
35133. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
35134. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
35135. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
35136. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
35137. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
35138. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
35139. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
35140. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
35141. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
35142. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
35143. BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
35144. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
35145. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
35146. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
35147. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
35148. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
35149. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
35150. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
35151. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
35152. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
35153. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
35154. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
35155. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
35156. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
35157. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
35158. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
35159. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
35160. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
35161. BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
35162. BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35163. BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35164. BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35165. BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35166. BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35167. BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35168. BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35169. BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35170. BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35171. BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35172. BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35173. BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35174. BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35175. BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35176. BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35177. BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35178. BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35179. BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35180. BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35181. BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35182. BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35183. BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35184. BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35185. BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35186. BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35187. BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35188. BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35189. BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35190. BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35191. BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35192. BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35193. BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35194. BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35195. BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35196. BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35197. BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35198. BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35199. BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35200. BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35201. BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35202. BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35203. BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35204. BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35205. BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35206. BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35207. BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35208. BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35209. BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35210. BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35211. BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35212. BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35213. BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35214. BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35215. BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35216. BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35217. BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35218. BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35219. BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35220. BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35221. BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35222. BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35223. BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35224. BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35225. BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35226. BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35227. BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35228. BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35229. BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35230. BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35231. BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35232. BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35233. BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35234. BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35235. BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35236. BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35237. BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35238. BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35239. BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35240. BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35241. BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35242. BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35243. BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35244. BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35245. BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35246. BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35247. BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35248. BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35249. BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35250. BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35251. BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35252. BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35253. BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35254. BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35255. BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35256. BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35257. BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35258. BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35259. BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35260. BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35261. BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35262. BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35263. BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35264. BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35265. BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35266. BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35267. BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35268. BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35269. BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35270. BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35271. BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35272. BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35273. BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35274. BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35275. BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35276. BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35277. BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35278. BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35279. BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35280. BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35281. BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35282. BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
35283. BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
35284. BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
35285. BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
35286. BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
35287. BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
35288. BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
35289. BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
35290. BIFPLR1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
35291. BIFPLR1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
35292. BIFPLR1_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
35293. BIFPLR1_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
35294. BIFPLR1_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
35295. BIFPLR1_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
35296. BIFPLR1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
35297. BIFPLR1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
35298. BIFPLR1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
35299. BIFPLR1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
35300. BIFPLR1_2_PCIE_LINK_CNTL3__RESERVED_MASK
35301. BIFPLR1_2_PCIE_LINK_CNTL3__RESERVED__SHIFT
35302. BIFPLR1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
35303. BIFPLR1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
35304. BIFPLR1_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
35305. BIFPLR1_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
35306. BIFPLR1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
35307. BIFPLR1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
35308. BIFPLR1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
35309. BIFPLR1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
35310. BIFPLR1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
35311. BIFPLR1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
35312. BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
35313. BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
35314. BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
35315. BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
35316. BIFPLR1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
35317. BIFPLR1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
35318. BIFPLR1_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK
35319. BIFPLR1_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
35320. BIFPLR1_2_PCIE_MC_CNTL__MC_ENABLE_MASK
35321. BIFPLR1_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT
35322. BIFPLR1_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
35323. BIFPLR1_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
35324. BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
35325. BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
35326. BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
35327. BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
35328. BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
35329. BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
35330. BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
35331. BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
35332. BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
35333. BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
35334. BIFPLR1_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
35335. BIFPLR1_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
35336. BIFPLR1_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
35337. BIFPLR1_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
35338. BIFPLR1_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
35339. BIFPLR1_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
35340. BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
35341. BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
35342. BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
35343. BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
35344. BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
35345. BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
35346. BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
35347. BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
35348. BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
35349. BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
35350. BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
35351. BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
35352. BIFPLR1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
35353. BIFPLR1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
35354. BIFPLR1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
35355. BIFPLR1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
35356. BIFPLR1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
35357. BIFPLR1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
35358. BIFPLR1_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
35359. BIFPLR1_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
35360. BIFPLR1_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
35361. BIFPLR1_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
35362. BIFPLR1_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
35363. BIFPLR1_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
35364. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
35365. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
35366. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
35367. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
35368. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
35369. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
35370. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
35371. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
35372. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
35373. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
35374. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
35375. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
35376. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
35377. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
35378. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
35379. BIFPLR1_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
35380. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
35381. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
35382. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
35383. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
35384. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
35385. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
35386. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
35387. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
35388. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
35389. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
35390. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
35391. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
35392. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
35393. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
35394. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
35395. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
35396. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
35397. BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
35398. BIFPLR1_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
35399. BIFPLR1_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
35400. BIFPLR1_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
35401. BIFPLR1_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
35402. BIFPLR1_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
35403. BIFPLR1_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
35404. BIFPLR1_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
35405. BIFPLR1_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
35406. BIFPLR1_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
35407. BIFPLR1_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
35408. BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
35409. BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
35410. BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK
35411. BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
35412. BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
35413. BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
35414. BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
35415. BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
35416. BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CTO_MASK
35417. BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
35418. BIFPLR1_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
35419. BIFPLR1_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
35420. BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
35421. BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
35422. BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK
35423. BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
35424. BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
35425. BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
35426. BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
35427. BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
35428. BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
35429. BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
35430. BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
35431. BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
35432. BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
35433. BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
35434. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
35435. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
35436. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
35437. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
35438. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
35439. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
35440. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
35441. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
35442. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
35443. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
35444. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
35445. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
35446. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
35447. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
35448. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
35449. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
35450. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
35451. BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
35452. BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
35453. BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
35454. BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
35455. BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
35456. BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
35457. BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
35458. BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
35459. BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
35460. BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK
35461. BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
35462. BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
35463. BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
35464. BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
35465. BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
35466. BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
35467. BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
35468. BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
35469. BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
35470. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
35471. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
35472. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
35473. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
35474. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
35475. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
35476. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
35477. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
35478. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
35479. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
35480. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
35481. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
35482. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
35483. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
35484. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
35485. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
35486. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
35487. BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
35488. BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
35489. BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
35490. BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
35491. BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
35492. BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
35493. BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
35494. BIFPLR1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
35495. BIFPLR1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
35496. BIFPLR1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
35497. BIFPLR1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
35498. BIFPLR1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
35499. BIFPLR1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
35500. BIFPLR1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
35501. BIFPLR1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
35502. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
35503. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
35504. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
35505. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
35506. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
35507. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
35508. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
35509. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
35510. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
35511. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
35512. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
35513. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
35514. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
35515. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
35516. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
35517. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
35518. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
35519. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
35520. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
35521. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
35522. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
35523. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
35524. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
35525. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
35526. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
35527. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
35528. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
35529. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
35530. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
35531. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
35532. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
35533. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
35534. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
35535. BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
35536. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
35537. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
35538. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
35539. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
35540. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
35541. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
35542. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
35543. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
35544. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
35545. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
35546. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
35547. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
35548. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
35549. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
35550. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
35551. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
35552. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
35553. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
35554. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
35555. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
35556. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
35557. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
35558. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
35559. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
35560. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
35561. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
35562. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
35563. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
35564. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
35565. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
35566. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
35567. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
35568. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
35569. BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
35570. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
35571. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
35572. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
35573. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
35574. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
35575. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
35576. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
35577. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
35578. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
35579. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
35580. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
35581. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
35582. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
35583. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
35584. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
35585. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
35586. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
35587. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
35588. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
35589. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
35590. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
35591. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
35592. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
35593. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
35594. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
35595. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
35596. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
35597. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
35598. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
35599. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
35600. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
35601. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
35602. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
35603. BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
35604. BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
35605. BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
35606. BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
35607. BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
35608. BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
35609. BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
35610. BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
35611. BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
35612. BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
35613. BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
35614. BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
35615. BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
35616. BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
35617. BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
35618. BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
35619. BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
35620. BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
35621. BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
35622. BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
35623. BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
35624. BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
35625. BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
35626. BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
35627. BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
35628. BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
35629. BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
35630. BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
35631. BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
35632. BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
35633. BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
35634. BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
35635. BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
35636. BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
35637. BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
35638. BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
35639. BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
35640. BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
35641. BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
35642. BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
35643. BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
35644. BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
35645. BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
35646. BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
35647. BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
35648. BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
35649. BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
35650. BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
35651. BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
35652. BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
35653. BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
35654. BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
35655. BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
35656. BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
35657. BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
35658. BIFPLR1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
35659. BIFPLR1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
35660. BIFPLR1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
35661. BIFPLR1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
35662. BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
35663. BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
35664. BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
35665. BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
35666. BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
35667. BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
35668. BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
35669. BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
35670. BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
35671. BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
35672. BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
35673. BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
35674. BIFPLR1_2_PMI_CAP_LIST__CAP_ID_MASK
35675. BIFPLR1_2_PMI_CAP_LIST__CAP_ID__SHIFT
35676. BIFPLR1_2_PMI_CAP_LIST__NEXT_PTR_MASK
35677. BIFPLR1_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
35678. BIFPLR1_2_PMI_CAP__AUX_CURRENT_MASK
35679. BIFPLR1_2_PMI_CAP__AUX_CURRENT__SHIFT
35680. BIFPLR1_2_PMI_CAP__D1_SUPPORT_MASK
35681. BIFPLR1_2_PMI_CAP__D1_SUPPORT__SHIFT
35682. BIFPLR1_2_PMI_CAP__D2_SUPPORT_MASK
35683. BIFPLR1_2_PMI_CAP__D2_SUPPORT__SHIFT
35684. BIFPLR1_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
35685. BIFPLR1_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
35686. BIFPLR1_2_PMI_CAP__PME_CLOCK_MASK
35687. BIFPLR1_2_PMI_CAP__PME_CLOCK__SHIFT
35688. BIFPLR1_2_PMI_CAP__PME_SUPPORT_MASK
35689. BIFPLR1_2_PMI_CAP__PME_SUPPORT__SHIFT
35690. BIFPLR1_2_PMI_CAP__VERSION_MASK
35691. BIFPLR1_2_PMI_CAP__VERSION__SHIFT
35692. BIFPLR1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
35693. BIFPLR1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
35694. BIFPLR1_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
35695. BIFPLR1_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
35696. BIFPLR1_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
35697. BIFPLR1_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
35698. BIFPLR1_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
35699. BIFPLR1_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
35700. BIFPLR1_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
35701. BIFPLR1_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
35702. BIFPLR1_2_PMI_STATUS_CNTL__PME_EN_MASK
35703. BIFPLR1_2_PMI_STATUS_CNTL__PME_EN__SHIFT
35704. BIFPLR1_2_PMI_STATUS_CNTL__PME_STATUS_MASK
35705. BIFPLR1_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
35706. BIFPLR1_2_PMI_STATUS_CNTL__PMI_DATA_MASK
35707. BIFPLR1_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
35708. BIFPLR1_2_PMI_STATUS_CNTL__POWER_STATE_MASK
35709. BIFPLR1_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
35710. BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
35711. BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
35712. BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
35713. BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
35714. BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
35715. BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
35716. BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
35717. BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
35718. BIFPLR1_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
35719. BIFPLR1_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
35720. BIFPLR1_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
35721. BIFPLR1_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
35722. BIFPLR1_2_PROG_INTERFACE__PROG_INTERFACE_MASK
35723. BIFPLR1_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
35724. BIFPLR1_2_REVISION_ID__MAJOR_REV_ID_MASK
35725. BIFPLR1_2_REVISION_ID__MAJOR_REV_ID__SHIFT
35726. BIFPLR1_2_REVISION_ID__MINOR_REV_ID_MASK
35727. BIFPLR1_2_REVISION_ID__MINOR_REV_ID__SHIFT
35728. BIFPLR1_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
35729. BIFPLR1_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
35730. BIFPLR1_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
35731. BIFPLR1_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
35732. BIFPLR1_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK
35733. BIFPLR1_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
35734. BIFPLR1_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
35735. BIFPLR1_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
35736. BIFPLR1_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
35737. BIFPLR1_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
35738. BIFPLR1_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
35739. BIFPLR1_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
35740. BIFPLR1_2_ROOT_STATUS__PME_PENDING_MASK
35741. BIFPLR1_2_ROOT_STATUS__PME_PENDING__SHIFT
35742. BIFPLR1_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK
35743. BIFPLR1_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
35744. BIFPLR1_2_ROOT_STATUS__PME_STATUS_MASK
35745. BIFPLR1_2_ROOT_STATUS__PME_STATUS__SHIFT
35746. BIFPLR1_2_SECONDARY_STATUS__CAP_LIST_MASK
35747. BIFPLR1_2_SECONDARY_STATUS__CAP_LIST__SHIFT
35748. BIFPLR1_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK
35749. BIFPLR1_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
35750. BIFPLR1_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
35751. BIFPLR1_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
35752. BIFPLR1_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
35753. BIFPLR1_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
35754. BIFPLR1_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
35755. BIFPLR1_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
35756. BIFPLR1_2_SECONDARY_STATUS__PCI_66_EN_MASK
35757. BIFPLR1_2_SECONDARY_STATUS__PCI_66_EN__SHIFT
35758. BIFPLR1_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
35759. BIFPLR1_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
35760. BIFPLR1_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
35761. BIFPLR1_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
35762. BIFPLR1_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
35763. BIFPLR1_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
35764. BIFPLR1_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
35765. BIFPLR1_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
35766. BIFPLR1_2_SLOT_CAP2__RESERVED_MASK
35767. BIFPLR1_2_SLOT_CAP2__RESERVED__SHIFT
35768. BIFPLR1_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
35769. BIFPLR1_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
35770. BIFPLR1_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
35771. BIFPLR1_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
35772. BIFPLR1_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
35773. BIFPLR1_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
35774. BIFPLR1_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK
35775. BIFPLR1_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
35776. BIFPLR1_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK
35777. BIFPLR1_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
35778. BIFPLR1_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
35779. BIFPLR1_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
35780. BIFPLR1_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
35781. BIFPLR1_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
35782. BIFPLR1_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
35783. BIFPLR1_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
35784. BIFPLR1_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
35785. BIFPLR1_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
35786. BIFPLR1_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
35787. BIFPLR1_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
35788. BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
35789. BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
35790. BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
35791. BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
35792. BIFPLR1_2_SLOT_CNTL2__RESERVED_MASK
35793. BIFPLR1_2_SLOT_CNTL2__RESERVED__SHIFT
35794. BIFPLR1_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
35795. BIFPLR1_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
35796. BIFPLR1_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
35797. BIFPLR1_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
35798. BIFPLR1_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
35799. BIFPLR1_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
35800. BIFPLR1_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
35801. BIFPLR1_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
35802. BIFPLR1_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
35803. BIFPLR1_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
35804. BIFPLR1_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
35805. BIFPLR1_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
35806. BIFPLR1_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
35807. BIFPLR1_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
35808. BIFPLR1_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
35809. BIFPLR1_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
35810. BIFPLR1_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
35811. BIFPLR1_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
35812. BIFPLR1_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
35813. BIFPLR1_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
35814. BIFPLR1_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
35815. BIFPLR1_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
35816. BIFPLR1_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
35817. BIFPLR1_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
35818. BIFPLR1_2_SLOT_STATUS2__RESERVED_MASK
35819. BIFPLR1_2_SLOT_STATUS2__RESERVED__SHIFT
35820. BIFPLR1_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
35821. BIFPLR1_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
35822. BIFPLR1_2_SLOT_STATUS__COMMAND_COMPLETED_MASK
35823. BIFPLR1_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
35824. BIFPLR1_2_SLOT_STATUS__DL_STATE_CHANGED_MASK
35825. BIFPLR1_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
35826. BIFPLR1_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
35827. BIFPLR1_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
35828. BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
35829. BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
35830. BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK
35831. BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
35832. BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
35833. BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
35834. BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
35835. BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
35836. BIFPLR1_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
35837. BIFPLR1_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
35838. BIFPLR1_2_SSID_CAP_LIST__CAP_ID_MASK
35839. BIFPLR1_2_SSID_CAP_LIST__CAP_ID__SHIFT
35840. BIFPLR1_2_SSID_CAP_LIST__NEXT_PTR_MASK
35841. BIFPLR1_2_SSID_CAP_LIST__NEXT_PTR__SHIFT
35842. BIFPLR1_2_SSID_CAP__SUBSYSTEM_ID_MASK
35843. BIFPLR1_2_SSID_CAP__SUBSYSTEM_ID__SHIFT
35844. BIFPLR1_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
35845. BIFPLR1_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
35846. BIFPLR1_2_STATUS__CAP_LIST_MASK
35847. BIFPLR1_2_STATUS__CAP_LIST__SHIFT
35848. BIFPLR1_2_STATUS__DEVSEL_TIMING_MASK
35849. BIFPLR1_2_STATUS__DEVSEL_TIMING__SHIFT
35850. BIFPLR1_2_STATUS__FAST_BACK_CAPABLE_MASK
35851. BIFPLR1_2_STATUS__FAST_BACK_CAPABLE__SHIFT
35852. BIFPLR1_2_STATUS__INT_STATUS_MASK
35853. BIFPLR1_2_STATUS__INT_STATUS__SHIFT
35854. BIFPLR1_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
35855. BIFPLR1_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
35856. BIFPLR1_2_STATUS__PARITY_ERROR_DETECTED_MASK
35857. BIFPLR1_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
35858. BIFPLR1_2_STATUS__PCI_66_EN_MASK
35859. BIFPLR1_2_STATUS__PCI_66_EN__SHIFT
35860. BIFPLR1_2_STATUS__RECEIVED_MASTER_ABORT_MASK
35861. BIFPLR1_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
35862. BIFPLR1_2_STATUS__RECEIVED_TARGET_ABORT_MASK
35863. BIFPLR1_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
35864. BIFPLR1_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
35865. BIFPLR1_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
35866. BIFPLR1_2_STATUS__SIGNAL_TARGET_ABORT_MASK
35867. BIFPLR1_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
35868. BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
35869. BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
35870. BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
35871. BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
35872. BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
35873. BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
35874. BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
35875. BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
35876. BIFPLR1_2_SUB_CLASS__SUB_CLASS_MASK
35877. BIFPLR1_2_SUB_CLASS__SUB_CLASS__SHIFT
35878. BIFPLR1_2_VENDOR_ID__VENDOR_ID_MASK
35879. BIFPLR1_2_VENDOR_ID__VENDOR_ID__SHIFT
35880. BIFPLR2_0_BASE_CLASS__BASE_CLASS_MASK
35881. BIFPLR2_0_BASE_CLASS__BASE_CLASS__SHIFT
35882. BIFPLR2_0_BIST__BIST_CAP_MASK
35883. BIFPLR2_0_BIST__BIST_CAP__SHIFT
35884. BIFPLR2_0_BIST__BIST_COMP_MASK
35885. BIFPLR2_0_BIST__BIST_COMP__SHIFT
35886. BIFPLR2_0_BIST__BIST_STRT_MASK
35887. BIFPLR2_0_BIST__BIST_STRT__SHIFT
35888. BIFPLR2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
35889. BIFPLR2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
35890. BIFPLR2_0_CAP_PTR__CAP_PTR_MASK
35891. BIFPLR2_0_CAP_PTR__CAP_PTR__SHIFT
35892. BIFPLR2_0_COMMAND__AD_STEPPING_MASK
35893. BIFPLR2_0_COMMAND__AD_STEPPING__SHIFT
35894. BIFPLR2_0_COMMAND__BUS_MASTER_EN_MASK
35895. BIFPLR2_0_COMMAND__BUS_MASTER_EN__SHIFT
35896. BIFPLR2_0_COMMAND__FAST_B2B_EN_MASK
35897. BIFPLR2_0_COMMAND__FAST_B2B_EN__SHIFT
35898. BIFPLR2_0_COMMAND__INT_DIS_MASK
35899. BIFPLR2_0_COMMAND__INT_DIS__SHIFT
35900. BIFPLR2_0_COMMAND__IO_ACCESS_EN_MASK
35901. BIFPLR2_0_COMMAND__IO_ACCESS_EN__SHIFT
35902. BIFPLR2_0_COMMAND__MEM_ACCESS_EN_MASK
35903. BIFPLR2_0_COMMAND__MEM_ACCESS_EN__SHIFT
35904. BIFPLR2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
35905. BIFPLR2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
35906. BIFPLR2_0_COMMAND__PAL_SNOOP_EN_MASK
35907. BIFPLR2_0_COMMAND__PAL_SNOOP_EN__SHIFT
35908. BIFPLR2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
35909. BIFPLR2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
35910. BIFPLR2_0_COMMAND__SERR_EN_MASK
35911. BIFPLR2_0_COMMAND__SERR_EN__SHIFT
35912. BIFPLR2_0_COMMAND__SPECIAL_CYCLE_EN_MASK
35913. BIFPLR2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
35914. BIFPLR2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
35915. BIFPLR2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
35916. BIFPLR2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
35917. BIFPLR2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
35918. BIFPLR2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
35919. BIFPLR2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
35920. BIFPLR2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
35921. BIFPLR2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
35922. BIFPLR2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
35923. BIFPLR2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
35924. BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
35925. BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
35926. BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
35927. BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
35928. BIFPLR2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
35929. BIFPLR2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
35930. BIFPLR2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
35931. BIFPLR2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
35932. BIFPLR2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
35933. BIFPLR2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
35934. BIFPLR2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
35935. BIFPLR2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
35936. BIFPLR2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
35937. BIFPLR2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
35938. BIFPLR2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
35939. BIFPLR2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
35940. BIFPLR2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
35941. BIFPLR2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
35942. BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
35943. BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
35944. BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
35945. BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
35946. BIFPLR2_0_DEVICE_CAP__EXTENDED_TAG_MASK
35947. BIFPLR2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
35948. BIFPLR2_0_DEVICE_CAP__FLR_CAPABLE_MASK
35949. BIFPLR2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
35950. BIFPLR2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
35951. BIFPLR2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
35952. BIFPLR2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
35953. BIFPLR2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
35954. BIFPLR2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
35955. BIFPLR2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
35956. BIFPLR2_0_DEVICE_CAP__PHANTOM_FUNC_MASK
35957. BIFPLR2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
35958. BIFPLR2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
35959. BIFPLR2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
35960. BIFPLR2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
35961. BIFPLR2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
35962. BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
35963. BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
35964. BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
35965. BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
35966. BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
35967. BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
35968. BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
35969. BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
35970. BIFPLR2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
35971. BIFPLR2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
35972. BIFPLR2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
35973. BIFPLR2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
35974. BIFPLR2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
35975. BIFPLR2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
35976. BIFPLR2_0_DEVICE_CNTL2__LTR_EN_MASK
35977. BIFPLR2_0_DEVICE_CNTL2__LTR_EN__SHIFT
35978. BIFPLR2_0_DEVICE_CNTL2__OBFF_EN_MASK
35979. BIFPLR2_0_DEVICE_CNTL2__OBFF_EN__SHIFT
35980. BIFPLR2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
35981. BIFPLR2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
35982. BIFPLR2_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
35983. BIFPLR2_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
35984. BIFPLR2_0_DEVICE_CNTL__CORR_ERR_EN_MASK
35985. BIFPLR2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
35986. BIFPLR2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
35987. BIFPLR2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
35988. BIFPLR2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
35989. BIFPLR2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
35990. BIFPLR2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
35991. BIFPLR2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
35992. BIFPLR2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
35993. BIFPLR2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
35994. BIFPLR2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
35995. BIFPLR2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
35996. BIFPLR2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
35997. BIFPLR2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
35998. BIFPLR2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
35999. BIFPLR2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
36000. BIFPLR2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
36001. BIFPLR2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
36002. BIFPLR2_0_DEVICE_CNTL__USR_REPORT_EN_MASK
36003. BIFPLR2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
36004. BIFPLR2_0_DEVICE_ID__DEVICE_ID_MASK
36005. BIFPLR2_0_DEVICE_ID__DEVICE_ID__SHIFT
36006. BIFPLR2_0_DEVICE_STATUS2__RESERVED_MASK
36007. BIFPLR2_0_DEVICE_STATUS2__RESERVED__SHIFT
36008. BIFPLR2_0_DEVICE_STATUS__AUX_PWR_MASK
36009. BIFPLR2_0_DEVICE_STATUS__AUX_PWR__SHIFT
36010. BIFPLR2_0_DEVICE_STATUS__CORR_ERR_MASK
36011. BIFPLR2_0_DEVICE_STATUS__CORR_ERR__SHIFT
36012. BIFPLR2_0_DEVICE_STATUS__FATAL_ERR_MASK
36013. BIFPLR2_0_DEVICE_STATUS__FATAL_ERR__SHIFT
36014. BIFPLR2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
36015. BIFPLR2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
36016. BIFPLR2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
36017. BIFPLR2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
36018. BIFPLR2_0_DEVICE_STATUS__USR_DETECTED_MASK
36019. BIFPLR2_0_DEVICE_STATUS__USR_DETECTED__SHIFT
36020. BIFPLR2_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
36021. BIFPLR2_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
36022. BIFPLR2_0_HEADER__DEVICE_TYPE_MASK
36023. BIFPLR2_0_HEADER__DEVICE_TYPE__SHIFT
36024. BIFPLR2_0_HEADER__HEADER_TYPE_MASK
36025. BIFPLR2_0_HEADER__HEADER_TYPE__SHIFT
36026. BIFPLR2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
36027. BIFPLR2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
36028. BIFPLR2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
36029. BIFPLR2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
36030. BIFPLR2_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
36031. BIFPLR2_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
36032. BIFPLR2_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
36033. BIFPLR2_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
36034. BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_MASK
36035. BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
36036. BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
36037. BIFPLR2_0_IO_BASE_LIMIT__IO_BASE__SHIFT
36038. BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_MASK
36039. BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
36040. BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
36041. BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT
36042. BIFPLR2_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
36043. BIFPLR2_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
36044. BIFPLR2_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK
36045. BIFPLR2_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
36046. BIFPLR2_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
36047. BIFPLR2_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
36048. BIFPLR2_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
36049. BIFPLR2_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
36050. BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
36051. BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
36052. BIFPLR2_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK
36053. BIFPLR2_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
36054. BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
36055. BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
36056. BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK
36057. BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
36058. BIFPLR2_0_LATENCY__LATENCY_TIMER_MASK
36059. BIFPLR2_0_LATENCY__LATENCY_TIMER__SHIFT
36060. BIFPLR2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
36061. BIFPLR2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
36062. BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
36063. BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
36064. BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
36065. BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
36066. BIFPLR2_0_LINK_CAP2__RESERVED_MASK
36067. BIFPLR2_0_LINK_CAP2__RESERVED__SHIFT
36068. BIFPLR2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
36069. BIFPLR2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
36070. BIFPLR2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
36071. BIFPLR2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
36072. BIFPLR2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
36073. BIFPLR2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
36074. BIFPLR2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
36075. BIFPLR2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
36076. BIFPLR2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
36077. BIFPLR2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
36078. BIFPLR2_0_LINK_CAP__L1_EXIT_LATENCY_MASK
36079. BIFPLR2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
36080. BIFPLR2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
36081. BIFPLR2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
36082. BIFPLR2_0_LINK_CAP__LINK_SPEED_MASK
36083. BIFPLR2_0_LINK_CAP__LINK_SPEED__SHIFT
36084. BIFPLR2_0_LINK_CAP__LINK_WIDTH_MASK
36085. BIFPLR2_0_LINK_CAP__LINK_WIDTH__SHIFT
36086. BIFPLR2_0_LINK_CAP__PM_SUPPORT_MASK
36087. BIFPLR2_0_LINK_CAP__PM_SUPPORT__SHIFT
36088. BIFPLR2_0_LINK_CAP__PORT_NUMBER_MASK
36089. BIFPLR2_0_LINK_CAP__PORT_NUMBER__SHIFT
36090. BIFPLR2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
36091. BIFPLR2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
36092. BIFPLR2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
36093. BIFPLR2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
36094. BIFPLR2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
36095. BIFPLR2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
36096. BIFPLR2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
36097. BIFPLR2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
36098. BIFPLR2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
36099. BIFPLR2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
36100. BIFPLR2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
36101. BIFPLR2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
36102. BIFPLR2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
36103. BIFPLR2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
36104. BIFPLR2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
36105. BIFPLR2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
36106. BIFPLR2_0_LINK_CNTL2__XMIT_MARGIN_MASK
36107. BIFPLR2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
36108. BIFPLR2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
36109. BIFPLR2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
36110. BIFPLR2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
36111. BIFPLR2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
36112. BIFPLR2_0_LINK_CNTL__EXTENDED_SYNC_MASK
36113. BIFPLR2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
36114. BIFPLR2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
36115. BIFPLR2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
36116. BIFPLR2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
36117. BIFPLR2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
36118. BIFPLR2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
36119. BIFPLR2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
36120. BIFPLR2_0_LINK_CNTL__LINK_DIS_MASK
36121. BIFPLR2_0_LINK_CNTL__LINK_DIS__SHIFT
36122. BIFPLR2_0_LINK_CNTL__PM_CONTROL_MASK
36123. BIFPLR2_0_LINK_CNTL__PM_CONTROL__SHIFT
36124. BIFPLR2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
36125. BIFPLR2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
36126. BIFPLR2_0_LINK_CNTL__RETRAIN_LINK_MASK
36127. BIFPLR2_0_LINK_CNTL__RETRAIN_LINK__SHIFT
36128. BIFPLR2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
36129. BIFPLR2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
36130. BIFPLR2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
36131. BIFPLR2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
36132. BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
36133. BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
36134. BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
36135. BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
36136. BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
36137. BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
36138. BIFPLR2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
36139. BIFPLR2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
36140. BIFPLR2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
36141. BIFPLR2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
36142. BIFPLR2_0_LINK_STATUS__DL_ACTIVE_MASK
36143. BIFPLR2_0_LINK_STATUS__DL_ACTIVE__SHIFT
36144. BIFPLR2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
36145. BIFPLR2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
36146. BIFPLR2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
36147. BIFPLR2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
36148. BIFPLR2_0_LINK_STATUS__LINK_TRAINING_MASK
36149. BIFPLR2_0_LINK_STATUS__LINK_TRAINING__SHIFT
36150. BIFPLR2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
36151. BIFPLR2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
36152. BIFPLR2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
36153. BIFPLR2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
36154. BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
36155. BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
36156. BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
36157. BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
36158. BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
36159. BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
36160. BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
36161. BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
36162. BIFPLR2_0_MSI_CAP_LIST__CAP_ID_MASK
36163. BIFPLR2_0_MSI_CAP_LIST__CAP_ID__SHIFT
36164. BIFPLR2_0_MSI_CAP_LIST__NEXT_PTR_MASK
36165. BIFPLR2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
36166. BIFPLR2_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
36167. BIFPLR2_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
36168. BIFPLR2_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
36169. BIFPLR2_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
36170. BIFPLR2_0_MSI_MAP_CAP_LIST__CAP_ID_MASK
36171. BIFPLR2_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
36172. BIFPLR2_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
36173. BIFPLR2_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
36174. BIFPLR2_0_MSI_MAP_CAP__CAP_TYPE_MASK
36175. BIFPLR2_0_MSI_MAP_CAP__CAP_TYPE__SHIFT
36176. BIFPLR2_0_MSI_MAP_CAP__EN_MASK
36177. BIFPLR2_0_MSI_MAP_CAP__EN__SHIFT
36178. BIFPLR2_0_MSI_MAP_CAP__FIXD_MASK
36179. BIFPLR2_0_MSI_MAP_CAP__FIXD__SHIFT
36180. BIFPLR2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
36181. BIFPLR2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
36182. BIFPLR2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
36183. BIFPLR2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
36184. BIFPLR2_0_MSI_MSG_CNTL__MSI_64BIT_MASK
36185. BIFPLR2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
36186. BIFPLR2_0_MSI_MSG_CNTL__MSI_EN_MASK
36187. BIFPLR2_0_MSI_MSG_CNTL__MSI_EN__SHIFT
36188. BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
36189. BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
36190. BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
36191. BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
36192. BIFPLR2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
36193. BIFPLR2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
36194. BIFPLR2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
36195. BIFPLR2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
36196. BIFPLR2_0_MSI_MSG_DATA__MSI_DATA_MASK
36197. BIFPLR2_0_MSI_MSG_DATA__MSI_DATA__SHIFT
36198. BIFPLR2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
36199. BIFPLR2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
36200. BIFPLR2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
36201. BIFPLR2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
36202. BIFPLR2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
36203. BIFPLR2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
36204. BIFPLR2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
36205. BIFPLR2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
36206. BIFPLR2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
36207. BIFPLR2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
36208. BIFPLR2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
36209. BIFPLR2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
36210. BIFPLR2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
36211. BIFPLR2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
36212. BIFPLR2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
36213. BIFPLR2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
36214. BIFPLR2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
36215. BIFPLR2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
36216. BIFPLR2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
36217. BIFPLR2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
36218. BIFPLR2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
36219. BIFPLR2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
36220. BIFPLR2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
36221. BIFPLR2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
36222. BIFPLR2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
36223. BIFPLR2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
36224. BIFPLR2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
36225. BIFPLR2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
36226. BIFPLR2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
36227. BIFPLR2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
36228. BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
36229. BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
36230. BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
36231. BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
36232. BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
36233. BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
36234. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
36235. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
36236. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
36237. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
36238. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
36239. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
36240. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
36241. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
36242. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
36243. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
36244. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
36245. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
36246. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
36247. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
36248. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
36249. BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
36250. BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
36251. BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
36252. BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
36253. BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
36254. BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
36255. BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
36256. BIFPLR2_0_PCIE_CAP_LIST__CAP_ID_MASK
36257. BIFPLR2_0_PCIE_CAP_LIST__CAP_ID__SHIFT
36258. BIFPLR2_0_PCIE_CAP_LIST__NEXT_PTR_MASK
36259. BIFPLR2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
36260. BIFPLR2_0_PCIE_CAP__DEVICE_TYPE_MASK
36261. BIFPLR2_0_PCIE_CAP__DEVICE_TYPE__SHIFT
36262. BIFPLR2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
36263. BIFPLR2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
36264. BIFPLR2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
36265. BIFPLR2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
36266. BIFPLR2_0_PCIE_CAP__VERSION_MASK
36267. BIFPLR2_0_PCIE_CAP__VERSION__SHIFT
36268. BIFPLR2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
36269. BIFPLR2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
36270. BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
36271. BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
36272. BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
36273. BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
36274. BIFPLR2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
36275. BIFPLR2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
36276. BIFPLR2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
36277. BIFPLR2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
36278. BIFPLR2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
36279. BIFPLR2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
36280. BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
36281. BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
36282. BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
36283. BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
36284. BIFPLR2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
36285. BIFPLR2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
36286. BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
36287. BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
36288. BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
36289. BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
36290. BIFPLR2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
36291. BIFPLR2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
36292. BIFPLR2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
36293. BIFPLR2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
36294. BIFPLR2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
36295. BIFPLR2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
36296. BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
36297. BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
36298. BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
36299. BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
36300. BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
36301. BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
36302. BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
36303. BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
36304. BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
36305. BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
36306. BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
36307. BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
36308. BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
36309. BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
36310. BIFPLR2_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
36311. BIFPLR2_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
36312. BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
36313. BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
36314. BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
36315. BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
36316. BIFPLR2_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
36317. BIFPLR2_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
36318. BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
36319. BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
36320. BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
36321. BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
36322. BIFPLR2_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
36323. BIFPLR2_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
36324. BIFPLR2_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
36325. BIFPLR2_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
36326. BIFPLR2_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
36327. BIFPLR2_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
36328. BIFPLR2_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
36329. BIFPLR2_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
36330. BIFPLR2_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
36331. BIFPLR2_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
36332. BIFPLR2_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
36333. BIFPLR2_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
36334. BIFPLR2_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
36335. BIFPLR2_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
36336. BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
36337. BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
36338. BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
36339. BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
36340. BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
36341. BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
36342. BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
36343. BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
36344. BIFPLR2_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
36345. BIFPLR2_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
36346. BIFPLR2_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
36347. BIFPLR2_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
36348. BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
36349. BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
36350. BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
36351. BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
36352. BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
36353. BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
36354. BIFPLR2_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
36355. BIFPLR2_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
36356. BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
36357. BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
36358. BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
36359. BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
36360. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK
36361. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
36362. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK
36363. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
36364. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK
36365. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
36366. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK
36367. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
36368. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK
36369. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
36370. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK
36371. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
36372. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK
36373. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
36374. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK
36375. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
36376. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK
36377. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
36378. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK
36379. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
36380. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK
36381. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
36382. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK
36383. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
36384. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK
36385. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
36386. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK
36387. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
36388. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK
36389. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
36390. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK
36391. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
36392. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK
36393. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
36394. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK
36395. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
36396. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK
36397. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
36398. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK
36399. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
36400. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK
36401. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
36402. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK
36403. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
36404. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK
36405. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
36406. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK
36407. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
36408. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK
36409. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
36410. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK
36411. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
36412. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK
36413. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
36414. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK
36415. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
36416. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK
36417. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
36418. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK
36419. BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
36420. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK
36421. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
36422. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK
36423. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
36424. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK
36425. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
36426. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK
36427. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
36428. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK
36429. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
36430. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK
36431. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
36432. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK
36433. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
36434. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK
36435. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
36436. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK
36437. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
36438. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK
36439. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
36440. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK
36441. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
36442. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK
36443. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
36444. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK
36445. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
36446. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK
36447. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
36448. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK
36449. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
36450. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK
36451. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
36452. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK
36453. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
36454. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK
36455. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
36456. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK
36457. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
36458. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK
36459. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
36460. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK
36461. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
36462. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK
36463. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
36464. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK
36465. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
36466. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK
36467. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
36468. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK
36469. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
36470. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK
36471. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
36472. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK
36473. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
36474. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK
36475. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
36476. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK
36477. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
36478. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK
36479. BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
36480. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK
36481. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
36482. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK
36483. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
36484. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK
36485. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
36486. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK
36487. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
36488. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK
36489. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
36490. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK
36491. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
36492. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK
36493. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
36494. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK
36495. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
36496. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK
36497. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
36498. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK
36499. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
36500. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK
36501. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
36502. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK
36503. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
36504. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK
36505. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
36506. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK
36507. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
36508. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK
36509. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
36510. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK
36511. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
36512. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK
36513. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
36514. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK
36515. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
36516. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK
36517. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
36518. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK
36519. BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
36520. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK
36521. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
36522. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK
36523. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
36524. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK
36525. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
36526. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK
36527. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
36528. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK
36529. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
36530. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK
36531. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
36532. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK
36533. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
36534. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK
36535. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
36536. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK
36537. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
36538. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK
36539. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
36540. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK
36541. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
36542. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK
36543. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
36544. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK
36545. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
36546. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK
36547. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
36548. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK
36549. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
36550. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK
36551. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
36552. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK
36553. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
36554. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK
36555. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
36556. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK
36557. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
36558. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK
36559. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
36560. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK
36561. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
36562. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK
36563. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
36564. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK
36565. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
36566. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK
36567. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
36568. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK
36569. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
36570. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK
36571. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
36572. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK
36573. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
36574. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK
36575. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
36576. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK
36577. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
36578. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK
36579. BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
36580. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK
36581. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
36582. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK
36583. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
36584. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK
36585. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
36586. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK
36587. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
36588. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK
36589. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
36590. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK
36591. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
36592. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK
36593. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
36594. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK
36595. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
36596. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK
36597. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
36598. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK
36599. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
36600. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK
36601. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
36602. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK
36603. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
36604. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK
36605. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
36606. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK
36607. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
36608. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK
36609. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
36610. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK
36611. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
36612. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK
36613. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
36614. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK
36615. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
36616. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK
36617. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
36618. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK
36619. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
36620. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK
36621. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
36622. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK
36623. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
36624. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK
36625. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
36626. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK
36627. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
36628. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK
36629. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
36630. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK
36631. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
36632. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK
36633. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
36634. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK
36635. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
36636. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK
36637. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
36638. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK
36639. BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
36640. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK
36641. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
36642. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK
36643. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
36644. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK
36645. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
36646. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK
36647. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
36648. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK
36649. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
36650. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK
36651. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
36652. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK
36653. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
36654. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK
36655. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
36656. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK
36657. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
36658. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK
36659. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
36660. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK
36661. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
36662. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK
36663. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
36664. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK
36665. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
36666. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK
36667. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
36668. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK
36669. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
36670. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK
36671. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
36672. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK
36673. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
36674. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK
36675. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
36676. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK
36677. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
36678. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK
36679. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
36680. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK
36681. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
36682. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK
36683. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
36684. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK
36685. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
36686. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK
36687. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
36688. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK
36689. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
36690. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK
36691. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
36692. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK
36693. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
36694. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK
36695. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
36696. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK
36697. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
36698. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK
36699. BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
36700. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK
36701. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
36702. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK
36703. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
36704. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK
36705. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
36706. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK
36707. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
36708. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK
36709. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
36710. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK
36711. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
36712. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK
36713. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
36714. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK
36715. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
36716. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK
36717. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
36718. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK
36719. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
36720. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK
36721. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
36722. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK
36723. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
36724. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK
36725. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
36726. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK
36727. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
36728. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK
36729. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
36730. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK
36731. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
36732. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK
36733. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
36734. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK
36735. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
36736. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK
36737. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
36738. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK
36739. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
36740. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK
36741. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
36742. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK
36743. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
36744. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK
36745. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
36746. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK
36747. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
36748. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK
36749. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
36750. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK
36751. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
36752. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK
36753. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
36754. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK
36755. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
36756. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK
36757. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
36758. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK
36759. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
36760. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK
36761. BIFPLR2_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
36762. BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK
36763. BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
36764. BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK
36765. BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
36766. BIFPLR2_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
36767. BIFPLR2_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
36768. BIFPLR2_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK
36769. BIFPLR2_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
36770. BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
36771. BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
36772. BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
36773. BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
36774. BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
36775. BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
36776. BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
36777. BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
36778. BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
36779. BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
36780. BIFPLR2_0_PCIE_ESM_HEADER_2__CAP_ID_MASK
36781. BIFPLR2_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
36782. BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
36783. BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
36784. BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
36785. BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
36786. BIFPLR2_0_PCIE_HDR_LOG0__TLP_HDR_MASK
36787. BIFPLR2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
36788. BIFPLR2_0_PCIE_HDR_LOG1__TLP_HDR_MASK
36789. BIFPLR2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
36790. BIFPLR2_0_PCIE_HDR_LOG2__TLP_HDR_MASK
36791. BIFPLR2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
36792. BIFPLR2_0_PCIE_HDR_LOG3__TLP_HDR_MASK
36793. BIFPLR2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
36794. BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
36795. BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
36796. BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
36797. BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
36798. BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
36799. BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
36800. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
36801. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
36802. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
36803. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
36804. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
36805. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
36806. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
36807. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
36808. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
36809. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
36810. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
36811. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
36812. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
36813. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
36814. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
36815. BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
36816. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
36817. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
36818. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
36819. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
36820. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
36821. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
36822. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
36823. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
36824. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
36825. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
36826. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
36827. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
36828. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
36829. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
36830. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
36831. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
36832. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
36833. BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
36834. BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36835. BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36836. BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36837. BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36838. BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36839. BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36840. BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36841. BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36842. BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36843. BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36844. BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36845. BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36846. BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36847. BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36848. BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36849. BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36850. BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36851. BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36852. BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36853. BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36854. BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36855. BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36856. BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36857. BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36858. BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36859. BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36860. BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36861. BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36862. BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36863. BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36864. BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36865. BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36866. BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36867. BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36868. BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36869. BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36870. BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36871. BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36872. BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36873. BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36874. BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36875. BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36876. BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36877. BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36878. BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36879. BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36880. BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36881. BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36882. BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36883. BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36884. BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36885. BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36886. BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36887. BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36888. BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36889. BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36890. BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36891. BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36892. BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36893. BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36894. BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36895. BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36896. BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36897. BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36898. BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36899. BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36900. BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36901. BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36902. BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36903. BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36904. BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36905. BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36906. BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36907. BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36908. BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36909. BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36910. BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36911. BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36912. BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36913. BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36914. BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36915. BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36916. BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36917. BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36918. BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36919. BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36920. BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36921. BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36922. BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36923. BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36924. BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36925. BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36926. BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36927. BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36928. BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36929. BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36930. BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36931. BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36932. BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36933. BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36934. BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36935. BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36936. BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36937. BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36938. BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36939. BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36940. BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36941. BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36942. BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36943. BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36944. BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36945. BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36946. BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36947. BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36948. BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36949. BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36950. BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36951. BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36952. BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36953. BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36954. BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
36955. BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
36956. BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
36957. BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
36958. BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
36959. BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
36960. BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
36961. BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
36962. BIFPLR2_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
36963. BIFPLR2_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
36964. BIFPLR2_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
36965. BIFPLR2_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
36966. BIFPLR2_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
36967. BIFPLR2_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
36968. BIFPLR2_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
36969. BIFPLR2_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
36970. BIFPLR2_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
36971. BIFPLR2_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
36972. BIFPLR2_0_PCIE_LINK_CNTL3__RESERVED_MASK
36973. BIFPLR2_0_PCIE_LINK_CNTL3__RESERVED__SHIFT
36974. BIFPLR2_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
36975. BIFPLR2_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
36976. BIFPLR2_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
36977. BIFPLR2_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
36978. BIFPLR2_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
36979. BIFPLR2_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
36980. BIFPLR2_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
36981. BIFPLR2_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
36982. BIFPLR2_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
36983. BIFPLR2_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
36984. BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
36985. BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
36986. BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
36987. BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
36988. BIFPLR2_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
36989. BIFPLR2_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
36990. BIFPLR2_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK
36991. BIFPLR2_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
36992. BIFPLR2_0_PCIE_MC_CNTL__MC_ENABLE_MASK
36993. BIFPLR2_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT
36994. BIFPLR2_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
36995. BIFPLR2_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
36996. BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
36997. BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
36998. BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
36999. BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
37000. BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
37001. BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
37002. BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
37003. BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
37004. BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
37005. BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
37006. BIFPLR2_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
37007. BIFPLR2_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
37008. BIFPLR2_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
37009. BIFPLR2_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
37010. BIFPLR2_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
37011. BIFPLR2_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
37012. BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
37013. BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
37014. BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
37015. BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
37016. BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
37017. BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
37018. BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
37019. BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
37020. BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
37021. BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
37022. BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
37023. BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
37024. BIFPLR2_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
37025. BIFPLR2_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
37026. BIFPLR2_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
37027. BIFPLR2_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
37028. BIFPLR2_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
37029. BIFPLR2_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
37030. BIFPLR2_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
37031. BIFPLR2_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
37032. BIFPLR2_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
37033. BIFPLR2_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
37034. BIFPLR2_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
37035. BIFPLR2_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
37036. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
37037. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
37038. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
37039. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
37040. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
37041. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
37042. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
37043. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
37044. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
37045. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
37046. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
37047. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
37048. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
37049. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
37050. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
37051. BIFPLR2_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
37052. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
37053. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
37054. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
37055. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
37056. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
37057. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
37058. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
37059. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
37060. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
37061. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
37062. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
37063. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
37064. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
37065. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
37066. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
37067. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
37068. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
37069. BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
37070. BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
37071. BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
37072. BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
37073. BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
37074. BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
37075. BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
37076. BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
37077. BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
37078. BIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
37079. BIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
37080. BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
37081. BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
37082. BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK
37083. BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
37084. BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
37085. BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
37086. BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
37087. BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
37088. BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CTO_MASK
37089. BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
37090. BIFPLR2_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
37091. BIFPLR2_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
37092. BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
37093. BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
37094. BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK
37095. BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
37096. BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
37097. BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
37098. BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
37099. BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
37100. BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
37101. BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
37102. BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
37103. BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
37104. BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
37105. BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
37106. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
37107. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
37108. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
37109. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
37110. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
37111. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
37112. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
37113. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
37114. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
37115. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
37116. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
37117. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
37118. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
37119. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
37120. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
37121. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
37122. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
37123. BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
37124. BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
37125. BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
37126. BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
37127. BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
37128. BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
37129. BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
37130. BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
37131. BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
37132. BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK
37133. BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
37134. BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
37135. BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
37136. BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
37137. BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
37138. BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
37139. BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
37140. BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
37141. BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
37142. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
37143. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
37144. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
37145. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
37146. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
37147. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
37148. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
37149. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
37150. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
37151. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
37152. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
37153. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
37154. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
37155. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
37156. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
37157. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
37158. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
37159. BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
37160. BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
37161. BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
37162. BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
37163. BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
37164. BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
37165. BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
37166. BIFPLR2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
37167. BIFPLR2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
37168. BIFPLR2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
37169. BIFPLR2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
37170. BIFPLR2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
37171. BIFPLR2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
37172. BIFPLR2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
37173. BIFPLR2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
37174. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
37175. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
37176. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
37177. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
37178. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
37179. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
37180. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
37181. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
37182. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
37183. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
37184. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
37185. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
37186. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
37187. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
37188. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
37189. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
37190. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
37191. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
37192. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
37193. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
37194. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
37195. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
37196. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
37197. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
37198. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
37199. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
37200. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
37201. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
37202. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
37203. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
37204. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
37205. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
37206. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
37207. BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
37208. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
37209. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
37210. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
37211. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
37212. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
37213. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
37214. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
37215. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
37216. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
37217. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
37218. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
37219. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
37220. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
37221. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
37222. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
37223. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
37224. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
37225. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
37226. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
37227. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
37228. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
37229. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
37230. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
37231. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
37232. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
37233. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
37234. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
37235. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
37236. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
37237. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
37238. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
37239. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
37240. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
37241. BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
37242. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
37243. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
37244. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
37245. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
37246. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
37247. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
37248. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
37249. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
37250. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
37251. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
37252. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
37253. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
37254. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
37255. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
37256. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
37257. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
37258. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
37259. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
37260. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
37261. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
37262. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
37263. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
37264. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
37265. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
37266. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
37267. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
37268. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
37269. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
37270. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
37271. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
37272. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
37273. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
37274. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
37275. BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
37276. BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
37277. BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
37278. BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
37279. BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
37280. BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
37281. BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
37282. BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
37283. BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
37284. BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
37285. BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
37286. BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
37287. BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
37288. BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
37289. BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
37290. BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
37291. BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
37292. BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
37293. BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
37294. BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
37295. BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
37296. BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
37297. BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
37298. BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
37299. BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
37300. BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
37301. BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
37302. BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
37303. BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
37304. BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
37305. BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
37306. BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
37307. BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
37308. BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
37309. BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
37310. BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
37311. BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
37312. BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
37313. BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
37314. BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
37315. BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
37316. BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
37317. BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
37318. BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
37319. BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
37320. BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
37321. BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
37322. BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
37323. BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
37324. BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
37325. BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
37326. BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
37327. BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
37328. BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
37329. BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
37330. BIFPLR2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
37331. BIFPLR2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
37332. BIFPLR2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
37333. BIFPLR2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
37334. BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
37335. BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
37336. BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
37337. BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
37338. BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
37339. BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
37340. BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
37341. BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
37342. BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
37343. BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
37344. BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
37345. BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
37346. BIFPLR2_0_PMI_CAP_LIST__CAP_ID_MASK
37347. BIFPLR2_0_PMI_CAP_LIST__CAP_ID__SHIFT
37348. BIFPLR2_0_PMI_CAP_LIST__NEXT_PTR_MASK
37349. BIFPLR2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
37350. BIFPLR2_0_PMI_CAP__AUX_CURRENT_MASK
37351. BIFPLR2_0_PMI_CAP__AUX_CURRENT__SHIFT
37352. BIFPLR2_0_PMI_CAP__D1_SUPPORT_MASK
37353. BIFPLR2_0_PMI_CAP__D1_SUPPORT__SHIFT
37354. BIFPLR2_0_PMI_CAP__D2_SUPPORT_MASK
37355. BIFPLR2_0_PMI_CAP__D2_SUPPORT__SHIFT
37356. BIFPLR2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
37357. BIFPLR2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
37358. BIFPLR2_0_PMI_CAP__PME_CLOCK_MASK
37359. BIFPLR2_0_PMI_CAP__PME_CLOCK__SHIFT
37360. BIFPLR2_0_PMI_CAP__PME_SUPPORT_MASK
37361. BIFPLR2_0_PMI_CAP__PME_SUPPORT__SHIFT
37362. BIFPLR2_0_PMI_CAP__VERSION_MASK
37363. BIFPLR2_0_PMI_CAP__VERSION__SHIFT
37364. BIFPLR2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
37365. BIFPLR2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
37366. BIFPLR2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
37367. BIFPLR2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
37368. BIFPLR2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
37369. BIFPLR2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
37370. BIFPLR2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
37371. BIFPLR2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
37372. BIFPLR2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
37373. BIFPLR2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
37374. BIFPLR2_0_PMI_STATUS_CNTL__PME_EN_MASK
37375. BIFPLR2_0_PMI_STATUS_CNTL__PME_EN__SHIFT
37376. BIFPLR2_0_PMI_STATUS_CNTL__PME_STATUS_MASK
37377. BIFPLR2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
37378. BIFPLR2_0_PMI_STATUS_CNTL__PMI_DATA_MASK
37379. BIFPLR2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
37380. BIFPLR2_0_PMI_STATUS_CNTL__POWER_STATE_MASK
37381. BIFPLR2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
37382. BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
37383. BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
37384. BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
37385. BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
37386. BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
37387. BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
37388. BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
37389. BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
37390. BIFPLR2_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
37391. BIFPLR2_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
37392. BIFPLR2_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
37393. BIFPLR2_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
37394. BIFPLR2_0_PROG_INTERFACE__PROG_INTERFACE_MASK
37395. BIFPLR2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
37396. BIFPLR2_0_REVISION_ID__MAJOR_REV_ID_MASK
37397. BIFPLR2_0_REVISION_ID__MAJOR_REV_ID__SHIFT
37398. BIFPLR2_0_REVISION_ID__MINOR_REV_ID_MASK
37399. BIFPLR2_0_REVISION_ID__MINOR_REV_ID__SHIFT
37400. BIFPLR2_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
37401. BIFPLR2_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
37402. BIFPLR2_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
37403. BIFPLR2_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
37404. BIFPLR2_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK
37405. BIFPLR2_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
37406. BIFPLR2_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
37407. BIFPLR2_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
37408. BIFPLR2_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
37409. BIFPLR2_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
37410. BIFPLR2_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
37411. BIFPLR2_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
37412. BIFPLR2_0_ROOT_STATUS__PME_PENDING_MASK
37413. BIFPLR2_0_ROOT_STATUS__PME_PENDING__SHIFT
37414. BIFPLR2_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK
37415. BIFPLR2_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
37416. BIFPLR2_0_ROOT_STATUS__PME_STATUS_MASK
37417. BIFPLR2_0_ROOT_STATUS__PME_STATUS__SHIFT
37418. BIFPLR2_0_SECONDARY_STATUS__CAP_LIST_MASK
37419. BIFPLR2_0_SECONDARY_STATUS__CAP_LIST__SHIFT
37420. BIFPLR2_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK
37421. BIFPLR2_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
37422. BIFPLR2_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
37423. BIFPLR2_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
37424. BIFPLR2_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
37425. BIFPLR2_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
37426. BIFPLR2_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
37427. BIFPLR2_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
37428. BIFPLR2_0_SECONDARY_STATUS__PCI_66_EN_MASK
37429. BIFPLR2_0_SECONDARY_STATUS__PCI_66_EN__SHIFT
37430. BIFPLR2_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
37431. BIFPLR2_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
37432. BIFPLR2_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
37433. BIFPLR2_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
37434. BIFPLR2_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
37435. BIFPLR2_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
37436. BIFPLR2_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
37437. BIFPLR2_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
37438. BIFPLR2_0_SLOT_CAP2__RESERVED_MASK
37439. BIFPLR2_0_SLOT_CAP2__RESERVED__SHIFT
37440. BIFPLR2_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
37441. BIFPLR2_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
37442. BIFPLR2_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
37443. BIFPLR2_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
37444. BIFPLR2_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
37445. BIFPLR2_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
37446. BIFPLR2_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK
37447. BIFPLR2_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
37448. BIFPLR2_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK
37449. BIFPLR2_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
37450. BIFPLR2_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
37451. BIFPLR2_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
37452. BIFPLR2_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
37453. BIFPLR2_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
37454. BIFPLR2_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
37455. BIFPLR2_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
37456. BIFPLR2_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
37457. BIFPLR2_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
37458. BIFPLR2_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
37459. BIFPLR2_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
37460. BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
37461. BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
37462. BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
37463. BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
37464. BIFPLR2_0_SLOT_CNTL2__RESERVED_MASK
37465. BIFPLR2_0_SLOT_CNTL2__RESERVED__SHIFT
37466. BIFPLR2_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
37467. BIFPLR2_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
37468. BIFPLR2_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
37469. BIFPLR2_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
37470. BIFPLR2_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
37471. BIFPLR2_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
37472. BIFPLR2_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
37473. BIFPLR2_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
37474. BIFPLR2_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
37475. BIFPLR2_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
37476. BIFPLR2_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
37477. BIFPLR2_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
37478. BIFPLR2_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
37479. BIFPLR2_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
37480. BIFPLR2_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
37481. BIFPLR2_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
37482. BIFPLR2_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
37483. BIFPLR2_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
37484. BIFPLR2_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
37485. BIFPLR2_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
37486. BIFPLR2_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
37487. BIFPLR2_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
37488. BIFPLR2_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
37489. BIFPLR2_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
37490. BIFPLR2_0_SLOT_STATUS2__RESERVED_MASK
37491. BIFPLR2_0_SLOT_STATUS2__RESERVED__SHIFT
37492. BIFPLR2_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
37493. BIFPLR2_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
37494. BIFPLR2_0_SLOT_STATUS__COMMAND_COMPLETED_MASK
37495. BIFPLR2_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
37496. BIFPLR2_0_SLOT_STATUS__DL_STATE_CHANGED_MASK
37497. BIFPLR2_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
37498. BIFPLR2_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
37499. BIFPLR2_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
37500. BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
37501. BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
37502. BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK
37503. BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
37504. BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
37505. BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
37506. BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
37507. BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
37508. BIFPLR2_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
37509. BIFPLR2_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
37510. BIFPLR2_0_SSID_CAP_LIST__CAP_ID_MASK
37511. BIFPLR2_0_SSID_CAP_LIST__CAP_ID__SHIFT
37512. BIFPLR2_0_SSID_CAP_LIST__NEXT_PTR_MASK
37513. BIFPLR2_0_SSID_CAP_LIST__NEXT_PTR__SHIFT
37514. BIFPLR2_0_SSID_CAP__SUBSYSTEM_ID_MASK
37515. BIFPLR2_0_SSID_CAP__SUBSYSTEM_ID__SHIFT
37516. BIFPLR2_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
37517. BIFPLR2_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
37518. BIFPLR2_0_STATUS__CAP_LIST_MASK
37519. BIFPLR2_0_STATUS__CAP_LIST__SHIFT
37520. BIFPLR2_0_STATUS__DEVSEL_TIMING_MASK
37521. BIFPLR2_0_STATUS__DEVSEL_TIMING__SHIFT
37522. BIFPLR2_0_STATUS__FAST_BACK_CAPABLE_MASK
37523. BIFPLR2_0_STATUS__FAST_BACK_CAPABLE__SHIFT
37524. BIFPLR2_0_STATUS__INT_STATUS_MASK
37525. BIFPLR2_0_STATUS__INT_STATUS__SHIFT
37526. BIFPLR2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
37527. BIFPLR2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
37528. BIFPLR2_0_STATUS__PARITY_ERROR_DETECTED_MASK
37529. BIFPLR2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
37530. BIFPLR2_0_STATUS__PCI_66_EN_MASK
37531. BIFPLR2_0_STATUS__PCI_66_EN__SHIFT
37532. BIFPLR2_0_STATUS__RECEIVED_MASTER_ABORT_MASK
37533. BIFPLR2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
37534. BIFPLR2_0_STATUS__RECEIVED_TARGET_ABORT_MASK
37535. BIFPLR2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
37536. BIFPLR2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
37537. BIFPLR2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
37538. BIFPLR2_0_STATUS__SIGNAL_TARGET_ABORT_MASK
37539. BIFPLR2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
37540. BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
37541. BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
37542. BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
37543. BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
37544. BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
37545. BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
37546. BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
37547. BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
37548. BIFPLR2_0_SUB_CLASS__SUB_CLASS_MASK
37549. BIFPLR2_0_SUB_CLASS__SUB_CLASS__SHIFT
37550. BIFPLR2_0_VENDOR_ID__VENDOR_ID_MASK
37551. BIFPLR2_0_VENDOR_ID__VENDOR_ID__SHIFT
37552. BIFPLR2_1_BASE_CLASS__BASE_CLASS_MASK
37553. BIFPLR2_1_BASE_CLASS__BASE_CLASS__SHIFT
37554. BIFPLR2_1_BIST__BIST_CAP_MASK
37555. BIFPLR2_1_BIST__BIST_CAP__SHIFT
37556. BIFPLR2_1_BIST__BIST_COMP_MASK
37557. BIFPLR2_1_BIST__BIST_COMP__SHIFT
37558. BIFPLR2_1_BIST__BIST_STRT_MASK
37559. BIFPLR2_1_BIST__BIST_STRT__SHIFT
37560. BIFPLR2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
37561. BIFPLR2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
37562. BIFPLR2_1_CAP_PTR__CAP_PTR_MASK
37563. BIFPLR2_1_CAP_PTR__CAP_PTR__SHIFT
37564. BIFPLR2_1_COMMAND__AD_STEPPING_MASK
37565. BIFPLR2_1_COMMAND__AD_STEPPING__SHIFT
37566. BIFPLR2_1_COMMAND__BUS_MASTER_EN_MASK
37567. BIFPLR2_1_COMMAND__BUS_MASTER_EN__SHIFT
37568. BIFPLR2_1_COMMAND__FAST_B2B_EN_MASK
37569. BIFPLR2_1_COMMAND__FAST_B2B_EN__SHIFT
37570. BIFPLR2_1_COMMAND__INT_DIS_MASK
37571. BIFPLR2_1_COMMAND__INT_DIS__SHIFT
37572. BIFPLR2_1_COMMAND__IO_ACCESS_EN_MASK
37573. BIFPLR2_1_COMMAND__IO_ACCESS_EN__SHIFT
37574. BIFPLR2_1_COMMAND__MEM_ACCESS_EN_MASK
37575. BIFPLR2_1_COMMAND__MEM_ACCESS_EN__SHIFT
37576. BIFPLR2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
37577. BIFPLR2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
37578. BIFPLR2_1_COMMAND__PAL_SNOOP_EN_MASK
37579. BIFPLR2_1_COMMAND__PAL_SNOOP_EN__SHIFT
37580. BIFPLR2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
37581. BIFPLR2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
37582. BIFPLR2_1_COMMAND__SERR_EN_MASK
37583. BIFPLR2_1_COMMAND__SERR_EN__SHIFT
37584. BIFPLR2_1_COMMAND__SPECIAL_CYCLE_EN_MASK
37585. BIFPLR2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
37586. BIFPLR2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
37587. BIFPLR2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
37588. BIFPLR2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
37589. BIFPLR2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
37590. BIFPLR2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
37591. BIFPLR2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
37592. BIFPLR2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
37593. BIFPLR2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
37594. BIFPLR2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
37595. BIFPLR2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
37596. BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
37597. BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
37598. BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
37599. BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
37600. BIFPLR2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
37601. BIFPLR2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
37602. BIFPLR2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
37603. BIFPLR2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
37604. BIFPLR2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
37605. BIFPLR2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
37606. BIFPLR2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
37607. BIFPLR2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
37608. BIFPLR2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
37609. BIFPLR2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
37610. BIFPLR2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
37611. BIFPLR2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
37612. BIFPLR2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
37613. BIFPLR2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
37614. BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
37615. BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
37616. BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
37617. BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
37618. BIFPLR2_1_DEVICE_CAP__EXTENDED_TAG_MASK
37619. BIFPLR2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
37620. BIFPLR2_1_DEVICE_CAP__FLR_CAPABLE_MASK
37621. BIFPLR2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
37622. BIFPLR2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
37623. BIFPLR2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
37624. BIFPLR2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
37625. BIFPLR2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
37626. BIFPLR2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
37627. BIFPLR2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
37628. BIFPLR2_1_DEVICE_CAP__PHANTOM_FUNC_MASK
37629. BIFPLR2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
37630. BIFPLR2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
37631. BIFPLR2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
37632. BIFPLR2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
37633. BIFPLR2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
37634. BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
37635. BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
37636. BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
37637. BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
37638. BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
37639. BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
37640. BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
37641. BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
37642. BIFPLR2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
37643. BIFPLR2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
37644. BIFPLR2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
37645. BIFPLR2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
37646. BIFPLR2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
37647. BIFPLR2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
37648. BIFPLR2_1_DEVICE_CNTL2__LTR_EN_MASK
37649. BIFPLR2_1_DEVICE_CNTL2__LTR_EN__SHIFT
37650. BIFPLR2_1_DEVICE_CNTL2__OBFF_EN_MASK
37651. BIFPLR2_1_DEVICE_CNTL2__OBFF_EN__SHIFT
37652. BIFPLR2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
37653. BIFPLR2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
37654. BIFPLR2_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
37655. BIFPLR2_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
37656. BIFPLR2_1_DEVICE_CNTL__CORR_ERR_EN_MASK
37657. BIFPLR2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
37658. BIFPLR2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
37659. BIFPLR2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
37660. BIFPLR2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
37661. BIFPLR2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
37662. BIFPLR2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
37663. BIFPLR2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
37664. BIFPLR2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
37665. BIFPLR2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
37666. BIFPLR2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
37667. BIFPLR2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
37668. BIFPLR2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
37669. BIFPLR2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
37670. BIFPLR2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
37671. BIFPLR2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
37672. BIFPLR2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
37673. BIFPLR2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
37674. BIFPLR2_1_DEVICE_CNTL__USR_REPORT_EN_MASK
37675. BIFPLR2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
37676. BIFPLR2_1_DEVICE_ID__DEVICE_ID_MASK
37677. BIFPLR2_1_DEVICE_ID__DEVICE_ID__SHIFT
37678. BIFPLR2_1_DEVICE_STATUS2__RESERVED_MASK
37679. BIFPLR2_1_DEVICE_STATUS2__RESERVED__SHIFT
37680. BIFPLR2_1_DEVICE_STATUS__AUX_PWR_MASK
37681. BIFPLR2_1_DEVICE_STATUS__AUX_PWR__SHIFT
37682. BIFPLR2_1_DEVICE_STATUS__CORR_ERR_MASK
37683. BIFPLR2_1_DEVICE_STATUS__CORR_ERR__SHIFT
37684. BIFPLR2_1_DEVICE_STATUS__FATAL_ERR_MASK
37685. BIFPLR2_1_DEVICE_STATUS__FATAL_ERR__SHIFT
37686. BIFPLR2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
37687. BIFPLR2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
37688. BIFPLR2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
37689. BIFPLR2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
37690. BIFPLR2_1_DEVICE_STATUS__USR_DETECTED_MASK
37691. BIFPLR2_1_DEVICE_STATUS__USR_DETECTED__SHIFT
37692. BIFPLR2_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
37693. BIFPLR2_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
37694. BIFPLR2_1_HEADER__DEVICE_TYPE_MASK
37695. BIFPLR2_1_HEADER__DEVICE_TYPE__SHIFT
37696. BIFPLR2_1_HEADER__HEADER_TYPE_MASK
37697. BIFPLR2_1_HEADER__HEADER_TYPE__SHIFT
37698. BIFPLR2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
37699. BIFPLR2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
37700. BIFPLR2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
37701. BIFPLR2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
37702. BIFPLR2_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
37703. BIFPLR2_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
37704. BIFPLR2_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
37705. BIFPLR2_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
37706. BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_MASK
37707. BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
37708. BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
37709. BIFPLR2_1_IO_BASE_LIMIT__IO_BASE__SHIFT
37710. BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_MASK
37711. BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
37712. BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
37713. BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT
37714. BIFPLR2_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
37715. BIFPLR2_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
37716. BIFPLR2_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK
37717. BIFPLR2_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
37718. BIFPLR2_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
37719. BIFPLR2_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
37720. BIFPLR2_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
37721. BIFPLR2_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
37722. BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
37723. BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
37724. BIFPLR2_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK
37725. BIFPLR2_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
37726. BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
37727. BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
37728. BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK
37729. BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
37730. BIFPLR2_1_LATENCY__LATENCY_TIMER_MASK
37731. BIFPLR2_1_LATENCY__LATENCY_TIMER__SHIFT
37732. BIFPLR2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
37733. BIFPLR2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
37734. BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
37735. BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
37736. BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
37737. BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
37738. BIFPLR2_1_LINK_CAP2__RESERVED_MASK
37739. BIFPLR2_1_LINK_CAP2__RESERVED__SHIFT
37740. BIFPLR2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
37741. BIFPLR2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
37742. BIFPLR2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
37743. BIFPLR2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
37744. BIFPLR2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
37745. BIFPLR2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
37746. BIFPLR2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
37747. BIFPLR2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
37748. BIFPLR2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
37749. BIFPLR2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
37750. BIFPLR2_1_LINK_CAP__L1_EXIT_LATENCY_MASK
37751. BIFPLR2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
37752. BIFPLR2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
37753. BIFPLR2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
37754. BIFPLR2_1_LINK_CAP__LINK_SPEED_MASK
37755. BIFPLR2_1_LINK_CAP__LINK_SPEED__SHIFT
37756. BIFPLR2_1_LINK_CAP__LINK_WIDTH_MASK
37757. BIFPLR2_1_LINK_CAP__LINK_WIDTH__SHIFT
37758. BIFPLR2_1_LINK_CAP__PM_SUPPORT_MASK
37759. BIFPLR2_1_LINK_CAP__PM_SUPPORT__SHIFT
37760. BIFPLR2_1_LINK_CAP__PORT_NUMBER_MASK
37761. BIFPLR2_1_LINK_CAP__PORT_NUMBER__SHIFT
37762. BIFPLR2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
37763. BIFPLR2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
37764. BIFPLR2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
37765. BIFPLR2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
37766. BIFPLR2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
37767. BIFPLR2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
37768. BIFPLR2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
37769. BIFPLR2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
37770. BIFPLR2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
37771. BIFPLR2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
37772. BIFPLR2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
37773. BIFPLR2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
37774. BIFPLR2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
37775. BIFPLR2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
37776. BIFPLR2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
37777. BIFPLR2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
37778. BIFPLR2_1_LINK_CNTL2__XMIT_MARGIN_MASK
37779. BIFPLR2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
37780. BIFPLR2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
37781. BIFPLR2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
37782. BIFPLR2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
37783. BIFPLR2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
37784. BIFPLR2_1_LINK_CNTL__EXTENDED_SYNC_MASK
37785. BIFPLR2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
37786. BIFPLR2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
37787. BIFPLR2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
37788. BIFPLR2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
37789. BIFPLR2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
37790. BIFPLR2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
37791. BIFPLR2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
37792. BIFPLR2_1_LINK_CNTL__LINK_DIS_MASK
37793. BIFPLR2_1_LINK_CNTL__LINK_DIS__SHIFT
37794. BIFPLR2_1_LINK_CNTL__PM_CONTROL_MASK
37795. BIFPLR2_1_LINK_CNTL__PM_CONTROL__SHIFT
37796. BIFPLR2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
37797. BIFPLR2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
37798. BIFPLR2_1_LINK_CNTL__RETRAIN_LINK_MASK
37799. BIFPLR2_1_LINK_CNTL__RETRAIN_LINK__SHIFT
37800. BIFPLR2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
37801. BIFPLR2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
37802. BIFPLR2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
37803. BIFPLR2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
37804. BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
37805. BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
37806. BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
37807. BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
37808. BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
37809. BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
37810. BIFPLR2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
37811. BIFPLR2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
37812. BIFPLR2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
37813. BIFPLR2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
37814. BIFPLR2_1_LINK_STATUS__DL_ACTIVE_MASK
37815. BIFPLR2_1_LINK_STATUS__DL_ACTIVE__SHIFT
37816. BIFPLR2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
37817. BIFPLR2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
37818. BIFPLR2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
37819. BIFPLR2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
37820. BIFPLR2_1_LINK_STATUS__LINK_TRAINING_MASK
37821. BIFPLR2_1_LINK_STATUS__LINK_TRAINING__SHIFT
37822. BIFPLR2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
37823. BIFPLR2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
37824. BIFPLR2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
37825. BIFPLR2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
37826. BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
37827. BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
37828. BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
37829. BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
37830. BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
37831. BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
37832. BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
37833. BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
37834. BIFPLR2_1_MSI_CAP_LIST__CAP_ID_MASK
37835. BIFPLR2_1_MSI_CAP_LIST__CAP_ID__SHIFT
37836. BIFPLR2_1_MSI_CAP_LIST__NEXT_PTR_MASK
37837. BIFPLR2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
37838. BIFPLR2_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
37839. BIFPLR2_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
37840. BIFPLR2_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
37841. BIFPLR2_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
37842. BIFPLR2_1_MSI_MAP_CAP_LIST__CAP_ID_MASK
37843. BIFPLR2_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
37844. BIFPLR2_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
37845. BIFPLR2_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
37846. BIFPLR2_1_MSI_MAP_CAP__CAP_TYPE_MASK
37847. BIFPLR2_1_MSI_MAP_CAP__CAP_TYPE__SHIFT
37848. BIFPLR2_1_MSI_MAP_CAP__EN_MASK
37849. BIFPLR2_1_MSI_MAP_CAP__EN__SHIFT
37850. BIFPLR2_1_MSI_MAP_CAP__FIXD_MASK
37851. BIFPLR2_1_MSI_MAP_CAP__FIXD__SHIFT
37852. BIFPLR2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
37853. BIFPLR2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
37854. BIFPLR2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
37855. BIFPLR2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
37856. BIFPLR2_1_MSI_MSG_CNTL__MSI_64BIT_MASK
37857. BIFPLR2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
37858. BIFPLR2_1_MSI_MSG_CNTL__MSI_EN_MASK
37859. BIFPLR2_1_MSI_MSG_CNTL__MSI_EN__SHIFT
37860. BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
37861. BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
37862. BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
37863. BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
37864. BIFPLR2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
37865. BIFPLR2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
37866. BIFPLR2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
37867. BIFPLR2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
37868. BIFPLR2_1_MSI_MSG_DATA__MSI_DATA_MASK
37869. BIFPLR2_1_MSI_MSG_DATA__MSI_DATA__SHIFT
37870. BIFPLR2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
37871. BIFPLR2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
37872. BIFPLR2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
37873. BIFPLR2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
37874. BIFPLR2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
37875. BIFPLR2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
37876. BIFPLR2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
37877. BIFPLR2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
37878. BIFPLR2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
37879. BIFPLR2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
37880. BIFPLR2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
37881. BIFPLR2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
37882. BIFPLR2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
37883. BIFPLR2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
37884. BIFPLR2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
37885. BIFPLR2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
37886. BIFPLR2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
37887. BIFPLR2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
37888. BIFPLR2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
37889. BIFPLR2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
37890. BIFPLR2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
37891. BIFPLR2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
37892. BIFPLR2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
37893. BIFPLR2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
37894. BIFPLR2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
37895. BIFPLR2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
37896. BIFPLR2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
37897. BIFPLR2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
37898. BIFPLR2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
37899. BIFPLR2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
37900. BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
37901. BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
37902. BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
37903. BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
37904. BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
37905. BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
37906. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
37907. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
37908. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
37909. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
37910. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
37911. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
37912. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
37913. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
37914. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
37915. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
37916. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
37917. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
37918. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
37919. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
37920. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
37921. BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
37922. BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
37923. BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
37924. BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
37925. BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
37926. BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
37927. BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
37928. BIFPLR2_1_PCIE_CAP_LIST__CAP_ID_MASK
37929. BIFPLR2_1_PCIE_CAP_LIST__CAP_ID__SHIFT
37930. BIFPLR2_1_PCIE_CAP_LIST__NEXT_PTR_MASK
37931. BIFPLR2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
37932. BIFPLR2_1_PCIE_CAP__DEVICE_TYPE_MASK
37933. BIFPLR2_1_PCIE_CAP__DEVICE_TYPE__SHIFT
37934. BIFPLR2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
37935. BIFPLR2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
37936. BIFPLR2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
37937. BIFPLR2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
37938. BIFPLR2_1_PCIE_CAP__VERSION_MASK
37939. BIFPLR2_1_PCIE_CAP__VERSION__SHIFT
37940. BIFPLR2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
37941. BIFPLR2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
37942. BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
37943. BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
37944. BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
37945. BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
37946. BIFPLR2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
37947. BIFPLR2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
37948. BIFPLR2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
37949. BIFPLR2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
37950. BIFPLR2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
37951. BIFPLR2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
37952. BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
37953. BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
37954. BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
37955. BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
37956. BIFPLR2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
37957. BIFPLR2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
37958. BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
37959. BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
37960. BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
37961. BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
37962. BIFPLR2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
37963. BIFPLR2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
37964. BIFPLR2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
37965. BIFPLR2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
37966. BIFPLR2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
37967. BIFPLR2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
37968. BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
37969. BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
37970. BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
37971. BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
37972. BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
37973. BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
37974. BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
37975. BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
37976. BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
37977. BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
37978. BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
37979. BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
37980. BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
37981. BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
37982. BIFPLR2_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
37983. BIFPLR2_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
37984. BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
37985. BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
37986. BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
37987. BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
37988. BIFPLR2_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
37989. BIFPLR2_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
37990. BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
37991. BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
37992. BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
37993. BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
37994. BIFPLR2_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
37995. BIFPLR2_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
37996. BIFPLR2_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
37997. BIFPLR2_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
37998. BIFPLR2_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
37999. BIFPLR2_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
38000. BIFPLR2_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
38001. BIFPLR2_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
38002. BIFPLR2_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
38003. BIFPLR2_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
38004. BIFPLR2_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
38005. BIFPLR2_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
38006. BIFPLR2_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
38007. BIFPLR2_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
38008. BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
38009. BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
38010. BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
38011. BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
38012. BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
38013. BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
38014. BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
38015. BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
38016. BIFPLR2_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
38017. BIFPLR2_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
38018. BIFPLR2_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
38019. BIFPLR2_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
38020. BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
38021. BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
38022. BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
38023. BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
38024. BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
38025. BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
38026. BIFPLR2_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
38027. BIFPLR2_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
38028. BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
38029. BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
38030. BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
38031. BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
38032. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK
38033. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
38034. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK
38035. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
38036. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK
38037. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
38038. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK
38039. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
38040. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK
38041. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
38042. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK
38043. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
38044. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK
38045. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
38046. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK
38047. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
38048. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK
38049. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
38050. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK
38051. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
38052. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK
38053. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
38054. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK
38055. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
38056. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK
38057. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
38058. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK
38059. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
38060. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK
38061. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
38062. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK
38063. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
38064. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK
38065. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
38066. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK
38067. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
38068. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK
38069. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
38070. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK
38071. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
38072. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK
38073. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
38074. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK
38075. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
38076. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK
38077. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
38078. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK
38079. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
38080. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK
38081. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
38082. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK
38083. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
38084. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK
38085. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
38086. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK
38087. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
38088. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK
38089. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
38090. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK
38091. BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
38092. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK
38093. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
38094. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK
38095. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
38096. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK
38097. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
38098. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK
38099. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
38100. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK
38101. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
38102. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK
38103. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
38104. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK
38105. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
38106. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK
38107. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
38108. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK
38109. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
38110. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK
38111. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
38112. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK
38113. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
38114. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK
38115. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
38116. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK
38117. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
38118. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK
38119. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
38120. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK
38121. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
38122. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK
38123. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
38124. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK
38125. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
38126. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK
38127. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
38128. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK
38129. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
38130. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK
38131. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
38132. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK
38133. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
38134. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK
38135. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
38136. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK
38137. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
38138. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK
38139. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
38140. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK
38141. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
38142. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK
38143. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
38144. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK
38145. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
38146. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK
38147. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
38148. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK
38149. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
38150. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK
38151. BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
38152. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK
38153. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
38154. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK
38155. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
38156. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK
38157. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
38158. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK
38159. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
38160. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK
38161. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
38162. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK
38163. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
38164. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK
38165. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
38166. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK
38167. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
38168. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK
38169. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
38170. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK
38171. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
38172. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK
38173. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
38174. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK
38175. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
38176. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK
38177. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
38178. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK
38179. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
38180. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK
38181. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
38182. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK
38183. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
38184. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK
38185. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
38186. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK
38187. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
38188. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK
38189. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
38190. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK
38191. BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
38192. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK
38193. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
38194. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK
38195. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
38196. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK
38197. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
38198. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK
38199. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
38200. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK
38201. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
38202. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK
38203. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
38204. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK
38205. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
38206. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK
38207. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
38208. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK
38209. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
38210. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK
38211. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
38212. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK
38213. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
38214. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK
38215. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
38216. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK
38217. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
38218. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK
38219. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
38220. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK
38221. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
38222. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK
38223. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
38224. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK
38225. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
38226. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK
38227. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
38228. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK
38229. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
38230. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK
38231. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
38232. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK
38233. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
38234. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK
38235. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
38236. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK
38237. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
38238. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK
38239. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
38240. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK
38241. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
38242. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK
38243. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
38244. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK
38245. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
38246. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK
38247. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
38248. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK
38249. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
38250. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK
38251. BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
38252. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK
38253. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
38254. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK
38255. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
38256. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK
38257. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
38258. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK
38259. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
38260. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK
38261. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
38262. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK
38263. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
38264. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK
38265. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
38266. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK
38267. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
38268. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK
38269. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
38270. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK
38271. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
38272. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK
38273. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
38274. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK
38275. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
38276. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK
38277. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
38278. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK
38279. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
38280. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK
38281. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
38282. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK
38283. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
38284. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK
38285. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
38286. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK
38287. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
38288. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK
38289. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
38290. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK
38291. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
38292. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK
38293. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
38294. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK
38295. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
38296. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK
38297. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
38298. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK
38299. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
38300. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK
38301. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
38302. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK
38303. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
38304. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK
38305. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
38306. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK
38307. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
38308. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK
38309. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
38310. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK
38311. BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
38312. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK
38313. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
38314. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK
38315. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
38316. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK
38317. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
38318. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK
38319. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
38320. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK
38321. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
38322. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK
38323. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
38324. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK
38325. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
38326. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK
38327. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
38328. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK
38329. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
38330. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK
38331. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
38332. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK
38333. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
38334. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK
38335. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
38336. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK
38337. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
38338. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK
38339. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
38340. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK
38341. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
38342. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK
38343. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
38344. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK
38345. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
38346. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK
38347. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
38348. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK
38349. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
38350. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK
38351. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
38352. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK
38353. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
38354. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK
38355. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
38356. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK
38357. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
38358. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK
38359. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
38360. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK
38361. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
38362. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK
38363. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
38364. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK
38365. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
38366. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK
38367. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
38368. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK
38369. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
38370. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK
38371. BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
38372. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK
38373. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
38374. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK
38375. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
38376. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK
38377. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
38378. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK
38379. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
38380. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK
38381. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
38382. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK
38383. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
38384. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK
38385. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
38386. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK
38387. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
38388. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK
38389. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
38390. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK
38391. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
38392. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK
38393. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
38394. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK
38395. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
38396. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK
38397. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
38398. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK
38399. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
38400. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK
38401. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
38402. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK
38403. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
38404. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK
38405. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
38406. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK
38407. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
38408. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK
38409. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
38410. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK
38411. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
38412. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK
38413. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
38414. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK
38415. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
38416. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK
38417. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
38418. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK
38419. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
38420. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK
38421. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
38422. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK
38423. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
38424. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK
38425. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
38426. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK
38427. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
38428. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK
38429. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
38430. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK
38431. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
38432. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK
38433. BIFPLR2_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
38434. BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK
38435. BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
38436. BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK
38437. BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
38438. BIFPLR2_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
38439. BIFPLR2_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
38440. BIFPLR2_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK
38441. BIFPLR2_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
38442. BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
38443. BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
38444. BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
38445. BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
38446. BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
38447. BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
38448. BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
38449. BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
38450. BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
38451. BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
38452. BIFPLR2_1_PCIE_ESM_HEADER_2__CAP_ID_MASK
38453. BIFPLR2_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
38454. BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
38455. BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
38456. BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
38457. BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
38458. BIFPLR2_1_PCIE_HDR_LOG0__TLP_HDR_MASK
38459. BIFPLR2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
38460. BIFPLR2_1_PCIE_HDR_LOG1__TLP_HDR_MASK
38461. BIFPLR2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
38462. BIFPLR2_1_PCIE_HDR_LOG2__TLP_HDR_MASK
38463. BIFPLR2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
38464. BIFPLR2_1_PCIE_HDR_LOG3__TLP_HDR_MASK
38465. BIFPLR2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
38466. BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
38467. BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
38468. BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
38469. BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
38470. BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
38471. BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
38472. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
38473. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
38474. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
38475. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
38476. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
38477. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
38478. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
38479. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
38480. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
38481. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
38482. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
38483. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
38484. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
38485. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
38486. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
38487. BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
38488. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
38489. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
38490. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
38491. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
38492. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
38493. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
38494. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
38495. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
38496. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
38497. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
38498. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
38499. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
38500. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
38501. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
38502. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
38503. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
38504. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
38505. BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
38506. BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38507. BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38508. BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38509. BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38510. BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38511. BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38512. BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38513. BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38514. BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38515. BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38516. BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38517. BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38518. BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38519. BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38520. BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38521. BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38522. BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38523. BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38524. BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38525. BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38526. BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38527. BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38528. BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38529. BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38530. BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38531. BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38532. BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38533. BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38534. BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38535. BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38536. BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38537. BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38538. BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38539. BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38540. BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38541. BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38542. BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38543. BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38544. BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38545. BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38546. BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38547. BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38548. BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38549. BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38550. BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38551. BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38552. BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38553. BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38554. BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38555. BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38556. BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38557. BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38558. BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38559. BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38560. BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38561. BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38562. BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38563. BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38564. BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38565. BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38566. BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38567. BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38568. BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38569. BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38570. BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38571. BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38572. BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38573. BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38574. BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38575. BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38576. BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38577. BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38578. BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38579. BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38580. BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38581. BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38582. BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38583. BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38584. BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38585. BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38586. BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38587. BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38588. BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38589. BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38590. BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38591. BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38592. BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38593. BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38594. BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38595. BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38596. BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38597. BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38598. BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38599. BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38600. BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38601. BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38602. BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38603. BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38604. BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38605. BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38606. BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38607. BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38608. BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38609. BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38610. BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38611. BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38612. BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38613. BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38614. BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38615. BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38616. BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38617. BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38618. BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38619. BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38620. BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38621. BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38622. BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38623. BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38624. BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38625. BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38626. BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
38627. BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
38628. BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
38629. BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
38630. BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
38631. BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
38632. BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
38633. BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
38634. BIFPLR2_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
38635. BIFPLR2_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
38636. BIFPLR2_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
38637. BIFPLR2_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
38638. BIFPLR2_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
38639. BIFPLR2_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
38640. BIFPLR2_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
38641. BIFPLR2_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
38642. BIFPLR2_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
38643. BIFPLR2_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
38644. BIFPLR2_1_PCIE_LINK_CNTL3__RESERVED_MASK
38645. BIFPLR2_1_PCIE_LINK_CNTL3__RESERVED__SHIFT
38646. BIFPLR2_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
38647. BIFPLR2_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
38648. BIFPLR2_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
38649. BIFPLR2_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
38650. BIFPLR2_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
38651. BIFPLR2_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
38652. BIFPLR2_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
38653. BIFPLR2_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
38654. BIFPLR2_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
38655. BIFPLR2_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
38656. BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
38657. BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
38658. BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
38659. BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
38660. BIFPLR2_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
38661. BIFPLR2_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
38662. BIFPLR2_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK
38663. BIFPLR2_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
38664. BIFPLR2_1_PCIE_MC_CNTL__MC_ENABLE_MASK
38665. BIFPLR2_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT
38666. BIFPLR2_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
38667. BIFPLR2_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
38668. BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
38669. BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
38670. BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
38671. BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
38672. BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
38673. BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
38674. BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
38675. BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
38676. BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
38677. BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
38678. BIFPLR2_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
38679. BIFPLR2_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
38680. BIFPLR2_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
38681. BIFPLR2_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
38682. BIFPLR2_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
38683. BIFPLR2_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
38684. BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
38685. BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
38686. BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
38687. BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
38688. BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
38689. BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
38690. BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
38691. BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
38692. BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
38693. BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
38694. BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
38695. BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
38696. BIFPLR2_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
38697. BIFPLR2_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
38698. BIFPLR2_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
38699. BIFPLR2_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
38700. BIFPLR2_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
38701. BIFPLR2_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
38702. BIFPLR2_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
38703. BIFPLR2_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
38704. BIFPLR2_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
38705. BIFPLR2_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
38706. BIFPLR2_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
38707. BIFPLR2_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
38708. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
38709. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
38710. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
38711. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
38712. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
38713. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
38714. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
38715. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
38716. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
38717. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
38718. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
38719. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
38720. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
38721. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
38722. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
38723. BIFPLR2_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
38724. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
38725. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
38726. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
38727. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
38728. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
38729. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
38730. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
38731. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
38732. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
38733. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
38734. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
38735. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
38736. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
38737. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
38738. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
38739. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
38740. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
38741. BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
38742. BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
38743. BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
38744. BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
38745. BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
38746. BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
38747. BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
38748. BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
38749. BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
38750. BIFPLR2_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
38751. BIFPLR2_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
38752. BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
38753. BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
38754. BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK
38755. BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
38756. BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
38757. BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
38758. BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
38759. BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
38760. BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CTO_MASK
38761. BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
38762. BIFPLR2_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
38763. BIFPLR2_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
38764. BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
38765. BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
38766. BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK
38767. BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
38768. BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
38769. BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
38770. BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
38771. BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
38772. BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
38773. BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
38774. BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
38775. BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
38776. BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
38777. BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
38778. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
38779. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
38780. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
38781. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
38782. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
38783. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
38784. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
38785. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
38786. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
38787. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
38788. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
38789. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
38790. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
38791. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
38792. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
38793. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
38794. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
38795. BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
38796. BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
38797. BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
38798. BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
38799. BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
38800. BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
38801. BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
38802. BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
38803. BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
38804. BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK
38805. BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
38806. BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
38807. BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
38808. BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
38809. BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
38810. BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
38811. BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
38812. BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
38813. BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
38814. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
38815. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
38816. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
38817. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
38818. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
38819. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
38820. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
38821. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
38822. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
38823. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
38824. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
38825. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
38826. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
38827. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
38828. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
38829. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
38830. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
38831. BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
38832. BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
38833. BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
38834. BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
38835. BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
38836. BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
38837. BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
38838. BIFPLR2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
38839. BIFPLR2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
38840. BIFPLR2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
38841. BIFPLR2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
38842. BIFPLR2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
38843. BIFPLR2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
38844. BIFPLR2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
38845. BIFPLR2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
38846. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
38847. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
38848. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
38849. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
38850. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
38851. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
38852. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
38853. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
38854. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
38855. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
38856. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
38857. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
38858. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
38859. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
38860. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
38861. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
38862. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
38863. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
38864. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
38865. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
38866. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
38867. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
38868. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
38869. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
38870. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
38871. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
38872. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
38873. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
38874. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
38875. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
38876. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
38877. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
38878. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
38879. BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
38880. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
38881. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
38882. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
38883. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
38884. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
38885. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
38886. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
38887. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
38888. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
38889. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
38890. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
38891. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
38892. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
38893. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
38894. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
38895. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
38896. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
38897. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
38898. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
38899. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
38900. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
38901. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
38902. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
38903. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
38904. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
38905. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
38906. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
38907. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
38908. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
38909. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
38910. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
38911. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
38912. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
38913. BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
38914. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
38915. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
38916. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
38917. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
38918. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
38919. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
38920. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
38921. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
38922. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
38923. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
38924. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
38925. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
38926. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
38927. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
38928. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
38929. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
38930. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
38931. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
38932. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
38933. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
38934. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
38935. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
38936. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
38937. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
38938. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
38939. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
38940. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
38941. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
38942. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
38943. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
38944. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
38945. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
38946. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
38947. BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
38948. BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
38949. BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
38950. BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
38951. BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
38952. BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
38953. BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
38954. BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
38955. BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
38956. BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
38957. BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
38958. BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
38959. BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
38960. BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
38961. BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
38962. BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
38963. BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
38964. BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
38965. BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
38966. BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
38967. BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
38968. BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
38969. BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
38970. BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
38971. BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
38972. BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
38973. BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
38974. BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
38975. BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
38976. BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
38977. BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
38978. BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
38979. BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
38980. BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
38981. BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
38982. BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
38983. BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
38984. BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
38985. BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
38986. BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
38987. BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
38988. BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
38989. BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
38990. BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
38991. BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
38992. BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
38993. BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
38994. BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
38995. BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
38996. BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
38997. BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
38998. BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
38999. BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
39000. BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
39001. BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
39002. BIFPLR2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
39003. BIFPLR2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
39004. BIFPLR2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
39005. BIFPLR2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
39006. BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
39007. BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
39008. BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
39009. BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
39010. BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
39011. BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
39012. BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
39013. BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
39014. BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
39015. BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
39016. BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
39017. BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
39018. BIFPLR2_1_PMI_CAP_LIST__CAP_ID_MASK
39019. BIFPLR2_1_PMI_CAP_LIST__CAP_ID__SHIFT
39020. BIFPLR2_1_PMI_CAP_LIST__NEXT_PTR_MASK
39021. BIFPLR2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
39022. BIFPLR2_1_PMI_CAP__AUX_CURRENT_MASK
39023. BIFPLR2_1_PMI_CAP__AUX_CURRENT__SHIFT
39024. BIFPLR2_1_PMI_CAP__D1_SUPPORT_MASK
39025. BIFPLR2_1_PMI_CAP__D1_SUPPORT__SHIFT
39026. BIFPLR2_1_PMI_CAP__D2_SUPPORT_MASK
39027. BIFPLR2_1_PMI_CAP__D2_SUPPORT__SHIFT
39028. BIFPLR2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
39029. BIFPLR2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
39030. BIFPLR2_1_PMI_CAP__PME_CLOCK_MASK
39031. BIFPLR2_1_PMI_CAP__PME_CLOCK__SHIFT
39032. BIFPLR2_1_PMI_CAP__PME_SUPPORT_MASK
39033. BIFPLR2_1_PMI_CAP__PME_SUPPORT__SHIFT
39034. BIFPLR2_1_PMI_CAP__VERSION_MASK
39035. BIFPLR2_1_PMI_CAP__VERSION__SHIFT
39036. BIFPLR2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
39037. BIFPLR2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
39038. BIFPLR2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
39039. BIFPLR2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
39040. BIFPLR2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
39041. BIFPLR2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
39042. BIFPLR2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
39043. BIFPLR2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
39044. BIFPLR2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
39045. BIFPLR2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
39046. BIFPLR2_1_PMI_STATUS_CNTL__PME_EN_MASK
39047. BIFPLR2_1_PMI_STATUS_CNTL__PME_EN__SHIFT
39048. BIFPLR2_1_PMI_STATUS_CNTL__PME_STATUS_MASK
39049. BIFPLR2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
39050. BIFPLR2_1_PMI_STATUS_CNTL__PMI_DATA_MASK
39051. BIFPLR2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
39052. BIFPLR2_1_PMI_STATUS_CNTL__POWER_STATE_MASK
39053. BIFPLR2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
39054. BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
39055. BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
39056. BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
39057. BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
39058. BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
39059. BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
39060. BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
39061. BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
39062. BIFPLR2_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
39063. BIFPLR2_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
39064. BIFPLR2_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
39065. BIFPLR2_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
39066. BIFPLR2_1_PROG_INTERFACE__PROG_INTERFACE_MASK
39067. BIFPLR2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
39068. BIFPLR2_1_REVISION_ID__MAJOR_REV_ID_MASK
39069. BIFPLR2_1_REVISION_ID__MAJOR_REV_ID__SHIFT
39070. BIFPLR2_1_REVISION_ID__MINOR_REV_ID_MASK
39071. BIFPLR2_1_REVISION_ID__MINOR_REV_ID__SHIFT
39072. BIFPLR2_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
39073. BIFPLR2_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
39074. BIFPLR2_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
39075. BIFPLR2_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
39076. BIFPLR2_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK
39077. BIFPLR2_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
39078. BIFPLR2_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
39079. BIFPLR2_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
39080. BIFPLR2_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
39081. BIFPLR2_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
39082. BIFPLR2_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
39083. BIFPLR2_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
39084. BIFPLR2_1_ROOT_STATUS__PME_PENDING_MASK
39085. BIFPLR2_1_ROOT_STATUS__PME_PENDING__SHIFT
39086. BIFPLR2_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK
39087. BIFPLR2_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
39088. BIFPLR2_1_ROOT_STATUS__PME_STATUS_MASK
39089. BIFPLR2_1_ROOT_STATUS__PME_STATUS__SHIFT
39090. BIFPLR2_1_SECONDARY_STATUS__CAP_LIST_MASK
39091. BIFPLR2_1_SECONDARY_STATUS__CAP_LIST__SHIFT
39092. BIFPLR2_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK
39093. BIFPLR2_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
39094. BIFPLR2_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
39095. BIFPLR2_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
39096. BIFPLR2_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
39097. BIFPLR2_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
39098. BIFPLR2_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
39099. BIFPLR2_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
39100. BIFPLR2_1_SECONDARY_STATUS__PCI_66_EN_MASK
39101. BIFPLR2_1_SECONDARY_STATUS__PCI_66_EN__SHIFT
39102. BIFPLR2_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
39103. BIFPLR2_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
39104. BIFPLR2_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
39105. BIFPLR2_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
39106. BIFPLR2_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
39107. BIFPLR2_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
39108. BIFPLR2_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
39109. BIFPLR2_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
39110. BIFPLR2_1_SLOT_CAP2__RESERVED_MASK
39111. BIFPLR2_1_SLOT_CAP2__RESERVED__SHIFT
39112. BIFPLR2_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
39113. BIFPLR2_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
39114. BIFPLR2_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
39115. BIFPLR2_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
39116. BIFPLR2_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
39117. BIFPLR2_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
39118. BIFPLR2_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK
39119. BIFPLR2_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
39120. BIFPLR2_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK
39121. BIFPLR2_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
39122. BIFPLR2_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
39123. BIFPLR2_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
39124. BIFPLR2_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
39125. BIFPLR2_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
39126. BIFPLR2_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
39127. BIFPLR2_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
39128. BIFPLR2_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
39129. BIFPLR2_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
39130. BIFPLR2_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
39131. BIFPLR2_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
39132. BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
39133. BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
39134. BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
39135. BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
39136. BIFPLR2_1_SLOT_CNTL2__RESERVED_MASK
39137. BIFPLR2_1_SLOT_CNTL2__RESERVED__SHIFT
39138. BIFPLR2_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
39139. BIFPLR2_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
39140. BIFPLR2_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
39141. BIFPLR2_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
39142. BIFPLR2_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
39143. BIFPLR2_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
39144. BIFPLR2_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
39145. BIFPLR2_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
39146. BIFPLR2_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
39147. BIFPLR2_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
39148. BIFPLR2_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
39149. BIFPLR2_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
39150. BIFPLR2_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
39151. BIFPLR2_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
39152. BIFPLR2_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
39153. BIFPLR2_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
39154. BIFPLR2_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
39155. BIFPLR2_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
39156. BIFPLR2_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
39157. BIFPLR2_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
39158. BIFPLR2_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
39159. BIFPLR2_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
39160. BIFPLR2_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
39161. BIFPLR2_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
39162. BIFPLR2_1_SLOT_STATUS2__RESERVED_MASK
39163. BIFPLR2_1_SLOT_STATUS2__RESERVED__SHIFT
39164. BIFPLR2_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
39165. BIFPLR2_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
39166. BIFPLR2_1_SLOT_STATUS__COMMAND_COMPLETED_MASK
39167. BIFPLR2_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
39168. BIFPLR2_1_SLOT_STATUS__DL_STATE_CHANGED_MASK
39169. BIFPLR2_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
39170. BIFPLR2_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
39171. BIFPLR2_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
39172. BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
39173. BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
39174. BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK
39175. BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
39176. BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
39177. BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
39178. BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
39179. BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
39180. BIFPLR2_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
39181. BIFPLR2_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
39182. BIFPLR2_1_SSID_CAP_LIST__CAP_ID_MASK
39183. BIFPLR2_1_SSID_CAP_LIST__CAP_ID__SHIFT
39184. BIFPLR2_1_SSID_CAP_LIST__NEXT_PTR_MASK
39185. BIFPLR2_1_SSID_CAP_LIST__NEXT_PTR__SHIFT
39186. BIFPLR2_1_SSID_CAP__SUBSYSTEM_ID_MASK
39187. BIFPLR2_1_SSID_CAP__SUBSYSTEM_ID__SHIFT
39188. BIFPLR2_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
39189. BIFPLR2_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
39190. BIFPLR2_1_STATUS__CAP_LIST_MASK
39191. BIFPLR2_1_STATUS__CAP_LIST__SHIFT
39192. BIFPLR2_1_STATUS__DEVSEL_TIMING_MASK
39193. BIFPLR2_1_STATUS__DEVSEL_TIMING__SHIFT
39194. BIFPLR2_1_STATUS__FAST_BACK_CAPABLE_MASK
39195. BIFPLR2_1_STATUS__FAST_BACK_CAPABLE__SHIFT
39196. BIFPLR2_1_STATUS__INT_STATUS_MASK
39197. BIFPLR2_1_STATUS__INT_STATUS__SHIFT
39198. BIFPLR2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
39199. BIFPLR2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
39200. BIFPLR2_1_STATUS__PARITY_ERROR_DETECTED_MASK
39201. BIFPLR2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
39202. BIFPLR2_1_STATUS__PCI_66_EN_MASK
39203. BIFPLR2_1_STATUS__PCI_66_EN__SHIFT
39204. BIFPLR2_1_STATUS__RECEIVED_MASTER_ABORT_MASK
39205. BIFPLR2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
39206. BIFPLR2_1_STATUS__RECEIVED_TARGET_ABORT_MASK
39207. BIFPLR2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
39208. BIFPLR2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
39209. BIFPLR2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
39210. BIFPLR2_1_STATUS__SIGNAL_TARGET_ABORT_MASK
39211. BIFPLR2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
39212. BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
39213. BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
39214. BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
39215. BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
39216. BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
39217. BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
39218. BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
39219. BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
39220. BIFPLR2_1_SUB_CLASS__SUB_CLASS_MASK
39221. BIFPLR2_1_SUB_CLASS__SUB_CLASS__SHIFT
39222. BIFPLR2_1_VENDOR_ID__VENDOR_ID_MASK
39223. BIFPLR2_1_VENDOR_ID__VENDOR_ID__SHIFT
39224. BIFPLR2_2_BASE_CLASS__BASE_CLASS_MASK
39225. BIFPLR2_2_BASE_CLASS__BASE_CLASS__SHIFT
39226. BIFPLR2_2_BIST__BIST_CAP_MASK
39227. BIFPLR2_2_BIST__BIST_CAP__SHIFT
39228. BIFPLR2_2_BIST__BIST_COMP_MASK
39229. BIFPLR2_2_BIST__BIST_COMP__SHIFT
39230. BIFPLR2_2_BIST__BIST_STRT_MASK
39231. BIFPLR2_2_BIST__BIST_STRT__SHIFT
39232. BIFPLR2_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
39233. BIFPLR2_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
39234. BIFPLR2_2_CAP_PTR__CAP_PTR_MASK
39235. BIFPLR2_2_CAP_PTR__CAP_PTR__SHIFT
39236. BIFPLR2_2_COMMAND__AD_STEPPING_MASK
39237. BIFPLR2_2_COMMAND__AD_STEPPING__SHIFT
39238. BIFPLR2_2_COMMAND__BUS_MASTER_EN_MASK
39239. BIFPLR2_2_COMMAND__BUS_MASTER_EN__SHIFT
39240. BIFPLR2_2_COMMAND__FAST_B2B_EN_MASK
39241. BIFPLR2_2_COMMAND__FAST_B2B_EN__SHIFT
39242. BIFPLR2_2_COMMAND__INT_DIS_MASK
39243. BIFPLR2_2_COMMAND__INT_DIS__SHIFT
39244. BIFPLR2_2_COMMAND__IO_ACCESS_EN_MASK
39245. BIFPLR2_2_COMMAND__IO_ACCESS_EN__SHIFT
39246. BIFPLR2_2_COMMAND__MEM_ACCESS_EN_MASK
39247. BIFPLR2_2_COMMAND__MEM_ACCESS_EN__SHIFT
39248. BIFPLR2_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
39249. BIFPLR2_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
39250. BIFPLR2_2_COMMAND__PAL_SNOOP_EN_MASK
39251. BIFPLR2_2_COMMAND__PAL_SNOOP_EN__SHIFT
39252. BIFPLR2_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
39253. BIFPLR2_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
39254. BIFPLR2_2_COMMAND__SERR_EN_MASK
39255. BIFPLR2_2_COMMAND__SERR_EN__SHIFT
39256. BIFPLR2_2_COMMAND__SPECIAL_CYCLE_EN_MASK
39257. BIFPLR2_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
39258. BIFPLR2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
39259. BIFPLR2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
39260. BIFPLR2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
39261. BIFPLR2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
39262. BIFPLR2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
39263. BIFPLR2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
39264. BIFPLR2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
39265. BIFPLR2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
39266. BIFPLR2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
39267. BIFPLR2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
39268. BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
39269. BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
39270. BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
39271. BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
39272. BIFPLR2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
39273. BIFPLR2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
39274. BIFPLR2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
39275. BIFPLR2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
39276. BIFPLR2_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
39277. BIFPLR2_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
39278. BIFPLR2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
39279. BIFPLR2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
39280. BIFPLR2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
39281. BIFPLR2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
39282. BIFPLR2_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
39283. BIFPLR2_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
39284. BIFPLR2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
39285. BIFPLR2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
39286. BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
39287. BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
39288. BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
39289. BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
39290. BIFPLR2_2_DEVICE_CAP__EXTENDED_TAG_MASK
39291. BIFPLR2_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
39292. BIFPLR2_2_DEVICE_CAP__FLR_CAPABLE_MASK
39293. BIFPLR2_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
39294. BIFPLR2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
39295. BIFPLR2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
39296. BIFPLR2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
39297. BIFPLR2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
39298. BIFPLR2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
39299. BIFPLR2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
39300. BIFPLR2_2_DEVICE_CAP__PHANTOM_FUNC_MASK
39301. BIFPLR2_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
39302. BIFPLR2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
39303. BIFPLR2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
39304. BIFPLR2_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
39305. BIFPLR2_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
39306. BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
39307. BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
39308. BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
39309. BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
39310. BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
39311. BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
39312. BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
39313. BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
39314. BIFPLR2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
39315. BIFPLR2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
39316. BIFPLR2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
39317. BIFPLR2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
39318. BIFPLR2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
39319. BIFPLR2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
39320. BIFPLR2_2_DEVICE_CNTL2__LTR_EN_MASK
39321. BIFPLR2_2_DEVICE_CNTL2__LTR_EN__SHIFT
39322. BIFPLR2_2_DEVICE_CNTL2__OBFF_EN_MASK
39323. BIFPLR2_2_DEVICE_CNTL2__OBFF_EN__SHIFT
39324. BIFPLR2_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
39325. BIFPLR2_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
39326. BIFPLR2_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
39327. BIFPLR2_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
39328. BIFPLR2_2_DEVICE_CNTL__CORR_ERR_EN_MASK
39329. BIFPLR2_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
39330. BIFPLR2_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
39331. BIFPLR2_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
39332. BIFPLR2_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
39333. BIFPLR2_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
39334. BIFPLR2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
39335. BIFPLR2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
39336. BIFPLR2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
39337. BIFPLR2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
39338. BIFPLR2_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
39339. BIFPLR2_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
39340. BIFPLR2_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
39341. BIFPLR2_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
39342. BIFPLR2_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
39343. BIFPLR2_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
39344. BIFPLR2_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
39345. BIFPLR2_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
39346. BIFPLR2_2_DEVICE_CNTL__USR_REPORT_EN_MASK
39347. BIFPLR2_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
39348. BIFPLR2_2_DEVICE_ID__DEVICE_ID_MASK
39349. BIFPLR2_2_DEVICE_ID__DEVICE_ID__SHIFT
39350. BIFPLR2_2_DEVICE_STATUS2__RESERVED_MASK
39351. BIFPLR2_2_DEVICE_STATUS2__RESERVED__SHIFT
39352. BIFPLR2_2_DEVICE_STATUS__AUX_PWR_MASK
39353. BIFPLR2_2_DEVICE_STATUS__AUX_PWR__SHIFT
39354. BIFPLR2_2_DEVICE_STATUS__CORR_ERR_MASK
39355. BIFPLR2_2_DEVICE_STATUS__CORR_ERR__SHIFT
39356. BIFPLR2_2_DEVICE_STATUS__FATAL_ERR_MASK
39357. BIFPLR2_2_DEVICE_STATUS__FATAL_ERR__SHIFT
39358. BIFPLR2_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
39359. BIFPLR2_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
39360. BIFPLR2_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
39361. BIFPLR2_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
39362. BIFPLR2_2_DEVICE_STATUS__USR_DETECTED_MASK
39363. BIFPLR2_2_DEVICE_STATUS__USR_DETECTED__SHIFT
39364. BIFPLR2_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
39365. BIFPLR2_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
39366. BIFPLR2_2_HEADER__DEVICE_TYPE_MASK
39367. BIFPLR2_2_HEADER__DEVICE_TYPE__SHIFT
39368. BIFPLR2_2_HEADER__HEADER_TYPE_MASK
39369. BIFPLR2_2_HEADER__HEADER_TYPE__SHIFT
39370. BIFPLR2_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
39371. BIFPLR2_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
39372. BIFPLR2_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
39373. BIFPLR2_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
39374. BIFPLR2_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
39375. BIFPLR2_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
39376. BIFPLR2_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
39377. BIFPLR2_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
39378. BIFPLR2_2_IO_BASE_LIMIT__IO_BASE_MASK
39379. BIFPLR2_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
39380. BIFPLR2_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
39381. BIFPLR2_2_IO_BASE_LIMIT__IO_BASE__SHIFT
39382. BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT_MASK
39383. BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
39384. BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
39385. BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT
39386. BIFPLR2_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
39387. BIFPLR2_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
39388. BIFPLR2_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK
39389. BIFPLR2_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
39390. BIFPLR2_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
39391. BIFPLR2_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
39392. BIFPLR2_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
39393. BIFPLR2_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
39394. BIFPLR2_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
39395. BIFPLR2_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
39396. BIFPLR2_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK
39397. BIFPLR2_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
39398. BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
39399. BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
39400. BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK
39401. BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
39402. BIFPLR2_2_LATENCY__LATENCY_TIMER_MASK
39403. BIFPLR2_2_LATENCY__LATENCY_TIMER__SHIFT
39404. BIFPLR2_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
39405. BIFPLR2_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
39406. BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
39407. BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
39408. BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
39409. BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
39410. BIFPLR2_2_LINK_CAP2__RESERVED_MASK
39411. BIFPLR2_2_LINK_CAP2__RESERVED__SHIFT
39412. BIFPLR2_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
39413. BIFPLR2_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
39414. BIFPLR2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
39415. BIFPLR2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
39416. BIFPLR2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
39417. BIFPLR2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
39418. BIFPLR2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
39419. BIFPLR2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
39420. BIFPLR2_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
39421. BIFPLR2_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
39422. BIFPLR2_2_LINK_CAP__L1_EXIT_LATENCY_MASK
39423. BIFPLR2_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
39424. BIFPLR2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
39425. BIFPLR2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
39426. BIFPLR2_2_LINK_CAP__LINK_SPEED_MASK
39427. BIFPLR2_2_LINK_CAP__LINK_SPEED__SHIFT
39428. BIFPLR2_2_LINK_CAP__LINK_WIDTH_MASK
39429. BIFPLR2_2_LINK_CAP__LINK_WIDTH__SHIFT
39430. BIFPLR2_2_LINK_CAP__PM_SUPPORT_MASK
39431. BIFPLR2_2_LINK_CAP__PM_SUPPORT__SHIFT
39432. BIFPLR2_2_LINK_CAP__PORT_NUMBER_MASK
39433. BIFPLR2_2_LINK_CAP__PORT_NUMBER__SHIFT
39434. BIFPLR2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
39435. BIFPLR2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
39436. BIFPLR2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
39437. BIFPLR2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
39438. BIFPLR2_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
39439. BIFPLR2_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
39440. BIFPLR2_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
39441. BIFPLR2_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
39442. BIFPLR2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
39443. BIFPLR2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
39444. BIFPLR2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
39445. BIFPLR2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
39446. BIFPLR2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
39447. BIFPLR2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
39448. BIFPLR2_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
39449. BIFPLR2_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
39450. BIFPLR2_2_LINK_CNTL2__XMIT_MARGIN_MASK
39451. BIFPLR2_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
39452. BIFPLR2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
39453. BIFPLR2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
39454. BIFPLR2_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
39455. BIFPLR2_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
39456. BIFPLR2_2_LINK_CNTL__EXTENDED_SYNC_MASK
39457. BIFPLR2_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
39458. BIFPLR2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
39459. BIFPLR2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
39460. BIFPLR2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
39461. BIFPLR2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
39462. BIFPLR2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
39463. BIFPLR2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
39464. BIFPLR2_2_LINK_CNTL__LINK_DIS_MASK
39465. BIFPLR2_2_LINK_CNTL__LINK_DIS__SHIFT
39466. BIFPLR2_2_LINK_CNTL__PM_CONTROL_MASK
39467. BIFPLR2_2_LINK_CNTL__PM_CONTROL__SHIFT
39468. BIFPLR2_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
39469. BIFPLR2_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
39470. BIFPLR2_2_LINK_CNTL__RETRAIN_LINK_MASK
39471. BIFPLR2_2_LINK_CNTL__RETRAIN_LINK__SHIFT
39472. BIFPLR2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
39473. BIFPLR2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
39474. BIFPLR2_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
39475. BIFPLR2_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
39476. BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
39477. BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
39478. BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
39479. BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
39480. BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
39481. BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
39482. BIFPLR2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
39483. BIFPLR2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
39484. BIFPLR2_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
39485. BIFPLR2_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
39486. BIFPLR2_2_LINK_STATUS__DL_ACTIVE_MASK
39487. BIFPLR2_2_LINK_STATUS__DL_ACTIVE__SHIFT
39488. BIFPLR2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
39489. BIFPLR2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
39490. BIFPLR2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
39491. BIFPLR2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
39492. BIFPLR2_2_LINK_STATUS__LINK_TRAINING_MASK
39493. BIFPLR2_2_LINK_STATUS__LINK_TRAINING__SHIFT
39494. BIFPLR2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
39495. BIFPLR2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
39496. BIFPLR2_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
39497. BIFPLR2_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
39498. BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
39499. BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
39500. BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
39501. BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
39502. BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
39503. BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
39504. BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
39505. BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
39506. BIFPLR2_2_MSI_CAP_LIST__CAP_ID_MASK
39507. BIFPLR2_2_MSI_CAP_LIST__CAP_ID__SHIFT
39508. BIFPLR2_2_MSI_CAP_LIST__NEXT_PTR_MASK
39509. BIFPLR2_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
39510. BIFPLR2_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
39511. BIFPLR2_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
39512. BIFPLR2_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
39513. BIFPLR2_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
39514. BIFPLR2_2_MSI_MAP_CAP_LIST__CAP_ID_MASK
39515. BIFPLR2_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
39516. BIFPLR2_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
39517. BIFPLR2_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
39518. BIFPLR2_2_MSI_MAP_CAP__CAP_TYPE_MASK
39519. BIFPLR2_2_MSI_MAP_CAP__CAP_TYPE__SHIFT
39520. BIFPLR2_2_MSI_MAP_CAP__EN_MASK
39521. BIFPLR2_2_MSI_MAP_CAP__EN__SHIFT
39522. BIFPLR2_2_MSI_MAP_CAP__FIXD_MASK
39523. BIFPLR2_2_MSI_MAP_CAP__FIXD__SHIFT
39524. BIFPLR2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
39525. BIFPLR2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
39526. BIFPLR2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
39527. BIFPLR2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
39528. BIFPLR2_2_MSI_MSG_CNTL__MSI_64BIT_MASK
39529. BIFPLR2_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
39530. BIFPLR2_2_MSI_MSG_CNTL__MSI_EN_MASK
39531. BIFPLR2_2_MSI_MSG_CNTL__MSI_EN__SHIFT
39532. BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
39533. BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
39534. BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
39535. BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
39536. BIFPLR2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
39537. BIFPLR2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
39538. BIFPLR2_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
39539. BIFPLR2_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
39540. BIFPLR2_2_MSI_MSG_DATA__MSI_DATA_MASK
39541. BIFPLR2_2_MSI_MSG_DATA__MSI_DATA__SHIFT
39542. BIFPLR2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
39543. BIFPLR2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
39544. BIFPLR2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
39545. BIFPLR2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
39546. BIFPLR2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
39547. BIFPLR2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
39548. BIFPLR2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
39549. BIFPLR2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
39550. BIFPLR2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
39551. BIFPLR2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
39552. BIFPLR2_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
39553. BIFPLR2_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
39554. BIFPLR2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
39555. BIFPLR2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
39556. BIFPLR2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
39557. BIFPLR2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
39558. BIFPLR2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
39559. BIFPLR2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
39560. BIFPLR2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
39561. BIFPLR2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
39562. BIFPLR2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
39563. BIFPLR2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
39564. BIFPLR2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
39565. BIFPLR2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
39566. BIFPLR2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
39567. BIFPLR2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
39568. BIFPLR2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
39569. BIFPLR2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
39570. BIFPLR2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
39571. BIFPLR2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
39572. BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
39573. BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
39574. BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
39575. BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
39576. BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
39577. BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
39578. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
39579. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
39580. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
39581. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
39582. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
39583. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
39584. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
39585. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
39586. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
39587. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
39588. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
39589. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
39590. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
39591. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
39592. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
39593. BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
39594. BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
39595. BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
39596. BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
39597. BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
39598. BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
39599. BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
39600. BIFPLR2_2_PCIE_CAP_LIST__CAP_ID_MASK
39601. BIFPLR2_2_PCIE_CAP_LIST__CAP_ID__SHIFT
39602. BIFPLR2_2_PCIE_CAP_LIST__NEXT_PTR_MASK
39603. BIFPLR2_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
39604. BIFPLR2_2_PCIE_CAP__DEVICE_TYPE_MASK
39605. BIFPLR2_2_PCIE_CAP__DEVICE_TYPE__SHIFT
39606. BIFPLR2_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
39607. BIFPLR2_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
39608. BIFPLR2_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
39609. BIFPLR2_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
39610. BIFPLR2_2_PCIE_CAP__VERSION_MASK
39611. BIFPLR2_2_PCIE_CAP__VERSION__SHIFT
39612. BIFPLR2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
39613. BIFPLR2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
39614. BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
39615. BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
39616. BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
39617. BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
39618. BIFPLR2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
39619. BIFPLR2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
39620. BIFPLR2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
39621. BIFPLR2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
39622. BIFPLR2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
39623. BIFPLR2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
39624. BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
39625. BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
39626. BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
39627. BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
39628. BIFPLR2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
39629. BIFPLR2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
39630. BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
39631. BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
39632. BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
39633. BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
39634. BIFPLR2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
39635. BIFPLR2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
39636. BIFPLR2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
39637. BIFPLR2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
39638. BIFPLR2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
39639. BIFPLR2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
39640. BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
39641. BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
39642. BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
39643. BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
39644. BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
39645. BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
39646. BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
39647. BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
39648. BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
39649. BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
39650. BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
39651. BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
39652. BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
39653. BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
39654. BIFPLR2_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
39655. BIFPLR2_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
39656. BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
39657. BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
39658. BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
39659. BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
39660. BIFPLR2_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
39661. BIFPLR2_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
39662. BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
39663. BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
39664. BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
39665. BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
39666. BIFPLR2_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
39667. BIFPLR2_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
39668. BIFPLR2_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
39669. BIFPLR2_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
39670. BIFPLR2_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
39671. BIFPLR2_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
39672. BIFPLR2_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
39673. BIFPLR2_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
39674. BIFPLR2_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
39675. BIFPLR2_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
39676. BIFPLR2_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
39677. BIFPLR2_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
39678. BIFPLR2_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
39679. BIFPLR2_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
39680. BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
39681. BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
39682. BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
39683. BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
39684. BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
39685. BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
39686. BIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
39687. BIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
39688. BIFPLR2_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
39689. BIFPLR2_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
39690. BIFPLR2_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
39691. BIFPLR2_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
39692. BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
39693. BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
39694. BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
39695. BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
39696. BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
39697. BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
39698. BIFPLR2_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
39699. BIFPLR2_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
39700. BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
39701. BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
39702. BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
39703. BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
39704. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK
39705. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
39706. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK
39707. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
39708. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK
39709. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
39710. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK
39711. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
39712. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK
39713. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
39714. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK
39715. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
39716. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK
39717. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
39718. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK
39719. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
39720. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK
39721. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
39722. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK
39723. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
39724. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK
39725. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
39726. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK
39727. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
39728. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK
39729. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
39730. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK
39731. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
39732. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK
39733. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
39734. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK
39735. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
39736. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK
39737. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
39738. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK
39739. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
39740. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK
39741. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
39742. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK
39743. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
39744. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK
39745. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
39746. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK
39747. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
39748. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK
39749. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
39750. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK
39751. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
39752. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK
39753. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
39754. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK
39755. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
39756. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK
39757. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
39758. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK
39759. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
39760. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK
39761. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
39762. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK
39763. BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
39764. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK
39765. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
39766. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK
39767. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
39768. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK
39769. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
39770. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK
39771. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
39772. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK
39773. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
39774. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK
39775. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
39776. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK
39777. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
39778. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK
39779. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
39780. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK
39781. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
39782. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK
39783. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
39784. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK
39785. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
39786. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK
39787. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
39788. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK
39789. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
39790. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK
39791. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
39792. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK
39793. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
39794. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK
39795. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
39796. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK
39797. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
39798. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK
39799. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
39800. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK
39801. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
39802. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK
39803. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
39804. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK
39805. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
39806. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK
39807. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
39808. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK
39809. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
39810. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK
39811. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
39812. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK
39813. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
39814. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK
39815. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
39816. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK
39817. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
39818. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK
39819. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
39820. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK
39821. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
39822. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK
39823. BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
39824. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK
39825. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
39826. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK
39827. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
39828. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK
39829. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
39830. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK
39831. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
39832. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK
39833. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
39834. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK
39835. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
39836. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK
39837. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
39838. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK
39839. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
39840. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK
39841. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
39842. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK
39843. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
39844. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK
39845. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
39846. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK
39847. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
39848. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK
39849. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
39850. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK
39851. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
39852. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK
39853. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
39854. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK
39855. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
39856. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK
39857. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
39858. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK
39859. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
39860. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK
39861. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
39862. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK
39863. BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
39864. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK
39865. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
39866. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK
39867. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
39868. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK
39869. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
39870. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK
39871. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
39872. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK
39873. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
39874. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK
39875. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
39876. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK
39877. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
39878. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK
39879. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
39880. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK
39881. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
39882. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK
39883. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
39884. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK
39885. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
39886. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK
39887. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
39888. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK
39889. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
39890. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK
39891. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
39892. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK
39893. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
39894. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK
39895. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
39896. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK
39897. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
39898. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK
39899. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
39900. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK
39901. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
39902. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK
39903. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
39904. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK
39905. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
39906. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK
39907. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
39908. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK
39909. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
39910. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK
39911. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
39912. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK
39913. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
39914. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK
39915. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
39916. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK
39917. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
39918. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK
39919. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
39920. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK
39921. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
39922. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK
39923. BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
39924. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK
39925. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
39926. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK
39927. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
39928. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK
39929. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
39930. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK
39931. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
39932. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK
39933. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
39934. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK
39935. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
39936. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK
39937. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
39938. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK
39939. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
39940. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK
39941. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
39942. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK
39943. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
39944. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK
39945. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
39946. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK
39947. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
39948. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK
39949. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
39950. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK
39951. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
39952. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK
39953. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
39954. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK
39955. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
39956. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK
39957. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
39958. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK
39959. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
39960. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK
39961. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
39962. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK
39963. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
39964. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK
39965. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
39966. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK
39967. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
39968. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK
39969. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
39970. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK
39971. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
39972. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK
39973. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
39974. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK
39975. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
39976. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK
39977. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
39978. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK
39979. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
39980. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK
39981. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
39982. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK
39983. BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
39984. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK
39985. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
39986. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK
39987. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
39988. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK
39989. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
39990. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK
39991. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
39992. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK
39993. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
39994. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK
39995. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
39996. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK
39997. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
39998. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK
39999. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
40000. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK
40001. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
40002. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK
40003. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
40004. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK
40005. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
40006. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK
40007. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
40008. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK
40009. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
40010. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK
40011. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
40012. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK
40013. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
40014. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK
40015. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
40016. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK
40017. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
40018. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK
40019. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
40020. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK
40021. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
40022. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK
40023. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
40024. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK
40025. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
40026. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK
40027. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
40028. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK
40029. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
40030. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK
40031. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
40032. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK
40033. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
40034. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK
40035. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
40036. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK
40037. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
40038. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK
40039. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
40040. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK
40041. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
40042. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK
40043. BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
40044. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK
40045. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
40046. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK
40047. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
40048. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK
40049. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
40050. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK
40051. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
40052. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK
40053. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
40054. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK
40055. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
40056. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK
40057. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
40058. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK
40059. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
40060. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK
40061. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
40062. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK
40063. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
40064. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK
40065. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
40066. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK
40067. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
40068. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK
40069. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
40070. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK
40071. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
40072. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK
40073. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
40074. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK
40075. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
40076. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK
40077. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
40078. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK
40079. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
40080. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK
40081. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
40082. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK
40083. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
40084. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK
40085. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
40086. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK
40087. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
40088. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK
40089. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
40090. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK
40091. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
40092. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK
40093. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
40094. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK
40095. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
40096. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK
40097. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
40098. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK
40099. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
40100. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK
40101. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
40102. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK
40103. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
40104. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK
40105. BIFPLR2_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
40106. BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK
40107. BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
40108. BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK
40109. BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
40110. BIFPLR2_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
40111. BIFPLR2_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
40112. BIFPLR2_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK
40113. BIFPLR2_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
40114. BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
40115. BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
40116. BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
40117. BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
40118. BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
40119. BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
40120. BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
40121. BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
40122. BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
40123. BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
40124. BIFPLR2_2_PCIE_ESM_HEADER_2__CAP_ID_MASK
40125. BIFPLR2_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
40126. BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
40127. BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
40128. BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
40129. BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
40130. BIFPLR2_2_PCIE_HDR_LOG0__TLP_HDR_MASK
40131. BIFPLR2_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
40132. BIFPLR2_2_PCIE_HDR_LOG1__TLP_HDR_MASK
40133. BIFPLR2_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
40134. BIFPLR2_2_PCIE_HDR_LOG2__TLP_HDR_MASK
40135. BIFPLR2_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
40136. BIFPLR2_2_PCIE_HDR_LOG3__TLP_HDR_MASK
40137. BIFPLR2_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
40138. BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
40139. BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
40140. BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
40141. BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
40142. BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
40143. BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
40144. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
40145. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
40146. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
40147. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
40148. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
40149. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
40150. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
40151. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
40152. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
40153. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
40154. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
40155. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
40156. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
40157. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
40158. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
40159. BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
40160. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
40161. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
40162. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
40163. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
40164. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
40165. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
40166. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
40167. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
40168. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
40169. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
40170. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
40171. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
40172. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
40173. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
40174. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
40175. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
40176. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
40177. BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
40178. BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40179. BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40180. BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40181. BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40182. BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40183. BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40184. BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40185. BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40186. BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40187. BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40188. BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40189. BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40190. BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40191. BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40192. BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40193. BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40194. BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40195. BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40196. BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40197. BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40198. BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40199. BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40200. BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40201. BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40202. BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40203. BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40204. BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40205. BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40206. BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40207. BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40208. BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40209. BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40210. BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40211. BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40212. BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40213. BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40214. BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40215. BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40216. BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40217. BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40218. BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40219. BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40220. BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40221. BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40222. BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40223. BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40224. BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40225. BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40226. BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40227. BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40228. BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40229. BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40230. BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40231. BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40232. BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40233. BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40234. BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40235. BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40236. BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40237. BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40238. BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40239. BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40240. BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40241. BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40242. BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40243. BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40244. BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40245. BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40246. BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40247. BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40248. BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40249. BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40250. BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40251. BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40252. BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40253. BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40254. BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40255. BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40256. BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40257. BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40258. BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40259. BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40260. BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40261. BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40262. BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40263. BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40264. BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40265. BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40266. BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40267. BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40268. BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40269. BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40270. BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40271. BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40272. BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40273. BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40274. BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40275. BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40276. BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40277. BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40278. BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40279. BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40280. BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40281. BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40282. BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40283. BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40284. BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40285. BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40286. BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40287. BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40288. BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40289. BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40290. BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40291. BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40292. BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40293. BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40294. BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40295. BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40296. BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40297. BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40298. BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
40299. BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
40300. BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
40301. BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
40302. BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
40303. BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
40304. BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
40305. BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
40306. BIFPLR2_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
40307. BIFPLR2_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
40308. BIFPLR2_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
40309. BIFPLR2_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
40310. BIFPLR2_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
40311. BIFPLR2_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
40312. BIFPLR2_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
40313. BIFPLR2_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
40314. BIFPLR2_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
40315. BIFPLR2_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
40316. BIFPLR2_2_PCIE_LINK_CNTL3__RESERVED_MASK
40317. BIFPLR2_2_PCIE_LINK_CNTL3__RESERVED__SHIFT
40318. BIFPLR2_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
40319. BIFPLR2_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
40320. BIFPLR2_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
40321. BIFPLR2_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
40322. BIFPLR2_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
40323. BIFPLR2_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
40324. BIFPLR2_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
40325. BIFPLR2_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
40326. BIFPLR2_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
40327. BIFPLR2_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
40328. BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
40329. BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
40330. BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
40331. BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
40332. BIFPLR2_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
40333. BIFPLR2_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
40334. BIFPLR2_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK
40335. BIFPLR2_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
40336. BIFPLR2_2_PCIE_MC_CNTL__MC_ENABLE_MASK
40337. BIFPLR2_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT
40338. BIFPLR2_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
40339. BIFPLR2_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
40340. BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
40341. BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
40342. BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
40343. BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
40344. BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
40345. BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
40346. BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
40347. BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
40348. BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
40349. BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
40350. BIFPLR2_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
40351. BIFPLR2_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
40352. BIFPLR2_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
40353. BIFPLR2_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
40354. BIFPLR2_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
40355. BIFPLR2_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
40356. BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
40357. BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
40358. BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
40359. BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
40360. BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
40361. BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
40362. BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
40363. BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
40364. BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
40365. BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
40366. BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
40367. BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
40368. BIFPLR2_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
40369. BIFPLR2_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
40370. BIFPLR2_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
40371. BIFPLR2_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
40372. BIFPLR2_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
40373. BIFPLR2_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
40374. BIFPLR2_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
40375. BIFPLR2_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
40376. BIFPLR2_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
40377. BIFPLR2_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
40378. BIFPLR2_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
40379. BIFPLR2_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
40380. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
40381. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
40382. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
40383. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
40384. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
40385. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
40386. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
40387. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
40388. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
40389. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
40390. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
40391. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
40392. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
40393. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
40394. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
40395. BIFPLR2_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
40396. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
40397. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
40398. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
40399. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
40400. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
40401. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
40402. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
40403. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
40404. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
40405. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
40406. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
40407. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
40408. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
40409. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
40410. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
40411. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
40412. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
40413. BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
40414. BIFPLR2_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
40415. BIFPLR2_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
40416. BIFPLR2_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
40417. BIFPLR2_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
40418. BIFPLR2_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
40419. BIFPLR2_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
40420. BIFPLR2_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
40421. BIFPLR2_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
40422. BIFPLR2_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
40423. BIFPLR2_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
40424. BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
40425. BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
40426. BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK
40427. BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
40428. BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
40429. BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
40430. BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
40431. BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
40432. BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CTO_MASK
40433. BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
40434. BIFPLR2_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
40435. BIFPLR2_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
40436. BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
40437. BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
40438. BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK
40439. BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
40440. BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
40441. BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
40442. BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
40443. BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
40444. BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
40445. BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
40446. BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
40447. BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
40448. BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
40449. BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
40450. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
40451. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
40452. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
40453. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
40454. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
40455. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
40456. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
40457. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
40458. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
40459. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
40460. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
40461. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
40462. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
40463. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
40464. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
40465. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
40466. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
40467. BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
40468. BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
40469. BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
40470. BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
40471. BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
40472. BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
40473. BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
40474. BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
40475. BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
40476. BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK
40477. BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
40478. BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
40479. BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
40480. BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
40481. BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
40482. BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
40483. BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
40484. BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
40485. BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
40486. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
40487. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
40488. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
40489. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
40490. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
40491. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
40492. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
40493. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
40494. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
40495. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
40496. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
40497. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
40498. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
40499. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
40500. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
40501. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
40502. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
40503. BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
40504. BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
40505. BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
40506. BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
40507. BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
40508. BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
40509. BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
40510. BIFPLR2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
40511. BIFPLR2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
40512. BIFPLR2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
40513. BIFPLR2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
40514. BIFPLR2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
40515. BIFPLR2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
40516. BIFPLR2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
40517. BIFPLR2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
40518. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
40519. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
40520. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
40521. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
40522. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
40523. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
40524. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
40525. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
40526. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
40527. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
40528. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
40529. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
40530. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
40531. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
40532. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
40533. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
40534. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
40535. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
40536. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
40537. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
40538. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
40539. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
40540. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
40541. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
40542. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
40543. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
40544. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
40545. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
40546. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
40547. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
40548. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
40549. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
40550. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
40551. BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
40552. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
40553. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
40554. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
40555. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
40556. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
40557. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
40558. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
40559. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
40560. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
40561. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
40562. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
40563. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
40564. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
40565. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
40566. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
40567. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
40568. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
40569. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
40570. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
40571. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
40572. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
40573. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
40574. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
40575. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
40576. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
40577. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
40578. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
40579. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
40580. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
40581. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
40582. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
40583. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
40584. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
40585. BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
40586. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
40587. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
40588. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
40589. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
40590. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
40591. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
40592. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
40593. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
40594. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
40595. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
40596. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
40597. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
40598. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
40599. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
40600. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
40601. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
40602. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
40603. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
40604. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
40605. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
40606. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
40607. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
40608. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
40609. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
40610. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
40611. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
40612. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
40613. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
40614. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
40615. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
40616. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
40617. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
40618. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
40619. BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
40620. BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
40621. BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
40622. BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
40623. BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
40624. BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
40625. BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
40626. BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
40627. BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
40628. BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
40629. BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
40630. BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
40631. BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
40632. BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
40633. BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
40634. BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
40635. BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
40636. BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
40637. BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
40638. BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
40639. BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
40640. BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
40641. BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
40642. BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
40643. BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
40644. BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
40645. BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
40646. BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
40647. BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
40648. BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
40649. BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
40650. BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
40651. BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
40652. BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
40653. BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
40654. BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
40655. BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
40656. BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
40657. BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
40658. BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
40659. BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
40660. BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
40661. BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
40662. BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
40663. BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
40664. BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
40665. BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
40666. BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
40667. BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
40668. BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
40669. BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
40670. BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
40671. BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
40672. BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
40673. BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
40674. BIFPLR2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
40675. BIFPLR2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
40676. BIFPLR2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
40677. BIFPLR2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
40678. BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
40679. BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
40680. BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
40681. BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
40682. BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
40683. BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
40684. BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
40685. BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
40686. BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
40687. BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
40688. BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
40689. BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
40690. BIFPLR2_2_PMI_CAP_LIST__CAP_ID_MASK
40691. BIFPLR2_2_PMI_CAP_LIST__CAP_ID__SHIFT
40692. BIFPLR2_2_PMI_CAP_LIST__NEXT_PTR_MASK
40693. BIFPLR2_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
40694. BIFPLR2_2_PMI_CAP__AUX_CURRENT_MASK
40695. BIFPLR2_2_PMI_CAP__AUX_CURRENT__SHIFT
40696. BIFPLR2_2_PMI_CAP__D1_SUPPORT_MASK
40697. BIFPLR2_2_PMI_CAP__D1_SUPPORT__SHIFT
40698. BIFPLR2_2_PMI_CAP__D2_SUPPORT_MASK
40699. BIFPLR2_2_PMI_CAP__D2_SUPPORT__SHIFT
40700. BIFPLR2_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
40701. BIFPLR2_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
40702. BIFPLR2_2_PMI_CAP__PME_CLOCK_MASK
40703. BIFPLR2_2_PMI_CAP__PME_CLOCK__SHIFT
40704. BIFPLR2_2_PMI_CAP__PME_SUPPORT_MASK
40705. BIFPLR2_2_PMI_CAP__PME_SUPPORT__SHIFT
40706. BIFPLR2_2_PMI_CAP__VERSION_MASK
40707. BIFPLR2_2_PMI_CAP__VERSION__SHIFT
40708. BIFPLR2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
40709. BIFPLR2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
40710. BIFPLR2_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
40711. BIFPLR2_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
40712. BIFPLR2_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
40713. BIFPLR2_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
40714. BIFPLR2_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
40715. BIFPLR2_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
40716. BIFPLR2_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
40717. BIFPLR2_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
40718. BIFPLR2_2_PMI_STATUS_CNTL__PME_EN_MASK
40719. BIFPLR2_2_PMI_STATUS_CNTL__PME_EN__SHIFT
40720. BIFPLR2_2_PMI_STATUS_CNTL__PME_STATUS_MASK
40721. BIFPLR2_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
40722. BIFPLR2_2_PMI_STATUS_CNTL__PMI_DATA_MASK
40723. BIFPLR2_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
40724. BIFPLR2_2_PMI_STATUS_CNTL__POWER_STATE_MASK
40725. BIFPLR2_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
40726. BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
40727. BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
40728. BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
40729. BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
40730. BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
40731. BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
40732. BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
40733. BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
40734. BIFPLR2_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
40735. BIFPLR2_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
40736. BIFPLR2_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
40737. BIFPLR2_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
40738. BIFPLR2_2_PROG_INTERFACE__PROG_INTERFACE_MASK
40739. BIFPLR2_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
40740. BIFPLR2_2_REVISION_ID__MAJOR_REV_ID_MASK
40741. BIFPLR2_2_REVISION_ID__MAJOR_REV_ID__SHIFT
40742. BIFPLR2_2_REVISION_ID__MINOR_REV_ID_MASK
40743. BIFPLR2_2_REVISION_ID__MINOR_REV_ID__SHIFT
40744. BIFPLR2_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
40745. BIFPLR2_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
40746. BIFPLR2_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
40747. BIFPLR2_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
40748. BIFPLR2_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK
40749. BIFPLR2_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
40750. BIFPLR2_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
40751. BIFPLR2_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
40752. BIFPLR2_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
40753. BIFPLR2_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
40754. BIFPLR2_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
40755. BIFPLR2_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
40756. BIFPLR2_2_ROOT_STATUS__PME_PENDING_MASK
40757. BIFPLR2_2_ROOT_STATUS__PME_PENDING__SHIFT
40758. BIFPLR2_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK
40759. BIFPLR2_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
40760. BIFPLR2_2_ROOT_STATUS__PME_STATUS_MASK
40761. BIFPLR2_2_ROOT_STATUS__PME_STATUS__SHIFT
40762. BIFPLR2_2_SECONDARY_STATUS__CAP_LIST_MASK
40763. BIFPLR2_2_SECONDARY_STATUS__CAP_LIST__SHIFT
40764. BIFPLR2_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK
40765. BIFPLR2_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
40766. BIFPLR2_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
40767. BIFPLR2_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
40768. BIFPLR2_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
40769. BIFPLR2_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
40770. BIFPLR2_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
40771. BIFPLR2_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
40772. BIFPLR2_2_SECONDARY_STATUS__PCI_66_EN_MASK
40773. BIFPLR2_2_SECONDARY_STATUS__PCI_66_EN__SHIFT
40774. BIFPLR2_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
40775. BIFPLR2_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
40776. BIFPLR2_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
40777. BIFPLR2_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
40778. BIFPLR2_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
40779. BIFPLR2_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
40780. BIFPLR2_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
40781. BIFPLR2_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
40782. BIFPLR2_2_SLOT_CAP2__RESERVED_MASK
40783. BIFPLR2_2_SLOT_CAP2__RESERVED__SHIFT
40784. BIFPLR2_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
40785. BIFPLR2_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
40786. BIFPLR2_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
40787. BIFPLR2_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
40788. BIFPLR2_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
40789. BIFPLR2_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
40790. BIFPLR2_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK
40791. BIFPLR2_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
40792. BIFPLR2_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK
40793. BIFPLR2_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
40794. BIFPLR2_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
40795. BIFPLR2_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
40796. BIFPLR2_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
40797. BIFPLR2_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
40798. BIFPLR2_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
40799. BIFPLR2_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
40800. BIFPLR2_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
40801. BIFPLR2_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
40802. BIFPLR2_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
40803. BIFPLR2_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
40804. BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
40805. BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
40806. BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
40807. BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
40808. BIFPLR2_2_SLOT_CNTL2__RESERVED_MASK
40809. BIFPLR2_2_SLOT_CNTL2__RESERVED__SHIFT
40810. BIFPLR2_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
40811. BIFPLR2_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
40812. BIFPLR2_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
40813. BIFPLR2_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
40814. BIFPLR2_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
40815. BIFPLR2_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
40816. BIFPLR2_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
40817. BIFPLR2_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
40818. BIFPLR2_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
40819. BIFPLR2_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
40820. BIFPLR2_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
40821. BIFPLR2_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
40822. BIFPLR2_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
40823. BIFPLR2_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
40824. BIFPLR2_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
40825. BIFPLR2_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
40826. BIFPLR2_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
40827. BIFPLR2_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
40828. BIFPLR2_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
40829. BIFPLR2_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
40830. BIFPLR2_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
40831. BIFPLR2_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
40832. BIFPLR2_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
40833. BIFPLR2_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
40834. BIFPLR2_2_SLOT_STATUS2__RESERVED_MASK
40835. BIFPLR2_2_SLOT_STATUS2__RESERVED__SHIFT
40836. BIFPLR2_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
40837. BIFPLR2_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
40838. BIFPLR2_2_SLOT_STATUS__COMMAND_COMPLETED_MASK
40839. BIFPLR2_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
40840. BIFPLR2_2_SLOT_STATUS__DL_STATE_CHANGED_MASK
40841. BIFPLR2_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
40842. BIFPLR2_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
40843. BIFPLR2_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
40844. BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
40845. BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
40846. BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK
40847. BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
40848. BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
40849. BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
40850. BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
40851. BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
40852. BIFPLR2_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
40853. BIFPLR2_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
40854. BIFPLR2_2_SSID_CAP_LIST__CAP_ID_MASK
40855. BIFPLR2_2_SSID_CAP_LIST__CAP_ID__SHIFT
40856. BIFPLR2_2_SSID_CAP_LIST__NEXT_PTR_MASK
40857. BIFPLR2_2_SSID_CAP_LIST__NEXT_PTR__SHIFT
40858. BIFPLR2_2_SSID_CAP__SUBSYSTEM_ID_MASK
40859. BIFPLR2_2_SSID_CAP__SUBSYSTEM_ID__SHIFT
40860. BIFPLR2_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
40861. BIFPLR2_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
40862. BIFPLR2_2_STATUS__CAP_LIST_MASK
40863. BIFPLR2_2_STATUS__CAP_LIST__SHIFT
40864. BIFPLR2_2_STATUS__DEVSEL_TIMING_MASK
40865. BIFPLR2_2_STATUS__DEVSEL_TIMING__SHIFT
40866. BIFPLR2_2_STATUS__FAST_BACK_CAPABLE_MASK
40867. BIFPLR2_2_STATUS__FAST_BACK_CAPABLE__SHIFT
40868. BIFPLR2_2_STATUS__INT_STATUS_MASK
40869. BIFPLR2_2_STATUS__INT_STATUS__SHIFT
40870. BIFPLR2_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
40871. BIFPLR2_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
40872. BIFPLR2_2_STATUS__PARITY_ERROR_DETECTED_MASK
40873. BIFPLR2_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
40874. BIFPLR2_2_STATUS__PCI_66_EN_MASK
40875. BIFPLR2_2_STATUS__PCI_66_EN__SHIFT
40876. BIFPLR2_2_STATUS__RECEIVED_MASTER_ABORT_MASK
40877. BIFPLR2_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
40878. BIFPLR2_2_STATUS__RECEIVED_TARGET_ABORT_MASK
40879. BIFPLR2_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
40880. BIFPLR2_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
40881. BIFPLR2_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
40882. BIFPLR2_2_STATUS__SIGNAL_TARGET_ABORT_MASK
40883. BIFPLR2_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
40884. BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
40885. BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
40886. BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
40887. BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
40888. BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
40889. BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
40890. BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
40891. BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
40892. BIFPLR2_2_SUB_CLASS__SUB_CLASS_MASK
40893. BIFPLR2_2_SUB_CLASS__SUB_CLASS__SHIFT
40894. BIFPLR2_2_VENDOR_ID__VENDOR_ID_MASK
40895. BIFPLR2_2_VENDOR_ID__VENDOR_ID__SHIFT
40896. BIFPLR3_0_BASE_CLASS__BASE_CLASS_MASK
40897. BIFPLR3_0_BASE_CLASS__BASE_CLASS__SHIFT
40898. BIFPLR3_0_BIST__BIST_CAP_MASK
40899. BIFPLR3_0_BIST__BIST_CAP__SHIFT
40900. BIFPLR3_0_BIST__BIST_COMP_MASK
40901. BIFPLR3_0_BIST__BIST_COMP__SHIFT
40902. BIFPLR3_0_BIST__BIST_STRT_MASK
40903. BIFPLR3_0_BIST__BIST_STRT__SHIFT
40904. BIFPLR3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
40905. BIFPLR3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
40906. BIFPLR3_0_CAP_PTR__CAP_PTR_MASK
40907. BIFPLR3_0_CAP_PTR__CAP_PTR__SHIFT
40908. BIFPLR3_0_COMMAND__AD_STEPPING_MASK
40909. BIFPLR3_0_COMMAND__AD_STEPPING__SHIFT
40910. BIFPLR3_0_COMMAND__BUS_MASTER_EN_MASK
40911. BIFPLR3_0_COMMAND__BUS_MASTER_EN__SHIFT
40912. BIFPLR3_0_COMMAND__FAST_B2B_EN_MASK
40913. BIFPLR3_0_COMMAND__FAST_B2B_EN__SHIFT
40914. BIFPLR3_0_COMMAND__INT_DIS_MASK
40915. BIFPLR3_0_COMMAND__INT_DIS__SHIFT
40916. BIFPLR3_0_COMMAND__IO_ACCESS_EN_MASK
40917. BIFPLR3_0_COMMAND__IO_ACCESS_EN__SHIFT
40918. BIFPLR3_0_COMMAND__MEM_ACCESS_EN_MASK
40919. BIFPLR3_0_COMMAND__MEM_ACCESS_EN__SHIFT
40920. BIFPLR3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
40921. BIFPLR3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
40922. BIFPLR3_0_COMMAND__PAL_SNOOP_EN_MASK
40923. BIFPLR3_0_COMMAND__PAL_SNOOP_EN__SHIFT
40924. BIFPLR3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
40925. BIFPLR3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
40926. BIFPLR3_0_COMMAND__SERR_EN_MASK
40927. BIFPLR3_0_COMMAND__SERR_EN__SHIFT
40928. BIFPLR3_0_COMMAND__SPECIAL_CYCLE_EN_MASK
40929. BIFPLR3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
40930. BIFPLR3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
40931. BIFPLR3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
40932. BIFPLR3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
40933. BIFPLR3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
40934. BIFPLR3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
40935. BIFPLR3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
40936. BIFPLR3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
40937. BIFPLR3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
40938. BIFPLR3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
40939. BIFPLR3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
40940. BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
40941. BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
40942. BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
40943. BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
40944. BIFPLR3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
40945. BIFPLR3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
40946. BIFPLR3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
40947. BIFPLR3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
40948. BIFPLR3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
40949. BIFPLR3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
40950. BIFPLR3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
40951. BIFPLR3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
40952. BIFPLR3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
40953. BIFPLR3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
40954. BIFPLR3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
40955. BIFPLR3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
40956. BIFPLR3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
40957. BIFPLR3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
40958. BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
40959. BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
40960. BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
40961. BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
40962. BIFPLR3_0_DEVICE_CAP__EXTENDED_TAG_MASK
40963. BIFPLR3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
40964. BIFPLR3_0_DEVICE_CAP__FLR_CAPABLE_MASK
40965. BIFPLR3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
40966. BIFPLR3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
40967. BIFPLR3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
40968. BIFPLR3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
40969. BIFPLR3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
40970. BIFPLR3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
40971. BIFPLR3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
40972. BIFPLR3_0_DEVICE_CAP__PHANTOM_FUNC_MASK
40973. BIFPLR3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
40974. BIFPLR3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
40975. BIFPLR3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
40976. BIFPLR3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
40977. BIFPLR3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
40978. BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
40979. BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
40980. BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
40981. BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
40982. BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
40983. BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
40984. BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
40985. BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
40986. BIFPLR3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
40987. BIFPLR3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
40988. BIFPLR3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
40989. BIFPLR3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
40990. BIFPLR3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
40991. BIFPLR3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
40992. BIFPLR3_0_DEVICE_CNTL2__LTR_EN_MASK
40993. BIFPLR3_0_DEVICE_CNTL2__LTR_EN__SHIFT
40994. BIFPLR3_0_DEVICE_CNTL2__OBFF_EN_MASK
40995. BIFPLR3_0_DEVICE_CNTL2__OBFF_EN__SHIFT
40996. BIFPLR3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
40997. BIFPLR3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
40998. BIFPLR3_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
40999. BIFPLR3_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
41000. BIFPLR3_0_DEVICE_CNTL__CORR_ERR_EN_MASK
41001. BIFPLR3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
41002. BIFPLR3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
41003. BIFPLR3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
41004. BIFPLR3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
41005. BIFPLR3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
41006. BIFPLR3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
41007. BIFPLR3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
41008. BIFPLR3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
41009. BIFPLR3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
41010. BIFPLR3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
41011. BIFPLR3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
41012. BIFPLR3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
41013. BIFPLR3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
41014. BIFPLR3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
41015. BIFPLR3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
41016. BIFPLR3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
41017. BIFPLR3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
41018. BIFPLR3_0_DEVICE_CNTL__USR_REPORT_EN_MASK
41019. BIFPLR3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
41020. BIFPLR3_0_DEVICE_ID__DEVICE_ID_MASK
41021. BIFPLR3_0_DEVICE_ID__DEVICE_ID__SHIFT
41022. BIFPLR3_0_DEVICE_STATUS2__RESERVED_MASK
41023. BIFPLR3_0_DEVICE_STATUS2__RESERVED__SHIFT
41024. BIFPLR3_0_DEVICE_STATUS__AUX_PWR_MASK
41025. BIFPLR3_0_DEVICE_STATUS__AUX_PWR__SHIFT
41026. BIFPLR3_0_DEVICE_STATUS__CORR_ERR_MASK
41027. BIFPLR3_0_DEVICE_STATUS__CORR_ERR__SHIFT
41028. BIFPLR3_0_DEVICE_STATUS__FATAL_ERR_MASK
41029. BIFPLR3_0_DEVICE_STATUS__FATAL_ERR__SHIFT
41030. BIFPLR3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
41031. BIFPLR3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
41032. BIFPLR3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
41033. BIFPLR3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
41034. BIFPLR3_0_DEVICE_STATUS__USR_DETECTED_MASK
41035. BIFPLR3_0_DEVICE_STATUS__USR_DETECTED__SHIFT
41036. BIFPLR3_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
41037. BIFPLR3_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
41038. BIFPLR3_0_HEADER__DEVICE_TYPE_MASK
41039. BIFPLR3_0_HEADER__DEVICE_TYPE__SHIFT
41040. BIFPLR3_0_HEADER__HEADER_TYPE_MASK
41041. BIFPLR3_0_HEADER__HEADER_TYPE__SHIFT
41042. BIFPLR3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
41043. BIFPLR3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
41044. BIFPLR3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
41045. BIFPLR3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
41046. BIFPLR3_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
41047. BIFPLR3_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
41048. BIFPLR3_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
41049. BIFPLR3_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
41050. BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_MASK
41051. BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
41052. BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
41053. BIFPLR3_0_IO_BASE_LIMIT__IO_BASE__SHIFT
41054. BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_MASK
41055. BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
41056. BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
41057. BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT
41058. BIFPLR3_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
41059. BIFPLR3_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
41060. BIFPLR3_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK
41061. BIFPLR3_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
41062. BIFPLR3_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
41063. BIFPLR3_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
41064. BIFPLR3_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
41065. BIFPLR3_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
41066. BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
41067. BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
41068. BIFPLR3_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK
41069. BIFPLR3_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
41070. BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
41071. BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
41072. BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK
41073. BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
41074. BIFPLR3_0_LATENCY__LATENCY_TIMER_MASK
41075. BIFPLR3_0_LATENCY__LATENCY_TIMER__SHIFT
41076. BIFPLR3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
41077. BIFPLR3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
41078. BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
41079. BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
41080. BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
41081. BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
41082. BIFPLR3_0_LINK_CAP2__RESERVED_MASK
41083. BIFPLR3_0_LINK_CAP2__RESERVED__SHIFT
41084. BIFPLR3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
41085. BIFPLR3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
41086. BIFPLR3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
41087. BIFPLR3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
41088. BIFPLR3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
41089. BIFPLR3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
41090. BIFPLR3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
41091. BIFPLR3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
41092. BIFPLR3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
41093. BIFPLR3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
41094. BIFPLR3_0_LINK_CAP__L1_EXIT_LATENCY_MASK
41095. BIFPLR3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
41096. BIFPLR3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
41097. BIFPLR3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
41098. BIFPLR3_0_LINK_CAP__LINK_SPEED_MASK
41099. BIFPLR3_0_LINK_CAP__LINK_SPEED__SHIFT
41100. BIFPLR3_0_LINK_CAP__LINK_WIDTH_MASK
41101. BIFPLR3_0_LINK_CAP__LINK_WIDTH__SHIFT
41102. BIFPLR3_0_LINK_CAP__PM_SUPPORT_MASK
41103. BIFPLR3_0_LINK_CAP__PM_SUPPORT__SHIFT
41104. BIFPLR3_0_LINK_CAP__PORT_NUMBER_MASK
41105. BIFPLR3_0_LINK_CAP__PORT_NUMBER__SHIFT
41106. BIFPLR3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
41107. BIFPLR3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
41108. BIFPLR3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
41109. BIFPLR3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
41110. BIFPLR3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
41111. BIFPLR3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
41112. BIFPLR3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
41113. BIFPLR3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
41114. BIFPLR3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
41115. BIFPLR3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
41116. BIFPLR3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
41117. BIFPLR3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
41118. BIFPLR3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
41119. BIFPLR3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
41120. BIFPLR3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
41121. BIFPLR3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
41122. BIFPLR3_0_LINK_CNTL2__XMIT_MARGIN_MASK
41123. BIFPLR3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
41124. BIFPLR3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
41125. BIFPLR3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
41126. BIFPLR3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
41127. BIFPLR3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
41128. BIFPLR3_0_LINK_CNTL__EXTENDED_SYNC_MASK
41129. BIFPLR3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
41130. BIFPLR3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
41131. BIFPLR3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
41132. BIFPLR3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
41133. BIFPLR3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
41134. BIFPLR3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
41135. BIFPLR3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
41136. BIFPLR3_0_LINK_CNTL__LINK_DIS_MASK
41137. BIFPLR3_0_LINK_CNTL__LINK_DIS__SHIFT
41138. BIFPLR3_0_LINK_CNTL__PM_CONTROL_MASK
41139. BIFPLR3_0_LINK_CNTL__PM_CONTROL__SHIFT
41140. BIFPLR3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
41141. BIFPLR3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
41142. BIFPLR3_0_LINK_CNTL__RETRAIN_LINK_MASK
41143. BIFPLR3_0_LINK_CNTL__RETRAIN_LINK__SHIFT
41144. BIFPLR3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
41145. BIFPLR3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
41146. BIFPLR3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
41147. BIFPLR3_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
41148. BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
41149. BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
41150. BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
41151. BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
41152. BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
41153. BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
41154. BIFPLR3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
41155. BIFPLR3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
41156. BIFPLR3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
41157. BIFPLR3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
41158. BIFPLR3_0_LINK_STATUS__DL_ACTIVE_MASK
41159. BIFPLR3_0_LINK_STATUS__DL_ACTIVE__SHIFT
41160. BIFPLR3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
41161. BIFPLR3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
41162. BIFPLR3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
41163. BIFPLR3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
41164. BIFPLR3_0_LINK_STATUS__LINK_TRAINING_MASK
41165. BIFPLR3_0_LINK_STATUS__LINK_TRAINING__SHIFT
41166. BIFPLR3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
41167. BIFPLR3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
41168. BIFPLR3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
41169. BIFPLR3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
41170. BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
41171. BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
41172. BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
41173. BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
41174. BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
41175. BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
41176. BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
41177. BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
41178. BIFPLR3_0_MSI_CAP_LIST__CAP_ID_MASK
41179. BIFPLR3_0_MSI_CAP_LIST__CAP_ID__SHIFT
41180. BIFPLR3_0_MSI_CAP_LIST__NEXT_PTR_MASK
41181. BIFPLR3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
41182. BIFPLR3_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
41183. BIFPLR3_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
41184. BIFPLR3_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
41185. BIFPLR3_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
41186. BIFPLR3_0_MSI_MAP_CAP_LIST__CAP_ID_MASK
41187. BIFPLR3_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
41188. BIFPLR3_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
41189. BIFPLR3_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
41190. BIFPLR3_0_MSI_MAP_CAP__CAP_TYPE_MASK
41191. BIFPLR3_0_MSI_MAP_CAP__CAP_TYPE__SHIFT
41192. BIFPLR3_0_MSI_MAP_CAP__EN_MASK
41193. BIFPLR3_0_MSI_MAP_CAP__EN__SHIFT
41194. BIFPLR3_0_MSI_MAP_CAP__FIXD_MASK
41195. BIFPLR3_0_MSI_MAP_CAP__FIXD__SHIFT
41196. BIFPLR3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
41197. BIFPLR3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
41198. BIFPLR3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
41199. BIFPLR3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
41200. BIFPLR3_0_MSI_MSG_CNTL__MSI_64BIT_MASK
41201. BIFPLR3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
41202. BIFPLR3_0_MSI_MSG_CNTL__MSI_EN_MASK
41203. BIFPLR3_0_MSI_MSG_CNTL__MSI_EN__SHIFT
41204. BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
41205. BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
41206. BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
41207. BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
41208. BIFPLR3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
41209. BIFPLR3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
41210. BIFPLR3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
41211. BIFPLR3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
41212. BIFPLR3_0_MSI_MSG_DATA__MSI_DATA_MASK
41213. BIFPLR3_0_MSI_MSG_DATA__MSI_DATA__SHIFT
41214. BIFPLR3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
41215. BIFPLR3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
41216. BIFPLR3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
41217. BIFPLR3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
41218. BIFPLR3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
41219. BIFPLR3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
41220. BIFPLR3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
41221. BIFPLR3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
41222. BIFPLR3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
41223. BIFPLR3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
41224. BIFPLR3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
41225. BIFPLR3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
41226. BIFPLR3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
41227. BIFPLR3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
41228. BIFPLR3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
41229. BIFPLR3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
41230. BIFPLR3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
41231. BIFPLR3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
41232. BIFPLR3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
41233. BIFPLR3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
41234. BIFPLR3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
41235. BIFPLR3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
41236. BIFPLR3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
41237. BIFPLR3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
41238. BIFPLR3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
41239. BIFPLR3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
41240. BIFPLR3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
41241. BIFPLR3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
41242. BIFPLR3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
41243. BIFPLR3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
41244. BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
41245. BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
41246. BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
41247. BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
41248. BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
41249. BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
41250. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
41251. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
41252. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
41253. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
41254. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
41255. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
41256. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
41257. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
41258. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
41259. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
41260. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
41261. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
41262. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
41263. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
41264. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
41265. BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
41266. BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
41267. BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
41268. BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
41269. BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
41270. BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
41271. BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
41272. BIFPLR3_0_PCIE_CAP_LIST__CAP_ID_MASK
41273. BIFPLR3_0_PCIE_CAP_LIST__CAP_ID__SHIFT
41274. BIFPLR3_0_PCIE_CAP_LIST__NEXT_PTR_MASK
41275. BIFPLR3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
41276. BIFPLR3_0_PCIE_CAP__DEVICE_TYPE_MASK
41277. BIFPLR3_0_PCIE_CAP__DEVICE_TYPE__SHIFT
41278. BIFPLR3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
41279. BIFPLR3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
41280. BIFPLR3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
41281. BIFPLR3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
41282. BIFPLR3_0_PCIE_CAP__VERSION_MASK
41283. BIFPLR3_0_PCIE_CAP__VERSION__SHIFT
41284. BIFPLR3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
41285. BIFPLR3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
41286. BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
41287. BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
41288. BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
41289. BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
41290. BIFPLR3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
41291. BIFPLR3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
41292. BIFPLR3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
41293. BIFPLR3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
41294. BIFPLR3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
41295. BIFPLR3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
41296. BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
41297. BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
41298. BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
41299. BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
41300. BIFPLR3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
41301. BIFPLR3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
41302. BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
41303. BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
41304. BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
41305. BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
41306. BIFPLR3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
41307. BIFPLR3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
41308. BIFPLR3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
41309. BIFPLR3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
41310. BIFPLR3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
41311. BIFPLR3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
41312. BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
41313. BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
41314. BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
41315. BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
41316. BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
41317. BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
41318. BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
41319. BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
41320. BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
41321. BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
41322. BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
41323. BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
41324. BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
41325. BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
41326. BIFPLR3_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
41327. BIFPLR3_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
41328. BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
41329. BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
41330. BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
41331. BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
41332. BIFPLR3_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
41333. BIFPLR3_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
41334. BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
41335. BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
41336. BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
41337. BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
41338. BIFPLR3_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
41339. BIFPLR3_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
41340. BIFPLR3_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
41341. BIFPLR3_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
41342. BIFPLR3_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
41343. BIFPLR3_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
41344. BIFPLR3_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
41345. BIFPLR3_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
41346. BIFPLR3_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
41347. BIFPLR3_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
41348. BIFPLR3_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
41349. BIFPLR3_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
41350. BIFPLR3_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
41351. BIFPLR3_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
41352. BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
41353. BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
41354. BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
41355. BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
41356. BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
41357. BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
41358. BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
41359. BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
41360. BIFPLR3_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
41361. BIFPLR3_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
41362. BIFPLR3_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
41363. BIFPLR3_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
41364. BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
41365. BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
41366. BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
41367. BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
41368. BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
41369. BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
41370. BIFPLR3_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
41371. BIFPLR3_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
41372. BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
41373. BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
41374. BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
41375. BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
41376. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK
41377. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
41378. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK
41379. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
41380. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK
41381. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
41382. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK
41383. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
41384. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK
41385. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
41386. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK
41387. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
41388. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK
41389. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
41390. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK
41391. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
41392. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK
41393. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
41394. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK
41395. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
41396. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK
41397. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
41398. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK
41399. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
41400. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK
41401. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
41402. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK
41403. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
41404. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK
41405. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
41406. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK
41407. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
41408. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK
41409. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
41410. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK
41411. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
41412. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK
41413. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
41414. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK
41415. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
41416. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK
41417. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
41418. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK
41419. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
41420. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK
41421. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
41422. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK
41423. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
41424. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK
41425. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
41426. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK
41427. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
41428. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK
41429. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
41430. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK
41431. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
41432. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK
41433. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
41434. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK
41435. BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
41436. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK
41437. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
41438. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK
41439. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
41440. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK
41441. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
41442. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK
41443. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
41444. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK
41445. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
41446. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK
41447. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
41448. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK
41449. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
41450. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK
41451. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
41452. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK
41453. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
41454. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK
41455. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
41456. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK
41457. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
41458. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK
41459. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
41460. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK
41461. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
41462. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK
41463. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
41464. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK
41465. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
41466. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK
41467. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
41468. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK
41469. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
41470. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK
41471. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
41472. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK
41473. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
41474. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK
41475. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
41476. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK
41477. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
41478. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK
41479. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
41480. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK
41481. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
41482. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK
41483. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
41484. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK
41485. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
41486. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK
41487. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
41488. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK
41489. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
41490. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK
41491. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
41492. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK
41493. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
41494. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK
41495. BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
41496. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK
41497. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
41498. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK
41499. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
41500. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK
41501. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
41502. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK
41503. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
41504. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK
41505. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
41506. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK
41507. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
41508. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK
41509. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
41510. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK
41511. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
41512. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK
41513. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
41514. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK
41515. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
41516. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK
41517. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
41518. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK
41519. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
41520. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK
41521. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
41522. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK
41523. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
41524. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK
41525. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
41526. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK
41527. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
41528. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK
41529. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
41530. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK
41531. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
41532. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK
41533. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
41534. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK
41535. BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
41536. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK
41537. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
41538. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK
41539. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
41540. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK
41541. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
41542. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK
41543. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
41544. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK
41545. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
41546. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK
41547. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
41548. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK
41549. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
41550. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK
41551. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
41552. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK
41553. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
41554. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK
41555. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
41556. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK
41557. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
41558. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK
41559. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
41560. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK
41561. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
41562. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK
41563. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
41564. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK
41565. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
41566. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK
41567. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
41568. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK
41569. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
41570. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK
41571. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
41572. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK
41573. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
41574. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK
41575. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
41576. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK
41577. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
41578. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK
41579. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
41580. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK
41581. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
41582. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK
41583. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
41584. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK
41585. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
41586. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK
41587. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
41588. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK
41589. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
41590. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK
41591. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
41592. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK
41593. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
41594. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK
41595. BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
41596. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK
41597. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
41598. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK
41599. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
41600. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK
41601. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
41602. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK
41603. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
41604. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK
41605. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
41606. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK
41607. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
41608. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK
41609. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
41610. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK
41611. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
41612. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK
41613. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
41614. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK
41615. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
41616. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK
41617. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
41618. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK
41619. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
41620. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK
41621. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
41622. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK
41623. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
41624. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK
41625. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
41626. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK
41627. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
41628. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK
41629. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
41630. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK
41631. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
41632. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK
41633. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
41634. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK
41635. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
41636. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK
41637. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
41638. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK
41639. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
41640. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK
41641. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
41642. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK
41643. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
41644. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK
41645. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
41646. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK
41647. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
41648. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK
41649. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
41650. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK
41651. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
41652. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK
41653. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
41654. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK
41655. BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
41656. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK
41657. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
41658. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK
41659. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
41660. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK
41661. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
41662. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK
41663. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
41664. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK
41665. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
41666. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK
41667. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
41668. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK
41669. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
41670. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK
41671. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
41672. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK
41673. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
41674. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK
41675. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
41676. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK
41677. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
41678. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK
41679. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
41680. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK
41681. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
41682. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK
41683. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
41684. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK
41685. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
41686. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK
41687. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
41688. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK
41689. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
41690. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK
41691. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
41692. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK
41693. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
41694. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK
41695. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
41696. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK
41697. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
41698. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK
41699. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
41700. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK
41701. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
41702. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK
41703. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
41704. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK
41705. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
41706. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK
41707. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
41708. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK
41709. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
41710. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK
41711. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
41712. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK
41713. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
41714. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK
41715. BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
41716. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK
41717. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
41718. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK
41719. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
41720. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK
41721. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
41722. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK
41723. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
41724. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK
41725. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
41726. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK
41727. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
41728. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK
41729. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
41730. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK
41731. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
41732. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK
41733. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
41734. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK
41735. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
41736. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK
41737. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
41738. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK
41739. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
41740. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK
41741. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
41742. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK
41743. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
41744. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK
41745. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
41746. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK
41747. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
41748. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK
41749. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
41750. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK
41751. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
41752. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK
41753. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
41754. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK
41755. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
41756. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK
41757. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
41758. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK
41759. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
41760. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK
41761. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
41762. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK
41763. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
41764. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK
41765. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
41766. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK
41767. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
41768. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK
41769. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
41770. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK
41771. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
41772. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK
41773. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
41774. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK
41775. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
41776. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK
41777. BIFPLR3_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
41778. BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK
41779. BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
41780. BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK
41781. BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
41782. BIFPLR3_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
41783. BIFPLR3_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
41784. BIFPLR3_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK
41785. BIFPLR3_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
41786. BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
41787. BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
41788. BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
41789. BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
41790. BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
41791. BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
41792. BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
41793. BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
41794. BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
41795. BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
41796. BIFPLR3_0_PCIE_ESM_HEADER_2__CAP_ID_MASK
41797. BIFPLR3_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
41798. BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
41799. BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
41800. BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
41801. BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
41802. BIFPLR3_0_PCIE_HDR_LOG0__TLP_HDR_MASK
41803. BIFPLR3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
41804. BIFPLR3_0_PCIE_HDR_LOG1__TLP_HDR_MASK
41805. BIFPLR3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
41806. BIFPLR3_0_PCIE_HDR_LOG2__TLP_HDR_MASK
41807. BIFPLR3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
41808. BIFPLR3_0_PCIE_HDR_LOG3__TLP_HDR_MASK
41809. BIFPLR3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
41810. BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
41811. BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
41812. BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
41813. BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
41814. BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
41815. BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
41816. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
41817. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
41818. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
41819. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
41820. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
41821. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
41822. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
41823. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
41824. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
41825. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
41826. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
41827. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
41828. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
41829. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
41830. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
41831. BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
41832. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
41833. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
41834. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
41835. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
41836. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
41837. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
41838. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
41839. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
41840. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
41841. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
41842. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
41843. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
41844. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
41845. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
41846. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
41847. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
41848. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
41849. BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
41850. BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41851. BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41852. BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41853. BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41854. BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41855. BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41856. BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41857. BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41858. BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41859. BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41860. BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41861. BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41862. BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41863. BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41864. BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41865. BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41866. BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41867. BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41868. BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41869. BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41870. BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41871. BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41872. BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41873. BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41874. BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41875. BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41876. BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41877. BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41878. BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41879. BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41880. BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41881. BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41882. BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41883. BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41884. BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41885. BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41886. BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41887. BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41888. BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41889. BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41890. BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41891. BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41892. BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41893. BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41894. BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41895. BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41896. BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41897. BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41898. BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41899. BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41900. BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41901. BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41902. BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41903. BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41904. BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41905. BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41906. BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41907. BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41908. BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41909. BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41910. BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41911. BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41912. BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41913. BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41914. BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41915. BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41916. BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41917. BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41918. BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41919. BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41920. BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41921. BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41922. BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41923. BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41924. BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41925. BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41926. BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41927. BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41928. BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41929. BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41930. BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41931. BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41932. BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41933. BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41934. BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41935. BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41936. BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41937. BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41938. BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41939. BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41940. BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41941. BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41942. BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41943. BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41944. BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41945. BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41946. BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41947. BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41948. BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41949. BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41950. BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41951. BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41952. BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41953. BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41954. BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41955. BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41956. BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41957. BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41958. BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41959. BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41960. BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41961. BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41962. BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41963. BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41964. BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41965. BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41966. BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41967. BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41968. BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41969. BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41970. BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
41971. BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
41972. BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
41973. BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
41974. BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
41975. BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
41976. BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
41977. BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
41978. BIFPLR3_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
41979. BIFPLR3_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
41980. BIFPLR3_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
41981. BIFPLR3_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
41982. BIFPLR3_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
41983. BIFPLR3_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
41984. BIFPLR3_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
41985. BIFPLR3_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
41986. BIFPLR3_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
41987. BIFPLR3_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
41988. BIFPLR3_0_PCIE_LINK_CNTL3__RESERVED_MASK
41989. BIFPLR3_0_PCIE_LINK_CNTL3__RESERVED__SHIFT
41990. BIFPLR3_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
41991. BIFPLR3_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
41992. BIFPLR3_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
41993. BIFPLR3_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
41994. BIFPLR3_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
41995. BIFPLR3_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
41996. BIFPLR3_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
41997. BIFPLR3_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
41998. BIFPLR3_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
41999. BIFPLR3_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
42000. BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
42001. BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
42002. BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
42003. BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
42004. BIFPLR3_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
42005. BIFPLR3_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
42006. BIFPLR3_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK
42007. BIFPLR3_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
42008. BIFPLR3_0_PCIE_MC_CNTL__MC_ENABLE_MASK
42009. BIFPLR3_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT
42010. BIFPLR3_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
42011. BIFPLR3_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
42012. BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
42013. BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
42014. BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
42015. BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
42016. BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
42017. BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
42018. BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
42019. BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
42020. BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
42021. BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
42022. BIFPLR3_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
42023. BIFPLR3_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
42024. BIFPLR3_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
42025. BIFPLR3_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
42026. BIFPLR3_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
42027. BIFPLR3_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
42028. BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
42029. BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
42030. BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
42031. BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
42032. BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
42033. BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
42034. BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
42035. BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
42036. BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
42037. BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
42038. BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
42039. BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
42040. BIFPLR3_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
42041. BIFPLR3_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
42042. BIFPLR3_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
42043. BIFPLR3_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
42044. BIFPLR3_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
42045. BIFPLR3_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
42046. BIFPLR3_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
42047. BIFPLR3_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
42048. BIFPLR3_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
42049. BIFPLR3_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
42050. BIFPLR3_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
42051. BIFPLR3_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
42052. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
42053. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
42054. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
42055. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
42056. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
42057. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
42058. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
42059. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
42060. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
42061. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
42062. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
42063. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
42064. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
42065. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
42066. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
42067. BIFPLR3_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
42068. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
42069. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
42070. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
42071. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
42072. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
42073. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
42074. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
42075. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
42076. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
42077. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
42078. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
42079. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
42080. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
42081. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
42082. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
42083. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
42084. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
42085. BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
42086. BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
42087. BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
42088. BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
42089. BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
42090. BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
42091. BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
42092. BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
42093. BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
42094. BIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
42095. BIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
42096. BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
42097. BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
42098. BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK
42099. BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
42100. BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
42101. BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
42102. BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
42103. BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
42104. BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CTO_MASK
42105. BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
42106. BIFPLR3_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
42107. BIFPLR3_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
42108. BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
42109. BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
42110. BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK
42111. BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
42112. BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
42113. BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
42114. BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
42115. BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
42116. BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
42117. BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
42118. BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
42119. BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
42120. BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
42121. BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
42122. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
42123. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
42124. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
42125. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
42126. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
42127. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
42128. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
42129. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
42130. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
42131. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
42132. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
42133. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
42134. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
42135. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
42136. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
42137. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
42138. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
42139. BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
42140. BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
42141. BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
42142. BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
42143. BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
42144. BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
42145. BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
42146. BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
42147. BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
42148. BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK
42149. BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
42150. BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
42151. BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
42152. BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
42153. BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
42154. BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
42155. BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
42156. BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
42157. BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
42158. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
42159. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
42160. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
42161. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
42162. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
42163. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
42164. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
42165. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
42166. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
42167. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
42168. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
42169. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
42170. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
42171. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
42172. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
42173. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
42174. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
42175. BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
42176. BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
42177. BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
42178. BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
42179. BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
42180. BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
42181. BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
42182. BIFPLR3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
42183. BIFPLR3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
42184. BIFPLR3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
42185. BIFPLR3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
42186. BIFPLR3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
42187. BIFPLR3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
42188. BIFPLR3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
42189. BIFPLR3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
42190. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
42191. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
42192. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
42193. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
42194. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
42195. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
42196. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
42197. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
42198. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
42199. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
42200. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
42201. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
42202. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
42203. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
42204. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
42205. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
42206. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
42207. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
42208. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
42209. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
42210. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
42211. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
42212. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
42213. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
42214. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
42215. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
42216. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
42217. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
42218. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
42219. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
42220. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
42221. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
42222. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
42223. BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
42224. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
42225. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
42226. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
42227. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
42228. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
42229. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
42230. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
42231. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
42232. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
42233. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
42234. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
42235. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
42236. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
42237. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
42238. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
42239. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
42240. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
42241. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
42242. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
42243. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
42244. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
42245. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
42246. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
42247. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
42248. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
42249. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
42250. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
42251. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
42252. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
42253. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
42254. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
42255. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
42256. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
42257. BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
42258. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
42259. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
42260. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
42261. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
42262. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
42263. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
42264. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
42265. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
42266. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
42267. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
42268. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
42269. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
42270. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
42271. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
42272. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
42273. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
42274. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
42275. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
42276. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
42277. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
42278. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
42279. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
42280. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
42281. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
42282. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
42283. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
42284. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
42285. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
42286. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
42287. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
42288. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
42289. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
42290. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
42291. BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
42292. BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
42293. BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
42294. BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
42295. BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
42296. BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
42297. BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
42298. BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
42299. BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
42300. BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
42301. BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
42302. BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
42303. BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
42304. BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
42305. BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
42306. BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
42307. BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
42308. BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
42309. BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
42310. BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
42311. BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
42312. BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
42313. BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
42314. BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
42315. BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
42316. BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
42317. BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
42318. BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
42319. BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
42320. BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
42321. BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
42322. BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
42323. BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
42324. BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
42325. BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
42326. BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
42327. BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
42328. BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
42329. BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
42330. BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
42331. BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
42332. BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
42333. BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
42334. BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
42335. BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
42336. BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
42337. BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
42338. BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
42339. BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
42340. BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
42341. BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
42342. BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
42343. BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
42344. BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
42345. BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
42346. BIFPLR3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
42347. BIFPLR3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
42348. BIFPLR3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
42349. BIFPLR3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
42350. BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
42351. BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
42352. BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
42353. BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
42354. BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
42355. BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
42356. BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
42357. BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
42358. BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
42359. BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
42360. BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
42361. BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
42362. BIFPLR3_0_PMI_CAP_LIST__CAP_ID_MASK
42363. BIFPLR3_0_PMI_CAP_LIST__CAP_ID__SHIFT
42364. BIFPLR3_0_PMI_CAP_LIST__NEXT_PTR_MASK
42365. BIFPLR3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
42366. BIFPLR3_0_PMI_CAP__AUX_CURRENT_MASK
42367. BIFPLR3_0_PMI_CAP__AUX_CURRENT__SHIFT
42368. BIFPLR3_0_PMI_CAP__D1_SUPPORT_MASK
42369. BIFPLR3_0_PMI_CAP__D1_SUPPORT__SHIFT
42370. BIFPLR3_0_PMI_CAP__D2_SUPPORT_MASK
42371. BIFPLR3_0_PMI_CAP__D2_SUPPORT__SHIFT
42372. BIFPLR3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
42373. BIFPLR3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
42374. BIFPLR3_0_PMI_CAP__PME_CLOCK_MASK
42375. BIFPLR3_0_PMI_CAP__PME_CLOCK__SHIFT
42376. BIFPLR3_0_PMI_CAP__PME_SUPPORT_MASK
42377. BIFPLR3_0_PMI_CAP__PME_SUPPORT__SHIFT
42378. BIFPLR3_0_PMI_CAP__VERSION_MASK
42379. BIFPLR3_0_PMI_CAP__VERSION__SHIFT
42380. BIFPLR3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
42381. BIFPLR3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
42382. BIFPLR3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
42383. BIFPLR3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
42384. BIFPLR3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
42385. BIFPLR3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
42386. BIFPLR3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
42387. BIFPLR3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
42388. BIFPLR3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
42389. BIFPLR3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
42390. BIFPLR3_0_PMI_STATUS_CNTL__PME_EN_MASK
42391. BIFPLR3_0_PMI_STATUS_CNTL__PME_EN__SHIFT
42392. BIFPLR3_0_PMI_STATUS_CNTL__PME_STATUS_MASK
42393. BIFPLR3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
42394. BIFPLR3_0_PMI_STATUS_CNTL__PMI_DATA_MASK
42395. BIFPLR3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
42396. BIFPLR3_0_PMI_STATUS_CNTL__POWER_STATE_MASK
42397. BIFPLR3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
42398. BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
42399. BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
42400. BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
42401. BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
42402. BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
42403. BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
42404. BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
42405. BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
42406. BIFPLR3_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
42407. BIFPLR3_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
42408. BIFPLR3_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
42409. BIFPLR3_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
42410. BIFPLR3_0_PROG_INTERFACE__PROG_INTERFACE_MASK
42411. BIFPLR3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
42412. BIFPLR3_0_REVISION_ID__MAJOR_REV_ID_MASK
42413. BIFPLR3_0_REVISION_ID__MAJOR_REV_ID__SHIFT
42414. BIFPLR3_0_REVISION_ID__MINOR_REV_ID_MASK
42415. BIFPLR3_0_REVISION_ID__MINOR_REV_ID__SHIFT
42416. BIFPLR3_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
42417. BIFPLR3_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
42418. BIFPLR3_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
42419. BIFPLR3_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
42420. BIFPLR3_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK
42421. BIFPLR3_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
42422. BIFPLR3_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
42423. BIFPLR3_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
42424. BIFPLR3_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
42425. BIFPLR3_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
42426. BIFPLR3_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
42427. BIFPLR3_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
42428. BIFPLR3_0_ROOT_STATUS__PME_PENDING_MASK
42429. BIFPLR3_0_ROOT_STATUS__PME_PENDING__SHIFT
42430. BIFPLR3_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK
42431. BIFPLR3_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
42432. BIFPLR3_0_ROOT_STATUS__PME_STATUS_MASK
42433. BIFPLR3_0_ROOT_STATUS__PME_STATUS__SHIFT
42434. BIFPLR3_0_SECONDARY_STATUS__CAP_LIST_MASK
42435. BIFPLR3_0_SECONDARY_STATUS__CAP_LIST__SHIFT
42436. BIFPLR3_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK
42437. BIFPLR3_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
42438. BIFPLR3_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
42439. BIFPLR3_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
42440. BIFPLR3_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
42441. BIFPLR3_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
42442. BIFPLR3_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
42443. BIFPLR3_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
42444. BIFPLR3_0_SECONDARY_STATUS__PCI_66_EN_MASK
42445. BIFPLR3_0_SECONDARY_STATUS__PCI_66_EN__SHIFT
42446. BIFPLR3_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
42447. BIFPLR3_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
42448. BIFPLR3_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
42449. BIFPLR3_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
42450. BIFPLR3_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
42451. BIFPLR3_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
42452. BIFPLR3_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
42453. BIFPLR3_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
42454. BIFPLR3_0_SLOT_CAP2__RESERVED_MASK
42455. BIFPLR3_0_SLOT_CAP2__RESERVED__SHIFT
42456. BIFPLR3_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
42457. BIFPLR3_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
42458. BIFPLR3_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
42459. BIFPLR3_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
42460. BIFPLR3_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
42461. BIFPLR3_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
42462. BIFPLR3_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK
42463. BIFPLR3_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
42464. BIFPLR3_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK
42465. BIFPLR3_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
42466. BIFPLR3_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
42467. BIFPLR3_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
42468. BIFPLR3_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
42469. BIFPLR3_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
42470. BIFPLR3_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
42471. BIFPLR3_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
42472. BIFPLR3_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
42473. BIFPLR3_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
42474. BIFPLR3_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
42475. BIFPLR3_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
42476. BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
42477. BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
42478. BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
42479. BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
42480. BIFPLR3_0_SLOT_CNTL2__RESERVED_MASK
42481. BIFPLR3_0_SLOT_CNTL2__RESERVED__SHIFT
42482. BIFPLR3_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
42483. BIFPLR3_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
42484. BIFPLR3_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
42485. BIFPLR3_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
42486. BIFPLR3_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
42487. BIFPLR3_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
42488. BIFPLR3_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
42489. BIFPLR3_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
42490. BIFPLR3_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
42491. BIFPLR3_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
42492. BIFPLR3_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
42493. BIFPLR3_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
42494. BIFPLR3_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
42495. BIFPLR3_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
42496. BIFPLR3_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
42497. BIFPLR3_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
42498. BIFPLR3_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
42499. BIFPLR3_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
42500. BIFPLR3_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
42501. BIFPLR3_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
42502. BIFPLR3_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
42503. BIFPLR3_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
42504. BIFPLR3_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
42505. BIFPLR3_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
42506. BIFPLR3_0_SLOT_STATUS2__RESERVED_MASK
42507. BIFPLR3_0_SLOT_STATUS2__RESERVED__SHIFT
42508. BIFPLR3_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
42509. BIFPLR3_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
42510. BIFPLR3_0_SLOT_STATUS__COMMAND_COMPLETED_MASK
42511. BIFPLR3_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
42512. BIFPLR3_0_SLOT_STATUS__DL_STATE_CHANGED_MASK
42513. BIFPLR3_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
42514. BIFPLR3_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
42515. BIFPLR3_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
42516. BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
42517. BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
42518. BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK
42519. BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
42520. BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
42521. BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
42522. BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
42523. BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
42524. BIFPLR3_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
42525. BIFPLR3_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
42526. BIFPLR3_0_SSID_CAP_LIST__CAP_ID_MASK
42527. BIFPLR3_0_SSID_CAP_LIST__CAP_ID__SHIFT
42528. BIFPLR3_0_SSID_CAP_LIST__NEXT_PTR_MASK
42529. BIFPLR3_0_SSID_CAP_LIST__NEXT_PTR__SHIFT
42530. BIFPLR3_0_SSID_CAP__SUBSYSTEM_ID_MASK
42531. BIFPLR3_0_SSID_CAP__SUBSYSTEM_ID__SHIFT
42532. BIFPLR3_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
42533. BIFPLR3_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
42534. BIFPLR3_0_STATUS__CAP_LIST_MASK
42535. BIFPLR3_0_STATUS__CAP_LIST__SHIFT
42536. BIFPLR3_0_STATUS__DEVSEL_TIMING_MASK
42537. BIFPLR3_0_STATUS__DEVSEL_TIMING__SHIFT
42538. BIFPLR3_0_STATUS__FAST_BACK_CAPABLE_MASK
42539. BIFPLR3_0_STATUS__FAST_BACK_CAPABLE__SHIFT
42540. BIFPLR3_0_STATUS__INT_STATUS_MASK
42541. BIFPLR3_0_STATUS__INT_STATUS__SHIFT
42542. BIFPLR3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
42543. BIFPLR3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
42544. BIFPLR3_0_STATUS__PARITY_ERROR_DETECTED_MASK
42545. BIFPLR3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
42546. BIFPLR3_0_STATUS__PCI_66_EN_MASK
42547. BIFPLR3_0_STATUS__PCI_66_EN__SHIFT
42548. BIFPLR3_0_STATUS__RECEIVED_MASTER_ABORT_MASK
42549. BIFPLR3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
42550. BIFPLR3_0_STATUS__RECEIVED_TARGET_ABORT_MASK
42551. BIFPLR3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
42552. BIFPLR3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
42553. BIFPLR3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
42554. BIFPLR3_0_STATUS__SIGNAL_TARGET_ABORT_MASK
42555. BIFPLR3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
42556. BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
42557. BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
42558. BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
42559. BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
42560. BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
42561. BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
42562. BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
42563. BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
42564. BIFPLR3_0_SUB_CLASS__SUB_CLASS_MASK
42565. BIFPLR3_0_SUB_CLASS__SUB_CLASS__SHIFT
42566. BIFPLR3_0_VENDOR_ID__VENDOR_ID_MASK
42567. BIFPLR3_0_VENDOR_ID__VENDOR_ID__SHIFT
42568. BIFPLR3_1_BASE_CLASS__BASE_CLASS_MASK
42569. BIFPLR3_1_BASE_CLASS__BASE_CLASS__SHIFT
42570. BIFPLR3_1_BIST__BIST_CAP_MASK
42571. BIFPLR3_1_BIST__BIST_CAP__SHIFT
42572. BIFPLR3_1_BIST__BIST_COMP_MASK
42573. BIFPLR3_1_BIST__BIST_COMP__SHIFT
42574. BIFPLR3_1_BIST__BIST_STRT_MASK
42575. BIFPLR3_1_BIST__BIST_STRT__SHIFT
42576. BIFPLR3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
42577. BIFPLR3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
42578. BIFPLR3_1_CAP_PTR__CAP_PTR_MASK
42579. BIFPLR3_1_CAP_PTR__CAP_PTR__SHIFT
42580. BIFPLR3_1_COMMAND__AD_STEPPING_MASK
42581. BIFPLR3_1_COMMAND__AD_STEPPING__SHIFT
42582. BIFPLR3_1_COMMAND__BUS_MASTER_EN_MASK
42583. BIFPLR3_1_COMMAND__BUS_MASTER_EN__SHIFT
42584. BIFPLR3_1_COMMAND__FAST_B2B_EN_MASK
42585. BIFPLR3_1_COMMAND__FAST_B2B_EN__SHIFT
42586. BIFPLR3_1_COMMAND__INT_DIS_MASK
42587. BIFPLR3_1_COMMAND__INT_DIS__SHIFT
42588. BIFPLR3_1_COMMAND__IO_ACCESS_EN_MASK
42589. BIFPLR3_1_COMMAND__IO_ACCESS_EN__SHIFT
42590. BIFPLR3_1_COMMAND__MEM_ACCESS_EN_MASK
42591. BIFPLR3_1_COMMAND__MEM_ACCESS_EN__SHIFT
42592. BIFPLR3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
42593. BIFPLR3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
42594. BIFPLR3_1_COMMAND__PAL_SNOOP_EN_MASK
42595. BIFPLR3_1_COMMAND__PAL_SNOOP_EN__SHIFT
42596. BIFPLR3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
42597. BIFPLR3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
42598. BIFPLR3_1_COMMAND__SERR_EN_MASK
42599. BIFPLR3_1_COMMAND__SERR_EN__SHIFT
42600. BIFPLR3_1_COMMAND__SPECIAL_CYCLE_EN_MASK
42601. BIFPLR3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
42602. BIFPLR3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
42603. BIFPLR3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
42604. BIFPLR3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
42605. BIFPLR3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
42606. BIFPLR3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
42607. BIFPLR3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
42608. BIFPLR3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
42609. BIFPLR3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
42610. BIFPLR3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
42611. BIFPLR3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
42612. BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
42613. BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
42614. BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
42615. BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
42616. BIFPLR3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
42617. BIFPLR3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
42618. BIFPLR3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
42619. BIFPLR3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
42620. BIFPLR3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
42621. BIFPLR3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
42622. BIFPLR3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
42623. BIFPLR3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
42624. BIFPLR3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
42625. BIFPLR3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
42626. BIFPLR3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
42627. BIFPLR3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
42628. BIFPLR3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
42629. BIFPLR3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
42630. BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
42631. BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
42632. BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
42633. BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
42634. BIFPLR3_1_DEVICE_CAP__EXTENDED_TAG_MASK
42635. BIFPLR3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
42636. BIFPLR3_1_DEVICE_CAP__FLR_CAPABLE_MASK
42637. BIFPLR3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
42638. BIFPLR3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
42639. BIFPLR3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
42640. BIFPLR3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
42641. BIFPLR3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
42642. BIFPLR3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
42643. BIFPLR3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
42644. BIFPLR3_1_DEVICE_CAP__PHANTOM_FUNC_MASK
42645. BIFPLR3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
42646. BIFPLR3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
42647. BIFPLR3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
42648. BIFPLR3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
42649. BIFPLR3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
42650. BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
42651. BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
42652. BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
42653. BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
42654. BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
42655. BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
42656. BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
42657. BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
42658. BIFPLR3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
42659. BIFPLR3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
42660. BIFPLR3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
42661. BIFPLR3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
42662. BIFPLR3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
42663. BIFPLR3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
42664. BIFPLR3_1_DEVICE_CNTL2__LTR_EN_MASK
42665. BIFPLR3_1_DEVICE_CNTL2__LTR_EN__SHIFT
42666. BIFPLR3_1_DEVICE_CNTL2__OBFF_EN_MASK
42667. BIFPLR3_1_DEVICE_CNTL2__OBFF_EN__SHIFT
42668. BIFPLR3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
42669. BIFPLR3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
42670. BIFPLR3_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
42671. BIFPLR3_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
42672. BIFPLR3_1_DEVICE_CNTL__CORR_ERR_EN_MASK
42673. BIFPLR3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
42674. BIFPLR3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
42675. BIFPLR3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
42676. BIFPLR3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
42677. BIFPLR3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
42678. BIFPLR3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
42679. BIFPLR3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
42680. BIFPLR3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
42681. BIFPLR3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
42682. BIFPLR3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
42683. BIFPLR3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
42684. BIFPLR3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
42685. BIFPLR3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
42686. BIFPLR3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
42687. BIFPLR3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
42688. BIFPLR3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
42689. BIFPLR3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
42690. BIFPLR3_1_DEVICE_CNTL__USR_REPORT_EN_MASK
42691. BIFPLR3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
42692. BIFPLR3_1_DEVICE_ID__DEVICE_ID_MASK
42693. BIFPLR3_1_DEVICE_ID__DEVICE_ID__SHIFT
42694. BIFPLR3_1_DEVICE_STATUS2__RESERVED_MASK
42695. BIFPLR3_1_DEVICE_STATUS2__RESERVED__SHIFT
42696. BIFPLR3_1_DEVICE_STATUS__AUX_PWR_MASK
42697. BIFPLR3_1_DEVICE_STATUS__AUX_PWR__SHIFT
42698. BIFPLR3_1_DEVICE_STATUS__CORR_ERR_MASK
42699. BIFPLR3_1_DEVICE_STATUS__CORR_ERR__SHIFT
42700. BIFPLR3_1_DEVICE_STATUS__FATAL_ERR_MASK
42701. BIFPLR3_1_DEVICE_STATUS__FATAL_ERR__SHIFT
42702. BIFPLR3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
42703. BIFPLR3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
42704. BIFPLR3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
42705. BIFPLR3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
42706. BIFPLR3_1_DEVICE_STATUS__USR_DETECTED_MASK
42707. BIFPLR3_1_DEVICE_STATUS__USR_DETECTED__SHIFT
42708. BIFPLR3_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
42709. BIFPLR3_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
42710. BIFPLR3_1_HEADER__DEVICE_TYPE_MASK
42711. BIFPLR3_1_HEADER__DEVICE_TYPE__SHIFT
42712. BIFPLR3_1_HEADER__HEADER_TYPE_MASK
42713. BIFPLR3_1_HEADER__HEADER_TYPE__SHIFT
42714. BIFPLR3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
42715. BIFPLR3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
42716. BIFPLR3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
42717. BIFPLR3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
42718. BIFPLR3_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
42719. BIFPLR3_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
42720. BIFPLR3_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
42721. BIFPLR3_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
42722. BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_MASK
42723. BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
42724. BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
42725. BIFPLR3_1_IO_BASE_LIMIT__IO_BASE__SHIFT
42726. BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_MASK
42727. BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
42728. BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
42729. BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT
42730. BIFPLR3_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
42731. BIFPLR3_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
42732. BIFPLR3_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK
42733. BIFPLR3_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
42734. BIFPLR3_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
42735. BIFPLR3_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
42736. BIFPLR3_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
42737. BIFPLR3_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
42738. BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
42739. BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
42740. BIFPLR3_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK
42741. BIFPLR3_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
42742. BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
42743. BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
42744. BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK
42745. BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
42746. BIFPLR3_1_LATENCY__LATENCY_TIMER_MASK
42747. BIFPLR3_1_LATENCY__LATENCY_TIMER__SHIFT
42748. BIFPLR3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
42749. BIFPLR3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
42750. BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
42751. BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
42752. BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
42753. BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
42754. BIFPLR3_1_LINK_CAP2__RESERVED_MASK
42755. BIFPLR3_1_LINK_CAP2__RESERVED__SHIFT
42756. BIFPLR3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
42757. BIFPLR3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
42758. BIFPLR3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
42759. BIFPLR3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
42760. BIFPLR3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
42761. BIFPLR3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
42762. BIFPLR3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
42763. BIFPLR3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
42764. BIFPLR3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
42765. BIFPLR3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
42766. BIFPLR3_1_LINK_CAP__L1_EXIT_LATENCY_MASK
42767. BIFPLR3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
42768. BIFPLR3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
42769. BIFPLR3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
42770. BIFPLR3_1_LINK_CAP__LINK_SPEED_MASK
42771. BIFPLR3_1_LINK_CAP__LINK_SPEED__SHIFT
42772. BIFPLR3_1_LINK_CAP__LINK_WIDTH_MASK
42773. BIFPLR3_1_LINK_CAP__LINK_WIDTH__SHIFT
42774. BIFPLR3_1_LINK_CAP__PM_SUPPORT_MASK
42775. BIFPLR3_1_LINK_CAP__PM_SUPPORT__SHIFT
42776. BIFPLR3_1_LINK_CAP__PORT_NUMBER_MASK
42777. BIFPLR3_1_LINK_CAP__PORT_NUMBER__SHIFT
42778. BIFPLR3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
42779. BIFPLR3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
42780. BIFPLR3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
42781. BIFPLR3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
42782. BIFPLR3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
42783. BIFPLR3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
42784. BIFPLR3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
42785. BIFPLR3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
42786. BIFPLR3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
42787. BIFPLR3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
42788. BIFPLR3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
42789. BIFPLR3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
42790. BIFPLR3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
42791. BIFPLR3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
42792. BIFPLR3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
42793. BIFPLR3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
42794. BIFPLR3_1_LINK_CNTL2__XMIT_MARGIN_MASK
42795. BIFPLR3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
42796. BIFPLR3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
42797. BIFPLR3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
42798. BIFPLR3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
42799. BIFPLR3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
42800. BIFPLR3_1_LINK_CNTL__EXTENDED_SYNC_MASK
42801. BIFPLR3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
42802. BIFPLR3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
42803. BIFPLR3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
42804. BIFPLR3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
42805. BIFPLR3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
42806. BIFPLR3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
42807. BIFPLR3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
42808. BIFPLR3_1_LINK_CNTL__LINK_DIS_MASK
42809. BIFPLR3_1_LINK_CNTL__LINK_DIS__SHIFT
42810. BIFPLR3_1_LINK_CNTL__PM_CONTROL_MASK
42811. BIFPLR3_1_LINK_CNTL__PM_CONTROL__SHIFT
42812. BIFPLR3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
42813. BIFPLR3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
42814. BIFPLR3_1_LINK_CNTL__RETRAIN_LINK_MASK
42815. BIFPLR3_1_LINK_CNTL__RETRAIN_LINK__SHIFT
42816. BIFPLR3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
42817. BIFPLR3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
42818. BIFPLR3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
42819. BIFPLR3_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
42820. BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
42821. BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
42822. BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
42823. BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
42824. BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
42825. BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
42826. BIFPLR3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
42827. BIFPLR3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
42828. BIFPLR3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
42829. BIFPLR3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
42830. BIFPLR3_1_LINK_STATUS__DL_ACTIVE_MASK
42831. BIFPLR3_1_LINK_STATUS__DL_ACTIVE__SHIFT
42832. BIFPLR3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
42833. BIFPLR3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
42834. BIFPLR3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
42835. BIFPLR3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
42836. BIFPLR3_1_LINK_STATUS__LINK_TRAINING_MASK
42837. BIFPLR3_1_LINK_STATUS__LINK_TRAINING__SHIFT
42838. BIFPLR3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
42839. BIFPLR3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
42840. BIFPLR3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
42841. BIFPLR3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
42842. BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
42843. BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
42844. BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
42845. BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
42846. BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
42847. BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
42848. BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
42849. BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
42850. BIFPLR3_1_MSI_CAP_LIST__CAP_ID_MASK
42851. BIFPLR3_1_MSI_CAP_LIST__CAP_ID__SHIFT
42852. BIFPLR3_1_MSI_CAP_LIST__NEXT_PTR_MASK
42853. BIFPLR3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
42854. BIFPLR3_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
42855. BIFPLR3_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
42856. BIFPLR3_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
42857. BIFPLR3_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
42858. BIFPLR3_1_MSI_MAP_CAP_LIST__CAP_ID_MASK
42859. BIFPLR3_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
42860. BIFPLR3_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
42861. BIFPLR3_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
42862. BIFPLR3_1_MSI_MAP_CAP__CAP_TYPE_MASK
42863. BIFPLR3_1_MSI_MAP_CAP__CAP_TYPE__SHIFT
42864. BIFPLR3_1_MSI_MAP_CAP__EN_MASK
42865. BIFPLR3_1_MSI_MAP_CAP__EN__SHIFT
42866. BIFPLR3_1_MSI_MAP_CAP__FIXD_MASK
42867. BIFPLR3_1_MSI_MAP_CAP__FIXD__SHIFT
42868. BIFPLR3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
42869. BIFPLR3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
42870. BIFPLR3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
42871. BIFPLR3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
42872. BIFPLR3_1_MSI_MSG_CNTL__MSI_64BIT_MASK
42873. BIFPLR3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
42874. BIFPLR3_1_MSI_MSG_CNTL__MSI_EN_MASK
42875. BIFPLR3_1_MSI_MSG_CNTL__MSI_EN__SHIFT
42876. BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
42877. BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
42878. BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
42879. BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
42880. BIFPLR3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
42881. BIFPLR3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
42882. BIFPLR3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
42883. BIFPLR3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
42884. BIFPLR3_1_MSI_MSG_DATA__MSI_DATA_MASK
42885. BIFPLR3_1_MSI_MSG_DATA__MSI_DATA__SHIFT
42886. BIFPLR3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
42887. BIFPLR3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
42888. BIFPLR3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
42889. BIFPLR3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
42890. BIFPLR3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
42891. BIFPLR3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
42892. BIFPLR3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
42893. BIFPLR3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
42894. BIFPLR3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
42895. BIFPLR3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
42896. BIFPLR3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
42897. BIFPLR3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
42898. BIFPLR3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
42899. BIFPLR3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
42900. BIFPLR3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
42901. BIFPLR3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
42902. BIFPLR3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
42903. BIFPLR3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
42904. BIFPLR3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
42905. BIFPLR3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
42906. BIFPLR3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
42907. BIFPLR3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
42908. BIFPLR3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
42909. BIFPLR3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
42910. BIFPLR3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
42911. BIFPLR3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
42912. BIFPLR3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
42913. BIFPLR3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
42914. BIFPLR3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
42915. BIFPLR3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
42916. BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
42917. BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
42918. BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
42919. BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
42920. BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
42921. BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
42922. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
42923. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
42924. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
42925. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
42926. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
42927. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
42928. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
42929. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
42930. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
42931. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
42932. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
42933. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
42934. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
42935. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
42936. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
42937. BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
42938. BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
42939. BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
42940. BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
42941. BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
42942. BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
42943. BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
42944. BIFPLR3_1_PCIE_CAP_LIST__CAP_ID_MASK
42945. BIFPLR3_1_PCIE_CAP_LIST__CAP_ID__SHIFT
42946. BIFPLR3_1_PCIE_CAP_LIST__NEXT_PTR_MASK
42947. BIFPLR3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
42948. BIFPLR3_1_PCIE_CAP__DEVICE_TYPE_MASK
42949. BIFPLR3_1_PCIE_CAP__DEVICE_TYPE__SHIFT
42950. BIFPLR3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
42951. BIFPLR3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
42952. BIFPLR3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
42953. BIFPLR3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
42954. BIFPLR3_1_PCIE_CAP__VERSION_MASK
42955. BIFPLR3_1_PCIE_CAP__VERSION__SHIFT
42956. BIFPLR3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
42957. BIFPLR3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
42958. BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
42959. BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
42960. BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
42961. BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
42962. BIFPLR3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
42963. BIFPLR3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
42964. BIFPLR3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
42965. BIFPLR3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
42966. BIFPLR3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
42967. BIFPLR3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
42968. BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
42969. BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
42970. BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
42971. BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
42972. BIFPLR3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
42973. BIFPLR3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
42974. BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
42975. BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
42976. BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
42977. BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
42978. BIFPLR3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
42979. BIFPLR3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
42980. BIFPLR3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
42981. BIFPLR3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
42982. BIFPLR3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
42983. BIFPLR3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
42984. BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
42985. BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
42986. BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
42987. BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
42988. BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
42989. BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
42990. BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
42991. BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
42992. BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
42993. BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
42994. BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
42995. BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
42996. BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
42997. BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
42998. BIFPLR3_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
42999. BIFPLR3_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
43000. BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
43001. BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
43002. BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
43003. BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
43004. BIFPLR3_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
43005. BIFPLR3_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
43006. BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
43007. BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
43008. BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
43009. BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
43010. BIFPLR3_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
43011. BIFPLR3_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
43012. BIFPLR3_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
43013. BIFPLR3_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
43014. BIFPLR3_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
43015. BIFPLR3_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
43016. BIFPLR3_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
43017. BIFPLR3_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
43018. BIFPLR3_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
43019. BIFPLR3_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
43020. BIFPLR3_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
43021. BIFPLR3_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
43022. BIFPLR3_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
43023. BIFPLR3_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
43024. BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
43025. BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
43026. BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
43027. BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
43028. BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
43029. BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
43030. BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
43031. BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
43032. BIFPLR3_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
43033. BIFPLR3_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
43034. BIFPLR3_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
43035. BIFPLR3_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
43036. BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
43037. BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
43038. BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
43039. BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
43040. BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
43041. BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
43042. BIFPLR3_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
43043. BIFPLR3_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
43044. BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
43045. BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
43046. BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
43047. BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
43048. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK
43049. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
43050. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK
43051. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
43052. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK
43053. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
43054. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK
43055. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
43056. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK
43057. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
43058. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK
43059. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
43060. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK
43061. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
43062. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK
43063. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
43064. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK
43065. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
43066. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK
43067. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
43068. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK
43069. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
43070. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK
43071. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
43072. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK
43073. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
43074. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK
43075. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
43076. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK
43077. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
43078. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK
43079. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
43080. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK
43081. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
43082. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK
43083. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
43084. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK
43085. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
43086. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK
43087. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
43088. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK
43089. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
43090. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK
43091. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
43092. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK
43093. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
43094. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK
43095. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
43096. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK
43097. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
43098. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK
43099. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
43100. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK
43101. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
43102. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK
43103. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
43104. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK
43105. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
43106. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK
43107. BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
43108. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK
43109. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
43110. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK
43111. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
43112. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK
43113. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
43114. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK
43115. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
43116. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK
43117. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
43118. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK
43119. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
43120. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK
43121. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
43122. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK
43123. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
43124. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK
43125. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
43126. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK
43127. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
43128. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK
43129. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
43130. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK
43131. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
43132. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK
43133. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
43134. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK
43135. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
43136. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK
43137. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
43138. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK
43139. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
43140. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK
43141. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
43142. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK
43143. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
43144. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK
43145. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
43146. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK
43147. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
43148. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK
43149. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
43150. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK
43151. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
43152. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK
43153. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
43154. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK
43155. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
43156. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK
43157. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
43158. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK
43159. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
43160. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK
43161. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
43162. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK
43163. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
43164. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK
43165. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
43166. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK
43167. BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
43168. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK
43169. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
43170. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK
43171. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
43172. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK
43173. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
43174. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK
43175. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
43176. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK
43177. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
43178. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK
43179. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
43180. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK
43181. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
43182. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK
43183. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
43184. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK
43185. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
43186. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK
43187. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
43188. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK
43189. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
43190. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK
43191. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
43192. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK
43193. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
43194. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK
43195. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
43196. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK
43197. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
43198. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK
43199. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
43200. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK
43201. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
43202. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK
43203. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
43204. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK
43205. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
43206. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK
43207. BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
43208. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK
43209. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
43210. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK
43211. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
43212. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK
43213. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
43214. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK
43215. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
43216. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK
43217. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
43218. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK
43219. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
43220. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK
43221. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
43222. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK
43223. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
43224. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK
43225. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
43226. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK
43227. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
43228. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK
43229. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
43230. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK
43231. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
43232. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK
43233. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
43234. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK
43235. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
43236. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK
43237. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
43238. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK
43239. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
43240. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK
43241. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
43242. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK
43243. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
43244. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK
43245. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
43246. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK
43247. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
43248. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK
43249. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
43250. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK
43251. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
43252. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK
43253. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
43254. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK
43255. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
43256. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK
43257. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
43258. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK
43259. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
43260. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK
43261. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
43262. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK
43263. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
43264. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK
43265. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
43266. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK
43267. BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
43268. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK
43269. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
43270. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK
43271. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
43272. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK
43273. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
43274. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK
43275. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
43276. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK
43277. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
43278. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK
43279. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
43280. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK
43281. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
43282. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK
43283. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
43284. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK
43285. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
43286. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK
43287. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
43288. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK
43289. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
43290. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK
43291. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
43292. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK
43293. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
43294. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK
43295. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
43296. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK
43297. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
43298. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK
43299. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
43300. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK
43301. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
43302. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK
43303. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
43304. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK
43305. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
43306. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK
43307. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
43308. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK
43309. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
43310. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK
43311. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
43312. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK
43313. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
43314. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK
43315. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
43316. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK
43317. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
43318. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK
43319. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
43320. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK
43321. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
43322. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK
43323. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
43324. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK
43325. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
43326. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK
43327. BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
43328. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK
43329. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
43330. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK
43331. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
43332. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK
43333. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
43334. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK
43335. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
43336. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK
43337. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
43338. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK
43339. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
43340. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK
43341. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
43342. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK
43343. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
43344. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK
43345. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
43346. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK
43347. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
43348. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK
43349. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
43350. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK
43351. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
43352. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK
43353. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
43354. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK
43355. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
43356. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK
43357. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
43358. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK
43359. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
43360. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK
43361. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
43362. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK
43363. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
43364. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK
43365. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
43366. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK
43367. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
43368. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK
43369. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
43370. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK
43371. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
43372. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK
43373. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
43374. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK
43375. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
43376. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK
43377. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
43378. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK
43379. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
43380. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK
43381. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
43382. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK
43383. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
43384. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK
43385. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
43386. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK
43387. BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
43388. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK
43389. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
43390. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK
43391. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
43392. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK
43393. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
43394. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK
43395. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
43396. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK
43397. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
43398. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK
43399. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
43400. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK
43401. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
43402. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK
43403. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
43404. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK
43405. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
43406. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK
43407. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
43408. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK
43409. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
43410. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK
43411. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
43412. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK
43413. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
43414. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK
43415. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
43416. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK
43417. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
43418. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK
43419. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
43420. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK
43421. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
43422. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK
43423. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
43424. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK
43425. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
43426. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK
43427. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
43428. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK
43429. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
43430. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK
43431. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
43432. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK
43433. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
43434. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK
43435. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
43436. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK
43437. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
43438. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK
43439. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
43440. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK
43441. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
43442. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK
43443. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
43444. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK
43445. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
43446. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK
43447. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
43448. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK
43449. BIFPLR3_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
43450. BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK
43451. BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
43452. BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK
43453. BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
43454. BIFPLR3_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
43455. BIFPLR3_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
43456. BIFPLR3_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK
43457. BIFPLR3_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
43458. BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
43459. BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
43460. BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
43461. BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
43462. BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
43463. BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
43464. BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
43465. BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
43466. BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
43467. BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
43468. BIFPLR3_1_PCIE_ESM_HEADER_2__CAP_ID_MASK
43469. BIFPLR3_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
43470. BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
43471. BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
43472. BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
43473. BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
43474. BIFPLR3_1_PCIE_HDR_LOG0__TLP_HDR_MASK
43475. BIFPLR3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
43476. BIFPLR3_1_PCIE_HDR_LOG1__TLP_HDR_MASK
43477. BIFPLR3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
43478. BIFPLR3_1_PCIE_HDR_LOG2__TLP_HDR_MASK
43479. BIFPLR3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
43480. BIFPLR3_1_PCIE_HDR_LOG3__TLP_HDR_MASK
43481. BIFPLR3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
43482. BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
43483. BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
43484. BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
43485. BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
43486. BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
43487. BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
43488. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
43489. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
43490. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
43491. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
43492. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
43493. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
43494. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
43495. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
43496. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
43497. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
43498. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
43499. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
43500. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
43501. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
43502. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
43503. BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
43504. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
43505. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
43506. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
43507. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
43508. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
43509. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
43510. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
43511. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
43512. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
43513. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
43514. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
43515. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
43516. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
43517. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
43518. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
43519. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
43520. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
43521. BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
43522. BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43523. BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43524. BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43525. BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43526. BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43527. BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43528. BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43529. BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43530. BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43531. BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43532. BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43533. BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43534. BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43535. BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43536. BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43537. BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43538. BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43539. BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43540. BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43541. BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43542. BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43543. BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43544. BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43545. BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43546. BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43547. BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43548. BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43549. BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43550. BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43551. BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43552. BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43553. BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43554. BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43555. BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43556. BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43557. BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43558. BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43559. BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43560. BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43561. BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43562. BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43563. BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43564. BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43565. BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43566. BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43567. BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43568. BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43569. BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43570. BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43571. BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43572. BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43573. BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43574. BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43575. BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43576. BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43577. BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43578. BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43579. BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43580. BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43581. BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43582. BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43583. BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43584. BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43585. BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43586. BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43587. BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43588. BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43589. BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43590. BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43591. BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43592. BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43593. BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43594. BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43595. BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43596. BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43597. BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43598. BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43599. BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43600. BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43601. BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43602. BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43603. BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43604. BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43605. BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43606. BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43607. BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43608. BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43609. BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43610. BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43611. BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43612. BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43613. BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43614. BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43615. BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43616. BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43617. BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43618. BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43619. BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43620. BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43621. BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43622. BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43623. BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43624. BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43625. BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43626. BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43627. BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43628. BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43629. BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43630. BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43631. BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43632. BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43633. BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43634. BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43635. BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43636. BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43637. BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43638. BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43639. BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43640. BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43641. BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43642. BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
43643. BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
43644. BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
43645. BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
43646. BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
43647. BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
43648. BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
43649. BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
43650. BIFPLR3_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
43651. BIFPLR3_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
43652. BIFPLR3_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
43653. BIFPLR3_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
43654. BIFPLR3_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
43655. BIFPLR3_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
43656. BIFPLR3_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
43657. BIFPLR3_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
43658. BIFPLR3_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
43659. BIFPLR3_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
43660. BIFPLR3_1_PCIE_LINK_CNTL3__RESERVED_MASK
43661. BIFPLR3_1_PCIE_LINK_CNTL3__RESERVED__SHIFT
43662. BIFPLR3_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
43663. BIFPLR3_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
43664. BIFPLR3_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
43665. BIFPLR3_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
43666. BIFPLR3_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
43667. BIFPLR3_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
43668. BIFPLR3_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
43669. BIFPLR3_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
43670. BIFPLR3_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
43671. BIFPLR3_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
43672. BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
43673. BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
43674. BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
43675. BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
43676. BIFPLR3_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
43677. BIFPLR3_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
43678. BIFPLR3_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK
43679. BIFPLR3_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
43680. BIFPLR3_1_PCIE_MC_CNTL__MC_ENABLE_MASK
43681. BIFPLR3_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT
43682. BIFPLR3_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
43683. BIFPLR3_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
43684. BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
43685. BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
43686. BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
43687. BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
43688. BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
43689. BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
43690. BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
43691. BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
43692. BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
43693. BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
43694. BIFPLR3_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
43695. BIFPLR3_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
43696. BIFPLR3_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
43697. BIFPLR3_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
43698. BIFPLR3_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
43699. BIFPLR3_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
43700. BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
43701. BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
43702. BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
43703. BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
43704. BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
43705. BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
43706. BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
43707. BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
43708. BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
43709. BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
43710. BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
43711. BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
43712. BIFPLR3_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
43713. BIFPLR3_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
43714. BIFPLR3_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
43715. BIFPLR3_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
43716. BIFPLR3_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
43717. BIFPLR3_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
43718. BIFPLR3_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
43719. BIFPLR3_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
43720. BIFPLR3_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
43721. BIFPLR3_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
43722. BIFPLR3_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
43723. BIFPLR3_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
43724. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
43725. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
43726. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
43727. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
43728. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
43729. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
43730. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
43731. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
43732. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
43733. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
43734. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
43735. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
43736. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
43737. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
43738. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
43739. BIFPLR3_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
43740. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
43741. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
43742. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
43743. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
43744. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
43745. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
43746. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
43747. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
43748. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
43749. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
43750. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
43751. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
43752. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
43753. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
43754. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
43755. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
43756. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
43757. BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
43758. BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
43759. BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
43760. BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
43761. BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
43762. BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
43763. BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
43764. BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
43765. BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
43766. BIFPLR3_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
43767. BIFPLR3_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
43768. BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
43769. BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
43770. BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK
43771. BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
43772. BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
43773. BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
43774. BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
43775. BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
43776. BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CTO_MASK
43777. BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
43778. BIFPLR3_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
43779. BIFPLR3_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
43780. BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
43781. BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
43782. BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK
43783. BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
43784. BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
43785. BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
43786. BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
43787. BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
43788. BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
43789. BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
43790. BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
43791. BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
43792. BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
43793. BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
43794. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
43795. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
43796. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
43797. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
43798. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
43799. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
43800. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
43801. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
43802. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
43803. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
43804. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
43805. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
43806. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
43807. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
43808. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
43809. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
43810. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
43811. BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
43812. BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
43813. BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
43814. BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
43815. BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
43816. BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
43817. BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
43818. BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
43819. BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
43820. BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK
43821. BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
43822. BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
43823. BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
43824. BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
43825. BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
43826. BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
43827. BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
43828. BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
43829. BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
43830. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
43831. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
43832. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
43833. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
43834. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
43835. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
43836. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
43837. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
43838. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
43839. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
43840. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
43841. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
43842. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
43843. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
43844. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
43845. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
43846. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
43847. BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
43848. BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
43849. BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
43850. BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
43851. BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
43852. BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
43853. BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
43854. BIFPLR3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
43855. BIFPLR3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
43856. BIFPLR3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
43857. BIFPLR3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
43858. BIFPLR3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
43859. BIFPLR3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
43860. BIFPLR3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
43861. BIFPLR3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
43862. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
43863. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
43864. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
43865. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
43866. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
43867. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
43868. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
43869. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
43870. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
43871. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
43872. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
43873. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
43874. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
43875. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
43876. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
43877. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
43878. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
43879. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
43880. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
43881. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
43882. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
43883. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
43884. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
43885. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
43886. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
43887. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
43888. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
43889. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
43890. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
43891. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
43892. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
43893. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
43894. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
43895. BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
43896. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
43897. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
43898. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
43899. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
43900. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
43901. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
43902. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
43903. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
43904. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
43905. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
43906. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
43907. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
43908. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
43909. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
43910. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
43911. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
43912. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
43913. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
43914. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
43915. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
43916. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
43917. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
43918. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
43919. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
43920. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
43921. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
43922. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
43923. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
43924. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
43925. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
43926. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
43927. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
43928. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
43929. BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
43930. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
43931. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
43932. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
43933. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
43934. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
43935. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
43936. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
43937. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
43938. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
43939. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
43940. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
43941. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
43942. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
43943. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
43944. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
43945. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
43946. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
43947. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
43948. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
43949. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
43950. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
43951. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
43952. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
43953. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
43954. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
43955. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
43956. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
43957. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
43958. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
43959. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
43960. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
43961. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
43962. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
43963. BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
43964. BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
43965. BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
43966. BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
43967. BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
43968. BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
43969. BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
43970. BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
43971. BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
43972. BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
43973. BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
43974. BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
43975. BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
43976. BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
43977. BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
43978. BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
43979. BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
43980. BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
43981. BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
43982. BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
43983. BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
43984. BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
43985. BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
43986. BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
43987. BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
43988. BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
43989. BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
43990. BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
43991. BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
43992. BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
43993. BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
43994. BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
43995. BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
43996. BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
43997. BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
43998. BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
43999. BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
44000. BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
44001. BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
44002. BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
44003. BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
44004. BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
44005. BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
44006. BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
44007. BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
44008. BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
44009. BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
44010. BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
44011. BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
44012. BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
44013. BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
44014. BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
44015. BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
44016. BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
44017. BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
44018. BIFPLR3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
44019. BIFPLR3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
44020. BIFPLR3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
44021. BIFPLR3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
44022. BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
44023. BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
44024. BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
44025. BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
44026. BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
44027. BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
44028. BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
44029. BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
44030. BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
44031. BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
44032. BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
44033. BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
44034. BIFPLR3_1_PMI_CAP_LIST__CAP_ID_MASK
44035. BIFPLR3_1_PMI_CAP_LIST__CAP_ID__SHIFT
44036. BIFPLR3_1_PMI_CAP_LIST__NEXT_PTR_MASK
44037. BIFPLR3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
44038. BIFPLR3_1_PMI_CAP__AUX_CURRENT_MASK
44039. BIFPLR3_1_PMI_CAP__AUX_CURRENT__SHIFT
44040. BIFPLR3_1_PMI_CAP__D1_SUPPORT_MASK
44041. BIFPLR3_1_PMI_CAP__D1_SUPPORT__SHIFT
44042. BIFPLR3_1_PMI_CAP__D2_SUPPORT_MASK
44043. BIFPLR3_1_PMI_CAP__D2_SUPPORT__SHIFT
44044. BIFPLR3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
44045. BIFPLR3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
44046. BIFPLR3_1_PMI_CAP__PME_CLOCK_MASK
44047. BIFPLR3_1_PMI_CAP__PME_CLOCK__SHIFT
44048. BIFPLR3_1_PMI_CAP__PME_SUPPORT_MASK
44049. BIFPLR3_1_PMI_CAP__PME_SUPPORT__SHIFT
44050. BIFPLR3_1_PMI_CAP__VERSION_MASK
44051. BIFPLR3_1_PMI_CAP__VERSION__SHIFT
44052. BIFPLR3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
44053. BIFPLR3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
44054. BIFPLR3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
44055. BIFPLR3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
44056. BIFPLR3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
44057. BIFPLR3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
44058. BIFPLR3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
44059. BIFPLR3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
44060. BIFPLR3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
44061. BIFPLR3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
44062. BIFPLR3_1_PMI_STATUS_CNTL__PME_EN_MASK
44063. BIFPLR3_1_PMI_STATUS_CNTL__PME_EN__SHIFT
44064. BIFPLR3_1_PMI_STATUS_CNTL__PME_STATUS_MASK
44065. BIFPLR3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
44066. BIFPLR3_1_PMI_STATUS_CNTL__PMI_DATA_MASK
44067. BIFPLR3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
44068. BIFPLR3_1_PMI_STATUS_CNTL__POWER_STATE_MASK
44069. BIFPLR3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
44070. BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
44071. BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
44072. BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
44073. BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
44074. BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
44075. BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
44076. BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
44077. BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
44078. BIFPLR3_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
44079. BIFPLR3_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
44080. BIFPLR3_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
44081. BIFPLR3_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
44082. BIFPLR3_1_PROG_INTERFACE__PROG_INTERFACE_MASK
44083. BIFPLR3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
44084. BIFPLR3_1_REVISION_ID__MAJOR_REV_ID_MASK
44085. BIFPLR3_1_REVISION_ID__MAJOR_REV_ID__SHIFT
44086. BIFPLR3_1_REVISION_ID__MINOR_REV_ID_MASK
44087. BIFPLR3_1_REVISION_ID__MINOR_REV_ID__SHIFT
44088. BIFPLR3_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
44089. BIFPLR3_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
44090. BIFPLR3_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
44091. BIFPLR3_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
44092. BIFPLR3_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK
44093. BIFPLR3_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
44094. BIFPLR3_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
44095. BIFPLR3_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
44096. BIFPLR3_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
44097. BIFPLR3_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
44098. BIFPLR3_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
44099. BIFPLR3_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
44100. BIFPLR3_1_ROOT_STATUS__PME_PENDING_MASK
44101. BIFPLR3_1_ROOT_STATUS__PME_PENDING__SHIFT
44102. BIFPLR3_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK
44103. BIFPLR3_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
44104. BIFPLR3_1_ROOT_STATUS__PME_STATUS_MASK
44105. BIFPLR3_1_ROOT_STATUS__PME_STATUS__SHIFT
44106. BIFPLR3_1_SECONDARY_STATUS__CAP_LIST_MASK
44107. BIFPLR3_1_SECONDARY_STATUS__CAP_LIST__SHIFT
44108. BIFPLR3_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK
44109. BIFPLR3_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
44110. BIFPLR3_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
44111. BIFPLR3_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
44112. BIFPLR3_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
44113. BIFPLR3_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
44114. BIFPLR3_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
44115. BIFPLR3_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
44116. BIFPLR3_1_SECONDARY_STATUS__PCI_66_EN_MASK
44117. BIFPLR3_1_SECONDARY_STATUS__PCI_66_EN__SHIFT
44118. BIFPLR3_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
44119. BIFPLR3_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
44120. BIFPLR3_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
44121. BIFPLR3_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
44122. BIFPLR3_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
44123. BIFPLR3_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
44124. BIFPLR3_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
44125. BIFPLR3_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
44126. BIFPLR3_1_SLOT_CAP2__RESERVED_MASK
44127. BIFPLR3_1_SLOT_CAP2__RESERVED__SHIFT
44128. BIFPLR3_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
44129. BIFPLR3_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
44130. BIFPLR3_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
44131. BIFPLR3_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
44132. BIFPLR3_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
44133. BIFPLR3_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
44134. BIFPLR3_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK
44135. BIFPLR3_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
44136. BIFPLR3_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK
44137. BIFPLR3_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
44138. BIFPLR3_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
44139. BIFPLR3_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
44140. BIFPLR3_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
44141. BIFPLR3_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
44142. BIFPLR3_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
44143. BIFPLR3_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
44144. BIFPLR3_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
44145. BIFPLR3_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
44146. BIFPLR3_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
44147. BIFPLR3_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
44148. BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
44149. BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
44150. BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
44151. BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
44152. BIFPLR3_1_SLOT_CNTL2__RESERVED_MASK
44153. BIFPLR3_1_SLOT_CNTL2__RESERVED__SHIFT
44154. BIFPLR3_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
44155. BIFPLR3_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
44156. BIFPLR3_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
44157. BIFPLR3_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
44158. BIFPLR3_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
44159. BIFPLR3_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
44160. BIFPLR3_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
44161. BIFPLR3_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
44162. BIFPLR3_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
44163. BIFPLR3_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
44164. BIFPLR3_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
44165. BIFPLR3_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
44166. BIFPLR3_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
44167. BIFPLR3_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
44168. BIFPLR3_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
44169. BIFPLR3_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
44170. BIFPLR3_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
44171. BIFPLR3_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
44172. BIFPLR3_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
44173. BIFPLR3_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
44174. BIFPLR3_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
44175. BIFPLR3_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
44176. BIFPLR3_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
44177. BIFPLR3_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
44178. BIFPLR3_1_SLOT_STATUS2__RESERVED_MASK
44179. BIFPLR3_1_SLOT_STATUS2__RESERVED__SHIFT
44180. BIFPLR3_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
44181. BIFPLR3_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
44182. BIFPLR3_1_SLOT_STATUS__COMMAND_COMPLETED_MASK
44183. BIFPLR3_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
44184. BIFPLR3_1_SLOT_STATUS__DL_STATE_CHANGED_MASK
44185. BIFPLR3_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
44186. BIFPLR3_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
44187. BIFPLR3_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
44188. BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
44189. BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
44190. BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK
44191. BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
44192. BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
44193. BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
44194. BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
44195. BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
44196. BIFPLR3_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
44197. BIFPLR3_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
44198. BIFPLR3_1_SSID_CAP_LIST__CAP_ID_MASK
44199. BIFPLR3_1_SSID_CAP_LIST__CAP_ID__SHIFT
44200. BIFPLR3_1_SSID_CAP_LIST__NEXT_PTR_MASK
44201. BIFPLR3_1_SSID_CAP_LIST__NEXT_PTR__SHIFT
44202. BIFPLR3_1_SSID_CAP__SUBSYSTEM_ID_MASK
44203. BIFPLR3_1_SSID_CAP__SUBSYSTEM_ID__SHIFT
44204. BIFPLR3_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
44205. BIFPLR3_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
44206. BIFPLR3_1_STATUS__CAP_LIST_MASK
44207. BIFPLR3_1_STATUS__CAP_LIST__SHIFT
44208. BIFPLR3_1_STATUS__DEVSEL_TIMING_MASK
44209. BIFPLR3_1_STATUS__DEVSEL_TIMING__SHIFT
44210. BIFPLR3_1_STATUS__FAST_BACK_CAPABLE_MASK
44211. BIFPLR3_1_STATUS__FAST_BACK_CAPABLE__SHIFT
44212. BIFPLR3_1_STATUS__INT_STATUS_MASK
44213. BIFPLR3_1_STATUS__INT_STATUS__SHIFT
44214. BIFPLR3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
44215. BIFPLR3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
44216. BIFPLR3_1_STATUS__PARITY_ERROR_DETECTED_MASK
44217. BIFPLR3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
44218. BIFPLR3_1_STATUS__PCI_66_EN_MASK
44219. BIFPLR3_1_STATUS__PCI_66_EN__SHIFT
44220. BIFPLR3_1_STATUS__RECEIVED_MASTER_ABORT_MASK
44221. BIFPLR3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
44222. BIFPLR3_1_STATUS__RECEIVED_TARGET_ABORT_MASK
44223. BIFPLR3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
44224. BIFPLR3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
44225. BIFPLR3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
44226. BIFPLR3_1_STATUS__SIGNAL_TARGET_ABORT_MASK
44227. BIFPLR3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
44228. BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
44229. BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
44230. BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
44231. BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
44232. BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
44233. BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
44234. BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
44235. BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
44236. BIFPLR3_1_SUB_CLASS__SUB_CLASS_MASK
44237. BIFPLR3_1_SUB_CLASS__SUB_CLASS__SHIFT
44238. BIFPLR3_1_VENDOR_ID__VENDOR_ID_MASK
44239. BIFPLR3_1_VENDOR_ID__VENDOR_ID__SHIFT
44240. BIFPLR3_2_BASE_CLASS__BASE_CLASS_MASK
44241. BIFPLR3_2_BASE_CLASS__BASE_CLASS__SHIFT
44242. BIFPLR3_2_BIST__BIST_CAP_MASK
44243. BIFPLR3_2_BIST__BIST_CAP__SHIFT
44244. BIFPLR3_2_BIST__BIST_COMP_MASK
44245. BIFPLR3_2_BIST__BIST_COMP__SHIFT
44246. BIFPLR3_2_BIST__BIST_STRT_MASK
44247. BIFPLR3_2_BIST__BIST_STRT__SHIFT
44248. BIFPLR3_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
44249. BIFPLR3_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
44250. BIFPLR3_2_CAP_PTR__CAP_PTR_MASK
44251. BIFPLR3_2_CAP_PTR__CAP_PTR__SHIFT
44252. BIFPLR3_2_COMMAND__AD_STEPPING_MASK
44253. BIFPLR3_2_COMMAND__AD_STEPPING__SHIFT
44254. BIFPLR3_2_COMMAND__BUS_MASTER_EN_MASK
44255. BIFPLR3_2_COMMAND__BUS_MASTER_EN__SHIFT
44256. BIFPLR3_2_COMMAND__FAST_B2B_EN_MASK
44257. BIFPLR3_2_COMMAND__FAST_B2B_EN__SHIFT
44258. BIFPLR3_2_COMMAND__INT_DIS_MASK
44259. BIFPLR3_2_COMMAND__INT_DIS__SHIFT
44260. BIFPLR3_2_COMMAND__IO_ACCESS_EN_MASK
44261. BIFPLR3_2_COMMAND__IO_ACCESS_EN__SHIFT
44262. BIFPLR3_2_COMMAND__MEM_ACCESS_EN_MASK
44263. BIFPLR3_2_COMMAND__MEM_ACCESS_EN__SHIFT
44264. BIFPLR3_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
44265. BIFPLR3_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
44266. BIFPLR3_2_COMMAND__PAL_SNOOP_EN_MASK
44267. BIFPLR3_2_COMMAND__PAL_SNOOP_EN__SHIFT
44268. BIFPLR3_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
44269. BIFPLR3_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
44270. BIFPLR3_2_COMMAND__SERR_EN_MASK
44271. BIFPLR3_2_COMMAND__SERR_EN__SHIFT
44272. BIFPLR3_2_COMMAND__SPECIAL_CYCLE_EN_MASK
44273. BIFPLR3_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
44274. BIFPLR3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
44275. BIFPLR3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
44276. BIFPLR3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
44277. BIFPLR3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
44278. BIFPLR3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
44279. BIFPLR3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
44280. BIFPLR3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
44281. BIFPLR3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
44282. BIFPLR3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
44283. BIFPLR3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
44284. BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
44285. BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
44286. BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
44287. BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
44288. BIFPLR3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
44289. BIFPLR3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
44290. BIFPLR3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
44291. BIFPLR3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
44292. BIFPLR3_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
44293. BIFPLR3_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
44294. BIFPLR3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
44295. BIFPLR3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
44296. BIFPLR3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
44297. BIFPLR3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
44298. BIFPLR3_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
44299. BIFPLR3_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
44300. BIFPLR3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
44301. BIFPLR3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
44302. BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
44303. BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
44304. BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
44305. BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
44306. BIFPLR3_2_DEVICE_CAP__EXTENDED_TAG_MASK
44307. BIFPLR3_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
44308. BIFPLR3_2_DEVICE_CAP__FLR_CAPABLE_MASK
44309. BIFPLR3_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
44310. BIFPLR3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
44311. BIFPLR3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
44312. BIFPLR3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
44313. BIFPLR3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
44314. BIFPLR3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
44315. BIFPLR3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
44316. BIFPLR3_2_DEVICE_CAP__PHANTOM_FUNC_MASK
44317. BIFPLR3_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
44318. BIFPLR3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
44319. BIFPLR3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
44320. BIFPLR3_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
44321. BIFPLR3_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
44322. BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
44323. BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
44324. BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
44325. BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
44326. BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
44327. BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
44328. BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
44329. BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
44330. BIFPLR3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
44331. BIFPLR3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
44332. BIFPLR3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
44333. BIFPLR3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
44334. BIFPLR3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
44335. BIFPLR3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
44336. BIFPLR3_2_DEVICE_CNTL2__LTR_EN_MASK
44337. BIFPLR3_2_DEVICE_CNTL2__LTR_EN__SHIFT
44338. BIFPLR3_2_DEVICE_CNTL2__OBFF_EN_MASK
44339. BIFPLR3_2_DEVICE_CNTL2__OBFF_EN__SHIFT
44340. BIFPLR3_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
44341. BIFPLR3_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
44342. BIFPLR3_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
44343. BIFPLR3_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
44344. BIFPLR3_2_DEVICE_CNTL__CORR_ERR_EN_MASK
44345. BIFPLR3_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
44346. BIFPLR3_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
44347. BIFPLR3_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
44348. BIFPLR3_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
44349. BIFPLR3_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
44350. BIFPLR3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
44351. BIFPLR3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
44352. BIFPLR3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
44353. BIFPLR3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
44354. BIFPLR3_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
44355. BIFPLR3_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
44356. BIFPLR3_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
44357. BIFPLR3_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
44358. BIFPLR3_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
44359. BIFPLR3_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
44360. BIFPLR3_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
44361. BIFPLR3_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
44362. BIFPLR3_2_DEVICE_CNTL__USR_REPORT_EN_MASK
44363. BIFPLR3_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
44364. BIFPLR3_2_DEVICE_ID__DEVICE_ID_MASK
44365. BIFPLR3_2_DEVICE_ID__DEVICE_ID__SHIFT
44366. BIFPLR3_2_DEVICE_STATUS2__RESERVED_MASK
44367. BIFPLR3_2_DEVICE_STATUS2__RESERVED__SHIFT
44368. BIFPLR3_2_DEVICE_STATUS__AUX_PWR_MASK
44369. BIFPLR3_2_DEVICE_STATUS__AUX_PWR__SHIFT
44370. BIFPLR3_2_DEVICE_STATUS__CORR_ERR_MASK
44371. BIFPLR3_2_DEVICE_STATUS__CORR_ERR__SHIFT
44372. BIFPLR3_2_DEVICE_STATUS__FATAL_ERR_MASK
44373. BIFPLR3_2_DEVICE_STATUS__FATAL_ERR__SHIFT
44374. BIFPLR3_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
44375. BIFPLR3_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
44376. BIFPLR3_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
44377. BIFPLR3_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
44378. BIFPLR3_2_DEVICE_STATUS__USR_DETECTED_MASK
44379. BIFPLR3_2_DEVICE_STATUS__USR_DETECTED__SHIFT
44380. BIFPLR3_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
44381. BIFPLR3_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
44382. BIFPLR3_2_HEADER__DEVICE_TYPE_MASK
44383. BIFPLR3_2_HEADER__DEVICE_TYPE__SHIFT
44384. BIFPLR3_2_HEADER__HEADER_TYPE_MASK
44385. BIFPLR3_2_HEADER__HEADER_TYPE__SHIFT
44386. BIFPLR3_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
44387. BIFPLR3_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
44388. BIFPLR3_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
44389. BIFPLR3_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
44390. BIFPLR3_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
44391. BIFPLR3_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
44392. BIFPLR3_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
44393. BIFPLR3_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
44394. BIFPLR3_2_IO_BASE_LIMIT__IO_BASE_MASK
44395. BIFPLR3_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
44396. BIFPLR3_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
44397. BIFPLR3_2_IO_BASE_LIMIT__IO_BASE__SHIFT
44398. BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT_MASK
44399. BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
44400. BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
44401. BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT
44402. BIFPLR3_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
44403. BIFPLR3_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
44404. BIFPLR3_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK
44405. BIFPLR3_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
44406. BIFPLR3_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
44407. BIFPLR3_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
44408. BIFPLR3_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
44409. BIFPLR3_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
44410. BIFPLR3_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
44411. BIFPLR3_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
44412. BIFPLR3_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK
44413. BIFPLR3_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
44414. BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
44415. BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
44416. BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK
44417. BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
44418. BIFPLR3_2_LATENCY__LATENCY_TIMER_MASK
44419. BIFPLR3_2_LATENCY__LATENCY_TIMER__SHIFT
44420. BIFPLR3_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
44421. BIFPLR3_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
44422. BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
44423. BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
44424. BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
44425. BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
44426. BIFPLR3_2_LINK_CAP2__RESERVED_MASK
44427. BIFPLR3_2_LINK_CAP2__RESERVED__SHIFT
44428. BIFPLR3_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
44429. BIFPLR3_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
44430. BIFPLR3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
44431. BIFPLR3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
44432. BIFPLR3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
44433. BIFPLR3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
44434. BIFPLR3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
44435. BIFPLR3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
44436. BIFPLR3_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
44437. BIFPLR3_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
44438. BIFPLR3_2_LINK_CAP__L1_EXIT_LATENCY_MASK
44439. BIFPLR3_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
44440. BIFPLR3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
44441. BIFPLR3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
44442. BIFPLR3_2_LINK_CAP__LINK_SPEED_MASK
44443. BIFPLR3_2_LINK_CAP__LINK_SPEED__SHIFT
44444. BIFPLR3_2_LINK_CAP__LINK_WIDTH_MASK
44445. BIFPLR3_2_LINK_CAP__LINK_WIDTH__SHIFT
44446. BIFPLR3_2_LINK_CAP__PM_SUPPORT_MASK
44447. BIFPLR3_2_LINK_CAP__PM_SUPPORT__SHIFT
44448. BIFPLR3_2_LINK_CAP__PORT_NUMBER_MASK
44449. BIFPLR3_2_LINK_CAP__PORT_NUMBER__SHIFT
44450. BIFPLR3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
44451. BIFPLR3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
44452. BIFPLR3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
44453. BIFPLR3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
44454. BIFPLR3_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
44455. BIFPLR3_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
44456. BIFPLR3_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
44457. BIFPLR3_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
44458. BIFPLR3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
44459. BIFPLR3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
44460. BIFPLR3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
44461. BIFPLR3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
44462. BIFPLR3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
44463. BIFPLR3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
44464. BIFPLR3_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
44465. BIFPLR3_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
44466. BIFPLR3_2_LINK_CNTL2__XMIT_MARGIN_MASK
44467. BIFPLR3_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
44468. BIFPLR3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
44469. BIFPLR3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
44470. BIFPLR3_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
44471. BIFPLR3_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
44472. BIFPLR3_2_LINK_CNTL__EXTENDED_SYNC_MASK
44473. BIFPLR3_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
44474. BIFPLR3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
44475. BIFPLR3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
44476. BIFPLR3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
44477. BIFPLR3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
44478. BIFPLR3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
44479. BIFPLR3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
44480. BIFPLR3_2_LINK_CNTL__LINK_DIS_MASK
44481. BIFPLR3_2_LINK_CNTL__LINK_DIS__SHIFT
44482. BIFPLR3_2_LINK_CNTL__PM_CONTROL_MASK
44483. BIFPLR3_2_LINK_CNTL__PM_CONTROL__SHIFT
44484. BIFPLR3_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
44485. BIFPLR3_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
44486. BIFPLR3_2_LINK_CNTL__RETRAIN_LINK_MASK
44487. BIFPLR3_2_LINK_CNTL__RETRAIN_LINK__SHIFT
44488. BIFPLR3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
44489. BIFPLR3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
44490. BIFPLR3_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
44491. BIFPLR3_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
44492. BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
44493. BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
44494. BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
44495. BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
44496. BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
44497. BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
44498. BIFPLR3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
44499. BIFPLR3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
44500. BIFPLR3_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
44501. BIFPLR3_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
44502. BIFPLR3_2_LINK_STATUS__DL_ACTIVE_MASK
44503. BIFPLR3_2_LINK_STATUS__DL_ACTIVE__SHIFT
44504. BIFPLR3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
44505. BIFPLR3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
44506. BIFPLR3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
44507. BIFPLR3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
44508. BIFPLR3_2_LINK_STATUS__LINK_TRAINING_MASK
44509. BIFPLR3_2_LINK_STATUS__LINK_TRAINING__SHIFT
44510. BIFPLR3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
44511. BIFPLR3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
44512. BIFPLR3_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
44513. BIFPLR3_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
44514. BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
44515. BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
44516. BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
44517. BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
44518. BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
44519. BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
44520. BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
44521. BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
44522. BIFPLR3_2_MSI_CAP_LIST__CAP_ID_MASK
44523. BIFPLR3_2_MSI_CAP_LIST__CAP_ID__SHIFT
44524. BIFPLR3_2_MSI_CAP_LIST__NEXT_PTR_MASK
44525. BIFPLR3_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
44526. BIFPLR3_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
44527. BIFPLR3_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
44528. BIFPLR3_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
44529. BIFPLR3_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
44530. BIFPLR3_2_MSI_MAP_CAP_LIST__CAP_ID_MASK
44531. BIFPLR3_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
44532. BIFPLR3_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
44533. BIFPLR3_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
44534. BIFPLR3_2_MSI_MAP_CAP__CAP_TYPE_MASK
44535. BIFPLR3_2_MSI_MAP_CAP__CAP_TYPE__SHIFT
44536. BIFPLR3_2_MSI_MAP_CAP__EN_MASK
44537. BIFPLR3_2_MSI_MAP_CAP__EN__SHIFT
44538. BIFPLR3_2_MSI_MAP_CAP__FIXD_MASK
44539. BIFPLR3_2_MSI_MAP_CAP__FIXD__SHIFT
44540. BIFPLR3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
44541. BIFPLR3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
44542. BIFPLR3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
44543. BIFPLR3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
44544. BIFPLR3_2_MSI_MSG_CNTL__MSI_64BIT_MASK
44545. BIFPLR3_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
44546. BIFPLR3_2_MSI_MSG_CNTL__MSI_EN_MASK
44547. BIFPLR3_2_MSI_MSG_CNTL__MSI_EN__SHIFT
44548. BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
44549. BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
44550. BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
44551. BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
44552. BIFPLR3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
44553. BIFPLR3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
44554. BIFPLR3_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
44555. BIFPLR3_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
44556. BIFPLR3_2_MSI_MSG_DATA__MSI_DATA_MASK
44557. BIFPLR3_2_MSI_MSG_DATA__MSI_DATA__SHIFT
44558. BIFPLR3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
44559. BIFPLR3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
44560. BIFPLR3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
44561. BIFPLR3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
44562. BIFPLR3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
44563. BIFPLR3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
44564. BIFPLR3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
44565. BIFPLR3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
44566. BIFPLR3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
44567. BIFPLR3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
44568. BIFPLR3_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
44569. BIFPLR3_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
44570. BIFPLR3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
44571. BIFPLR3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
44572. BIFPLR3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
44573. BIFPLR3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
44574. BIFPLR3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
44575. BIFPLR3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
44576. BIFPLR3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
44577. BIFPLR3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
44578. BIFPLR3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
44579. BIFPLR3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
44580. BIFPLR3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
44581. BIFPLR3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
44582. BIFPLR3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
44583. BIFPLR3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
44584. BIFPLR3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
44585. BIFPLR3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
44586. BIFPLR3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
44587. BIFPLR3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
44588. BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
44589. BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
44590. BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
44591. BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
44592. BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
44593. BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
44594. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
44595. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
44596. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
44597. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
44598. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
44599. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
44600. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
44601. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
44602. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
44603. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
44604. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
44605. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
44606. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
44607. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
44608. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
44609. BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
44610. BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
44611. BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
44612. BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
44613. BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
44614. BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
44615. BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
44616. BIFPLR3_2_PCIE_CAP_LIST__CAP_ID_MASK
44617. BIFPLR3_2_PCIE_CAP_LIST__CAP_ID__SHIFT
44618. BIFPLR3_2_PCIE_CAP_LIST__NEXT_PTR_MASK
44619. BIFPLR3_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
44620. BIFPLR3_2_PCIE_CAP__DEVICE_TYPE_MASK
44621. BIFPLR3_2_PCIE_CAP__DEVICE_TYPE__SHIFT
44622. BIFPLR3_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
44623. BIFPLR3_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
44624. BIFPLR3_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
44625. BIFPLR3_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
44626. BIFPLR3_2_PCIE_CAP__VERSION_MASK
44627. BIFPLR3_2_PCIE_CAP__VERSION__SHIFT
44628. BIFPLR3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
44629. BIFPLR3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
44630. BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
44631. BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
44632. BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
44633. BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
44634. BIFPLR3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
44635. BIFPLR3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
44636. BIFPLR3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
44637. BIFPLR3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
44638. BIFPLR3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
44639. BIFPLR3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
44640. BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
44641. BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
44642. BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
44643. BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
44644. BIFPLR3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
44645. BIFPLR3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
44646. BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
44647. BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
44648. BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
44649. BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
44650. BIFPLR3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
44651. BIFPLR3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
44652. BIFPLR3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
44653. BIFPLR3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
44654. BIFPLR3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
44655. BIFPLR3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
44656. BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
44657. BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
44658. BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
44659. BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
44660. BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
44661. BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
44662. BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
44663. BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
44664. BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
44665. BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
44666. BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
44667. BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
44668. BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
44669. BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
44670. BIFPLR3_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
44671. BIFPLR3_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
44672. BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
44673. BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
44674. BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
44675. BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
44676. BIFPLR3_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
44677. BIFPLR3_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
44678. BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
44679. BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
44680. BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
44681. BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
44682. BIFPLR3_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
44683. BIFPLR3_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
44684. BIFPLR3_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
44685. BIFPLR3_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
44686. BIFPLR3_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
44687. BIFPLR3_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
44688. BIFPLR3_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
44689. BIFPLR3_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
44690. BIFPLR3_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
44691. BIFPLR3_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
44692. BIFPLR3_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
44693. BIFPLR3_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
44694. BIFPLR3_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
44695. BIFPLR3_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
44696. BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
44697. BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
44698. BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
44699. BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
44700. BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
44701. BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
44702. BIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
44703. BIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
44704. BIFPLR3_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
44705. BIFPLR3_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
44706. BIFPLR3_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
44707. BIFPLR3_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
44708. BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
44709. BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
44710. BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
44711. BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
44712. BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
44713. BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
44714. BIFPLR3_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
44715. BIFPLR3_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
44716. BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
44717. BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
44718. BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
44719. BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
44720. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK
44721. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
44722. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK
44723. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
44724. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK
44725. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
44726. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK
44727. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
44728. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK
44729. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
44730. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK
44731. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
44732. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK
44733. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
44734. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK
44735. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
44736. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK
44737. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
44738. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK
44739. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
44740. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK
44741. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
44742. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK
44743. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
44744. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK
44745. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
44746. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK
44747. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
44748. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK
44749. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
44750. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK
44751. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
44752. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK
44753. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
44754. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK
44755. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
44756. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK
44757. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
44758. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK
44759. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
44760. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK
44761. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
44762. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK
44763. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
44764. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK
44765. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
44766. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK
44767. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
44768. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK
44769. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
44770. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK
44771. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
44772. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK
44773. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
44774. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK
44775. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
44776. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK
44777. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
44778. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK
44779. BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
44780. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK
44781. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
44782. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK
44783. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
44784. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK
44785. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
44786. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK
44787. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
44788. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK
44789. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
44790. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK
44791. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
44792. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK
44793. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
44794. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK
44795. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
44796. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK
44797. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
44798. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK
44799. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
44800. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK
44801. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
44802. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK
44803. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
44804. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK
44805. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
44806. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK
44807. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
44808. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK
44809. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
44810. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK
44811. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
44812. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK
44813. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
44814. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK
44815. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
44816. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK
44817. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
44818. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK
44819. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
44820. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK
44821. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
44822. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK
44823. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
44824. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK
44825. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
44826. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK
44827. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
44828. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK
44829. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
44830. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK
44831. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
44832. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK
44833. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
44834. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK
44835. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
44836. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK
44837. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
44838. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK
44839. BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
44840. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK
44841. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
44842. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK
44843. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
44844. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK
44845. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
44846. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK
44847. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
44848. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK
44849. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
44850. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK
44851. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
44852. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK
44853. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
44854. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK
44855. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
44856. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK
44857. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
44858. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK
44859. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
44860. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK
44861. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
44862. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK
44863. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
44864. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK
44865. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
44866. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK
44867. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
44868. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK
44869. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
44870. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK
44871. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
44872. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK
44873. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
44874. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK
44875. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
44876. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK
44877. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
44878. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK
44879. BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
44880. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK
44881. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
44882. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK
44883. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
44884. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK
44885. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
44886. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK
44887. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
44888. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK
44889. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
44890. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK
44891. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
44892. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK
44893. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
44894. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK
44895. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
44896. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK
44897. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
44898. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK
44899. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
44900. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK
44901. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
44902. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK
44903. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
44904. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK
44905. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
44906. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK
44907. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
44908. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK
44909. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
44910. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK
44911. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
44912. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK
44913. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
44914. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK
44915. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
44916. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK
44917. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
44918. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK
44919. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
44920. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK
44921. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
44922. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK
44923. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
44924. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK
44925. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
44926. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK
44927. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
44928. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK
44929. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
44930. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK
44931. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
44932. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK
44933. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
44934. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK
44935. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
44936. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK
44937. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
44938. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK
44939. BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
44940. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK
44941. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
44942. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK
44943. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
44944. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK
44945. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
44946. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK
44947. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
44948. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK
44949. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
44950. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK
44951. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
44952. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK
44953. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
44954. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK
44955. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
44956. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK
44957. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
44958. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK
44959. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
44960. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK
44961. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
44962. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK
44963. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
44964. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK
44965. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
44966. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK
44967. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
44968. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK
44969. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
44970. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK
44971. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
44972. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK
44973. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
44974. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK
44975. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
44976. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK
44977. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
44978. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK
44979. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
44980. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK
44981. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
44982. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK
44983. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
44984. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK
44985. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
44986. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK
44987. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
44988. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK
44989. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
44990. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK
44991. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
44992. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK
44993. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
44994. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK
44995. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
44996. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK
44997. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
44998. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK
44999. BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
45000. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK
45001. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
45002. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK
45003. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
45004. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK
45005. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
45006. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK
45007. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
45008. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK
45009. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
45010. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK
45011. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
45012. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK
45013. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
45014. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK
45015. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
45016. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK
45017. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
45018. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK
45019. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
45020. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK
45021. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
45022. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK
45023. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
45024. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK
45025. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
45026. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK
45027. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
45028. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK
45029. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
45030. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK
45031. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
45032. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK
45033. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
45034. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK
45035. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
45036. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK
45037. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
45038. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK
45039. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
45040. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK
45041. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
45042. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK
45043. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
45044. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK
45045. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
45046. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK
45047. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
45048. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK
45049. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
45050. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK
45051. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
45052. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK
45053. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
45054. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK
45055. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
45056. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK
45057. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
45058. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK
45059. BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
45060. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK
45061. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
45062. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK
45063. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
45064. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK
45065. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
45066. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK
45067. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
45068. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK
45069. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
45070. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK
45071. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
45072. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK
45073. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
45074. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK
45075. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
45076. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK
45077. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
45078. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK
45079. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
45080. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK
45081. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
45082. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK
45083. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
45084. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK
45085. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
45086. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK
45087. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
45088. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK
45089. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
45090. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK
45091. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
45092. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK
45093. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
45094. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK
45095. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
45096. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK
45097. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
45098. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK
45099. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
45100. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK
45101. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
45102. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK
45103. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
45104. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK
45105. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
45106. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK
45107. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
45108. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK
45109. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
45110. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK
45111. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
45112. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK
45113. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
45114. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK
45115. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
45116. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK
45117. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
45118. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK
45119. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
45120. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK
45121. BIFPLR3_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
45122. BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK
45123. BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
45124. BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK
45125. BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
45126. BIFPLR3_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
45127. BIFPLR3_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
45128. BIFPLR3_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK
45129. BIFPLR3_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
45130. BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
45131. BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
45132. BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
45133. BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
45134. BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
45135. BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
45136. BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
45137. BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
45138. BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
45139. BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
45140. BIFPLR3_2_PCIE_ESM_HEADER_2__CAP_ID_MASK
45141. BIFPLR3_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
45142. BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
45143. BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
45144. BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
45145. BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
45146. BIFPLR3_2_PCIE_HDR_LOG0__TLP_HDR_MASK
45147. BIFPLR3_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
45148. BIFPLR3_2_PCIE_HDR_LOG1__TLP_HDR_MASK
45149. BIFPLR3_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
45150. BIFPLR3_2_PCIE_HDR_LOG2__TLP_HDR_MASK
45151. BIFPLR3_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
45152. BIFPLR3_2_PCIE_HDR_LOG3__TLP_HDR_MASK
45153. BIFPLR3_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
45154. BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
45155. BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
45156. BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
45157. BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
45158. BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
45159. BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
45160. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
45161. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
45162. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
45163. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
45164. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
45165. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
45166. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
45167. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
45168. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
45169. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
45170. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
45171. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
45172. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
45173. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
45174. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
45175. BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
45176. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
45177. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
45178. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
45179. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
45180. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
45181. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
45182. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
45183. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
45184. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
45185. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
45186. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
45187. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
45188. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
45189. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
45190. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
45191. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
45192. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
45193. BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
45194. BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45195. BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45196. BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45197. BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45198. BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45199. BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45200. BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45201. BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45202. BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45203. BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45204. BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45205. BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45206. BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45207. BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45208. BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45209. BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45210. BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45211. BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45212. BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45213. BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45214. BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45215. BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45216. BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45217. BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45218. BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45219. BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45220. BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45221. BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45222. BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45223. BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45224. BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45225. BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45226. BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45227. BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45228. BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45229. BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45230. BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45231. BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45232. BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45233. BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45234. BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45235. BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45236. BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45237. BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45238. BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45239. BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45240. BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45241. BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45242. BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45243. BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45244. BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45245. BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45246. BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45247. BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45248. BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45249. BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45250. BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45251. BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45252. BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45253. BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45254. BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45255. BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45256. BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45257. BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45258. BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45259. BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45260. BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45261. BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45262. BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45263. BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45264. BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45265. BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45266. BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45267. BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45268. BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45269. BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45270. BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45271. BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45272. BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45273. BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45274. BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45275. BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45276. BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45277. BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45278. BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45279. BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45280. BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45281. BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45282. BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45283. BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45284. BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45285. BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45286. BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45287. BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45288. BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45289. BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45290. BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45291. BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45292. BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45293. BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45294. BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45295. BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45296. BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45297. BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45298. BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45299. BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45300. BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45301. BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45302. BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45303. BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45304. BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45305. BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45306. BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45307. BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45308. BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45309. BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45310. BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45311. BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45312. BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45313. BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45314. BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
45315. BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
45316. BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
45317. BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
45318. BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
45319. BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
45320. BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
45321. BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
45322. BIFPLR3_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
45323. BIFPLR3_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
45324. BIFPLR3_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
45325. BIFPLR3_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
45326. BIFPLR3_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
45327. BIFPLR3_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
45328. BIFPLR3_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
45329. BIFPLR3_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
45330. BIFPLR3_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
45331. BIFPLR3_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
45332. BIFPLR3_2_PCIE_LINK_CNTL3__RESERVED_MASK
45333. BIFPLR3_2_PCIE_LINK_CNTL3__RESERVED__SHIFT
45334. BIFPLR3_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
45335. BIFPLR3_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
45336. BIFPLR3_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
45337. BIFPLR3_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
45338. BIFPLR3_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
45339. BIFPLR3_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
45340. BIFPLR3_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
45341. BIFPLR3_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
45342. BIFPLR3_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
45343. BIFPLR3_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
45344. BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
45345. BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
45346. BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
45347. BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
45348. BIFPLR3_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
45349. BIFPLR3_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
45350. BIFPLR3_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK
45351. BIFPLR3_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
45352. BIFPLR3_2_PCIE_MC_CNTL__MC_ENABLE_MASK
45353. BIFPLR3_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT
45354. BIFPLR3_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
45355. BIFPLR3_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
45356. BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
45357. BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
45358. BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
45359. BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
45360. BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
45361. BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
45362. BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
45363. BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
45364. BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
45365. BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
45366. BIFPLR3_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
45367. BIFPLR3_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
45368. BIFPLR3_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
45369. BIFPLR3_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
45370. BIFPLR3_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
45371. BIFPLR3_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
45372. BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
45373. BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
45374. BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
45375. BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
45376. BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
45377. BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
45378. BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
45379. BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
45380. BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
45381. BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
45382. BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
45383. BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
45384. BIFPLR3_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
45385. BIFPLR3_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
45386. BIFPLR3_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
45387. BIFPLR3_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
45388. BIFPLR3_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
45389. BIFPLR3_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
45390. BIFPLR3_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
45391. BIFPLR3_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
45392. BIFPLR3_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
45393. BIFPLR3_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
45394. BIFPLR3_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
45395. BIFPLR3_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
45396. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
45397. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
45398. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
45399. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
45400. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
45401. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
45402. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
45403. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
45404. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
45405. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
45406. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
45407. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
45408. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
45409. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
45410. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
45411. BIFPLR3_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
45412. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
45413. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
45414. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
45415. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
45416. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
45417. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
45418. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
45419. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
45420. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
45421. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
45422. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
45423. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
45424. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
45425. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
45426. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
45427. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
45428. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
45429. BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
45430. BIFPLR3_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
45431. BIFPLR3_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
45432. BIFPLR3_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
45433. BIFPLR3_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
45434. BIFPLR3_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
45435. BIFPLR3_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
45436. BIFPLR3_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
45437. BIFPLR3_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
45438. BIFPLR3_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
45439. BIFPLR3_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
45440. BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
45441. BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
45442. BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK
45443. BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
45444. BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
45445. BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
45446. BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
45447. BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
45448. BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CTO_MASK
45449. BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
45450. BIFPLR3_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
45451. BIFPLR3_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
45452. BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
45453. BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
45454. BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK
45455. BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
45456. BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
45457. BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
45458. BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
45459. BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
45460. BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
45461. BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
45462. BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
45463. BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
45464. BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
45465. BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
45466. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
45467. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
45468. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
45469. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
45470. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
45471. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
45472. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
45473. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
45474. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
45475. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
45476. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
45477. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
45478. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
45479. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
45480. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
45481. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
45482. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
45483. BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
45484. BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
45485. BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
45486. BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
45487. BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
45488. BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
45489. BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
45490. BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
45491. BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
45492. BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK
45493. BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
45494. BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
45495. BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
45496. BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
45497. BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
45498. BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
45499. BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
45500. BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
45501. BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
45502. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
45503. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
45504. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
45505. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
45506. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
45507. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
45508. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
45509. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
45510. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
45511. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
45512. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
45513. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
45514. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
45515. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
45516. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
45517. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
45518. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
45519. BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
45520. BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
45521. BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
45522. BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
45523. BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
45524. BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
45525. BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
45526. BIFPLR3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
45527. BIFPLR3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
45528. BIFPLR3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
45529. BIFPLR3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
45530. BIFPLR3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
45531. BIFPLR3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
45532. BIFPLR3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
45533. BIFPLR3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
45534. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
45535. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
45536. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
45537. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
45538. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
45539. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
45540. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
45541. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
45542. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
45543. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
45544. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
45545. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
45546. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
45547. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
45548. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
45549. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
45550. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
45551. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
45552. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
45553. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
45554. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
45555. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
45556. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
45557. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
45558. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
45559. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
45560. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
45561. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
45562. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
45563. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
45564. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
45565. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
45566. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
45567. BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
45568. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
45569. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
45570. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
45571. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
45572. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
45573. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
45574. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
45575. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
45576. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
45577. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
45578. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
45579. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
45580. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
45581. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
45582. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
45583. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
45584. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
45585. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
45586. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
45587. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
45588. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
45589. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
45590. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
45591. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
45592. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
45593. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
45594. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
45595. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
45596. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
45597. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
45598. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
45599. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
45600. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
45601. BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
45602. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
45603. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
45604. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
45605. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
45606. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
45607. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
45608. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
45609. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
45610. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
45611. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
45612. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
45613. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
45614. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
45615. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
45616. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
45617. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
45618. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
45619. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
45620. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
45621. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
45622. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
45623. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
45624. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
45625. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
45626. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
45627. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
45628. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
45629. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
45630. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
45631. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
45632. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
45633. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
45634. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
45635. BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
45636. BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
45637. BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
45638. BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
45639. BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
45640. BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
45641. BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
45642. BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
45643. BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
45644. BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
45645. BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
45646. BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
45647. BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
45648. BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
45649. BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
45650. BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
45651. BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
45652. BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
45653. BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
45654. BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
45655. BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
45656. BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
45657. BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
45658. BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
45659. BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
45660. BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
45661. BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
45662. BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
45663. BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
45664. BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
45665. BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
45666. BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
45667. BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
45668. BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
45669. BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
45670. BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
45671. BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
45672. BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
45673. BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
45674. BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
45675. BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
45676. BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
45677. BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
45678. BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
45679. BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
45680. BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
45681. BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
45682. BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
45683. BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
45684. BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
45685. BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
45686. BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
45687. BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
45688. BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
45689. BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
45690. BIFPLR3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
45691. BIFPLR3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
45692. BIFPLR3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
45693. BIFPLR3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
45694. BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
45695. BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
45696. BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
45697. BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
45698. BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
45699. BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
45700. BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
45701. BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
45702. BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
45703. BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
45704. BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
45705. BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
45706. BIFPLR3_2_PMI_CAP_LIST__CAP_ID_MASK
45707. BIFPLR3_2_PMI_CAP_LIST__CAP_ID__SHIFT
45708. BIFPLR3_2_PMI_CAP_LIST__NEXT_PTR_MASK
45709. BIFPLR3_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
45710. BIFPLR3_2_PMI_CAP__AUX_CURRENT_MASK
45711. BIFPLR3_2_PMI_CAP__AUX_CURRENT__SHIFT
45712. BIFPLR3_2_PMI_CAP__D1_SUPPORT_MASK
45713. BIFPLR3_2_PMI_CAP__D1_SUPPORT__SHIFT
45714. BIFPLR3_2_PMI_CAP__D2_SUPPORT_MASK
45715. BIFPLR3_2_PMI_CAP__D2_SUPPORT__SHIFT
45716. BIFPLR3_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
45717. BIFPLR3_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
45718. BIFPLR3_2_PMI_CAP__PME_CLOCK_MASK
45719. BIFPLR3_2_PMI_CAP__PME_CLOCK__SHIFT
45720. BIFPLR3_2_PMI_CAP__PME_SUPPORT_MASK
45721. BIFPLR3_2_PMI_CAP__PME_SUPPORT__SHIFT
45722. BIFPLR3_2_PMI_CAP__VERSION_MASK
45723. BIFPLR3_2_PMI_CAP__VERSION__SHIFT
45724. BIFPLR3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
45725. BIFPLR3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
45726. BIFPLR3_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
45727. BIFPLR3_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
45728. BIFPLR3_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
45729. BIFPLR3_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
45730. BIFPLR3_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
45731. BIFPLR3_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
45732. BIFPLR3_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
45733. BIFPLR3_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
45734. BIFPLR3_2_PMI_STATUS_CNTL__PME_EN_MASK
45735. BIFPLR3_2_PMI_STATUS_CNTL__PME_EN__SHIFT
45736. BIFPLR3_2_PMI_STATUS_CNTL__PME_STATUS_MASK
45737. BIFPLR3_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
45738. BIFPLR3_2_PMI_STATUS_CNTL__PMI_DATA_MASK
45739. BIFPLR3_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
45740. BIFPLR3_2_PMI_STATUS_CNTL__POWER_STATE_MASK
45741. BIFPLR3_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
45742. BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
45743. BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
45744. BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
45745. BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
45746. BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
45747. BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
45748. BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
45749. BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
45750. BIFPLR3_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
45751. BIFPLR3_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
45752. BIFPLR3_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
45753. BIFPLR3_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
45754. BIFPLR3_2_PROG_INTERFACE__PROG_INTERFACE_MASK
45755. BIFPLR3_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
45756. BIFPLR3_2_REVISION_ID__MAJOR_REV_ID_MASK
45757. BIFPLR3_2_REVISION_ID__MAJOR_REV_ID__SHIFT
45758. BIFPLR3_2_REVISION_ID__MINOR_REV_ID_MASK
45759. BIFPLR3_2_REVISION_ID__MINOR_REV_ID__SHIFT
45760. BIFPLR3_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
45761. BIFPLR3_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
45762. BIFPLR3_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
45763. BIFPLR3_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
45764. BIFPLR3_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK
45765. BIFPLR3_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
45766. BIFPLR3_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
45767. BIFPLR3_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
45768. BIFPLR3_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
45769. BIFPLR3_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
45770. BIFPLR3_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
45771. BIFPLR3_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
45772. BIFPLR3_2_ROOT_STATUS__PME_PENDING_MASK
45773. BIFPLR3_2_ROOT_STATUS__PME_PENDING__SHIFT
45774. BIFPLR3_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK
45775. BIFPLR3_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
45776. BIFPLR3_2_ROOT_STATUS__PME_STATUS_MASK
45777. BIFPLR3_2_ROOT_STATUS__PME_STATUS__SHIFT
45778. BIFPLR3_2_SECONDARY_STATUS__CAP_LIST_MASK
45779. BIFPLR3_2_SECONDARY_STATUS__CAP_LIST__SHIFT
45780. BIFPLR3_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK
45781. BIFPLR3_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
45782. BIFPLR3_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
45783. BIFPLR3_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
45784. BIFPLR3_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
45785. BIFPLR3_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
45786. BIFPLR3_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
45787. BIFPLR3_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
45788. BIFPLR3_2_SECONDARY_STATUS__PCI_66_EN_MASK
45789. BIFPLR3_2_SECONDARY_STATUS__PCI_66_EN__SHIFT
45790. BIFPLR3_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
45791. BIFPLR3_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
45792. BIFPLR3_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
45793. BIFPLR3_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
45794. BIFPLR3_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
45795. BIFPLR3_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
45796. BIFPLR3_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
45797. BIFPLR3_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
45798. BIFPLR3_2_SLOT_CAP2__RESERVED_MASK
45799. BIFPLR3_2_SLOT_CAP2__RESERVED__SHIFT
45800. BIFPLR3_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
45801. BIFPLR3_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
45802. BIFPLR3_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
45803. BIFPLR3_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
45804. BIFPLR3_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
45805. BIFPLR3_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
45806. BIFPLR3_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK
45807. BIFPLR3_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
45808. BIFPLR3_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK
45809. BIFPLR3_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
45810. BIFPLR3_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
45811. BIFPLR3_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
45812. BIFPLR3_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
45813. BIFPLR3_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
45814. BIFPLR3_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
45815. BIFPLR3_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
45816. BIFPLR3_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
45817. BIFPLR3_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
45818. BIFPLR3_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
45819. BIFPLR3_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
45820. BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
45821. BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
45822. BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
45823. BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
45824. BIFPLR3_2_SLOT_CNTL2__RESERVED_MASK
45825. BIFPLR3_2_SLOT_CNTL2__RESERVED__SHIFT
45826. BIFPLR3_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
45827. BIFPLR3_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
45828. BIFPLR3_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
45829. BIFPLR3_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
45830. BIFPLR3_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
45831. BIFPLR3_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
45832. BIFPLR3_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
45833. BIFPLR3_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
45834. BIFPLR3_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
45835. BIFPLR3_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
45836. BIFPLR3_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
45837. BIFPLR3_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
45838. BIFPLR3_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
45839. BIFPLR3_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
45840. BIFPLR3_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
45841. BIFPLR3_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
45842. BIFPLR3_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
45843. BIFPLR3_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
45844. BIFPLR3_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
45845. BIFPLR3_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
45846. BIFPLR3_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
45847. BIFPLR3_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
45848. BIFPLR3_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
45849. BIFPLR3_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
45850. BIFPLR3_2_SLOT_STATUS2__RESERVED_MASK
45851. BIFPLR3_2_SLOT_STATUS2__RESERVED__SHIFT
45852. BIFPLR3_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
45853. BIFPLR3_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
45854. BIFPLR3_2_SLOT_STATUS__COMMAND_COMPLETED_MASK
45855. BIFPLR3_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
45856. BIFPLR3_2_SLOT_STATUS__DL_STATE_CHANGED_MASK
45857. BIFPLR3_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
45858. BIFPLR3_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
45859. BIFPLR3_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
45860. BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
45861. BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
45862. BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK
45863. BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
45864. BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
45865. BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
45866. BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
45867. BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
45868. BIFPLR3_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
45869. BIFPLR3_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
45870. BIFPLR3_2_SSID_CAP_LIST__CAP_ID_MASK
45871. BIFPLR3_2_SSID_CAP_LIST__CAP_ID__SHIFT
45872. BIFPLR3_2_SSID_CAP_LIST__NEXT_PTR_MASK
45873. BIFPLR3_2_SSID_CAP_LIST__NEXT_PTR__SHIFT
45874. BIFPLR3_2_SSID_CAP__SUBSYSTEM_ID_MASK
45875. BIFPLR3_2_SSID_CAP__SUBSYSTEM_ID__SHIFT
45876. BIFPLR3_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
45877. BIFPLR3_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
45878. BIFPLR3_2_STATUS__CAP_LIST_MASK
45879. BIFPLR3_2_STATUS__CAP_LIST__SHIFT
45880. BIFPLR3_2_STATUS__DEVSEL_TIMING_MASK
45881. BIFPLR3_2_STATUS__DEVSEL_TIMING__SHIFT
45882. BIFPLR3_2_STATUS__FAST_BACK_CAPABLE_MASK
45883. BIFPLR3_2_STATUS__FAST_BACK_CAPABLE__SHIFT
45884. BIFPLR3_2_STATUS__INT_STATUS_MASK
45885. BIFPLR3_2_STATUS__INT_STATUS__SHIFT
45886. BIFPLR3_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
45887. BIFPLR3_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
45888. BIFPLR3_2_STATUS__PARITY_ERROR_DETECTED_MASK
45889. BIFPLR3_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
45890. BIFPLR3_2_STATUS__PCI_66_EN_MASK
45891. BIFPLR3_2_STATUS__PCI_66_EN__SHIFT
45892. BIFPLR3_2_STATUS__RECEIVED_MASTER_ABORT_MASK
45893. BIFPLR3_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
45894. BIFPLR3_2_STATUS__RECEIVED_TARGET_ABORT_MASK
45895. BIFPLR3_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
45896. BIFPLR3_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
45897. BIFPLR3_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
45898. BIFPLR3_2_STATUS__SIGNAL_TARGET_ABORT_MASK
45899. BIFPLR3_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
45900. BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
45901. BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
45902. BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
45903. BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
45904. BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
45905. BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
45906. BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
45907. BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
45908. BIFPLR3_2_SUB_CLASS__SUB_CLASS_MASK
45909. BIFPLR3_2_SUB_CLASS__SUB_CLASS__SHIFT
45910. BIFPLR3_2_VENDOR_ID__VENDOR_ID_MASK
45911. BIFPLR3_2_VENDOR_ID__VENDOR_ID__SHIFT
45912. BIFPLR4_0_BASE_CLASS__BASE_CLASS_MASK
45913. BIFPLR4_0_BASE_CLASS__BASE_CLASS__SHIFT
45914. BIFPLR4_0_BIST__BIST_CAP_MASK
45915. BIFPLR4_0_BIST__BIST_CAP__SHIFT
45916. BIFPLR4_0_BIST__BIST_COMP_MASK
45917. BIFPLR4_0_BIST__BIST_COMP__SHIFT
45918. BIFPLR4_0_BIST__BIST_STRT_MASK
45919. BIFPLR4_0_BIST__BIST_STRT__SHIFT
45920. BIFPLR4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
45921. BIFPLR4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
45922. BIFPLR4_0_CAP_PTR__CAP_PTR_MASK
45923. BIFPLR4_0_CAP_PTR__CAP_PTR__SHIFT
45924. BIFPLR4_0_COMMAND__AD_STEPPING_MASK
45925. BIFPLR4_0_COMMAND__AD_STEPPING__SHIFT
45926. BIFPLR4_0_COMMAND__BUS_MASTER_EN_MASK
45927. BIFPLR4_0_COMMAND__BUS_MASTER_EN__SHIFT
45928. BIFPLR4_0_COMMAND__FAST_B2B_EN_MASK
45929. BIFPLR4_0_COMMAND__FAST_B2B_EN__SHIFT
45930. BIFPLR4_0_COMMAND__INT_DIS_MASK
45931. BIFPLR4_0_COMMAND__INT_DIS__SHIFT
45932. BIFPLR4_0_COMMAND__IO_ACCESS_EN_MASK
45933. BIFPLR4_0_COMMAND__IO_ACCESS_EN__SHIFT
45934. BIFPLR4_0_COMMAND__MEM_ACCESS_EN_MASK
45935. BIFPLR4_0_COMMAND__MEM_ACCESS_EN__SHIFT
45936. BIFPLR4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
45937. BIFPLR4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
45938. BIFPLR4_0_COMMAND__PAL_SNOOP_EN_MASK
45939. BIFPLR4_0_COMMAND__PAL_SNOOP_EN__SHIFT
45940. BIFPLR4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
45941. BIFPLR4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
45942. BIFPLR4_0_COMMAND__SERR_EN_MASK
45943. BIFPLR4_0_COMMAND__SERR_EN__SHIFT
45944. BIFPLR4_0_COMMAND__SPECIAL_CYCLE_EN_MASK
45945. BIFPLR4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
45946. BIFPLR4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
45947. BIFPLR4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
45948. BIFPLR4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
45949. BIFPLR4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
45950. BIFPLR4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
45951. BIFPLR4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
45952. BIFPLR4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
45953. BIFPLR4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
45954. BIFPLR4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
45955. BIFPLR4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
45956. BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
45957. BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
45958. BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
45959. BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
45960. BIFPLR4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
45961. BIFPLR4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
45962. BIFPLR4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
45963. BIFPLR4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
45964. BIFPLR4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
45965. BIFPLR4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
45966. BIFPLR4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
45967. BIFPLR4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
45968. BIFPLR4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
45969. BIFPLR4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
45970. BIFPLR4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
45971. BIFPLR4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
45972. BIFPLR4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
45973. BIFPLR4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
45974. BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
45975. BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
45976. BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
45977. BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
45978. BIFPLR4_0_DEVICE_CAP__EXTENDED_TAG_MASK
45979. BIFPLR4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
45980. BIFPLR4_0_DEVICE_CAP__FLR_CAPABLE_MASK
45981. BIFPLR4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
45982. BIFPLR4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
45983. BIFPLR4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
45984. BIFPLR4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
45985. BIFPLR4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
45986. BIFPLR4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
45987. BIFPLR4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
45988. BIFPLR4_0_DEVICE_CAP__PHANTOM_FUNC_MASK
45989. BIFPLR4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
45990. BIFPLR4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
45991. BIFPLR4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
45992. BIFPLR4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
45993. BIFPLR4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
45994. BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
45995. BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
45996. BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
45997. BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
45998. BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
45999. BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
46000. BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
46001. BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
46002. BIFPLR4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
46003. BIFPLR4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
46004. BIFPLR4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
46005. BIFPLR4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
46006. BIFPLR4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
46007. BIFPLR4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
46008. BIFPLR4_0_DEVICE_CNTL2__LTR_EN_MASK
46009. BIFPLR4_0_DEVICE_CNTL2__LTR_EN__SHIFT
46010. BIFPLR4_0_DEVICE_CNTL2__OBFF_EN_MASK
46011. BIFPLR4_0_DEVICE_CNTL2__OBFF_EN__SHIFT
46012. BIFPLR4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
46013. BIFPLR4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
46014. BIFPLR4_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
46015. BIFPLR4_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
46016. BIFPLR4_0_DEVICE_CNTL__CORR_ERR_EN_MASK
46017. BIFPLR4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
46018. BIFPLR4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
46019. BIFPLR4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
46020. BIFPLR4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
46021. BIFPLR4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
46022. BIFPLR4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
46023. BIFPLR4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
46024. BIFPLR4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
46025. BIFPLR4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
46026. BIFPLR4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
46027. BIFPLR4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
46028. BIFPLR4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
46029. BIFPLR4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
46030. BIFPLR4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
46031. BIFPLR4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
46032. BIFPLR4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
46033. BIFPLR4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
46034. BIFPLR4_0_DEVICE_CNTL__USR_REPORT_EN_MASK
46035. BIFPLR4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
46036. BIFPLR4_0_DEVICE_ID__DEVICE_ID_MASK
46037. BIFPLR4_0_DEVICE_ID__DEVICE_ID__SHIFT
46038. BIFPLR4_0_DEVICE_STATUS2__RESERVED_MASK
46039. BIFPLR4_0_DEVICE_STATUS2__RESERVED__SHIFT
46040. BIFPLR4_0_DEVICE_STATUS__AUX_PWR_MASK
46041. BIFPLR4_0_DEVICE_STATUS__AUX_PWR__SHIFT
46042. BIFPLR4_0_DEVICE_STATUS__CORR_ERR_MASK
46043. BIFPLR4_0_DEVICE_STATUS__CORR_ERR__SHIFT
46044. BIFPLR4_0_DEVICE_STATUS__FATAL_ERR_MASK
46045. BIFPLR4_0_DEVICE_STATUS__FATAL_ERR__SHIFT
46046. BIFPLR4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
46047. BIFPLR4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
46048. BIFPLR4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
46049. BIFPLR4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
46050. BIFPLR4_0_DEVICE_STATUS__USR_DETECTED_MASK
46051. BIFPLR4_0_DEVICE_STATUS__USR_DETECTED__SHIFT
46052. BIFPLR4_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
46053. BIFPLR4_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
46054. BIFPLR4_0_HEADER__DEVICE_TYPE_MASK
46055. BIFPLR4_0_HEADER__DEVICE_TYPE__SHIFT
46056. BIFPLR4_0_HEADER__HEADER_TYPE_MASK
46057. BIFPLR4_0_HEADER__HEADER_TYPE__SHIFT
46058. BIFPLR4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
46059. BIFPLR4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
46060. BIFPLR4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
46061. BIFPLR4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
46062. BIFPLR4_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
46063. BIFPLR4_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
46064. BIFPLR4_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
46065. BIFPLR4_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
46066. BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_MASK
46067. BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
46068. BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
46069. BIFPLR4_0_IO_BASE_LIMIT__IO_BASE__SHIFT
46070. BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_MASK
46071. BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
46072. BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
46073. BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT
46074. BIFPLR4_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
46075. BIFPLR4_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
46076. BIFPLR4_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK
46077. BIFPLR4_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
46078. BIFPLR4_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
46079. BIFPLR4_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
46080. BIFPLR4_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
46081. BIFPLR4_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
46082. BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
46083. BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
46084. BIFPLR4_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK
46085. BIFPLR4_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
46086. BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
46087. BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
46088. BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK
46089. BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
46090. BIFPLR4_0_LATENCY__LATENCY_TIMER_MASK
46091. BIFPLR4_0_LATENCY__LATENCY_TIMER__SHIFT
46092. BIFPLR4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
46093. BIFPLR4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
46094. BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
46095. BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
46096. BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
46097. BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
46098. BIFPLR4_0_LINK_CAP2__RESERVED_MASK
46099. BIFPLR4_0_LINK_CAP2__RESERVED__SHIFT
46100. BIFPLR4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
46101. BIFPLR4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
46102. BIFPLR4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
46103. BIFPLR4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
46104. BIFPLR4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
46105. BIFPLR4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
46106. BIFPLR4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
46107. BIFPLR4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
46108. BIFPLR4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
46109. BIFPLR4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
46110. BIFPLR4_0_LINK_CAP__L1_EXIT_LATENCY_MASK
46111. BIFPLR4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
46112. BIFPLR4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
46113. BIFPLR4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
46114. BIFPLR4_0_LINK_CAP__LINK_SPEED_MASK
46115. BIFPLR4_0_LINK_CAP__LINK_SPEED__SHIFT
46116. BIFPLR4_0_LINK_CAP__LINK_WIDTH_MASK
46117. BIFPLR4_0_LINK_CAP__LINK_WIDTH__SHIFT
46118. BIFPLR4_0_LINK_CAP__PM_SUPPORT_MASK
46119. BIFPLR4_0_LINK_CAP__PM_SUPPORT__SHIFT
46120. BIFPLR4_0_LINK_CAP__PORT_NUMBER_MASK
46121. BIFPLR4_0_LINK_CAP__PORT_NUMBER__SHIFT
46122. BIFPLR4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
46123. BIFPLR4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
46124. BIFPLR4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
46125. BIFPLR4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
46126. BIFPLR4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
46127. BIFPLR4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
46128. BIFPLR4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
46129. BIFPLR4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
46130. BIFPLR4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
46131. BIFPLR4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
46132. BIFPLR4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
46133. BIFPLR4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
46134. BIFPLR4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
46135. BIFPLR4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
46136. BIFPLR4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
46137. BIFPLR4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
46138. BIFPLR4_0_LINK_CNTL2__XMIT_MARGIN_MASK
46139. BIFPLR4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
46140. BIFPLR4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
46141. BIFPLR4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
46142. BIFPLR4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
46143. BIFPLR4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
46144. BIFPLR4_0_LINK_CNTL__EXTENDED_SYNC_MASK
46145. BIFPLR4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
46146. BIFPLR4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
46147. BIFPLR4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
46148. BIFPLR4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
46149. BIFPLR4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
46150. BIFPLR4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
46151. BIFPLR4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
46152. BIFPLR4_0_LINK_CNTL__LINK_DIS_MASK
46153. BIFPLR4_0_LINK_CNTL__LINK_DIS__SHIFT
46154. BIFPLR4_0_LINK_CNTL__PM_CONTROL_MASK
46155. BIFPLR4_0_LINK_CNTL__PM_CONTROL__SHIFT
46156. BIFPLR4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
46157. BIFPLR4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
46158. BIFPLR4_0_LINK_CNTL__RETRAIN_LINK_MASK
46159. BIFPLR4_0_LINK_CNTL__RETRAIN_LINK__SHIFT
46160. BIFPLR4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
46161. BIFPLR4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
46162. BIFPLR4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
46163. BIFPLR4_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
46164. BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
46165. BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
46166. BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
46167. BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
46168. BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
46169. BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
46170. BIFPLR4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
46171. BIFPLR4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
46172. BIFPLR4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
46173. BIFPLR4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
46174. BIFPLR4_0_LINK_STATUS__DL_ACTIVE_MASK
46175. BIFPLR4_0_LINK_STATUS__DL_ACTIVE__SHIFT
46176. BIFPLR4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
46177. BIFPLR4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
46178. BIFPLR4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
46179. BIFPLR4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
46180. BIFPLR4_0_LINK_STATUS__LINK_TRAINING_MASK
46181. BIFPLR4_0_LINK_STATUS__LINK_TRAINING__SHIFT
46182. BIFPLR4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
46183. BIFPLR4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
46184. BIFPLR4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
46185. BIFPLR4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
46186. BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
46187. BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
46188. BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
46189. BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
46190. BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
46191. BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
46192. BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
46193. BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
46194. BIFPLR4_0_MSI_CAP_LIST__CAP_ID_MASK
46195. BIFPLR4_0_MSI_CAP_LIST__CAP_ID__SHIFT
46196. BIFPLR4_0_MSI_CAP_LIST__NEXT_PTR_MASK
46197. BIFPLR4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
46198. BIFPLR4_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
46199. BIFPLR4_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
46200. BIFPLR4_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
46201. BIFPLR4_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
46202. BIFPLR4_0_MSI_MAP_CAP_LIST__CAP_ID_MASK
46203. BIFPLR4_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
46204. BIFPLR4_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
46205. BIFPLR4_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
46206. BIFPLR4_0_MSI_MAP_CAP__CAP_TYPE_MASK
46207. BIFPLR4_0_MSI_MAP_CAP__CAP_TYPE__SHIFT
46208. BIFPLR4_0_MSI_MAP_CAP__EN_MASK
46209. BIFPLR4_0_MSI_MAP_CAP__EN__SHIFT
46210. BIFPLR4_0_MSI_MAP_CAP__FIXD_MASK
46211. BIFPLR4_0_MSI_MAP_CAP__FIXD__SHIFT
46212. BIFPLR4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
46213. BIFPLR4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
46214. BIFPLR4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
46215. BIFPLR4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
46216. BIFPLR4_0_MSI_MSG_CNTL__MSI_64BIT_MASK
46217. BIFPLR4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
46218. BIFPLR4_0_MSI_MSG_CNTL__MSI_EN_MASK
46219. BIFPLR4_0_MSI_MSG_CNTL__MSI_EN__SHIFT
46220. BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
46221. BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
46222. BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
46223. BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
46224. BIFPLR4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
46225. BIFPLR4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
46226. BIFPLR4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
46227. BIFPLR4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
46228. BIFPLR4_0_MSI_MSG_DATA__MSI_DATA_MASK
46229. BIFPLR4_0_MSI_MSG_DATA__MSI_DATA__SHIFT
46230. BIFPLR4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
46231. BIFPLR4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
46232. BIFPLR4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
46233. BIFPLR4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
46234. BIFPLR4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
46235. BIFPLR4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
46236. BIFPLR4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
46237. BIFPLR4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
46238. BIFPLR4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
46239. BIFPLR4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
46240. BIFPLR4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
46241. BIFPLR4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
46242. BIFPLR4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
46243. BIFPLR4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
46244. BIFPLR4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
46245. BIFPLR4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
46246. BIFPLR4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
46247. BIFPLR4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
46248. BIFPLR4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
46249. BIFPLR4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
46250. BIFPLR4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
46251. BIFPLR4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
46252. BIFPLR4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
46253. BIFPLR4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
46254. BIFPLR4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
46255. BIFPLR4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
46256. BIFPLR4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
46257. BIFPLR4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
46258. BIFPLR4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
46259. BIFPLR4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
46260. BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
46261. BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
46262. BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
46263. BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
46264. BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
46265. BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
46266. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
46267. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
46268. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
46269. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
46270. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
46271. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
46272. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
46273. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
46274. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
46275. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
46276. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
46277. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
46278. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
46279. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
46280. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
46281. BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
46282. BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
46283. BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
46284. BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
46285. BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
46286. BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
46287. BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
46288. BIFPLR4_0_PCIE_CAP_LIST__CAP_ID_MASK
46289. BIFPLR4_0_PCIE_CAP_LIST__CAP_ID__SHIFT
46290. BIFPLR4_0_PCIE_CAP_LIST__NEXT_PTR_MASK
46291. BIFPLR4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
46292. BIFPLR4_0_PCIE_CAP__DEVICE_TYPE_MASK
46293. BIFPLR4_0_PCIE_CAP__DEVICE_TYPE__SHIFT
46294. BIFPLR4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
46295. BIFPLR4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
46296. BIFPLR4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
46297. BIFPLR4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
46298. BIFPLR4_0_PCIE_CAP__VERSION_MASK
46299. BIFPLR4_0_PCIE_CAP__VERSION__SHIFT
46300. BIFPLR4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
46301. BIFPLR4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
46302. BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
46303. BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
46304. BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
46305. BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
46306. BIFPLR4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
46307. BIFPLR4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
46308. BIFPLR4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
46309. BIFPLR4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
46310. BIFPLR4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
46311. BIFPLR4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
46312. BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
46313. BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
46314. BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
46315. BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
46316. BIFPLR4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
46317. BIFPLR4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
46318. BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
46319. BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
46320. BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
46321. BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
46322. BIFPLR4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
46323. BIFPLR4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
46324. BIFPLR4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
46325. BIFPLR4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
46326. BIFPLR4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
46327. BIFPLR4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
46328. BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
46329. BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
46330. BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
46331. BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
46332. BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
46333. BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
46334. BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
46335. BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
46336. BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
46337. BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
46338. BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
46339. BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
46340. BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
46341. BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
46342. BIFPLR4_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
46343. BIFPLR4_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
46344. BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
46345. BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
46346. BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
46347. BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
46348. BIFPLR4_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
46349. BIFPLR4_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
46350. BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
46351. BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
46352. BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
46353. BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
46354. BIFPLR4_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
46355. BIFPLR4_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
46356. BIFPLR4_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
46357. BIFPLR4_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
46358. BIFPLR4_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
46359. BIFPLR4_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
46360. BIFPLR4_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
46361. BIFPLR4_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
46362. BIFPLR4_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
46363. BIFPLR4_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
46364. BIFPLR4_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
46365. BIFPLR4_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
46366. BIFPLR4_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
46367. BIFPLR4_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
46368. BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
46369. BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
46370. BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
46371. BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
46372. BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
46373. BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
46374. BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
46375. BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
46376. BIFPLR4_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
46377. BIFPLR4_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
46378. BIFPLR4_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
46379. BIFPLR4_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
46380. BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
46381. BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
46382. BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
46383. BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
46384. BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
46385. BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
46386. BIFPLR4_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
46387. BIFPLR4_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
46388. BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
46389. BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
46390. BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
46391. BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
46392. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK
46393. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
46394. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK
46395. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
46396. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK
46397. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
46398. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK
46399. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
46400. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK
46401. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
46402. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK
46403. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
46404. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK
46405. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
46406. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK
46407. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
46408. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK
46409. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
46410. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK
46411. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
46412. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK
46413. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
46414. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK
46415. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
46416. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK
46417. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
46418. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK
46419. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
46420. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK
46421. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
46422. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK
46423. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
46424. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK
46425. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
46426. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK
46427. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
46428. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK
46429. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
46430. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK
46431. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
46432. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK
46433. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
46434. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK
46435. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
46436. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK
46437. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
46438. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK
46439. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
46440. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK
46441. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
46442. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK
46443. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
46444. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK
46445. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
46446. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK
46447. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
46448. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK
46449. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
46450. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK
46451. BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
46452. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK
46453. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
46454. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK
46455. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
46456. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK
46457. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
46458. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK
46459. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
46460. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK
46461. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
46462. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK
46463. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
46464. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK
46465. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
46466. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK
46467. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
46468. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK
46469. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
46470. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK
46471. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
46472. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK
46473. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
46474. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK
46475. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
46476. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK
46477. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
46478. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK
46479. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
46480. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK
46481. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
46482. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK
46483. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
46484. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK
46485. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
46486. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK
46487. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
46488. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK
46489. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
46490. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK
46491. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
46492. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK
46493. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
46494. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK
46495. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
46496. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK
46497. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
46498. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK
46499. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
46500. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK
46501. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
46502. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK
46503. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
46504. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK
46505. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
46506. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK
46507. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
46508. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK
46509. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
46510. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK
46511. BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
46512. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK
46513. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
46514. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK
46515. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
46516. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK
46517. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
46518. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK
46519. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
46520. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK
46521. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
46522. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK
46523. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
46524. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK
46525. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
46526. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK
46527. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
46528. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK
46529. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
46530. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK
46531. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
46532. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK
46533. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
46534. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK
46535. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
46536. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK
46537. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
46538. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK
46539. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
46540. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK
46541. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
46542. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK
46543. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
46544. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK
46545. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
46546. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK
46547. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
46548. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK
46549. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
46550. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK
46551. BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
46552. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK
46553. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
46554. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK
46555. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
46556. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK
46557. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
46558. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK
46559. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
46560. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK
46561. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
46562. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK
46563. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
46564. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK
46565. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
46566. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK
46567. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
46568. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK
46569. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
46570. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK
46571. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
46572. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK
46573. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
46574. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK
46575. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
46576. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK
46577. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
46578. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK
46579. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
46580. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK
46581. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
46582. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK
46583. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
46584. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK
46585. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
46586. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK
46587. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
46588. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK
46589. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
46590. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK
46591. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
46592. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK
46593. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
46594. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK
46595. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
46596. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK
46597. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
46598. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK
46599. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
46600. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK
46601. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
46602. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK
46603. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
46604. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK
46605. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
46606. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK
46607. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
46608. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK
46609. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
46610. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK
46611. BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
46612. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK
46613. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
46614. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK
46615. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
46616. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK
46617. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
46618. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK
46619. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
46620. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK
46621. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
46622. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK
46623. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
46624. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK
46625. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
46626. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK
46627. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
46628. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK
46629. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
46630. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK
46631. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
46632. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK
46633. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
46634. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK
46635. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
46636. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK
46637. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
46638. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK
46639. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
46640. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK
46641. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
46642. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK
46643. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
46644. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK
46645. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
46646. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK
46647. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
46648. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK
46649. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
46650. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK
46651. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
46652. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK
46653. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
46654. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK
46655. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
46656. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK
46657. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
46658. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK
46659. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
46660. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK
46661. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
46662. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK
46663. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
46664. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK
46665. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
46666. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK
46667. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
46668. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK
46669. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
46670. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK
46671. BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
46672. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK
46673. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
46674. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK
46675. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
46676. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK
46677. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
46678. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK
46679. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
46680. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK
46681. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
46682. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK
46683. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
46684. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK
46685. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
46686. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK
46687. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
46688. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK
46689. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
46690. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK
46691. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
46692. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK
46693. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
46694. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK
46695. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
46696. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK
46697. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
46698. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK
46699. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
46700. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK
46701. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
46702. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK
46703. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
46704. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK
46705. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
46706. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK
46707. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
46708. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK
46709. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
46710. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK
46711. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
46712. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK
46713. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
46714. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK
46715. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
46716. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK
46717. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
46718. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK
46719. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
46720. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK
46721. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
46722. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK
46723. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
46724. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK
46725. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
46726. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK
46727. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
46728. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK
46729. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
46730. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK
46731. BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
46732. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK
46733. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
46734. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK
46735. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
46736. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK
46737. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
46738. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK
46739. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
46740. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK
46741. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
46742. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK
46743. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
46744. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK
46745. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
46746. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK
46747. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
46748. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK
46749. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
46750. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK
46751. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
46752. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK
46753. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
46754. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK
46755. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
46756. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK
46757. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
46758. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK
46759. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
46760. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK
46761. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
46762. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK
46763. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
46764. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK
46765. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
46766. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK
46767. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
46768. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK
46769. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
46770. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK
46771. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
46772. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK
46773. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
46774. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK
46775. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
46776. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK
46777. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
46778. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK
46779. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
46780. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK
46781. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
46782. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK
46783. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
46784. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK
46785. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
46786. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK
46787. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
46788. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK
46789. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
46790. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK
46791. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
46792. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK
46793. BIFPLR4_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
46794. BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK
46795. BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
46796. BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK
46797. BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
46798. BIFPLR4_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
46799. BIFPLR4_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
46800. BIFPLR4_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK
46801. BIFPLR4_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
46802. BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
46803. BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
46804. BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
46805. BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
46806. BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
46807. BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
46808. BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
46809. BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
46810. BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
46811. BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
46812. BIFPLR4_0_PCIE_ESM_HEADER_2__CAP_ID_MASK
46813. BIFPLR4_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
46814. BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
46815. BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
46816. BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
46817. BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
46818. BIFPLR4_0_PCIE_HDR_LOG0__TLP_HDR_MASK
46819. BIFPLR4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
46820. BIFPLR4_0_PCIE_HDR_LOG1__TLP_HDR_MASK
46821. BIFPLR4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
46822. BIFPLR4_0_PCIE_HDR_LOG2__TLP_HDR_MASK
46823. BIFPLR4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
46824. BIFPLR4_0_PCIE_HDR_LOG3__TLP_HDR_MASK
46825. BIFPLR4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
46826. BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
46827. BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
46828. BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
46829. BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
46830. BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
46831. BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
46832. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
46833. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
46834. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
46835. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
46836. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
46837. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
46838. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
46839. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
46840. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
46841. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
46842. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
46843. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
46844. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
46845. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
46846. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
46847. BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
46848. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
46849. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
46850. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
46851. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
46852. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
46853. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
46854. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
46855. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
46856. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
46857. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
46858. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
46859. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
46860. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
46861. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
46862. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
46863. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
46864. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
46865. BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
46866. BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46867. BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46868. BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46869. BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46870. BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46871. BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46872. BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46873. BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46874. BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46875. BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46876. BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46877. BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46878. BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46879. BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46880. BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46881. BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46882. BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46883. BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46884. BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46885. BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46886. BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46887. BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46888. BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46889. BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46890. BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46891. BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46892. BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46893. BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46894. BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46895. BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46896. BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46897. BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46898. BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46899. BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46900. BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46901. BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46902. BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46903. BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46904. BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46905. BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46906. BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46907. BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46908. BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46909. BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46910. BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46911. BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46912. BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46913. BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46914. BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46915. BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46916. BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46917. BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46918. BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46919. BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46920. BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46921. BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46922. BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46923. BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46924. BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46925. BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46926. BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46927. BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46928. BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46929. BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46930. BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46931. BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46932. BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46933. BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46934. BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46935. BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46936. BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46937. BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46938. BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46939. BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46940. BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46941. BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46942. BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46943. BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46944. BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46945. BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46946. BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46947. BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46948. BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46949. BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46950. BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46951. BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46952. BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46953. BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46954. BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46955. BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46956. BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46957. BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46958. BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46959. BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46960. BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46961. BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46962. BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46963. BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46964. BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46965. BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46966. BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46967. BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46968. BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46969. BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46970. BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46971. BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46972. BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46973. BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46974. BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46975. BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46976. BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46977. BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46978. BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46979. BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46980. BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46981. BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46982. BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46983. BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46984. BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46985. BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46986. BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
46987. BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
46988. BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
46989. BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
46990. BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
46991. BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
46992. BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
46993. BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
46994. BIFPLR4_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
46995. BIFPLR4_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
46996. BIFPLR4_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
46997. BIFPLR4_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
46998. BIFPLR4_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
46999. BIFPLR4_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
47000. BIFPLR4_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
47001. BIFPLR4_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
47002. BIFPLR4_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
47003. BIFPLR4_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
47004. BIFPLR4_0_PCIE_LINK_CNTL3__RESERVED_MASK
47005. BIFPLR4_0_PCIE_LINK_CNTL3__RESERVED__SHIFT
47006. BIFPLR4_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
47007. BIFPLR4_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
47008. BIFPLR4_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
47009. BIFPLR4_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
47010. BIFPLR4_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
47011. BIFPLR4_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
47012. BIFPLR4_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
47013. BIFPLR4_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
47014. BIFPLR4_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
47015. BIFPLR4_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
47016. BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
47017. BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
47018. BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
47019. BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
47020. BIFPLR4_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
47021. BIFPLR4_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
47022. BIFPLR4_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK
47023. BIFPLR4_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
47024. BIFPLR4_0_PCIE_MC_CNTL__MC_ENABLE_MASK
47025. BIFPLR4_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT
47026. BIFPLR4_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
47027. BIFPLR4_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
47028. BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
47029. BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
47030. BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
47031. BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
47032. BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
47033. BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
47034. BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
47035. BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
47036. BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
47037. BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
47038. BIFPLR4_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
47039. BIFPLR4_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
47040. BIFPLR4_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
47041. BIFPLR4_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
47042. BIFPLR4_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
47043. BIFPLR4_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
47044. BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
47045. BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
47046. BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
47047. BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
47048. BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
47049. BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
47050. BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
47051. BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
47052. BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
47053. BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
47054. BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
47055. BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
47056. BIFPLR4_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
47057. BIFPLR4_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
47058. BIFPLR4_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
47059. BIFPLR4_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
47060. BIFPLR4_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
47061. BIFPLR4_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
47062. BIFPLR4_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
47063. BIFPLR4_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
47064. BIFPLR4_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
47065. BIFPLR4_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
47066. BIFPLR4_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
47067. BIFPLR4_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
47068. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
47069. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
47070. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
47071. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
47072. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
47073. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
47074. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
47075. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
47076. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
47077. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
47078. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
47079. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
47080. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
47081. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
47082. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
47083. BIFPLR4_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
47084. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
47085. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
47086. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
47087. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
47088. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
47089. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
47090. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
47091. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
47092. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
47093. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
47094. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
47095. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
47096. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
47097. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
47098. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
47099. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
47100. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
47101. BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
47102. BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
47103. BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
47104. BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
47105. BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
47106. BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
47107. BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
47108. BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
47109. BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
47110. BIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
47111. BIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
47112. BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
47113. BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
47114. BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK
47115. BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
47116. BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
47117. BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
47118. BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
47119. BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
47120. BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CTO_MASK
47121. BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
47122. BIFPLR4_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
47123. BIFPLR4_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
47124. BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
47125. BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
47126. BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK
47127. BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
47128. BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
47129. BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
47130. BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
47131. BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
47132. BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
47133. BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
47134. BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
47135. BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
47136. BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
47137. BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
47138. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
47139. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
47140. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
47141. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
47142. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
47143. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
47144. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
47145. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
47146. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
47147. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
47148. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
47149. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
47150. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
47151. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
47152. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
47153. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
47154. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
47155. BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
47156. BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
47157. BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
47158. BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
47159. BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
47160. BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
47161. BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
47162. BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
47163. BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
47164. BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK
47165. BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
47166. BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
47167. BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
47168. BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
47169. BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
47170. BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
47171. BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
47172. BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
47173. BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
47174. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
47175. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
47176. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
47177. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
47178. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
47179. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
47180. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
47181. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
47182. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
47183. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
47184. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
47185. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
47186. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
47187. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
47188. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
47189. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
47190. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
47191. BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
47192. BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
47193. BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
47194. BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
47195. BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
47196. BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
47197. BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
47198. BIFPLR4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
47199. BIFPLR4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
47200. BIFPLR4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
47201. BIFPLR4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
47202. BIFPLR4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
47203. BIFPLR4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
47204. BIFPLR4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
47205. BIFPLR4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
47206. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
47207. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
47208. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
47209. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
47210. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
47211. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
47212. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
47213. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
47214. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
47215. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
47216. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
47217. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
47218. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
47219. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
47220. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
47221. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
47222. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
47223. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
47224. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
47225. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
47226. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
47227. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
47228. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
47229. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
47230. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
47231. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
47232. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
47233. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
47234. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
47235. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
47236. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
47237. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
47238. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
47239. BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
47240. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
47241. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
47242. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
47243. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
47244. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
47245. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
47246. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
47247. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
47248. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
47249. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
47250. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
47251. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
47252. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
47253. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
47254. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
47255. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
47256. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
47257. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
47258. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
47259. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
47260. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
47261. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
47262. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
47263. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
47264. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
47265. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
47266. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
47267. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
47268. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
47269. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
47270. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
47271. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
47272. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
47273. BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
47274. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
47275. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
47276. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
47277. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
47278. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
47279. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
47280. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
47281. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
47282. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
47283. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
47284. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
47285. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
47286. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
47287. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
47288. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
47289. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
47290. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
47291. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
47292. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
47293. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
47294. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
47295. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
47296. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
47297. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
47298. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
47299. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
47300. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
47301. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
47302. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
47303. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
47304. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
47305. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
47306. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
47307. BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
47308. BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
47309. BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
47310. BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
47311. BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
47312. BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
47313. BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
47314. BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
47315. BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
47316. BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
47317. BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
47318. BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
47319. BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
47320. BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
47321. BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
47322. BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
47323. BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
47324. BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
47325. BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
47326. BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
47327. BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
47328. BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
47329. BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
47330. BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
47331. BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
47332. BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
47333. BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
47334. BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
47335. BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
47336. BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
47337. BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
47338. BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
47339. BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
47340. BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
47341. BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
47342. BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
47343. BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
47344. BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
47345. BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
47346. BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
47347. BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
47348. BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
47349. BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
47350. BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
47351. BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
47352. BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
47353. BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
47354. BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
47355. BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
47356. BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
47357. BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
47358. BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
47359. BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
47360. BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
47361. BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
47362. BIFPLR4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
47363. BIFPLR4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
47364. BIFPLR4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
47365. BIFPLR4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
47366. BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
47367. BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
47368. BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
47369. BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
47370. BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
47371. BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
47372. BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
47373. BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
47374. BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
47375. BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
47376. BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
47377. BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
47378. BIFPLR4_0_PMI_CAP_LIST__CAP_ID_MASK
47379. BIFPLR4_0_PMI_CAP_LIST__CAP_ID__SHIFT
47380. BIFPLR4_0_PMI_CAP_LIST__NEXT_PTR_MASK
47381. BIFPLR4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
47382. BIFPLR4_0_PMI_CAP__AUX_CURRENT_MASK
47383. BIFPLR4_0_PMI_CAP__AUX_CURRENT__SHIFT
47384. BIFPLR4_0_PMI_CAP__D1_SUPPORT_MASK
47385. BIFPLR4_0_PMI_CAP__D1_SUPPORT__SHIFT
47386. BIFPLR4_0_PMI_CAP__D2_SUPPORT_MASK
47387. BIFPLR4_0_PMI_CAP__D2_SUPPORT__SHIFT
47388. BIFPLR4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
47389. BIFPLR4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
47390. BIFPLR4_0_PMI_CAP__PME_CLOCK_MASK
47391. BIFPLR4_0_PMI_CAP__PME_CLOCK__SHIFT
47392. BIFPLR4_0_PMI_CAP__PME_SUPPORT_MASK
47393. BIFPLR4_0_PMI_CAP__PME_SUPPORT__SHIFT
47394. BIFPLR4_0_PMI_CAP__VERSION_MASK
47395. BIFPLR4_0_PMI_CAP__VERSION__SHIFT
47396. BIFPLR4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
47397. BIFPLR4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
47398. BIFPLR4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
47399. BIFPLR4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
47400. BIFPLR4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
47401. BIFPLR4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
47402. BIFPLR4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
47403. BIFPLR4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
47404. BIFPLR4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
47405. BIFPLR4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
47406. BIFPLR4_0_PMI_STATUS_CNTL__PME_EN_MASK
47407. BIFPLR4_0_PMI_STATUS_CNTL__PME_EN__SHIFT
47408. BIFPLR4_0_PMI_STATUS_CNTL__PME_STATUS_MASK
47409. BIFPLR4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
47410. BIFPLR4_0_PMI_STATUS_CNTL__PMI_DATA_MASK
47411. BIFPLR4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
47412. BIFPLR4_0_PMI_STATUS_CNTL__POWER_STATE_MASK
47413. BIFPLR4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
47414. BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
47415. BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
47416. BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
47417. BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
47418. BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
47419. BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
47420. BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
47421. BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
47422. BIFPLR4_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
47423. BIFPLR4_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
47424. BIFPLR4_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
47425. BIFPLR4_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
47426. BIFPLR4_0_PROG_INTERFACE__PROG_INTERFACE_MASK
47427. BIFPLR4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
47428. BIFPLR4_0_REVISION_ID__MAJOR_REV_ID_MASK
47429. BIFPLR4_0_REVISION_ID__MAJOR_REV_ID__SHIFT
47430. BIFPLR4_0_REVISION_ID__MINOR_REV_ID_MASK
47431. BIFPLR4_0_REVISION_ID__MINOR_REV_ID__SHIFT
47432. BIFPLR4_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
47433. BIFPLR4_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
47434. BIFPLR4_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
47435. BIFPLR4_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
47436. BIFPLR4_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK
47437. BIFPLR4_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
47438. BIFPLR4_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
47439. BIFPLR4_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
47440. BIFPLR4_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
47441. BIFPLR4_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
47442. BIFPLR4_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
47443. BIFPLR4_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
47444. BIFPLR4_0_ROOT_STATUS__PME_PENDING_MASK
47445. BIFPLR4_0_ROOT_STATUS__PME_PENDING__SHIFT
47446. BIFPLR4_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK
47447. BIFPLR4_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
47448. BIFPLR4_0_ROOT_STATUS__PME_STATUS_MASK
47449. BIFPLR4_0_ROOT_STATUS__PME_STATUS__SHIFT
47450. BIFPLR4_0_SECONDARY_STATUS__CAP_LIST_MASK
47451. BIFPLR4_0_SECONDARY_STATUS__CAP_LIST__SHIFT
47452. BIFPLR4_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK
47453. BIFPLR4_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
47454. BIFPLR4_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
47455. BIFPLR4_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
47456. BIFPLR4_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
47457. BIFPLR4_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
47458. BIFPLR4_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
47459. BIFPLR4_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
47460. BIFPLR4_0_SECONDARY_STATUS__PCI_66_EN_MASK
47461. BIFPLR4_0_SECONDARY_STATUS__PCI_66_EN__SHIFT
47462. BIFPLR4_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
47463. BIFPLR4_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
47464. BIFPLR4_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
47465. BIFPLR4_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
47466. BIFPLR4_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
47467. BIFPLR4_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
47468. BIFPLR4_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
47469. BIFPLR4_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
47470. BIFPLR4_0_SLOT_CAP2__RESERVED_MASK
47471. BIFPLR4_0_SLOT_CAP2__RESERVED__SHIFT
47472. BIFPLR4_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
47473. BIFPLR4_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
47474. BIFPLR4_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
47475. BIFPLR4_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
47476. BIFPLR4_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
47477. BIFPLR4_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
47478. BIFPLR4_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK
47479. BIFPLR4_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
47480. BIFPLR4_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK
47481. BIFPLR4_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
47482. BIFPLR4_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
47483. BIFPLR4_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
47484. BIFPLR4_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
47485. BIFPLR4_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
47486. BIFPLR4_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
47487. BIFPLR4_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
47488. BIFPLR4_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
47489. BIFPLR4_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
47490. BIFPLR4_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
47491. BIFPLR4_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
47492. BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
47493. BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
47494. BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
47495. BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
47496. BIFPLR4_0_SLOT_CNTL2__RESERVED_MASK
47497. BIFPLR4_0_SLOT_CNTL2__RESERVED__SHIFT
47498. BIFPLR4_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
47499. BIFPLR4_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
47500. BIFPLR4_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
47501. BIFPLR4_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
47502. BIFPLR4_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
47503. BIFPLR4_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
47504. BIFPLR4_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
47505. BIFPLR4_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
47506. BIFPLR4_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
47507. BIFPLR4_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
47508. BIFPLR4_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
47509. BIFPLR4_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
47510. BIFPLR4_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
47511. BIFPLR4_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
47512. BIFPLR4_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
47513. BIFPLR4_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
47514. BIFPLR4_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
47515. BIFPLR4_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
47516. BIFPLR4_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
47517. BIFPLR4_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
47518. BIFPLR4_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
47519. BIFPLR4_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
47520. BIFPLR4_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
47521. BIFPLR4_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
47522. BIFPLR4_0_SLOT_STATUS2__RESERVED_MASK
47523. BIFPLR4_0_SLOT_STATUS2__RESERVED__SHIFT
47524. BIFPLR4_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
47525. BIFPLR4_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
47526. BIFPLR4_0_SLOT_STATUS__COMMAND_COMPLETED_MASK
47527. BIFPLR4_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
47528. BIFPLR4_0_SLOT_STATUS__DL_STATE_CHANGED_MASK
47529. BIFPLR4_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
47530. BIFPLR4_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
47531. BIFPLR4_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
47532. BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
47533. BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
47534. BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK
47535. BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
47536. BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
47537. BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
47538. BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
47539. BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
47540. BIFPLR4_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
47541. BIFPLR4_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
47542. BIFPLR4_0_SSID_CAP_LIST__CAP_ID_MASK
47543. BIFPLR4_0_SSID_CAP_LIST__CAP_ID__SHIFT
47544. BIFPLR4_0_SSID_CAP_LIST__NEXT_PTR_MASK
47545. BIFPLR4_0_SSID_CAP_LIST__NEXT_PTR__SHIFT
47546. BIFPLR4_0_SSID_CAP__SUBSYSTEM_ID_MASK
47547. BIFPLR4_0_SSID_CAP__SUBSYSTEM_ID__SHIFT
47548. BIFPLR4_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
47549. BIFPLR4_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
47550. BIFPLR4_0_STATUS__CAP_LIST_MASK
47551. BIFPLR4_0_STATUS__CAP_LIST__SHIFT
47552. BIFPLR4_0_STATUS__DEVSEL_TIMING_MASK
47553. BIFPLR4_0_STATUS__DEVSEL_TIMING__SHIFT
47554. BIFPLR4_0_STATUS__FAST_BACK_CAPABLE_MASK
47555. BIFPLR4_0_STATUS__FAST_BACK_CAPABLE__SHIFT
47556. BIFPLR4_0_STATUS__INT_STATUS_MASK
47557. BIFPLR4_0_STATUS__INT_STATUS__SHIFT
47558. BIFPLR4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
47559. BIFPLR4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
47560. BIFPLR4_0_STATUS__PARITY_ERROR_DETECTED_MASK
47561. BIFPLR4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
47562. BIFPLR4_0_STATUS__PCI_66_EN_MASK
47563. BIFPLR4_0_STATUS__PCI_66_EN__SHIFT
47564. BIFPLR4_0_STATUS__RECEIVED_MASTER_ABORT_MASK
47565. BIFPLR4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
47566. BIFPLR4_0_STATUS__RECEIVED_TARGET_ABORT_MASK
47567. BIFPLR4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
47568. BIFPLR4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
47569. BIFPLR4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
47570. BIFPLR4_0_STATUS__SIGNAL_TARGET_ABORT_MASK
47571. BIFPLR4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
47572. BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
47573. BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
47574. BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
47575. BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
47576. BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
47577. BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
47578. BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
47579. BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
47580. BIFPLR4_0_SUB_CLASS__SUB_CLASS_MASK
47581. BIFPLR4_0_SUB_CLASS__SUB_CLASS__SHIFT
47582. BIFPLR4_0_VENDOR_ID__VENDOR_ID_MASK
47583. BIFPLR4_0_VENDOR_ID__VENDOR_ID__SHIFT
47584. BIFPLR4_1_BASE_CLASS__BASE_CLASS_MASK
47585. BIFPLR4_1_BASE_CLASS__BASE_CLASS__SHIFT
47586. BIFPLR4_1_BIST__BIST_CAP_MASK
47587. BIFPLR4_1_BIST__BIST_CAP__SHIFT
47588. BIFPLR4_1_BIST__BIST_COMP_MASK
47589. BIFPLR4_1_BIST__BIST_COMP__SHIFT
47590. BIFPLR4_1_BIST__BIST_STRT_MASK
47591. BIFPLR4_1_BIST__BIST_STRT__SHIFT
47592. BIFPLR4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
47593. BIFPLR4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
47594. BIFPLR4_1_CAP_PTR__CAP_PTR_MASK
47595. BIFPLR4_1_CAP_PTR__CAP_PTR__SHIFT
47596. BIFPLR4_1_COMMAND__AD_STEPPING_MASK
47597. BIFPLR4_1_COMMAND__AD_STEPPING__SHIFT
47598. BIFPLR4_1_COMMAND__BUS_MASTER_EN_MASK
47599. BIFPLR4_1_COMMAND__BUS_MASTER_EN__SHIFT
47600. BIFPLR4_1_COMMAND__FAST_B2B_EN_MASK
47601. BIFPLR4_1_COMMAND__FAST_B2B_EN__SHIFT
47602. BIFPLR4_1_COMMAND__INT_DIS_MASK
47603. BIFPLR4_1_COMMAND__INT_DIS__SHIFT
47604. BIFPLR4_1_COMMAND__IO_ACCESS_EN_MASK
47605. BIFPLR4_1_COMMAND__IO_ACCESS_EN__SHIFT
47606. BIFPLR4_1_COMMAND__MEM_ACCESS_EN_MASK
47607. BIFPLR4_1_COMMAND__MEM_ACCESS_EN__SHIFT
47608. BIFPLR4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
47609. BIFPLR4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
47610. BIFPLR4_1_COMMAND__PAL_SNOOP_EN_MASK
47611. BIFPLR4_1_COMMAND__PAL_SNOOP_EN__SHIFT
47612. BIFPLR4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
47613. BIFPLR4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
47614. BIFPLR4_1_COMMAND__SERR_EN_MASK
47615. BIFPLR4_1_COMMAND__SERR_EN__SHIFT
47616. BIFPLR4_1_COMMAND__SPECIAL_CYCLE_EN_MASK
47617. BIFPLR4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
47618. BIFPLR4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
47619. BIFPLR4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
47620. BIFPLR4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
47621. BIFPLR4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
47622. BIFPLR4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
47623. BIFPLR4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
47624. BIFPLR4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
47625. BIFPLR4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
47626. BIFPLR4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
47627. BIFPLR4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
47628. BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
47629. BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
47630. BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
47631. BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
47632. BIFPLR4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
47633. BIFPLR4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
47634. BIFPLR4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
47635. BIFPLR4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
47636. BIFPLR4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
47637. BIFPLR4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
47638. BIFPLR4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
47639. BIFPLR4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
47640. BIFPLR4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
47641. BIFPLR4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
47642. BIFPLR4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
47643. BIFPLR4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
47644. BIFPLR4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
47645. BIFPLR4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
47646. BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
47647. BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
47648. BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
47649. BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
47650. BIFPLR4_1_DEVICE_CAP__EXTENDED_TAG_MASK
47651. BIFPLR4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
47652. BIFPLR4_1_DEVICE_CAP__FLR_CAPABLE_MASK
47653. BIFPLR4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
47654. BIFPLR4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
47655. BIFPLR4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
47656. BIFPLR4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
47657. BIFPLR4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
47658. BIFPLR4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
47659. BIFPLR4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
47660. BIFPLR4_1_DEVICE_CAP__PHANTOM_FUNC_MASK
47661. BIFPLR4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
47662. BIFPLR4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
47663. BIFPLR4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
47664. BIFPLR4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
47665. BIFPLR4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
47666. BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
47667. BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
47668. BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
47669. BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
47670. BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
47671. BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
47672. BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
47673. BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
47674. BIFPLR4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
47675. BIFPLR4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
47676. BIFPLR4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
47677. BIFPLR4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
47678. BIFPLR4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
47679. BIFPLR4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
47680. BIFPLR4_1_DEVICE_CNTL2__LTR_EN_MASK
47681. BIFPLR4_1_DEVICE_CNTL2__LTR_EN__SHIFT
47682. BIFPLR4_1_DEVICE_CNTL2__OBFF_EN_MASK
47683. BIFPLR4_1_DEVICE_CNTL2__OBFF_EN__SHIFT
47684. BIFPLR4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
47685. BIFPLR4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
47686. BIFPLR4_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
47687. BIFPLR4_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
47688. BIFPLR4_1_DEVICE_CNTL__CORR_ERR_EN_MASK
47689. BIFPLR4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
47690. BIFPLR4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
47691. BIFPLR4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
47692. BIFPLR4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
47693. BIFPLR4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
47694. BIFPLR4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
47695. BIFPLR4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
47696. BIFPLR4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
47697. BIFPLR4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
47698. BIFPLR4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
47699. BIFPLR4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
47700. BIFPLR4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
47701. BIFPLR4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
47702. BIFPLR4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
47703. BIFPLR4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
47704. BIFPLR4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
47705. BIFPLR4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
47706. BIFPLR4_1_DEVICE_CNTL__USR_REPORT_EN_MASK
47707. BIFPLR4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
47708. BIFPLR4_1_DEVICE_ID__DEVICE_ID_MASK
47709. BIFPLR4_1_DEVICE_ID__DEVICE_ID__SHIFT
47710. BIFPLR4_1_DEVICE_STATUS2__RESERVED_MASK
47711. BIFPLR4_1_DEVICE_STATUS2__RESERVED__SHIFT
47712. BIFPLR4_1_DEVICE_STATUS__AUX_PWR_MASK
47713. BIFPLR4_1_DEVICE_STATUS__AUX_PWR__SHIFT
47714. BIFPLR4_1_DEVICE_STATUS__CORR_ERR_MASK
47715. BIFPLR4_1_DEVICE_STATUS__CORR_ERR__SHIFT
47716. BIFPLR4_1_DEVICE_STATUS__FATAL_ERR_MASK
47717. BIFPLR4_1_DEVICE_STATUS__FATAL_ERR__SHIFT
47718. BIFPLR4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
47719. BIFPLR4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
47720. BIFPLR4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
47721. BIFPLR4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
47722. BIFPLR4_1_DEVICE_STATUS__USR_DETECTED_MASK
47723. BIFPLR4_1_DEVICE_STATUS__USR_DETECTED__SHIFT
47724. BIFPLR4_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
47725. BIFPLR4_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
47726. BIFPLR4_1_HEADER__DEVICE_TYPE_MASK
47727. BIFPLR4_1_HEADER__DEVICE_TYPE__SHIFT
47728. BIFPLR4_1_HEADER__HEADER_TYPE_MASK
47729. BIFPLR4_1_HEADER__HEADER_TYPE__SHIFT
47730. BIFPLR4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
47731. BIFPLR4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
47732. BIFPLR4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
47733. BIFPLR4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
47734. BIFPLR4_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
47735. BIFPLR4_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
47736. BIFPLR4_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
47737. BIFPLR4_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
47738. BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_MASK
47739. BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
47740. BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
47741. BIFPLR4_1_IO_BASE_LIMIT__IO_BASE__SHIFT
47742. BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_MASK
47743. BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
47744. BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
47745. BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT
47746. BIFPLR4_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
47747. BIFPLR4_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
47748. BIFPLR4_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK
47749. BIFPLR4_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
47750. BIFPLR4_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
47751. BIFPLR4_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
47752. BIFPLR4_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
47753. BIFPLR4_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
47754. BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
47755. BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
47756. BIFPLR4_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK
47757. BIFPLR4_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
47758. BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
47759. BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
47760. BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK
47761. BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
47762. BIFPLR4_1_LATENCY__LATENCY_TIMER_MASK
47763. BIFPLR4_1_LATENCY__LATENCY_TIMER__SHIFT
47764. BIFPLR4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
47765. BIFPLR4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
47766. BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
47767. BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
47768. BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
47769. BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
47770. BIFPLR4_1_LINK_CAP2__RESERVED_MASK
47771. BIFPLR4_1_LINK_CAP2__RESERVED__SHIFT
47772. BIFPLR4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
47773. BIFPLR4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
47774. BIFPLR4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
47775. BIFPLR4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
47776. BIFPLR4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
47777. BIFPLR4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
47778. BIFPLR4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
47779. BIFPLR4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
47780. BIFPLR4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
47781. BIFPLR4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
47782. BIFPLR4_1_LINK_CAP__L1_EXIT_LATENCY_MASK
47783. BIFPLR4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
47784. BIFPLR4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
47785. BIFPLR4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
47786. BIFPLR4_1_LINK_CAP__LINK_SPEED_MASK
47787. BIFPLR4_1_LINK_CAP__LINK_SPEED__SHIFT
47788. BIFPLR4_1_LINK_CAP__LINK_WIDTH_MASK
47789. BIFPLR4_1_LINK_CAP__LINK_WIDTH__SHIFT
47790. BIFPLR4_1_LINK_CAP__PM_SUPPORT_MASK
47791. BIFPLR4_1_LINK_CAP__PM_SUPPORT__SHIFT
47792. BIFPLR4_1_LINK_CAP__PORT_NUMBER_MASK
47793. BIFPLR4_1_LINK_CAP__PORT_NUMBER__SHIFT
47794. BIFPLR4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
47795. BIFPLR4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
47796. BIFPLR4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
47797. BIFPLR4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
47798. BIFPLR4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
47799. BIFPLR4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
47800. BIFPLR4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
47801. BIFPLR4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
47802. BIFPLR4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
47803. BIFPLR4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
47804. BIFPLR4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
47805. BIFPLR4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
47806. BIFPLR4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
47807. BIFPLR4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
47808. BIFPLR4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
47809. BIFPLR4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
47810. BIFPLR4_1_LINK_CNTL2__XMIT_MARGIN_MASK
47811. BIFPLR4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
47812. BIFPLR4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
47813. BIFPLR4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
47814. BIFPLR4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
47815. BIFPLR4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
47816. BIFPLR4_1_LINK_CNTL__EXTENDED_SYNC_MASK
47817. BIFPLR4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
47818. BIFPLR4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
47819. BIFPLR4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
47820. BIFPLR4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
47821. BIFPLR4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
47822. BIFPLR4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
47823. BIFPLR4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
47824. BIFPLR4_1_LINK_CNTL__LINK_DIS_MASK
47825. BIFPLR4_1_LINK_CNTL__LINK_DIS__SHIFT
47826. BIFPLR4_1_LINK_CNTL__PM_CONTROL_MASK
47827. BIFPLR4_1_LINK_CNTL__PM_CONTROL__SHIFT
47828. BIFPLR4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
47829. BIFPLR4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
47830. BIFPLR4_1_LINK_CNTL__RETRAIN_LINK_MASK
47831. BIFPLR4_1_LINK_CNTL__RETRAIN_LINK__SHIFT
47832. BIFPLR4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
47833. BIFPLR4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
47834. BIFPLR4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
47835. BIFPLR4_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
47836. BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
47837. BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
47838. BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
47839. BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
47840. BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
47841. BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
47842. BIFPLR4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
47843. BIFPLR4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
47844. BIFPLR4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
47845. BIFPLR4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
47846. BIFPLR4_1_LINK_STATUS__DL_ACTIVE_MASK
47847. BIFPLR4_1_LINK_STATUS__DL_ACTIVE__SHIFT
47848. BIFPLR4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
47849. BIFPLR4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
47850. BIFPLR4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
47851. BIFPLR4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
47852. BIFPLR4_1_LINK_STATUS__LINK_TRAINING_MASK
47853. BIFPLR4_1_LINK_STATUS__LINK_TRAINING__SHIFT
47854. BIFPLR4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
47855. BIFPLR4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
47856. BIFPLR4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
47857. BIFPLR4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
47858. BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
47859. BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
47860. BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
47861. BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
47862. BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
47863. BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
47864. BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
47865. BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
47866. BIFPLR4_1_MSI_CAP_LIST__CAP_ID_MASK
47867. BIFPLR4_1_MSI_CAP_LIST__CAP_ID__SHIFT
47868. BIFPLR4_1_MSI_CAP_LIST__NEXT_PTR_MASK
47869. BIFPLR4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
47870. BIFPLR4_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
47871. BIFPLR4_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
47872. BIFPLR4_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
47873. BIFPLR4_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
47874. BIFPLR4_1_MSI_MAP_CAP_LIST__CAP_ID_MASK
47875. BIFPLR4_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
47876. BIFPLR4_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
47877. BIFPLR4_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
47878. BIFPLR4_1_MSI_MAP_CAP__CAP_TYPE_MASK
47879. BIFPLR4_1_MSI_MAP_CAP__CAP_TYPE__SHIFT
47880. BIFPLR4_1_MSI_MAP_CAP__EN_MASK
47881. BIFPLR4_1_MSI_MAP_CAP__EN__SHIFT
47882. BIFPLR4_1_MSI_MAP_CAP__FIXD_MASK
47883. BIFPLR4_1_MSI_MAP_CAP__FIXD__SHIFT
47884. BIFPLR4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
47885. BIFPLR4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
47886. BIFPLR4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
47887. BIFPLR4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
47888. BIFPLR4_1_MSI_MSG_CNTL__MSI_64BIT_MASK
47889. BIFPLR4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
47890. BIFPLR4_1_MSI_MSG_CNTL__MSI_EN_MASK
47891. BIFPLR4_1_MSI_MSG_CNTL__MSI_EN__SHIFT
47892. BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
47893. BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
47894. BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
47895. BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
47896. BIFPLR4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
47897. BIFPLR4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
47898. BIFPLR4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
47899. BIFPLR4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
47900. BIFPLR4_1_MSI_MSG_DATA__MSI_DATA_MASK
47901. BIFPLR4_1_MSI_MSG_DATA__MSI_DATA__SHIFT
47902. BIFPLR4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
47903. BIFPLR4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
47904. BIFPLR4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
47905. BIFPLR4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
47906. BIFPLR4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
47907. BIFPLR4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
47908. BIFPLR4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
47909. BIFPLR4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
47910. BIFPLR4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
47911. BIFPLR4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
47912. BIFPLR4_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
47913. BIFPLR4_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
47914. BIFPLR4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
47915. BIFPLR4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
47916. BIFPLR4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
47917. BIFPLR4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
47918. BIFPLR4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
47919. BIFPLR4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
47920. BIFPLR4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
47921. BIFPLR4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
47922. BIFPLR4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
47923. BIFPLR4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
47924. BIFPLR4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
47925. BIFPLR4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
47926. BIFPLR4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
47927. BIFPLR4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
47928. BIFPLR4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
47929. BIFPLR4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
47930. BIFPLR4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
47931. BIFPLR4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
47932. BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
47933. BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
47934. BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
47935. BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
47936. BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
47937. BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
47938. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
47939. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
47940. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
47941. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
47942. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
47943. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
47944. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
47945. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
47946. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
47947. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
47948. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
47949. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
47950. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
47951. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
47952. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
47953. BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
47954. BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
47955. BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
47956. BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
47957. BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
47958. BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
47959. BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
47960. BIFPLR4_1_PCIE_CAP_LIST__CAP_ID_MASK
47961. BIFPLR4_1_PCIE_CAP_LIST__CAP_ID__SHIFT
47962. BIFPLR4_1_PCIE_CAP_LIST__NEXT_PTR_MASK
47963. BIFPLR4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
47964. BIFPLR4_1_PCIE_CAP__DEVICE_TYPE_MASK
47965. BIFPLR4_1_PCIE_CAP__DEVICE_TYPE__SHIFT
47966. BIFPLR4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
47967. BIFPLR4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
47968. BIFPLR4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
47969. BIFPLR4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
47970. BIFPLR4_1_PCIE_CAP__VERSION_MASK
47971. BIFPLR4_1_PCIE_CAP__VERSION__SHIFT
47972. BIFPLR4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
47973. BIFPLR4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
47974. BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
47975. BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
47976. BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
47977. BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
47978. BIFPLR4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
47979. BIFPLR4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
47980. BIFPLR4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
47981. BIFPLR4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
47982. BIFPLR4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
47983. BIFPLR4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
47984. BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
47985. BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
47986. BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
47987. BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
47988. BIFPLR4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
47989. BIFPLR4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
47990. BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
47991. BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
47992. BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
47993. BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
47994. BIFPLR4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
47995. BIFPLR4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
47996. BIFPLR4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
47997. BIFPLR4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
47998. BIFPLR4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
47999. BIFPLR4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
48000. BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
48001. BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
48002. BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
48003. BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
48004. BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
48005. BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
48006. BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
48007. BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
48008. BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
48009. BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
48010. BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
48011. BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
48012. BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
48013. BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
48014. BIFPLR4_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
48015. BIFPLR4_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
48016. BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
48017. BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
48018. BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
48019. BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
48020. BIFPLR4_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
48021. BIFPLR4_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
48022. BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
48023. BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
48024. BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
48025. BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
48026. BIFPLR4_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
48027. BIFPLR4_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
48028. BIFPLR4_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
48029. BIFPLR4_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
48030. BIFPLR4_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
48031. BIFPLR4_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
48032. BIFPLR4_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
48033. BIFPLR4_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
48034. BIFPLR4_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
48035. BIFPLR4_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
48036. BIFPLR4_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
48037. BIFPLR4_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
48038. BIFPLR4_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
48039. BIFPLR4_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
48040. BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
48041. BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
48042. BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
48043. BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
48044. BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
48045. BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
48046. BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
48047. BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
48048. BIFPLR4_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
48049. BIFPLR4_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
48050. BIFPLR4_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
48051. BIFPLR4_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
48052. BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
48053. BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
48054. BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
48055. BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
48056. BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
48057. BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
48058. BIFPLR4_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
48059. BIFPLR4_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
48060. BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
48061. BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
48062. BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
48063. BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
48064. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK
48065. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
48066. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK
48067. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
48068. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK
48069. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
48070. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK
48071. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
48072. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK
48073. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
48074. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK
48075. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
48076. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK
48077. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
48078. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK
48079. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
48080. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK
48081. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
48082. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK
48083. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
48084. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK
48085. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
48086. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK
48087. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
48088. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK
48089. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
48090. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK
48091. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
48092. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK
48093. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
48094. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK
48095. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
48096. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK
48097. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
48098. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK
48099. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
48100. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK
48101. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
48102. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK
48103. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
48104. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK
48105. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
48106. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK
48107. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
48108. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK
48109. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
48110. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK
48111. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
48112. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK
48113. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
48114. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK
48115. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
48116. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK
48117. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
48118. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK
48119. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
48120. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK
48121. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
48122. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK
48123. BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
48124. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK
48125. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
48126. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK
48127. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
48128. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK
48129. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
48130. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK
48131. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
48132. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK
48133. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
48134. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK
48135. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
48136. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK
48137. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
48138. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK
48139. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
48140. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK
48141. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
48142. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK
48143. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
48144. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK
48145. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
48146. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK
48147. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
48148. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK
48149. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
48150. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK
48151. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
48152. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK
48153. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
48154. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK
48155. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
48156. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK
48157. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
48158. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK
48159. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
48160. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK
48161. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
48162. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK
48163. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
48164. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK
48165. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
48166. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK
48167. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
48168. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK
48169. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
48170. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK
48171. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
48172. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK
48173. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
48174. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK
48175. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
48176. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK
48177. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
48178. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK
48179. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
48180. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK
48181. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
48182. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK
48183. BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
48184. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK
48185. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
48186. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK
48187. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
48188. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK
48189. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
48190. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK
48191. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
48192. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK
48193. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
48194. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK
48195. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
48196. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK
48197. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
48198. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK
48199. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
48200. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK
48201. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
48202. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK
48203. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
48204. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK
48205. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
48206. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK
48207. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
48208. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK
48209. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
48210. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK
48211. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
48212. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK
48213. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
48214. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK
48215. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
48216. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK
48217. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
48218. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK
48219. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
48220. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK
48221. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
48222. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK
48223. BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
48224. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK
48225. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
48226. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK
48227. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
48228. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK
48229. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
48230. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK
48231. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
48232. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK
48233. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
48234. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK
48235. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
48236. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK
48237. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
48238. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK
48239. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
48240. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK
48241. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
48242. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK
48243. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
48244. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK
48245. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
48246. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK
48247. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
48248. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK
48249. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
48250. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK
48251. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
48252. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK
48253. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
48254. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK
48255. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
48256. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK
48257. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
48258. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK
48259. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
48260. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK
48261. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
48262. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK
48263. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
48264. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK
48265. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
48266. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK
48267. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
48268. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK
48269. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
48270. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK
48271. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
48272. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK
48273. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
48274. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK
48275. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
48276. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK
48277. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
48278. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK
48279. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
48280. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK
48281. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
48282. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK
48283. BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
48284. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK
48285. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
48286. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK
48287. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
48288. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK
48289. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
48290. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK
48291. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
48292. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK
48293. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
48294. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK
48295. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
48296. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK
48297. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
48298. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK
48299. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
48300. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK
48301. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
48302. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK
48303. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
48304. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK
48305. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
48306. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK
48307. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
48308. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK
48309. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
48310. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK
48311. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
48312. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK
48313. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
48314. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK
48315. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
48316. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK
48317. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
48318. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK
48319. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
48320. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK
48321. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
48322. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK
48323. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
48324. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK
48325. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
48326. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK
48327. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
48328. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK
48329. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
48330. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK
48331. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
48332. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK
48333. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
48334. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK
48335. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
48336. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK
48337. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
48338. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK
48339. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
48340. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK
48341. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
48342. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK
48343. BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
48344. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK
48345. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
48346. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK
48347. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
48348. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK
48349. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
48350. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK
48351. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
48352. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK
48353. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
48354. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK
48355. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
48356. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK
48357. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
48358. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK
48359. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
48360. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK
48361. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
48362. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK
48363. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
48364. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK
48365. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
48366. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK
48367. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
48368. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK
48369. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
48370. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK
48371. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
48372. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK
48373. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
48374. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK
48375. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
48376. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK
48377. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
48378. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK
48379. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
48380. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK
48381. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
48382. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK
48383. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
48384. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK
48385. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
48386. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK
48387. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
48388. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK
48389. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
48390. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK
48391. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
48392. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK
48393. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
48394. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK
48395. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
48396. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK
48397. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
48398. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK
48399. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
48400. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK
48401. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
48402. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK
48403. BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
48404. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK
48405. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
48406. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK
48407. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
48408. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK
48409. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
48410. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK
48411. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
48412. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK
48413. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
48414. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK
48415. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
48416. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK
48417. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
48418. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK
48419. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
48420. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK
48421. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
48422. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK
48423. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
48424. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK
48425. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
48426. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK
48427. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
48428. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK
48429. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
48430. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK
48431. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
48432. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK
48433. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
48434. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK
48435. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
48436. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK
48437. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
48438. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK
48439. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
48440. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK
48441. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
48442. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK
48443. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
48444. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK
48445. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
48446. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK
48447. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
48448. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK
48449. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
48450. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK
48451. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
48452. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK
48453. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
48454. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK
48455. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
48456. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK
48457. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
48458. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK
48459. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
48460. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK
48461. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
48462. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK
48463. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
48464. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK
48465. BIFPLR4_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
48466. BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK
48467. BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
48468. BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK
48469. BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
48470. BIFPLR4_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
48471. BIFPLR4_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
48472. BIFPLR4_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK
48473. BIFPLR4_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
48474. BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
48475. BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
48476. BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
48477. BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
48478. BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
48479. BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
48480. BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
48481. BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
48482. BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
48483. BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
48484. BIFPLR4_1_PCIE_ESM_HEADER_2__CAP_ID_MASK
48485. BIFPLR4_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
48486. BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
48487. BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
48488. BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
48489. BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
48490. BIFPLR4_1_PCIE_HDR_LOG0__TLP_HDR_MASK
48491. BIFPLR4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
48492. BIFPLR4_1_PCIE_HDR_LOG1__TLP_HDR_MASK
48493. BIFPLR4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
48494. BIFPLR4_1_PCIE_HDR_LOG2__TLP_HDR_MASK
48495. BIFPLR4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
48496. BIFPLR4_1_PCIE_HDR_LOG3__TLP_HDR_MASK
48497. BIFPLR4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
48498. BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
48499. BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
48500. BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
48501. BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
48502. BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
48503. BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
48504. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
48505. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
48506. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
48507. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
48508. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
48509. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
48510. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
48511. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
48512. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
48513. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
48514. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
48515. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
48516. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
48517. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
48518. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
48519. BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
48520. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
48521. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
48522. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
48523. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
48524. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
48525. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
48526. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
48527. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
48528. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
48529. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
48530. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
48531. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
48532. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
48533. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
48534. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
48535. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
48536. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
48537. BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
48538. BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48539. BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48540. BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48541. BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48542. BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48543. BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48544. BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48545. BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48546. BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48547. BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48548. BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48549. BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48550. BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48551. BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48552. BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48553. BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48554. BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48555. BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48556. BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48557. BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48558. BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48559. BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48560. BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48561. BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48562. BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48563. BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48564. BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48565. BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48566. BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48567. BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48568. BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48569. BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48570. BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48571. BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48572. BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48573. BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48574. BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48575. BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48576. BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48577. BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48578. BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48579. BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48580. BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48581. BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48582. BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48583. BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48584. BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48585. BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48586. BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48587. BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48588. BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48589. BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48590. BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48591. BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48592. BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48593. BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48594. BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48595. BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48596. BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48597. BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48598. BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48599. BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48600. BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48601. BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48602. BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48603. BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48604. BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48605. BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48606. BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48607. BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48608. BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48609. BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48610. BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48611. BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48612. BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48613. BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48614. BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48615. BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48616. BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48617. BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48618. BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48619. BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48620. BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48621. BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48622. BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48623. BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48624. BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48625. BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48626. BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48627. BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48628. BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48629. BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48630. BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48631. BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48632. BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48633. BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48634. BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48635. BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48636. BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48637. BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48638. BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48639. BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48640. BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48641. BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48642. BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48643. BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48644. BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48645. BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48646. BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48647. BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48648. BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48649. BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48650. BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48651. BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48652. BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48653. BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48654. BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48655. BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48656. BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48657. BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48658. BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
48659. BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
48660. BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
48661. BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
48662. BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
48663. BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
48664. BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
48665. BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
48666. BIFPLR4_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
48667. BIFPLR4_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
48668. BIFPLR4_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
48669. BIFPLR4_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
48670. BIFPLR4_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
48671. BIFPLR4_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
48672. BIFPLR4_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
48673. BIFPLR4_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
48674. BIFPLR4_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
48675. BIFPLR4_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
48676. BIFPLR4_1_PCIE_LINK_CNTL3__RESERVED_MASK
48677. BIFPLR4_1_PCIE_LINK_CNTL3__RESERVED__SHIFT
48678. BIFPLR4_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
48679. BIFPLR4_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
48680. BIFPLR4_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
48681. BIFPLR4_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
48682. BIFPLR4_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
48683. BIFPLR4_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
48684. BIFPLR4_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
48685. BIFPLR4_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
48686. BIFPLR4_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
48687. BIFPLR4_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
48688. BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
48689. BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
48690. BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
48691. BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
48692. BIFPLR4_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
48693. BIFPLR4_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
48694. BIFPLR4_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK
48695. BIFPLR4_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
48696. BIFPLR4_1_PCIE_MC_CNTL__MC_ENABLE_MASK
48697. BIFPLR4_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT
48698. BIFPLR4_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
48699. BIFPLR4_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
48700. BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
48701. BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
48702. BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
48703. BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
48704. BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
48705. BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
48706. BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
48707. BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
48708. BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
48709. BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
48710. BIFPLR4_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
48711. BIFPLR4_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
48712. BIFPLR4_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
48713. BIFPLR4_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
48714. BIFPLR4_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
48715. BIFPLR4_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
48716. BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
48717. BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
48718. BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
48719. BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
48720. BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
48721. BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
48722. BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
48723. BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
48724. BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
48725. BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
48726. BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
48727. BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
48728. BIFPLR4_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
48729. BIFPLR4_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
48730. BIFPLR4_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
48731. BIFPLR4_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
48732. BIFPLR4_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
48733. BIFPLR4_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
48734. BIFPLR4_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
48735. BIFPLR4_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
48736. BIFPLR4_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
48737. BIFPLR4_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
48738. BIFPLR4_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
48739. BIFPLR4_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
48740. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
48741. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
48742. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
48743. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
48744. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
48745. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
48746. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
48747. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
48748. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
48749. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
48750. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
48751. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
48752. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
48753. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
48754. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
48755. BIFPLR4_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
48756. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
48757. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
48758. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
48759. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
48760. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
48761. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
48762. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
48763. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
48764. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
48765. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
48766. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
48767. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
48768. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
48769. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
48770. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
48771. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
48772. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
48773. BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
48774. BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
48775. BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
48776. BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
48777. BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
48778. BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
48779. BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
48780. BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
48781. BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
48782. BIFPLR4_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
48783. BIFPLR4_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
48784. BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
48785. BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
48786. BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK
48787. BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
48788. BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
48789. BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
48790. BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
48791. BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
48792. BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CTO_MASK
48793. BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
48794. BIFPLR4_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
48795. BIFPLR4_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
48796. BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
48797. BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
48798. BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK
48799. BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
48800. BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
48801. BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
48802. BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
48803. BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
48804. BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
48805. BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
48806. BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
48807. BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
48808. BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
48809. BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
48810. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
48811. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
48812. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
48813. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
48814. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
48815. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
48816. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
48817. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
48818. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
48819. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
48820. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
48821. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
48822. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
48823. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
48824. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
48825. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
48826. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
48827. BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
48828. BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
48829. BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
48830. BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
48831. BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
48832. BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
48833. BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
48834. BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
48835. BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
48836. BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK
48837. BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
48838. BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
48839. BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
48840. BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
48841. BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
48842. BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
48843. BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
48844. BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
48845. BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
48846. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
48847. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
48848. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
48849. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
48850. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
48851. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
48852. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
48853. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
48854. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
48855. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
48856. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
48857. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
48858. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
48859. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
48860. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
48861. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
48862. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
48863. BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
48864. BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
48865. BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
48866. BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
48867. BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
48868. BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
48869. BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
48870. BIFPLR4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
48871. BIFPLR4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
48872. BIFPLR4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
48873. BIFPLR4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
48874. BIFPLR4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
48875. BIFPLR4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
48876. BIFPLR4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
48877. BIFPLR4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
48878. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
48879. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
48880. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
48881. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
48882. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
48883. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
48884. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
48885. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
48886. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
48887. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
48888. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
48889. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
48890. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
48891. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
48892. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
48893. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
48894. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
48895. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
48896. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
48897. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
48898. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
48899. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
48900. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
48901. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
48902. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
48903. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
48904. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
48905. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
48906. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
48907. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
48908. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
48909. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
48910. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
48911. BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
48912. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
48913. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
48914. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
48915. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
48916. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
48917. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
48918. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
48919. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
48920. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
48921. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
48922. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
48923. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
48924. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
48925. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
48926. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
48927. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
48928. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
48929. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
48930. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
48931. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
48932. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
48933. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
48934. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
48935. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
48936. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
48937. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
48938. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
48939. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
48940. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
48941. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
48942. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
48943. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
48944. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
48945. BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
48946. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
48947. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
48948. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
48949. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
48950. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
48951. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
48952. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
48953. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
48954. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
48955. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
48956. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
48957. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
48958. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
48959. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
48960. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
48961. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
48962. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
48963. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
48964. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
48965. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
48966. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
48967. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
48968. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
48969. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
48970. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
48971. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
48972. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
48973. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
48974. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
48975. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
48976. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
48977. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
48978. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
48979. BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
48980. BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
48981. BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
48982. BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
48983. BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
48984. BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
48985. BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
48986. BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
48987. BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
48988. BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
48989. BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
48990. BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
48991. BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
48992. BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
48993. BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
48994. BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
48995. BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
48996. BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
48997. BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
48998. BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
48999. BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
49000. BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
49001. BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
49002. BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
49003. BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
49004. BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
49005. BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
49006. BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
49007. BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
49008. BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
49009. BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
49010. BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
49011. BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
49012. BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
49013. BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
49014. BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
49015. BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
49016. BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
49017. BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
49018. BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
49019. BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
49020. BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
49021. BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
49022. BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
49023. BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
49024. BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
49025. BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
49026. BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
49027. BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
49028. BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
49029. BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
49030. BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
49031. BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
49032. BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
49033. BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
49034. BIFPLR4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
49035. BIFPLR4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
49036. BIFPLR4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
49037. BIFPLR4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
49038. BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
49039. BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
49040. BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
49041. BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
49042. BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
49043. BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
49044. BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
49045. BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
49046. BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
49047. BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
49048. BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
49049. BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
49050. BIFPLR4_1_PMI_CAP_LIST__CAP_ID_MASK
49051. BIFPLR4_1_PMI_CAP_LIST__CAP_ID__SHIFT
49052. BIFPLR4_1_PMI_CAP_LIST__NEXT_PTR_MASK
49053. BIFPLR4_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
49054. BIFPLR4_1_PMI_CAP__AUX_CURRENT_MASK
49055. BIFPLR4_1_PMI_CAP__AUX_CURRENT__SHIFT
49056. BIFPLR4_1_PMI_CAP__D1_SUPPORT_MASK
49057. BIFPLR4_1_PMI_CAP__D1_SUPPORT__SHIFT
49058. BIFPLR4_1_PMI_CAP__D2_SUPPORT_MASK
49059. BIFPLR4_1_PMI_CAP__D2_SUPPORT__SHIFT
49060. BIFPLR4_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
49061. BIFPLR4_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
49062. BIFPLR4_1_PMI_CAP__PME_CLOCK_MASK
49063. BIFPLR4_1_PMI_CAP__PME_CLOCK__SHIFT
49064. BIFPLR4_1_PMI_CAP__PME_SUPPORT_MASK
49065. BIFPLR4_1_PMI_CAP__PME_SUPPORT__SHIFT
49066. BIFPLR4_1_PMI_CAP__VERSION_MASK
49067. BIFPLR4_1_PMI_CAP__VERSION__SHIFT
49068. BIFPLR4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
49069. BIFPLR4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
49070. BIFPLR4_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
49071. BIFPLR4_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
49072. BIFPLR4_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
49073. BIFPLR4_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
49074. BIFPLR4_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
49075. BIFPLR4_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
49076. BIFPLR4_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
49077. BIFPLR4_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
49078. BIFPLR4_1_PMI_STATUS_CNTL__PME_EN_MASK
49079. BIFPLR4_1_PMI_STATUS_CNTL__PME_EN__SHIFT
49080. BIFPLR4_1_PMI_STATUS_CNTL__PME_STATUS_MASK
49081. BIFPLR4_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
49082. BIFPLR4_1_PMI_STATUS_CNTL__PMI_DATA_MASK
49083. BIFPLR4_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
49084. BIFPLR4_1_PMI_STATUS_CNTL__POWER_STATE_MASK
49085. BIFPLR4_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
49086. BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
49087. BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
49088. BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
49089. BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
49090. BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
49091. BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
49092. BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
49093. BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
49094. BIFPLR4_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
49095. BIFPLR4_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
49096. BIFPLR4_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
49097. BIFPLR4_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
49098. BIFPLR4_1_PROG_INTERFACE__PROG_INTERFACE_MASK
49099. BIFPLR4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
49100. BIFPLR4_1_REVISION_ID__MAJOR_REV_ID_MASK
49101. BIFPLR4_1_REVISION_ID__MAJOR_REV_ID__SHIFT
49102. BIFPLR4_1_REVISION_ID__MINOR_REV_ID_MASK
49103. BIFPLR4_1_REVISION_ID__MINOR_REV_ID__SHIFT
49104. BIFPLR4_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
49105. BIFPLR4_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
49106. BIFPLR4_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
49107. BIFPLR4_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
49108. BIFPLR4_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK
49109. BIFPLR4_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
49110. BIFPLR4_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
49111. BIFPLR4_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
49112. BIFPLR4_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
49113. BIFPLR4_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
49114. BIFPLR4_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
49115. BIFPLR4_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
49116. BIFPLR4_1_ROOT_STATUS__PME_PENDING_MASK
49117. BIFPLR4_1_ROOT_STATUS__PME_PENDING__SHIFT
49118. BIFPLR4_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK
49119. BIFPLR4_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
49120. BIFPLR4_1_ROOT_STATUS__PME_STATUS_MASK
49121. BIFPLR4_1_ROOT_STATUS__PME_STATUS__SHIFT
49122. BIFPLR4_1_SECONDARY_STATUS__CAP_LIST_MASK
49123. BIFPLR4_1_SECONDARY_STATUS__CAP_LIST__SHIFT
49124. BIFPLR4_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK
49125. BIFPLR4_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
49126. BIFPLR4_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
49127. BIFPLR4_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
49128. BIFPLR4_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
49129. BIFPLR4_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
49130. BIFPLR4_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
49131. BIFPLR4_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
49132. BIFPLR4_1_SECONDARY_STATUS__PCI_66_EN_MASK
49133. BIFPLR4_1_SECONDARY_STATUS__PCI_66_EN__SHIFT
49134. BIFPLR4_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
49135. BIFPLR4_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
49136. BIFPLR4_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
49137. BIFPLR4_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
49138. BIFPLR4_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
49139. BIFPLR4_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
49140. BIFPLR4_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
49141. BIFPLR4_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
49142. BIFPLR4_1_SLOT_CAP2__RESERVED_MASK
49143. BIFPLR4_1_SLOT_CAP2__RESERVED__SHIFT
49144. BIFPLR4_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
49145. BIFPLR4_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
49146. BIFPLR4_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
49147. BIFPLR4_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
49148. BIFPLR4_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
49149. BIFPLR4_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
49150. BIFPLR4_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK
49151. BIFPLR4_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
49152. BIFPLR4_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK
49153. BIFPLR4_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
49154. BIFPLR4_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
49155. BIFPLR4_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
49156. BIFPLR4_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
49157. BIFPLR4_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
49158. BIFPLR4_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
49159. BIFPLR4_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
49160. BIFPLR4_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
49161. BIFPLR4_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
49162. BIFPLR4_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
49163. BIFPLR4_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
49164. BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
49165. BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
49166. BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
49167. BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
49168. BIFPLR4_1_SLOT_CNTL2__RESERVED_MASK
49169. BIFPLR4_1_SLOT_CNTL2__RESERVED__SHIFT
49170. BIFPLR4_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
49171. BIFPLR4_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
49172. BIFPLR4_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
49173. BIFPLR4_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
49174. BIFPLR4_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
49175. BIFPLR4_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
49176. BIFPLR4_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
49177. BIFPLR4_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
49178. BIFPLR4_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
49179. BIFPLR4_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
49180. BIFPLR4_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
49181. BIFPLR4_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
49182. BIFPLR4_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
49183. BIFPLR4_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
49184. BIFPLR4_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
49185. BIFPLR4_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
49186. BIFPLR4_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
49187. BIFPLR4_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
49188. BIFPLR4_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
49189. BIFPLR4_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
49190. BIFPLR4_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
49191. BIFPLR4_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
49192. BIFPLR4_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
49193. BIFPLR4_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
49194. BIFPLR4_1_SLOT_STATUS2__RESERVED_MASK
49195. BIFPLR4_1_SLOT_STATUS2__RESERVED__SHIFT
49196. BIFPLR4_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
49197. BIFPLR4_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
49198. BIFPLR4_1_SLOT_STATUS__COMMAND_COMPLETED_MASK
49199. BIFPLR4_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
49200. BIFPLR4_1_SLOT_STATUS__DL_STATE_CHANGED_MASK
49201. BIFPLR4_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
49202. BIFPLR4_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
49203. BIFPLR4_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
49204. BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
49205. BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
49206. BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK
49207. BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
49208. BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
49209. BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
49210. BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
49211. BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
49212. BIFPLR4_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
49213. BIFPLR4_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
49214. BIFPLR4_1_SSID_CAP_LIST__CAP_ID_MASK
49215. BIFPLR4_1_SSID_CAP_LIST__CAP_ID__SHIFT
49216. BIFPLR4_1_SSID_CAP_LIST__NEXT_PTR_MASK
49217. BIFPLR4_1_SSID_CAP_LIST__NEXT_PTR__SHIFT
49218. BIFPLR4_1_SSID_CAP__SUBSYSTEM_ID_MASK
49219. BIFPLR4_1_SSID_CAP__SUBSYSTEM_ID__SHIFT
49220. BIFPLR4_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
49221. BIFPLR4_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
49222. BIFPLR4_1_STATUS__CAP_LIST_MASK
49223. BIFPLR4_1_STATUS__CAP_LIST__SHIFT
49224. BIFPLR4_1_STATUS__DEVSEL_TIMING_MASK
49225. BIFPLR4_1_STATUS__DEVSEL_TIMING__SHIFT
49226. BIFPLR4_1_STATUS__FAST_BACK_CAPABLE_MASK
49227. BIFPLR4_1_STATUS__FAST_BACK_CAPABLE__SHIFT
49228. BIFPLR4_1_STATUS__INT_STATUS_MASK
49229. BIFPLR4_1_STATUS__INT_STATUS__SHIFT
49230. BIFPLR4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
49231. BIFPLR4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
49232. BIFPLR4_1_STATUS__PARITY_ERROR_DETECTED_MASK
49233. BIFPLR4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
49234. BIFPLR4_1_STATUS__PCI_66_EN_MASK
49235. BIFPLR4_1_STATUS__PCI_66_EN__SHIFT
49236. BIFPLR4_1_STATUS__RECEIVED_MASTER_ABORT_MASK
49237. BIFPLR4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
49238. BIFPLR4_1_STATUS__RECEIVED_TARGET_ABORT_MASK
49239. BIFPLR4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
49240. BIFPLR4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
49241. BIFPLR4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
49242. BIFPLR4_1_STATUS__SIGNAL_TARGET_ABORT_MASK
49243. BIFPLR4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
49244. BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
49245. BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
49246. BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
49247. BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
49248. BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
49249. BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
49250. BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
49251. BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
49252. BIFPLR4_1_SUB_CLASS__SUB_CLASS_MASK
49253. BIFPLR4_1_SUB_CLASS__SUB_CLASS__SHIFT
49254. BIFPLR4_1_VENDOR_ID__VENDOR_ID_MASK
49255. BIFPLR4_1_VENDOR_ID__VENDOR_ID__SHIFT
49256. BIFPLR4_2_BASE_CLASS__BASE_CLASS_MASK
49257. BIFPLR4_2_BASE_CLASS__BASE_CLASS__SHIFT
49258. BIFPLR4_2_BIST__BIST_CAP_MASK
49259. BIFPLR4_2_BIST__BIST_CAP__SHIFT
49260. BIFPLR4_2_BIST__BIST_COMP_MASK
49261. BIFPLR4_2_BIST__BIST_COMP__SHIFT
49262. BIFPLR4_2_BIST__BIST_STRT_MASK
49263. BIFPLR4_2_BIST__BIST_STRT__SHIFT
49264. BIFPLR4_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
49265. BIFPLR4_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
49266. BIFPLR4_2_CAP_PTR__CAP_PTR_MASK
49267. BIFPLR4_2_CAP_PTR__CAP_PTR__SHIFT
49268. BIFPLR4_2_COMMAND__AD_STEPPING_MASK
49269. BIFPLR4_2_COMMAND__AD_STEPPING__SHIFT
49270. BIFPLR4_2_COMMAND__BUS_MASTER_EN_MASK
49271. BIFPLR4_2_COMMAND__BUS_MASTER_EN__SHIFT
49272. BIFPLR4_2_COMMAND__FAST_B2B_EN_MASK
49273. BIFPLR4_2_COMMAND__FAST_B2B_EN__SHIFT
49274. BIFPLR4_2_COMMAND__INT_DIS_MASK
49275. BIFPLR4_2_COMMAND__INT_DIS__SHIFT
49276. BIFPLR4_2_COMMAND__IO_ACCESS_EN_MASK
49277. BIFPLR4_2_COMMAND__IO_ACCESS_EN__SHIFT
49278. BIFPLR4_2_COMMAND__MEM_ACCESS_EN_MASK
49279. BIFPLR4_2_COMMAND__MEM_ACCESS_EN__SHIFT
49280. BIFPLR4_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
49281. BIFPLR4_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
49282. BIFPLR4_2_COMMAND__PAL_SNOOP_EN_MASK
49283. BIFPLR4_2_COMMAND__PAL_SNOOP_EN__SHIFT
49284. BIFPLR4_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
49285. BIFPLR4_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
49286. BIFPLR4_2_COMMAND__SERR_EN_MASK
49287. BIFPLR4_2_COMMAND__SERR_EN__SHIFT
49288. BIFPLR4_2_COMMAND__SPECIAL_CYCLE_EN_MASK
49289. BIFPLR4_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
49290. BIFPLR4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
49291. BIFPLR4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
49292. BIFPLR4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
49293. BIFPLR4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
49294. BIFPLR4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
49295. BIFPLR4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
49296. BIFPLR4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
49297. BIFPLR4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
49298. BIFPLR4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
49299. BIFPLR4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
49300. BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
49301. BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
49302. BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
49303. BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
49304. BIFPLR4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
49305. BIFPLR4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
49306. BIFPLR4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
49307. BIFPLR4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
49308. BIFPLR4_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
49309. BIFPLR4_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
49310. BIFPLR4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
49311. BIFPLR4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
49312. BIFPLR4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
49313. BIFPLR4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
49314. BIFPLR4_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
49315. BIFPLR4_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
49316. BIFPLR4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
49317. BIFPLR4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
49318. BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
49319. BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
49320. BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
49321. BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
49322. BIFPLR4_2_DEVICE_CAP__EXTENDED_TAG_MASK
49323. BIFPLR4_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
49324. BIFPLR4_2_DEVICE_CAP__FLR_CAPABLE_MASK
49325. BIFPLR4_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
49326. BIFPLR4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
49327. BIFPLR4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
49328. BIFPLR4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
49329. BIFPLR4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
49330. BIFPLR4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
49331. BIFPLR4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
49332. BIFPLR4_2_DEVICE_CAP__PHANTOM_FUNC_MASK
49333. BIFPLR4_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
49334. BIFPLR4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
49335. BIFPLR4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
49336. BIFPLR4_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
49337. BIFPLR4_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
49338. BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
49339. BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
49340. BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
49341. BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
49342. BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
49343. BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
49344. BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
49345. BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
49346. BIFPLR4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
49347. BIFPLR4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
49348. BIFPLR4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
49349. BIFPLR4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
49350. BIFPLR4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
49351. BIFPLR4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
49352. BIFPLR4_2_DEVICE_CNTL2__LTR_EN_MASK
49353. BIFPLR4_2_DEVICE_CNTL2__LTR_EN__SHIFT
49354. BIFPLR4_2_DEVICE_CNTL2__OBFF_EN_MASK
49355. BIFPLR4_2_DEVICE_CNTL2__OBFF_EN__SHIFT
49356. BIFPLR4_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
49357. BIFPLR4_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
49358. BIFPLR4_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
49359. BIFPLR4_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
49360. BIFPLR4_2_DEVICE_CNTL__CORR_ERR_EN_MASK
49361. BIFPLR4_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
49362. BIFPLR4_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
49363. BIFPLR4_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
49364. BIFPLR4_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
49365. BIFPLR4_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
49366. BIFPLR4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
49367. BIFPLR4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
49368. BIFPLR4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
49369. BIFPLR4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
49370. BIFPLR4_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
49371. BIFPLR4_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
49372. BIFPLR4_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
49373. BIFPLR4_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
49374. BIFPLR4_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
49375. BIFPLR4_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
49376. BIFPLR4_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
49377. BIFPLR4_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
49378. BIFPLR4_2_DEVICE_CNTL__USR_REPORT_EN_MASK
49379. BIFPLR4_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
49380. BIFPLR4_2_DEVICE_ID__DEVICE_ID_MASK
49381. BIFPLR4_2_DEVICE_ID__DEVICE_ID__SHIFT
49382. BIFPLR4_2_DEVICE_STATUS2__RESERVED_MASK
49383. BIFPLR4_2_DEVICE_STATUS2__RESERVED__SHIFT
49384. BIFPLR4_2_DEVICE_STATUS__AUX_PWR_MASK
49385. BIFPLR4_2_DEVICE_STATUS__AUX_PWR__SHIFT
49386. BIFPLR4_2_DEVICE_STATUS__CORR_ERR_MASK
49387. BIFPLR4_2_DEVICE_STATUS__CORR_ERR__SHIFT
49388. BIFPLR4_2_DEVICE_STATUS__FATAL_ERR_MASK
49389. BIFPLR4_2_DEVICE_STATUS__FATAL_ERR__SHIFT
49390. BIFPLR4_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
49391. BIFPLR4_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
49392. BIFPLR4_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
49393. BIFPLR4_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
49394. BIFPLR4_2_DEVICE_STATUS__USR_DETECTED_MASK
49395. BIFPLR4_2_DEVICE_STATUS__USR_DETECTED__SHIFT
49396. BIFPLR4_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
49397. BIFPLR4_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
49398. BIFPLR4_2_HEADER__DEVICE_TYPE_MASK
49399. BIFPLR4_2_HEADER__DEVICE_TYPE__SHIFT
49400. BIFPLR4_2_HEADER__HEADER_TYPE_MASK
49401. BIFPLR4_2_HEADER__HEADER_TYPE__SHIFT
49402. BIFPLR4_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
49403. BIFPLR4_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
49404. BIFPLR4_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
49405. BIFPLR4_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
49406. BIFPLR4_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
49407. BIFPLR4_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
49408. BIFPLR4_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
49409. BIFPLR4_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
49410. BIFPLR4_2_IO_BASE_LIMIT__IO_BASE_MASK
49411. BIFPLR4_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
49412. BIFPLR4_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
49413. BIFPLR4_2_IO_BASE_LIMIT__IO_BASE__SHIFT
49414. BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT_MASK
49415. BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
49416. BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
49417. BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT
49418. BIFPLR4_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
49419. BIFPLR4_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
49420. BIFPLR4_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK
49421. BIFPLR4_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
49422. BIFPLR4_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
49423. BIFPLR4_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
49424. BIFPLR4_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
49425. BIFPLR4_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
49426. BIFPLR4_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
49427. BIFPLR4_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
49428. BIFPLR4_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK
49429. BIFPLR4_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
49430. BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
49431. BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
49432. BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK
49433. BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
49434. BIFPLR4_2_LATENCY__LATENCY_TIMER_MASK
49435. BIFPLR4_2_LATENCY__LATENCY_TIMER__SHIFT
49436. BIFPLR4_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
49437. BIFPLR4_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
49438. BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
49439. BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
49440. BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
49441. BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
49442. BIFPLR4_2_LINK_CAP2__RESERVED_MASK
49443. BIFPLR4_2_LINK_CAP2__RESERVED__SHIFT
49444. BIFPLR4_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
49445. BIFPLR4_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
49446. BIFPLR4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
49447. BIFPLR4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
49448. BIFPLR4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
49449. BIFPLR4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
49450. BIFPLR4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
49451. BIFPLR4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
49452. BIFPLR4_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
49453. BIFPLR4_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
49454. BIFPLR4_2_LINK_CAP__L1_EXIT_LATENCY_MASK
49455. BIFPLR4_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
49456. BIFPLR4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
49457. BIFPLR4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
49458. BIFPLR4_2_LINK_CAP__LINK_SPEED_MASK
49459. BIFPLR4_2_LINK_CAP__LINK_SPEED__SHIFT
49460. BIFPLR4_2_LINK_CAP__LINK_WIDTH_MASK
49461. BIFPLR4_2_LINK_CAP__LINK_WIDTH__SHIFT
49462. BIFPLR4_2_LINK_CAP__PM_SUPPORT_MASK
49463. BIFPLR4_2_LINK_CAP__PM_SUPPORT__SHIFT
49464. BIFPLR4_2_LINK_CAP__PORT_NUMBER_MASK
49465. BIFPLR4_2_LINK_CAP__PORT_NUMBER__SHIFT
49466. BIFPLR4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
49467. BIFPLR4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
49468. BIFPLR4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
49469. BIFPLR4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
49470. BIFPLR4_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
49471. BIFPLR4_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
49472. BIFPLR4_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
49473. BIFPLR4_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
49474. BIFPLR4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
49475. BIFPLR4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
49476. BIFPLR4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
49477. BIFPLR4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
49478. BIFPLR4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
49479. BIFPLR4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
49480. BIFPLR4_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
49481. BIFPLR4_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
49482. BIFPLR4_2_LINK_CNTL2__XMIT_MARGIN_MASK
49483. BIFPLR4_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
49484. BIFPLR4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
49485. BIFPLR4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
49486. BIFPLR4_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
49487. BIFPLR4_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
49488. BIFPLR4_2_LINK_CNTL__EXTENDED_SYNC_MASK
49489. BIFPLR4_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
49490. BIFPLR4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
49491. BIFPLR4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
49492. BIFPLR4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
49493. BIFPLR4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
49494. BIFPLR4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
49495. BIFPLR4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
49496. BIFPLR4_2_LINK_CNTL__LINK_DIS_MASK
49497. BIFPLR4_2_LINK_CNTL__LINK_DIS__SHIFT
49498. BIFPLR4_2_LINK_CNTL__PM_CONTROL_MASK
49499. BIFPLR4_2_LINK_CNTL__PM_CONTROL__SHIFT
49500. BIFPLR4_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
49501. BIFPLR4_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
49502. BIFPLR4_2_LINK_CNTL__RETRAIN_LINK_MASK
49503. BIFPLR4_2_LINK_CNTL__RETRAIN_LINK__SHIFT
49504. BIFPLR4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
49505. BIFPLR4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
49506. BIFPLR4_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
49507. BIFPLR4_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
49508. BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
49509. BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
49510. BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
49511. BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
49512. BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
49513. BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
49514. BIFPLR4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
49515. BIFPLR4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
49516. BIFPLR4_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
49517. BIFPLR4_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
49518. BIFPLR4_2_LINK_STATUS__DL_ACTIVE_MASK
49519. BIFPLR4_2_LINK_STATUS__DL_ACTIVE__SHIFT
49520. BIFPLR4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
49521. BIFPLR4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
49522. BIFPLR4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
49523. BIFPLR4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
49524. BIFPLR4_2_LINK_STATUS__LINK_TRAINING_MASK
49525. BIFPLR4_2_LINK_STATUS__LINK_TRAINING__SHIFT
49526. BIFPLR4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
49527. BIFPLR4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
49528. BIFPLR4_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
49529. BIFPLR4_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
49530. BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
49531. BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
49532. BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
49533. BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
49534. BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
49535. BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
49536. BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
49537. BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
49538. BIFPLR4_2_MSI_CAP_LIST__CAP_ID_MASK
49539. BIFPLR4_2_MSI_CAP_LIST__CAP_ID__SHIFT
49540. BIFPLR4_2_MSI_CAP_LIST__NEXT_PTR_MASK
49541. BIFPLR4_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
49542. BIFPLR4_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
49543. BIFPLR4_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
49544. BIFPLR4_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
49545. BIFPLR4_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
49546. BIFPLR4_2_MSI_MAP_CAP_LIST__CAP_ID_MASK
49547. BIFPLR4_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
49548. BIFPLR4_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
49549. BIFPLR4_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
49550. BIFPLR4_2_MSI_MAP_CAP__CAP_TYPE_MASK
49551. BIFPLR4_2_MSI_MAP_CAP__CAP_TYPE__SHIFT
49552. BIFPLR4_2_MSI_MAP_CAP__EN_MASK
49553. BIFPLR4_2_MSI_MAP_CAP__EN__SHIFT
49554. BIFPLR4_2_MSI_MAP_CAP__FIXD_MASK
49555. BIFPLR4_2_MSI_MAP_CAP__FIXD__SHIFT
49556. BIFPLR4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
49557. BIFPLR4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
49558. BIFPLR4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
49559. BIFPLR4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
49560. BIFPLR4_2_MSI_MSG_CNTL__MSI_64BIT_MASK
49561. BIFPLR4_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
49562. BIFPLR4_2_MSI_MSG_CNTL__MSI_EN_MASK
49563. BIFPLR4_2_MSI_MSG_CNTL__MSI_EN__SHIFT
49564. BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
49565. BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
49566. BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
49567. BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
49568. BIFPLR4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
49569. BIFPLR4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
49570. BIFPLR4_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
49571. BIFPLR4_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
49572. BIFPLR4_2_MSI_MSG_DATA__MSI_DATA_MASK
49573. BIFPLR4_2_MSI_MSG_DATA__MSI_DATA__SHIFT
49574. BIFPLR4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
49575. BIFPLR4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
49576. BIFPLR4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
49577. BIFPLR4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
49578. BIFPLR4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
49579. BIFPLR4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
49580. BIFPLR4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
49581. BIFPLR4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
49582. BIFPLR4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
49583. BIFPLR4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
49584. BIFPLR4_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
49585. BIFPLR4_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
49586. BIFPLR4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
49587. BIFPLR4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
49588. BIFPLR4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
49589. BIFPLR4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
49590. BIFPLR4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
49591. BIFPLR4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
49592. BIFPLR4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
49593. BIFPLR4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
49594. BIFPLR4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
49595. BIFPLR4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
49596. BIFPLR4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
49597. BIFPLR4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
49598. BIFPLR4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
49599. BIFPLR4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
49600. BIFPLR4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
49601. BIFPLR4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
49602. BIFPLR4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
49603. BIFPLR4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
49604. BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
49605. BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
49606. BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
49607. BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
49608. BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
49609. BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
49610. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
49611. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
49612. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
49613. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
49614. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
49615. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
49616. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
49617. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
49618. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
49619. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
49620. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
49621. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
49622. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
49623. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
49624. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
49625. BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
49626. BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
49627. BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
49628. BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
49629. BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
49630. BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
49631. BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
49632. BIFPLR4_2_PCIE_CAP_LIST__CAP_ID_MASK
49633. BIFPLR4_2_PCIE_CAP_LIST__CAP_ID__SHIFT
49634. BIFPLR4_2_PCIE_CAP_LIST__NEXT_PTR_MASK
49635. BIFPLR4_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
49636. BIFPLR4_2_PCIE_CAP__DEVICE_TYPE_MASK
49637. BIFPLR4_2_PCIE_CAP__DEVICE_TYPE__SHIFT
49638. BIFPLR4_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
49639. BIFPLR4_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
49640. BIFPLR4_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
49641. BIFPLR4_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
49642. BIFPLR4_2_PCIE_CAP__VERSION_MASK
49643. BIFPLR4_2_PCIE_CAP__VERSION__SHIFT
49644. BIFPLR4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
49645. BIFPLR4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
49646. BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
49647. BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
49648. BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
49649. BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
49650. BIFPLR4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
49651. BIFPLR4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
49652. BIFPLR4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
49653. BIFPLR4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
49654. BIFPLR4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
49655. BIFPLR4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
49656. BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
49657. BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
49658. BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
49659. BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
49660. BIFPLR4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
49661. BIFPLR4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
49662. BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
49663. BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
49664. BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
49665. BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
49666. BIFPLR4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
49667. BIFPLR4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
49668. BIFPLR4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
49669. BIFPLR4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
49670. BIFPLR4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
49671. BIFPLR4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
49672. BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
49673. BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
49674. BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
49675. BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
49676. BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
49677. BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
49678. BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
49679. BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
49680. BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
49681. BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
49682. BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
49683. BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
49684. BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
49685. BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
49686. BIFPLR4_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
49687. BIFPLR4_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
49688. BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
49689. BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
49690. BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
49691. BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
49692. BIFPLR4_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
49693. BIFPLR4_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
49694. BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
49695. BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
49696. BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
49697. BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
49698. BIFPLR4_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
49699. BIFPLR4_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
49700. BIFPLR4_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
49701. BIFPLR4_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
49702. BIFPLR4_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
49703. BIFPLR4_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
49704. BIFPLR4_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
49705. BIFPLR4_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
49706. BIFPLR4_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
49707. BIFPLR4_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
49708. BIFPLR4_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
49709. BIFPLR4_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
49710. BIFPLR4_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
49711. BIFPLR4_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
49712. BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
49713. BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
49714. BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
49715. BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
49716. BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
49717. BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
49718. BIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
49719. BIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
49720. BIFPLR4_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
49721. BIFPLR4_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
49722. BIFPLR4_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
49723. BIFPLR4_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
49724. BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
49725. BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
49726. BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
49727. BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
49728. BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
49729. BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
49730. BIFPLR4_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
49731. BIFPLR4_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
49732. BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
49733. BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
49734. BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
49735. BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
49736. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK
49737. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
49738. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK
49739. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
49740. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK
49741. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
49742. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK
49743. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
49744. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK
49745. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
49746. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK
49747. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
49748. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK
49749. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
49750. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK
49751. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
49752. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK
49753. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
49754. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK
49755. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
49756. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK
49757. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
49758. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK
49759. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
49760. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK
49761. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
49762. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK
49763. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
49764. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK
49765. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
49766. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK
49767. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
49768. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK
49769. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
49770. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK
49771. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
49772. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK
49773. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
49774. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK
49775. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
49776. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK
49777. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
49778. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK
49779. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
49780. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK
49781. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
49782. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK
49783. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
49784. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK
49785. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
49786. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK
49787. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
49788. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK
49789. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
49790. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK
49791. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
49792. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK
49793. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
49794. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK
49795. BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
49796. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK
49797. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
49798. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK
49799. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
49800. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK
49801. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
49802. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK
49803. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
49804. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK
49805. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
49806. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK
49807. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
49808. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK
49809. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
49810. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK
49811. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
49812. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK
49813. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
49814. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK
49815. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
49816. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK
49817. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
49818. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK
49819. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
49820. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK
49821. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
49822. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK
49823. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
49824. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK
49825. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
49826. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK
49827. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
49828. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK
49829. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
49830. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK
49831. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
49832. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK
49833. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
49834. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK
49835. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
49836. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK
49837. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
49838. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK
49839. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
49840. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK
49841. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
49842. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK
49843. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
49844. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK
49845. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
49846. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK
49847. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
49848. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK
49849. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
49850. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK
49851. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
49852. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK
49853. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
49854. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK
49855. BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
49856. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK
49857. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
49858. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK
49859. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
49860. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK
49861. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
49862. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK
49863. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
49864. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK
49865. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
49866. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK
49867. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
49868. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK
49869. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
49870. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK
49871. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
49872. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK
49873. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
49874. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK
49875. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
49876. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK
49877. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
49878. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK
49879. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
49880. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK
49881. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
49882. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK
49883. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
49884. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK
49885. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
49886. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK
49887. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
49888. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK
49889. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
49890. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK
49891. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
49892. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK
49893. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
49894. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK
49895. BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
49896. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK
49897. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
49898. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK
49899. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
49900. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK
49901. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
49902. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK
49903. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
49904. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK
49905. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
49906. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK
49907. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
49908. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK
49909. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
49910. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK
49911. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
49912. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK
49913. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
49914. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK
49915. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
49916. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK
49917. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
49918. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK
49919. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
49920. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK
49921. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
49922. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK
49923. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
49924. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK
49925. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
49926. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK
49927. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
49928. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK
49929. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
49930. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK
49931. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
49932. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK
49933. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
49934. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK
49935. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
49936. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK
49937. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
49938. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK
49939. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
49940. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK
49941. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
49942. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK
49943. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
49944. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK
49945. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
49946. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK
49947. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
49948. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK
49949. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
49950. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK
49951. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
49952. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK
49953. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
49954. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK
49955. BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
49956. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK
49957. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
49958. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK
49959. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
49960. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK
49961. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
49962. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK
49963. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
49964. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK
49965. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
49966. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK
49967. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
49968. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK
49969. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
49970. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK
49971. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
49972. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK
49973. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
49974. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK
49975. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
49976. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK
49977. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
49978. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK
49979. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
49980. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK
49981. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
49982. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK
49983. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
49984. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK
49985. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
49986. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK
49987. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
49988. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK
49989. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
49990. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK
49991. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
49992. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK
49993. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
49994. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK
49995. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
49996. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK
49997. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
49998. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK
49999. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
50000. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK
50001. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
50002. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK
50003. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
50004. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK
50005. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
50006. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK
50007. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
50008. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK
50009. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
50010. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK
50011. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
50012. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK
50013. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
50014. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK
50015. BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
50016. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK
50017. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
50018. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK
50019. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
50020. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK
50021. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
50022. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK
50023. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
50024. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK
50025. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
50026. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK
50027. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
50028. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK
50029. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
50030. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK
50031. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
50032. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK
50033. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
50034. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK
50035. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
50036. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK
50037. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
50038. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK
50039. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
50040. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK
50041. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
50042. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK
50043. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
50044. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK
50045. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
50046. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK
50047. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
50048. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK
50049. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
50050. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK
50051. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
50052. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK
50053. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
50054. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK
50055. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
50056. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK
50057. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
50058. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK
50059. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
50060. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK
50061. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
50062. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK
50063. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
50064. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK
50065. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
50066. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK
50067. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
50068. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK
50069. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
50070. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK
50071. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
50072. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK
50073. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
50074. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK
50075. BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
50076. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK
50077. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
50078. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK
50079. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
50080. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK
50081. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
50082. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK
50083. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
50084. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK
50085. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
50086. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK
50087. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
50088. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK
50089. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
50090. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK
50091. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
50092. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK
50093. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
50094. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK
50095. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
50096. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK
50097. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
50098. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK
50099. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
50100. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK
50101. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
50102. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK
50103. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
50104. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK
50105. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
50106. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK
50107. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
50108. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK
50109. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
50110. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK
50111. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
50112. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK
50113. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
50114. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK
50115. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
50116. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK
50117. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
50118. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK
50119. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
50120. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK
50121. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
50122. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK
50123. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
50124. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK
50125. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
50126. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK
50127. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
50128. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK
50129. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
50130. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK
50131. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
50132. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK
50133. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
50134. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK
50135. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
50136. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK
50137. BIFPLR4_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
50138. BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK
50139. BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
50140. BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK
50141. BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
50142. BIFPLR4_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
50143. BIFPLR4_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
50144. BIFPLR4_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK
50145. BIFPLR4_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
50146. BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
50147. BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
50148. BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
50149. BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
50150. BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
50151. BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
50152. BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
50153. BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
50154. BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
50155. BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
50156. BIFPLR4_2_PCIE_ESM_HEADER_2__CAP_ID_MASK
50157. BIFPLR4_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
50158. BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
50159. BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
50160. BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
50161. BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
50162. BIFPLR4_2_PCIE_HDR_LOG0__TLP_HDR_MASK
50163. BIFPLR4_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
50164. BIFPLR4_2_PCIE_HDR_LOG1__TLP_HDR_MASK
50165. BIFPLR4_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
50166. BIFPLR4_2_PCIE_HDR_LOG2__TLP_HDR_MASK
50167. BIFPLR4_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
50168. BIFPLR4_2_PCIE_HDR_LOG3__TLP_HDR_MASK
50169. BIFPLR4_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
50170. BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
50171. BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
50172. BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
50173. BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
50174. BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
50175. BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
50176. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
50177. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
50178. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
50179. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
50180. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
50181. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
50182. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
50183. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
50184. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
50185. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
50186. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
50187. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
50188. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
50189. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
50190. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
50191. BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
50192. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
50193. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
50194. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
50195. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
50196. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
50197. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
50198. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
50199. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
50200. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
50201. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
50202. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
50203. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
50204. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
50205. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
50206. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
50207. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
50208. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
50209. BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
50210. BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50211. BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50212. BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50213. BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50214. BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50215. BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50216. BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50217. BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50218. BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50219. BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50220. BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50221. BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50222. BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50223. BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50224. BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50225. BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50226. BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50227. BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50228. BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50229. BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50230. BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50231. BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50232. BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50233. BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50234. BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50235. BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50236. BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50237. BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50238. BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50239. BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50240. BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50241. BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50242. BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50243. BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50244. BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50245. BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50246. BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50247. BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50248. BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50249. BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50250. BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50251. BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50252. BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50253. BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50254. BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50255. BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50256. BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50257. BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50258. BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50259. BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50260. BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50261. BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50262. BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50263. BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50264. BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50265. BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50266. BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50267. BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50268. BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50269. BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50270. BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50271. BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50272. BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50273. BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50274. BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50275. BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50276. BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50277. BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50278. BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50279. BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50280. BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50281. BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50282. BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50283. BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50284. BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50285. BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50286. BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50287. BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50288. BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50289. BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50290. BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50291. BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50292. BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50293. BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50294. BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50295. BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50296. BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50297. BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50298. BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50299. BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50300. BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50301. BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50302. BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50303. BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50304. BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50305. BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50306. BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50307. BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50308. BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50309. BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50310. BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50311. BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50312. BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50313. BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50314. BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50315. BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50316. BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50317. BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50318. BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50319. BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50320. BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50321. BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50322. BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50323. BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50324. BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50325. BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50326. BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50327. BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50328. BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50329. BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50330. BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
50331. BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
50332. BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
50333. BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
50334. BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
50335. BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
50336. BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
50337. BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
50338. BIFPLR4_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
50339. BIFPLR4_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
50340. BIFPLR4_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
50341. BIFPLR4_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
50342. BIFPLR4_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
50343. BIFPLR4_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
50344. BIFPLR4_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
50345. BIFPLR4_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
50346. BIFPLR4_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
50347. BIFPLR4_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
50348. BIFPLR4_2_PCIE_LINK_CNTL3__RESERVED_MASK
50349. BIFPLR4_2_PCIE_LINK_CNTL3__RESERVED__SHIFT
50350. BIFPLR4_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
50351. BIFPLR4_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
50352. BIFPLR4_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
50353. BIFPLR4_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
50354. BIFPLR4_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
50355. BIFPLR4_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
50356. BIFPLR4_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
50357. BIFPLR4_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
50358. BIFPLR4_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
50359. BIFPLR4_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
50360. BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
50361. BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
50362. BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
50363. BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
50364. BIFPLR4_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
50365. BIFPLR4_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
50366. BIFPLR4_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK
50367. BIFPLR4_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
50368. BIFPLR4_2_PCIE_MC_CNTL__MC_ENABLE_MASK
50369. BIFPLR4_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT
50370. BIFPLR4_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
50371. BIFPLR4_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
50372. BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
50373. BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
50374. BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
50375. BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
50376. BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
50377. BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
50378. BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
50379. BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
50380. BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
50381. BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
50382. BIFPLR4_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
50383. BIFPLR4_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
50384. BIFPLR4_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
50385. BIFPLR4_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
50386. BIFPLR4_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
50387. BIFPLR4_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
50388. BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
50389. BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
50390. BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
50391. BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
50392. BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
50393. BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
50394. BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
50395. BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
50396. BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
50397. BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
50398. BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
50399. BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
50400. BIFPLR4_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
50401. BIFPLR4_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
50402. BIFPLR4_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
50403. BIFPLR4_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
50404. BIFPLR4_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
50405. BIFPLR4_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
50406. BIFPLR4_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
50407. BIFPLR4_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
50408. BIFPLR4_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
50409. BIFPLR4_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
50410. BIFPLR4_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
50411. BIFPLR4_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
50412. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
50413. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
50414. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
50415. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
50416. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
50417. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
50418. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
50419. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
50420. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
50421. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
50422. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
50423. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
50424. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
50425. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
50426. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
50427. BIFPLR4_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
50428. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
50429. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
50430. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
50431. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
50432. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
50433. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
50434. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
50435. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
50436. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
50437. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
50438. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
50439. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
50440. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
50441. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
50442. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
50443. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
50444. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
50445. BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
50446. BIFPLR4_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
50447. BIFPLR4_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
50448. BIFPLR4_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
50449. BIFPLR4_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
50450. BIFPLR4_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
50451. BIFPLR4_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
50452. BIFPLR4_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
50453. BIFPLR4_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
50454. BIFPLR4_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
50455. BIFPLR4_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
50456. BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
50457. BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
50458. BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK
50459. BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
50460. BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
50461. BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
50462. BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
50463. BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
50464. BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CTO_MASK
50465. BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
50466. BIFPLR4_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
50467. BIFPLR4_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
50468. BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
50469. BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
50470. BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK
50471. BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
50472. BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
50473. BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
50474. BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
50475. BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
50476. BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
50477. BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
50478. BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
50479. BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
50480. BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
50481. BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
50482. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
50483. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
50484. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
50485. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
50486. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
50487. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
50488. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
50489. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
50490. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
50491. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
50492. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
50493. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
50494. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
50495. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
50496. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
50497. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
50498. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
50499. BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
50500. BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
50501. BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
50502. BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
50503. BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
50504. BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
50505. BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
50506. BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
50507. BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
50508. BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK
50509. BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
50510. BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
50511. BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
50512. BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
50513. BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
50514. BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
50515. BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
50516. BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
50517. BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
50518. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
50519. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
50520. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
50521. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
50522. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
50523. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
50524. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
50525. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
50526. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
50527. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
50528. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
50529. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
50530. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
50531. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
50532. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
50533. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
50534. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
50535. BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
50536. BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
50537. BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
50538. BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
50539. BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
50540. BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
50541. BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
50542. BIFPLR4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
50543. BIFPLR4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
50544. BIFPLR4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
50545. BIFPLR4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
50546. BIFPLR4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
50547. BIFPLR4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
50548. BIFPLR4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
50549. BIFPLR4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
50550. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
50551. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
50552. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
50553. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
50554. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
50555. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
50556. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
50557. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
50558. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
50559. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
50560. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
50561. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
50562. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
50563. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
50564. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
50565. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
50566. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
50567. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
50568. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
50569. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
50570. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
50571. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
50572. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
50573. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
50574. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
50575. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
50576. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
50577. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
50578. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
50579. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
50580. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
50581. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
50582. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
50583. BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
50584. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
50585. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
50586. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
50587. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
50588. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
50589. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
50590. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
50591. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
50592. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
50593. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
50594. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
50595. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
50596. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
50597. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
50598. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
50599. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
50600. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
50601. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
50602. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
50603. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
50604. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
50605. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
50606. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
50607. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
50608. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
50609. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
50610. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
50611. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
50612. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
50613. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
50614. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
50615. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
50616. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
50617. BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
50618. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
50619. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
50620. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
50621. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
50622. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
50623. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
50624. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
50625. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
50626. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
50627. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
50628. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
50629. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
50630. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
50631. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
50632. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
50633. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
50634. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
50635. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
50636. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
50637. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
50638. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
50639. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
50640. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
50641. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
50642. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
50643. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
50644. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
50645. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
50646. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
50647. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
50648. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
50649. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
50650. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
50651. BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
50652. BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
50653. BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
50654. BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
50655. BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
50656. BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
50657. BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
50658. BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
50659. BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
50660. BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
50661. BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
50662. BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
50663. BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
50664. BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
50665. BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
50666. BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
50667. BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
50668. BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
50669. BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
50670. BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
50671. BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
50672. BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
50673. BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
50674. BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
50675. BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
50676. BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
50677. BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
50678. BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
50679. BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
50680. BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
50681. BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
50682. BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
50683. BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
50684. BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
50685. BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
50686. BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
50687. BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
50688. BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
50689. BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
50690. BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
50691. BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
50692. BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
50693. BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
50694. BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
50695. BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
50696. BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
50697. BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
50698. BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
50699. BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
50700. BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
50701. BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
50702. BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
50703. BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
50704. BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
50705. BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
50706. BIFPLR4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
50707. BIFPLR4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
50708. BIFPLR4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
50709. BIFPLR4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
50710. BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
50711. BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
50712. BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
50713. BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
50714. BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
50715. BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
50716. BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
50717. BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
50718. BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
50719. BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
50720. BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
50721. BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
50722. BIFPLR4_2_PMI_CAP_LIST__CAP_ID_MASK
50723. BIFPLR4_2_PMI_CAP_LIST__CAP_ID__SHIFT
50724. BIFPLR4_2_PMI_CAP_LIST__NEXT_PTR_MASK
50725. BIFPLR4_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
50726. BIFPLR4_2_PMI_CAP__AUX_CURRENT_MASK
50727. BIFPLR4_2_PMI_CAP__AUX_CURRENT__SHIFT
50728. BIFPLR4_2_PMI_CAP__D1_SUPPORT_MASK
50729. BIFPLR4_2_PMI_CAP__D1_SUPPORT__SHIFT
50730. BIFPLR4_2_PMI_CAP__D2_SUPPORT_MASK
50731. BIFPLR4_2_PMI_CAP__D2_SUPPORT__SHIFT
50732. BIFPLR4_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
50733. BIFPLR4_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
50734. BIFPLR4_2_PMI_CAP__PME_CLOCK_MASK
50735. BIFPLR4_2_PMI_CAP__PME_CLOCK__SHIFT
50736. BIFPLR4_2_PMI_CAP__PME_SUPPORT_MASK
50737. BIFPLR4_2_PMI_CAP__PME_SUPPORT__SHIFT
50738. BIFPLR4_2_PMI_CAP__VERSION_MASK
50739. BIFPLR4_2_PMI_CAP__VERSION__SHIFT
50740. BIFPLR4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
50741. BIFPLR4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
50742. BIFPLR4_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
50743. BIFPLR4_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
50744. BIFPLR4_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
50745. BIFPLR4_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
50746. BIFPLR4_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
50747. BIFPLR4_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
50748. BIFPLR4_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
50749. BIFPLR4_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
50750. BIFPLR4_2_PMI_STATUS_CNTL__PME_EN_MASK
50751. BIFPLR4_2_PMI_STATUS_CNTL__PME_EN__SHIFT
50752. BIFPLR4_2_PMI_STATUS_CNTL__PME_STATUS_MASK
50753. BIFPLR4_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
50754. BIFPLR4_2_PMI_STATUS_CNTL__PMI_DATA_MASK
50755. BIFPLR4_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
50756. BIFPLR4_2_PMI_STATUS_CNTL__POWER_STATE_MASK
50757. BIFPLR4_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
50758. BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
50759. BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
50760. BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
50761. BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
50762. BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
50763. BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
50764. BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
50765. BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
50766. BIFPLR4_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
50767. BIFPLR4_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
50768. BIFPLR4_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
50769. BIFPLR4_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
50770. BIFPLR4_2_PROG_INTERFACE__PROG_INTERFACE_MASK
50771. BIFPLR4_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
50772. BIFPLR4_2_REVISION_ID__MAJOR_REV_ID_MASK
50773. BIFPLR4_2_REVISION_ID__MAJOR_REV_ID__SHIFT
50774. BIFPLR4_2_REVISION_ID__MINOR_REV_ID_MASK
50775. BIFPLR4_2_REVISION_ID__MINOR_REV_ID__SHIFT
50776. BIFPLR4_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
50777. BIFPLR4_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
50778. BIFPLR4_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
50779. BIFPLR4_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
50780. BIFPLR4_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK
50781. BIFPLR4_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
50782. BIFPLR4_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
50783. BIFPLR4_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
50784. BIFPLR4_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
50785. BIFPLR4_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
50786. BIFPLR4_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
50787. BIFPLR4_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
50788. BIFPLR4_2_ROOT_STATUS__PME_PENDING_MASK
50789. BIFPLR4_2_ROOT_STATUS__PME_PENDING__SHIFT
50790. BIFPLR4_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK
50791. BIFPLR4_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
50792. BIFPLR4_2_ROOT_STATUS__PME_STATUS_MASK
50793. BIFPLR4_2_ROOT_STATUS__PME_STATUS__SHIFT
50794. BIFPLR4_2_SECONDARY_STATUS__CAP_LIST_MASK
50795. BIFPLR4_2_SECONDARY_STATUS__CAP_LIST__SHIFT
50796. BIFPLR4_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK
50797. BIFPLR4_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
50798. BIFPLR4_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
50799. BIFPLR4_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
50800. BIFPLR4_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
50801. BIFPLR4_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
50802. BIFPLR4_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
50803. BIFPLR4_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
50804. BIFPLR4_2_SECONDARY_STATUS__PCI_66_EN_MASK
50805. BIFPLR4_2_SECONDARY_STATUS__PCI_66_EN__SHIFT
50806. BIFPLR4_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
50807. BIFPLR4_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
50808. BIFPLR4_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
50809. BIFPLR4_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
50810. BIFPLR4_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
50811. BIFPLR4_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
50812. BIFPLR4_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
50813. BIFPLR4_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
50814. BIFPLR4_2_SLOT_CAP2__RESERVED_MASK
50815. BIFPLR4_2_SLOT_CAP2__RESERVED__SHIFT
50816. BIFPLR4_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
50817. BIFPLR4_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
50818. BIFPLR4_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
50819. BIFPLR4_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
50820. BIFPLR4_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
50821. BIFPLR4_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
50822. BIFPLR4_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK
50823. BIFPLR4_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
50824. BIFPLR4_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK
50825. BIFPLR4_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
50826. BIFPLR4_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
50827. BIFPLR4_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
50828. BIFPLR4_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
50829. BIFPLR4_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
50830. BIFPLR4_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
50831. BIFPLR4_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
50832. BIFPLR4_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
50833. BIFPLR4_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
50834. BIFPLR4_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
50835. BIFPLR4_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
50836. BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
50837. BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
50838. BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
50839. BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
50840. BIFPLR4_2_SLOT_CNTL2__RESERVED_MASK
50841. BIFPLR4_2_SLOT_CNTL2__RESERVED__SHIFT
50842. BIFPLR4_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
50843. BIFPLR4_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
50844. BIFPLR4_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
50845. BIFPLR4_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
50846. BIFPLR4_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
50847. BIFPLR4_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
50848. BIFPLR4_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
50849. BIFPLR4_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
50850. BIFPLR4_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
50851. BIFPLR4_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
50852. BIFPLR4_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
50853. BIFPLR4_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
50854. BIFPLR4_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
50855. BIFPLR4_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
50856. BIFPLR4_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
50857. BIFPLR4_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
50858. BIFPLR4_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
50859. BIFPLR4_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
50860. BIFPLR4_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
50861. BIFPLR4_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
50862. BIFPLR4_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
50863. BIFPLR4_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
50864. BIFPLR4_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
50865. BIFPLR4_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
50866. BIFPLR4_2_SLOT_STATUS2__RESERVED_MASK
50867. BIFPLR4_2_SLOT_STATUS2__RESERVED__SHIFT
50868. BIFPLR4_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
50869. BIFPLR4_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
50870. BIFPLR4_2_SLOT_STATUS__COMMAND_COMPLETED_MASK
50871. BIFPLR4_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
50872. BIFPLR4_2_SLOT_STATUS__DL_STATE_CHANGED_MASK
50873. BIFPLR4_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
50874. BIFPLR4_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
50875. BIFPLR4_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
50876. BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
50877. BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
50878. BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK
50879. BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
50880. BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
50881. BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
50882. BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
50883. BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
50884. BIFPLR4_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
50885. BIFPLR4_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
50886. BIFPLR4_2_SSID_CAP_LIST__CAP_ID_MASK
50887. BIFPLR4_2_SSID_CAP_LIST__CAP_ID__SHIFT
50888. BIFPLR4_2_SSID_CAP_LIST__NEXT_PTR_MASK
50889. BIFPLR4_2_SSID_CAP_LIST__NEXT_PTR__SHIFT
50890. BIFPLR4_2_SSID_CAP__SUBSYSTEM_ID_MASK
50891. BIFPLR4_2_SSID_CAP__SUBSYSTEM_ID__SHIFT
50892. BIFPLR4_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
50893. BIFPLR4_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
50894. BIFPLR4_2_STATUS__CAP_LIST_MASK
50895. BIFPLR4_2_STATUS__CAP_LIST__SHIFT
50896. BIFPLR4_2_STATUS__DEVSEL_TIMING_MASK
50897. BIFPLR4_2_STATUS__DEVSEL_TIMING__SHIFT
50898. BIFPLR4_2_STATUS__FAST_BACK_CAPABLE_MASK
50899. BIFPLR4_2_STATUS__FAST_BACK_CAPABLE__SHIFT
50900. BIFPLR4_2_STATUS__INT_STATUS_MASK
50901. BIFPLR4_2_STATUS__INT_STATUS__SHIFT
50902. BIFPLR4_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
50903. BIFPLR4_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
50904. BIFPLR4_2_STATUS__PARITY_ERROR_DETECTED_MASK
50905. BIFPLR4_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
50906. BIFPLR4_2_STATUS__PCI_66_EN_MASK
50907. BIFPLR4_2_STATUS__PCI_66_EN__SHIFT
50908. BIFPLR4_2_STATUS__RECEIVED_MASTER_ABORT_MASK
50909. BIFPLR4_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
50910. BIFPLR4_2_STATUS__RECEIVED_TARGET_ABORT_MASK
50911. BIFPLR4_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
50912. BIFPLR4_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
50913. BIFPLR4_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
50914. BIFPLR4_2_STATUS__SIGNAL_TARGET_ABORT_MASK
50915. BIFPLR4_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
50916. BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
50917. BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
50918. BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
50919. BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
50920. BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
50921. BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
50922. BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
50923. BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
50924. BIFPLR4_2_SUB_CLASS__SUB_CLASS_MASK
50925. BIFPLR4_2_SUB_CLASS__SUB_CLASS__SHIFT
50926. BIFPLR4_2_VENDOR_ID__VENDOR_ID_MASK
50927. BIFPLR4_2_VENDOR_ID__VENDOR_ID__SHIFT
50928. BIFPLR5_0_BASE_CLASS__BASE_CLASS_MASK
50929. BIFPLR5_0_BASE_CLASS__BASE_CLASS__SHIFT
50930. BIFPLR5_0_BIST__BIST_CAP_MASK
50931. BIFPLR5_0_BIST__BIST_CAP__SHIFT
50932. BIFPLR5_0_BIST__BIST_COMP_MASK
50933. BIFPLR5_0_BIST__BIST_COMP__SHIFT
50934. BIFPLR5_0_BIST__BIST_STRT_MASK
50935. BIFPLR5_0_BIST__BIST_STRT__SHIFT
50936. BIFPLR5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
50937. BIFPLR5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
50938. BIFPLR5_0_CAP_PTR__CAP_PTR_MASK
50939. BIFPLR5_0_CAP_PTR__CAP_PTR__SHIFT
50940. BIFPLR5_0_COMMAND__AD_STEPPING_MASK
50941. BIFPLR5_0_COMMAND__AD_STEPPING__SHIFT
50942. BIFPLR5_0_COMMAND__BUS_MASTER_EN_MASK
50943. BIFPLR5_0_COMMAND__BUS_MASTER_EN__SHIFT
50944. BIFPLR5_0_COMMAND__FAST_B2B_EN_MASK
50945. BIFPLR5_0_COMMAND__FAST_B2B_EN__SHIFT
50946. BIFPLR5_0_COMMAND__INT_DIS_MASK
50947. BIFPLR5_0_COMMAND__INT_DIS__SHIFT
50948. BIFPLR5_0_COMMAND__IO_ACCESS_EN_MASK
50949. BIFPLR5_0_COMMAND__IO_ACCESS_EN__SHIFT
50950. BIFPLR5_0_COMMAND__MEM_ACCESS_EN_MASK
50951. BIFPLR5_0_COMMAND__MEM_ACCESS_EN__SHIFT
50952. BIFPLR5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
50953. BIFPLR5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
50954. BIFPLR5_0_COMMAND__PAL_SNOOP_EN_MASK
50955. BIFPLR5_0_COMMAND__PAL_SNOOP_EN__SHIFT
50956. BIFPLR5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
50957. BIFPLR5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
50958. BIFPLR5_0_COMMAND__SERR_EN_MASK
50959. BIFPLR5_0_COMMAND__SERR_EN__SHIFT
50960. BIFPLR5_0_COMMAND__SPECIAL_CYCLE_EN_MASK
50961. BIFPLR5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
50962. BIFPLR5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
50963. BIFPLR5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
50964. BIFPLR5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
50965. BIFPLR5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
50966. BIFPLR5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
50967. BIFPLR5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
50968. BIFPLR5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
50969. BIFPLR5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
50970. BIFPLR5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
50971. BIFPLR5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
50972. BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
50973. BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
50974. BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
50975. BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
50976. BIFPLR5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
50977. BIFPLR5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
50978. BIFPLR5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
50979. BIFPLR5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
50980. BIFPLR5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
50981. BIFPLR5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
50982. BIFPLR5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
50983. BIFPLR5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
50984. BIFPLR5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
50985. BIFPLR5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
50986. BIFPLR5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
50987. BIFPLR5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
50988. BIFPLR5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
50989. BIFPLR5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
50990. BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
50991. BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
50992. BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
50993. BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
50994. BIFPLR5_0_DEVICE_CAP__EXTENDED_TAG_MASK
50995. BIFPLR5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
50996. BIFPLR5_0_DEVICE_CAP__FLR_CAPABLE_MASK
50997. BIFPLR5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
50998. BIFPLR5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
50999. BIFPLR5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
51000. BIFPLR5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
51001. BIFPLR5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
51002. BIFPLR5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
51003. BIFPLR5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
51004. BIFPLR5_0_DEVICE_CAP__PHANTOM_FUNC_MASK
51005. BIFPLR5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
51006. BIFPLR5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
51007. BIFPLR5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
51008. BIFPLR5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
51009. BIFPLR5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
51010. BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
51011. BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
51012. BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
51013. BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
51014. BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
51015. BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
51016. BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
51017. BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
51018. BIFPLR5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
51019. BIFPLR5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
51020. BIFPLR5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
51021. BIFPLR5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
51022. BIFPLR5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
51023. BIFPLR5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
51024. BIFPLR5_0_DEVICE_CNTL2__LTR_EN_MASK
51025. BIFPLR5_0_DEVICE_CNTL2__LTR_EN__SHIFT
51026. BIFPLR5_0_DEVICE_CNTL2__OBFF_EN_MASK
51027. BIFPLR5_0_DEVICE_CNTL2__OBFF_EN__SHIFT
51028. BIFPLR5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
51029. BIFPLR5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
51030. BIFPLR5_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
51031. BIFPLR5_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
51032. BIFPLR5_0_DEVICE_CNTL__CORR_ERR_EN_MASK
51033. BIFPLR5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
51034. BIFPLR5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
51035. BIFPLR5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
51036. BIFPLR5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
51037. BIFPLR5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
51038. BIFPLR5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
51039. BIFPLR5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
51040. BIFPLR5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
51041. BIFPLR5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
51042. BIFPLR5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
51043. BIFPLR5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
51044. BIFPLR5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
51045. BIFPLR5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
51046. BIFPLR5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
51047. BIFPLR5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
51048. BIFPLR5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
51049. BIFPLR5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
51050. BIFPLR5_0_DEVICE_CNTL__USR_REPORT_EN_MASK
51051. BIFPLR5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
51052. BIFPLR5_0_DEVICE_ID__DEVICE_ID_MASK
51053. BIFPLR5_0_DEVICE_ID__DEVICE_ID__SHIFT
51054. BIFPLR5_0_DEVICE_STATUS2__RESERVED_MASK
51055. BIFPLR5_0_DEVICE_STATUS2__RESERVED__SHIFT
51056. BIFPLR5_0_DEVICE_STATUS__AUX_PWR_MASK
51057. BIFPLR5_0_DEVICE_STATUS__AUX_PWR__SHIFT
51058. BIFPLR5_0_DEVICE_STATUS__CORR_ERR_MASK
51059. BIFPLR5_0_DEVICE_STATUS__CORR_ERR__SHIFT
51060. BIFPLR5_0_DEVICE_STATUS__FATAL_ERR_MASK
51061. BIFPLR5_0_DEVICE_STATUS__FATAL_ERR__SHIFT
51062. BIFPLR5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
51063. BIFPLR5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
51064. BIFPLR5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
51065. BIFPLR5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
51066. BIFPLR5_0_DEVICE_STATUS__USR_DETECTED_MASK
51067. BIFPLR5_0_DEVICE_STATUS__USR_DETECTED__SHIFT
51068. BIFPLR5_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
51069. BIFPLR5_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
51070. BIFPLR5_0_HEADER__DEVICE_TYPE_MASK
51071. BIFPLR5_0_HEADER__DEVICE_TYPE__SHIFT
51072. BIFPLR5_0_HEADER__HEADER_TYPE_MASK
51073. BIFPLR5_0_HEADER__HEADER_TYPE__SHIFT
51074. BIFPLR5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
51075. BIFPLR5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
51076. BIFPLR5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
51077. BIFPLR5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
51078. BIFPLR5_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
51079. BIFPLR5_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
51080. BIFPLR5_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
51081. BIFPLR5_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
51082. BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_MASK
51083. BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
51084. BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
51085. BIFPLR5_0_IO_BASE_LIMIT__IO_BASE__SHIFT
51086. BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_MASK
51087. BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
51088. BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
51089. BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT
51090. BIFPLR5_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
51091. BIFPLR5_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
51092. BIFPLR5_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK
51093. BIFPLR5_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
51094. BIFPLR5_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
51095. BIFPLR5_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
51096. BIFPLR5_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
51097. BIFPLR5_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
51098. BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
51099. BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
51100. BIFPLR5_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK
51101. BIFPLR5_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
51102. BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
51103. BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
51104. BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK
51105. BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
51106. BIFPLR5_0_LATENCY__LATENCY_TIMER_MASK
51107. BIFPLR5_0_LATENCY__LATENCY_TIMER__SHIFT
51108. BIFPLR5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
51109. BIFPLR5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
51110. BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
51111. BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
51112. BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
51113. BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
51114. BIFPLR5_0_LINK_CAP2__RESERVED_MASK
51115. BIFPLR5_0_LINK_CAP2__RESERVED__SHIFT
51116. BIFPLR5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
51117. BIFPLR5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
51118. BIFPLR5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
51119. BIFPLR5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
51120. BIFPLR5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
51121. BIFPLR5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
51122. BIFPLR5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
51123. BIFPLR5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
51124. BIFPLR5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
51125. BIFPLR5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
51126. BIFPLR5_0_LINK_CAP__L1_EXIT_LATENCY_MASK
51127. BIFPLR5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
51128. BIFPLR5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
51129. BIFPLR5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
51130. BIFPLR5_0_LINK_CAP__LINK_SPEED_MASK
51131. BIFPLR5_0_LINK_CAP__LINK_SPEED__SHIFT
51132. BIFPLR5_0_LINK_CAP__LINK_WIDTH_MASK
51133. BIFPLR5_0_LINK_CAP__LINK_WIDTH__SHIFT
51134. BIFPLR5_0_LINK_CAP__PM_SUPPORT_MASK
51135. BIFPLR5_0_LINK_CAP__PM_SUPPORT__SHIFT
51136. BIFPLR5_0_LINK_CAP__PORT_NUMBER_MASK
51137. BIFPLR5_0_LINK_CAP__PORT_NUMBER__SHIFT
51138. BIFPLR5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
51139. BIFPLR5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
51140. BIFPLR5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
51141. BIFPLR5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
51142. BIFPLR5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
51143. BIFPLR5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
51144. BIFPLR5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
51145. BIFPLR5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
51146. BIFPLR5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
51147. BIFPLR5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
51148. BIFPLR5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
51149. BIFPLR5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
51150. BIFPLR5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
51151. BIFPLR5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
51152. BIFPLR5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
51153. BIFPLR5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
51154. BIFPLR5_0_LINK_CNTL2__XMIT_MARGIN_MASK
51155. BIFPLR5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
51156. BIFPLR5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
51157. BIFPLR5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
51158. BIFPLR5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
51159. BIFPLR5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
51160. BIFPLR5_0_LINK_CNTL__EXTENDED_SYNC_MASK
51161. BIFPLR5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
51162. BIFPLR5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
51163. BIFPLR5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
51164. BIFPLR5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
51165. BIFPLR5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
51166. BIFPLR5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
51167. BIFPLR5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
51168. BIFPLR5_0_LINK_CNTL__LINK_DIS_MASK
51169. BIFPLR5_0_LINK_CNTL__LINK_DIS__SHIFT
51170. BIFPLR5_0_LINK_CNTL__PM_CONTROL_MASK
51171. BIFPLR5_0_LINK_CNTL__PM_CONTROL__SHIFT
51172. BIFPLR5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
51173. BIFPLR5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
51174. BIFPLR5_0_LINK_CNTL__RETRAIN_LINK_MASK
51175. BIFPLR5_0_LINK_CNTL__RETRAIN_LINK__SHIFT
51176. BIFPLR5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
51177. BIFPLR5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
51178. BIFPLR5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
51179. BIFPLR5_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
51180. BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
51181. BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
51182. BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
51183. BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
51184. BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
51185. BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
51186. BIFPLR5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
51187. BIFPLR5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
51188. BIFPLR5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
51189. BIFPLR5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
51190. BIFPLR5_0_LINK_STATUS__DL_ACTIVE_MASK
51191. BIFPLR5_0_LINK_STATUS__DL_ACTIVE__SHIFT
51192. BIFPLR5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
51193. BIFPLR5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
51194. BIFPLR5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
51195. BIFPLR5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
51196. BIFPLR5_0_LINK_STATUS__LINK_TRAINING_MASK
51197. BIFPLR5_0_LINK_STATUS__LINK_TRAINING__SHIFT
51198. BIFPLR5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
51199. BIFPLR5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
51200. BIFPLR5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
51201. BIFPLR5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
51202. BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
51203. BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
51204. BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
51205. BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
51206. BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
51207. BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
51208. BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
51209. BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
51210. BIFPLR5_0_MSI_CAP_LIST__CAP_ID_MASK
51211. BIFPLR5_0_MSI_CAP_LIST__CAP_ID__SHIFT
51212. BIFPLR5_0_MSI_CAP_LIST__NEXT_PTR_MASK
51213. BIFPLR5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
51214. BIFPLR5_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
51215. BIFPLR5_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
51216. BIFPLR5_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
51217. BIFPLR5_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
51218. BIFPLR5_0_MSI_MAP_CAP_LIST__CAP_ID_MASK
51219. BIFPLR5_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
51220. BIFPLR5_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
51221. BIFPLR5_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
51222. BIFPLR5_0_MSI_MAP_CAP__CAP_TYPE_MASK
51223. BIFPLR5_0_MSI_MAP_CAP__CAP_TYPE__SHIFT
51224. BIFPLR5_0_MSI_MAP_CAP__EN_MASK
51225. BIFPLR5_0_MSI_MAP_CAP__EN__SHIFT
51226. BIFPLR5_0_MSI_MAP_CAP__FIXD_MASK
51227. BIFPLR5_0_MSI_MAP_CAP__FIXD__SHIFT
51228. BIFPLR5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
51229. BIFPLR5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
51230. BIFPLR5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
51231. BIFPLR5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
51232. BIFPLR5_0_MSI_MSG_CNTL__MSI_64BIT_MASK
51233. BIFPLR5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
51234. BIFPLR5_0_MSI_MSG_CNTL__MSI_EN_MASK
51235. BIFPLR5_0_MSI_MSG_CNTL__MSI_EN__SHIFT
51236. BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
51237. BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
51238. BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
51239. BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
51240. BIFPLR5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
51241. BIFPLR5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
51242. BIFPLR5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
51243. BIFPLR5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
51244. BIFPLR5_0_MSI_MSG_DATA__MSI_DATA_MASK
51245. BIFPLR5_0_MSI_MSG_DATA__MSI_DATA__SHIFT
51246. BIFPLR5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
51247. BIFPLR5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
51248. BIFPLR5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
51249. BIFPLR5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
51250. BIFPLR5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
51251. BIFPLR5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
51252. BIFPLR5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
51253. BIFPLR5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
51254. BIFPLR5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
51255. BIFPLR5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
51256. BIFPLR5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
51257. BIFPLR5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
51258. BIFPLR5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
51259. BIFPLR5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
51260. BIFPLR5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
51261. BIFPLR5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
51262. BIFPLR5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
51263. BIFPLR5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
51264. BIFPLR5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
51265. BIFPLR5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
51266. BIFPLR5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
51267. BIFPLR5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
51268. BIFPLR5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
51269. BIFPLR5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
51270. BIFPLR5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
51271. BIFPLR5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
51272. BIFPLR5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
51273. BIFPLR5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
51274. BIFPLR5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
51275. BIFPLR5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
51276. BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
51277. BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
51278. BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
51279. BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
51280. BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
51281. BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
51282. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
51283. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
51284. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
51285. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
51286. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
51287. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
51288. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
51289. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
51290. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
51291. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
51292. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
51293. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
51294. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
51295. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
51296. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
51297. BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
51298. BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
51299. BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
51300. BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
51301. BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
51302. BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
51303. BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
51304. BIFPLR5_0_PCIE_CAP_LIST__CAP_ID_MASK
51305. BIFPLR5_0_PCIE_CAP_LIST__CAP_ID__SHIFT
51306. BIFPLR5_0_PCIE_CAP_LIST__NEXT_PTR_MASK
51307. BIFPLR5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
51308. BIFPLR5_0_PCIE_CAP__DEVICE_TYPE_MASK
51309. BIFPLR5_0_PCIE_CAP__DEVICE_TYPE__SHIFT
51310. BIFPLR5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
51311. BIFPLR5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
51312. BIFPLR5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
51313. BIFPLR5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
51314. BIFPLR5_0_PCIE_CAP__VERSION_MASK
51315. BIFPLR5_0_PCIE_CAP__VERSION__SHIFT
51316. BIFPLR5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
51317. BIFPLR5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
51318. BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
51319. BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
51320. BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
51321. BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
51322. BIFPLR5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
51323. BIFPLR5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
51324. BIFPLR5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
51325. BIFPLR5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
51326. BIFPLR5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
51327. BIFPLR5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
51328. BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
51329. BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
51330. BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
51331. BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
51332. BIFPLR5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
51333. BIFPLR5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
51334. BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
51335. BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
51336. BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
51337. BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
51338. BIFPLR5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
51339. BIFPLR5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
51340. BIFPLR5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
51341. BIFPLR5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
51342. BIFPLR5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
51343. BIFPLR5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
51344. BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
51345. BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
51346. BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
51347. BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
51348. BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
51349. BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
51350. BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
51351. BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
51352. BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
51353. BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
51354. BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
51355. BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
51356. BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
51357. BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
51358. BIFPLR5_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
51359. BIFPLR5_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
51360. BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
51361. BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
51362. BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
51363. BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
51364. BIFPLR5_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
51365. BIFPLR5_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
51366. BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
51367. BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
51368. BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
51369. BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
51370. BIFPLR5_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
51371. BIFPLR5_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
51372. BIFPLR5_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
51373. BIFPLR5_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
51374. BIFPLR5_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
51375. BIFPLR5_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
51376. BIFPLR5_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
51377. BIFPLR5_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
51378. BIFPLR5_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
51379. BIFPLR5_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
51380. BIFPLR5_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
51381. BIFPLR5_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
51382. BIFPLR5_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
51383. BIFPLR5_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
51384. BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
51385. BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
51386. BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
51387. BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
51388. BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
51389. BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
51390. BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
51391. BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
51392. BIFPLR5_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
51393. BIFPLR5_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
51394. BIFPLR5_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
51395. BIFPLR5_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
51396. BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
51397. BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
51398. BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
51399. BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
51400. BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
51401. BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
51402. BIFPLR5_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
51403. BIFPLR5_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
51404. BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
51405. BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
51406. BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
51407. BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
51408. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK
51409. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
51410. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK
51411. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
51412. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK
51413. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
51414. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK
51415. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
51416. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK
51417. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
51418. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK
51419. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
51420. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK
51421. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
51422. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK
51423. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
51424. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK
51425. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
51426. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK
51427. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
51428. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK
51429. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
51430. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK
51431. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
51432. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK
51433. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
51434. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK
51435. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
51436. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK
51437. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
51438. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK
51439. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
51440. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK
51441. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
51442. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK
51443. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
51444. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK
51445. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
51446. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK
51447. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
51448. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK
51449. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
51450. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK
51451. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
51452. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK
51453. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
51454. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK
51455. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
51456. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK
51457. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
51458. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK
51459. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
51460. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK
51461. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
51462. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK
51463. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
51464. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK
51465. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
51466. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK
51467. BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
51468. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK
51469. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
51470. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK
51471. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
51472. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK
51473. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
51474. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK
51475. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
51476. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK
51477. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
51478. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK
51479. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
51480. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK
51481. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
51482. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK
51483. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
51484. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK
51485. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
51486. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK
51487. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
51488. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK
51489. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
51490. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK
51491. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
51492. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK
51493. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
51494. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK
51495. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
51496. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK
51497. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
51498. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK
51499. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
51500. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK
51501. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
51502. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK
51503. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
51504. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK
51505. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
51506. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK
51507. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
51508. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK
51509. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
51510. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK
51511. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
51512. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK
51513. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
51514. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK
51515. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
51516. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK
51517. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
51518. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK
51519. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
51520. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK
51521. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
51522. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK
51523. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
51524. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK
51525. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
51526. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK
51527. BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
51528. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK
51529. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
51530. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK
51531. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
51532. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK
51533. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
51534. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK
51535. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
51536. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK
51537. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
51538. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK
51539. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
51540. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK
51541. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
51542. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK
51543. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
51544. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK
51545. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
51546. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK
51547. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
51548. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK
51549. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
51550. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK
51551. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
51552. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK
51553. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
51554. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK
51555. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
51556. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK
51557. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
51558. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK
51559. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
51560. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK
51561. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
51562. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK
51563. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
51564. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK
51565. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
51566. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK
51567. BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
51568. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK
51569. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
51570. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK
51571. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
51572. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK
51573. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
51574. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK
51575. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
51576. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK
51577. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
51578. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK
51579. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
51580. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK
51581. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
51582. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK
51583. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
51584. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK
51585. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
51586. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK
51587. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
51588. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK
51589. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
51590. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK
51591. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
51592. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK
51593. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
51594. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK
51595. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
51596. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK
51597. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
51598. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK
51599. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
51600. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK
51601. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
51602. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK
51603. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
51604. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK
51605. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
51606. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK
51607. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
51608. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK
51609. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
51610. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK
51611. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
51612. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK
51613. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
51614. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK
51615. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
51616. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK
51617. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
51618. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK
51619. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
51620. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK
51621. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
51622. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK
51623. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
51624. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK
51625. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
51626. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK
51627. BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
51628. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK
51629. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
51630. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK
51631. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
51632. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK
51633. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
51634. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK
51635. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
51636. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK
51637. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
51638. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK
51639. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
51640. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK
51641. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
51642. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK
51643. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
51644. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK
51645. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
51646. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK
51647. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
51648. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK
51649. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
51650. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK
51651. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
51652. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK
51653. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
51654. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK
51655. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
51656. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK
51657. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
51658. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK
51659. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
51660. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK
51661. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
51662. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK
51663. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
51664. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK
51665. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
51666. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK
51667. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
51668. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK
51669. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
51670. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK
51671. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
51672. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK
51673. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
51674. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK
51675. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
51676. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK
51677. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
51678. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK
51679. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
51680. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK
51681. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
51682. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK
51683. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
51684. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK
51685. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
51686. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK
51687. BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
51688. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK
51689. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
51690. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK
51691. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
51692. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK
51693. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
51694. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK
51695. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
51696. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK
51697. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
51698. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK
51699. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
51700. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK
51701. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
51702. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK
51703. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
51704. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK
51705. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
51706. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK
51707. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
51708. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK
51709. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
51710. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK
51711. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
51712. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK
51713. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
51714. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK
51715. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
51716. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK
51717. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
51718. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK
51719. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
51720. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK
51721. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
51722. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK
51723. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
51724. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK
51725. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
51726. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK
51727. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
51728. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK
51729. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
51730. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK
51731. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
51732. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK
51733. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
51734. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK
51735. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
51736. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK
51737. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
51738. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK
51739. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
51740. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK
51741. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
51742. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK
51743. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
51744. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK
51745. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
51746. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK
51747. BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
51748. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK
51749. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
51750. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK
51751. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
51752. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK
51753. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
51754. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK
51755. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
51756. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK
51757. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
51758. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK
51759. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
51760. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK
51761. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
51762. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK
51763. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
51764. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK
51765. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
51766. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK
51767. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
51768. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK
51769. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
51770. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK
51771. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
51772. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK
51773. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
51774. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK
51775. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
51776. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK
51777. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
51778. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK
51779. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
51780. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK
51781. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
51782. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK
51783. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
51784. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK
51785. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
51786. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK
51787. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
51788. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK
51789. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
51790. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK
51791. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
51792. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK
51793. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
51794. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK
51795. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
51796. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK
51797. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
51798. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK
51799. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
51800. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK
51801. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
51802. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK
51803. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
51804. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK
51805. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
51806. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK
51807. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
51808. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK
51809. BIFPLR5_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
51810. BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK
51811. BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
51812. BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK
51813. BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
51814. BIFPLR5_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
51815. BIFPLR5_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
51816. BIFPLR5_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK
51817. BIFPLR5_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
51818. BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
51819. BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
51820. BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
51821. BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
51822. BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
51823. BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
51824. BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
51825. BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
51826. BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
51827. BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
51828. BIFPLR5_0_PCIE_ESM_HEADER_2__CAP_ID_MASK
51829. BIFPLR5_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
51830. BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
51831. BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
51832. BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
51833. BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
51834. BIFPLR5_0_PCIE_HDR_LOG0__TLP_HDR_MASK
51835. BIFPLR5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
51836. BIFPLR5_0_PCIE_HDR_LOG1__TLP_HDR_MASK
51837. BIFPLR5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
51838. BIFPLR5_0_PCIE_HDR_LOG2__TLP_HDR_MASK
51839. BIFPLR5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
51840. BIFPLR5_0_PCIE_HDR_LOG3__TLP_HDR_MASK
51841. BIFPLR5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
51842. BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
51843. BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
51844. BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
51845. BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
51846. BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
51847. BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
51848. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
51849. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
51850. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
51851. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
51852. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
51853. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
51854. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
51855. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
51856. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
51857. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
51858. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
51859. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
51860. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
51861. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
51862. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
51863. BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
51864. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
51865. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
51866. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
51867. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
51868. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
51869. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
51870. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
51871. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
51872. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
51873. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
51874. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
51875. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
51876. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
51877. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
51878. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
51879. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
51880. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
51881. BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
51882. BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51883. BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51884. BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51885. BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51886. BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51887. BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51888. BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51889. BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51890. BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51891. BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51892. BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51893. BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51894. BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51895. BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51896. BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51897. BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51898. BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51899. BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51900. BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51901. BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51902. BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51903. BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51904. BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51905. BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51906. BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51907. BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51908. BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51909. BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51910. BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51911. BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51912. BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51913. BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51914. BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51915. BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51916. BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51917. BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51918. BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51919. BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51920. BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51921. BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51922. BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51923. BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51924. BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51925. BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51926. BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51927. BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51928. BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51929. BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51930. BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51931. BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51932. BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51933. BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51934. BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51935. BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51936. BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51937. BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51938. BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51939. BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51940. BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51941. BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51942. BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51943. BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51944. BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51945. BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51946. BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51947. BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51948. BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51949. BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51950. BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51951. BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51952. BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51953. BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51954. BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51955. BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51956. BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51957. BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51958. BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51959. BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51960. BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51961. BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51962. BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51963. BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51964. BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51965. BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51966. BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51967. BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51968. BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51969. BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51970. BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51971. BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51972. BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51973. BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51974. BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51975. BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51976. BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51977. BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51978. BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51979. BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51980. BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51981. BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51982. BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51983. BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51984. BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51985. BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51986. BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51987. BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51988. BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51989. BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51990. BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51991. BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
51992. BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
51993. BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
51994. BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
51995. BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
51996. BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
51997. BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
51998. BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
51999. BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
52000. BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
52001. BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
52002. BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
52003. BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
52004. BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
52005. BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
52006. BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
52007. BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
52008. BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
52009. BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
52010. BIFPLR5_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
52011. BIFPLR5_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
52012. BIFPLR5_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
52013. BIFPLR5_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
52014. BIFPLR5_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
52015. BIFPLR5_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
52016. BIFPLR5_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
52017. BIFPLR5_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
52018. BIFPLR5_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
52019. BIFPLR5_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
52020. BIFPLR5_0_PCIE_LINK_CNTL3__RESERVED_MASK
52021. BIFPLR5_0_PCIE_LINK_CNTL3__RESERVED__SHIFT
52022. BIFPLR5_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
52023. BIFPLR5_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
52024. BIFPLR5_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
52025. BIFPLR5_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
52026. BIFPLR5_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
52027. BIFPLR5_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
52028. BIFPLR5_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
52029. BIFPLR5_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
52030. BIFPLR5_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
52031. BIFPLR5_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
52032. BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
52033. BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
52034. BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
52035. BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
52036. BIFPLR5_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
52037. BIFPLR5_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
52038. BIFPLR5_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK
52039. BIFPLR5_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
52040. BIFPLR5_0_PCIE_MC_CNTL__MC_ENABLE_MASK
52041. BIFPLR5_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT
52042. BIFPLR5_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
52043. BIFPLR5_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
52044. BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
52045. BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
52046. BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
52047. BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
52048. BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
52049. BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
52050. BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
52051. BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
52052. BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
52053. BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
52054. BIFPLR5_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
52055. BIFPLR5_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
52056. BIFPLR5_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
52057. BIFPLR5_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
52058. BIFPLR5_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
52059. BIFPLR5_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
52060. BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
52061. BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
52062. BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
52063. BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
52064. BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
52065. BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
52066. BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
52067. BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
52068. BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
52069. BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
52070. BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
52071. BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
52072. BIFPLR5_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
52073. BIFPLR5_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
52074. BIFPLR5_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
52075. BIFPLR5_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
52076. BIFPLR5_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
52077. BIFPLR5_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
52078. BIFPLR5_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
52079. BIFPLR5_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
52080. BIFPLR5_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
52081. BIFPLR5_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
52082. BIFPLR5_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
52083. BIFPLR5_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
52084. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
52085. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
52086. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
52087. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
52088. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
52089. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
52090. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
52091. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
52092. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
52093. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
52094. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
52095. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
52096. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
52097. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
52098. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
52099. BIFPLR5_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
52100. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
52101. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
52102. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
52103. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
52104. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
52105. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
52106. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
52107. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
52108. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
52109. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
52110. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
52111. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
52112. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
52113. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
52114. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
52115. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
52116. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
52117. BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
52118. BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
52119. BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
52120. BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
52121. BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
52122. BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
52123. BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
52124. BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
52125. BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
52126. BIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
52127. BIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
52128. BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
52129. BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
52130. BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK
52131. BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
52132. BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
52133. BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
52134. BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
52135. BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
52136. BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CTO_MASK
52137. BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
52138. BIFPLR5_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
52139. BIFPLR5_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
52140. BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
52141. BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
52142. BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK
52143. BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
52144. BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
52145. BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
52146. BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
52147. BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
52148. BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
52149. BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
52150. BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
52151. BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
52152. BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
52153. BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
52154. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
52155. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
52156. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
52157. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
52158. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
52159. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
52160. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
52161. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
52162. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
52163. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
52164. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
52165. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
52166. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
52167. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
52168. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
52169. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
52170. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
52171. BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
52172. BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
52173. BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
52174. BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
52175. BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
52176. BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
52177. BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
52178. BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
52179. BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
52180. BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK
52181. BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
52182. BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
52183. BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
52184. BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
52185. BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
52186. BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
52187. BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
52188. BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
52189. BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
52190. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
52191. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
52192. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
52193. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
52194. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
52195. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
52196. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
52197. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
52198. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
52199. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
52200. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
52201. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
52202. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
52203. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
52204. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
52205. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
52206. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
52207. BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
52208. BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
52209. BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
52210. BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
52211. BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
52212. BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
52213. BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
52214. BIFPLR5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
52215. BIFPLR5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
52216. BIFPLR5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
52217. BIFPLR5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
52218. BIFPLR5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
52219. BIFPLR5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
52220. BIFPLR5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
52221. BIFPLR5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
52222. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
52223. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
52224. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
52225. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
52226. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
52227. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
52228. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
52229. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
52230. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
52231. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
52232. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
52233. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
52234. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
52235. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
52236. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
52237. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
52238. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
52239. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
52240. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
52241. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
52242. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
52243. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
52244. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
52245. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
52246. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
52247. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
52248. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
52249. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
52250. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
52251. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
52252. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
52253. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
52254. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
52255. BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
52256. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
52257. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
52258. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
52259. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
52260. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
52261. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
52262. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
52263. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
52264. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
52265. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
52266. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
52267. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
52268. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
52269. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
52270. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
52271. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
52272. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
52273. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
52274. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
52275. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
52276. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
52277. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
52278. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
52279. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
52280. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
52281. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
52282. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
52283. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
52284. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
52285. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
52286. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
52287. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
52288. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
52289. BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
52290. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
52291. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
52292. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
52293. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
52294. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
52295. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
52296. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
52297. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
52298. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
52299. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
52300. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
52301. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
52302. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
52303. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
52304. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
52305. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
52306. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
52307. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
52308. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
52309. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
52310. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
52311. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
52312. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
52313. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
52314. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
52315. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
52316. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
52317. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
52318. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
52319. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
52320. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
52321. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
52322. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
52323. BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
52324. BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
52325. BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
52326. BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
52327. BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
52328. BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
52329. BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
52330. BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
52331. BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
52332. BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
52333. BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
52334. BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
52335. BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
52336. BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
52337. BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
52338. BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
52339. BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
52340. BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
52341. BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
52342. BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
52343. BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
52344. BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
52345. BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
52346. BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
52347. BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
52348. BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
52349. BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
52350. BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
52351. BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
52352. BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
52353. BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
52354. BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
52355. BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
52356. BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
52357. BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
52358. BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
52359. BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
52360. BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
52361. BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
52362. BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
52363. BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
52364. BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
52365. BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
52366. BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
52367. BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
52368. BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
52369. BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
52370. BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
52371. BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
52372. BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
52373. BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
52374. BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
52375. BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
52376. BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
52377. BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
52378. BIFPLR5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
52379. BIFPLR5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
52380. BIFPLR5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
52381. BIFPLR5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
52382. BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
52383. BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
52384. BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
52385. BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
52386. BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
52387. BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
52388. BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
52389. BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
52390. BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
52391. BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
52392. BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
52393. BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
52394. BIFPLR5_0_PMI_CAP_LIST__CAP_ID_MASK
52395. BIFPLR5_0_PMI_CAP_LIST__CAP_ID__SHIFT
52396. BIFPLR5_0_PMI_CAP_LIST__NEXT_PTR_MASK
52397. BIFPLR5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
52398. BIFPLR5_0_PMI_CAP__AUX_CURRENT_MASK
52399. BIFPLR5_0_PMI_CAP__AUX_CURRENT__SHIFT
52400. BIFPLR5_0_PMI_CAP__D1_SUPPORT_MASK
52401. BIFPLR5_0_PMI_CAP__D1_SUPPORT__SHIFT
52402. BIFPLR5_0_PMI_CAP__D2_SUPPORT_MASK
52403. BIFPLR5_0_PMI_CAP__D2_SUPPORT__SHIFT
52404. BIFPLR5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
52405. BIFPLR5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
52406. BIFPLR5_0_PMI_CAP__PME_CLOCK_MASK
52407. BIFPLR5_0_PMI_CAP__PME_CLOCK__SHIFT
52408. BIFPLR5_0_PMI_CAP__PME_SUPPORT_MASK
52409. BIFPLR5_0_PMI_CAP__PME_SUPPORT__SHIFT
52410. BIFPLR5_0_PMI_CAP__VERSION_MASK
52411. BIFPLR5_0_PMI_CAP__VERSION__SHIFT
52412. BIFPLR5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
52413. BIFPLR5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
52414. BIFPLR5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
52415. BIFPLR5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
52416. BIFPLR5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
52417. BIFPLR5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
52418. BIFPLR5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
52419. BIFPLR5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
52420. BIFPLR5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
52421. BIFPLR5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
52422. BIFPLR5_0_PMI_STATUS_CNTL__PME_EN_MASK
52423. BIFPLR5_0_PMI_STATUS_CNTL__PME_EN__SHIFT
52424. BIFPLR5_0_PMI_STATUS_CNTL__PME_STATUS_MASK
52425. BIFPLR5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
52426. BIFPLR5_0_PMI_STATUS_CNTL__PMI_DATA_MASK
52427. BIFPLR5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
52428. BIFPLR5_0_PMI_STATUS_CNTL__POWER_STATE_MASK
52429. BIFPLR5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
52430. BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
52431. BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
52432. BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
52433. BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
52434. BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
52435. BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
52436. BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
52437. BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
52438. BIFPLR5_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
52439. BIFPLR5_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
52440. BIFPLR5_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
52441. BIFPLR5_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
52442. BIFPLR5_0_PROG_INTERFACE__PROG_INTERFACE_MASK
52443. BIFPLR5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
52444. BIFPLR5_0_REVISION_ID__MAJOR_REV_ID_MASK
52445. BIFPLR5_0_REVISION_ID__MAJOR_REV_ID__SHIFT
52446. BIFPLR5_0_REVISION_ID__MINOR_REV_ID_MASK
52447. BIFPLR5_0_REVISION_ID__MINOR_REV_ID__SHIFT
52448. BIFPLR5_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
52449. BIFPLR5_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
52450. BIFPLR5_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
52451. BIFPLR5_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
52452. BIFPLR5_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK
52453. BIFPLR5_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
52454. BIFPLR5_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
52455. BIFPLR5_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
52456. BIFPLR5_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
52457. BIFPLR5_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
52458. BIFPLR5_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
52459. BIFPLR5_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
52460. BIFPLR5_0_ROOT_STATUS__PME_PENDING_MASK
52461. BIFPLR5_0_ROOT_STATUS__PME_PENDING__SHIFT
52462. BIFPLR5_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK
52463. BIFPLR5_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
52464. BIFPLR5_0_ROOT_STATUS__PME_STATUS_MASK
52465. BIFPLR5_0_ROOT_STATUS__PME_STATUS__SHIFT
52466. BIFPLR5_0_SECONDARY_STATUS__CAP_LIST_MASK
52467. BIFPLR5_0_SECONDARY_STATUS__CAP_LIST__SHIFT
52468. BIFPLR5_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK
52469. BIFPLR5_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
52470. BIFPLR5_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
52471. BIFPLR5_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
52472. BIFPLR5_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
52473. BIFPLR5_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
52474. BIFPLR5_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
52475. BIFPLR5_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
52476. BIFPLR5_0_SECONDARY_STATUS__PCI_66_EN_MASK
52477. BIFPLR5_0_SECONDARY_STATUS__PCI_66_EN__SHIFT
52478. BIFPLR5_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
52479. BIFPLR5_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
52480. BIFPLR5_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
52481. BIFPLR5_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
52482. BIFPLR5_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
52483. BIFPLR5_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
52484. BIFPLR5_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
52485. BIFPLR5_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
52486. BIFPLR5_0_SLOT_CAP2__RESERVED_MASK
52487. BIFPLR5_0_SLOT_CAP2__RESERVED__SHIFT
52488. BIFPLR5_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
52489. BIFPLR5_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
52490. BIFPLR5_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
52491. BIFPLR5_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
52492. BIFPLR5_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
52493. BIFPLR5_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
52494. BIFPLR5_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK
52495. BIFPLR5_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
52496. BIFPLR5_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK
52497. BIFPLR5_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
52498. BIFPLR5_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
52499. BIFPLR5_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
52500. BIFPLR5_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
52501. BIFPLR5_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
52502. BIFPLR5_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
52503. BIFPLR5_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
52504. BIFPLR5_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
52505. BIFPLR5_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
52506. BIFPLR5_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
52507. BIFPLR5_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
52508. BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
52509. BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
52510. BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
52511. BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
52512. BIFPLR5_0_SLOT_CNTL2__RESERVED_MASK
52513. BIFPLR5_0_SLOT_CNTL2__RESERVED__SHIFT
52514. BIFPLR5_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
52515. BIFPLR5_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
52516. BIFPLR5_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
52517. BIFPLR5_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
52518. BIFPLR5_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
52519. BIFPLR5_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
52520. BIFPLR5_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
52521. BIFPLR5_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
52522. BIFPLR5_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
52523. BIFPLR5_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
52524. BIFPLR5_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
52525. BIFPLR5_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
52526. BIFPLR5_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
52527. BIFPLR5_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
52528. BIFPLR5_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
52529. BIFPLR5_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
52530. BIFPLR5_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
52531. BIFPLR5_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
52532. BIFPLR5_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
52533. BIFPLR5_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
52534. BIFPLR5_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
52535. BIFPLR5_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
52536. BIFPLR5_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
52537. BIFPLR5_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
52538. BIFPLR5_0_SLOT_STATUS2__RESERVED_MASK
52539. BIFPLR5_0_SLOT_STATUS2__RESERVED__SHIFT
52540. BIFPLR5_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
52541. BIFPLR5_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
52542. BIFPLR5_0_SLOT_STATUS__COMMAND_COMPLETED_MASK
52543. BIFPLR5_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
52544. BIFPLR5_0_SLOT_STATUS__DL_STATE_CHANGED_MASK
52545. BIFPLR5_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
52546. BIFPLR5_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
52547. BIFPLR5_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
52548. BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
52549. BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
52550. BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK
52551. BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
52552. BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
52553. BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
52554. BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
52555. BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
52556. BIFPLR5_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
52557. BIFPLR5_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
52558. BIFPLR5_0_SSID_CAP_LIST__CAP_ID_MASK
52559. BIFPLR5_0_SSID_CAP_LIST__CAP_ID__SHIFT
52560. BIFPLR5_0_SSID_CAP_LIST__NEXT_PTR_MASK
52561. BIFPLR5_0_SSID_CAP_LIST__NEXT_PTR__SHIFT
52562. BIFPLR5_0_SSID_CAP__SUBSYSTEM_ID_MASK
52563. BIFPLR5_0_SSID_CAP__SUBSYSTEM_ID__SHIFT
52564. BIFPLR5_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
52565. BIFPLR5_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
52566. BIFPLR5_0_STATUS__CAP_LIST_MASK
52567. BIFPLR5_0_STATUS__CAP_LIST__SHIFT
52568. BIFPLR5_0_STATUS__DEVSEL_TIMING_MASK
52569. BIFPLR5_0_STATUS__DEVSEL_TIMING__SHIFT
52570. BIFPLR5_0_STATUS__FAST_BACK_CAPABLE_MASK
52571. BIFPLR5_0_STATUS__FAST_BACK_CAPABLE__SHIFT
52572. BIFPLR5_0_STATUS__INT_STATUS_MASK
52573. BIFPLR5_0_STATUS__INT_STATUS__SHIFT
52574. BIFPLR5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
52575. BIFPLR5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
52576. BIFPLR5_0_STATUS__PARITY_ERROR_DETECTED_MASK
52577. BIFPLR5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
52578. BIFPLR5_0_STATUS__PCI_66_EN_MASK
52579. BIFPLR5_0_STATUS__PCI_66_EN__SHIFT
52580. BIFPLR5_0_STATUS__RECEIVED_MASTER_ABORT_MASK
52581. BIFPLR5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
52582. BIFPLR5_0_STATUS__RECEIVED_TARGET_ABORT_MASK
52583. BIFPLR5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
52584. BIFPLR5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
52585. BIFPLR5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
52586. BIFPLR5_0_STATUS__SIGNAL_TARGET_ABORT_MASK
52587. BIFPLR5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
52588. BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
52589. BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
52590. BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
52591. BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
52592. BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
52593. BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
52594. BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
52595. BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
52596. BIFPLR5_0_SUB_CLASS__SUB_CLASS_MASK
52597. BIFPLR5_0_SUB_CLASS__SUB_CLASS__SHIFT
52598. BIFPLR5_0_VENDOR_ID__VENDOR_ID_MASK
52599. BIFPLR5_0_VENDOR_ID__VENDOR_ID__SHIFT
52600. BIFPLR5_1_BASE_CLASS__BASE_CLASS_MASK
52601. BIFPLR5_1_BASE_CLASS__BASE_CLASS__SHIFT
52602. BIFPLR5_1_BIST__BIST_CAP_MASK
52603. BIFPLR5_1_BIST__BIST_CAP__SHIFT
52604. BIFPLR5_1_BIST__BIST_COMP_MASK
52605. BIFPLR5_1_BIST__BIST_COMP__SHIFT
52606. BIFPLR5_1_BIST__BIST_STRT_MASK
52607. BIFPLR5_1_BIST__BIST_STRT__SHIFT
52608. BIFPLR5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
52609. BIFPLR5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
52610. BIFPLR5_1_CAP_PTR__CAP_PTR_MASK
52611. BIFPLR5_1_CAP_PTR__CAP_PTR__SHIFT
52612. BIFPLR5_1_COMMAND__AD_STEPPING_MASK
52613. BIFPLR5_1_COMMAND__AD_STEPPING__SHIFT
52614. BIFPLR5_1_COMMAND__BUS_MASTER_EN_MASK
52615. BIFPLR5_1_COMMAND__BUS_MASTER_EN__SHIFT
52616. BIFPLR5_1_COMMAND__FAST_B2B_EN_MASK
52617. BIFPLR5_1_COMMAND__FAST_B2B_EN__SHIFT
52618. BIFPLR5_1_COMMAND__INT_DIS_MASK
52619. BIFPLR5_1_COMMAND__INT_DIS__SHIFT
52620. BIFPLR5_1_COMMAND__IO_ACCESS_EN_MASK
52621. BIFPLR5_1_COMMAND__IO_ACCESS_EN__SHIFT
52622. BIFPLR5_1_COMMAND__MEM_ACCESS_EN_MASK
52623. BIFPLR5_1_COMMAND__MEM_ACCESS_EN__SHIFT
52624. BIFPLR5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
52625. BIFPLR5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
52626. BIFPLR5_1_COMMAND__PAL_SNOOP_EN_MASK
52627. BIFPLR5_1_COMMAND__PAL_SNOOP_EN__SHIFT
52628. BIFPLR5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
52629. BIFPLR5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
52630. BIFPLR5_1_COMMAND__SERR_EN_MASK
52631. BIFPLR5_1_COMMAND__SERR_EN__SHIFT
52632. BIFPLR5_1_COMMAND__SPECIAL_CYCLE_EN_MASK
52633. BIFPLR5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
52634. BIFPLR5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
52635. BIFPLR5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
52636. BIFPLR5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
52637. BIFPLR5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
52638. BIFPLR5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
52639. BIFPLR5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
52640. BIFPLR5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
52641. BIFPLR5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
52642. BIFPLR5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
52643. BIFPLR5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
52644. BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
52645. BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
52646. BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
52647. BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
52648. BIFPLR5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
52649. BIFPLR5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
52650. BIFPLR5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
52651. BIFPLR5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
52652. BIFPLR5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
52653. BIFPLR5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
52654. BIFPLR5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
52655. BIFPLR5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
52656. BIFPLR5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
52657. BIFPLR5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
52658. BIFPLR5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
52659. BIFPLR5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
52660. BIFPLR5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
52661. BIFPLR5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
52662. BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
52663. BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
52664. BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
52665. BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
52666. BIFPLR5_1_DEVICE_CAP__EXTENDED_TAG_MASK
52667. BIFPLR5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
52668. BIFPLR5_1_DEVICE_CAP__FLR_CAPABLE_MASK
52669. BIFPLR5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
52670. BIFPLR5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
52671. BIFPLR5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
52672. BIFPLR5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
52673. BIFPLR5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
52674. BIFPLR5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
52675. BIFPLR5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
52676. BIFPLR5_1_DEVICE_CAP__PHANTOM_FUNC_MASK
52677. BIFPLR5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
52678. BIFPLR5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
52679. BIFPLR5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
52680. BIFPLR5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
52681. BIFPLR5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
52682. BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
52683. BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
52684. BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
52685. BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
52686. BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
52687. BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
52688. BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
52689. BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
52690. BIFPLR5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
52691. BIFPLR5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
52692. BIFPLR5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
52693. BIFPLR5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
52694. BIFPLR5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
52695. BIFPLR5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
52696. BIFPLR5_1_DEVICE_CNTL2__LTR_EN_MASK
52697. BIFPLR5_1_DEVICE_CNTL2__LTR_EN__SHIFT
52698. BIFPLR5_1_DEVICE_CNTL2__OBFF_EN_MASK
52699. BIFPLR5_1_DEVICE_CNTL2__OBFF_EN__SHIFT
52700. BIFPLR5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
52701. BIFPLR5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
52702. BIFPLR5_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
52703. BIFPLR5_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
52704. BIFPLR5_1_DEVICE_CNTL__CORR_ERR_EN_MASK
52705. BIFPLR5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
52706. BIFPLR5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
52707. BIFPLR5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
52708. BIFPLR5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
52709. BIFPLR5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
52710. BIFPLR5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
52711. BIFPLR5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
52712. BIFPLR5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
52713. BIFPLR5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
52714. BIFPLR5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
52715. BIFPLR5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
52716. BIFPLR5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
52717. BIFPLR5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
52718. BIFPLR5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
52719. BIFPLR5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
52720. BIFPLR5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
52721. BIFPLR5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
52722. BIFPLR5_1_DEVICE_CNTL__USR_REPORT_EN_MASK
52723. BIFPLR5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
52724. BIFPLR5_1_DEVICE_ID__DEVICE_ID_MASK
52725. BIFPLR5_1_DEVICE_ID__DEVICE_ID__SHIFT
52726. BIFPLR5_1_DEVICE_STATUS2__RESERVED_MASK
52727. BIFPLR5_1_DEVICE_STATUS2__RESERVED__SHIFT
52728. BIFPLR5_1_DEVICE_STATUS__AUX_PWR_MASK
52729. BIFPLR5_1_DEVICE_STATUS__AUX_PWR__SHIFT
52730. BIFPLR5_1_DEVICE_STATUS__CORR_ERR_MASK
52731. BIFPLR5_1_DEVICE_STATUS__CORR_ERR__SHIFT
52732. BIFPLR5_1_DEVICE_STATUS__FATAL_ERR_MASK
52733. BIFPLR5_1_DEVICE_STATUS__FATAL_ERR__SHIFT
52734. BIFPLR5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
52735. BIFPLR5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
52736. BIFPLR5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
52737. BIFPLR5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
52738. BIFPLR5_1_DEVICE_STATUS__USR_DETECTED_MASK
52739. BIFPLR5_1_DEVICE_STATUS__USR_DETECTED__SHIFT
52740. BIFPLR5_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
52741. BIFPLR5_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
52742. BIFPLR5_1_HEADER__DEVICE_TYPE_MASK
52743. BIFPLR5_1_HEADER__DEVICE_TYPE__SHIFT
52744. BIFPLR5_1_HEADER__HEADER_TYPE_MASK
52745. BIFPLR5_1_HEADER__HEADER_TYPE__SHIFT
52746. BIFPLR5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
52747. BIFPLR5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
52748. BIFPLR5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
52749. BIFPLR5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
52750. BIFPLR5_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
52751. BIFPLR5_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
52752. BIFPLR5_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
52753. BIFPLR5_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
52754. BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_MASK
52755. BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
52756. BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
52757. BIFPLR5_1_IO_BASE_LIMIT__IO_BASE__SHIFT
52758. BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_MASK
52759. BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
52760. BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
52761. BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT
52762. BIFPLR5_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
52763. BIFPLR5_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
52764. BIFPLR5_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK
52765. BIFPLR5_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
52766. BIFPLR5_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
52767. BIFPLR5_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
52768. BIFPLR5_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
52769. BIFPLR5_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
52770. BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
52771. BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
52772. BIFPLR5_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK
52773. BIFPLR5_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
52774. BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
52775. BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
52776. BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK
52777. BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
52778. BIFPLR5_1_LATENCY__LATENCY_TIMER_MASK
52779. BIFPLR5_1_LATENCY__LATENCY_TIMER__SHIFT
52780. BIFPLR5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
52781. BIFPLR5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
52782. BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
52783. BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
52784. BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
52785. BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
52786. BIFPLR5_1_LINK_CAP2__RESERVED_MASK
52787. BIFPLR5_1_LINK_CAP2__RESERVED__SHIFT
52788. BIFPLR5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
52789. BIFPLR5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
52790. BIFPLR5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
52791. BIFPLR5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
52792. BIFPLR5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
52793. BIFPLR5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
52794. BIFPLR5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
52795. BIFPLR5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
52796. BIFPLR5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
52797. BIFPLR5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
52798. BIFPLR5_1_LINK_CAP__L1_EXIT_LATENCY_MASK
52799. BIFPLR5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
52800. BIFPLR5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
52801. BIFPLR5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
52802. BIFPLR5_1_LINK_CAP__LINK_SPEED_MASK
52803. BIFPLR5_1_LINK_CAP__LINK_SPEED__SHIFT
52804. BIFPLR5_1_LINK_CAP__LINK_WIDTH_MASK
52805. BIFPLR5_1_LINK_CAP__LINK_WIDTH__SHIFT
52806. BIFPLR5_1_LINK_CAP__PM_SUPPORT_MASK
52807. BIFPLR5_1_LINK_CAP__PM_SUPPORT__SHIFT
52808. BIFPLR5_1_LINK_CAP__PORT_NUMBER_MASK
52809. BIFPLR5_1_LINK_CAP__PORT_NUMBER__SHIFT
52810. BIFPLR5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
52811. BIFPLR5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
52812. BIFPLR5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
52813. BIFPLR5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
52814. BIFPLR5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
52815. BIFPLR5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
52816. BIFPLR5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
52817. BIFPLR5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
52818. BIFPLR5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
52819. BIFPLR5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
52820. BIFPLR5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
52821. BIFPLR5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
52822. BIFPLR5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
52823. BIFPLR5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
52824. BIFPLR5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
52825. BIFPLR5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
52826. BIFPLR5_1_LINK_CNTL2__XMIT_MARGIN_MASK
52827. BIFPLR5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
52828. BIFPLR5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
52829. BIFPLR5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
52830. BIFPLR5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
52831. BIFPLR5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
52832. BIFPLR5_1_LINK_CNTL__EXTENDED_SYNC_MASK
52833. BIFPLR5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
52834. BIFPLR5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
52835. BIFPLR5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
52836. BIFPLR5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
52837. BIFPLR5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
52838. BIFPLR5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
52839. BIFPLR5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
52840. BIFPLR5_1_LINK_CNTL__LINK_DIS_MASK
52841. BIFPLR5_1_LINK_CNTL__LINK_DIS__SHIFT
52842. BIFPLR5_1_LINK_CNTL__PM_CONTROL_MASK
52843. BIFPLR5_1_LINK_CNTL__PM_CONTROL__SHIFT
52844. BIFPLR5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
52845. BIFPLR5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
52846. BIFPLR5_1_LINK_CNTL__RETRAIN_LINK_MASK
52847. BIFPLR5_1_LINK_CNTL__RETRAIN_LINK__SHIFT
52848. BIFPLR5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
52849. BIFPLR5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
52850. BIFPLR5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
52851. BIFPLR5_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
52852. BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
52853. BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
52854. BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
52855. BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
52856. BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
52857. BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
52858. BIFPLR5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
52859. BIFPLR5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
52860. BIFPLR5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
52861. BIFPLR5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
52862. BIFPLR5_1_LINK_STATUS__DL_ACTIVE_MASK
52863. BIFPLR5_1_LINK_STATUS__DL_ACTIVE__SHIFT
52864. BIFPLR5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
52865. BIFPLR5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
52866. BIFPLR5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
52867. BIFPLR5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
52868. BIFPLR5_1_LINK_STATUS__LINK_TRAINING_MASK
52869. BIFPLR5_1_LINK_STATUS__LINK_TRAINING__SHIFT
52870. BIFPLR5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
52871. BIFPLR5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
52872. BIFPLR5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
52873. BIFPLR5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
52874. BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
52875. BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
52876. BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
52877. BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
52878. BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
52879. BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
52880. BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
52881. BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
52882. BIFPLR5_1_MSI_CAP_LIST__CAP_ID_MASK
52883. BIFPLR5_1_MSI_CAP_LIST__CAP_ID__SHIFT
52884. BIFPLR5_1_MSI_CAP_LIST__NEXT_PTR_MASK
52885. BIFPLR5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
52886. BIFPLR5_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
52887. BIFPLR5_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
52888. BIFPLR5_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
52889. BIFPLR5_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
52890. BIFPLR5_1_MSI_MAP_CAP_LIST__CAP_ID_MASK
52891. BIFPLR5_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
52892. BIFPLR5_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
52893. BIFPLR5_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
52894. BIFPLR5_1_MSI_MAP_CAP__CAP_TYPE_MASK
52895. BIFPLR5_1_MSI_MAP_CAP__CAP_TYPE__SHIFT
52896. BIFPLR5_1_MSI_MAP_CAP__EN_MASK
52897. BIFPLR5_1_MSI_MAP_CAP__EN__SHIFT
52898. BIFPLR5_1_MSI_MAP_CAP__FIXD_MASK
52899. BIFPLR5_1_MSI_MAP_CAP__FIXD__SHIFT
52900. BIFPLR5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
52901. BIFPLR5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
52902. BIFPLR5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
52903. BIFPLR5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
52904. BIFPLR5_1_MSI_MSG_CNTL__MSI_64BIT_MASK
52905. BIFPLR5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
52906. BIFPLR5_1_MSI_MSG_CNTL__MSI_EN_MASK
52907. BIFPLR5_1_MSI_MSG_CNTL__MSI_EN__SHIFT
52908. BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
52909. BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
52910. BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
52911. BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
52912. BIFPLR5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
52913. BIFPLR5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
52914. BIFPLR5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
52915. BIFPLR5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
52916. BIFPLR5_1_MSI_MSG_DATA__MSI_DATA_MASK
52917. BIFPLR5_1_MSI_MSG_DATA__MSI_DATA__SHIFT
52918. BIFPLR5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
52919. BIFPLR5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
52920. BIFPLR5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
52921. BIFPLR5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
52922. BIFPLR5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
52923. BIFPLR5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
52924. BIFPLR5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
52925. BIFPLR5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
52926. BIFPLR5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
52927. BIFPLR5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
52928. BIFPLR5_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
52929. BIFPLR5_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
52930. BIFPLR5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
52931. BIFPLR5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
52932. BIFPLR5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
52933. BIFPLR5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
52934. BIFPLR5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
52935. BIFPLR5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
52936. BIFPLR5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
52937. BIFPLR5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
52938. BIFPLR5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
52939. BIFPLR5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
52940. BIFPLR5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
52941. BIFPLR5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
52942. BIFPLR5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
52943. BIFPLR5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
52944. BIFPLR5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
52945. BIFPLR5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
52946. BIFPLR5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
52947. BIFPLR5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
52948. BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
52949. BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
52950. BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
52951. BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
52952. BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
52953. BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
52954. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
52955. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
52956. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
52957. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
52958. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
52959. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
52960. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
52961. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
52962. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
52963. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
52964. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
52965. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
52966. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
52967. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
52968. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
52969. BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
52970. BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
52971. BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
52972. BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
52973. BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
52974. BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
52975. BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
52976. BIFPLR5_1_PCIE_CAP_LIST__CAP_ID_MASK
52977. BIFPLR5_1_PCIE_CAP_LIST__CAP_ID__SHIFT
52978. BIFPLR5_1_PCIE_CAP_LIST__NEXT_PTR_MASK
52979. BIFPLR5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
52980. BIFPLR5_1_PCIE_CAP__DEVICE_TYPE_MASK
52981. BIFPLR5_1_PCIE_CAP__DEVICE_TYPE__SHIFT
52982. BIFPLR5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
52983. BIFPLR5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
52984. BIFPLR5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
52985. BIFPLR5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
52986. BIFPLR5_1_PCIE_CAP__VERSION_MASK
52987. BIFPLR5_1_PCIE_CAP__VERSION__SHIFT
52988. BIFPLR5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
52989. BIFPLR5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
52990. BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
52991. BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
52992. BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
52993. BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
52994. BIFPLR5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
52995. BIFPLR5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
52996. BIFPLR5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
52997. BIFPLR5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
52998. BIFPLR5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
52999. BIFPLR5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
53000. BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
53001. BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
53002. BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
53003. BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
53004. BIFPLR5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
53005. BIFPLR5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
53006. BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
53007. BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
53008. BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
53009. BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
53010. BIFPLR5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
53011. BIFPLR5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
53012. BIFPLR5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
53013. BIFPLR5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
53014. BIFPLR5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
53015. BIFPLR5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
53016. BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
53017. BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
53018. BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
53019. BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
53020. BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
53021. BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
53022. BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
53023. BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
53024. BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
53025. BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
53026. BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
53027. BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
53028. BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
53029. BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
53030. BIFPLR5_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
53031. BIFPLR5_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
53032. BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
53033. BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
53034. BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
53035. BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
53036. BIFPLR5_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
53037. BIFPLR5_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
53038. BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
53039. BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
53040. BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
53041. BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
53042. BIFPLR5_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
53043. BIFPLR5_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
53044. BIFPLR5_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
53045. BIFPLR5_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
53046. BIFPLR5_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
53047. BIFPLR5_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
53048. BIFPLR5_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
53049. BIFPLR5_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
53050. BIFPLR5_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
53051. BIFPLR5_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
53052. BIFPLR5_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
53053. BIFPLR5_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
53054. BIFPLR5_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
53055. BIFPLR5_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
53056. BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
53057. BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
53058. BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
53059. BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
53060. BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
53061. BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
53062. BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
53063. BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
53064. BIFPLR5_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
53065. BIFPLR5_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
53066. BIFPLR5_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
53067. BIFPLR5_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
53068. BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
53069. BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
53070. BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
53071. BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
53072. BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
53073. BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
53074. BIFPLR5_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
53075. BIFPLR5_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
53076. BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
53077. BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
53078. BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
53079. BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
53080. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK
53081. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
53082. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK
53083. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
53084. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK
53085. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
53086. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK
53087. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
53088. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK
53089. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
53090. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK
53091. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
53092. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK
53093. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
53094. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK
53095. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
53096. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK
53097. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
53098. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK
53099. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
53100. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK
53101. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
53102. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK
53103. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
53104. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK
53105. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
53106. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK
53107. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
53108. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK
53109. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
53110. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK
53111. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
53112. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK
53113. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
53114. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK
53115. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
53116. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK
53117. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
53118. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK
53119. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
53120. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK
53121. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
53122. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK
53123. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
53124. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK
53125. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
53126. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK
53127. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
53128. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK
53129. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
53130. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK
53131. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
53132. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK
53133. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
53134. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK
53135. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
53136. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK
53137. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
53138. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK
53139. BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
53140. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK
53141. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
53142. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK
53143. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
53144. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK
53145. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
53146. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK
53147. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
53148. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK
53149. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
53150. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK
53151. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
53152. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK
53153. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
53154. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK
53155. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
53156. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK
53157. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
53158. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK
53159. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
53160. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK
53161. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
53162. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK
53163. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
53164. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK
53165. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
53166. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK
53167. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
53168. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK
53169. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
53170. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK
53171. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
53172. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK
53173. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
53174. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK
53175. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
53176. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK
53177. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
53178. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK
53179. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
53180. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK
53181. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
53182. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK
53183. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
53184. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK
53185. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
53186. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK
53187. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
53188. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK
53189. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
53190. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK
53191. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
53192. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK
53193. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
53194. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK
53195. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
53196. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK
53197. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
53198. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK
53199. BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
53200. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK
53201. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
53202. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK
53203. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
53204. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK
53205. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
53206. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK
53207. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
53208. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK
53209. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
53210. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK
53211. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
53212. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK
53213. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
53214. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK
53215. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
53216. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK
53217. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
53218. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK
53219. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
53220. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK
53221. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
53222. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK
53223. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
53224. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK
53225. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
53226. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK
53227. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
53228. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK
53229. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
53230. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK
53231. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
53232. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK
53233. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
53234. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK
53235. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
53236. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK
53237. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
53238. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK
53239. BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
53240. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK
53241. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
53242. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK
53243. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
53244. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK
53245. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
53246. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK
53247. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
53248. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK
53249. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
53250. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK
53251. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
53252. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK
53253. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
53254. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK
53255. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
53256. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK
53257. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
53258. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK
53259. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
53260. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK
53261. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
53262. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK
53263. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
53264. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK
53265. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
53266. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK
53267. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
53268. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK
53269. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
53270. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK
53271. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
53272. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK
53273. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
53274. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK
53275. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
53276. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK
53277. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
53278. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK
53279. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
53280. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK
53281. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
53282. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK
53283. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
53284. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK
53285. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
53286. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK
53287. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
53288. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK
53289. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
53290. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK
53291. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
53292. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK
53293. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
53294. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK
53295. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
53296. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK
53297. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
53298. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK
53299. BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
53300. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK
53301. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
53302. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK
53303. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
53304. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK
53305. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
53306. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK
53307. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
53308. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK
53309. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
53310. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK
53311. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
53312. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK
53313. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
53314. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK
53315. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
53316. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK
53317. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
53318. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK
53319. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
53320. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK
53321. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
53322. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK
53323. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
53324. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK
53325. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
53326. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK
53327. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
53328. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK
53329. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
53330. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK
53331. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
53332. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK
53333. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
53334. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK
53335. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
53336. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK
53337. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
53338. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK
53339. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
53340. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK
53341. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
53342. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK
53343. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
53344. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK
53345. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
53346. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK
53347. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
53348. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK
53349. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
53350. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK
53351. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
53352. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK
53353. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
53354. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK
53355. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
53356. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK
53357. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
53358. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK
53359. BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
53360. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK
53361. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
53362. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK
53363. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
53364. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK
53365. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
53366. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK
53367. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
53368. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK
53369. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
53370. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK
53371. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
53372. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK
53373. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
53374. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK
53375. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
53376. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK
53377. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
53378. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK
53379. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
53380. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK
53381. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
53382. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK
53383. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
53384. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK
53385. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
53386. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK
53387. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
53388. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK
53389. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
53390. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK
53391. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
53392. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK
53393. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
53394. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK
53395. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
53396. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK
53397. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
53398. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK
53399. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
53400. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK
53401. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
53402. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK
53403. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
53404. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK
53405. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
53406. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK
53407. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
53408. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK
53409. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
53410. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK
53411. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
53412. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK
53413. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
53414. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK
53415. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
53416. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK
53417. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
53418. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK
53419. BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
53420. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK
53421. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
53422. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK
53423. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
53424. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK
53425. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
53426. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK
53427. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
53428. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK
53429. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
53430. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK
53431. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
53432. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK
53433. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
53434. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK
53435. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
53436. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK
53437. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
53438. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK
53439. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
53440. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK
53441. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
53442. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK
53443. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
53444. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK
53445. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
53446. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK
53447. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
53448. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK
53449. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
53450. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK
53451. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
53452. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK
53453. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
53454. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK
53455. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
53456. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK
53457. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
53458. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK
53459. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
53460. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK
53461. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
53462. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK
53463. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
53464. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK
53465. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
53466. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK
53467. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
53468. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK
53469. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
53470. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK
53471. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
53472. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK
53473. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
53474. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK
53475. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
53476. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK
53477. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
53478. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK
53479. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
53480. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK
53481. BIFPLR5_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
53482. BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK
53483. BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
53484. BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK
53485. BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
53486. BIFPLR5_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
53487. BIFPLR5_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
53488. BIFPLR5_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK
53489. BIFPLR5_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
53490. BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
53491. BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
53492. BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
53493. BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
53494. BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
53495. BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
53496. BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
53497. BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
53498. BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
53499. BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
53500. BIFPLR5_1_PCIE_ESM_HEADER_2__CAP_ID_MASK
53501. BIFPLR5_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
53502. BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
53503. BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
53504. BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
53505. BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
53506. BIFPLR5_1_PCIE_HDR_LOG0__TLP_HDR_MASK
53507. BIFPLR5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
53508. BIFPLR5_1_PCIE_HDR_LOG1__TLP_HDR_MASK
53509. BIFPLR5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
53510. BIFPLR5_1_PCIE_HDR_LOG2__TLP_HDR_MASK
53511. BIFPLR5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
53512. BIFPLR5_1_PCIE_HDR_LOG3__TLP_HDR_MASK
53513. BIFPLR5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
53514. BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
53515. BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
53516. BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
53517. BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
53518. BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
53519. BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
53520. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
53521. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
53522. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
53523. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
53524. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
53525. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
53526. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
53527. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
53528. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
53529. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
53530. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
53531. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
53532. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
53533. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
53534. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
53535. BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
53536. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
53537. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
53538. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
53539. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
53540. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
53541. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
53542. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
53543. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
53544. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
53545. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
53546. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
53547. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
53548. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
53549. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
53550. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
53551. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
53552. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
53553. BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
53554. BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53555. BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53556. BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53557. BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53558. BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53559. BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53560. BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53561. BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53562. BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53563. BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53564. BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53565. BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53566. BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53567. BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53568. BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53569. BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53570. BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53571. BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53572. BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53573. BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53574. BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53575. BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53576. BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53577. BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53578. BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53579. BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53580. BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53581. BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53582. BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53583. BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53584. BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53585. BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53586. BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53587. BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53588. BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53589. BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53590. BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53591. BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53592. BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53593. BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53594. BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53595. BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53596. BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53597. BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53598. BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53599. BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53600. BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53601. BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53602. BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53603. BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53604. BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53605. BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53606. BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53607. BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53608. BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53609. BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53610. BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53611. BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53612. BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53613. BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53614. BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53615. BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53616. BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53617. BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53618. BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53619. BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53620. BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53621. BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53622. BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53623. BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53624. BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53625. BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53626. BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53627. BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53628. BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53629. BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53630. BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53631. BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53632. BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53633. BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53634. BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53635. BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53636. BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53637. BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53638. BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53639. BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53640. BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53641. BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53642. BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53643. BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53644. BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53645. BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53646. BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53647. BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53648. BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53649. BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53650. BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53651. BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53652. BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53653. BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53654. BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53655. BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53656. BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53657. BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53658. BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53659. BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53660. BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53661. BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53662. BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53663. BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53664. BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53665. BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53666. BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53667. BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53668. BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53669. BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53670. BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53671. BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53672. BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53673. BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53674. BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
53675. BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
53676. BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
53677. BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
53678. BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
53679. BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
53680. BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
53681. BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
53682. BIFPLR5_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
53683. BIFPLR5_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
53684. BIFPLR5_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
53685. BIFPLR5_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
53686. BIFPLR5_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
53687. BIFPLR5_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
53688. BIFPLR5_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
53689. BIFPLR5_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
53690. BIFPLR5_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
53691. BIFPLR5_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
53692. BIFPLR5_1_PCIE_LINK_CNTL3__RESERVED_MASK
53693. BIFPLR5_1_PCIE_LINK_CNTL3__RESERVED__SHIFT
53694. BIFPLR5_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
53695. BIFPLR5_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
53696. BIFPLR5_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
53697. BIFPLR5_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
53698. BIFPLR5_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
53699. BIFPLR5_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
53700. BIFPLR5_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
53701. BIFPLR5_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
53702. BIFPLR5_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
53703. BIFPLR5_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
53704. BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
53705. BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
53706. BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
53707. BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
53708. BIFPLR5_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
53709. BIFPLR5_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
53710. BIFPLR5_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK
53711. BIFPLR5_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
53712. BIFPLR5_1_PCIE_MC_CNTL__MC_ENABLE_MASK
53713. BIFPLR5_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT
53714. BIFPLR5_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
53715. BIFPLR5_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
53716. BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
53717. BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
53718. BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
53719. BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
53720. BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
53721. BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
53722. BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
53723. BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
53724. BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
53725. BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
53726. BIFPLR5_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
53727. BIFPLR5_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
53728. BIFPLR5_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
53729. BIFPLR5_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
53730. BIFPLR5_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
53731. BIFPLR5_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
53732. BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
53733. BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
53734. BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
53735. BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
53736. BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
53737. BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
53738. BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
53739. BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
53740. BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
53741. BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
53742. BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
53743. BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
53744. BIFPLR5_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
53745. BIFPLR5_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
53746. BIFPLR5_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
53747. BIFPLR5_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
53748. BIFPLR5_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
53749. BIFPLR5_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
53750. BIFPLR5_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
53751. BIFPLR5_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
53752. BIFPLR5_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
53753. BIFPLR5_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
53754. BIFPLR5_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
53755. BIFPLR5_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
53756. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
53757. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
53758. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
53759. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
53760. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
53761. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
53762. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
53763. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
53764. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
53765. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
53766. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
53767. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
53768. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
53769. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
53770. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
53771. BIFPLR5_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
53772. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
53773. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
53774. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
53775. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
53776. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
53777. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
53778. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
53779. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
53780. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
53781. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
53782. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
53783. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
53784. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
53785. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
53786. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
53787. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
53788. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
53789. BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
53790. BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
53791. BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
53792. BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
53793. BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
53794. BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
53795. BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
53796. BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
53797. BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
53798. BIFPLR5_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
53799. BIFPLR5_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
53800. BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
53801. BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
53802. BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK
53803. BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
53804. BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
53805. BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
53806. BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
53807. BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
53808. BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CTO_MASK
53809. BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
53810. BIFPLR5_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
53811. BIFPLR5_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
53812. BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
53813. BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
53814. BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK
53815. BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
53816. BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
53817. BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
53818. BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
53819. BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
53820. BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
53821. BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
53822. BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
53823. BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
53824. BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
53825. BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
53826. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
53827. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
53828. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
53829. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
53830. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
53831. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
53832. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
53833. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
53834. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
53835. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
53836. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
53837. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
53838. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
53839. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
53840. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
53841. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
53842. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
53843. BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
53844. BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
53845. BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
53846. BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
53847. BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
53848. BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
53849. BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
53850. BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
53851. BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
53852. BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK
53853. BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
53854. BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
53855. BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
53856. BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
53857. BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
53858. BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
53859. BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
53860. BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
53861. BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
53862. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
53863. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
53864. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
53865. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
53866. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
53867. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
53868. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
53869. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
53870. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
53871. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
53872. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
53873. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
53874. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
53875. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
53876. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
53877. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
53878. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
53879. BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
53880. BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
53881. BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
53882. BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
53883. BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
53884. BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
53885. BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
53886. BIFPLR5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
53887. BIFPLR5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
53888. BIFPLR5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
53889. BIFPLR5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
53890. BIFPLR5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
53891. BIFPLR5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
53892. BIFPLR5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
53893. BIFPLR5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
53894. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
53895. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
53896. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
53897. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
53898. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
53899. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
53900. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
53901. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
53902. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
53903. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
53904. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
53905. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
53906. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
53907. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
53908. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
53909. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
53910. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
53911. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
53912. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
53913. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
53914. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
53915. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
53916. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
53917. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
53918. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
53919. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
53920. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
53921. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
53922. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
53923. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
53924. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
53925. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
53926. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
53927. BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
53928. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
53929. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
53930. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
53931. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
53932. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
53933. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
53934. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
53935. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
53936. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
53937. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
53938. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
53939. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
53940. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
53941. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
53942. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
53943. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
53944. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
53945. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
53946. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
53947. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
53948. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
53949. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
53950. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
53951. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
53952. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
53953. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
53954. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
53955. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
53956. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
53957. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
53958. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
53959. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
53960. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
53961. BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
53962. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
53963. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
53964. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
53965. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
53966. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
53967. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
53968. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
53969. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
53970. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
53971. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
53972. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
53973. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
53974. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
53975. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
53976. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
53977. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
53978. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
53979. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
53980. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
53981. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
53982. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
53983. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
53984. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
53985. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
53986. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
53987. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
53988. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
53989. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
53990. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
53991. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
53992. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
53993. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
53994. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
53995. BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
53996. BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
53997. BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
53998. BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
53999. BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
54000. BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
54001. BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
54002. BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
54003. BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
54004. BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
54005. BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
54006. BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
54007. BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
54008. BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
54009. BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
54010. BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
54011. BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
54012. BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
54013. BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
54014. BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
54015. BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
54016. BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
54017. BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
54018. BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
54019. BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
54020. BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
54021. BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
54022. BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
54023. BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
54024. BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
54025. BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
54026. BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
54027. BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
54028. BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
54029. BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
54030. BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
54031. BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
54032. BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
54033. BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
54034. BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
54035. BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
54036. BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
54037. BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
54038. BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
54039. BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
54040. BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
54041. BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
54042. BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
54043. BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
54044. BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
54045. BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
54046. BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
54047. BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
54048. BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
54049. BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
54050. BIFPLR5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
54051. BIFPLR5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
54052. BIFPLR5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
54053. BIFPLR5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
54054. BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
54055. BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
54056. BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
54057. BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
54058. BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
54059. BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
54060. BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
54061. BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
54062. BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
54063. BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
54064. BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
54065. BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
54066. BIFPLR5_1_PMI_CAP_LIST__CAP_ID_MASK
54067. BIFPLR5_1_PMI_CAP_LIST__CAP_ID__SHIFT
54068. BIFPLR5_1_PMI_CAP_LIST__NEXT_PTR_MASK
54069. BIFPLR5_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
54070. BIFPLR5_1_PMI_CAP__AUX_CURRENT_MASK
54071. BIFPLR5_1_PMI_CAP__AUX_CURRENT__SHIFT
54072. BIFPLR5_1_PMI_CAP__D1_SUPPORT_MASK
54073. BIFPLR5_1_PMI_CAP__D1_SUPPORT__SHIFT
54074. BIFPLR5_1_PMI_CAP__D2_SUPPORT_MASK
54075. BIFPLR5_1_PMI_CAP__D2_SUPPORT__SHIFT
54076. BIFPLR5_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
54077. BIFPLR5_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
54078. BIFPLR5_1_PMI_CAP__PME_CLOCK_MASK
54079. BIFPLR5_1_PMI_CAP__PME_CLOCK__SHIFT
54080. BIFPLR5_1_PMI_CAP__PME_SUPPORT_MASK
54081. BIFPLR5_1_PMI_CAP__PME_SUPPORT__SHIFT
54082. BIFPLR5_1_PMI_CAP__VERSION_MASK
54083. BIFPLR5_1_PMI_CAP__VERSION__SHIFT
54084. BIFPLR5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
54085. BIFPLR5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
54086. BIFPLR5_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
54087. BIFPLR5_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
54088. BIFPLR5_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
54089. BIFPLR5_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
54090. BIFPLR5_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
54091. BIFPLR5_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
54092. BIFPLR5_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
54093. BIFPLR5_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
54094. BIFPLR5_1_PMI_STATUS_CNTL__PME_EN_MASK
54095. BIFPLR5_1_PMI_STATUS_CNTL__PME_EN__SHIFT
54096. BIFPLR5_1_PMI_STATUS_CNTL__PME_STATUS_MASK
54097. BIFPLR5_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
54098. BIFPLR5_1_PMI_STATUS_CNTL__PMI_DATA_MASK
54099. BIFPLR5_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
54100. BIFPLR5_1_PMI_STATUS_CNTL__POWER_STATE_MASK
54101. BIFPLR5_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
54102. BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
54103. BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
54104. BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
54105. BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
54106. BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
54107. BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
54108. BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
54109. BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
54110. BIFPLR5_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
54111. BIFPLR5_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
54112. BIFPLR5_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
54113. BIFPLR5_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
54114. BIFPLR5_1_PROG_INTERFACE__PROG_INTERFACE_MASK
54115. BIFPLR5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
54116. BIFPLR5_1_REVISION_ID__MAJOR_REV_ID_MASK
54117. BIFPLR5_1_REVISION_ID__MAJOR_REV_ID__SHIFT
54118. BIFPLR5_1_REVISION_ID__MINOR_REV_ID_MASK
54119. BIFPLR5_1_REVISION_ID__MINOR_REV_ID__SHIFT
54120. BIFPLR5_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
54121. BIFPLR5_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
54122. BIFPLR5_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
54123. BIFPLR5_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
54124. BIFPLR5_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK
54125. BIFPLR5_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
54126. BIFPLR5_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
54127. BIFPLR5_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
54128. BIFPLR5_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
54129. BIFPLR5_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
54130. BIFPLR5_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
54131. BIFPLR5_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
54132. BIFPLR5_1_ROOT_STATUS__PME_PENDING_MASK
54133. BIFPLR5_1_ROOT_STATUS__PME_PENDING__SHIFT
54134. BIFPLR5_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK
54135. BIFPLR5_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
54136. BIFPLR5_1_ROOT_STATUS__PME_STATUS_MASK
54137. BIFPLR5_1_ROOT_STATUS__PME_STATUS__SHIFT
54138. BIFPLR5_1_SECONDARY_STATUS__CAP_LIST_MASK
54139. BIFPLR5_1_SECONDARY_STATUS__CAP_LIST__SHIFT
54140. BIFPLR5_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK
54141. BIFPLR5_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
54142. BIFPLR5_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
54143. BIFPLR5_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
54144. BIFPLR5_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
54145. BIFPLR5_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
54146. BIFPLR5_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
54147. BIFPLR5_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
54148. BIFPLR5_1_SECONDARY_STATUS__PCI_66_EN_MASK
54149. BIFPLR5_1_SECONDARY_STATUS__PCI_66_EN__SHIFT
54150. BIFPLR5_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
54151. BIFPLR5_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
54152. BIFPLR5_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
54153. BIFPLR5_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
54154. BIFPLR5_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
54155. BIFPLR5_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
54156. BIFPLR5_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
54157. BIFPLR5_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
54158. BIFPLR5_1_SLOT_CAP2__RESERVED_MASK
54159. BIFPLR5_1_SLOT_CAP2__RESERVED__SHIFT
54160. BIFPLR5_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
54161. BIFPLR5_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
54162. BIFPLR5_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
54163. BIFPLR5_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
54164. BIFPLR5_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
54165. BIFPLR5_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
54166. BIFPLR5_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK
54167. BIFPLR5_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
54168. BIFPLR5_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK
54169. BIFPLR5_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
54170. BIFPLR5_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
54171. BIFPLR5_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
54172. BIFPLR5_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
54173. BIFPLR5_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
54174. BIFPLR5_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
54175. BIFPLR5_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
54176. BIFPLR5_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
54177. BIFPLR5_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
54178. BIFPLR5_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
54179. BIFPLR5_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
54180. BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
54181. BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
54182. BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
54183. BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
54184. BIFPLR5_1_SLOT_CNTL2__RESERVED_MASK
54185. BIFPLR5_1_SLOT_CNTL2__RESERVED__SHIFT
54186. BIFPLR5_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
54187. BIFPLR5_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
54188. BIFPLR5_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
54189. BIFPLR5_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
54190. BIFPLR5_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
54191. BIFPLR5_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
54192. BIFPLR5_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
54193. BIFPLR5_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
54194. BIFPLR5_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
54195. BIFPLR5_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
54196. BIFPLR5_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
54197. BIFPLR5_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
54198. BIFPLR5_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
54199. BIFPLR5_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
54200. BIFPLR5_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
54201. BIFPLR5_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
54202. BIFPLR5_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
54203. BIFPLR5_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
54204. BIFPLR5_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
54205. BIFPLR5_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
54206. BIFPLR5_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
54207. BIFPLR5_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
54208. BIFPLR5_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
54209. BIFPLR5_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
54210. BIFPLR5_1_SLOT_STATUS2__RESERVED_MASK
54211. BIFPLR5_1_SLOT_STATUS2__RESERVED__SHIFT
54212. BIFPLR5_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
54213. BIFPLR5_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
54214. BIFPLR5_1_SLOT_STATUS__COMMAND_COMPLETED_MASK
54215. BIFPLR5_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
54216. BIFPLR5_1_SLOT_STATUS__DL_STATE_CHANGED_MASK
54217. BIFPLR5_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
54218. BIFPLR5_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
54219. BIFPLR5_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
54220. BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
54221. BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
54222. BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK
54223. BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
54224. BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
54225. BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
54226. BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
54227. BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
54228. BIFPLR5_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
54229. BIFPLR5_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
54230. BIFPLR5_1_SSID_CAP_LIST__CAP_ID_MASK
54231. BIFPLR5_1_SSID_CAP_LIST__CAP_ID__SHIFT
54232. BIFPLR5_1_SSID_CAP_LIST__NEXT_PTR_MASK
54233. BIFPLR5_1_SSID_CAP_LIST__NEXT_PTR__SHIFT
54234. BIFPLR5_1_SSID_CAP__SUBSYSTEM_ID_MASK
54235. BIFPLR5_1_SSID_CAP__SUBSYSTEM_ID__SHIFT
54236. BIFPLR5_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
54237. BIFPLR5_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
54238. BIFPLR5_1_STATUS__CAP_LIST_MASK
54239. BIFPLR5_1_STATUS__CAP_LIST__SHIFT
54240. BIFPLR5_1_STATUS__DEVSEL_TIMING_MASK
54241. BIFPLR5_1_STATUS__DEVSEL_TIMING__SHIFT
54242. BIFPLR5_1_STATUS__FAST_BACK_CAPABLE_MASK
54243. BIFPLR5_1_STATUS__FAST_BACK_CAPABLE__SHIFT
54244. BIFPLR5_1_STATUS__INT_STATUS_MASK
54245. BIFPLR5_1_STATUS__INT_STATUS__SHIFT
54246. BIFPLR5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
54247. BIFPLR5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
54248. BIFPLR5_1_STATUS__PARITY_ERROR_DETECTED_MASK
54249. BIFPLR5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
54250. BIFPLR5_1_STATUS__PCI_66_EN_MASK
54251. BIFPLR5_1_STATUS__PCI_66_EN__SHIFT
54252. BIFPLR5_1_STATUS__RECEIVED_MASTER_ABORT_MASK
54253. BIFPLR5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
54254. BIFPLR5_1_STATUS__RECEIVED_TARGET_ABORT_MASK
54255. BIFPLR5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
54256. BIFPLR5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
54257. BIFPLR5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
54258. BIFPLR5_1_STATUS__SIGNAL_TARGET_ABORT_MASK
54259. BIFPLR5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
54260. BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
54261. BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
54262. BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
54263. BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
54264. BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
54265. BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
54266. BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
54267. BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
54268. BIFPLR5_1_SUB_CLASS__SUB_CLASS_MASK
54269. BIFPLR5_1_SUB_CLASS__SUB_CLASS__SHIFT
54270. BIFPLR5_1_VENDOR_ID__VENDOR_ID_MASK
54271. BIFPLR5_1_VENDOR_ID__VENDOR_ID__SHIFT
54272. BIFPLR5_2_BASE_CLASS__BASE_CLASS_MASK
54273. BIFPLR5_2_BASE_CLASS__BASE_CLASS__SHIFT
54274. BIFPLR5_2_BIST__BIST_CAP_MASK
54275. BIFPLR5_2_BIST__BIST_CAP__SHIFT
54276. BIFPLR5_2_BIST__BIST_COMP_MASK
54277. BIFPLR5_2_BIST__BIST_COMP__SHIFT
54278. BIFPLR5_2_BIST__BIST_STRT_MASK
54279. BIFPLR5_2_BIST__BIST_STRT__SHIFT
54280. BIFPLR5_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
54281. BIFPLR5_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
54282. BIFPLR5_2_CAP_PTR__CAP_PTR_MASK
54283. BIFPLR5_2_CAP_PTR__CAP_PTR__SHIFT
54284. BIFPLR5_2_COMMAND__AD_STEPPING_MASK
54285. BIFPLR5_2_COMMAND__AD_STEPPING__SHIFT
54286. BIFPLR5_2_COMMAND__BUS_MASTER_EN_MASK
54287. BIFPLR5_2_COMMAND__BUS_MASTER_EN__SHIFT
54288. BIFPLR5_2_COMMAND__FAST_B2B_EN_MASK
54289. BIFPLR5_2_COMMAND__FAST_B2B_EN__SHIFT
54290. BIFPLR5_2_COMMAND__INT_DIS_MASK
54291. BIFPLR5_2_COMMAND__INT_DIS__SHIFT
54292. BIFPLR5_2_COMMAND__IO_ACCESS_EN_MASK
54293. BIFPLR5_2_COMMAND__IO_ACCESS_EN__SHIFT
54294. BIFPLR5_2_COMMAND__MEM_ACCESS_EN_MASK
54295. BIFPLR5_2_COMMAND__MEM_ACCESS_EN__SHIFT
54296. BIFPLR5_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
54297. BIFPLR5_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
54298. BIFPLR5_2_COMMAND__PAL_SNOOP_EN_MASK
54299. BIFPLR5_2_COMMAND__PAL_SNOOP_EN__SHIFT
54300. BIFPLR5_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
54301. BIFPLR5_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
54302. BIFPLR5_2_COMMAND__SERR_EN_MASK
54303. BIFPLR5_2_COMMAND__SERR_EN__SHIFT
54304. BIFPLR5_2_COMMAND__SPECIAL_CYCLE_EN_MASK
54305. BIFPLR5_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
54306. BIFPLR5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
54307. BIFPLR5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
54308. BIFPLR5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
54309. BIFPLR5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
54310. BIFPLR5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
54311. BIFPLR5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
54312. BIFPLR5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
54313. BIFPLR5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
54314. BIFPLR5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
54315. BIFPLR5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
54316. BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
54317. BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
54318. BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
54319. BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
54320. BIFPLR5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
54321. BIFPLR5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
54322. BIFPLR5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
54323. BIFPLR5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
54324. BIFPLR5_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
54325. BIFPLR5_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
54326. BIFPLR5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
54327. BIFPLR5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
54328. BIFPLR5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
54329. BIFPLR5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
54330. BIFPLR5_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
54331. BIFPLR5_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
54332. BIFPLR5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
54333. BIFPLR5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
54334. BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
54335. BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
54336. BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
54337. BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
54338. BIFPLR5_2_DEVICE_CAP__EXTENDED_TAG_MASK
54339. BIFPLR5_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
54340. BIFPLR5_2_DEVICE_CAP__FLR_CAPABLE_MASK
54341. BIFPLR5_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
54342. BIFPLR5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
54343. BIFPLR5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
54344. BIFPLR5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
54345. BIFPLR5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
54346. BIFPLR5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
54347. BIFPLR5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
54348. BIFPLR5_2_DEVICE_CAP__PHANTOM_FUNC_MASK
54349. BIFPLR5_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
54350. BIFPLR5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
54351. BIFPLR5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
54352. BIFPLR5_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
54353. BIFPLR5_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
54354. BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
54355. BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
54356. BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
54357. BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
54358. BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
54359. BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
54360. BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
54361. BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
54362. BIFPLR5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
54363. BIFPLR5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
54364. BIFPLR5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
54365. BIFPLR5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
54366. BIFPLR5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
54367. BIFPLR5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
54368. BIFPLR5_2_DEVICE_CNTL2__LTR_EN_MASK
54369. BIFPLR5_2_DEVICE_CNTL2__LTR_EN__SHIFT
54370. BIFPLR5_2_DEVICE_CNTL2__OBFF_EN_MASK
54371. BIFPLR5_2_DEVICE_CNTL2__OBFF_EN__SHIFT
54372. BIFPLR5_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
54373. BIFPLR5_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
54374. BIFPLR5_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
54375. BIFPLR5_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
54376. BIFPLR5_2_DEVICE_CNTL__CORR_ERR_EN_MASK
54377. BIFPLR5_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
54378. BIFPLR5_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
54379. BIFPLR5_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
54380. BIFPLR5_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
54381. BIFPLR5_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
54382. BIFPLR5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
54383. BIFPLR5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
54384. BIFPLR5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
54385. BIFPLR5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
54386. BIFPLR5_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
54387. BIFPLR5_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
54388. BIFPLR5_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
54389. BIFPLR5_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
54390. BIFPLR5_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
54391. BIFPLR5_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
54392. BIFPLR5_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
54393. BIFPLR5_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
54394. BIFPLR5_2_DEVICE_CNTL__USR_REPORT_EN_MASK
54395. BIFPLR5_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
54396. BIFPLR5_2_DEVICE_ID__DEVICE_ID_MASK
54397. BIFPLR5_2_DEVICE_ID__DEVICE_ID__SHIFT
54398. BIFPLR5_2_DEVICE_STATUS2__RESERVED_MASK
54399. BIFPLR5_2_DEVICE_STATUS2__RESERVED__SHIFT
54400. BIFPLR5_2_DEVICE_STATUS__AUX_PWR_MASK
54401. BIFPLR5_2_DEVICE_STATUS__AUX_PWR__SHIFT
54402. BIFPLR5_2_DEVICE_STATUS__CORR_ERR_MASK
54403. BIFPLR5_2_DEVICE_STATUS__CORR_ERR__SHIFT
54404. BIFPLR5_2_DEVICE_STATUS__FATAL_ERR_MASK
54405. BIFPLR5_2_DEVICE_STATUS__FATAL_ERR__SHIFT
54406. BIFPLR5_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
54407. BIFPLR5_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
54408. BIFPLR5_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
54409. BIFPLR5_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
54410. BIFPLR5_2_DEVICE_STATUS__USR_DETECTED_MASK
54411. BIFPLR5_2_DEVICE_STATUS__USR_DETECTED__SHIFT
54412. BIFPLR5_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
54413. BIFPLR5_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
54414. BIFPLR5_2_HEADER__DEVICE_TYPE_MASK
54415. BIFPLR5_2_HEADER__DEVICE_TYPE__SHIFT
54416. BIFPLR5_2_HEADER__HEADER_TYPE_MASK
54417. BIFPLR5_2_HEADER__HEADER_TYPE__SHIFT
54418. BIFPLR5_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
54419. BIFPLR5_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
54420. BIFPLR5_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
54421. BIFPLR5_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
54422. BIFPLR5_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
54423. BIFPLR5_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
54424. BIFPLR5_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
54425. BIFPLR5_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
54426. BIFPLR5_2_IO_BASE_LIMIT__IO_BASE_MASK
54427. BIFPLR5_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
54428. BIFPLR5_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
54429. BIFPLR5_2_IO_BASE_LIMIT__IO_BASE__SHIFT
54430. BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT_MASK
54431. BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
54432. BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
54433. BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT
54434. BIFPLR5_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
54435. BIFPLR5_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
54436. BIFPLR5_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK
54437. BIFPLR5_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
54438. BIFPLR5_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
54439. BIFPLR5_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
54440. BIFPLR5_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
54441. BIFPLR5_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
54442. BIFPLR5_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
54443. BIFPLR5_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
54444. BIFPLR5_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK
54445. BIFPLR5_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
54446. BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
54447. BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
54448. BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK
54449. BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
54450. BIFPLR5_2_LATENCY__LATENCY_TIMER_MASK
54451. BIFPLR5_2_LATENCY__LATENCY_TIMER__SHIFT
54452. BIFPLR5_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
54453. BIFPLR5_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
54454. BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
54455. BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
54456. BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
54457. BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
54458. BIFPLR5_2_LINK_CAP2__RESERVED_MASK
54459. BIFPLR5_2_LINK_CAP2__RESERVED__SHIFT
54460. BIFPLR5_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
54461. BIFPLR5_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
54462. BIFPLR5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
54463. BIFPLR5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
54464. BIFPLR5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
54465. BIFPLR5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
54466. BIFPLR5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
54467. BIFPLR5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
54468. BIFPLR5_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
54469. BIFPLR5_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
54470. BIFPLR5_2_LINK_CAP__L1_EXIT_LATENCY_MASK
54471. BIFPLR5_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
54472. BIFPLR5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
54473. BIFPLR5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
54474. BIFPLR5_2_LINK_CAP__LINK_SPEED_MASK
54475. BIFPLR5_2_LINK_CAP__LINK_SPEED__SHIFT
54476. BIFPLR5_2_LINK_CAP__LINK_WIDTH_MASK
54477. BIFPLR5_2_LINK_CAP__LINK_WIDTH__SHIFT
54478. BIFPLR5_2_LINK_CAP__PM_SUPPORT_MASK
54479. BIFPLR5_2_LINK_CAP__PM_SUPPORT__SHIFT
54480. BIFPLR5_2_LINK_CAP__PORT_NUMBER_MASK
54481. BIFPLR5_2_LINK_CAP__PORT_NUMBER__SHIFT
54482. BIFPLR5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
54483. BIFPLR5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
54484. BIFPLR5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
54485. BIFPLR5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
54486. BIFPLR5_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
54487. BIFPLR5_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
54488. BIFPLR5_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
54489. BIFPLR5_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
54490. BIFPLR5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
54491. BIFPLR5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
54492. BIFPLR5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
54493. BIFPLR5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
54494. BIFPLR5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
54495. BIFPLR5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
54496. BIFPLR5_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
54497. BIFPLR5_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
54498. BIFPLR5_2_LINK_CNTL2__XMIT_MARGIN_MASK
54499. BIFPLR5_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
54500. BIFPLR5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
54501. BIFPLR5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
54502. BIFPLR5_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
54503. BIFPLR5_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
54504. BIFPLR5_2_LINK_CNTL__EXTENDED_SYNC_MASK
54505. BIFPLR5_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
54506. BIFPLR5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
54507. BIFPLR5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
54508. BIFPLR5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
54509. BIFPLR5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
54510. BIFPLR5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
54511. BIFPLR5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
54512. BIFPLR5_2_LINK_CNTL__LINK_DIS_MASK
54513. BIFPLR5_2_LINK_CNTL__LINK_DIS__SHIFT
54514. BIFPLR5_2_LINK_CNTL__PM_CONTROL_MASK
54515. BIFPLR5_2_LINK_CNTL__PM_CONTROL__SHIFT
54516. BIFPLR5_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
54517. BIFPLR5_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
54518. BIFPLR5_2_LINK_CNTL__RETRAIN_LINK_MASK
54519. BIFPLR5_2_LINK_CNTL__RETRAIN_LINK__SHIFT
54520. BIFPLR5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
54521. BIFPLR5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
54522. BIFPLR5_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
54523. BIFPLR5_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
54524. BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
54525. BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
54526. BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
54527. BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
54528. BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
54529. BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
54530. BIFPLR5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
54531. BIFPLR5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
54532. BIFPLR5_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
54533. BIFPLR5_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
54534. BIFPLR5_2_LINK_STATUS__DL_ACTIVE_MASK
54535. BIFPLR5_2_LINK_STATUS__DL_ACTIVE__SHIFT
54536. BIFPLR5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
54537. BIFPLR5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
54538. BIFPLR5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
54539. BIFPLR5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
54540. BIFPLR5_2_LINK_STATUS__LINK_TRAINING_MASK
54541. BIFPLR5_2_LINK_STATUS__LINK_TRAINING__SHIFT
54542. BIFPLR5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
54543. BIFPLR5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
54544. BIFPLR5_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
54545. BIFPLR5_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
54546. BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
54547. BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
54548. BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
54549. BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
54550. BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
54551. BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
54552. BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
54553. BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
54554. BIFPLR5_2_MSI_CAP_LIST__CAP_ID_MASK
54555. BIFPLR5_2_MSI_CAP_LIST__CAP_ID__SHIFT
54556. BIFPLR5_2_MSI_CAP_LIST__NEXT_PTR_MASK
54557. BIFPLR5_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
54558. BIFPLR5_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
54559. BIFPLR5_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
54560. BIFPLR5_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
54561. BIFPLR5_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
54562. BIFPLR5_2_MSI_MAP_CAP_LIST__CAP_ID_MASK
54563. BIFPLR5_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
54564. BIFPLR5_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
54565. BIFPLR5_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
54566. BIFPLR5_2_MSI_MAP_CAP__CAP_TYPE_MASK
54567. BIFPLR5_2_MSI_MAP_CAP__CAP_TYPE__SHIFT
54568. BIFPLR5_2_MSI_MAP_CAP__EN_MASK
54569. BIFPLR5_2_MSI_MAP_CAP__EN__SHIFT
54570. BIFPLR5_2_MSI_MAP_CAP__FIXD_MASK
54571. BIFPLR5_2_MSI_MAP_CAP__FIXD__SHIFT
54572. BIFPLR5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
54573. BIFPLR5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
54574. BIFPLR5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
54575. BIFPLR5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
54576. BIFPLR5_2_MSI_MSG_CNTL__MSI_64BIT_MASK
54577. BIFPLR5_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
54578. BIFPLR5_2_MSI_MSG_CNTL__MSI_EN_MASK
54579. BIFPLR5_2_MSI_MSG_CNTL__MSI_EN__SHIFT
54580. BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
54581. BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
54582. BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
54583. BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
54584. BIFPLR5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
54585. BIFPLR5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
54586. BIFPLR5_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
54587. BIFPLR5_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
54588. BIFPLR5_2_MSI_MSG_DATA__MSI_DATA_MASK
54589. BIFPLR5_2_MSI_MSG_DATA__MSI_DATA__SHIFT
54590. BIFPLR5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
54591. BIFPLR5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
54592. BIFPLR5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
54593. BIFPLR5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
54594. BIFPLR5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
54595. BIFPLR5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
54596. BIFPLR5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
54597. BIFPLR5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
54598. BIFPLR5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
54599. BIFPLR5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
54600. BIFPLR5_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
54601. BIFPLR5_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
54602. BIFPLR5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
54603. BIFPLR5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
54604. BIFPLR5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
54605. BIFPLR5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
54606. BIFPLR5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
54607. BIFPLR5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
54608. BIFPLR5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
54609. BIFPLR5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
54610. BIFPLR5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
54611. BIFPLR5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
54612. BIFPLR5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
54613. BIFPLR5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
54614. BIFPLR5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
54615. BIFPLR5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
54616. BIFPLR5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
54617. BIFPLR5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
54618. BIFPLR5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
54619. BIFPLR5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
54620. BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
54621. BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
54622. BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
54623. BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
54624. BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
54625. BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
54626. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
54627. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
54628. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
54629. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
54630. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
54631. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
54632. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
54633. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
54634. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
54635. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
54636. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
54637. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
54638. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
54639. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
54640. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
54641. BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
54642. BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
54643. BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
54644. BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
54645. BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
54646. BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
54647. BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
54648. BIFPLR5_2_PCIE_CAP_LIST__CAP_ID_MASK
54649. BIFPLR5_2_PCIE_CAP_LIST__CAP_ID__SHIFT
54650. BIFPLR5_2_PCIE_CAP_LIST__NEXT_PTR_MASK
54651. BIFPLR5_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
54652. BIFPLR5_2_PCIE_CAP__DEVICE_TYPE_MASK
54653. BIFPLR5_2_PCIE_CAP__DEVICE_TYPE__SHIFT
54654. BIFPLR5_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
54655. BIFPLR5_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
54656. BIFPLR5_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
54657. BIFPLR5_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
54658. BIFPLR5_2_PCIE_CAP__VERSION_MASK
54659. BIFPLR5_2_PCIE_CAP__VERSION__SHIFT
54660. BIFPLR5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
54661. BIFPLR5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
54662. BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
54663. BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
54664. BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
54665. BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
54666. BIFPLR5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
54667. BIFPLR5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
54668. BIFPLR5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
54669. BIFPLR5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
54670. BIFPLR5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
54671. BIFPLR5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
54672. BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
54673. BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
54674. BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
54675. BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
54676. BIFPLR5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
54677. BIFPLR5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
54678. BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
54679. BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
54680. BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
54681. BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
54682. BIFPLR5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
54683. BIFPLR5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
54684. BIFPLR5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
54685. BIFPLR5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
54686. BIFPLR5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
54687. BIFPLR5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
54688. BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
54689. BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
54690. BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
54691. BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
54692. BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
54693. BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
54694. BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
54695. BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
54696. BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
54697. BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
54698. BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
54699. BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
54700. BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
54701. BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
54702. BIFPLR5_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
54703. BIFPLR5_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
54704. BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
54705. BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
54706. BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
54707. BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
54708. BIFPLR5_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
54709. BIFPLR5_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
54710. BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
54711. BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
54712. BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
54713. BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
54714. BIFPLR5_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
54715. BIFPLR5_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
54716. BIFPLR5_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
54717. BIFPLR5_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
54718. BIFPLR5_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
54719. BIFPLR5_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
54720. BIFPLR5_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
54721. BIFPLR5_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
54722. BIFPLR5_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
54723. BIFPLR5_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
54724. BIFPLR5_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
54725. BIFPLR5_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
54726. BIFPLR5_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
54727. BIFPLR5_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
54728. BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
54729. BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
54730. BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
54731. BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
54732. BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
54733. BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
54734. BIFPLR5_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
54735. BIFPLR5_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
54736. BIFPLR5_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
54737. BIFPLR5_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
54738. BIFPLR5_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
54739. BIFPLR5_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
54740. BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
54741. BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
54742. BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
54743. BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
54744. BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
54745. BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
54746. BIFPLR5_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
54747. BIFPLR5_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
54748. BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
54749. BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
54750. BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
54751. BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
54752. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK
54753. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
54754. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK
54755. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
54756. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK
54757. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
54758. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK
54759. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
54760. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK
54761. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
54762. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK
54763. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
54764. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK
54765. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
54766. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK
54767. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
54768. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK
54769. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
54770. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK
54771. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
54772. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK
54773. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
54774. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK
54775. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
54776. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK
54777. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
54778. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK
54779. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
54780. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK
54781. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
54782. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK
54783. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
54784. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK
54785. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
54786. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK
54787. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
54788. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK
54789. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
54790. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK
54791. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
54792. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK
54793. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
54794. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK
54795. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
54796. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK
54797. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
54798. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK
54799. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
54800. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK
54801. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
54802. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK
54803. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
54804. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK
54805. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
54806. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK
54807. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
54808. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK
54809. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
54810. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK
54811. BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
54812. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK
54813. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
54814. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK
54815. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
54816. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK
54817. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
54818. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK
54819. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
54820. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK
54821. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
54822. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK
54823. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
54824. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK
54825. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
54826. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK
54827. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
54828. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK
54829. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
54830. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK
54831. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
54832. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK
54833. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
54834. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK
54835. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
54836. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK
54837. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
54838. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK
54839. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
54840. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK
54841. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
54842. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK
54843. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
54844. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK
54845. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
54846. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK
54847. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
54848. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK
54849. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
54850. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK
54851. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
54852. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK
54853. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
54854. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK
54855. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
54856. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK
54857. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
54858. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK
54859. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
54860. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK
54861. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
54862. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK
54863. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
54864. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK
54865. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
54866. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK
54867. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
54868. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK
54869. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
54870. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK
54871. BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
54872. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK
54873. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
54874. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK
54875. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
54876. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK
54877. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
54878. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK
54879. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
54880. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK
54881. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
54882. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK
54883. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
54884. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK
54885. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
54886. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK
54887. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
54888. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK
54889. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
54890. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK
54891. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
54892. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK
54893. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
54894. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK
54895. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
54896. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK
54897. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
54898. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK
54899. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
54900. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK
54901. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
54902. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK
54903. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
54904. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK
54905. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
54906. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK
54907. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
54908. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK
54909. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
54910. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK
54911. BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
54912. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK
54913. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
54914. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK
54915. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
54916. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK
54917. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
54918. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK
54919. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
54920. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK
54921. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
54922. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK
54923. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
54924. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK
54925. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
54926. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK
54927. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
54928. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK
54929. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
54930. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK
54931. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
54932. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK
54933. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
54934. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK
54935. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
54936. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK
54937. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
54938. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK
54939. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
54940. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK
54941. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
54942. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK
54943. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
54944. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK
54945. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
54946. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK
54947. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
54948. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK
54949. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
54950. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK
54951. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
54952. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK
54953. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
54954. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK
54955. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
54956. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK
54957. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
54958. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK
54959. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
54960. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK
54961. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
54962. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK
54963. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
54964. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK
54965. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
54966. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK
54967. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
54968. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK
54969. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
54970. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK
54971. BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
54972. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK
54973. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
54974. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK
54975. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
54976. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK
54977. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
54978. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK
54979. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
54980. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK
54981. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
54982. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK
54983. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
54984. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK
54985. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
54986. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK
54987. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
54988. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK
54989. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
54990. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK
54991. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
54992. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK
54993. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
54994. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK
54995. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
54996. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK
54997. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
54998. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK
54999. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
55000. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK
55001. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
55002. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK
55003. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
55004. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK
55005. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
55006. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK
55007. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
55008. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK
55009. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
55010. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK
55011. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
55012. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK
55013. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
55014. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK
55015. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
55016. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK
55017. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
55018. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK
55019. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
55020. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK
55021. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
55022. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK
55023. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
55024. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK
55025. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
55026. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK
55027. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
55028. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK
55029. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
55030. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK
55031. BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
55032. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK
55033. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
55034. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK
55035. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
55036. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK
55037. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
55038. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK
55039. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
55040. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK
55041. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
55042. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK
55043. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
55044. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK
55045. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
55046. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK
55047. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
55048. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK
55049. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
55050. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK
55051. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
55052. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK
55053. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
55054. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK
55055. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
55056. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK
55057. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
55058. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK
55059. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
55060. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK
55061. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
55062. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK
55063. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
55064. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK
55065. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
55066. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK
55067. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
55068. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK
55069. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
55070. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK
55071. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
55072. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK
55073. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
55074. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK
55075. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
55076. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK
55077. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
55078. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK
55079. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
55080. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK
55081. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
55082. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK
55083. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
55084. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK
55085. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
55086. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK
55087. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
55088. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK
55089. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
55090. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK
55091. BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
55092. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK
55093. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
55094. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK
55095. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
55096. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK
55097. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
55098. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK
55099. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
55100. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK
55101. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
55102. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK
55103. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
55104. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK
55105. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
55106. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK
55107. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
55108. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK
55109. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
55110. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK
55111. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
55112. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK
55113. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
55114. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK
55115. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
55116. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK
55117. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
55118. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK
55119. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
55120. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK
55121. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
55122. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK
55123. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
55124. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK
55125. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
55126. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK
55127. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
55128. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK
55129. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
55130. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK
55131. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
55132. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK
55133. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
55134. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK
55135. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
55136. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK
55137. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
55138. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK
55139. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
55140. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK
55141. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
55142. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK
55143. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
55144. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK
55145. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
55146. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK
55147. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
55148. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK
55149. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
55150. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK
55151. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
55152. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK
55153. BIFPLR5_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
55154. BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK
55155. BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
55156. BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK
55157. BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
55158. BIFPLR5_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
55159. BIFPLR5_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
55160. BIFPLR5_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK
55161. BIFPLR5_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
55162. BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
55163. BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
55164. BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
55165. BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
55166. BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
55167. BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
55168. BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
55169. BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
55170. BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
55171. BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
55172. BIFPLR5_2_PCIE_ESM_HEADER_2__CAP_ID_MASK
55173. BIFPLR5_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
55174. BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
55175. BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
55176. BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
55177. BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
55178. BIFPLR5_2_PCIE_HDR_LOG0__TLP_HDR_MASK
55179. BIFPLR5_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
55180. BIFPLR5_2_PCIE_HDR_LOG1__TLP_HDR_MASK
55181. BIFPLR5_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
55182. BIFPLR5_2_PCIE_HDR_LOG2__TLP_HDR_MASK
55183. BIFPLR5_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
55184. BIFPLR5_2_PCIE_HDR_LOG3__TLP_HDR_MASK
55185. BIFPLR5_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
55186. BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
55187. BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
55188. BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
55189. BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
55190. BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
55191. BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
55192. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
55193. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
55194. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
55195. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
55196. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
55197. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
55198. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
55199. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
55200. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
55201. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
55202. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
55203. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
55204. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
55205. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
55206. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
55207. BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
55208. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
55209. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
55210. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
55211. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
55212. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
55213. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
55214. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
55215. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
55216. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
55217. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
55218. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
55219. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
55220. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
55221. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
55222. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
55223. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
55224. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
55225. BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
55226. BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55227. BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55228. BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55229. BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55230. BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55231. BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55232. BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55233. BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55234. BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55235. BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55236. BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55237. BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55238. BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55239. BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55240. BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55241. BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55242. BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55243. BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55244. BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55245. BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55246. BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55247. BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55248. BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55249. BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55250. BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55251. BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55252. BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55253. BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55254. BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55255. BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55256. BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55257. BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55258. BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55259. BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55260. BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55261. BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55262. BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55263. BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55264. BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55265. BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55266. BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55267. BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55268. BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55269. BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55270. BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55271. BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55272. BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55273. BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55274. BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55275. BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55276. BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55277. BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55278. BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55279. BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55280. BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55281. BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55282. BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55283. BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55284. BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55285. BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55286. BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55287. BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55288. BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55289. BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55290. BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55291. BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55292. BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55293. BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55294. BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55295. BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55296. BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55297. BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55298. BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55299. BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55300. BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55301. BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55302. BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55303. BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55304. BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55305. BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55306. BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55307. BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55308. BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55309. BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55310. BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55311. BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55312. BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55313. BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55314. BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55315. BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55316. BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55317. BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55318. BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55319. BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55320. BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55321. BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55322. BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55323. BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55324. BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55325. BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55326. BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55327. BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55328. BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55329. BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55330. BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55331. BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55332. BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55333. BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55334. BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55335. BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55336. BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55337. BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55338. BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55339. BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55340. BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55341. BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55342. BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55343. BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55344. BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55345. BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55346. BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
55347. BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
55348. BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
55349. BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
55350. BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
55351. BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
55352. BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
55353. BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
55354. BIFPLR5_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
55355. BIFPLR5_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
55356. BIFPLR5_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
55357. BIFPLR5_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
55358. BIFPLR5_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
55359. BIFPLR5_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
55360. BIFPLR5_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
55361. BIFPLR5_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
55362. BIFPLR5_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
55363. BIFPLR5_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
55364. BIFPLR5_2_PCIE_LINK_CNTL3__RESERVED_MASK
55365. BIFPLR5_2_PCIE_LINK_CNTL3__RESERVED__SHIFT
55366. BIFPLR5_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
55367. BIFPLR5_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
55368. BIFPLR5_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
55369. BIFPLR5_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
55370. BIFPLR5_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
55371. BIFPLR5_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
55372. BIFPLR5_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
55373. BIFPLR5_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
55374. BIFPLR5_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
55375. BIFPLR5_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
55376. BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
55377. BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
55378. BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
55379. BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
55380. BIFPLR5_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
55381. BIFPLR5_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
55382. BIFPLR5_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK
55383. BIFPLR5_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
55384. BIFPLR5_2_PCIE_MC_CNTL__MC_ENABLE_MASK
55385. BIFPLR5_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT
55386. BIFPLR5_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
55387. BIFPLR5_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
55388. BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
55389. BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
55390. BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
55391. BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
55392. BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
55393. BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
55394. BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
55395. BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
55396. BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
55397. BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
55398. BIFPLR5_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
55399. BIFPLR5_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
55400. BIFPLR5_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
55401. BIFPLR5_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
55402. BIFPLR5_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
55403. BIFPLR5_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
55404. BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
55405. BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
55406. BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
55407. BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
55408. BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
55409. BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
55410. BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
55411. BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
55412. BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
55413. BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
55414. BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
55415. BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
55416. BIFPLR5_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
55417. BIFPLR5_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
55418. BIFPLR5_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
55419. BIFPLR5_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
55420. BIFPLR5_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
55421. BIFPLR5_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
55422. BIFPLR5_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
55423. BIFPLR5_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
55424. BIFPLR5_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
55425. BIFPLR5_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
55426. BIFPLR5_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
55427. BIFPLR5_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
55428. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
55429. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
55430. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
55431. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
55432. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
55433. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
55434. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
55435. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
55436. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
55437. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
55438. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
55439. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
55440. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
55441. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
55442. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
55443. BIFPLR5_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
55444. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
55445. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
55446. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
55447. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
55448. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
55449. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
55450. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
55451. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
55452. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
55453. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
55454. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
55455. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
55456. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
55457. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
55458. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
55459. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
55460. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
55461. BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
55462. BIFPLR5_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
55463. BIFPLR5_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
55464. BIFPLR5_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
55465. BIFPLR5_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
55466. BIFPLR5_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
55467. BIFPLR5_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
55468. BIFPLR5_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
55469. BIFPLR5_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
55470. BIFPLR5_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
55471. BIFPLR5_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
55472. BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
55473. BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
55474. BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK
55475. BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
55476. BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
55477. BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
55478. BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
55479. BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
55480. BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CTO_MASK
55481. BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
55482. BIFPLR5_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
55483. BIFPLR5_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
55484. BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
55485. BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
55486. BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK
55487. BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
55488. BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
55489. BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
55490. BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
55491. BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
55492. BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
55493. BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
55494. BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
55495. BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
55496. BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
55497. BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
55498. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
55499. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
55500. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
55501. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
55502. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
55503. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
55504. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
55505. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
55506. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
55507. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
55508. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
55509. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
55510. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
55511. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
55512. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
55513. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
55514. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
55515. BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
55516. BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
55517. BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
55518. BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
55519. BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
55520. BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
55521. BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
55522. BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
55523. BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
55524. BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK
55525. BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
55526. BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
55527. BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
55528. BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
55529. BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
55530. BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
55531. BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
55532. BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
55533. BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
55534. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
55535. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
55536. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
55537. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
55538. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
55539. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
55540. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
55541. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
55542. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
55543. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
55544. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
55545. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
55546. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
55547. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
55548. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
55549. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
55550. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
55551. BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
55552. BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
55553. BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
55554. BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
55555. BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
55556. BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
55557. BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
55558. BIFPLR5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
55559. BIFPLR5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
55560. BIFPLR5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
55561. BIFPLR5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
55562. BIFPLR5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
55563. BIFPLR5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
55564. BIFPLR5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
55565. BIFPLR5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
55566. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
55567. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
55568. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
55569. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
55570. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
55571. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
55572. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
55573. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
55574. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
55575. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
55576. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
55577. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
55578. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
55579. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
55580. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
55581. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
55582. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
55583. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
55584. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
55585. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
55586. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
55587. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
55588. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
55589. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
55590. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
55591. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
55592. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
55593. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
55594. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
55595. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
55596. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
55597. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
55598. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
55599. BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
55600. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
55601. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
55602. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
55603. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
55604. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
55605. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
55606. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
55607. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
55608. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
55609. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
55610. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
55611. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
55612. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
55613. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
55614. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
55615. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
55616. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
55617. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
55618. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
55619. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
55620. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
55621. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
55622. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
55623. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
55624. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
55625. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
55626. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
55627. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
55628. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
55629. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
55630. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
55631. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
55632. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
55633. BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
55634. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
55635. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
55636. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
55637. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
55638. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
55639. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
55640. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
55641. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
55642. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
55643. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
55644. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
55645. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
55646. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
55647. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
55648. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
55649. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
55650. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
55651. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
55652. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
55653. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
55654. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
55655. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
55656. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
55657. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
55658. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
55659. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
55660. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
55661. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
55662. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
55663. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
55664. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
55665. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
55666. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
55667. BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
55668. BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
55669. BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
55670. BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
55671. BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
55672. BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
55673. BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
55674. BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
55675. BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
55676. BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
55677. BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
55678. BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
55679. BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
55680. BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
55681. BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
55682. BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
55683. BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
55684. BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
55685. BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
55686. BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
55687. BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
55688. BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
55689. BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
55690. BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
55691. BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
55692. BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
55693. BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
55694. BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
55695. BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
55696. BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
55697. BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
55698. BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
55699. BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
55700. BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
55701. BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
55702. BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
55703. BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
55704. BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
55705. BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
55706. BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
55707. BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
55708. BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
55709. BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
55710. BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
55711. BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
55712. BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
55713. BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
55714. BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
55715. BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
55716. BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
55717. BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
55718. BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
55719. BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
55720. BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
55721. BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
55722. BIFPLR5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
55723. BIFPLR5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
55724. BIFPLR5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
55725. BIFPLR5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
55726. BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
55727. BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
55728. BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
55729. BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
55730. BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
55731. BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
55732. BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
55733. BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
55734. BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
55735. BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
55736. BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
55737. BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
55738. BIFPLR5_2_PMI_CAP_LIST__CAP_ID_MASK
55739. BIFPLR5_2_PMI_CAP_LIST__CAP_ID__SHIFT
55740. BIFPLR5_2_PMI_CAP_LIST__NEXT_PTR_MASK
55741. BIFPLR5_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
55742. BIFPLR5_2_PMI_CAP__AUX_CURRENT_MASK
55743. BIFPLR5_2_PMI_CAP__AUX_CURRENT__SHIFT
55744. BIFPLR5_2_PMI_CAP__D1_SUPPORT_MASK
55745. BIFPLR5_2_PMI_CAP__D1_SUPPORT__SHIFT
55746. BIFPLR5_2_PMI_CAP__D2_SUPPORT_MASK
55747. BIFPLR5_2_PMI_CAP__D2_SUPPORT__SHIFT
55748. BIFPLR5_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
55749. BIFPLR5_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
55750. BIFPLR5_2_PMI_CAP__PME_CLOCK_MASK
55751. BIFPLR5_2_PMI_CAP__PME_CLOCK__SHIFT
55752. BIFPLR5_2_PMI_CAP__PME_SUPPORT_MASK
55753. BIFPLR5_2_PMI_CAP__PME_SUPPORT__SHIFT
55754. BIFPLR5_2_PMI_CAP__VERSION_MASK
55755. BIFPLR5_2_PMI_CAP__VERSION__SHIFT
55756. BIFPLR5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
55757. BIFPLR5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
55758. BIFPLR5_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
55759. BIFPLR5_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
55760. BIFPLR5_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
55761. BIFPLR5_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
55762. BIFPLR5_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
55763. BIFPLR5_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
55764. BIFPLR5_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
55765. BIFPLR5_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
55766. BIFPLR5_2_PMI_STATUS_CNTL__PME_EN_MASK
55767. BIFPLR5_2_PMI_STATUS_CNTL__PME_EN__SHIFT
55768. BIFPLR5_2_PMI_STATUS_CNTL__PME_STATUS_MASK
55769. BIFPLR5_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
55770. BIFPLR5_2_PMI_STATUS_CNTL__PMI_DATA_MASK
55771. BIFPLR5_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
55772. BIFPLR5_2_PMI_STATUS_CNTL__POWER_STATE_MASK
55773. BIFPLR5_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
55774. BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
55775. BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
55776. BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
55777. BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
55778. BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
55779. BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
55780. BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
55781. BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
55782. BIFPLR5_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
55783. BIFPLR5_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
55784. BIFPLR5_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
55785. BIFPLR5_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
55786. BIFPLR5_2_PROG_INTERFACE__PROG_INTERFACE_MASK
55787. BIFPLR5_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
55788. BIFPLR5_2_REVISION_ID__MAJOR_REV_ID_MASK
55789. BIFPLR5_2_REVISION_ID__MAJOR_REV_ID__SHIFT
55790. BIFPLR5_2_REVISION_ID__MINOR_REV_ID_MASK
55791. BIFPLR5_2_REVISION_ID__MINOR_REV_ID__SHIFT
55792. BIFPLR5_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
55793. BIFPLR5_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
55794. BIFPLR5_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
55795. BIFPLR5_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
55796. BIFPLR5_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK
55797. BIFPLR5_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
55798. BIFPLR5_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
55799. BIFPLR5_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
55800. BIFPLR5_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
55801. BIFPLR5_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
55802. BIFPLR5_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
55803. BIFPLR5_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
55804. BIFPLR5_2_ROOT_STATUS__PME_PENDING_MASK
55805. BIFPLR5_2_ROOT_STATUS__PME_PENDING__SHIFT
55806. BIFPLR5_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK
55807. BIFPLR5_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
55808. BIFPLR5_2_ROOT_STATUS__PME_STATUS_MASK
55809. BIFPLR5_2_ROOT_STATUS__PME_STATUS__SHIFT
55810. BIFPLR5_2_SECONDARY_STATUS__CAP_LIST_MASK
55811. BIFPLR5_2_SECONDARY_STATUS__CAP_LIST__SHIFT
55812. BIFPLR5_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK
55813. BIFPLR5_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
55814. BIFPLR5_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
55815. BIFPLR5_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
55816. BIFPLR5_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
55817. BIFPLR5_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
55818. BIFPLR5_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
55819. BIFPLR5_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
55820. BIFPLR5_2_SECONDARY_STATUS__PCI_66_EN_MASK
55821. BIFPLR5_2_SECONDARY_STATUS__PCI_66_EN__SHIFT
55822. BIFPLR5_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
55823. BIFPLR5_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
55824. BIFPLR5_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
55825. BIFPLR5_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
55826. BIFPLR5_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
55827. BIFPLR5_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
55828. BIFPLR5_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
55829. BIFPLR5_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
55830. BIFPLR5_2_SLOT_CAP2__RESERVED_MASK
55831. BIFPLR5_2_SLOT_CAP2__RESERVED__SHIFT
55832. BIFPLR5_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
55833. BIFPLR5_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
55834. BIFPLR5_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
55835. BIFPLR5_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
55836. BIFPLR5_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
55837. BIFPLR5_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
55838. BIFPLR5_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK
55839. BIFPLR5_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
55840. BIFPLR5_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK
55841. BIFPLR5_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
55842. BIFPLR5_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
55843. BIFPLR5_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
55844. BIFPLR5_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
55845. BIFPLR5_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
55846. BIFPLR5_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
55847. BIFPLR5_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
55848. BIFPLR5_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
55849. BIFPLR5_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
55850. BIFPLR5_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
55851. BIFPLR5_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
55852. BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
55853. BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
55854. BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
55855. BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
55856. BIFPLR5_2_SLOT_CNTL2__RESERVED_MASK
55857. BIFPLR5_2_SLOT_CNTL2__RESERVED__SHIFT
55858. BIFPLR5_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
55859. BIFPLR5_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
55860. BIFPLR5_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
55861. BIFPLR5_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
55862. BIFPLR5_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
55863. BIFPLR5_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
55864. BIFPLR5_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
55865. BIFPLR5_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
55866. BIFPLR5_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
55867. BIFPLR5_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
55868. BIFPLR5_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
55869. BIFPLR5_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
55870. BIFPLR5_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
55871. BIFPLR5_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
55872. BIFPLR5_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
55873. BIFPLR5_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
55874. BIFPLR5_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
55875. BIFPLR5_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
55876. BIFPLR5_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
55877. BIFPLR5_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
55878. BIFPLR5_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
55879. BIFPLR5_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
55880. BIFPLR5_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
55881. BIFPLR5_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
55882. BIFPLR5_2_SLOT_STATUS2__RESERVED_MASK
55883. BIFPLR5_2_SLOT_STATUS2__RESERVED__SHIFT
55884. BIFPLR5_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
55885. BIFPLR5_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
55886. BIFPLR5_2_SLOT_STATUS__COMMAND_COMPLETED_MASK
55887. BIFPLR5_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
55888. BIFPLR5_2_SLOT_STATUS__DL_STATE_CHANGED_MASK
55889. BIFPLR5_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
55890. BIFPLR5_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
55891. BIFPLR5_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
55892. BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
55893. BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
55894. BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK
55895. BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
55896. BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
55897. BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
55898. BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
55899. BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
55900. BIFPLR5_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
55901. BIFPLR5_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
55902. BIFPLR5_2_SSID_CAP_LIST__CAP_ID_MASK
55903. BIFPLR5_2_SSID_CAP_LIST__CAP_ID__SHIFT
55904. BIFPLR5_2_SSID_CAP_LIST__NEXT_PTR_MASK
55905. BIFPLR5_2_SSID_CAP_LIST__NEXT_PTR__SHIFT
55906. BIFPLR5_2_SSID_CAP__SUBSYSTEM_ID_MASK
55907. BIFPLR5_2_SSID_CAP__SUBSYSTEM_ID__SHIFT
55908. BIFPLR5_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
55909. BIFPLR5_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
55910. BIFPLR5_2_STATUS__CAP_LIST_MASK
55911. BIFPLR5_2_STATUS__CAP_LIST__SHIFT
55912. BIFPLR5_2_STATUS__DEVSEL_TIMING_MASK
55913. BIFPLR5_2_STATUS__DEVSEL_TIMING__SHIFT
55914. BIFPLR5_2_STATUS__FAST_BACK_CAPABLE_MASK
55915. BIFPLR5_2_STATUS__FAST_BACK_CAPABLE__SHIFT
55916. BIFPLR5_2_STATUS__INT_STATUS_MASK
55917. BIFPLR5_2_STATUS__INT_STATUS__SHIFT
55918. BIFPLR5_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
55919. BIFPLR5_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
55920. BIFPLR5_2_STATUS__PARITY_ERROR_DETECTED_MASK
55921. BIFPLR5_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
55922. BIFPLR5_2_STATUS__PCI_66_EN_MASK
55923. BIFPLR5_2_STATUS__PCI_66_EN__SHIFT
55924. BIFPLR5_2_STATUS__RECEIVED_MASTER_ABORT_MASK
55925. BIFPLR5_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
55926. BIFPLR5_2_STATUS__RECEIVED_TARGET_ABORT_MASK
55927. BIFPLR5_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
55928. BIFPLR5_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
55929. BIFPLR5_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
55930. BIFPLR5_2_STATUS__SIGNAL_TARGET_ABORT_MASK
55931. BIFPLR5_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
55932. BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
55933. BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
55934. BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
55935. BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
55936. BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
55937. BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
55938. BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
55939. BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
55940. BIFPLR5_2_SUB_CLASS__SUB_CLASS_MASK
55941. BIFPLR5_2_SUB_CLASS__SUB_CLASS__SHIFT
55942. BIFPLR5_2_VENDOR_ID__VENDOR_ID_MASK
55943. BIFPLR5_2_VENDOR_ID__VENDOR_ID__SHIFT
55944. BIFPLR6_0_BASE_CLASS__BASE_CLASS_MASK
55945. BIFPLR6_0_BASE_CLASS__BASE_CLASS__SHIFT
55946. BIFPLR6_0_BIST__BIST_CAP_MASK
55947. BIFPLR6_0_BIST__BIST_CAP__SHIFT
55948. BIFPLR6_0_BIST__BIST_COMP_MASK
55949. BIFPLR6_0_BIST__BIST_COMP__SHIFT
55950. BIFPLR6_0_BIST__BIST_STRT_MASK
55951. BIFPLR6_0_BIST__BIST_STRT__SHIFT
55952. BIFPLR6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
55953. BIFPLR6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
55954. BIFPLR6_0_CAP_PTR__CAP_PTR_MASK
55955. BIFPLR6_0_CAP_PTR__CAP_PTR__SHIFT
55956. BIFPLR6_0_COMMAND__AD_STEPPING_MASK
55957. BIFPLR6_0_COMMAND__AD_STEPPING__SHIFT
55958. BIFPLR6_0_COMMAND__BUS_MASTER_EN_MASK
55959. BIFPLR6_0_COMMAND__BUS_MASTER_EN__SHIFT
55960. BIFPLR6_0_COMMAND__FAST_B2B_EN_MASK
55961. BIFPLR6_0_COMMAND__FAST_B2B_EN__SHIFT
55962. BIFPLR6_0_COMMAND__INT_DIS_MASK
55963. BIFPLR6_0_COMMAND__INT_DIS__SHIFT
55964. BIFPLR6_0_COMMAND__IO_ACCESS_EN_MASK
55965. BIFPLR6_0_COMMAND__IO_ACCESS_EN__SHIFT
55966. BIFPLR6_0_COMMAND__MEM_ACCESS_EN_MASK
55967. BIFPLR6_0_COMMAND__MEM_ACCESS_EN__SHIFT
55968. BIFPLR6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
55969. BIFPLR6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
55970. BIFPLR6_0_COMMAND__PAL_SNOOP_EN_MASK
55971. BIFPLR6_0_COMMAND__PAL_SNOOP_EN__SHIFT
55972. BIFPLR6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
55973. BIFPLR6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
55974. BIFPLR6_0_COMMAND__SERR_EN_MASK
55975. BIFPLR6_0_COMMAND__SERR_EN__SHIFT
55976. BIFPLR6_0_COMMAND__SPECIAL_CYCLE_EN_MASK
55977. BIFPLR6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
55978. BIFPLR6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
55979. BIFPLR6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
55980. BIFPLR6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
55981. BIFPLR6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
55982. BIFPLR6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
55983. BIFPLR6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
55984. BIFPLR6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
55985. BIFPLR6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
55986. BIFPLR6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
55987. BIFPLR6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
55988. BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
55989. BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
55990. BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
55991. BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
55992. BIFPLR6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
55993. BIFPLR6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
55994. BIFPLR6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
55995. BIFPLR6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
55996. BIFPLR6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
55997. BIFPLR6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
55998. BIFPLR6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
55999. BIFPLR6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
56000. BIFPLR6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
56001. BIFPLR6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
56002. BIFPLR6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
56003. BIFPLR6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
56004. BIFPLR6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
56005. BIFPLR6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
56006. BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
56007. BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
56008. BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
56009. BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
56010. BIFPLR6_0_DEVICE_CAP__EXTENDED_TAG_MASK
56011. BIFPLR6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
56012. BIFPLR6_0_DEVICE_CAP__FLR_CAPABLE_MASK
56013. BIFPLR6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
56014. BIFPLR6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
56015. BIFPLR6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
56016. BIFPLR6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
56017. BIFPLR6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
56018. BIFPLR6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
56019. BIFPLR6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
56020. BIFPLR6_0_DEVICE_CAP__PHANTOM_FUNC_MASK
56021. BIFPLR6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
56022. BIFPLR6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
56023. BIFPLR6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
56024. BIFPLR6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
56025. BIFPLR6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
56026. BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
56027. BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
56028. BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
56029. BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
56030. BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
56031. BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
56032. BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
56033. BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
56034. BIFPLR6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
56035. BIFPLR6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
56036. BIFPLR6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
56037. BIFPLR6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
56038. BIFPLR6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
56039. BIFPLR6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
56040. BIFPLR6_0_DEVICE_CNTL2__LTR_EN_MASK
56041. BIFPLR6_0_DEVICE_CNTL2__LTR_EN__SHIFT
56042. BIFPLR6_0_DEVICE_CNTL2__OBFF_EN_MASK
56043. BIFPLR6_0_DEVICE_CNTL2__OBFF_EN__SHIFT
56044. BIFPLR6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
56045. BIFPLR6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
56046. BIFPLR6_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
56047. BIFPLR6_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
56048. BIFPLR6_0_DEVICE_CNTL__CORR_ERR_EN_MASK
56049. BIFPLR6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
56050. BIFPLR6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
56051. BIFPLR6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
56052. BIFPLR6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
56053. BIFPLR6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
56054. BIFPLR6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
56055. BIFPLR6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
56056. BIFPLR6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
56057. BIFPLR6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
56058. BIFPLR6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
56059. BIFPLR6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
56060. BIFPLR6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
56061. BIFPLR6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
56062. BIFPLR6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
56063. BIFPLR6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
56064. BIFPLR6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
56065. BIFPLR6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
56066. BIFPLR6_0_DEVICE_CNTL__USR_REPORT_EN_MASK
56067. BIFPLR6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
56068. BIFPLR6_0_DEVICE_ID__DEVICE_ID_MASK
56069. BIFPLR6_0_DEVICE_ID__DEVICE_ID__SHIFT
56070. BIFPLR6_0_DEVICE_STATUS2__RESERVED_MASK
56071. BIFPLR6_0_DEVICE_STATUS2__RESERVED__SHIFT
56072. BIFPLR6_0_DEVICE_STATUS__AUX_PWR_MASK
56073. BIFPLR6_0_DEVICE_STATUS__AUX_PWR__SHIFT
56074. BIFPLR6_0_DEVICE_STATUS__CORR_ERR_MASK
56075. BIFPLR6_0_DEVICE_STATUS__CORR_ERR__SHIFT
56076. BIFPLR6_0_DEVICE_STATUS__FATAL_ERR_MASK
56077. BIFPLR6_0_DEVICE_STATUS__FATAL_ERR__SHIFT
56078. BIFPLR6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
56079. BIFPLR6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
56080. BIFPLR6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
56081. BIFPLR6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
56082. BIFPLR6_0_DEVICE_STATUS__USR_DETECTED_MASK
56083. BIFPLR6_0_DEVICE_STATUS__USR_DETECTED__SHIFT
56084. BIFPLR6_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
56085. BIFPLR6_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
56086. BIFPLR6_0_HEADER__DEVICE_TYPE_MASK
56087. BIFPLR6_0_HEADER__DEVICE_TYPE__SHIFT
56088. BIFPLR6_0_HEADER__HEADER_TYPE_MASK
56089. BIFPLR6_0_HEADER__HEADER_TYPE__SHIFT
56090. BIFPLR6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
56091. BIFPLR6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
56092. BIFPLR6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
56093. BIFPLR6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
56094. BIFPLR6_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
56095. BIFPLR6_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
56096. BIFPLR6_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
56097. BIFPLR6_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
56098. BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_MASK
56099. BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
56100. BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
56101. BIFPLR6_0_IO_BASE_LIMIT__IO_BASE__SHIFT
56102. BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_MASK
56103. BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
56104. BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
56105. BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT
56106. BIFPLR6_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
56107. BIFPLR6_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
56108. BIFPLR6_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK
56109. BIFPLR6_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
56110. BIFPLR6_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
56111. BIFPLR6_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
56112. BIFPLR6_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
56113. BIFPLR6_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
56114. BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
56115. BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
56116. BIFPLR6_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK
56117. BIFPLR6_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
56118. BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
56119. BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
56120. BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK
56121. BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
56122. BIFPLR6_0_LATENCY__LATENCY_TIMER_MASK
56123. BIFPLR6_0_LATENCY__LATENCY_TIMER__SHIFT
56124. BIFPLR6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
56125. BIFPLR6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
56126. BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
56127. BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
56128. BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
56129. BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
56130. BIFPLR6_0_LINK_CAP2__RESERVED_MASK
56131. BIFPLR6_0_LINK_CAP2__RESERVED__SHIFT
56132. BIFPLR6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
56133. BIFPLR6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
56134. BIFPLR6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
56135. BIFPLR6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
56136. BIFPLR6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
56137. BIFPLR6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
56138. BIFPLR6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
56139. BIFPLR6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
56140. BIFPLR6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
56141. BIFPLR6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
56142. BIFPLR6_0_LINK_CAP__L1_EXIT_LATENCY_MASK
56143. BIFPLR6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
56144. BIFPLR6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
56145. BIFPLR6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
56146. BIFPLR6_0_LINK_CAP__LINK_SPEED_MASK
56147. BIFPLR6_0_LINK_CAP__LINK_SPEED__SHIFT
56148. BIFPLR6_0_LINK_CAP__LINK_WIDTH_MASK
56149. BIFPLR6_0_LINK_CAP__LINK_WIDTH__SHIFT
56150. BIFPLR6_0_LINK_CAP__PM_SUPPORT_MASK
56151. BIFPLR6_0_LINK_CAP__PM_SUPPORT__SHIFT
56152. BIFPLR6_0_LINK_CAP__PORT_NUMBER_MASK
56153. BIFPLR6_0_LINK_CAP__PORT_NUMBER__SHIFT
56154. BIFPLR6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
56155. BIFPLR6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
56156. BIFPLR6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
56157. BIFPLR6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
56158. BIFPLR6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
56159. BIFPLR6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
56160. BIFPLR6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
56161. BIFPLR6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
56162. BIFPLR6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
56163. BIFPLR6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
56164. BIFPLR6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
56165. BIFPLR6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
56166. BIFPLR6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
56167. BIFPLR6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
56168. BIFPLR6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
56169. BIFPLR6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
56170. BIFPLR6_0_LINK_CNTL2__XMIT_MARGIN_MASK
56171. BIFPLR6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
56172. BIFPLR6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
56173. BIFPLR6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
56174. BIFPLR6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
56175. BIFPLR6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
56176. BIFPLR6_0_LINK_CNTL__EXTENDED_SYNC_MASK
56177. BIFPLR6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
56178. BIFPLR6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
56179. BIFPLR6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
56180. BIFPLR6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
56181. BIFPLR6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
56182. BIFPLR6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
56183. BIFPLR6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
56184. BIFPLR6_0_LINK_CNTL__LINK_DIS_MASK
56185. BIFPLR6_0_LINK_CNTL__LINK_DIS__SHIFT
56186. BIFPLR6_0_LINK_CNTL__PM_CONTROL_MASK
56187. BIFPLR6_0_LINK_CNTL__PM_CONTROL__SHIFT
56188. BIFPLR6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
56189. BIFPLR6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
56190. BIFPLR6_0_LINK_CNTL__RETRAIN_LINK_MASK
56191. BIFPLR6_0_LINK_CNTL__RETRAIN_LINK__SHIFT
56192. BIFPLR6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
56193. BIFPLR6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
56194. BIFPLR6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
56195. BIFPLR6_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
56196. BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
56197. BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
56198. BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
56199. BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
56200. BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
56201. BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
56202. BIFPLR6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
56203. BIFPLR6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
56204. BIFPLR6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
56205. BIFPLR6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
56206. BIFPLR6_0_LINK_STATUS__DL_ACTIVE_MASK
56207. BIFPLR6_0_LINK_STATUS__DL_ACTIVE__SHIFT
56208. BIFPLR6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
56209. BIFPLR6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
56210. BIFPLR6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
56211. BIFPLR6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
56212. BIFPLR6_0_LINK_STATUS__LINK_TRAINING_MASK
56213. BIFPLR6_0_LINK_STATUS__LINK_TRAINING__SHIFT
56214. BIFPLR6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
56215. BIFPLR6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
56216. BIFPLR6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
56217. BIFPLR6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
56218. BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
56219. BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
56220. BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
56221. BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
56222. BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
56223. BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
56224. BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
56225. BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
56226. BIFPLR6_0_MSI_CAP_LIST__CAP_ID_MASK
56227. BIFPLR6_0_MSI_CAP_LIST__CAP_ID__SHIFT
56228. BIFPLR6_0_MSI_CAP_LIST__NEXT_PTR_MASK
56229. BIFPLR6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
56230. BIFPLR6_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
56231. BIFPLR6_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
56232. BIFPLR6_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
56233. BIFPLR6_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
56234. BIFPLR6_0_MSI_MAP_CAP_LIST__CAP_ID_MASK
56235. BIFPLR6_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
56236. BIFPLR6_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
56237. BIFPLR6_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
56238. BIFPLR6_0_MSI_MAP_CAP__CAP_TYPE_MASK
56239. BIFPLR6_0_MSI_MAP_CAP__CAP_TYPE__SHIFT
56240. BIFPLR6_0_MSI_MAP_CAP__EN_MASK
56241. BIFPLR6_0_MSI_MAP_CAP__EN__SHIFT
56242. BIFPLR6_0_MSI_MAP_CAP__FIXD_MASK
56243. BIFPLR6_0_MSI_MAP_CAP__FIXD__SHIFT
56244. BIFPLR6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
56245. BIFPLR6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
56246. BIFPLR6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
56247. BIFPLR6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
56248. BIFPLR6_0_MSI_MSG_CNTL__MSI_64BIT_MASK
56249. BIFPLR6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
56250. BIFPLR6_0_MSI_MSG_CNTL__MSI_EN_MASK
56251. BIFPLR6_0_MSI_MSG_CNTL__MSI_EN__SHIFT
56252. BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
56253. BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
56254. BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
56255. BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
56256. BIFPLR6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
56257. BIFPLR6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
56258. BIFPLR6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
56259. BIFPLR6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
56260. BIFPLR6_0_MSI_MSG_DATA__MSI_DATA_MASK
56261. BIFPLR6_0_MSI_MSG_DATA__MSI_DATA__SHIFT
56262. BIFPLR6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
56263. BIFPLR6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
56264. BIFPLR6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
56265. BIFPLR6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
56266. BIFPLR6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
56267. BIFPLR6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
56268. BIFPLR6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
56269. BIFPLR6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
56270. BIFPLR6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
56271. BIFPLR6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
56272. BIFPLR6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
56273. BIFPLR6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
56274. BIFPLR6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
56275. BIFPLR6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
56276. BIFPLR6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
56277. BIFPLR6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
56278. BIFPLR6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
56279. BIFPLR6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
56280. BIFPLR6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
56281. BIFPLR6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
56282. BIFPLR6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
56283. BIFPLR6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
56284. BIFPLR6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
56285. BIFPLR6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
56286. BIFPLR6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
56287. BIFPLR6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
56288. BIFPLR6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
56289. BIFPLR6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
56290. BIFPLR6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
56291. BIFPLR6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
56292. BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
56293. BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
56294. BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
56295. BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
56296. BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
56297. BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
56298. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
56299. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
56300. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
56301. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
56302. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
56303. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
56304. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
56305. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
56306. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
56307. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
56308. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
56309. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
56310. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
56311. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
56312. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
56313. BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
56314. BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
56315. BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
56316. BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
56317. BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
56318. BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
56319. BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
56320. BIFPLR6_0_PCIE_CAP_LIST__CAP_ID_MASK
56321. BIFPLR6_0_PCIE_CAP_LIST__CAP_ID__SHIFT
56322. BIFPLR6_0_PCIE_CAP_LIST__NEXT_PTR_MASK
56323. BIFPLR6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
56324. BIFPLR6_0_PCIE_CAP__DEVICE_TYPE_MASK
56325. BIFPLR6_0_PCIE_CAP__DEVICE_TYPE__SHIFT
56326. BIFPLR6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
56327. BIFPLR6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
56328. BIFPLR6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
56329. BIFPLR6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
56330. BIFPLR6_0_PCIE_CAP__VERSION_MASK
56331. BIFPLR6_0_PCIE_CAP__VERSION__SHIFT
56332. BIFPLR6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
56333. BIFPLR6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
56334. BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
56335. BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
56336. BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
56337. BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
56338. BIFPLR6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
56339. BIFPLR6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
56340. BIFPLR6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
56341. BIFPLR6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
56342. BIFPLR6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
56343. BIFPLR6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
56344. BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
56345. BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
56346. BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
56347. BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
56348. BIFPLR6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
56349. BIFPLR6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
56350. BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
56351. BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
56352. BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
56353. BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
56354. BIFPLR6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
56355. BIFPLR6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
56356. BIFPLR6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
56357. BIFPLR6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
56358. BIFPLR6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
56359. BIFPLR6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
56360. BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
56361. BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
56362. BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
56363. BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
56364. BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
56365. BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
56366. BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
56367. BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
56368. BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
56369. BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
56370. BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
56371. BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
56372. BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
56373. BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
56374. BIFPLR6_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
56375. BIFPLR6_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
56376. BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
56377. BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
56378. BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
56379. BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
56380. BIFPLR6_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
56381. BIFPLR6_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
56382. BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
56383. BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
56384. BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
56385. BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
56386. BIFPLR6_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
56387. BIFPLR6_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
56388. BIFPLR6_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
56389. BIFPLR6_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
56390. BIFPLR6_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
56391. BIFPLR6_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
56392. BIFPLR6_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
56393. BIFPLR6_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
56394. BIFPLR6_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
56395. BIFPLR6_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
56396. BIFPLR6_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
56397. BIFPLR6_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
56398. BIFPLR6_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
56399. BIFPLR6_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
56400. BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
56401. BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
56402. BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
56403. BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
56404. BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
56405. BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
56406. BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
56407. BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
56408. BIFPLR6_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
56409. BIFPLR6_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
56410. BIFPLR6_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
56411. BIFPLR6_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
56412. BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
56413. BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
56414. BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
56415. BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
56416. BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
56417. BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
56418. BIFPLR6_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
56419. BIFPLR6_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
56420. BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
56421. BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
56422. BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
56423. BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
56424. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK
56425. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
56426. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK
56427. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
56428. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK
56429. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
56430. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK
56431. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
56432. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK
56433. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
56434. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK
56435. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
56436. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK
56437. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
56438. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK
56439. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
56440. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK
56441. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
56442. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK
56443. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
56444. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK
56445. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
56446. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK
56447. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
56448. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK
56449. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
56450. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK
56451. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
56452. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK
56453. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
56454. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK
56455. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
56456. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK
56457. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
56458. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK
56459. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
56460. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK
56461. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
56462. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK
56463. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
56464. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK
56465. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
56466. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK
56467. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
56468. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK
56469. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
56470. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK
56471. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
56472. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK
56473. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
56474. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK
56475. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
56476. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK
56477. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
56478. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK
56479. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
56480. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK
56481. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
56482. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK
56483. BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
56484. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK
56485. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
56486. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK
56487. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
56488. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK
56489. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
56490. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK
56491. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
56492. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK
56493. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
56494. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK
56495. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
56496. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK
56497. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
56498. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK
56499. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
56500. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK
56501. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
56502. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK
56503. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
56504. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK
56505. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
56506. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK
56507. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
56508. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK
56509. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
56510. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK
56511. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
56512. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK
56513. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
56514. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK
56515. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
56516. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK
56517. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
56518. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK
56519. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
56520. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK
56521. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
56522. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK
56523. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
56524. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK
56525. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
56526. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK
56527. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
56528. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK
56529. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
56530. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK
56531. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
56532. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK
56533. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
56534. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK
56535. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
56536. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK
56537. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
56538. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK
56539. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
56540. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK
56541. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
56542. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK
56543. BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
56544. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK
56545. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
56546. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK
56547. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
56548. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK
56549. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
56550. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK
56551. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
56552. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK
56553. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
56554. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK
56555. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
56556. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK
56557. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
56558. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK
56559. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
56560. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK
56561. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
56562. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK
56563. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
56564. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK
56565. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
56566. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK
56567. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
56568. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK
56569. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
56570. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK
56571. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
56572. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK
56573. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
56574. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK
56575. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
56576. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK
56577. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
56578. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK
56579. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
56580. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK
56581. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
56582. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK
56583. BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
56584. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK
56585. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
56586. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK
56587. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
56588. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK
56589. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
56590. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK
56591. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
56592. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK
56593. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
56594. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK
56595. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
56596. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK
56597. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
56598. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK
56599. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
56600. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK
56601. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
56602. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK
56603. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
56604. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK
56605. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
56606. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK
56607. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
56608. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK
56609. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
56610. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK
56611. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
56612. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK
56613. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
56614. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK
56615. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
56616. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK
56617. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
56618. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK
56619. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
56620. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK
56621. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
56622. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK
56623. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
56624. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK
56625. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
56626. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK
56627. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
56628. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK
56629. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
56630. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK
56631. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
56632. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK
56633. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
56634. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK
56635. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
56636. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK
56637. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
56638. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK
56639. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
56640. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK
56641. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
56642. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK
56643. BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
56644. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK
56645. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
56646. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK
56647. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
56648. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK
56649. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
56650. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK
56651. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
56652. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK
56653. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
56654. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK
56655. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
56656. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK
56657. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
56658. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK
56659. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
56660. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK
56661. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
56662. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK
56663. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
56664. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK
56665. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
56666. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK
56667. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
56668. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK
56669. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
56670. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK
56671. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
56672. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK
56673. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
56674. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK
56675. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
56676. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK
56677. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
56678. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK
56679. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
56680. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK
56681. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
56682. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK
56683. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
56684. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK
56685. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
56686. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK
56687. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
56688. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK
56689. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
56690. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK
56691. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
56692. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK
56693. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
56694. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK
56695. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
56696. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK
56697. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
56698. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK
56699. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
56700. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK
56701. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
56702. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK
56703. BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
56704. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK
56705. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
56706. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK
56707. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
56708. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK
56709. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
56710. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK
56711. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
56712. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK
56713. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
56714. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK
56715. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
56716. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK
56717. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
56718. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK
56719. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
56720. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK
56721. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
56722. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK
56723. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
56724. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK
56725. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
56726. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK
56727. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
56728. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK
56729. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
56730. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK
56731. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
56732. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK
56733. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
56734. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK
56735. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
56736. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK
56737. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
56738. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK
56739. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
56740. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK
56741. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
56742. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK
56743. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
56744. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK
56745. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
56746. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK
56747. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
56748. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK
56749. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
56750. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK
56751. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
56752. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK
56753. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
56754. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK
56755. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
56756. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK
56757. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
56758. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK
56759. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
56760. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK
56761. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
56762. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK
56763. BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
56764. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK
56765. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
56766. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK
56767. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
56768. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK
56769. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
56770. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK
56771. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
56772. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK
56773. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
56774. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK
56775. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
56776. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK
56777. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
56778. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK
56779. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
56780. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK
56781. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
56782. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK
56783. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
56784. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK
56785. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
56786. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK
56787. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
56788. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK
56789. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
56790. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK
56791. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
56792. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK
56793. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
56794. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK
56795. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
56796. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK
56797. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
56798. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK
56799. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
56800. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK
56801. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
56802. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK
56803. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
56804. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK
56805. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
56806. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK
56807. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
56808. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK
56809. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
56810. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK
56811. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
56812. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK
56813. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
56814. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK
56815. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
56816. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK
56817. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
56818. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK
56819. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
56820. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK
56821. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
56822. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK
56823. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
56824. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK
56825. BIFPLR6_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
56826. BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK
56827. BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
56828. BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK
56829. BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
56830. BIFPLR6_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
56831. BIFPLR6_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
56832. BIFPLR6_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK
56833. BIFPLR6_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
56834. BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
56835. BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
56836. BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
56837. BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
56838. BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
56839. BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
56840. BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
56841. BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
56842. BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
56843. BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
56844. BIFPLR6_0_PCIE_ESM_HEADER_2__CAP_ID_MASK
56845. BIFPLR6_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
56846. BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
56847. BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
56848. BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
56849. BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
56850. BIFPLR6_0_PCIE_HDR_LOG0__TLP_HDR_MASK
56851. BIFPLR6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
56852. BIFPLR6_0_PCIE_HDR_LOG1__TLP_HDR_MASK
56853. BIFPLR6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
56854. BIFPLR6_0_PCIE_HDR_LOG2__TLP_HDR_MASK
56855. BIFPLR6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
56856. BIFPLR6_0_PCIE_HDR_LOG3__TLP_HDR_MASK
56857. BIFPLR6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
56858. BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
56859. BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
56860. BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
56861. BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
56862. BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
56863. BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
56864. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
56865. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
56866. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
56867. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
56868. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
56869. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
56870. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
56871. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
56872. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
56873. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
56874. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
56875. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
56876. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
56877. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
56878. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
56879. BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
56880. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
56881. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
56882. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
56883. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
56884. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
56885. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
56886. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
56887. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
56888. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
56889. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
56890. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
56891. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
56892. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
56893. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
56894. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
56895. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
56896. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
56897. BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
56898. BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
56899. BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
56900. BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
56901. BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
56902. BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
56903. BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
56904. BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
56905. BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
56906. BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
56907. BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
56908. BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
56909. BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
56910. BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
56911. BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
56912. BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
56913. BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
56914. BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
56915. BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
56916. BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
56917. BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
56918. BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
56919. BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
56920. BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
56921. BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
56922. BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
56923. BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
56924. BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
56925. BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
56926. BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
56927. BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
56928. BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
56929. BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
56930. BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
56931. BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
56932. BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
56933. BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
56934. BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
56935. BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
56936. BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
56937. BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
56938. BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
56939. BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
56940. BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
56941. BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
56942. BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
56943. BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
56944. BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
56945. BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
56946. BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
56947. BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
56948. BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
56949. BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
56950. BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
56951. BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
56952. BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
56953. BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
56954. BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
56955. BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
56956. BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
56957. BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
56958. BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
56959. BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
56960. BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
56961. BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
56962. BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
56963. BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
56964. BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
56965. BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
56966. BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
56967. BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
56968. BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
56969. BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
56970. BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
56971. BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
56972. BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
56973. BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
56974. BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
56975. BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
56976. BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
56977. BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
56978. BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
56979. BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
56980. BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
56981. BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
56982. BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
56983. BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
56984. BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
56985. BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
56986. BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
56987. BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
56988. BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
56989. BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
56990. BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
56991. BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
56992. BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
56993. BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
56994. BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
56995. BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
56996. BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
56997. BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
56998. BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
56999. BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
57000. BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
57001. BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
57002. BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
57003. BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
57004. BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
57005. BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
57006. BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
57007. BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
57008. BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
57009. BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
57010. BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
57011. BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
57012. BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
57013. BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
57014. BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
57015. BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
57016. BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
57017. BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
57018. BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
57019. BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
57020. BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
57021. BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
57022. BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
57023. BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
57024. BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
57025. BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
57026. BIFPLR6_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
57027. BIFPLR6_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
57028. BIFPLR6_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
57029. BIFPLR6_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
57030. BIFPLR6_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
57031. BIFPLR6_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
57032. BIFPLR6_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
57033. BIFPLR6_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
57034. BIFPLR6_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
57035. BIFPLR6_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
57036. BIFPLR6_0_PCIE_LINK_CNTL3__RESERVED_MASK
57037. BIFPLR6_0_PCIE_LINK_CNTL3__RESERVED__SHIFT
57038. BIFPLR6_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
57039. BIFPLR6_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
57040. BIFPLR6_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
57041. BIFPLR6_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
57042. BIFPLR6_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
57043. BIFPLR6_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
57044. BIFPLR6_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
57045. BIFPLR6_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
57046. BIFPLR6_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
57047. BIFPLR6_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
57048. BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
57049. BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
57050. BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
57051. BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
57052. BIFPLR6_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
57053. BIFPLR6_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
57054. BIFPLR6_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK
57055. BIFPLR6_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
57056. BIFPLR6_0_PCIE_MC_CNTL__MC_ENABLE_MASK
57057. BIFPLR6_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT
57058. BIFPLR6_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
57059. BIFPLR6_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
57060. BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
57061. BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
57062. BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
57063. BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
57064. BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
57065. BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
57066. BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
57067. BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
57068. BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
57069. BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
57070. BIFPLR6_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
57071. BIFPLR6_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
57072. BIFPLR6_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
57073. BIFPLR6_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
57074. BIFPLR6_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
57075. BIFPLR6_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
57076. BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
57077. BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
57078. BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
57079. BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
57080. BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
57081. BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
57082. BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
57083. BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
57084. BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
57085. BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
57086. BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
57087. BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
57088. BIFPLR6_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
57089. BIFPLR6_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
57090. BIFPLR6_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
57091. BIFPLR6_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
57092. BIFPLR6_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
57093. BIFPLR6_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
57094. BIFPLR6_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
57095. BIFPLR6_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
57096. BIFPLR6_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
57097. BIFPLR6_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
57098. BIFPLR6_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
57099. BIFPLR6_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
57100. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
57101. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
57102. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
57103. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
57104. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
57105. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
57106. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
57107. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
57108. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
57109. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
57110. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
57111. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
57112. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
57113. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
57114. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
57115. BIFPLR6_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
57116. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
57117. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
57118. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
57119. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
57120. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
57121. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
57122. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
57123. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
57124. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
57125. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
57126. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
57127. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
57128. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
57129. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
57130. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
57131. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
57132. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
57133. BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
57134. BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
57135. BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
57136. BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
57137. BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
57138. BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
57139. BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
57140. BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
57141. BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
57142. BIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
57143. BIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
57144. BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
57145. BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
57146. BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK
57147. BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
57148. BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
57149. BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
57150. BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
57151. BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
57152. BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CTO_MASK
57153. BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
57154. BIFPLR6_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
57155. BIFPLR6_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
57156. BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
57157. BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
57158. BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK
57159. BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
57160. BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
57161. BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
57162. BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
57163. BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
57164. BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
57165. BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
57166. BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
57167. BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
57168. BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
57169. BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
57170. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
57171. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
57172. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
57173. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
57174. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
57175. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
57176. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
57177. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
57178. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
57179. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
57180. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
57181. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
57182. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
57183. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
57184. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
57185. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
57186. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
57187. BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
57188. BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
57189. BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
57190. BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
57191. BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
57192. BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
57193. BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
57194. BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
57195. BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
57196. BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK
57197. BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
57198. BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
57199. BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
57200. BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
57201. BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
57202. BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
57203. BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
57204. BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
57205. BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
57206. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
57207. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
57208. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
57209. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
57210. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
57211. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
57212. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
57213. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
57214. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
57215. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
57216. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
57217. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
57218. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
57219. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
57220. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
57221. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
57222. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
57223. BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
57224. BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
57225. BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
57226. BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
57227. BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
57228. BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
57229. BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
57230. BIFPLR6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
57231. BIFPLR6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
57232. BIFPLR6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
57233. BIFPLR6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
57234. BIFPLR6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
57235. BIFPLR6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
57236. BIFPLR6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
57237. BIFPLR6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
57238. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
57239. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
57240. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
57241. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
57242. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
57243. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
57244. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
57245. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
57246. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
57247. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
57248. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
57249. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
57250. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
57251. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
57252. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
57253. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
57254. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
57255. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
57256. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
57257. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
57258. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
57259. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
57260. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
57261. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
57262. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
57263. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
57264. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
57265. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
57266. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
57267. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
57268. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
57269. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
57270. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
57271. BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
57272. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
57273. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
57274. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
57275. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
57276. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
57277. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
57278. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
57279. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
57280. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
57281. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
57282. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
57283. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
57284. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
57285. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
57286. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
57287. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
57288. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
57289. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
57290. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
57291. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
57292. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
57293. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
57294. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
57295. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
57296. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
57297. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
57298. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
57299. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
57300. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
57301. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
57302. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
57303. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
57304. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
57305. BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
57306. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
57307. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
57308. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
57309. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
57310. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
57311. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
57312. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
57313. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
57314. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
57315. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
57316. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
57317. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
57318. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
57319. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
57320. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
57321. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
57322. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
57323. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
57324. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
57325. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
57326. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
57327. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
57328. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
57329. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
57330. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
57331. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
57332. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
57333. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
57334. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
57335. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
57336. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
57337. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
57338. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
57339. BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
57340. BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
57341. BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
57342. BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
57343. BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
57344. BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
57345. BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
57346. BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
57347. BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
57348. BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
57349. BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
57350. BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
57351. BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
57352. BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
57353. BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
57354. BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
57355. BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
57356. BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
57357. BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
57358. BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
57359. BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
57360. BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
57361. BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
57362. BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
57363. BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
57364. BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
57365. BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
57366. BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
57367. BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
57368. BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
57369. BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
57370. BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
57371. BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
57372. BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
57373. BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
57374. BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
57375. BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
57376. BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
57377. BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
57378. BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
57379. BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
57380. BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
57381. BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
57382. BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
57383. BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
57384. BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
57385. BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
57386. BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
57387. BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
57388. BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
57389. BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
57390. BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
57391. BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
57392. BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
57393. BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
57394. BIFPLR6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
57395. BIFPLR6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
57396. BIFPLR6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
57397. BIFPLR6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
57398. BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
57399. BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
57400. BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
57401. BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
57402. BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
57403. BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
57404. BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
57405. BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
57406. BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
57407. BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
57408. BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
57409. BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
57410. BIFPLR6_0_PMI_CAP_LIST__CAP_ID_MASK
57411. BIFPLR6_0_PMI_CAP_LIST__CAP_ID__SHIFT
57412. BIFPLR6_0_PMI_CAP_LIST__NEXT_PTR_MASK
57413. BIFPLR6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
57414. BIFPLR6_0_PMI_CAP__AUX_CURRENT_MASK
57415. BIFPLR6_0_PMI_CAP__AUX_CURRENT__SHIFT
57416. BIFPLR6_0_PMI_CAP__D1_SUPPORT_MASK
57417. BIFPLR6_0_PMI_CAP__D1_SUPPORT__SHIFT
57418. BIFPLR6_0_PMI_CAP__D2_SUPPORT_MASK
57419. BIFPLR6_0_PMI_CAP__D2_SUPPORT__SHIFT
57420. BIFPLR6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
57421. BIFPLR6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
57422. BIFPLR6_0_PMI_CAP__PME_CLOCK_MASK
57423. BIFPLR6_0_PMI_CAP__PME_CLOCK__SHIFT
57424. BIFPLR6_0_PMI_CAP__PME_SUPPORT_MASK
57425. BIFPLR6_0_PMI_CAP__PME_SUPPORT__SHIFT
57426. BIFPLR6_0_PMI_CAP__VERSION_MASK
57427. BIFPLR6_0_PMI_CAP__VERSION__SHIFT
57428. BIFPLR6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
57429. BIFPLR6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
57430. BIFPLR6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
57431. BIFPLR6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
57432. BIFPLR6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
57433. BIFPLR6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
57434. BIFPLR6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
57435. BIFPLR6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
57436. BIFPLR6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
57437. BIFPLR6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
57438. BIFPLR6_0_PMI_STATUS_CNTL__PME_EN_MASK
57439. BIFPLR6_0_PMI_STATUS_CNTL__PME_EN__SHIFT
57440. BIFPLR6_0_PMI_STATUS_CNTL__PME_STATUS_MASK
57441. BIFPLR6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
57442. BIFPLR6_0_PMI_STATUS_CNTL__PMI_DATA_MASK
57443. BIFPLR6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
57444. BIFPLR6_0_PMI_STATUS_CNTL__POWER_STATE_MASK
57445. BIFPLR6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
57446. BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
57447. BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
57448. BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
57449. BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
57450. BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
57451. BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
57452. BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
57453. BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
57454. BIFPLR6_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
57455. BIFPLR6_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
57456. BIFPLR6_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
57457. BIFPLR6_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
57458. BIFPLR6_0_PROG_INTERFACE__PROG_INTERFACE_MASK
57459. BIFPLR6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
57460. BIFPLR6_0_REVISION_ID__MAJOR_REV_ID_MASK
57461. BIFPLR6_0_REVISION_ID__MAJOR_REV_ID__SHIFT
57462. BIFPLR6_0_REVISION_ID__MINOR_REV_ID_MASK
57463. BIFPLR6_0_REVISION_ID__MINOR_REV_ID__SHIFT
57464. BIFPLR6_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
57465. BIFPLR6_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
57466. BIFPLR6_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
57467. BIFPLR6_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
57468. BIFPLR6_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK
57469. BIFPLR6_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
57470. BIFPLR6_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
57471. BIFPLR6_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
57472. BIFPLR6_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
57473. BIFPLR6_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
57474. BIFPLR6_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
57475. BIFPLR6_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
57476. BIFPLR6_0_ROOT_STATUS__PME_PENDING_MASK
57477. BIFPLR6_0_ROOT_STATUS__PME_PENDING__SHIFT
57478. BIFPLR6_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK
57479. BIFPLR6_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
57480. BIFPLR6_0_ROOT_STATUS__PME_STATUS_MASK
57481. BIFPLR6_0_ROOT_STATUS__PME_STATUS__SHIFT
57482. BIFPLR6_0_SECONDARY_STATUS__CAP_LIST_MASK
57483. BIFPLR6_0_SECONDARY_STATUS__CAP_LIST__SHIFT
57484. BIFPLR6_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK
57485. BIFPLR6_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
57486. BIFPLR6_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
57487. BIFPLR6_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
57488. BIFPLR6_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
57489. BIFPLR6_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
57490. BIFPLR6_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
57491. BIFPLR6_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
57492. BIFPLR6_0_SECONDARY_STATUS__PCI_66_EN_MASK
57493. BIFPLR6_0_SECONDARY_STATUS__PCI_66_EN__SHIFT
57494. BIFPLR6_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
57495. BIFPLR6_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
57496. BIFPLR6_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
57497. BIFPLR6_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
57498. BIFPLR6_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
57499. BIFPLR6_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
57500. BIFPLR6_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
57501. BIFPLR6_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
57502. BIFPLR6_0_SLOT_CAP2__RESERVED_MASK
57503. BIFPLR6_0_SLOT_CAP2__RESERVED__SHIFT
57504. BIFPLR6_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
57505. BIFPLR6_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
57506. BIFPLR6_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
57507. BIFPLR6_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
57508. BIFPLR6_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
57509. BIFPLR6_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
57510. BIFPLR6_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK
57511. BIFPLR6_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
57512. BIFPLR6_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK
57513. BIFPLR6_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
57514. BIFPLR6_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
57515. BIFPLR6_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
57516. BIFPLR6_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
57517. BIFPLR6_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
57518. BIFPLR6_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
57519. BIFPLR6_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
57520. BIFPLR6_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
57521. BIFPLR6_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
57522. BIFPLR6_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
57523. BIFPLR6_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
57524. BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
57525. BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
57526. BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
57527. BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
57528. BIFPLR6_0_SLOT_CNTL2__RESERVED_MASK
57529. BIFPLR6_0_SLOT_CNTL2__RESERVED__SHIFT
57530. BIFPLR6_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
57531. BIFPLR6_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
57532. BIFPLR6_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
57533. BIFPLR6_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
57534. BIFPLR6_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
57535. BIFPLR6_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
57536. BIFPLR6_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
57537. BIFPLR6_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
57538. BIFPLR6_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
57539. BIFPLR6_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
57540. BIFPLR6_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
57541. BIFPLR6_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
57542. BIFPLR6_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
57543. BIFPLR6_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
57544. BIFPLR6_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
57545. BIFPLR6_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
57546. BIFPLR6_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
57547. BIFPLR6_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
57548. BIFPLR6_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
57549. BIFPLR6_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
57550. BIFPLR6_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
57551. BIFPLR6_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
57552. BIFPLR6_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
57553. BIFPLR6_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
57554. BIFPLR6_0_SLOT_STATUS2__RESERVED_MASK
57555. BIFPLR6_0_SLOT_STATUS2__RESERVED__SHIFT
57556. BIFPLR6_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
57557. BIFPLR6_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
57558. BIFPLR6_0_SLOT_STATUS__COMMAND_COMPLETED_MASK
57559. BIFPLR6_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
57560. BIFPLR6_0_SLOT_STATUS__DL_STATE_CHANGED_MASK
57561. BIFPLR6_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
57562. BIFPLR6_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
57563. BIFPLR6_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
57564. BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
57565. BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
57566. BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK
57567. BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
57568. BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
57569. BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
57570. BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
57571. BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
57572. BIFPLR6_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
57573. BIFPLR6_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
57574. BIFPLR6_0_SSID_CAP_LIST__CAP_ID_MASK
57575. BIFPLR6_0_SSID_CAP_LIST__CAP_ID__SHIFT
57576. BIFPLR6_0_SSID_CAP_LIST__NEXT_PTR_MASK
57577. BIFPLR6_0_SSID_CAP_LIST__NEXT_PTR__SHIFT
57578. BIFPLR6_0_SSID_CAP__SUBSYSTEM_ID_MASK
57579. BIFPLR6_0_SSID_CAP__SUBSYSTEM_ID__SHIFT
57580. BIFPLR6_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
57581. BIFPLR6_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
57582. BIFPLR6_0_STATUS__CAP_LIST_MASK
57583. BIFPLR6_0_STATUS__CAP_LIST__SHIFT
57584. BIFPLR6_0_STATUS__DEVSEL_TIMING_MASK
57585. BIFPLR6_0_STATUS__DEVSEL_TIMING__SHIFT
57586. BIFPLR6_0_STATUS__FAST_BACK_CAPABLE_MASK
57587. BIFPLR6_0_STATUS__FAST_BACK_CAPABLE__SHIFT
57588. BIFPLR6_0_STATUS__INT_STATUS_MASK
57589. BIFPLR6_0_STATUS__INT_STATUS__SHIFT
57590. BIFPLR6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
57591. BIFPLR6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
57592. BIFPLR6_0_STATUS__PARITY_ERROR_DETECTED_MASK
57593. BIFPLR6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
57594. BIFPLR6_0_STATUS__PCI_66_EN_MASK
57595. BIFPLR6_0_STATUS__PCI_66_EN__SHIFT
57596. BIFPLR6_0_STATUS__RECEIVED_MASTER_ABORT_MASK
57597. BIFPLR6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
57598. BIFPLR6_0_STATUS__RECEIVED_TARGET_ABORT_MASK
57599. BIFPLR6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
57600. BIFPLR6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
57601. BIFPLR6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
57602. BIFPLR6_0_STATUS__SIGNAL_TARGET_ABORT_MASK
57603. BIFPLR6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
57604. BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
57605. BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
57606. BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
57607. BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
57608. BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
57609. BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
57610. BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
57611. BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
57612. BIFPLR6_0_SUB_CLASS__SUB_CLASS_MASK
57613. BIFPLR6_0_SUB_CLASS__SUB_CLASS__SHIFT
57614. BIFPLR6_0_VENDOR_ID__VENDOR_ID_MASK
57615. BIFPLR6_0_VENDOR_ID__VENDOR_ID__SHIFT
57616. BIFPLR6_1_BASE_CLASS__BASE_CLASS_MASK
57617. BIFPLR6_1_BASE_CLASS__BASE_CLASS__SHIFT
57618. BIFPLR6_1_BIST__BIST_CAP_MASK
57619. BIFPLR6_1_BIST__BIST_CAP__SHIFT
57620. BIFPLR6_1_BIST__BIST_COMP_MASK
57621. BIFPLR6_1_BIST__BIST_COMP__SHIFT
57622. BIFPLR6_1_BIST__BIST_STRT_MASK
57623. BIFPLR6_1_BIST__BIST_STRT__SHIFT
57624. BIFPLR6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
57625. BIFPLR6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
57626. BIFPLR6_1_CAP_PTR__CAP_PTR_MASK
57627. BIFPLR6_1_CAP_PTR__CAP_PTR__SHIFT
57628. BIFPLR6_1_COMMAND__AD_STEPPING_MASK
57629. BIFPLR6_1_COMMAND__AD_STEPPING__SHIFT
57630. BIFPLR6_1_COMMAND__BUS_MASTER_EN_MASK
57631. BIFPLR6_1_COMMAND__BUS_MASTER_EN__SHIFT
57632. BIFPLR6_1_COMMAND__FAST_B2B_EN_MASK
57633. BIFPLR6_1_COMMAND__FAST_B2B_EN__SHIFT
57634. BIFPLR6_1_COMMAND__INT_DIS_MASK
57635. BIFPLR6_1_COMMAND__INT_DIS__SHIFT
57636. BIFPLR6_1_COMMAND__IO_ACCESS_EN_MASK
57637. BIFPLR6_1_COMMAND__IO_ACCESS_EN__SHIFT
57638. BIFPLR6_1_COMMAND__MEM_ACCESS_EN_MASK
57639. BIFPLR6_1_COMMAND__MEM_ACCESS_EN__SHIFT
57640. BIFPLR6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
57641. BIFPLR6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
57642. BIFPLR6_1_COMMAND__PAL_SNOOP_EN_MASK
57643. BIFPLR6_1_COMMAND__PAL_SNOOP_EN__SHIFT
57644. BIFPLR6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
57645. BIFPLR6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
57646. BIFPLR6_1_COMMAND__SERR_EN_MASK
57647. BIFPLR6_1_COMMAND__SERR_EN__SHIFT
57648. BIFPLR6_1_COMMAND__SPECIAL_CYCLE_EN_MASK
57649. BIFPLR6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
57650. BIFPLR6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
57651. BIFPLR6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
57652. BIFPLR6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
57653. BIFPLR6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
57654. BIFPLR6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
57655. BIFPLR6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
57656. BIFPLR6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
57657. BIFPLR6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
57658. BIFPLR6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
57659. BIFPLR6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
57660. BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
57661. BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
57662. BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
57663. BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
57664. BIFPLR6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
57665. BIFPLR6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
57666. BIFPLR6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
57667. BIFPLR6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
57668. BIFPLR6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
57669. BIFPLR6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
57670. BIFPLR6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
57671. BIFPLR6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
57672. BIFPLR6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
57673. BIFPLR6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
57674. BIFPLR6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
57675. BIFPLR6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
57676. BIFPLR6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
57677. BIFPLR6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
57678. BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
57679. BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
57680. BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
57681. BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
57682. BIFPLR6_1_DEVICE_CAP__EXTENDED_TAG_MASK
57683. BIFPLR6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
57684. BIFPLR6_1_DEVICE_CAP__FLR_CAPABLE_MASK
57685. BIFPLR6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
57686. BIFPLR6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
57687. BIFPLR6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
57688. BIFPLR6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
57689. BIFPLR6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
57690. BIFPLR6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
57691. BIFPLR6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
57692. BIFPLR6_1_DEVICE_CAP__PHANTOM_FUNC_MASK
57693. BIFPLR6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
57694. BIFPLR6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
57695. BIFPLR6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
57696. BIFPLR6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
57697. BIFPLR6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
57698. BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
57699. BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
57700. BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
57701. BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
57702. BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
57703. BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
57704. BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
57705. BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
57706. BIFPLR6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
57707. BIFPLR6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
57708. BIFPLR6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
57709. BIFPLR6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
57710. BIFPLR6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
57711. BIFPLR6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
57712. BIFPLR6_1_DEVICE_CNTL2__LTR_EN_MASK
57713. BIFPLR6_1_DEVICE_CNTL2__LTR_EN__SHIFT
57714. BIFPLR6_1_DEVICE_CNTL2__OBFF_EN_MASK
57715. BIFPLR6_1_DEVICE_CNTL2__OBFF_EN__SHIFT
57716. BIFPLR6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
57717. BIFPLR6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
57718. BIFPLR6_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
57719. BIFPLR6_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
57720. BIFPLR6_1_DEVICE_CNTL__CORR_ERR_EN_MASK
57721. BIFPLR6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
57722. BIFPLR6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
57723. BIFPLR6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
57724. BIFPLR6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
57725. BIFPLR6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
57726. BIFPLR6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
57727. BIFPLR6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
57728. BIFPLR6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
57729. BIFPLR6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
57730. BIFPLR6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
57731. BIFPLR6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
57732. BIFPLR6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
57733. BIFPLR6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
57734. BIFPLR6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
57735. BIFPLR6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
57736. BIFPLR6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
57737. BIFPLR6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
57738. BIFPLR6_1_DEVICE_CNTL__USR_REPORT_EN_MASK
57739. BIFPLR6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
57740. BIFPLR6_1_DEVICE_ID__DEVICE_ID_MASK
57741. BIFPLR6_1_DEVICE_ID__DEVICE_ID__SHIFT
57742. BIFPLR6_1_DEVICE_STATUS2__RESERVED_MASK
57743. BIFPLR6_1_DEVICE_STATUS2__RESERVED__SHIFT
57744. BIFPLR6_1_DEVICE_STATUS__AUX_PWR_MASK
57745. BIFPLR6_1_DEVICE_STATUS__AUX_PWR__SHIFT
57746. BIFPLR6_1_DEVICE_STATUS__CORR_ERR_MASK
57747. BIFPLR6_1_DEVICE_STATUS__CORR_ERR__SHIFT
57748. BIFPLR6_1_DEVICE_STATUS__FATAL_ERR_MASK
57749. BIFPLR6_1_DEVICE_STATUS__FATAL_ERR__SHIFT
57750. BIFPLR6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
57751. BIFPLR6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
57752. BIFPLR6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
57753. BIFPLR6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
57754. BIFPLR6_1_DEVICE_STATUS__USR_DETECTED_MASK
57755. BIFPLR6_1_DEVICE_STATUS__USR_DETECTED__SHIFT
57756. BIFPLR6_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
57757. BIFPLR6_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
57758. BIFPLR6_1_HEADER__DEVICE_TYPE_MASK
57759. BIFPLR6_1_HEADER__DEVICE_TYPE__SHIFT
57760. BIFPLR6_1_HEADER__HEADER_TYPE_MASK
57761. BIFPLR6_1_HEADER__HEADER_TYPE__SHIFT
57762. BIFPLR6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
57763. BIFPLR6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
57764. BIFPLR6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
57765. BIFPLR6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
57766. BIFPLR6_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
57767. BIFPLR6_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
57768. BIFPLR6_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
57769. BIFPLR6_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
57770. BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_MASK
57771. BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
57772. BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
57773. BIFPLR6_1_IO_BASE_LIMIT__IO_BASE__SHIFT
57774. BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_MASK
57775. BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
57776. BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
57777. BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT
57778. BIFPLR6_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
57779. BIFPLR6_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
57780. BIFPLR6_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK
57781. BIFPLR6_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
57782. BIFPLR6_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
57783. BIFPLR6_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
57784. BIFPLR6_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
57785. BIFPLR6_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
57786. BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
57787. BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
57788. BIFPLR6_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK
57789. BIFPLR6_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
57790. BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
57791. BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
57792. BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK
57793. BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
57794. BIFPLR6_1_LATENCY__LATENCY_TIMER_MASK
57795. BIFPLR6_1_LATENCY__LATENCY_TIMER__SHIFT
57796. BIFPLR6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
57797. BIFPLR6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
57798. BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
57799. BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
57800. BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
57801. BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
57802. BIFPLR6_1_LINK_CAP2__RESERVED_MASK
57803. BIFPLR6_1_LINK_CAP2__RESERVED__SHIFT
57804. BIFPLR6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
57805. BIFPLR6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
57806. BIFPLR6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
57807. BIFPLR6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
57808. BIFPLR6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
57809. BIFPLR6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
57810. BIFPLR6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
57811. BIFPLR6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
57812. BIFPLR6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
57813. BIFPLR6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
57814. BIFPLR6_1_LINK_CAP__L1_EXIT_LATENCY_MASK
57815. BIFPLR6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
57816. BIFPLR6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
57817. BIFPLR6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
57818. BIFPLR6_1_LINK_CAP__LINK_SPEED_MASK
57819. BIFPLR6_1_LINK_CAP__LINK_SPEED__SHIFT
57820. BIFPLR6_1_LINK_CAP__LINK_WIDTH_MASK
57821. BIFPLR6_1_LINK_CAP__LINK_WIDTH__SHIFT
57822. BIFPLR6_1_LINK_CAP__PM_SUPPORT_MASK
57823. BIFPLR6_1_LINK_CAP__PM_SUPPORT__SHIFT
57824. BIFPLR6_1_LINK_CAP__PORT_NUMBER_MASK
57825. BIFPLR6_1_LINK_CAP__PORT_NUMBER__SHIFT
57826. BIFPLR6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
57827. BIFPLR6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
57828. BIFPLR6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
57829. BIFPLR6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
57830. BIFPLR6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
57831. BIFPLR6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
57832. BIFPLR6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
57833. BIFPLR6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
57834. BIFPLR6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
57835. BIFPLR6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
57836. BIFPLR6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
57837. BIFPLR6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
57838. BIFPLR6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
57839. BIFPLR6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
57840. BIFPLR6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
57841. BIFPLR6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
57842. BIFPLR6_1_LINK_CNTL2__XMIT_MARGIN_MASK
57843. BIFPLR6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
57844. BIFPLR6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
57845. BIFPLR6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
57846. BIFPLR6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
57847. BIFPLR6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
57848. BIFPLR6_1_LINK_CNTL__EXTENDED_SYNC_MASK
57849. BIFPLR6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
57850. BIFPLR6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
57851. BIFPLR6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
57852. BIFPLR6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
57853. BIFPLR6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
57854. BIFPLR6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
57855. BIFPLR6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
57856. BIFPLR6_1_LINK_CNTL__LINK_DIS_MASK
57857. BIFPLR6_1_LINK_CNTL__LINK_DIS__SHIFT
57858. BIFPLR6_1_LINK_CNTL__PM_CONTROL_MASK
57859. BIFPLR6_1_LINK_CNTL__PM_CONTROL__SHIFT
57860. BIFPLR6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
57861. BIFPLR6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
57862. BIFPLR6_1_LINK_CNTL__RETRAIN_LINK_MASK
57863. BIFPLR6_1_LINK_CNTL__RETRAIN_LINK__SHIFT
57864. BIFPLR6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
57865. BIFPLR6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
57866. BIFPLR6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
57867. BIFPLR6_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
57868. BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
57869. BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
57870. BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
57871. BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
57872. BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
57873. BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
57874. BIFPLR6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
57875. BIFPLR6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
57876. BIFPLR6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
57877. BIFPLR6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
57878. BIFPLR6_1_LINK_STATUS__DL_ACTIVE_MASK
57879. BIFPLR6_1_LINK_STATUS__DL_ACTIVE__SHIFT
57880. BIFPLR6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
57881. BIFPLR6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
57882. BIFPLR6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
57883. BIFPLR6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
57884. BIFPLR6_1_LINK_STATUS__LINK_TRAINING_MASK
57885. BIFPLR6_1_LINK_STATUS__LINK_TRAINING__SHIFT
57886. BIFPLR6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
57887. BIFPLR6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
57888. BIFPLR6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
57889. BIFPLR6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
57890. BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
57891. BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
57892. BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
57893. BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
57894. BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
57895. BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
57896. BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
57897. BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
57898. BIFPLR6_1_MSI_CAP_LIST__CAP_ID_MASK
57899. BIFPLR6_1_MSI_CAP_LIST__CAP_ID__SHIFT
57900. BIFPLR6_1_MSI_CAP_LIST__NEXT_PTR_MASK
57901. BIFPLR6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
57902. BIFPLR6_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
57903. BIFPLR6_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
57904. BIFPLR6_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
57905. BIFPLR6_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
57906. BIFPLR6_1_MSI_MAP_CAP_LIST__CAP_ID_MASK
57907. BIFPLR6_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
57908. BIFPLR6_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
57909. BIFPLR6_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
57910. BIFPLR6_1_MSI_MAP_CAP__CAP_TYPE_MASK
57911. BIFPLR6_1_MSI_MAP_CAP__CAP_TYPE__SHIFT
57912. BIFPLR6_1_MSI_MAP_CAP__EN_MASK
57913. BIFPLR6_1_MSI_MAP_CAP__EN__SHIFT
57914. BIFPLR6_1_MSI_MAP_CAP__FIXD_MASK
57915. BIFPLR6_1_MSI_MAP_CAP__FIXD__SHIFT
57916. BIFPLR6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
57917. BIFPLR6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
57918. BIFPLR6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
57919. BIFPLR6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
57920. BIFPLR6_1_MSI_MSG_CNTL__MSI_64BIT_MASK
57921. BIFPLR6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
57922. BIFPLR6_1_MSI_MSG_CNTL__MSI_EN_MASK
57923. BIFPLR6_1_MSI_MSG_CNTL__MSI_EN__SHIFT
57924. BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
57925. BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
57926. BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
57927. BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
57928. BIFPLR6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
57929. BIFPLR6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
57930. BIFPLR6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
57931. BIFPLR6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
57932. BIFPLR6_1_MSI_MSG_DATA__MSI_DATA_MASK
57933. BIFPLR6_1_MSI_MSG_DATA__MSI_DATA__SHIFT
57934. BIFPLR6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
57935. BIFPLR6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
57936. BIFPLR6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
57937. BIFPLR6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
57938. BIFPLR6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
57939. BIFPLR6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
57940. BIFPLR6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
57941. BIFPLR6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
57942. BIFPLR6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
57943. BIFPLR6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
57944. BIFPLR6_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
57945. BIFPLR6_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
57946. BIFPLR6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
57947. BIFPLR6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
57948. BIFPLR6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
57949. BIFPLR6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
57950. BIFPLR6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
57951. BIFPLR6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
57952. BIFPLR6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
57953. BIFPLR6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
57954. BIFPLR6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
57955. BIFPLR6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
57956. BIFPLR6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
57957. BIFPLR6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
57958. BIFPLR6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
57959. BIFPLR6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
57960. BIFPLR6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
57961. BIFPLR6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
57962. BIFPLR6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
57963. BIFPLR6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
57964. BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
57965. BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
57966. BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
57967. BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
57968. BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
57969. BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
57970. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
57971. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
57972. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
57973. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
57974. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
57975. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
57976. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
57977. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
57978. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
57979. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
57980. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
57981. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
57982. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
57983. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
57984. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
57985. BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
57986. BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
57987. BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
57988. BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
57989. BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
57990. BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
57991. BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
57992. BIFPLR6_1_PCIE_CAP_LIST__CAP_ID_MASK
57993. BIFPLR6_1_PCIE_CAP_LIST__CAP_ID__SHIFT
57994. BIFPLR6_1_PCIE_CAP_LIST__NEXT_PTR_MASK
57995. BIFPLR6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
57996. BIFPLR6_1_PCIE_CAP__DEVICE_TYPE_MASK
57997. BIFPLR6_1_PCIE_CAP__DEVICE_TYPE__SHIFT
57998. BIFPLR6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
57999. BIFPLR6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
58000. BIFPLR6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
58001. BIFPLR6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
58002. BIFPLR6_1_PCIE_CAP__VERSION_MASK
58003. BIFPLR6_1_PCIE_CAP__VERSION__SHIFT
58004. BIFPLR6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
58005. BIFPLR6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
58006. BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
58007. BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
58008. BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
58009. BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
58010. BIFPLR6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
58011. BIFPLR6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
58012. BIFPLR6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
58013. BIFPLR6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
58014. BIFPLR6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
58015. BIFPLR6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
58016. BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
58017. BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
58018. BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
58019. BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
58020. BIFPLR6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
58021. BIFPLR6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
58022. BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
58023. BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
58024. BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
58025. BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
58026. BIFPLR6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
58027. BIFPLR6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
58028. BIFPLR6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
58029. BIFPLR6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
58030. BIFPLR6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
58031. BIFPLR6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
58032. BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
58033. BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
58034. BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
58035. BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
58036. BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
58037. BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
58038. BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
58039. BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
58040. BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
58041. BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
58042. BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
58043. BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
58044. BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
58045. BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
58046. BIFPLR6_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
58047. BIFPLR6_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
58048. BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
58049. BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
58050. BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
58051. BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
58052. BIFPLR6_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
58053. BIFPLR6_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
58054. BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
58055. BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
58056. BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
58057. BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
58058. BIFPLR6_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
58059. BIFPLR6_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
58060. BIFPLR6_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
58061. BIFPLR6_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
58062. BIFPLR6_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
58063. BIFPLR6_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
58064. BIFPLR6_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
58065. BIFPLR6_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
58066. BIFPLR6_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
58067. BIFPLR6_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
58068. BIFPLR6_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
58069. BIFPLR6_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
58070. BIFPLR6_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
58071. BIFPLR6_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
58072. BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
58073. BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
58074. BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
58075. BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
58076. BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
58077. BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
58078. BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
58079. BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
58080. BIFPLR6_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
58081. BIFPLR6_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
58082. BIFPLR6_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
58083. BIFPLR6_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
58084. BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
58085. BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
58086. BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
58087. BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
58088. BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
58089. BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
58090. BIFPLR6_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
58091. BIFPLR6_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
58092. BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
58093. BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
58094. BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
58095. BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
58096. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK
58097. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
58098. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK
58099. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
58100. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK
58101. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
58102. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK
58103. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
58104. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK
58105. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
58106. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK
58107. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
58108. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK
58109. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
58110. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK
58111. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
58112. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK
58113. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
58114. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK
58115. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
58116. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK
58117. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
58118. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK
58119. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
58120. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK
58121. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
58122. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK
58123. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
58124. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK
58125. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
58126. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK
58127. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
58128. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK
58129. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
58130. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK
58131. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
58132. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK
58133. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
58134. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK
58135. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
58136. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK
58137. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
58138. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK
58139. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
58140. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK
58141. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
58142. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK
58143. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
58144. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK
58145. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
58146. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK
58147. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
58148. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK
58149. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
58150. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK
58151. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
58152. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK
58153. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
58154. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK
58155. BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
58156. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK
58157. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
58158. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK
58159. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
58160. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK
58161. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
58162. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK
58163. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
58164. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK
58165. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
58166. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK
58167. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
58168. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK
58169. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
58170. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK
58171. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
58172. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK
58173. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
58174. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK
58175. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
58176. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK
58177. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
58178. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK
58179. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
58180. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK
58181. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
58182. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK
58183. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
58184. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK
58185. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
58186. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK
58187. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
58188. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK
58189. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
58190. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK
58191. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
58192. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK
58193. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
58194. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK
58195. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
58196. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK
58197. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
58198. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK
58199. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
58200. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK
58201. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
58202. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK
58203. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
58204. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK
58205. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
58206. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK
58207. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
58208. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK
58209. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
58210. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK
58211. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
58212. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK
58213. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
58214. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK
58215. BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
58216. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK
58217. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
58218. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK
58219. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
58220. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK
58221. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
58222. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK
58223. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
58224. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK
58225. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
58226. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK
58227. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
58228. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK
58229. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
58230. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK
58231. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
58232. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK
58233. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
58234. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK
58235. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
58236. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK
58237. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
58238. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK
58239. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
58240. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK
58241. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
58242. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK
58243. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
58244. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK
58245. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
58246. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK
58247. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
58248. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK
58249. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
58250. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK
58251. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
58252. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK
58253. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
58254. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK
58255. BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
58256. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK
58257. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
58258. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK
58259. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
58260. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK
58261. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
58262. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK
58263. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
58264. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK
58265. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
58266. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK
58267. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
58268. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK
58269. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
58270. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK
58271. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
58272. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK
58273. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
58274. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK
58275. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
58276. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK
58277. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
58278. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK
58279. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
58280. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK
58281. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
58282. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK
58283. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
58284. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK
58285. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
58286. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK
58287. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
58288. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK
58289. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
58290. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK
58291. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
58292. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK
58293. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
58294. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK
58295. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
58296. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK
58297. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
58298. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK
58299. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
58300. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK
58301. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
58302. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK
58303. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
58304. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK
58305. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
58306. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK
58307. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
58308. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK
58309. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
58310. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK
58311. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
58312. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK
58313. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
58314. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK
58315. BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
58316. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK
58317. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
58318. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK
58319. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
58320. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK
58321. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
58322. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK
58323. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
58324. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK
58325. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
58326. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK
58327. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
58328. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK
58329. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
58330. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK
58331. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
58332. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK
58333. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
58334. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK
58335. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
58336. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK
58337. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
58338. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK
58339. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
58340. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK
58341. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
58342. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK
58343. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
58344. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK
58345. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
58346. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK
58347. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
58348. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK
58349. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
58350. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK
58351. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
58352. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK
58353. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
58354. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK
58355. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
58356. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK
58357. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
58358. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK
58359. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
58360. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK
58361. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
58362. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK
58363. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
58364. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK
58365. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
58366. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK
58367. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
58368. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK
58369. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
58370. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK
58371. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
58372. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK
58373. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
58374. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK
58375. BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
58376. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK
58377. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
58378. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK
58379. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
58380. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK
58381. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
58382. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK
58383. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
58384. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK
58385. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
58386. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK
58387. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
58388. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK
58389. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
58390. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK
58391. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
58392. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK
58393. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
58394. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK
58395. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
58396. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK
58397. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
58398. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK
58399. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
58400. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK
58401. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
58402. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK
58403. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
58404. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK
58405. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
58406. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK
58407. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
58408. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK
58409. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
58410. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK
58411. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
58412. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK
58413. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
58414. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK
58415. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
58416. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK
58417. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
58418. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK
58419. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
58420. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK
58421. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
58422. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK
58423. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
58424. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK
58425. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
58426. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK
58427. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
58428. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK
58429. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
58430. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK
58431. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
58432. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK
58433. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
58434. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK
58435. BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
58436. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK
58437. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
58438. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK
58439. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
58440. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK
58441. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
58442. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK
58443. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
58444. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK
58445. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
58446. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK
58447. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
58448. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK
58449. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
58450. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK
58451. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
58452. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK
58453. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
58454. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK
58455. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
58456. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK
58457. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
58458. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK
58459. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
58460. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK
58461. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
58462. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK
58463. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
58464. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK
58465. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
58466. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK
58467. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
58468. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK
58469. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
58470. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK
58471. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
58472. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK
58473. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
58474. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK
58475. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
58476. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK
58477. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
58478. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK
58479. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
58480. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK
58481. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
58482. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK
58483. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
58484. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK
58485. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
58486. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK
58487. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
58488. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK
58489. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
58490. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK
58491. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
58492. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK
58493. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
58494. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK
58495. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
58496. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK
58497. BIFPLR6_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
58498. BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK
58499. BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
58500. BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK
58501. BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
58502. BIFPLR6_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
58503. BIFPLR6_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
58504. BIFPLR6_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK
58505. BIFPLR6_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
58506. BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
58507. BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
58508. BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
58509. BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
58510. BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
58511. BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
58512. BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
58513. BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
58514. BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
58515. BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
58516. BIFPLR6_1_PCIE_ESM_HEADER_2__CAP_ID_MASK
58517. BIFPLR6_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
58518. BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
58519. BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
58520. BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
58521. BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
58522. BIFPLR6_1_PCIE_HDR_LOG0__TLP_HDR_MASK
58523. BIFPLR6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
58524. BIFPLR6_1_PCIE_HDR_LOG1__TLP_HDR_MASK
58525. BIFPLR6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
58526. BIFPLR6_1_PCIE_HDR_LOG2__TLP_HDR_MASK
58527. BIFPLR6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
58528. BIFPLR6_1_PCIE_HDR_LOG3__TLP_HDR_MASK
58529. BIFPLR6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
58530. BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
58531. BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
58532. BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
58533. BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
58534. BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
58535. BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
58536. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
58537. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
58538. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
58539. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
58540. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
58541. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
58542. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
58543. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
58544. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
58545. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
58546. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
58547. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
58548. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
58549. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
58550. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
58551. BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
58552. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
58553. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
58554. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
58555. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
58556. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
58557. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
58558. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
58559. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
58560. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
58561. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
58562. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
58563. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
58564. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
58565. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
58566. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
58567. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
58568. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
58569. BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
58570. BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58571. BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58572. BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58573. BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58574. BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58575. BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58576. BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58577. BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58578. BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58579. BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58580. BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58581. BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58582. BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58583. BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58584. BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58585. BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58586. BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58587. BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58588. BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58589. BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58590. BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58591. BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58592. BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58593. BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58594. BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58595. BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58596. BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58597. BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58598. BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58599. BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58600. BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58601. BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58602. BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58603. BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58604. BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58605. BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58606. BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58607. BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58608. BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58609. BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58610. BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58611. BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58612. BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58613. BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58614. BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58615. BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58616. BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58617. BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58618. BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58619. BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58620. BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58621. BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58622. BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58623. BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58624. BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58625. BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58626. BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58627. BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58628. BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58629. BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58630. BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58631. BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58632. BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58633. BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58634. BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58635. BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58636. BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58637. BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58638. BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58639. BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58640. BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58641. BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58642. BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58643. BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58644. BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58645. BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58646. BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58647. BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58648. BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58649. BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58650. BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58651. BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58652. BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58653. BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58654. BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58655. BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58656. BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58657. BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58658. BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58659. BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58660. BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58661. BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58662. BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58663. BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58664. BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58665. BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58666. BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58667. BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58668. BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58669. BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58670. BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58671. BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58672. BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58673. BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58674. BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58675. BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58676. BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58677. BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58678. BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58679. BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58680. BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58681. BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58682. BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58683. BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58684. BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58685. BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58686. BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58687. BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58688. BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58689. BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58690. BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
58691. BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
58692. BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
58693. BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
58694. BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
58695. BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
58696. BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
58697. BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
58698. BIFPLR6_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
58699. BIFPLR6_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
58700. BIFPLR6_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
58701. BIFPLR6_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
58702. BIFPLR6_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
58703. BIFPLR6_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
58704. BIFPLR6_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
58705. BIFPLR6_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
58706. BIFPLR6_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
58707. BIFPLR6_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
58708. BIFPLR6_1_PCIE_LINK_CNTL3__RESERVED_MASK
58709. BIFPLR6_1_PCIE_LINK_CNTL3__RESERVED__SHIFT
58710. BIFPLR6_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
58711. BIFPLR6_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
58712. BIFPLR6_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
58713. BIFPLR6_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
58714. BIFPLR6_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
58715. BIFPLR6_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
58716. BIFPLR6_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
58717. BIFPLR6_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
58718. BIFPLR6_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
58719. BIFPLR6_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
58720. BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
58721. BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
58722. BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
58723. BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
58724. BIFPLR6_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
58725. BIFPLR6_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
58726. BIFPLR6_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK
58727. BIFPLR6_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
58728. BIFPLR6_1_PCIE_MC_CNTL__MC_ENABLE_MASK
58729. BIFPLR6_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT
58730. BIFPLR6_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
58731. BIFPLR6_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
58732. BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
58733. BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
58734. BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
58735. BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
58736. BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
58737. BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
58738. BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
58739. BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
58740. BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
58741. BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
58742. BIFPLR6_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
58743. BIFPLR6_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
58744. BIFPLR6_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
58745. BIFPLR6_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
58746. BIFPLR6_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
58747. BIFPLR6_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
58748. BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
58749. BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
58750. BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
58751. BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
58752. BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
58753. BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
58754. BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
58755. BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
58756. BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
58757. BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
58758. BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
58759. BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
58760. BIFPLR6_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
58761. BIFPLR6_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
58762. BIFPLR6_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
58763. BIFPLR6_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
58764. BIFPLR6_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
58765. BIFPLR6_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
58766. BIFPLR6_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
58767. BIFPLR6_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
58768. BIFPLR6_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
58769. BIFPLR6_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
58770. BIFPLR6_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
58771. BIFPLR6_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
58772. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
58773. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
58774. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
58775. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
58776. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
58777. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
58778. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
58779. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
58780. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
58781. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
58782. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
58783. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
58784. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
58785. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
58786. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
58787. BIFPLR6_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
58788. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
58789. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
58790. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
58791. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
58792. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
58793. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
58794. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
58795. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
58796. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
58797. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
58798. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
58799. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
58800. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
58801. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
58802. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
58803. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
58804. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
58805. BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
58806. BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
58807. BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
58808. BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
58809. BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
58810. BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
58811. BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
58812. BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
58813. BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
58814. BIFPLR6_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
58815. BIFPLR6_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
58816. BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
58817. BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
58818. BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK
58819. BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
58820. BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
58821. BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
58822. BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
58823. BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
58824. BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CTO_MASK
58825. BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
58826. BIFPLR6_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
58827. BIFPLR6_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
58828. BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
58829. BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
58830. BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK
58831. BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
58832. BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
58833. BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
58834. BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
58835. BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
58836. BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
58837. BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
58838. BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
58839. BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
58840. BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
58841. BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
58842. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
58843. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
58844. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
58845. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
58846. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
58847. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
58848. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
58849. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
58850. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
58851. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
58852. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
58853. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
58854. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
58855. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
58856. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
58857. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
58858. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
58859. BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
58860. BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
58861. BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
58862. BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
58863. BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
58864. BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
58865. BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
58866. BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
58867. BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
58868. BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK
58869. BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
58870. BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
58871. BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
58872. BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
58873. BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
58874. BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
58875. BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
58876. BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
58877. BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
58878. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
58879. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
58880. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
58881. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
58882. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
58883. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
58884. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
58885. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
58886. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
58887. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
58888. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
58889. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
58890. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
58891. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
58892. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
58893. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
58894. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
58895. BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
58896. BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
58897. BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
58898. BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
58899. BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
58900. BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
58901. BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
58902. BIFPLR6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
58903. BIFPLR6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
58904. BIFPLR6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
58905. BIFPLR6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
58906. BIFPLR6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
58907. BIFPLR6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
58908. BIFPLR6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
58909. BIFPLR6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
58910. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
58911. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
58912. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
58913. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
58914. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
58915. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
58916. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
58917. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
58918. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
58919. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
58920. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
58921. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
58922. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
58923. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
58924. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
58925. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
58926. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
58927. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
58928. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
58929. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
58930. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
58931. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
58932. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
58933. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
58934. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
58935. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
58936. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
58937. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
58938. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
58939. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
58940. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
58941. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
58942. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
58943. BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
58944. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
58945. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
58946. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
58947. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
58948. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
58949. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
58950. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
58951. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
58952. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
58953. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
58954. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
58955. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
58956. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
58957. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
58958. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
58959. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
58960. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
58961. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
58962. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
58963. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
58964. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
58965. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
58966. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
58967. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
58968. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
58969. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
58970. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
58971. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
58972. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
58973. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
58974. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
58975. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
58976. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
58977. BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
58978. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
58979. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
58980. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
58981. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
58982. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
58983. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
58984. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
58985. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
58986. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
58987. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
58988. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
58989. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
58990. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
58991. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
58992. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
58993. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
58994. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
58995. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
58996. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
58997. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
58998. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
58999. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
59000. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
59001. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
59002. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
59003. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
59004. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
59005. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
59006. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
59007. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
59008. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
59009. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
59010. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
59011. BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
59012. BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
59013. BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
59014. BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
59015. BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
59016. BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
59017. BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
59018. BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
59019. BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
59020. BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
59021. BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
59022. BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
59023. BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
59024. BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
59025. BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
59026. BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
59027. BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
59028. BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
59029. BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
59030. BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
59031. BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
59032. BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
59033. BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
59034. BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
59035. BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
59036. BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
59037. BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
59038. BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
59039. BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
59040. BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
59041. BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
59042. BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
59043. BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
59044. BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
59045. BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
59046. BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
59047. BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
59048. BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
59049. BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
59050. BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
59051. BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
59052. BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
59053. BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
59054. BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
59055. BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
59056. BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
59057. BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
59058. BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
59059. BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
59060. BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
59061. BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
59062. BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
59063. BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
59064. BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
59065. BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
59066. BIFPLR6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
59067. BIFPLR6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
59068. BIFPLR6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
59069. BIFPLR6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
59070. BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
59071. BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
59072. BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
59073. BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
59074. BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
59075. BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
59076. BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
59077. BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
59078. BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
59079. BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
59080. BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
59081. BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
59082. BIFPLR6_1_PMI_CAP_LIST__CAP_ID_MASK
59083. BIFPLR6_1_PMI_CAP_LIST__CAP_ID__SHIFT
59084. BIFPLR6_1_PMI_CAP_LIST__NEXT_PTR_MASK
59085. BIFPLR6_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
59086. BIFPLR6_1_PMI_CAP__AUX_CURRENT_MASK
59087. BIFPLR6_1_PMI_CAP__AUX_CURRENT__SHIFT
59088. BIFPLR6_1_PMI_CAP__D1_SUPPORT_MASK
59089. BIFPLR6_1_PMI_CAP__D1_SUPPORT__SHIFT
59090. BIFPLR6_1_PMI_CAP__D2_SUPPORT_MASK
59091. BIFPLR6_1_PMI_CAP__D2_SUPPORT__SHIFT
59092. BIFPLR6_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
59093. BIFPLR6_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
59094. BIFPLR6_1_PMI_CAP__PME_CLOCK_MASK
59095. BIFPLR6_1_PMI_CAP__PME_CLOCK__SHIFT
59096. BIFPLR6_1_PMI_CAP__PME_SUPPORT_MASK
59097. BIFPLR6_1_PMI_CAP__PME_SUPPORT__SHIFT
59098. BIFPLR6_1_PMI_CAP__VERSION_MASK
59099. BIFPLR6_1_PMI_CAP__VERSION__SHIFT
59100. BIFPLR6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
59101. BIFPLR6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
59102. BIFPLR6_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
59103. BIFPLR6_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
59104. BIFPLR6_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
59105. BIFPLR6_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
59106. BIFPLR6_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
59107. BIFPLR6_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
59108. BIFPLR6_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
59109. BIFPLR6_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
59110. BIFPLR6_1_PMI_STATUS_CNTL__PME_EN_MASK
59111. BIFPLR6_1_PMI_STATUS_CNTL__PME_EN__SHIFT
59112. BIFPLR6_1_PMI_STATUS_CNTL__PME_STATUS_MASK
59113. BIFPLR6_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
59114. BIFPLR6_1_PMI_STATUS_CNTL__PMI_DATA_MASK
59115. BIFPLR6_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
59116. BIFPLR6_1_PMI_STATUS_CNTL__POWER_STATE_MASK
59117. BIFPLR6_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
59118. BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
59119. BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
59120. BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
59121. BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
59122. BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
59123. BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
59124. BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
59125. BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
59126. BIFPLR6_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
59127. BIFPLR6_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
59128. BIFPLR6_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
59129. BIFPLR6_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
59130. BIFPLR6_1_PROG_INTERFACE__PROG_INTERFACE_MASK
59131. BIFPLR6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
59132. BIFPLR6_1_REVISION_ID__MAJOR_REV_ID_MASK
59133. BIFPLR6_1_REVISION_ID__MAJOR_REV_ID__SHIFT
59134. BIFPLR6_1_REVISION_ID__MINOR_REV_ID_MASK
59135. BIFPLR6_1_REVISION_ID__MINOR_REV_ID__SHIFT
59136. BIFPLR6_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
59137. BIFPLR6_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
59138. BIFPLR6_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
59139. BIFPLR6_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
59140. BIFPLR6_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK
59141. BIFPLR6_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
59142. BIFPLR6_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
59143. BIFPLR6_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
59144. BIFPLR6_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
59145. BIFPLR6_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
59146. BIFPLR6_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
59147. BIFPLR6_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
59148. BIFPLR6_1_ROOT_STATUS__PME_PENDING_MASK
59149. BIFPLR6_1_ROOT_STATUS__PME_PENDING__SHIFT
59150. BIFPLR6_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK
59151. BIFPLR6_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
59152. BIFPLR6_1_ROOT_STATUS__PME_STATUS_MASK
59153. BIFPLR6_1_ROOT_STATUS__PME_STATUS__SHIFT
59154. BIFPLR6_1_SECONDARY_STATUS__CAP_LIST_MASK
59155. BIFPLR6_1_SECONDARY_STATUS__CAP_LIST__SHIFT
59156. BIFPLR6_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK
59157. BIFPLR6_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
59158. BIFPLR6_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
59159. BIFPLR6_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
59160. BIFPLR6_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
59161. BIFPLR6_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
59162. BIFPLR6_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
59163. BIFPLR6_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
59164. BIFPLR6_1_SECONDARY_STATUS__PCI_66_EN_MASK
59165. BIFPLR6_1_SECONDARY_STATUS__PCI_66_EN__SHIFT
59166. BIFPLR6_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
59167. BIFPLR6_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
59168. BIFPLR6_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
59169. BIFPLR6_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
59170. BIFPLR6_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
59171. BIFPLR6_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
59172. BIFPLR6_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
59173. BIFPLR6_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
59174. BIFPLR6_1_SLOT_CAP2__RESERVED_MASK
59175. BIFPLR6_1_SLOT_CAP2__RESERVED__SHIFT
59176. BIFPLR6_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
59177. BIFPLR6_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
59178. BIFPLR6_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
59179. BIFPLR6_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
59180. BIFPLR6_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
59181. BIFPLR6_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
59182. BIFPLR6_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK
59183. BIFPLR6_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
59184. BIFPLR6_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK
59185. BIFPLR6_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
59186. BIFPLR6_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
59187. BIFPLR6_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
59188. BIFPLR6_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
59189. BIFPLR6_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
59190. BIFPLR6_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
59191. BIFPLR6_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
59192. BIFPLR6_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
59193. BIFPLR6_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
59194. BIFPLR6_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
59195. BIFPLR6_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
59196. BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
59197. BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
59198. BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
59199. BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
59200. BIFPLR6_1_SLOT_CNTL2__RESERVED_MASK
59201. BIFPLR6_1_SLOT_CNTL2__RESERVED__SHIFT
59202. BIFPLR6_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
59203. BIFPLR6_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
59204. BIFPLR6_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
59205. BIFPLR6_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
59206. BIFPLR6_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
59207. BIFPLR6_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
59208. BIFPLR6_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
59209. BIFPLR6_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
59210. BIFPLR6_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
59211. BIFPLR6_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
59212. BIFPLR6_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
59213. BIFPLR6_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
59214. BIFPLR6_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
59215. BIFPLR6_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
59216. BIFPLR6_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
59217. BIFPLR6_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
59218. BIFPLR6_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
59219. BIFPLR6_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
59220. BIFPLR6_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
59221. BIFPLR6_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
59222. BIFPLR6_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
59223. BIFPLR6_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
59224. BIFPLR6_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
59225. BIFPLR6_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
59226. BIFPLR6_1_SLOT_STATUS2__RESERVED_MASK
59227. BIFPLR6_1_SLOT_STATUS2__RESERVED__SHIFT
59228. BIFPLR6_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
59229. BIFPLR6_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
59230. BIFPLR6_1_SLOT_STATUS__COMMAND_COMPLETED_MASK
59231. BIFPLR6_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
59232. BIFPLR6_1_SLOT_STATUS__DL_STATE_CHANGED_MASK
59233. BIFPLR6_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
59234. BIFPLR6_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
59235. BIFPLR6_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
59236. BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
59237. BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
59238. BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK
59239. BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
59240. BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
59241. BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
59242. BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
59243. BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
59244. BIFPLR6_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
59245. BIFPLR6_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
59246. BIFPLR6_1_SSID_CAP_LIST__CAP_ID_MASK
59247. BIFPLR6_1_SSID_CAP_LIST__CAP_ID__SHIFT
59248. BIFPLR6_1_SSID_CAP_LIST__NEXT_PTR_MASK
59249. BIFPLR6_1_SSID_CAP_LIST__NEXT_PTR__SHIFT
59250. BIFPLR6_1_SSID_CAP__SUBSYSTEM_ID_MASK
59251. BIFPLR6_1_SSID_CAP__SUBSYSTEM_ID__SHIFT
59252. BIFPLR6_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
59253. BIFPLR6_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
59254. BIFPLR6_1_STATUS__CAP_LIST_MASK
59255. BIFPLR6_1_STATUS__CAP_LIST__SHIFT
59256. BIFPLR6_1_STATUS__DEVSEL_TIMING_MASK
59257. BIFPLR6_1_STATUS__DEVSEL_TIMING__SHIFT
59258. BIFPLR6_1_STATUS__FAST_BACK_CAPABLE_MASK
59259. BIFPLR6_1_STATUS__FAST_BACK_CAPABLE__SHIFT
59260. BIFPLR6_1_STATUS__INT_STATUS_MASK
59261. BIFPLR6_1_STATUS__INT_STATUS__SHIFT
59262. BIFPLR6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
59263. BIFPLR6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
59264. BIFPLR6_1_STATUS__PARITY_ERROR_DETECTED_MASK
59265. BIFPLR6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
59266. BIFPLR6_1_STATUS__PCI_66_EN_MASK
59267. BIFPLR6_1_STATUS__PCI_66_EN__SHIFT
59268. BIFPLR6_1_STATUS__RECEIVED_MASTER_ABORT_MASK
59269. BIFPLR6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
59270. BIFPLR6_1_STATUS__RECEIVED_TARGET_ABORT_MASK
59271. BIFPLR6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
59272. BIFPLR6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
59273. BIFPLR6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
59274. BIFPLR6_1_STATUS__SIGNAL_TARGET_ABORT_MASK
59275. BIFPLR6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
59276. BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
59277. BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
59278. BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
59279. BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
59280. BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
59281. BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
59282. BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
59283. BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
59284. BIFPLR6_1_SUB_CLASS__SUB_CLASS_MASK
59285. BIFPLR6_1_SUB_CLASS__SUB_CLASS__SHIFT
59286. BIFPLR6_1_VENDOR_ID__VENDOR_ID_MASK
59287. BIFPLR6_1_VENDOR_ID__VENDOR_ID__SHIFT
59288. BIFPLR6_2_BASE_CLASS__BASE_CLASS_MASK
59289. BIFPLR6_2_BASE_CLASS__BASE_CLASS__SHIFT
59290. BIFPLR6_2_BIST__BIST_CAP_MASK
59291. BIFPLR6_2_BIST__BIST_CAP__SHIFT
59292. BIFPLR6_2_BIST__BIST_COMP_MASK
59293. BIFPLR6_2_BIST__BIST_COMP__SHIFT
59294. BIFPLR6_2_BIST__BIST_STRT_MASK
59295. BIFPLR6_2_BIST__BIST_STRT__SHIFT
59296. BIFPLR6_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
59297. BIFPLR6_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
59298. BIFPLR6_2_CAP_PTR__CAP_PTR_MASK
59299. BIFPLR6_2_CAP_PTR__CAP_PTR__SHIFT
59300. BIFPLR6_2_COMMAND__AD_STEPPING_MASK
59301. BIFPLR6_2_COMMAND__AD_STEPPING__SHIFT
59302. BIFPLR6_2_COMMAND__BUS_MASTER_EN_MASK
59303. BIFPLR6_2_COMMAND__BUS_MASTER_EN__SHIFT
59304. BIFPLR6_2_COMMAND__FAST_B2B_EN_MASK
59305. BIFPLR6_2_COMMAND__FAST_B2B_EN__SHIFT
59306. BIFPLR6_2_COMMAND__INT_DIS_MASK
59307. BIFPLR6_2_COMMAND__INT_DIS__SHIFT
59308. BIFPLR6_2_COMMAND__IO_ACCESS_EN_MASK
59309. BIFPLR6_2_COMMAND__IO_ACCESS_EN__SHIFT
59310. BIFPLR6_2_COMMAND__MEM_ACCESS_EN_MASK
59311. BIFPLR6_2_COMMAND__MEM_ACCESS_EN__SHIFT
59312. BIFPLR6_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
59313. BIFPLR6_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
59314. BIFPLR6_2_COMMAND__PAL_SNOOP_EN_MASK
59315. BIFPLR6_2_COMMAND__PAL_SNOOP_EN__SHIFT
59316. BIFPLR6_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
59317. BIFPLR6_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
59318. BIFPLR6_2_COMMAND__SERR_EN_MASK
59319. BIFPLR6_2_COMMAND__SERR_EN__SHIFT
59320. BIFPLR6_2_COMMAND__SPECIAL_CYCLE_EN_MASK
59321. BIFPLR6_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
59322. BIFPLR6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
59323. BIFPLR6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
59324. BIFPLR6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
59325. BIFPLR6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
59326. BIFPLR6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
59327. BIFPLR6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
59328. BIFPLR6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
59329. BIFPLR6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
59330. BIFPLR6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
59331. BIFPLR6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
59332. BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
59333. BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
59334. BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
59335. BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
59336. BIFPLR6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
59337. BIFPLR6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
59338. BIFPLR6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
59339. BIFPLR6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
59340. BIFPLR6_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
59341. BIFPLR6_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
59342. BIFPLR6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
59343. BIFPLR6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
59344. BIFPLR6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
59345. BIFPLR6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
59346. BIFPLR6_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
59347. BIFPLR6_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
59348. BIFPLR6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
59349. BIFPLR6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
59350. BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
59351. BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
59352. BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
59353. BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
59354. BIFPLR6_2_DEVICE_CAP__EXTENDED_TAG_MASK
59355. BIFPLR6_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
59356. BIFPLR6_2_DEVICE_CAP__FLR_CAPABLE_MASK
59357. BIFPLR6_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
59358. BIFPLR6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
59359. BIFPLR6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
59360. BIFPLR6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
59361. BIFPLR6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
59362. BIFPLR6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
59363. BIFPLR6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
59364. BIFPLR6_2_DEVICE_CAP__PHANTOM_FUNC_MASK
59365. BIFPLR6_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
59366. BIFPLR6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
59367. BIFPLR6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
59368. BIFPLR6_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
59369. BIFPLR6_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
59370. BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
59371. BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
59372. BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
59373. BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
59374. BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
59375. BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
59376. BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
59377. BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
59378. BIFPLR6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
59379. BIFPLR6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
59380. BIFPLR6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
59381. BIFPLR6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
59382. BIFPLR6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
59383. BIFPLR6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
59384. BIFPLR6_2_DEVICE_CNTL2__LTR_EN_MASK
59385. BIFPLR6_2_DEVICE_CNTL2__LTR_EN__SHIFT
59386. BIFPLR6_2_DEVICE_CNTL2__OBFF_EN_MASK
59387. BIFPLR6_2_DEVICE_CNTL2__OBFF_EN__SHIFT
59388. BIFPLR6_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
59389. BIFPLR6_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
59390. BIFPLR6_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
59391. BIFPLR6_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
59392. BIFPLR6_2_DEVICE_CNTL__CORR_ERR_EN_MASK
59393. BIFPLR6_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
59394. BIFPLR6_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
59395. BIFPLR6_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
59396. BIFPLR6_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
59397. BIFPLR6_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
59398. BIFPLR6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
59399. BIFPLR6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
59400. BIFPLR6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
59401. BIFPLR6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
59402. BIFPLR6_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
59403. BIFPLR6_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
59404. BIFPLR6_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
59405. BIFPLR6_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
59406. BIFPLR6_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
59407. BIFPLR6_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
59408. BIFPLR6_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
59409. BIFPLR6_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
59410. BIFPLR6_2_DEVICE_CNTL__USR_REPORT_EN_MASK
59411. BIFPLR6_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
59412. BIFPLR6_2_DEVICE_ID__DEVICE_ID_MASK
59413. BIFPLR6_2_DEVICE_ID__DEVICE_ID__SHIFT
59414. BIFPLR6_2_DEVICE_STATUS2__RESERVED_MASK
59415. BIFPLR6_2_DEVICE_STATUS2__RESERVED__SHIFT
59416. BIFPLR6_2_DEVICE_STATUS__AUX_PWR_MASK
59417. BIFPLR6_2_DEVICE_STATUS__AUX_PWR__SHIFT
59418. BIFPLR6_2_DEVICE_STATUS__CORR_ERR_MASK
59419. BIFPLR6_2_DEVICE_STATUS__CORR_ERR__SHIFT
59420. BIFPLR6_2_DEVICE_STATUS__FATAL_ERR_MASK
59421. BIFPLR6_2_DEVICE_STATUS__FATAL_ERR__SHIFT
59422. BIFPLR6_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
59423. BIFPLR6_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
59424. BIFPLR6_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
59425. BIFPLR6_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
59426. BIFPLR6_2_DEVICE_STATUS__USR_DETECTED_MASK
59427. BIFPLR6_2_DEVICE_STATUS__USR_DETECTED__SHIFT
59428. BIFPLR6_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
59429. BIFPLR6_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
59430. BIFPLR6_2_HEADER__DEVICE_TYPE_MASK
59431. BIFPLR6_2_HEADER__DEVICE_TYPE__SHIFT
59432. BIFPLR6_2_HEADER__HEADER_TYPE_MASK
59433. BIFPLR6_2_HEADER__HEADER_TYPE__SHIFT
59434. BIFPLR6_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
59435. BIFPLR6_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
59436. BIFPLR6_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
59437. BIFPLR6_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
59438. BIFPLR6_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
59439. BIFPLR6_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
59440. BIFPLR6_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
59441. BIFPLR6_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
59442. BIFPLR6_2_IO_BASE_LIMIT__IO_BASE_MASK
59443. BIFPLR6_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
59444. BIFPLR6_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
59445. BIFPLR6_2_IO_BASE_LIMIT__IO_BASE__SHIFT
59446. BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT_MASK
59447. BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
59448. BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
59449. BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT
59450. BIFPLR6_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
59451. BIFPLR6_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
59452. BIFPLR6_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK
59453. BIFPLR6_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
59454. BIFPLR6_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
59455. BIFPLR6_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
59456. BIFPLR6_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
59457. BIFPLR6_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
59458. BIFPLR6_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
59459. BIFPLR6_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
59460. BIFPLR6_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK
59461. BIFPLR6_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
59462. BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
59463. BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
59464. BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK
59465. BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
59466. BIFPLR6_2_LATENCY__LATENCY_TIMER_MASK
59467. BIFPLR6_2_LATENCY__LATENCY_TIMER__SHIFT
59468. BIFPLR6_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
59469. BIFPLR6_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
59470. BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
59471. BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
59472. BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
59473. BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
59474. BIFPLR6_2_LINK_CAP2__RESERVED_MASK
59475. BIFPLR6_2_LINK_CAP2__RESERVED__SHIFT
59476. BIFPLR6_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
59477. BIFPLR6_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
59478. BIFPLR6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
59479. BIFPLR6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
59480. BIFPLR6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
59481. BIFPLR6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
59482. BIFPLR6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
59483. BIFPLR6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
59484. BIFPLR6_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
59485. BIFPLR6_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
59486. BIFPLR6_2_LINK_CAP__L1_EXIT_LATENCY_MASK
59487. BIFPLR6_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
59488. BIFPLR6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
59489. BIFPLR6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
59490. BIFPLR6_2_LINK_CAP__LINK_SPEED_MASK
59491. BIFPLR6_2_LINK_CAP__LINK_SPEED__SHIFT
59492. BIFPLR6_2_LINK_CAP__LINK_WIDTH_MASK
59493. BIFPLR6_2_LINK_CAP__LINK_WIDTH__SHIFT
59494. BIFPLR6_2_LINK_CAP__PM_SUPPORT_MASK
59495. BIFPLR6_2_LINK_CAP__PM_SUPPORT__SHIFT
59496. BIFPLR6_2_LINK_CAP__PORT_NUMBER_MASK
59497. BIFPLR6_2_LINK_CAP__PORT_NUMBER__SHIFT
59498. BIFPLR6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
59499. BIFPLR6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
59500. BIFPLR6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
59501. BIFPLR6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
59502. BIFPLR6_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
59503. BIFPLR6_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
59504. BIFPLR6_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
59505. BIFPLR6_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
59506. BIFPLR6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
59507. BIFPLR6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
59508. BIFPLR6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
59509. BIFPLR6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
59510. BIFPLR6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
59511. BIFPLR6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
59512. BIFPLR6_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
59513. BIFPLR6_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
59514. BIFPLR6_2_LINK_CNTL2__XMIT_MARGIN_MASK
59515. BIFPLR6_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
59516. BIFPLR6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
59517. BIFPLR6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
59518. BIFPLR6_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
59519. BIFPLR6_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
59520. BIFPLR6_2_LINK_CNTL__EXTENDED_SYNC_MASK
59521. BIFPLR6_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
59522. BIFPLR6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
59523. BIFPLR6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
59524. BIFPLR6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
59525. BIFPLR6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
59526. BIFPLR6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
59527. BIFPLR6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
59528. BIFPLR6_2_LINK_CNTL__LINK_DIS_MASK
59529. BIFPLR6_2_LINK_CNTL__LINK_DIS__SHIFT
59530. BIFPLR6_2_LINK_CNTL__PM_CONTROL_MASK
59531. BIFPLR6_2_LINK_CNTL__PM_CONTROL__SHIFT
59532. BIFPLR6_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
59533. BIFPLR6_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
59534. BIFPLR6_2_LINK_CNTL__RETRAIN_LINK_MASK
59535. BIFPLR6_2_LINK_CNTL__RETRAIN_LINK__SHIFT
59536. BIFPLR6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
59537. BIFPLR6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
59538. BIFPLR6_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
59539. BIFPLR6_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
59540. BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
59541. BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
59542. BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
59543. BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
59544. BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
59545. BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
59546. BIFPLR6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
59547. BIFPLR6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
59548. BIFPLR6_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
59549. BIFPLR6_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
59550. BIFPLR6_2_LINK_STATUS__DL_ACTIVE_MASK
59551. BIFPLR6_2_LINK_STATUS__DL_ACTIVE__SHIFT
59552. BIFPLR6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
59553. BIFPLR6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
59554. BIFPLR6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
59555. BIFPLR6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
59556. BIFPLR6_2_LINK_STATUS__LINK_TRAINING_MASK
59557. BIFPLR6_2_LINK_STATUS__LINK_TRAINING__SHIFT
59558. BIFPLR6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
59559. BIFPLR6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
59560. BIFPLR6_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
59561. BIFPLR6_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
59562. BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
59563. BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
59564. BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
59565. BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
59566. BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
59567. BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
59568. BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
59569. BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
59570. BIFPLR6_2_MSI_CAP_LIST__CAP_ID_MASK
59571. BIFPLR6_2_MSI_CAP_LIST__CAP_ID__SHIFT
59572. BIFPLR6_2_MSI_CAP_LIST__NEXT_PTR_MASK
59573. BIFPLR6_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
59574. BIFPLR6_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
59575. BIFPLR6_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
59576. BIFPLR6_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
59577. BIFPLR6_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
59578. BIFPLR6_2_MSI_MAP_CAP_LIST__CAP_ID_MASK
59579. BIFPLR6_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
59580. BIFPLR6_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
59581. BIFPLR6_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
59582. BIFPLR6_2_MSI_MAP_CAP__CAP_TYPE_MASK
59583. BIFPLR6_2_MSI_MAP_CAP__CAP_TYPE__SHIFT
59584. BIFPLR6_2_MSI_MAP_CAP__EN_MASK
59585. BIFPLR6_2_MSI_MAP_CAP__EN__SHIFT
59586. BIFPLR6_2_MSI_MAP_CAP__FIXD_MASK
59587. BIFPLR6_2_MSI_MAP_CAP__FIXD__SHIFT
59588. BIFPLR6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
59589. BIFPLR6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
59590. BIFPLR6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
59591. BIFPLR6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
59592. BIFPLR6_2_MSI_MSG_CNTL__MSI_64BIT_MASK
59593. BIFPLR6_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
59594. BIFPLR6_2_MSI_MSG_CNTL__MSI_EN_MASK
59595. BIFPLR6_2_MSI_MSG_CNTL__MSI_EN__SHIFT
59596. BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
59597. BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
59598. BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
59599. BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
59600. BIFPLR6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
59601. BIFPLR6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
59602. BIFPLR6_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
59603. BIFPLR6_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
59604. BIFPLR6_2_MSI_MSG_DATA__MSI_DATA_MASK
59605. BIFPLR6_2_MSI_MSG_DATA__MSI_DATA__SHIFT
59606. BIFPLR6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
59607. BIFPLR6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
59608. BIFPLR6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
59609. BIFPLR6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
59610. BIFPLR6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
59611. BIFPLR6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
59612. BIFPLR6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
59613. BIFPLR6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
59614. BIFPLR6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
59615. BIFPLR6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
59616. BIFPLR6_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
59617. BIFPLR6_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
59618. BIFPLR6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
59619. BIFPLR6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
59620. BIFPLR6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
59621. BIFPLR6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
59622. BIFPLR6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
59623. BIFPLR6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
59624. BIFPLR6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
59625. BIFPLR6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
59626. BIFPLR6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
59627. BIFPLR6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
59628. BIFPLR6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
59629. BIFPLR6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
59630. BIFPLR6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
59631. BIFPLR6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
59632. BIFPLR6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
59633. BIFPLR6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
59634. BIFPLR6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
59635. BIFPLR6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
59636. BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
59637. BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
59638. BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
59639. BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
59640. BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
59641. BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
59642. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
59643. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
59644. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
59645. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
59646. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
59647. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
59648. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
59649. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
59650. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
59651. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
59652. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
59653. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
59654. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
59655. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
59656. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
59657. BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
59658. BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
59659. BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
59660. BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
59661. BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
59662. BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
59663. BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
59664. BIFPLR6_2_PCIE_CAP_LIST__CAP_ID_MASK
59665. BIFPLR6_2_PCIE_CAP_LIST__CAP_ID__SHIFT
59666. BIFPLR6_2_PCIE_CAP_LIST__NEXT_PTR_MASK
59667. BIFPLR6_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
59668. BIFPLR6_2_PCIE_CAP__DEVICE_TYPE_MASK
59669. BIFPLR6_2_PCIE_CAP__DEVICE_TYPE__SHIFT
59670. BIFPLR6_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
59671. BIFPLR6_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
59672. BIFPLR6_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
59673. BIFPLR6_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
59674. BIFPLR6_2_PCIE_CAP__VERSION_MASK
59675. BIFPLR6_2_PCIE_CAP__VERSION__SHIFT
59676. BIFPLR6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
59677. BIFPLR6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
59678. BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
59679. BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
59680. BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
59681. BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
59682. BIFPLR6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
59683. BIFPLR6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
59684. BIFPLR6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
59685. BIFPLR6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
59686. BIFPLR6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
59687. BIFPLR6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
59688. BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
59689. BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
59690. BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
59691. BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
59692. BIFPLR6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
59693. BIFPLR6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
59694. BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
59695. BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
59696. BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
59697. BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
59698. BIFPLR6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
59699. BIFPLR6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
59700. BIFPLR6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
59701. BIFPLR6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
59702. BIFPLR6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
59703. BIFPLR6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
59704. BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
59705. BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
59706. BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
59707. BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
59708. BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
59709. BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
59710. BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
59711. BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
59712. BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
59713. BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
59714. BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
59715. BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
59716. BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
59717. BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
59718. BIFPLR6_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK
59719. BIFPLR6_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT
59720. BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK
59721. BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT
59722. BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK
59723. BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT
59724. BIFPLR6_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK
59725. BIFPLR6_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT
59726. BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK
59727. BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT
59728. BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK
59729. BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT
59730. BIFPLR6_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK
59731. BIFPLR6_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT
59732. BIFPLR6_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK
59733. BIFPLR6_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT
59734. BIFPLR6_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK
59735. BIFPLR6_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT
59736. BIFPLR6_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK
59737. BIFPLR6_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT
59738. BIFPLR6_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK
59739. BIFPLR6_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT
59740. BIFPLR6_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK
59741. BIFPLR6_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT
59742. BIFPLR6_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK
59743. BIFPLR6_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT
59744. BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK
59745. BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT
59746. BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK
59747. BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT
59748. BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK
59749. BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT
59750. BIFPLR6_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK
59751. BIFPLR6_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT
59752. BIFPLR6_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK
59753. BIFPLR6_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT
59754. BIFPLR6_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK
59755. BIFPLR6_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT
59756. BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK
59757. BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT
59758. BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK
59759. BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT
59760. BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK
59761. BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT
59762. BIFPLR6_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK
59763. BIFPLR6_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT
59764. BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
59765. BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
59766. BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
59767. BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
59768. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK
59769. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
59770. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK
59771. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
59772. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK
59773. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
59774. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK
59775. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
59776. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK
59777. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
59778. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK
59779. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
59780. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK
59781. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
59782. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK
59783. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
59784. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK
59785. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
59786. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK
59787. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
59788. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK
59789. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
59790. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK
59791. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
59792. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK
59793. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
59794. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK
59795. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
59796. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK
59797. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
59798. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK
59799. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
59800. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK
59801. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
59802. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK
59803. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
59804. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK
59805. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
59806. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK
59807. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
59808. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK
59809. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
59810. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK
59811. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
59812. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK
59813. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
59814. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK
59815. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
59816. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK
59817. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
59818. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK
59819. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
59820. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK
59821. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
59822. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK
59823. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
59824. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK
59825. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
59826. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK
59827. BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
59828. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK
59829. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
59830. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK
59831. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
59832. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK
59833. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
59834. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK
59835. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
59836. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK
59837. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
59838. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK
59839. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
59840. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK
59841. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
59842. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK
59843. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
59844. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK
59845. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
59846. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK
59847. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
59848. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK
59849. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
59850. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK
59851. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
59852. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK
59853. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
59854. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK
59855. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
59856. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK
59857. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
59858. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK
59859. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
59860. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK
59861. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
59862. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK
59863. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
59864. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK
59865. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
59866. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK
59867. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
59868. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK
59869. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
59870. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK
59871. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
59872. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK
59873. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
59874. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK
59875. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
59876. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK
59877. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
59878. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK
59879. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
59880. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK
59881. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
59882. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK
59883. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
59884. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK
59885. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
59886. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK
59887. BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
59888. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK
59889. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
59890. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK
59891. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
59892. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK
59893. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
59894. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK
59895. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
59896. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK
59897. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
59898. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK
59899. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
59900. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK
59901. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
59902. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK
59903. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
59904. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK
59905. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
59906. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK
59907. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
59908. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK
59909. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
59910. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK
59911. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
59912. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK
59913. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
59914. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK
59915. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
59916. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK
59917. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
59918. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK
59919. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
59920. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK
59921. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
59922. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK
59923. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
59924. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK
59925. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
59926. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK
59927. BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
59928. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK
59929. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
59930. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK
59931. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
59932. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK
59933. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
59934. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK
59935. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
59936. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK
59937. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
59938. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK
59939. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
59940. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK
59941. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
59942. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK
59943. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
59944. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK
59945. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
59946. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK
59947. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
59948. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK
59949. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
59950. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK
59951. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
59952. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK
59953. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
59954. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK
59955. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
59956. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK
59957. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
59958. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK
59959. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
59960. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK
59961. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
59962. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK
59963. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
59964. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK
59965. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
59966. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK
59967. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
59968. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK
59969. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
59970. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK
59971. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
59972. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK
59973. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
59974. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK
59975. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
59976. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK
59977. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
59978. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK
59979. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
59980. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK
59981. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
59982. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK
59983. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
59984. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK
59985. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
59986. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK
59987. BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
59988. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK
59989. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
59990. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK
59991. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
59992. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK
59993. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
59994. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK
59995. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
59996. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK
59997. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
59998. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK
59999. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
60000. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK
60001. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
60002. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK
60003. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
60004. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK
60005. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
60006. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK
60007. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
60008. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK
60009. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
60010. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK
60011. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
60012. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK
60013. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
60014. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK
60015. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
60016. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK
60017. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
60018. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK
60019. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
60020. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK
60021. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
60022. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK
60023. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
60024. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK
60025. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
60026. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK
60027. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
60028. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK
60029. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
60030. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK
60031. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
60032. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK
60033. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
60034. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK
60035. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
60036. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK
60037. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
60038. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK
60039. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
60040. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK
60041. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
60042. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK
60043. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
60044. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK
60045. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
60046. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK
60047. BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
60048. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK
60049. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
60050. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK
60051. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
60052. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK
60053. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
60054. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK
60055. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
60056. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK
60057. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
60058. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK
60059. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
60060. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK
60061. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
60062. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK
60063. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
60064. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK
60065. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
60066. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK
60067. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
60068. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK
60069. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
60070. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK
60071. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
60072. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK
60073. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
60074. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK
60075. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
60076. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK
60077. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
60078. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK
60079. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
60080. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK
60081. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
60082. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK
60083. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
60084. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK
60085. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
60086. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK
60087. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
60088. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK
60089. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
60090. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK
60091. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
60092. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK
60093. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
60094. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK
60095. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
60096. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK
60097. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
60098. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK
60099. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
60100. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK
60101. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
60102. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK
60103. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
60104. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK
60105. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
60106. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK
60107. BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
60108. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK
60109. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
60110. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK
60111. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
60112. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK
60113. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
60114. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK
60115. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
60116. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK
60117. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
60118. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK
60119. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
60120. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK
60121. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
60122. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK
60123. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
60124. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK
60125. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
60126. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK
60127. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
60128. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK
60129. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
60130. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK
60131. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
60132. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK
60133. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
60134. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK
60135. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
60136. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK
60137. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
60138. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK
60139. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
60140. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK
60141. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
60142. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK
60143. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
60144. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK
60145. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
60146. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK
60147. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
60148. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK
60149. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
60150. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK
60151. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
60152. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK
60153. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
60154. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK
60155. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
60156. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK
60157. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
60158. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK
60159. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
60160. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK
60161. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
60162. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK
60163. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
60164. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK
60165. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
60166. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK
60167. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
60168. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK
60169. BIFPLR6_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
60170. BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK
60171. BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
60172. BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK
60173. BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
60174. BIFPLR6_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
60175. BIFPLR6_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
60176. BIFPLR6_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK
60177. BIFPLR6_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
60178. BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
60179. BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
60180. BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
60181. BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
60182. BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
60183. BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
60184. BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
60185. BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
60186. BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
60187. BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
60188. BIFPLR6_2_PCIE_ESM_HEADER_2__CAP_ID_MASK
60189. BIFPLR6_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
60190. BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
60191. BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
60192. BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
60193. BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
60194. BIFPLR6_2_PCIE_HDR_LOG0__TLP_HDR_MASK
60195. BIFPLR6_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
60196. BIFPLR6_2_PCIE_HDR_LOG1__TLP_HDR_MASK
60197. BIFPLR6_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
60198. BIFPLR6_2_PCIE_HDR_LOG2__TLP_HDR_MASK
60199. BIFPLR6_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
60200. BIFPLR6_2_PCIE_HDR_LOG3__TLP_HDR_MASK
60201. BIFPLR6_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
60202. BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
60203. BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
60204. BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
60205. BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
60206. BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
60207. BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
60208. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
60209. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
60210. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
60211. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
60212. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
60213. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
60214. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
60215. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
60216. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
60217. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
60218. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
60219. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
60220. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
60221. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
60222. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
60223. BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
60224. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
60225. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
60226. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
60227. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
60228. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
60229. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
60230. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
60231. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
60232. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
60233. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
60234. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
60235. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
60236. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
60237. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
60238. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
60239. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
60240. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
60241. BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
60242. BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60243. BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60244. BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60245. BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60246. BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60247. BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60248. BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60249. BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60250. BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60251. BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60252. BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60253. BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60254. BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60255. BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60256. BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60257. BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60258. BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60259. BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60260. BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60261. BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60262. BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60263. BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60264. BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60265. BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60266. BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60267. BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60268. BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60269. BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60270. BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60271. BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60272. BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60273. BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60274. BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60275. BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60276. BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60277. BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60278. BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60279. BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60280. BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60281. BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60282. BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60283. BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60284. BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60285. BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60286. BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60287. BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60288. BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60289. BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60290. BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60291. BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60292. BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60293. BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60294. BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60295. BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60296. BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60297. BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60298. BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60299. BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60300. BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60301. BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60302. BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60303. BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60304. BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60305. BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60306. BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60307. BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60308. BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60309. BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60310. BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60311. BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60312. BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60313. BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60314. BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60315. BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60316. BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60317. BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60318. BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60319. BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60320. BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60321. BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60322. BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60323. BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60324. BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60325. BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60326. BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60327. BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60328. BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60329. BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60330. BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60331. BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60332. BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60333. BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60334. BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60335. BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60336. BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60337. BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60338. BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60339. BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60340. BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60341. BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60342. BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60343. BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60344. BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60345. BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60346. BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60347. BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60348. BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60349. BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60350. BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60351. BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60352. BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60353. BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60354. BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60355. BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60356. BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60357. BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60358. BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60359. BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60360. BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60361. BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60362. BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
60363. BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
60364. BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
60365. BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
60366. BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
60367. BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
60368. BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
60369. BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
60370. BIFPLR6_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
60371. BIFPLR6_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
60372. BIFPLR6_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
60373. BIFPLR6_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
60374. BIFPLR6_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
60375. BIFPLR6_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
60376. BIFPLR6_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
60377. BIFPLR6_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
60378. BIFPLR6_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
60379. BIFPLR6_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
60380. BIFPLR6_2_PCIE_LINK_CNTL3__RESERVED_MASK
60381. BIFPLR6_2_PCIE_LINK_CNTL3__RESERVED__SHIFT
60382. BIFPLR6_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
60383. BIFPLR6_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
60384. BIFPLR6_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
60385. BIFPLR6_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
60386. BIFPLR6_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
60387. BIFPLR6_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
60388. BIFPLR6_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
60389. BIFPLR6_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
60390. BIFPLR6_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
60391. BIFPLR6_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
60392. BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
60393. BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
60394. BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
60395. BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
60396. BIFPLR6_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
60397. BIFPLR6_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
60398. BIFPLR6_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK
60399. BIFPLR6_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
60400. BIFPLR6_2_PCIE_MC_CNTL__MC_ENABLE_MASK
60401. BIFPLR6_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT
60402. BIFPLR6_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
60403. BIFPLR6_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
60404. BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
60405. BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
60406. BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
60407. BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
60408. BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
60409. BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
60410. BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
60411. BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
60412. BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
60413. BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
60414. BIFPLR6_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
60415. BIFPLR6_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
60416. BIFPLR6_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
60417. BIFPLR6_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
60418. BIFPLR6_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
60419. BIFPLR6_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
60420. BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
60421. BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
60422. BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
60423. BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
60424. BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
60425. BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
60426. BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
60427. BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
60428. BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
60429. BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
60430. BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
60431. BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
60432. BIFPLR6_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
60433. BIFPLR6_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
60434. BIFPLR6_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
60435. BIFPLR6_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
60436. BIFPLR6_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
60437. BIFPLR6_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
60438. BIFPLR6_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
60439. BIFPLR6_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
60440. BIFPLR6_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
60441. BIFPLR6_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
60442. BIFPLR6_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
60443. BIFPLR6_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
60444. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
60445. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
60446. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
60447. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
60448. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
60449. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
60450. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
60451. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
60452. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
60453. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
60454. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
60455. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
60456. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
60457. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
60458. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
60459. BIFPLR6_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
60460. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK
60461. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT
60462. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK
60463. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT
60464. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK
60465. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT
60466. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK
60467. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT
60468. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK
60469. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT
60470. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK
60471. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT
60472. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK
60473. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT
60474. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK
60475. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT
60476. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK
60477. BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT
60478. BIFPLR6_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK
60479. BIFPLR6_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT
60480. BIFPLR6_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK
60481. BIFPLR6_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT
60482. BIFPLR6_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK
60483. BIFPLR6_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT
60484. BIFPLR6_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK
60485. BIFPLR6_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT
60486. BIFPLR6_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK
60487. BIFPLR6_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT
60488. BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK
60489. BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT
60490. BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK
60491. BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT
60492. BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK
60493. BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT
60494. BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK
60495. BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT
60496. BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CTO_MASK
60497. BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT
60498. BIFPLR6_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK
60499. BIFPLR6_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT
60500. BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK
60501. BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT
60502. BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK
60503. BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT
60504. BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK
60505. BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT
60506. BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK
60507. BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT
60508. BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK
60509. BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT
60510. BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK
60511. BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT
60512. BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK
60513. BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT
60514. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK
60515. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT
60516. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK
60517. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT
60518. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK
60519. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT
60520. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK
60521. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT
60522. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK
60523. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT
60524. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK
60525. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT
60526. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK
60527. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT
60528. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK
60529. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT
60530. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK
60531. BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT
60532. BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK
60533. BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT
60534. BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK
60535. BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT
60536. BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK
60537. BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT
60538. BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK
60539. BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT
60540. BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK
60541. BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT
60542. BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK
60543. BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT
60544. BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK
60545. BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT
60546. BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK
60547. BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT
60548. BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK
60549. BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT
60550. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK
60551. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT
60552. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK
60553. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT
60554. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK
60555. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT
60556. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK
60557. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT
60558. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK
60559. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT
60560. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK
60561. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT
60562. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK
60563. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT
60564. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK
60565. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT
60566. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK
60567. BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT
60568. BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
60569. BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
60570. BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
60571. BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
60572. BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
60573. BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
60574. BIFPLR6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
60575. BIFPLR6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
60576. BIFPLR6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
60577. BIFPLR6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
60578. BIFPLR6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
60579. BIFPLR6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
60580. BIFPLR6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
60581. BIFPLR6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
60582. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
60583. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
60584. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
60585. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
60586. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
60587. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
60588. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
60589. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
60590. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
60591. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
60592. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
60593. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
60594. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
60595. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
60596. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
60597. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
60598. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
60599. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
60600. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
60601. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
60602. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
60603. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
60604. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
60605. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
60606. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
60607. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
60608. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
60609. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
60610. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
60611. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
60612. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
60613. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
60614. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
60615. BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
60616. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
60617. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
60618. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
60619. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
60620. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
60621. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
60622. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
60623. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
60624. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
60625. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
60626. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
60627. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
60628. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
60629. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
60630. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
60631. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
60632. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
60633. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
60634. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
60635. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
60636. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
60637. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
60638. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
60639. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
60640. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
60641. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
60642. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
60643. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
60644. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
60645. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
60646. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
60647. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
60648. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
60649. BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
60650. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
60651. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
60652. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
60653. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
60654. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
60655. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
60656. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
60657. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
60658. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
60659. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
60660. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
60661. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
60662. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
60663. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
60664. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
60665. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
60666. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
60667. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
60668. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
60669. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
60670. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
60671. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
60672. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
60673. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
60674. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
60675. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
60676. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
60677. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
60678. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
60679. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
60680. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
60681. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
60682. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
60683. BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
60684. BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
60685. BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
60686. BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
60687. BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
60688. BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
60689. BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
60690. BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
60691. BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
60692. BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
60693. BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
60694. BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
60695. BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
60696. BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
60697. BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
60698. BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
60699. BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
60700. BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
60701. BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
60702. BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
60703. BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
60704. BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
60705. BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
60706. BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
60707. BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
60708. BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
60709. BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
60710. BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
60711. BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
60712. BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
60713. BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
60714. BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
60715. BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
60716. BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
60717. BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
60718. BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
60719. BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
60720. BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
60721. BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
60722. BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
60723. BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
60724. BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
60725. BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
60726. BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
60727. BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
60728. BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
60729. BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
60730. BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
60731. BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
60732. BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
60733. BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
60734. BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
60735. BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
60736. BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
60737. BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
60738. BIFPLR6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
60739. BIFPLR6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
60740. BIFPLR6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
60741. BIFPLR6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
60742. BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
60743. BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
60744. BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
60745. BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
60746. BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
60747. BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
60748. BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
60749. BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
60750. BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
60751. BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
60752. BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
60753. BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
60754. BIFPLR6_2_PMI_CAP_LIST__CAP_ID_MASK
60755. BIFPLR6_2_PMI_CAP_LIST__CAP_ID__SHIFT
60756. BIFPLR6_2_PMI_CAP_LIST__NEXT_PTR_MASK
60757. BIFPLR6_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
60758. BIFPLR6_2_PMI_CAP__AUX_CURRENT_MASK
60759. BIFPLR6_2_PMI_CAP__AUX_CURRENT__SHIFT
60760. BIFPLR6_2_PMI_CAP__D1_SUPPORT_MASK
60761. BIFPLR6_2_PMI_CAP__D1_SUPPORT__SHIFT
60762. BIFPLR6_2_PMI_CAP__D2_SUPPORT_MASK
60763. BIFPLR6_2_PMI_CAP__D2_SUPPORT__SHIFT
60764. BIFPLR6_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
60765. BIFPLR6_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
60766. BIFPLR6_2_PMI_CAP__PME_CLOCK_MASK
60767. BIFPLR6_2_PMI_CAP__PME_CLOCK__SHIFT
60768. BIFPLR6_2_PMI_CAP__PME_SUPPORT_MASK
60769. BIFPLR6_2_PMI_CAP__PME_SUPPORT__SHIFT
60770. BIFPLR6_2_PMI_CAP__VERSION_MASK
60771. BIFPLR6_2_PMI_CAP__VERSION__SHIFT
60772. BIFPLR6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
60773. BIFPLR6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
60774. BIFPLR6_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
60775. BIFPLR6_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
60776. BIFPLR6_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
60777. BIFPLR6_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
60778. BIFPLR6_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
60779. BIFPLR6_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
60780. BIFPLR6_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
60781. BIFPLR6_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
60782. BIFPLR6_2_PMI_STATUS_CNTL__PME_EN_MASK
60783. BIFPLR6_2_PMI_STATUS_CNTL__PME_EN__SHIFT
60784. BIFPLR6_2_PMI_STATUS_CNTL__PME_STATUS_MASK
60785. BIFPLR6_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
60786. BIFPLR6_2_PMI_STATUS_CNTL__PMI_DATA_MASK
60787. BIFPLR6_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
60788. BIFPLR6_2_PMI_STATUS_CNTL__POWER_STATE_MASK
60789. BIFPLR6_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
60790. BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
60791. BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
60792. BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
60793. BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
60794. BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
60795. BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
60796. BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
60797. BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
60798. BIFPLR6_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
60799. BIFPLR6_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
60800. BIFPLR6_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
60801. BIFPLR6_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
60802. BIFPLR6_2_PROG_INTERFACE__PROG_INTERFACE_MASK
60803. BIFPLR6_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
60804. BIFPLR6_2_REVISION_ID__MAJOR_REV_ID_MASK
60805. BIFPLR6_2_REVISION_ID__MAJOR_REV_ID__SHIFT
60806. BIFPLR6_2_REVISION_ID__MINOR_REV_ID_MASK
60807. BIFPLR6_2_REVISION_ID__MINOR_REV_ID__SHIFT
60808. BIFPLR6_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
60809. BIFPLR6_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
60810. BIFPLR6_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
60811. BIFPLR6_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
60812. BIFPLR6_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK
60813. BIFPLR6_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
60814. BIFPLR6_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
60815. BIFPLR6_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
60816. BIFPLR6_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
60817. BIFPLR6_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
60818. BIFPLR6_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
60819. BIFPLR6_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
60820. BIFPLR6_2_ROOT_STATUS__PME_PENDING_MASK
60821. BIFPLR6_2_ROOT_STATUS__PME_PENDING__SHIFT
60822. BIFPLR6_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK
60823. BIFPLR6_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
60824. BIFPLR6_2_ROOT_STATUS__PME_STATUS_MASK
60825. BIFPLR6_2_ROOT_STATUS__PME_STATUS__SHIFT
60826. BIFPLR6_2_SECONDARY_STATUS__CAP_LIST_MASK
60827. BIFPLR6_2_SECONDARY_STATUS__CAP_LIST__SHIFT
60828. BIFPLR6_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK
60829. BIFPLR6_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
60830. BIFPLR6_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
60831. BIFPLR6_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
60832. BIFPLR6_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
60833. BIFPLR6_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
60834. BIFPLR6_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
60835. BIFPLR6_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
60836. BIFPLR6_2_SECONDARY_STATUS__PCI_66_EN_MASK
60837. BIFPLR6_2_SECONDARY_STATUS__PCI_66_EN__SHIFT
60838. BIFPLR6_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
60839. BIFPLR6_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
60840. BIFPLR6_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
60841. BIFPLR6_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
60842. BIFPLR6_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
60843. BIFPLR6_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
60844. BIFPLR6_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
60845. BIFPLR6_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
60846. BIFPLR6_2_SLOT_CAP2__RESERVED_MASK
60847. BIFPLR6_2_SLOT_CAP2__RESERVED__SHIFT
60848. BIFPLR6_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
60849. BIFPLR6_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
60850. BIFPLR6_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
60851. BIFPLR6_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
60852. BIFPLR6_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
60853. BIFPLR6_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
60854. BIFPLR6_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK
60855. BIFPLR6_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
60856. BIFPLR6_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK
60857. BIFPLR6_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
60858. BIFPLR6_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
60859. BIFPLR6_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
60860. BIFPLR6_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
60861. BIFPLR6_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
60862. BIFPLR6_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
60863. BIFPLR6_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
60864. BIFPLR6_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
60865. BIFPLR6_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
60866. BIFPLR6_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
60867. BIFPLR6_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
60868. BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
60869. BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
60870. BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
60871. BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
60872. BIFPLR6_2_SLOT_CNTL2__RESERVED_MASK
60873. BIFPLR6_2_SLOT_CNTL2__RESERVED__SHIFT
60874. BIFPLR6_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
60875. BIFPLR6_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
60876. BIFPLR6_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
60877. BIFPLR6_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
60878. BIFPLR6_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
60879. BIFPLR6_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
60880. BIFPLR6_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
60881. BIFPLR6_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
60882. BIFPLR6_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
60883. BIFPLR6_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
60884. BIFPLR6_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
60885. BIFPLR6_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
60886. BIFPLR6_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
60887. BIFPLR6_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
60888. BIFPLR6_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
60889. BIFPLR6_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
60890. BIFPLR6_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
60891. BIFPLR6_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
60892. BIFPLR6_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
60893. BIFPLR6_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
60894. BIFPLR6_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
60895. BIFPLR6_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
60896. BIFPLR6_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
60897. BIFPLR6_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
60898. BIFPLR6_2_SLOT_STATUS2__RESERVED_MASK
60899. BIFPLR6_2_SLOT_STATUS2__RESERVED__SHIFT
60900. BIFPLR6_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
60901. BIFPLR6_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
60902. BIFPLR6_2_SLOT_STATUS__COMMAND_COMPLETED_MASK
60903. BIFPLR6_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
60904. BIFPLR6_2_SLOT_STATUS__DL_STATE_CHANGED_MASK
60905. BIFPLR6_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
60906. BIFPLR6_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
60907. BIFPLR6_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
60908. BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
60909. BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
60910. BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK
60911. BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
60912. BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
60913. BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
60914. BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
60915. BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
60916. BIFPLR6_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
60917. BIFPLR6_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
60918. BIFPLR6_2_SSID_CAP_LIST__CAP_ID_MASK
60919. BIFPLR6_2_SSID_CAP_LIST__CAP_ID__SHIFT
60920. BIFPLR6_2_SSID_CAP_LIST__NEXT_PTR_MASK
60921. BIFPLR6_2_SSID_CAP_LIST__NEXT_PTR__SHIFT
60922. BIFPLR6_2_SSID_CAP__SUBSYSTEM_ID_MASK
60923. BIFPLR6_2_SSID_CAP__SUBSYSTEM_ID__SHIFT
60924. BIFPLR6_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
60925. BIFPLR6_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
60926. BIFPLR6_2_STATUS__CAP_LIST_MASK
60927. BIFPLR6_2_STATUS__CAP_LIST__SHIFT
60928. BIFPLR6_2_STATUS__DEVSEL_TIMING_MASK
60929. BIFPLR6_2_STATUS__DEVSEL_TIMING__SHIFT
60930. BIFPLR6_2_STATUS__FAST_BACK_CAPABLE_MASK
60931. BIFPLR6_2_STATUS__FAST_BACK_CAPABLE__SHIFT
60932. BIFPLR6_2_STATUS__INT_STATUS_MASK
60933. BIFPLR6_2_STATUS__INT_STATUS__SHIFT
60934. BIFPLR6_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
60935. BIFPLR6_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
60936. BIFPLR6_2_STATUS__PARITY_ERROR_DETECTED_MASK
60937. BIFPLR6_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
60938. BIFPLR6_2_STATUS__PCI_66_EN_MASK
60939. BIFPLR6_2_STATUS__PCI_66_EN__SHIFT
60940. BIFPLR6_2_STATUS__RECEIVED_MASTER_ABORT_MASK
60941. BIFPLR6_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
60942. BIFPLR6_2_STATUS__RECEIVED_TARGET_ABORT_MASK
60943. BIFPLR6_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
60944. BIFPLR6_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
60945. BIFPLR6_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
60946. BIFPLR6_2_STATUS__SIGNAL_TARGET_ABORT_MASK
60947. BIFPLR6_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
60948. BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
60949. BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
60950. BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
60951. BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
60952. BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
60953. BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
60954. BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
60955. BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
60956. BIFPLR6_2_SUB_CLASS__SUB_CLASS_MASK
60957. BIFPLR6_2_SUB_CLASS__SUB_CLASS__SHIFT
60958. BIFPLR6_2_VENDOR_ID__VENDOR_ID_MASK
60959. BIFPLR6_2_VENDOR_ID__VENDOR_ID__SHIFT
60960. BIF_3_0_D_H
60961. BIF_3_0_SH_MASK_H
60962. BIF_4_1_D_H
60963. BIF_4_1_SH_MASK_H
60964. BIF_5_0_D_H
60965. BIF_5_0_ENUM_H
60966. BIF_5_0_SH_MASK_H
60967. BIF_5_1_D_H
60968. BIF_5_1_ENUM_H
60969. BIF_5_1_SH_MASK_H
60970. BIF_ACV_DOORBELL_RANGE__OFFSET_MASK
60971. BIF_ACV_DOORBELL_RANGE__OFFSET__SHIFT
60972. BIF_ACV_DOORBELL_RANGE__SIZE_MASK
60973. BIF_ACV_DOORBELL_RANGE__SIZE__SHIFT
60974. BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK
60975. BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT
60976. BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK
60977. BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT
60978. BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK
60979. BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT
60980. BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK
60981. BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT
60982. BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK
60983. BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT
60984. BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK
60985. BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT
60986. BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK
60987. BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT
60988. BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK
60989. BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT
60990. BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK
60991. BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT
60992. BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK
60993. BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT
60994. BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK
60995. BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT
60996. BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK
60997. BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT
60998. BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK
60999. BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT
61000. BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK
61001. BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT
61002. BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK
61003. BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT
61004. BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK
61005. BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT
61006. BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2_MASK
61007. BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2__SHIFT
61008. BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2_MASK
61009. BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2__SHIFT
61010. BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2_MASK
61011. BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2__SHIFT
61012. BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK
61013. BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT
61014. BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2_MASK
61015. BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2__SHIFT
61016. BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2_MASK
61017. BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2__SHIFT
61018. BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2_MASK
61019. BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2__SHIFT
61020. BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK
61021. BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT
61022. BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3_MASK
61023. BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3__SHIFT
61024. BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3_MASK
61025. BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3__SHIFT
61026. BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3_MASK
61027. BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3__SHIFT
61028. BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK
61029. BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT
61030. BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3_MASK
61031. BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3__SHIFT
61032. BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3_MASK
61033. BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3__SHIFT
61034. BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3_MASK
61035. BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3__SHIFT
61036. BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK
61037. BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT
61038. BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F4_MASK
61039. BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F4__SHIFT
61040. BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_NR_DEV0_F4_MASK
61041. BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_NR_DEV0_F4__SHIFT
61042. BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F4_MASK
61043. BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F4__SHIFT
61044. BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F4_MASK
61045. BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F4__SHIFT
61046. BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_LENGTH_DEV0_F4_MASK
61047. BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_LENGTH_DEV0_F4__SHIFT
61048. BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_NR_DEV0_F4_MASK
61049. BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_NR_DEV0_F4__SHIFT
61050. BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_OPCODE_DEV0_F4_MASK
61051. BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_OPCODE_DEV0_F4__SHIFT
61052. BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_REQEN_LOW_DEV0_F4_MASK
61053. BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_REQEN_LOW_DEV0_F4__SHIFT
61054. BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F5_MASK
61055. BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F5__SHIFT
61056. BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_NR_DEV0_F5_MASK
61057. BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_NR_DEV0_F5__SHIFT
61058. BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F5_MASK
61059. BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F5__SHIFT
61060. BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F5_MASK
61061. BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F5__SHIFT
61062. BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_LENGTH_DEV0_F5_MASK
61063. BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_LENGTH_DEV0_F5__SHIFT
61064. BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_NR_DEV0_F5_MASK
61065. BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_NR_DEV0_F5__SHIFT
61066. BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_OPCODE_DEV0_F5_MASK
61067. BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_OPCODE_DEV0_F5__SHIFT
61068. BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_REQEN_LOW_DEV0_F5_MASK
61069. BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_REQEN_LOW_DEV0_F5__SHIFT
61070. BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F6_MASK
61071. BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F6__SHIFT
61072. BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_NR_DEV0_F6_MASK
61073. BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_NR_DEV0_F6__SHIFT
61074. BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F6_MASK
61075. BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F6__SHIFT
61076. BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F6_MASK
61077. BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F6__SHIFT
61078. BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_LENGTH_DEV0_F6_MASK
61079. BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_LENGTH_DEV0_F6__SHIFT
61080. BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_NR_DEV0_F6_MASK
61081. BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_NR_DEV0_F6__SHIFT
61082. BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_OPCODE_DEV0_F6_MASK
61083. BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_OPCODE_DEV0_F6__SHIFT
61084. BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_REQEN_LOW_DEV0_F6_MASK
61085. BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_REQEN_LOW_DEV0_F6__SHIFT
61086. BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F7_MASK
61087. BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F7__SHIFT
61088. BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_NR_DEV0_F7_MASK
61089. BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_NR_DEV0_F7__SHIFT
61090. BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F7_MASK
61091. BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F7__SHIFT
61092. BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F7_MASK
61093. BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F7__SHIFT
61094. BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_LENGTH_DEV0_F7_MASK
61095. BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_LENGTH_DEV0_F7__SHIFT
61096. BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_NR_DEV0_F7_MASK
61097. BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_NR_DEV0_F7__SHIFT
61098. BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_OPCODE_DEV0_F7_MASK
61099. BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_OPCODE_DEV0_F7__SHIFT
61100. BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_REQEN_LOW_DEV0_F7_MASK
61101. BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_REQEN_LOW_DEV0_F7__SHIFT
61102. BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
61103. BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
61104. BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
61105. BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
61106. BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
61107. BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__MASK
61108. BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
61109. BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
61110. BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__MASK
61111. BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
61112. BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
61113. BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
61114. BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
61115. BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
61116. BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
61117. BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__MASK
61118. BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
61119. BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
61120. BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__MASK
61121. BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
61122. BIF_BACO_DEBUG_IND__BIF_BACO_SCANDUMP_FLG_MASK
61123. BIF_BACO_DEBUG_IND__BIF_BACO_SCANDUMP_FLG__SHIFT
61124. BIF_BACO_DEBUG_LATCH_IND__BIF_BACO_LATCH_FLG_MASK
61125. BIF_BACO_DEBUG_LATCH_IND__BIF_BACO_LATCH_FLG__SHIFT
61126. BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK
61127. BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT
61128. BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK
61129. BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT
61130. BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK
61131. BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__MASK
61132. BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT
61133. BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK
61134. BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__MASK
61135. BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT
61136. BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK
61137. BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__MASK
61138. BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT
61139. BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK
61140. BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT
61141. BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK
61142. BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__MASK
61143. BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT
61144. BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK
61145. BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT
61146. BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK
61147. BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__MASK
61148. BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT
61149. BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK
61150. BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__MASK
61151. BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT
61152. BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK
61153. BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__MASK
61154. BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT
61155. BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK
61156. BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__MASK
61157. BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT
61158. BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK
61159. BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__MASK
61160. BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT
61161. BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK
61162. BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__MASK
61163. BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT
61164. BIF_BACO_MSIC_IND__ACPI_BACO_MUX_DIS_MASK
61165. BIF_BACO_MSIC_IND__ACPI_BACO_MUX_DIS__SHIFT
61166. BIF_BACO_MSIC_IND__BACO_LINK_RST_SEL_MASK
61167. BIF_BACO_MSIC_IND__BACO_LINK_RST_SEL__SHIFT
61168. BIF_BACO_MSIC_IND__BIF_XTALIN_SEL_MASK
61169. BIF_BACO_MSIC_IND__BIF_XTALIN_SEL__SHIFT
61170. BIF_BACO_MSIC__ACPI_BACO_MUX_DIS_MASK
61171. BIF_BACO_MSIC__ACPI_BACO_MUX_DIS__SHIFT
61172. BIF_BACO_MSIC__BACO_LINK_RST_SEL_MASK
61173. BIF_BACO_MSIC__BACO_LINK_RST_SEL__SHIFT
61174. BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK
61175. BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT
61176. BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
61177. BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__MASK
61178. BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
61179. BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
61180. BIF_BME_STATUS__DMA_ON_BME_LOW__MASK
61181. BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
61182. BIF_BUSNUM_CNTL1_IND__ID_MASK_MASK
61183. BIF_BUSNUM_CNTL1_IND__ID_MASK__SHIFT
61184. BIF_BUSNUM_CNTL1__ID_MASK_MASK
61185. BIF_BUSNUM_CNTL1__ID_MASK__SHIFT
61186. BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_EN_MASK
61187. BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_EN__SHIFT
61188. BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_SEL_MASK
61189. BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_SEL__SHIFT
61190. BIF_BUSNUM_CNTL2_IND__ERROR_MULTIPLE_ID_MATCH_MASK
61191. BIF_BUSNUM_CNTL2_IND__ERROR_MULTIPLE_ID_MATCH__SHIFT
61192. BIF_BUSNUM_CNTL2_IND__HDPREG_CNTL_MASK
61193. BIF_BUSNUM_CNTL2_IND__HDPREG_CNTL__SHIFT
61194. BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK
61195. BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT
61196. BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK
61197. BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT
61198. BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK
61199. BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT
61200. BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK
61201. BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT
61202. BIF_BUSNUM_LIST0_IND__ID0_MASK
61203. BIF_BUSNUM_LIST0_IND__ID0__SHIFT
61204. BIF_BUSNUM_LIST0_IND__ID1_MASK
61205. BIF_BUSNUM_LIST0_IND__ID1__SHIFT
61206. BIF_BUSNUM_LIST0_IND__ID2_MASK
61207. BIF_BUSNUM_LIST0_IND__ID2__SHIFT
61208. BIF_BUSNUM_LIST0_IND__ID3_MASK
61209. BIF_BUSNUM_LIST0_IND__ID3__SHIFT
61210. BIF_BUSNUM_LIST0__ID0_MASK
61211. BIF_BUSNUM_LIST0__ID0__SHIFT
61212. BIF_BUSNUM_LIST0__ID1_MASK
61213. BIF_BUSNUM_LIST0__ID1__SHIFT
61214. BIF_BUSNUM_LIST0__ID2_MASK
61215. BIF_BUSNUM_LIST0__ID2__SHIFT
61216. BIF_BUSNUM_LIST0__ID3_MASK
61217. BIF_BUSNUM_LIST0__ID3__SHIFT
61218. BIF_BUSNUM_LIST1_IND__ID4_MASK
61219. BIF_BUSNUM_LIST1_IND__ID4__SHIFT
61220. BIF_BUSNUM_LIST1_IND__ID5_MASK
61221. BIF_BUSNUM_LIST1_IND__ID5__SHIFT
61222. BIF_BUSNUM_LIST1_IND__ID6_MASK
61223. BIF_BUSNUM_LIST1_IND__ID6__SHIFT
61224. BIF_BUSNUM_LIST1_IND__ID7_MASK
61225. BIF_BUSNUM_LIST1_IND__ID7__SHIFT
61226. BIF_BUSNUM_LIST1__ID4_MASK
61227. BIF_BUSNUM_LIST1__ID4__SHIFT
61228. BIF_BUSNUM_LIST1__ID5_MASK
61229. BIF_BUSNUM_LIST1__ID5__SHIFT
61230. BIF_BUSNUM_LIST1__ID6_MASK
61231. BIF_BUSNUM_LIST1__ID6__SHIFT
61232. BIF_BUSNUM_LIST1__ID7_MASK
61233. BIF_BUSNUM_LIST1__ID7__SHIFT
61234. BIF_BUSY_DELAY_CNTR_IND__DELAY_CNT_MASK
61235. BIF_BUSY_DELAY_CNTR_IND__DELAY_CNT__SHIFT
61236. BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK
61237. BIF_BUSY_DELAY_CNTR__DELAY_CNT__MASK
61238. BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT
61239. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
61240. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
61241. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
61242. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
61243. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
61244. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
61245. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
61246. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
61247. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
61248. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
61249. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
61250. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
61251. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
61252. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
61253. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
61254. BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
61255. BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
61256. BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
61257. BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
61258. BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
61259. BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
61260. BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
61261. BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
61262. BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
61263. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
61264. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
61265. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
61266. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
61267. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
61268. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
61269. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
61270. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
61271. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
61272. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
61273. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
61274. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
61275. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
61276. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
61277. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
61278. BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
61279. BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
61280. BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
61281. BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
61282. BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
61283. BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
61284. BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
61285. BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
61286. BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
61287. BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
61288. BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
61289. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0_MASK
61290. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT
61291. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1_MASK
61292. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT
61293. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2_MASK
61294. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT
61295. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3_MASK
61296. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT
61297. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4_MASK
61298. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT
61299. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5_MASK
61300. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT
61301. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6_MASK
61302. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT
61303. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7_MASK
61304. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT
61305. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8_MASK
61306. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT
61307. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9_MASK
61308. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT
61309. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK
61310. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
61311. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
61312. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
61313. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0_MASK
61314. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT
61315. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1_MASK
61316. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT
61317. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2_MASK
61318. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT
61319. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3_MASK
61320. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT
61321. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4_MASK
61322. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT
61323. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5_MASK
61324. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT
61325. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6_MASK
61326. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT
61327. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7_MASK
61328. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT
61329. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8_MASK
61330. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT
61331. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9_MASK
61332. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT
61333. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK
61334. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
61335. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK
61336. BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
61337. BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
61338. BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
61339. BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
61340. BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
61341. BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
61342. BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
61343. BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
61344. BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
61345. BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
61346. BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
61347. BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
61348. BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
61349. BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
61350. BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
61351. BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
61352. BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
61353. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
61354. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
61355. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
61356. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
61357. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
61358. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
61359. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
61360. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
61361. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
61362. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
61363. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
61364. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
61365. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
61366. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
61367. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
61368. BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
61369. BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA_MASK
61370. BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA__SHIFT
61371. BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI_MASK
61372. BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
61373. BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER_MASK
61374. BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER__SHIFT
61375. BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET_MASK
61376. BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET__SHIFT
61377. BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
61378. BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
61379. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
61380. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
61381. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
61382. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
61383. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
61384. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
61385. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
61386. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
61387. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
61388. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
61389. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
61390. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
61391. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
61392. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
61393. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
61394. BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
61395. BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
61396. BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
61397. BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
61398. BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
61399. BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
61400. BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
61401. BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
61402. BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
61403. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
61404. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
61405. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
61406. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
61407. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
61408. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
61409. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
61410. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
61411. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
61412. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
61413. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
61414. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
61415. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
61416. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
61417. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
61418. BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
61419. BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
61420. BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
61421. BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
61422. BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
61423. BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
61424. BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
61425. BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
61426. BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
61427. BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
61428. BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
61429. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0_MASK
61430. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0__SHIFT
61431. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1_MASK
61432. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1__SHIFT
61433. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2_MASK
61434. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2__SHIFT
61435. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3_MASK
61436. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3__SHIFT
61437. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4_MASK
61438. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4__SHIFT
61439. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5_MASK
61440. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5__SHIFT
61441. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6_MASK
61442. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6__SHIFT
61443. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7_MASK
61444. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7__SHIFT
61445. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8_MASK
61446. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8__SHIFT
61447. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9_MASK
61448. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9__SHIFT
61449. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0_MASK
61450. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
61451. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1_MASK
61452. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
61453. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0_MASK
61454. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0__SHIFT
61455. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1_MASK
61456. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1__SHIFT
61457. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2_MASK
61458. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2__SHIFT
61459. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3_MASK
61460. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3__SHIFT
61461. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4_MASK
61462. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4__SHIFT
61463. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5_MASK
61464. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5__SHIFT
61465. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6_MASK
61466. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6__SHIFT
61467. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7_MASK
61468. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7__SHIFT
61469. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8_MASK
61470. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8__SHIFT
61471. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9_MASK
61472. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9__SHIFT
61473. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0_MASK
61474. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
61475. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1_MASK
61476. BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
61477. BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
61478. BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
61479. BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
61480. BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
61481. BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
61482. BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
61483. BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
61484. BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
61485. BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
61486. BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
61487. BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
61488. BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
61489. BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
61490. BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
61491. BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
61492. BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
61493. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
61494. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
61495. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
61496. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
61497. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
61498. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
61499. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
61500. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
61501. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
61502. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
61503. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
61504. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
61505. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
61506. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
61507. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
61508. BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
61509. BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA_MASK
61510. BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA__SHIFT
61511. BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI_MASK
61512. BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
61513. BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER_MASK
61514. BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER__SHIFT
61515. BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET_MASK
61516. BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET__SHIFT
61517. BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
61518. BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
61519. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
61520. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
61521. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
61522. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
61523. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
61524. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
61525. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
61526. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
61527. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
61528. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
61529. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
61530. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
61531. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
61532. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
61533. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
61534. BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
61535. BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
61536. BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
61537. BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
61538. BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
61539. BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
61540. BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
61541. BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
61542. BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
61543. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
61544. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
61545. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
61546. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
61547. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
61548. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
61549. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
61550. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
61551. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
61552. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
61553. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
61554. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
61555. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
61556. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
61557. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
61558. BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
61559. BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
61560. BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
61561. BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
61562. BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
61563. BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
61564. BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
61565. BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
61566. BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
61567. BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
61568. BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
61569. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0_MASK
61570. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0__SHIFT
61571. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1_MASK
61572. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1__SHIFT
61573. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2_MASK
61574. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2__SHIFT
61575. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3_MASK
61576. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3__SHIFT
61577. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4_MASK
61578. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4__SHIFT
61579. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5_MASK
61580. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5__SHIFT
61581. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6_MASK
61582. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6__SHIFT
61583. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7_MASK
61584. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7__SHIFT
61585. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8_MASK
61586. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8__SHIFT
61587. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9_MASK
61588. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9__SHIFT
61589. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0_MASK
61590. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
61591. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1_MASK
61592. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
61593. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0_MASK
61594. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0__SHIFT
61595. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1_MASK
61596. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1__SHIFT
61597. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2_MASK
61598. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2__SHIFT
61599. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3_MASK
61600. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3__SHIFT
61601. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4_MASK
61602. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4__SHIFT
61603. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5_MASK
61604. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5__SHIFT
61605. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6_MASK
61606. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6__SHIFT
61607. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7_MASK
61608. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7__SHIFT
61609. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8_MASK
61610. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8__SHIFT
61611. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9_MASK
61612. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9__SHIFT
61613. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0_MASK
61614. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
61615. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1_MASK
61616. BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
61617. BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
61618. BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
61619. BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
61620. BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
61621. BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
61622. BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
61623. BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
61624. BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
61625. BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
61626. BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
61627. BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
61628. BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
61629. BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
61630. BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
61631. BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
61632. BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
61633. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
61634. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
61635. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
61636. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
61637. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
61638. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
61639. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
61640. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
61641. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
61642. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
61643. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
61644. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
61645. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
61646. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
61647. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
61648. BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
61649. BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA_MASK
61650. BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA__SHIFT
61651. BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI_MASK
61652. BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
61653. BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER_MASK
61654. BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER__SHIFT
61655. BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET_MASK
61656. BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET__SHIFT
61657. BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
61658. BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
61659. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
61660. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
61661. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
61662. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
61663. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
61664. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
61665. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
61666. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
61667. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
61668. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
61669. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
61670. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
61671. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
61672. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
61673. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
61674. BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
61675. BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
61676. BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
61677. BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
61678. BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
61679. BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
61680. BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
61681. BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
61682. BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
61683. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
61684. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
61685. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
61686. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
61687. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
61688. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
61689. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
61690. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
61691. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
61692. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
61693. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
61694. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
61695. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
61696. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
61697. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
61698. BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
61699. BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
61700. BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
61701. BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
61702. BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
61703. BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
61704. BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
61705. BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
61706. BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
61707. BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
61708. BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
61709. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0_MASK
61710. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0__SHIFT
61711. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1_MASK
61712. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1__SHIFT
61713. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2_MASK
61714. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2__SHIFT
61715. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3_MASK
61716. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3__SHIFT
61717. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4_MASK
61718. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4__SHIFT
61719. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5_MASK
61720. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5__SHIFT
61721. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6_MASK
61722. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6__SHIFT
61723. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7_MASK
61724. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7__SHIFT
61725. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8_MASK
61726. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8__SHIFT
61727. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9_MASK
61728. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9__SHIFT
61729. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0_MASK
61730. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
61731. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1_MASK
61732. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
61733. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0_MASK
61734. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0__SHIFT
61735. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1_MASK
61736. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1__SHIFT
61737. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2_MASK
61738. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2__SHIFT
61739. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3_MASK
61740. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3__SHIFT
61741. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4_MASK
61742. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4__SHIFT
61743. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5_MASK
61744. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5__SHIFT
61745. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6_MASK
61746. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6__SHIFT
61747. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7_MASK
61748. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7__SHIFT
61749. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8_MASK
61750. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8__SHIFT
61751. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9_MASK
61752. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9__SHIFT
61753. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0_MASK
61754. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
61755. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1_MASK
61756. BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
61757. BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
61758. BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
61759. BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
61760. BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
61761. BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
61762. BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
61763. BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
61764. BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
61765. BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
61766. BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
61767. BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
61768. BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
61769. BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
61770. BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
61771. BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
61772. BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
61773. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
61774. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
61775. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
61776. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
61777. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
61778. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
61779. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
61780. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
61781. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
61782. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
61783. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
61784. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
61785. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
61786. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
61787. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
61788. BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
61789. BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA_MASK
61790. BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA__SHIFT
61791. BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI_MASK
61792. BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
61793. BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER_MASK
61794. BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER__SHIFT
61795. BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET_MASK
61796. BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET__SHIFT
61797. BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
61798. BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
61799. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
61800. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
61801. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
61802. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
61803. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
61804. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
61805. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
61806. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
61807. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
61808. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
61809. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
61810. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
61811. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
61812. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
61813. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
61814. BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
61815. BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
61816. BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
61817. BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
61818. BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
61819. BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
61820. BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
61821. BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
61822. BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
61823. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
61824. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
61825. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
61826. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
61827. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
61828. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
61829. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
61830. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
61831. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
61832. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
61833. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
61834. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
61835. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
61836. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
61837. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
61838. BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
61839. BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
61840. BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
61841. BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
61842. BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
61843. BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
61844. BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
61845. BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
61846. BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
61847. BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
61848. BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
61849. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0_MASK
61850. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0__SHIFT
61851. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1_MASK
61852. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1__SHIFT
61853. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2_MASK
61854. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2__SHIFT
61855. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3_MASK
61856. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3__SHIFT
61857. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4_MASK
61858. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4__SHIFT
61859. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5_MASK
61860. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5__SHIFT
61861. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6_MASK
61862. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6__SHIFT
61863. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7_MASK
61864. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7__SHIFT
61865. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8_MASK
61866. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8__SHIFT
61867. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9_MASK
61868. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9__SHIFT
61869. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0_MASK
61870. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
61871. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1_MASK
61872. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
61873. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0_MASK
61874. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0__SHIFT
61875. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1_MASK
61876. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1__SHIFT
61877. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2_MASK
61878. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2__SHIFT
61879. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3_MASK
61880. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3__SHIFT
61881. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4_MASK
61882. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4__SHIFT
61883. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5_MASK
61884. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5__SHIFT
61885. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6_MASK
61886. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6__SHIFT
61887. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7_MASK
61888. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7__SHIFT
61889. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8_MASK
61890. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8__SHIFT
61891. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9_MASK
61892. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9__SHIFT
61893. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0_MASK
61894. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
61895. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1_MASK
61896. BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
61897. BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
61898. BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
61899. BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
61900. BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
61901. BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
61902. BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
61903. BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
61904. BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
61905. BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
61906. BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
61907. BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
61908. BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
61909. BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
61910. BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
61911. BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
61912. BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
61913. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
61914. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
61915. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
61916. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
61917. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
61918. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
61919. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
61920. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
61921. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
61922. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
61923. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
61924. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
61925. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
61926. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
61927. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
61928. BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
61929. BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA_MASK
61930. BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA__SHIFT
61931. BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI_MASK
61932. BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
61933. BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER_MASK
61934. BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER__SHIFT
61935. BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET_MASK
61936. BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET__SHIFT
61937. BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
61938. BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
61939. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
61940. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
61941. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
61942. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
61943. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
61944. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
61945. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
61946. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
61947. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
61948. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
61949. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
61950. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
61951. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
61952. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
61953. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
61954. BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
61955. BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
61956. BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
61957. BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
61958. BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
61959. BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
61960. BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
61961. BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
61962. BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
61963. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
61964. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
61965. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
61966. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
61967. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
61968. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
61969. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
61970. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
61971. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
61972. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
61973. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
61974. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
61975. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
61976. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
61977. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
61978. BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
61979. BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
61980. BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
61981. BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
61982. BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
61983. BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
61984. BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
61985. BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
61986. BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
61987. BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
61988. BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
61989. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0_MASK
61990. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0__SHIFT
61991. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1_MASK
61992. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1__SHIFT
61993. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2_MASK
61994. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2__SHIFT
61995. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3_MASK
61996. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3__SHIFT
61997. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4_MASK
61998. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4__SHIFT
61999. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5_MASK
62000. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5__SHIFT
62001. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6_MASK
62002. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6__SHIFT
62003. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7_MASK
62004. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7__SHIFT
62005. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8_MASK
62006. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8__SHIFT
62007. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9_MASK
62008. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9__SHIFT
62009. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0_MASK
62010. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
62011. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1_MASK
62012. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
62013. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0_MASK
62014. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0__SHIFT
62015. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1_MASK
62016. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1__SHIFT
62017. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2_MASK
62018. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2__SHIFT
62019. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3_MASK
62020. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3__SHIFT
62021. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4_MASK
62022. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4__SHIFT
62023. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5_MASK
62024. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5__SHIFT
62025. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6_MASK
62026. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6__SHIFT
62027. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7_MASK
62028. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7__SHIFT
62029. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8_MASK
62030. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8__SHIFT
62031. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9_MASK
62032. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9__SHIFT
62033. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0_MASK
62034. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
62035. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1_MASK
62036. BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
62037. BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
62038. BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
62039. BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
62040. BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
62041. BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
62042. BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
62043. BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
62044. BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
62045. BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
62046. BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
62047. BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
62048. BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
62049. BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
62050. BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
62051. BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
62052. BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
62053. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
62054. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
62055. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
62056. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
62057. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
62058. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
62059. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
62060. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
62061. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
62062. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
62063. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
62064. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
62065. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
62066. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
62067. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
62068. BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
62069. BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA_MASK
62070. BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA__SHIFT
62071. BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI_MASK
62072. BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
62073. BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER_MASK
62074. BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER__SHIFT
62075. BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET_MASK
62076. BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET__SHIFT
62077. BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
62078. BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
62079. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
62080. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
62081. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
62082. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
62083. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
62084. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
62085. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
62086. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
62087. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
62088. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
62089. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
62090. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
62091. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
62092. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
62093. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
62094. BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
62095. BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
62096. BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
62097. BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
62098. BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
62099. BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
62100. BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
62101. BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
62102. BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
62103. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
62104. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
62105. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
62106. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
62107. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
62108. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
62109. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
62110. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
62111. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
62112. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
62113. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
62114. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
62115. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
62116. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
62117. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
62118. BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
62119. BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
62120. BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
62121. BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
62122. BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
62123. BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
62124. BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
62125. BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
62126. BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
62127. BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
62128. BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
62129. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0_MASK
62130. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0__SHIFT
62131. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1_MASK
62132. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1__SHIFT
62133. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2_MASK
62134. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2__SHIFT
62135. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3_MASK
62136. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3__SHIFT
62137. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4_MASK
62138. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4__SHIFT
62139. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5_MASK
62140. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5__SHIFT
62141. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6_MASK
62142. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6__SHIFT
62143. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7_MASK
62144. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7__SHIFT
62145. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8_MASK
62146. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8__SHIFT
62147. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9_MASK
62148. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9__SHIFT
62149. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0_MASK
62150. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
62151. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1_MASK
62152. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
62153. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0_MASK
62154. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0__SHIFT
62155. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1_MASK
62156. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1__SHIFT
62157. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2_MASK
62158. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2__SHIFT
62159. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3_MASK
62160. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3__SHIFT
62161. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4_MASK
62162. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4__SHIFT
62163. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5_MASK
62164. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5__SHIFT
62165. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6_MASK
62166. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6__SHIFT
62167. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7_MASK
62168. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7__SHIFT
62169. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8_MASK
62170. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8__SHIFT
62171. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9_MASK
62172. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9__SHIFT
62173. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0_MASK
62174. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
62175. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1_MASK
62176. BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
62177. BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
62178. BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
62179. BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
62180. BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
62181. BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
62182. BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
62183. BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
62184. BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
62185. BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
62186. BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
62187. BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
62188. BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
62189. BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
62190. BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
62191. BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
62192. BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
62193. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
62194. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
62195. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
62196. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
62197. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
62198. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
62199. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
62200. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
62201. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
62202. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
62203. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
62204. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
62205. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
62206. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
62207. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
62208. BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
62209. BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA_MASK
62210. BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA__SHIFT
62211. BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI_MASK
62212. BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
62213. BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER_MASK
62214. BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER__SHIFT
62215. BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET_MASK
62216. BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET__SHIFT
62217. BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
62218. BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
62219. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
62220. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
62221. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
62222. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
62223. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
62224. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
62225. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
62226. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
62227. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
62228. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
62229. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
62230. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
62231. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
62232. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
62233. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
62234. BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
62235. BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
62236. BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
62237. BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
62238. BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
62239. BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
62240. BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
62241. BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
62242. BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
62243. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
62244. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
62245. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
62246. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
62247. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
62248. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
62249. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
62250. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
62251. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
62252. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
62253. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
62254. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
62255. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
62256. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
62257. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
62258. BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
62259. BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
62260. BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
62261. BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
62262. BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
62263. BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
62264. BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
62265. BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
62266. BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
62267. BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
62268. BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
62269. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP0_MASK
62270. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP0__SHIFT
62271. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP1_MASK
62272. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP1__SHIFT
62273. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP2_MASK
62274. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP2__SHIFT
62275. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP3_MASK
62276. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP3__SHIFT
62277. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP4_MASK
62278. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP4__SHIFT
62279. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP5_MASK
62280. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP5__SHIFT
62281. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP6_MASK
62282. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP6__SHIFT
62283. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP7_MASK
62284. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP7__SHIFT
62285. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP8_MASK
62286. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP8__SHIFT
62287. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP9_MASK
62288. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP9__SHIFT
62289. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA0_MASK
62290. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
62291. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA1_MASK
62292. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
62293. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP0_MASK
62294. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP0__SHIFT
62295. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP1_MASK
62296. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP1__SHIFT
62297. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP2_MASK
62298. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP2__SHIFT
62299. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP3_MASK
62300. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP3__SHIFT
62301. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP4_MASK
62302. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP4__SHIFT
62303. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP5_MASK
62304. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP5__SHIFT
62305. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP6_MASK
62306. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP6__SHIFT
62307. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP7_MASK
62308. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP7__SHIFT
62309. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP8_MASK
62310. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP8__SHIFT
62311. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP9_MASK
62312. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP9__SHIFT
62313. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA0_MASK
62314. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
62315. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA1_MASK
62316. BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
62317. BIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
62318. BIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
62319. BIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
62320. BIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
62321. BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
62322. BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
62323. BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
62324. BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
62325. BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
62326. BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
62327. BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
62328. BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
62329. BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
62330. BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
62331. BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
62332. BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
62333. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
62334. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
62335. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
62336. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
62337. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
62338. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
62339. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
62340. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
62341. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
62342. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
62343. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
62344. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
62345. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
62346. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
62347. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
62348. BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
62349. BIF_BX_DEV0_EPF0_VF16_MM_DATA__MM_DATA_MASK
62350. BIF_BX_DEV0_EPF0_VF16_MM_DATA__MM_DATA__SHIFT
62351. BIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI__MM_OFFSET_HI_MASK
62352. BIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
62353. BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_APER_MASK
62354. BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_APER__SHIFT
62355. BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_OFFSET_MASK
62356. BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_OFFSET__SHIFT
62357. BIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
62358. BIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
62359. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
62360. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
62361. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
62362. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
62363. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
62364. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
62365. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
62366. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
62367. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
62368. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
62369. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
62370. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
62371. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
62372. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
62373. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
62374. BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
62375. BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
62376. BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
62377. BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
62378. BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
62379. BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
62380. BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
62381. BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
62382. BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
62383. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
62384. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
62385. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
62386. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
62387. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
62388. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
62389. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
62390. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
62391. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
62392. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
62393. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
62394. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
62395. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
62396. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
62397. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
62398. BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
62399. BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
62400. BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
62401. BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
62402. BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
62403. BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
62404. BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
62405. BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
62406. BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
62407. BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
62408. BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
62409. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP0_MASK
62410. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP0__SHIFT
62411. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP1_MASK
62412. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP1__SHIFT
62413. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP2_MASK
62414. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP2__SHIFT
62415. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP3_MASK
62416. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP3__SHIFT
62417. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP4_MASK
62418. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP4__SHIFT
62419. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP5_MASK
62420. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP5__SHIFT
62421. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP6_MASK
62422. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP6__SHIFT
62423. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP7_MASK
62424. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP7__SHIFT
62425. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP8_MASK
62426. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP8__SHIFT
62427. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP9_MASK
62428. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP9__SHIFT
62429. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA0_MASK
62430. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
62431. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA1_MASK
62432. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
62433. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP0_MASK
62434. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP0__SHIFT
62435. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP1_MASK
62436. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP1__SHIFT
62437. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP2_MASK
62438. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP2__SHIFT
62439. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP3_MASK
62440. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP3__SHIFT
62441. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP4_MASK
62442. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP4__SHIFT
62443. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP5_MASK
62444. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP5__SHIFT
62445. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP6_MASK
62446. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP6__SHIFT
62447. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP7_MASK
62448. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP7__SHIFT
62449. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP8_MASK
62450. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP8__SHIFT
62451. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP9_MASK
62452. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP9__SHIFT
62453. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA0_MASK
62454. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
62455. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA1_MASK
62456. BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
62457. BIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
62458. BIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
62459. BIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
62460. BIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
62461. BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
62462. BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
62463. BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
62464. BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
62465. BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
62466. BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
62467. BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
62468. BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
62469. BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
62470. BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
62471. BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
62472. BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
62473. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
62474. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
62475. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
62476. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
62477. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
62478. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
62479. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
62480. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
62481. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
62482. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
62483. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
62484. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
62485. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
62486. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
62487. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
62488. BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
62489. BIF_BX_DEV0_EPF0_VF17_MM_DATA__MM_DATA_MASK
62490. BIF_BX_DEV0_EPF0_VF17_MM_DATA__MM_DATA__SHIFT
62491. BIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI__MM_OFFSET_HI_MASK
62492. BIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
62493. BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_APER_MASK
62494. BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_APER__SHIFT
62495. BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_OFFSET_MASK
62496. BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_OFFSET__SHIFT
62497. BIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
62498. BIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
62499. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
62500. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
62501. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
62502. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
62503. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
62504. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
62505. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
62506. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
62507. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
62508. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
62509. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
62510. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
62511. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
62512. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
62513. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
62514. BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
62515. BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
62516. BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
62517. BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
62518. BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
62519. BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
62520. BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
62521. BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
62522. BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
62523. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
62524. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
62525. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
62526. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
62527. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
62528. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
62529. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
62530. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
62531. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
62532. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
62533. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
62534. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
62535. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
62536. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
62537. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
62538. BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
62539. BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
62540. BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
62541. BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
62542. BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
62543. BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
62544. BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
62545. BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
62546. BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
62547. BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
62548. BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
62549. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP0_MASK
62550. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP0__SHIFT
62551. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP1_MASK
62552. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP1__SHIFT
62553. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP2_MASK
62554. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP2__SHIFT
62555. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP3_MASK
62556. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP3__SHIFT
62557. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP4_MASK
62558. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP4__SHIFT
62559. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP5_MASK
62560. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP5__SHIFT
62561. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP6_MASK
62562. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP6__SHIFT
62563. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP7_MASK
62564. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP7__SHIFT
62565. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP8_MASK
62566. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP8__SHIFT
62567. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP9_MASK
62568. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP9__SHIFT
62569. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA0_MASK
62570. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
62571. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA1_MASK
62572. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
62573. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP0_MASK
62574. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP0__SHIFT
62575. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP1_MASK
62576. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP1__SHIFT
62577. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP2_MASK
62578. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP2__SHIFT
62579. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP3_MASK
62580. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP3__SHIFT
62581. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP4_MASK
62582. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP4__SHIFT
62583. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP5_MASK
62584. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP5__SHIFT
62585. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP6_MASK
62586. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP6__SHIFT
62587. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP7_MASK
62588. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP7__SHIFT
62589. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP8_MASK
62590. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP8__SHIFT
62591. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP9_MASK
62592. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP9__SHIFT
62593. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA0_MASK
62594. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
62595. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA1_MASK
62596. BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
62597. BIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
62598. BIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
62599. BIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
62600. BIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
62601. BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
62602. BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
62603. BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
62604. BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
62605. BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
62606. BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
62607. BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
62608. BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
62609. BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
62610. BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
62611. BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
62612. BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
62613. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
62614. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
62615. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
62616. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
62617. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
62618. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
62619. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
62620. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
62621. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
62622. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
62623. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
62624. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
62625. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
62626. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
62627. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
62628. BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
62629. BIF_BX_DEV0_EPF0_VF18_MM_DATA__MM_DATA_MASK
62630. BIF_BX_DEV0_EPF0_VF18_MM_DATA__MM_DATA__SHIFT
62631. BIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI__MM_OFFSET_HI_MASK
62632. BIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
62633. BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_APER_MASK
62634. BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_APER__SHIFT
62635. BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_OFFSET_MASK
62636. BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_OFFSET__SHIFT
62637. BIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
62638. BIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
62639. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
62640. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
62641. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
62642. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
62643. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
62644. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
62645. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
62646. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
62647. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
62648. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
62649. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
62650. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
62651. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
62652. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
62653. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
62654. BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
62655. BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
62656. BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
62657. BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
62658. BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
62659. BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
62660. BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
62661. BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
62662. BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
62663. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
62664. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
62665. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
62666. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
62667. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
62668. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
62669. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
62670. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
62671. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
62672. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
62673. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
62674. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
62675. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
62676. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
62677. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
62678. BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
62679. BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
62680. BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
62681. BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
62682. BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
62683. BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
62684. BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
62685. BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
62686. BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
62687. BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
62688. BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
62689. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP0_MASK
62690. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP0__SHIFT
62691. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP1_MASK
62692. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP1__SHIFT
62693. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP2_MASK
62694. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP2__SHIFT
62695. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP3_MASK
62696. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP3__SHIFT
62697. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP4_MASK
62698. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP4__SHIFT
62699. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP5_MASK
62700. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP5__SHIFT
62701. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP6_MASK
62702. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP6__SHIFT
62703. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP7_MASK
62704. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP7__SHIFT
62705. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP8_MASK
62706. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP8__SHIFT
62707. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP9_MASK
62708. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP9__SHIFT
62709. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA0_MASK
62710. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
62711. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA1_MASK
62712. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
62713. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP0_MASK
62714. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP0__SHIFT
62715. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP1_MASK
62716. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP1__SHIFT
62717. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP2_MASK
62718. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP2__SHIFT
62719. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP3_MASK
62720. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP3__SHIFT
62721. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP4_MASK
62722. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP4__SHIFT
62723. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP5_MASK
62724. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP5__SHIFT
62725. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP6_MASK
62726. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP6__SHIFT
62727. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP7_MASK
62728. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP7__SHIFT
62729. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP8_MASK
62730. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP8__SHIFT
62731. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP9_MASK
62732. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP9__SHIFT
62733. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA0_MASK
62734. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
62735. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA1_MASK
62736. BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
62737. BIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
62738. BIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
62739. BIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
62740. BIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
62741. BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
62742. BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
62743. BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
62744. BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
62745. BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
62746. BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
62747. BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
62748. BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
62749. BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
62750. BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
62751. BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
62752. BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
62753. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
62754. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
62755. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
62756. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
62757. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
62758. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
62759. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
62760. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
62761. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
62762. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
62763. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
62764. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
62765. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
62766. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
62767. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
62768. BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
62769. BIF_BX_DEV0_EPF0_VF19_MM_DATA__MM_DATA_MASK
62770. BIF_BX_DEV0_EPF0_VF19_MM_DATA__MM_DATA__SHIFT
62771. BIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI__MM_OFFSET_HI_MASK
62772. BIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
62773. BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_APER_MASK
62774. BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_APER__SHIFT
62775. BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_OFFSET_MASK
62776. BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_OFFSET__SHIFT
62777. BIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
62778. BIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
62779. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
62780. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
62781. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
62782. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
62783. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
62784. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
62785. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
62786. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
62787. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
62788. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
62789. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
62790. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
62791. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
62792. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
62793. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
62794. BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
62795. BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
62796. BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
62797. BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
62798. BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
62799. BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
62800. BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
62801. BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
62802. BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
62803. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
62804. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
62805. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
62806. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
62807. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
62808. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
62809. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
62810. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
62811. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
62812. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
62813. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
62814. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
62815. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
62816. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
62817. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
62818. BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
62819. BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
62820. BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
62821. BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
62822. BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
62823. BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
62824. BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
62825. BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
62826. BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
62827. BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
62828. BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
62829. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0_MASK
62830. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT
62831. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1_MASK
62832. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT
62833. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2_MASK
62834. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT
62835. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3_MASK
62836. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT
62837. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4_MASK
62838. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT
62839. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5_MASK
62840. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT
62841. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6_MASK
62842. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT
62843. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7_MASK
62844. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT
62845. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8_MASK
62846. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT
62847. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9_MASK
62848. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT
62849. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK
62850. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
62851. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK
62852. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
62853. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0_MASK
62854. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT
62855. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1_MASK
62856. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT
62857. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2_MASK
62858. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT
62859. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3_MASK
62860. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT
62861. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4_MASK
62862. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT
62863. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5_MASK
62864. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT
62865. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6_MASK
62866. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT
62867. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7_MASK
62868. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT
62869. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8_MASK
62870. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT
62871. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9_MASK
62872. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT
62873. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK
62874. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
62875. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK
62876. BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
62877. BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
62878. BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
62879. BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
62880. BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
62881. BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
62882. BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
62883. BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
62884. BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
62885. BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
62886. BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
62887. BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
62888. BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
62889. BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
62890. BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
62891. BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
62892. BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
62893. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
62894. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
62895. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
62896. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
62897. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
62898. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
62899. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
62900. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
62901. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
62902. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
62903. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
62904. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
62905. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
62906. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
62907. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
62908. BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
62909. BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA_MASK
62910. BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA__SHIFT
62911. BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI_MASK
62912. BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
62913. BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER_MASK
62914. BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER__SHIFT
62915. BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET_MASK
62916. BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET__SHIFT
62917. BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
62918. BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
62919. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
62920. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
62921. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
62922. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
62923. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
62924. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
62925. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
62926. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
62927. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
62928. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
62929. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
62930. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
62931. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
62932. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
62933. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
62934. BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
62935. BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
62936. BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
62937. BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
62938. BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
62939. BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
62940. BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
62941. BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
62942. BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
62943. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
62944. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
62945. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
62946. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
62947. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
62948. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
62949. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
62950. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
62951. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
62952. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
62953. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
62954. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
62955. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
62956. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
62957. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
62958. BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
62959. BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
62960. BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
62961. BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
62962. BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
62963. BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
62964. BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
62965. BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
62966. BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
62967. BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
62968. BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
62969. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP0_MASK
62970. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP0__SHIFT
62971. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP1_MASK
62972. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP1__SHIFT
62973. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP2_MASK
62974. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP2__SHIFT
62975. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP3_MASK
62976. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP3__SHIFT
62977. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP4_MASK
62978. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP4__SHIFT
62979. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP5_MASK
62980. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP5__SHIFT
62981. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP6_MASK
62982. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP6__SHIFT
62983. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP7_MASK
62984. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP7__SHIFT
62985. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP8_MASK
62986. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP8__SHIFT
62987. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP9_MASK
62988. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP9__SHIFT
62989. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA0_MASK
62990. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
62991. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA1_MASK
62992. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
62993. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP0_MASK
62994. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP0__SHIFT
62995. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP1_MASK
62996. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP1__SHIFT
62997. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP2_MASK
62998. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP2__SHIFT
62999. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP3_MASK
63000. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP3__SHIFT
63001. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP4_MASK
63002. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP4__SHIFT
63003. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP5_MASK
63004. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP5__SHIFT
63005. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP6_MASK
63006. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP6__SHIFT
63007. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP7_MASK
63008. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP7__SHIFT
63009. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP8_MASK
63010. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP8__SHIFT
63011. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP9_MASK
63012. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP9__SHIFT
63013. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA0_MASK
63014. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
63015. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA1_MASK
63016. BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
63017. BIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
63018. BIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
63019. BIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
63020. BIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
63021. BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
63022. BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
63023. BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
63024. BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
63025. BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
63026. BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
63027. BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
63028. BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
63029. BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
63030. BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
63031. BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
63032. BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
63033. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
63034. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
63035. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
63036. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
63037. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
63038. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
63039. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
63040. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
63041. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
63042. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
63043. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
63044. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
63045. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
63046. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
63047. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
63048. BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
63049. BIF_BX_DEV0_EPF0_VF20_MM_DATA__MM_DATA_MASK
63050. BIF_BX_DEV0_EPF0_VF20_MM_DATA__MM_DATA__SHIFT
63051. BIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI__MM_OFFSET_HI_MASK
63052. BIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
63053. BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_APER_MASK
63054. BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_APER__SHIFT
63055. BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_OFFSET_MASK
63056. BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_OFFSET__SHIFT
63057. BIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
63058. BIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
63059. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
63060. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
63061. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
63062. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
63063. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
63064. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
63065. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
63066. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
63067. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
63068. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
63069. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
63070. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
63071. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
63072. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
63073. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
63074. BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
63075. BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
63076. BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
63077. BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
63078. BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
63079. BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
63080. BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
63081. BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
63082. BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
63083. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
63084. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
63085. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
63086. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
63087. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
63088. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
63089. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
63090. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
63091. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
63092. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
63093. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
63094. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
63095. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
63096. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
63097. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
63098. BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
63099. BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
63100. BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
63101. BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
63102. BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
63103. BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
63104. BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
63105. BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
63106. BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
63107. BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
63108. BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
63109. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP0_MASK
63110. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP0__SHIFT
63111. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP1_MASK
63112. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP1__SHIFT
63113. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP2_MASK
63114. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP2__SHIFT
63115. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP3_MASK
63116. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP3__SHIFT
63117. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP4_MASK
63118. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP4__SHIFT
63119. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP5_MASK
63120. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP5__SHIFT
63121. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP6_MASK
63122. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP6__SHIFT
63123. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP7_MASK
63124. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP7__SHIFT
63125. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP8_MASK
63126. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP8__SHIFT
63127. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP9_MASK
63128. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP9__SHIFT
63129. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA0_MASK
63130. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
63131. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA1_MASK
63132. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
63133. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP0_MASK
63134. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP0__SHIFT
63135. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP1_MASK
63136. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP1__SHIFT
63137. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP2_MASK
63138. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP2__SHIFT
63139. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP3_MASK
63140. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP3__SHIFT
63141. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP4_MASK
63142. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP4__SHIFT
63143. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP5_MASK
63144. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP5__SHIFT
63145. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP6_MASK
63146. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP6__SHIFT
63147. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP7_MASK
63148. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP7__SHIFT
63149. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP8_MASK
63150. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP8__SHIFT
63151. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP9_MASK
63152. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP9__SHIFT
63153. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA0_MASK
63154. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
63155. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA1_MASK
63156. BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
63157. BIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
63158. BIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
63159. BIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
63160. BIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
63161. BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
63162. BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
63163. BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
63164. BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
63165. BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
63166. BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
63167. BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
63168. BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
63169. BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
63170. BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
63171. BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
63172. BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
63173. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
63174. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
63175. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
63176. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
63177. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
63178. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
63179. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
63180. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
63181. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
63182. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
63183. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
63184. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
63185. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
63186. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
63187. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
63188. BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
63189. BIF_BX_DEV0_EPF0_VF21_MM_DATA__MM_DATA_MASK
63190. BIF_BX_DEV0_EPF0_VF21_MM_DATA__MM_DATA__SHIFT
63191. BIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI__MM_OFFSET_HI_MASK
63192. BIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
63193. BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_APER_MASK
63194. BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_APER__SHIFT
63195. BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_OFFSET_MASK
63196. BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_OFFSET__SHIFT
63197. BIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
63198. BIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
63199. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
63200. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
63201. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
63202. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
63203. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
63204. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
63205. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
63206. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
63207. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
63208. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
63209. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
63210. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
63211. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
63212. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
63213. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
63214. BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
63215. BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
63216. BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
63217. BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
63218. BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
63219. BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
63220. BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
63221. BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
63222. BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
63223. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
63224. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
63225. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
63226. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
63227. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
63228. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
63229. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
63230. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
63231. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
63232. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
63233. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
63234. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
63235. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
63236. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
63237. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
63238. BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
63239. BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
63240. BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
63241. BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
63242. BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
63243. BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
63244. BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
63245. BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
63246. BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
63247. BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
63248. BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
63249. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP0_MASK
63250. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP0__SHIFT
63251. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP1_MASK
63252. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP1__SHIFT
63253. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP2_MASK
63254. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP2__SHIFT
63255. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP3_MASK
63256. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP3__SHIFT
63257. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP4_MASK
63258. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP4__SHIFT
63259. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP5_MASK
63260. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP5__SHIFT
63261. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP6_MASK
63262. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP6__SHIFT
63263. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP7_MASK
63264. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP7__SHIFT
63265. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP8_MASK
63266. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP8__SHIFT
63267. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP9_MASK
63268. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP9__SHIFT
63269. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA0_MASK
63270. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
63271. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA1_MASK
63272. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
63273. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP0_MASK
63274. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP0__SHIFT
63275. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP1_MASK
63276. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP1__SHIFT
63277. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP2_MASK
63278. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP2__SHIFT
63279. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP3_MASK
63280. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP3__SHIFT
63281. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP4_MASK
63282. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP4__SHIFT
63283. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP5_MASK
63284. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP5__SHIFT
63285. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP6_MASK
63286. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP6__SHIFT
63287. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP7_MASK
63288. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP7__SHIFT
63289. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP8_MASK
63290. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP8__SHIFT
63291. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP9_MASK
63292. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP9__SHIFT
63293. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA0_MASK
63294. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
63295. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA1_MASK
63296. BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
63297. BIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
63298. BIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
63299. BIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
63300. BIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
63301. BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
63302. BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
63303. BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
63304. BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
63305. BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
63306. BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
63307. BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
63308. BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
63309. BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
63310. BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
63311. BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
63312. BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
63313. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
63314. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
63315. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
63316. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
63317. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
63318. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
63319. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
63320. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
63321. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
63322. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
63323. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
63324. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
63325. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
63326. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
63327. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
63328. BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
63329. BIF_BX_DEV0_EPF0_VF22_MM_DATA__MM_DATA_MASK
63330. BIF_BX_DEV0_EPF0_VF22_MM_DATA__MM_DATA__SHIFT
63331. BIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI__MM_OFFSET_HI_MASK
63332. BIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
63333. BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_APER_MASK
63334. BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_APER__SHIFT
63335. BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_OFFSET_MASK
63336. BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_OFFSET__SHIFT
63337. BIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
63338. BIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
63339. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
63340. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
63341. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
63342. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
63343. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
63344. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
63345. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
63346. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
63347. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
63348. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
63349. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
63350. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
63351. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
63352. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
63353. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
63354. BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
63355. BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
63356. BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
63357. BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
63358. BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
63359. BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
63360. BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
63361. BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
63362. BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
63363. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
63364. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
63365. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
63366. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
63367. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
63368. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
63369. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
63370. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
63371. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
63372. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
63373. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
63374. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
63375. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
63376. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
63377. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
63378. BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
63379. BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
63380. BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
63381. BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
63382. BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
63383. BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
63384. BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
63385. BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
63386. BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
63387. BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
63388. BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
63389. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP0_MASK
63390. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP0__SHIFT
63391. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP1_MASK
63392. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP1__SHIFT
63393. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP2_MASK
63394. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP2__SHIFT
63395. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP3_MASK
63396. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP3__SHIFT
63397. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP4_MASK
63398. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP4__SHIFT
63399. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP5_MASK
63400. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP5__SHIFT
63401. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP6_MASK
63402. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP6__SHIFT
63403. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP7_MASK
63404. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP7__SHIFT
63405. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP8_MASK
63406. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP8__SHIFT
63407. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP9_MASK
63408. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP9__SHIFT
63409. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA0_MASK
63410. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
63411. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA1_MASK
63412. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
63413. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP0_MASK
63414. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP0__SHIFT
63415. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP1_MASK
63416. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP1__SHIFT
63417. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP2_MASK
63418. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP2__SHIFT
63419. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP3_MASK
63420. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP3__SHIFT
63421. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP4_MASK
63422. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP4__SHIFT
63423. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP5_MASK
63424. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP5__SHIFT
63425. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP6_MASK
63426. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP6__SHIFT
63427. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP7_MASK
63428. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP7__SHIFT
63429. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP8_MASK
63430. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP8__SHIFT
63431. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP9_MASK
63432. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP9__SHIFT
63433. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA0_MASK
63434. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
63435. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA1_MASK
63436. BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
63437. BIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
63438. BIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
63439. BIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
63440. BIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
63441. BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
63442. BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
63443. BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
63444. BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
63445. BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
63446. BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
63447. BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
63448. BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
63449. BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
63450. BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
63451. BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
63452. BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
63453. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
63454. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
63455. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
63456. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
63457. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
63458. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
63459. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
63460. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
63461. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
63462. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
63463. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
63464. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
63465. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
63466. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
63467. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
63468. BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
63469. BIF_BX_DEV0_EPF0_VF23_MM_DATA__MM_DATA_MASK
63470. BIF_BX_DEV0_EPF0_VF23_MM_DATA__MM_DATA__SHIFT
63471. BIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI__MM_OFFSET_HI_MASK
63472. BIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
63473. BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_APER_MASK
63474. BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_APER__SHIFT
63475. BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_OFFSET_MASK
63476. BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_OFFSET__SHIFT
63477. BIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
63478. BIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
63479. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
63480. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
63481. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
63482. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
63483. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
63484. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
63485. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
63486. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
63487. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
63488. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
63489. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
63490. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
63491. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
63492. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
63493. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
63494. BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
63495. BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
63496. BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
63497. BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
63498. BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
63499. BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
63500. BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
63501. BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
63502. BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
63503. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
63504. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
63505. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
63506. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
63507. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
63508. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
63509. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
63510. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
63511. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
63512. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
63513. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
63514. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
63515. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
63516. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
63517. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
63518. BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
63519. BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
63520. BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
63521. BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
63522. BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
63523. BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
63524. BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
63525. BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
63526. BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
63527. BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
63528. BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
63529. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP0_MASK
63530. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP0__SHIFT
63531. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP1_MASK
63532. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP1__SHIFT
63533. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP2_MASK
63534. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP2__SHIFT
63535. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP3_MASK
63536. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP3__SHIFT
63537. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP4_MASK
63538. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP4__SHIFT
63539. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP5_MASK
63540. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP5__SHIFT
63541. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP6_MASK
63542. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP6__SHIFT
63543. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP7_MASK
63544. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP7__SHIFT
63545. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP8_MASK
63546. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP8__SHIFT
63547. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP9_MASK
63548. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP9__SHIFT
63549. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__SDMA0_MASK
63550. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
63551. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__SDMA1_MASK
63552. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
63553. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP0_MASK
63554. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP0__SHIFT
63555. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP1_MASK
63556. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP1__SHIFT
63557. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP2_MASK
63558. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP2__SHIFT
63559. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP3_MASK
63560. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP3__SHIFT
63561. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP4_MASK
63562. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP4__SHIFT
63563. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP5_MASK
63564. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP5__SHIFT
63565. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP6_MASK
63566. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP6__SHIFT
63567. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP7_MASK
63568. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP7__SHIFT
63569. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP8_MASK
63570. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP8__SHIFT
63571. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP9_MASK
63572. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP9__SHIFT
63573. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__SDMA0_MASK
63574. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
63575. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__SDMA1_MASK
63576. BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
63577. BIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
63578. BIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
63579. BIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
63580. BIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
63581. BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
63582. BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
63583. BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
63584. BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
63585. BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
63586. BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
63587. BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
63588. BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
63589. BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
63590. BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
63591. BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
63592. BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
63593. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
63594. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
63595. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
63596. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
63597. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
63598. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
63599. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
63600. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
63601. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
63602. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
63603. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
63604. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
63605. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
63606. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
63607. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
63608. BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
63609. BIF_BX_DEV0_EPF0_VF24_MM_DATA__MM_DATA_MASK
63610. BIF_BX_DEV0_EPF0_VF24_MM_DATA__MM_DATA__SHIFT
63611. BIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI__MM_OFFSET_HI_MASK
63612. BIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
63613. BIF_BX_DEV0_EPF0_VF24_MM_INDEX__MM_APER_MASK
63614. BIF_BX_DEV0_EPF0_VF24_MM_INDEX__MM_APER__SHIFT
63615. BIF_BX_DEV0_EPF0_VF24_MM_INDEX__MM_OFFSET_MASK
63616. BIF_BX_DEV0_EPF0_VF24_MM_INDEX__MM_OFFSET__SHIFT
63617. BIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
63618. BIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
63619. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
63620. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
63621. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
63622. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
63623. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
63624. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
63625. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
63626. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
63627. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
63628. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
63629. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
63630. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
63631. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
63632. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
63633. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
63634. BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
63635. BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
63636. BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
63637. BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
63638. BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
63639. BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
63640. BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
63641. BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
63642. BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
63643. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
63644. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
63645. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
63646. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
63647. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
63648. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
63649. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
63650. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
63651. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
63652. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
63653. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
63654. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
63655. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
63656. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
63657. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
63658. BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
63659. BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
63660. BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
63661. BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
63662. BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
63663. BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
63664. BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
63665. BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
63666. BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
63667. BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
63668. BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
63669. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP0_MASK
63670. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP0__SHIFT
63671. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP1_MASK
63672. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP1__SHIFT
63673. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP2_MASK
63674. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP2__SHIFT
63675. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP3_MASK
63676. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP3__SHIFT
63677. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP4_MASK
63678. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP4__SHIFT
63679. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP5_MASK
63680. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP5__SHIFT
63681. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP6_MASK
63682. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP6__SHIFT
63683. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP7_MASK
63684. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP7__SHIFT
63685. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP8_MASK
63686. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP8__SHIFT
63687. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP9_MASK
63688. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP9__SHIFT
63689. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__SDMA0_MASK
63690. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
63691. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__SDMA1_MASK
63692. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
63693. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP0_MASK
63694. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP0__SHIFT
63695. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP1_MASK
63696. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP1__SHIFT
63697. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP2_MASK
63698. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP2__SHIFT
63699. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP3_MASK
63700. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP3__SHIFT
63701. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP4_MASK
63702. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP4__SHIFT
63703. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP5_MASK
63704. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP5__SHIFT
63705. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP6_MASK
63706. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP6__SHIFT
63707. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP7_MASK
63708. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP7__SHIFT
63709. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP8_MASK
63710. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP8__SHIFT
63711. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP9_MASK
63712. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP9__SHIFT
63713. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__SDMA0_MASK
63714. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
63715. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__SDMA1_MASK
63716. BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
63717. BIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
63718. BIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
63719. BIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
63720. BIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
63721. BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
63722. BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
63723. BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
63724. BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
63725. BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
63726. BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
63727. BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
63728. BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
63729. BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
63730. BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
63731. BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
63732. BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
63733. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
63734. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
63735. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
63736. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
63737. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
63738. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
63739. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
63740. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
63741. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
63742. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
63743. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
63744. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
63745. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
63746. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
63747. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
63748. BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
63749. BIF_BX_DEV0_EPF0_VF25_MM_DATA__MM_DATA_MASK
63750. BIF_BX_DEV0_EPF0_VF25_MM_DATA__MM_DATA__SHIFT
63751. BIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI__MM_OFFSET_HI_MASK
63752. BIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
63753. BIF_BX_DEV0_EPF0_VF25_MM_INDEX__MM_APER_MASK
63754. BIF_BX_DEV0_EPF0_VF25_MM_INDEX__MM_APER__SHIFT
63755. BIF_BX_DEV0_EPF0_VF25_MM_INDEX__MM_OFFSET_MASK
63756. BIF_BX_DEV0_EPF0_VF25_MM_INDEX__MM_OFFSET__SHIFT
63757. BIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
63758. BIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
63759. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
63760. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
63761. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
63762. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
63763. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
63764. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
63765. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
63766. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
63767. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
63768. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
63769. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
63770. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
63771. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
63772. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
63773. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
63774. BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
63775. BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
63776. BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
63777. BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
63778. BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
63779. BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
63780. BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
63781. BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
63782. BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
63783. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
63784. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
63785. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
63786. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
63787. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
63788. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
63789. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
63790. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
63791. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
63792. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
63793. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
63794. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
63795. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
63796. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
63797. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
63798. BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
63799. BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
63800. BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
63801. BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
63802. BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
63803. BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
63804. BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
63805. BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
63806. BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
63807. BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
63808. BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
63809. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP0_MASK
63810. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP0__SHIFT
63811. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP1_MASK
63812. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP1__SHIFT
63813. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP2_MASK
63814. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP2__SHIFT
63815. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP3_MASK
63816. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP3__SHIFT
63817. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP4_MASK
63818. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP4__SHIFT
63819. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP5_MASK
63820. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP5__SHIFT
63821. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP6_MASK
63822. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP6__SHIFT
63823. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP7_MASK
63824. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP7__SHIFT
63825. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP8_MASK
63826. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP8__SHIFT
63827. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP9_MASK
63828. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP9__SHIFT
63829. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__SDMA0_MASK
63830. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
63831. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__SDMA1_MASK
63832. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
63833. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP0_MASK
63834. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP0__SHIFT
63835. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP1_MASK
63836. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP1__SHIFT
63837. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP2_MASK
63838. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP2__SHIFT
63839. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP3_MASK
63840. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP3__SHIFT
63841. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP4_MASK
63842. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP4__SHIFT
63843. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP5_MASK
63844. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP5__SHIFT
63845. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP6_MASK
63846. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP6__SHIFT
63847. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP7_MASK
63848. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP7__SHIFT
63849. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP8_MASK
63850. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP8__SHIFT
63851. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP9_MASK
63852. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP9__SHIFT
63853. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__SDMA0_MASK
63854. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
63855. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__SDMA1_MASK
63856. BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
63857. BIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
63858. BIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
63859. BIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
63860. BIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
63861. BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
63862. BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
63863. BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
63864. BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
63865. BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
63866. BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
63867. BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
63868. BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
63869. BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
63870. BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
63871. BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
63872. BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
63873. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
63874. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
63875. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
63876. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
63877. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
63878. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
63879. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
63880. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
63881. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
63882. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
63883. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
63884. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
63885. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
63886. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
63887. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
63888. BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
63889. BIF_BX_DEV0_EPF0_VF26_MM_DATA__MM_DATA_MASK
63890. BIF_BX_DEV0_EPF0_VF26_MM_DATA__MM_DATA__SHIFT
63891. BIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI__MM_OFFSET_HI_MASK
63892. BIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
63893. BIF_BX_DEV0_EPF0_VF26_MM_INDEX__MM_APER_MASK
63894. BIF_BX_DEV0_EPF0_VF26_MM_INDEX__MM_APER__SHIFT
63895. BIF_BX_DEV0_EPF0_VF26_MM_INDEX__MM_OFFSET_MASK
63896. BIF_BX_DEV0_EPF0_VF26_MM_INDEX__MM_OFFSET__SHIFT
63897. BIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
63898. BIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
63899. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
63900. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
63901. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
63902. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
63903. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
63904. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
63905. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
63906. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
63907. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
63908. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
63909. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
63910. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
63911. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
63912. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
63913. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
63914. BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
63915. BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
63916. BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
63917. BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
63918. BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
63919. BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
63920. BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
63921. BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
63922. BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
63923. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
63924. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
63925. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
63926. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
63927. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
63928. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
63929. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
63930. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
63931. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
63932. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
63933. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
63934. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
63935. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
63936. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
63937. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
63938. BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
63939. BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
63940. BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
63941. BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
63942. BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
63943. BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
63944. BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
63945. BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
63946. BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
63947. BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
63948. BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
63949. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP0_MASK
63950. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP0__SHIFT
63951. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP1_MASK
63952. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP1__SHIFT
63953. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP2_MASK
63954. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP2__SHIFT
63955. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP3_MASK
63956. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP3__SHIFT
63957. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP4_MASK
63958. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP4__SHIFT
63959. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP5_MASK
63960. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP5__SHIFT
63961. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP6_MASK
63962. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP6__SHIFT
63963. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP7_MASK
63964. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP7__SHIFT
63965. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP8_MASK
63966. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP8__SHIFT
63967. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP9_MASK
63968. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP9__SHIFT
63969. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__SDMA0_MASK
63970. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
63971. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__SDMA1_MASK
63972. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
63973. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP0_MASK
63974. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP0__SHIFT
63975. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP1_MASK
63976. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP1__SHIFT
63977. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP2_MASK
63978. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP2__SHIFT
63979. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP3_MASK
63980. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP3__SHIFT
63981. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP4_MASK
63982. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP4__SHIFT
63983. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP5_MASK
63984. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP5__SHIFT
63985. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP6_MASK
63986. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP6__SHIFT
63987. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP7_MASK
63988. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP7__SHIFT
63989. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP8_MASK
63990. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP8__SHIFT
63991. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP9_MASK
63992. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP9__SHIFT
63993. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__SDMA0_MASK
63994. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
63995. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__SDMA1_MASK
63996. BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
63997. BIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
63998. BIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
63999. BIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
64000. BIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
64001. BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
64002. BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
64003. BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
64004. BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
64005. BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
64006. BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
64007. BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
64008. BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
64009. BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
64010. BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
64011. BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
64012. BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
64013. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
64014. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
64015. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
64016. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
64017. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
64018. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
64019. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
64020. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
64021. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
64022. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
64023. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
64024. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
64025. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
64026. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
64027. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
64028. BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
64029. BIF_BX_DEV0_EPF0_VF27_MM_DATA__MM_DATA_MASK
64030. BIF_BX_DEV0_EPF0_VF27_MM_DATA__MM_DATA__SHIFT
64031. BIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI__MM_OFFSET_HI_MASK
64032. BIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
64033. BIF_BX_DEV0_EPF0_VF27_MM_INDEX__MM_APER_MASK
64034. BIF_BX_DEV0_EPF0_VF27_MM_INDEX__MM_APER__SHIFT
64035. BIF_BX_DEV0_EPF0_VF27_MM_INDEX__MM_OFFSET_MASK
64036. BIF_BX_DEV0_EPF0_VF27_MM_INDEX__MM_OFFSET__SHIFT
64037. BIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
64038. BIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
64039. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
64040. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
64041. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
64042. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
64043. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
64044. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
64045. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
64046. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
64047. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
64048. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
64049. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
64050. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
64051. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
64052. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
64053. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
64054. BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
64055. BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
64056. BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
64057. BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
64058. BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
64059. BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
64060. BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
64061. BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
64062. BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
64063. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
64064. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
64065. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
64066. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
64067. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
64068. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
64069. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
64070. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
64071. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
64072. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
64073. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
64074. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
64075. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
64076. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
64077. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
64078. BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
64079. BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
64080. BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
64081. BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
64082. BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
64083. BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
64084. BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
64085. BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
64086. BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
64087. BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
64088. BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
64089. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP0_MASK
64090. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP0__SHIFT
64091. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP1_MASK
64092. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP1__SHIFT
64093. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP2_MASK
64094. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP2__SHIFT
64095. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP3_MASK
64096. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP3__SHIFT
64097. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP4_MASK
64098. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP4__SHIFT
64099. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP5_MASK
64100. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP5__SHIFT
64101. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP6_MASK
64102. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP6__SHIFT
64103. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP7_MASK
64104. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP7__SHIFT
64105. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP8_MASK
64106. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP8__SHIFT
64107. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP9_MASK
64108. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP9__SHIFT
64109. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__SDMA0_MASK
64110. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
64111. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__SDMA1_MASK
64112. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
64113. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP0_MASK
64114. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP0__SHIFT
64115. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP1_MASK
64116. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP1__SHIFT
64117. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP2_MASK
64118. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP2__SHIFT
64119. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP3_MASK
64120. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP3__SHIFT
64121. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP4_MASK
64122. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP4__SHIFT
64123. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP5_MASK
64124. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP5__SHIFT
64125. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP6_MASK
64126. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP6__SHIFT
64127. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP7_MASK
64128. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP7__SHIFT
64129. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP8_MASK
64130. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP8__SHIFT
64131. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP9_MASK
64132. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP9__SHIFT
64133. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__SDMA0_MASK
64134. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
64135. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__SDMA1_MASK
64136. BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
64137. BIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
64138. BIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
64139. BIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
64140. BIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
64141. BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
64142. BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
64143. BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
64144. BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
64145. BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
64146. BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
64147. BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
64148. BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
64149. BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
64150. BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
64151. BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
64152. BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
64153. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
64154. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
64155. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
64156. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
64157. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
64158. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
64159. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
64160. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
64161. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
64162. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
64163. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
64164. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
64165. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
64166. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
64167. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
64168. BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
64169. BIF_BX_DEV0_EPF0_VF28_MM_DATA__MM_DATA_MASK
64170. BIF_BX_DEV0_EPF0_VF28_MM_DATA__MM_DATA__SHIFT
64171. BIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI__MM_OFFSET_HI_MASK
64172. BIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
64173. BIF_BX_DEV0_EPF0_VF28_MM_INDEX__MM_APER_MASK
64174. BIF_BX_DEV0_EPF0_VF28_MM_INDEX__MM_APER__SHIFT
64175. BIF_BX_DEV0_EPF0_VF28_MM_INDEX__MM_OFFSET_MASK
64176. BIF_BX_DEV0_EPF0_VF28_MM_INDEX__MM_OFFSET__SHIFT
64177. BIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
64178. BIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
64179. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
64180. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
64181. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
64182. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
64183. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
64184. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
64185. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
64186. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
64187. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
64188. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
64189. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
64190. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
64191. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
64192. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
64193. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
64194. BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
64195. BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
64196. BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
64197. BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
64198. BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
64199. BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
64200. BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
64201. BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
64202. BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
64203. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
64204. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
64205. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
64206. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
64207. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
64208. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
64209. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
64210. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
64211. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
64212. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
64213. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
64214. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
64215. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
64216. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
64217. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
64218. BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
64219. BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
64220. BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
64221. BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
64222. BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
64223. BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
64224. BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
64225. BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
64226. BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
64227. BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
64228. BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
64229. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP0_MASK
64230. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP0__SHIFT
64231. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP1_MASK
64232. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP1__SHIFT
64233. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP2_MASK
64234. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP2__SHIFT
64235. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP3_MASK
64236. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP3__SHIFT
64237. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP4_MASK
64238. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP4__SHIFT
64239. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP5_MASK
64240. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP5__SHIFT
64241. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP6_MASK
64242. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP6__SHIFT
64243. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP7_MASK
64244. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP7__SHIFT
64245. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP8_MASK
64246. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP8__SHIFT
64247. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP9_MASK
64248. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP9__SHIFT
64249. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__SDMA0_MASK
64250. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
64251. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__SDMA1_MASK
64252. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
64253. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP0_MASK
64254. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP0__SHIFT
64255. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP1_MASK
64256. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP1__SHIFT
64257. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP2_MASK
64258. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP2__SHIFT
64259. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP3_MASK
64260. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP3__SHIFT
64261. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP4_MASK
64262. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP4__SHIFT
64263. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP5_MASK
64264. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP5__SHIFT
64265. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP6_MASK
64266. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP6__SHIFT
64267. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP7_MASK
64268. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP7__SHIFT
64269. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP8_MASK
64270. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP8__SHIFT
64271. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP9_MASK
64272. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP9__SHIFT
64273. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__SDMA0_MASK
64274. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
64275. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__SDMA1_MASK
64276. BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
64277. BIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
64278. BIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
64279. BIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
64280. BIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
64281. BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
64282. BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
64283. BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
64284. BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
64285. BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
64286. BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
64287. BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
64288. BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
64289. BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
64290. BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
64291. BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
64292. BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
64293. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
64294. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
64295. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
64296. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
64297. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
64298. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
64299. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
64300. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
64301. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
64302. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
64303. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
64304. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
64305. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
64306. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
64307. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
64308. BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
64309. BIF_BX_DEV0_EPF0_VF29_MM_DATA__MM_DATA_MASK
64310. BIF_BX_DEV0_EPF0_VF29_MM_DATA__MM_DATA__SHIFT
64311. BIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI__MM_OFFSET_HI_MASK
64312. BIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
64313. BIF_BX_DEV0_EPF0_VF29_MM_INDEX__MM_APER_MASK
64314. BIF_BX_DEV0_EPF0_VF29_MM_INDEX__MM_APER__SHIFT
64315. BIF_BX_DEV0_EPF0_VF29_MM_INDEX__MM_OFFSET_MASK
64316. BIF_BX_DEV0_EPF0_VF29_MM_INDEX__MM_OFFSET__SHIFT
64317. BIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
64318. BIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
64319. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
64320. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
64321. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
64322. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
64323. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
64324. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
64325. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
64326. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
64327. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
64328. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
64329. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
64330. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
64331. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
64332. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
64333. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
64334. BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
64335. BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
64336. BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
64337. BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
64338. BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
64339. BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
64340. BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
64341. BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
64342. BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
64343. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
64344. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
64345. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
64346. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
64347. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
64348. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
64349. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
64350. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
64351. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
64352. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
64353. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
64354. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
64355. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
64356. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
64357. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
64358. BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
64359. BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
64360. BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
64361. BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
64362. BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
64363. BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
64364. BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
64365. BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
64366. BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
64367. BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
64368. BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
64369. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0_MASK
64370. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT
64371. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1_MASK
64372. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT
64373. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2_MASK
64374. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT
64375. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3_MASK
64376. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT
64377. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4_MASK
64378. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT
64379. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5_MASK
64380. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT
64381. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6_MASK
64382. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT
64383. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7_MASK
64384. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT
64385. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8_MASK
64386. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT
64387. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9_MASK
64388. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT
64389. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK
64390. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
64391. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK
64392. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
64393. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0_MASK
64394. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT
64395. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1_MASK
64396. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT
64397. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2_MASK
64398. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT
64399. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3_MASK
64400. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT
64401. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4_MASK
64402. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT
64403. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5_MASK
64404. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT
64405. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6_MASK
64406. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT
64407. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7_MASK
64408. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT
64409. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8_MASK
64410. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT
64411. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9_MASK
64412. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT
64413. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK
64414. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
64415. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK
64416. BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
64417. BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
64418. BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
64419. BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
64420. BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
64421. BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
64422. BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
64423. BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
64424. BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
64425. BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
64426. BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
64427. BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
64428. BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
64429. BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
64430. BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
64431. BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
64432. BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
64433. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
64434. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
64435. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
64436. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
64437. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
64438. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
64439. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
64440. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
64441. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
64442. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
64443. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
64444. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
64445. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
64446. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
64447. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
64448. BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
64449. BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA_MASK
64450. BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA__SHIFT
64451. BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI_MASK
64452. BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
64453. BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER_MASK
64454. BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER__SHIFT
64455. BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET_MASK
64456. BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET__SHIFT
64457. BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
64458. BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
64459. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
64460. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
64461. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
64462. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
64463. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
64464. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
64465. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
64466. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
64467. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
64468. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
64469. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
64470. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
64471. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
64472. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
64473. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
64474. BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
64475. BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
64476. BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
64477. BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
64478. BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
64479. BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
64480. BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
64481. BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
64482. BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
64483. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
64484. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
64485. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
64486. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
64487. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
64488. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
64489. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
64490. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
64491. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
64492. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
64493. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
64494. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
64495. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
64496. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
64497. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
64498. BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
64499. BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
64500. BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
64501. BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
64502. BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
64503. BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
64504. BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
64505. BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
64506. BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
64507. BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
64508. BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
64509. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP0_MASK
64510. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP0__SHIFT
64511. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP1_MASK
64512. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP1__SHIFT
64513. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP2_MASK
64514. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP2__SHIFT
64515. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP3_MASK
64516. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP3__SHIFT
64517. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP4_MASK
64518. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP4__SHIFT
64519. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP5_MASK
64520. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP5__SHIFT
64521. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP6_MASK
64522. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP6__SHIFT
64523. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP7_MASK
64524. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP7__SHIFT
64525. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP8_MASK
64526. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP8__SHIFT
64527. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP9_MASK
64528. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP9__SHIFT
64529. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__SDMA0_MASK
64530. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
64531. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__SDMA1_MASK
64532. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
64533. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP0_MASK
64534. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP0__SHIFT
64535. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP1_MASK
64536. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP1__SHIFT
64537. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP2_MASK
64538. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP2__SHIFT
64539. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP3_MASK
64540. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP3__SHIFT
64541. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP4_MASK
64542. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP4__SHIFT
64543. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP5_MASK
64544. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP5__SHIFT
64545. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP6_MASK
64546. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP6__SHIFT
64547. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP7_MASK
64548. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP7__SHIFT
64549. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP8_MASK
64550. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP8__SHIFT
64551. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP9_MASK
64552. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP9__SHIFT
64553. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__SDMA0_MASK
64554. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
64555. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__SDMA1_MASK
64556. BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
64557. BIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
64558. BIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
64559. BIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
64560. BIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
64561. BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
64562. BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
64563. BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
64564. BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
64565. BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
64566. BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
64567. BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
64568. BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
64569. BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
64570. BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
64571. BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
64572. BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
64573. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
64574. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
64575. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
64576. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
64577. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
64578. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
64579. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
64580. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
64581. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
64582. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
64583. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
64584. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
64585. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
64586. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
64587. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
64588. BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
64589. BIF_BX_DEV0_EPF0_VF30_MM_DATA__MM_DATA_MASK
64590. BIF_BX_DEV0_EPF0_VF30_MM_DATA__MM_DATA__SHIFT
64591. BIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI__MM_OFFSET_HI_MASK
64592. BIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
64593. BIF_BX_DEV0_EPF0_VF30_MM_INDEX__MM_APER_MASK
64594. BIF_BX_DEV0_EPF0_VF30_MM_INDEX__MM_APER__SHIFT
64595. BIF_BX_DEV0_EPF0_VF30_MM_INDEX__MM_OFFSET_MASK
64596. BIF_BX_DEV0_EPF0_VF30_MM_INDEX__MM_OFFSET__SHIFT
64597. BIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
64598. BIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
64599. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
64600. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
64601. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
64602. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
64603. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
64604. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
64605. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
64606. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
64607. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
64608. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
64609. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
64610. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
64611. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
64612. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
64613. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
64614. BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
64615. BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
64616. BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
64617. BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
64618. BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
64619. BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
64620. BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
64621. BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
64622. BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
64623. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
64624. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
64625. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
64626. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
64627. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
64628. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
64629. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
64630. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
64631. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
64632. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
64633. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
64634. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
64635. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
64636. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
64637. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
64638. BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
64639. BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
64640. BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
64641. BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
64642. BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
64643. BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
64644. BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
64645. BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
64646. BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
64647. BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
64648. BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
64649. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0_MASK
64650. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0__SHIFT
64651. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1_MASK
64652. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1__SHIFT
64653. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2_MASK
64654. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2__SHIFT
64655. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3_MASK
64656. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3__SHIFT
64657. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4_MASK
64658. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4__SHIFT
64659. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5_MASK
64660. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5__SHIFT
64661. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6_MASK
64662. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6__SHIFT
64663. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7_MASK
64664. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7__SHIFT
64665. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8_MASK
64666. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8__SHIFT
64667. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9_MASK
64668. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9__SHIFT
64669. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0_MASK
64670. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
64671. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1_MASK
64672. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
64673. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0_MASK
64674. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0__SHIFT
64675. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1_MASK
64676. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1__SHIFT
64677. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2_MASK
64678. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2__SHIFT
64679. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3_MASK
64680. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3__SHIFT
64681. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4_MASK
64682. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4__SHIFT
64683. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5_MASK
64684. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5__SHIFT
64685. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6_MASK
64686. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6__SHIFT
64687. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7_MASK
64688. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7__SHIFT
64689. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8_MASK
64690. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8__SHIFT
64691. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9_MASK
64692. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9__SHIFT
64693. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0_MASK
64694. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
64695. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1_MASK
64696. BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
64697. BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
64698. BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
64699. BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
64700. BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
64701. BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
64702. BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
64703. BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
64704. BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
64705. BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
64706. BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
64707. BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
64708. BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
64709. BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
64710. BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
64711. BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
64712. BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
64713. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
64714. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
64715. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
64716. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
64717. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
64718. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
64719. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
64720. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
64721. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
64722. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
64723. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
64724. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
64725. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
64726. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
64727. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
64728. BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
64729. BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA_MASK
64730. BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA__SHIFT
64731. BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI_MASK
64732. BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
64733. BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER_MASK
64734. BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER__SHIFT
64735. BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET_MASK
64736. BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET__SHIFT
64737. BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
64738. BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
64739. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
64740. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
64741. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
64742. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
64743. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
64744. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
64745. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
64746. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
64747. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
64748. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
64749. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
64750. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
64751. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
64752. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
64753. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
64754. BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
64755. BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
64756. BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
64757. BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
64758. BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
64759. BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
64760. BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
64761. BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
64762. BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
64763. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
64764. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
64765. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
64766. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
64767. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
64768. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
64769. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
64770. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
64771. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
64772. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
64773. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
64774. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
64775. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
64776. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
64777. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
64778. BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
64779. BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
64780. BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
64781. BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
64782. BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
64783. BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
64784. BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
64785. BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
64786. BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
64787. BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
64788. BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
64789. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0_MASK
64790. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0__SHIFT
64791. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1_MASK
64792. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1__SHIFT
64793. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2_MASK
64794. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2__SHIFT
64795. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3_MASK
64796. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3__SHIFT
64797. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4_MASK
64798. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4__SHIFT
64799. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5_MASK
64800. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5__SHIFT
64801. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6_MASK
64802. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6__SHIFT
64803. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7_MASK
64804. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7__SHIFT
64805. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8_MASK
64806. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8__SHIFT
64807. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9_MASK
64808. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9__SHIFT
64809. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0_MASK
64810. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
64811. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1_MASK
64812. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
64813. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0_MASK
64814. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0__SHIFT
64815. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1_MASK
64816. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1__SHIFT
64817. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2_MASK
64818. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2__SHIFT
64819. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3_MASK
64820. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3__SHIFT
64821. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4_MASK
64822. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4__SHIFT
64823. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5_MASK
64824. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5__SHIFT
64825. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6_MASK
64826. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6__SHIFT
64827. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7_MASK
64828. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7__SHIFT
64829. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8_MASK
64830. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8__SHIFT
64831. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9_MASK
64832. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9__SHIFT
64833. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0_MASK
64834. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
64835. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1_MASK
64836. BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
64837. BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
64838. BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
64839. BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
64840. BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
64841. BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
64842. BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
64843. BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
64844. BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
64845. BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
64846. BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
64847. BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
64848. BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
64849. BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
64850. BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
64851. BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
64852. BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
64853. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
64854. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
64855. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
64856. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
64857. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
64858. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
64859. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
64860. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
64861. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
64862. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
64863. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
64864. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
64865. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
64866. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
64867. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
64868. BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
64869. BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA_MASK
64870. BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA__SHIFT
64871. BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI_MASK
64872. BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
64873. BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER_MASK
64874. BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER__SHIFT
64875. BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET_MASK
64876. BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET__SHIFT
64877. BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
64878. BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
64879. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
64880. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
64881. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
64882. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
64883. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
64884. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
64885. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
64886. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
64887. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
64888. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
64889. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
64890. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
64891. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
64892. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
64893. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
64894. BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
64895. BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
64896. BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
64897. BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
64898. BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
64899. BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
64900. BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
64901. BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
64902. BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
64903. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
64904. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
64905. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
64906. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
64907. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
64908. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
64909. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
64910. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
64911. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
64912. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
64913. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
64914. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
64915. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
64916. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
64917. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
64918. BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
64919. BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
64920. BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
64921. BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
64922. BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
64923. BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
64924. BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
64925. BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
64926. BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
64927. BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
64928. BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
64929. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0_MASK
64930. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0__SHIFT
64931. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1_MASK
64932. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1__SHIFT
64933. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2_MASK
64934. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2__SHIFT
64935. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3_MASK
64936. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3__SHIFT
64937. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4_MASK
64938. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4__SHIFT
64939. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5_MASK
64940. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5__SHIFT
64941. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6_MASK
64942. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6__SHIFT
64943. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7_MASK
64944. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7__SHIFT
64945. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8_MASK
64946. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8__SHIFT
64947. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9_MASK
64948. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9__SHIFT
64949. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0_MASK
64950. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
64951. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1_MASK
64952. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
64953. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0_MASK
64954. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0__SHIFT
64955. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1_MASK
64956. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1__SHIFT
64957. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2_MASK
64958. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2__SHIFT
64959. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3_MASK
64960. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3__SHIFT
64961. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4_MASK
64962. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4__SHIFT
64963. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5_MASK
64964. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5__SHIFT
64965. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6_MASK
64966. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6__SHIFT
64967. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7_MASK
64968. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7__SHIFT
64969. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8_MASK
64970. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8__SHIFT
64971. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9_MASK
64972. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9__SHIFT
64973. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0_MASK
64974. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
64975. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1_MASK
64976. BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
64977. BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
64978. BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
64979. BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
64980. BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
64981. BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
64982. BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
64983. BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
64984. BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
64985. BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
64986. BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
64987. BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
64988. BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
64989. BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
64990. BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
64991. BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
64992. BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
64993. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
64994. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
64995. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
64996. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
64997. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
64998. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
64999. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
65000. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
65001. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
65002. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
65003. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
65004. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
65005. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
65006. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
65007. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
65008. BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
65009. BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA_MASK
65010. BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA__SHIFT
65011. BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI_MASK
65012. BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
65013. BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER_MASK
65014. BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER__SHIFT
65015. BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET_MASK
65016. BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET__SHIFT
65017. BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
65018. BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
65019. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
65020. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
65021. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
65022. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
65023. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
65024. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
65025. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
65026. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
65027. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
65028. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
65029. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
65030. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
65031. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
65032. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
65033. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
65034. BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
65035. BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
65036. BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
65037. BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
65038. BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
65039. BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
65040. BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
65041. BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
65042. BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
65043. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
65044. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
65045. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
65046. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
65047. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
65048. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
65049. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
65050. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
65051. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
65052. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
65053. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
65054. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
65055. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
65056. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
65057. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
65058. BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
65059. BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
65060. BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
65061. BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
65062. BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
65063. BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
65064. BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
65065. BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
65066. BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
65067. BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
65068. BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
65069. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0_MASK
65070. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0__SHIFT
65071. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1_MASK
65072. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1__SHIFT
65073. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2_MASK
65074. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2__SHIFT
65075. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3_MASK
65076. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3__SHIFT
65077. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4_MASK
65078. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4__SHIFT
65079. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5_MASK
65080. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5__SHIFT
65081. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6_MASK
65082. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6__SHIFT
65083. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7_MASK
65084. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7__SHIFT
65085. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8_MASK
65086. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8__SHIFT
65087. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9_MASK
65088. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9__SHIFT
65089. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0_MASK
65090. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
65091. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1_MASK
65092. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
65093. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0_MASK
65094. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0__SHIFT
65095. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1_MASK
65096. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1__SHIFT
65097. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2_MASK
65098. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2__SHIFT
65099. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3_MASK
65100. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3__SHIFT
65101. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4_MASK
65102. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4__SHIFT
65103. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5_MASK
65104. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5__SHIFT
65105. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6_MASK
65106. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6__SHIFT
65107. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7_MASK
65108. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7__SHIFT
65109. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8_MASK
65110. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8__SHIFT
65111. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9_MASK
65112. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9__SHIFT
65113. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0_MASK
65114. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
65115. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1_MASK
65116. BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
65117. BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
65118. BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
65119. BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
65120. BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
65121. BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
65122. BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
65123. BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
65124. BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
65125. BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
65126. BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
65127. BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
65128. BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
65129. BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
65130. BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
65131. BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
65132. BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
65133. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
65134. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
65135. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
65136. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
65137. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
65138. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
65139. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
65140. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
65141. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
65142. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
65143. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
65144. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
65145. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
65146. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
65147. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
65148. BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
65149. BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA_MASK
65150. BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA__SHIFT
65151. BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI_MASK
65152. BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
65153. BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER_MASK
65154. BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER__SHIFT
65155. BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET_MASK
65156. BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET__SHIFT
65157. BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
65158. BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
65159. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
65160. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
65161. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
65162. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
65163. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
65164. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
65165. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
65166. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
65167. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
65168. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
65169. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
65170. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
65171. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
65172. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
65173. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
65174. BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
65175. BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
65176. BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
65177. BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
65178. BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
65179. BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
65180. BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
65181. BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
65182. BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
65183. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
65184. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
65185. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
65186. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
65187. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
65188. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
65189. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
65190. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
65191. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
65192. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
65193. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
65194. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
65195. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
65196. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
65197. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
65198. BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
65199. BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
65200. BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
65201. BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
65202. BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
65203. BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
65204. BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
65205. BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
65206. BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
65207. BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
65208. BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
65209. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0_MASK
65210. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0__SHIFT
65211. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1_MASK
65212. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1__SHIFT
65213. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2_MASK
65214. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2__SHIFT
65215. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3_MASK
65216. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3__SHIFT
65217. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4_MASK
65218. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4__SHIFT
65219. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5_MASK
65220. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5__SHIFT
65221. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6_MASK
65222. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6__SHIFT
65223. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7_MASK
65224. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7__SHIFT
65225. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8_MASK
65226. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8__SHIFT
65227. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9_MASK
65228. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9__SHIFT
65229. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0_MASK
65230. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
65231. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1_MASK
65232. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
65233. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0_MASK
65234. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0__SHIFT
65235. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1_MASK
65236. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1__SHIFT
65237. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2_MASK
65238. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2__SHIFT
65239. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3_MASK
65240. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3__SHIFT
65241. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4_MASK
65242. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4__SHIFT
65243. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5_MASK
65244. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5__SHIFT
65245. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6_MASK
65246. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6__SHIFT
65247. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7_MASK
65248. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7__SHIFT
65249. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8_MASK
65250. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8__SHIFT
65251. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9_MASK
65252. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9__SHIFT
65253. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0_MASK
65254. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
65255. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1_MASK
65256. BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
65257. BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
65258. BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
65259. BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
65260. BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
65261. BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
65262. BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
65263. BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
65264. BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
65265. BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
65266. BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
65267. BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
65268. BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
65269. BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
65270. BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
65271. BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
65272. BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
65273. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
65274. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
65275. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
65276. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
65277. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
65278. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
65279. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
65280. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
65281. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
65282. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
65283. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
65284. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
65285. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
65286. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
65287. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
65288. BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
65289. BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA_MASK
65290. BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA__SHIFT
65291. BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI_MASK
65292. BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
65293. BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER_MASK
65294. BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER__SHIFT
65295. BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET_MASK
65296. BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET__SHIFT
65297. BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
65298. BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
65299. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
65300. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
65301. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
65302. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
65303. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
65304. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
65305. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
65306. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
65307. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
65308. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
65309. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
65310. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
65311. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
65312. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
65313. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
65314. BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
65315. BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
65316. BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
65317. BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
65318. BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
65319. BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
65320. BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
65321. BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
65322. BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
65323. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
65324. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
65325. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
65326. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
65327. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
65328. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
65329. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
65330. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
65331. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
65332. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
65333. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
65334. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
65335. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
65336. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
65337. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
65338. BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
65339. BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
65340. BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
65341. BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
65342. BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
65343. BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
65344. BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
65345. BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
65346. BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
65347. BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
65348. BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
65349. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0_MASK
65350. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0__SHIFT
65351. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1_MASK
65352. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1__SHIFT
65353. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2_MASK
65354. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2__SHIFT
65355. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3_MASK
65356. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3__SHIFT
65357. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4_MASK
65358. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4__SHIFT
65359. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5_MASK
65360. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5__SHIFT
65361. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6_MASK
65362. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6__SHIFT
65363. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7_MASK
65364. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7__SHIFT
65365. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8_MASK
65366. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8__SHIFT
65367. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9_MASK
65368. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9__SHIFT
65369. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0_MASK
65370. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
65371. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1_MASK
65372. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
65373. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0_MASK
65374. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0__SHIFT
65375. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1_MASK
65376. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1__SHIFT
65377. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2_MASK
65378. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2__SHIFT
65379. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3_MASK
65380. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3__SHIFT
65381. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4_MASK
65382. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4__SHIFT
65383. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5_MASK
65384. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5__SHIFT
65385. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6_MASK
65386. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6__SHIFT
65387. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7_MASK
65388. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7__SHIFT
65389. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8_MASK
65390. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8__SHIFT
65391. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9_MASK
65392. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9__SHIFT
65393. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0_MASK
65394. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
65395. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1_MASK
65396. BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
65397. BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
65398. BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
65399. BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
65400. BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
65401. BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
65402. BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
65403. BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
65404. BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
65405. BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
65406. BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
65407. BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
65408. BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
65409. BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
65410. BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
65411. BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
65412. BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
65413. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
65414. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
65415. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
65416. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
65417. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
65418. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
65419. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
65420. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
65421. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
65422. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
65423. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
65424. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
65425. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
65426. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
65427. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
65428. BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
65429. BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA_MASK
65430. BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA__SHIFT
65431. BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI_MASK
65432. BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
65433. BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER_MASK
65434. BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER__SHIFT
65435. BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET_MASK
65436. BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET__SHIFT
65437. BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
65438. BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
65439. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
65440. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
65441. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
65442. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
65443. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
65444. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
65445. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
65446. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
65447. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
65448. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
65449. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
65450. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
65451. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
65452. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
65453. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
65454. BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
65455. BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
65456. BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
65457. BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
65458. BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
65459. BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
65460. BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
65461. BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
65462. BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
65463. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
65464. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
65465. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
65466. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
65467. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
65468. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
65469. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
65470. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
65471. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
65472. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
65473. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
65474. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
65475. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
65476. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
65477. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
65478. BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
65479. BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
65480. BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
65481. BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
65482. BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
65483. BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
65484. BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
65485. BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
65486. BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
65487. BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
65488. BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
65489. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0_MASK
65490. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0__SHIFT
65491. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1_MASK
65492. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1__SHIFT
65493. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2_MASK
65494. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2__SHIFT
65495. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3_MASK
65496. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3__SHIFT
65497. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4_MASK
65498. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4__SHIFT
65499. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5_MASK
65500. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5__SHIFT
65501. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6_MASK
65502. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6__SHIFT
65503. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7_MASK
65504. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7__SHIFT
65505. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8_MASK
65506. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8__SHIFT
65507. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9_MASK
65508. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9__SHIFT
65509. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0_MASK
65510. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
65511. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1_MASK
65512. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
65513. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0_MASK
65514. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0__SHIFT
65515. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1_MASK
65516. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1__SHIFT
65517. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2_MASK
65518. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2__SHIFT
65519. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3_MASK
65520. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3__SHIFT
65521. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4_MASK
65522. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4__SHIFT
65523. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5_MASK
65524. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5__SHIFT
65525. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6_MASK
65526. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6__SHIFT
65527. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7_MASK
65528. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7__SHIFT
65529. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8_MASK
65530. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8__SHIFT
65531. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9_MASK
65532. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9__SHIFT
65533. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0_MASK
65534. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
65535. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1_MASK
65536. BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
65537. BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
65538. BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
65539. BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
65540. BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
65541. BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
65542. BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
65543. BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
65544. BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
65545. BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
65546. BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
65547. BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
65548. BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
65549. BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
65550. BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
65551. BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
65552. BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
65553. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
65554. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
65555. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
65556. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
65557. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
65558. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
65559. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
65560. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
65561. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
65562. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
65563. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
65564. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
65565. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
65566. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
65567. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
65568. BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
65569. BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA_MASK
65570. BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA__SHIFT
65571. BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI_MASK
65572. BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
65573. BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER_MASK
65574. BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER__SHIFT
65575. BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET_MASK
65576. BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET__SHIFT
65577. BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
65578. BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
65579. BIF_BX_PF0_BACO_CNTL__BACO_AUTO_EXIT_MASK
65580. BIF_BX_PF0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT
65581. BIF_BX_PF0_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK
65582. BIF_BX_PF0_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT
65583. BIF_BX_PF0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK
65584. BIF_BX_PF0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT
65585. BIF_BX_PF0_BACO_CNTL__BACO_DUMMY_EN_MASK
65586. BIF_BX_PF0_BACO_CNTL__BACO_DUMMY_EN__SHIFT
65587. BIF_BX_PF0_BACO_CNTL__BACO_EN_MASK
65588. BIF_BX_PF0_BACO_CNTL__BACO_EN__SHIFT
65589. BIF_BX_PF0_BACO_CNTL__BACO_MODE_MASK
65590. BIF_BX_PF0_BACO_CNTL__BACO_MODE__SHIFT
65591. BIF_BX_PF0_BACO_CNTL__BACO_POWER_OFF_MASK
65592. BIF_BX_PF0_BACO_CNTL__BACO_POWER_OFF__SHIFT
65593. BIF_BX_PF0_BACO_CNTL__BACO_RST_INTR_MASK_MASK
65594. BIF_BX_PF0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT
65595. BIF_BX_PF0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK
65596. BIF_BX_PF0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT
65597. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
65598. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
65599. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
65600. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
65601. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
65602. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
65603. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
65604. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
65605. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
65606. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
65607. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
65608. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
65609. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
65610. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
65611. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
65612. BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
65613. BIF_BX_PF0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK
65614. BIF_BX_PF0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT
65615. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK
65616. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT
65617. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK
65618. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT
65619. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK
65620. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT
65621. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK
65622. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT
65623. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK
65624. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT
65625. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK
65626. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT
65627. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK
65628. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT
65629. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK
65630. BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT
65631. BIF_BX_PF0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK
65632. BIF_BX_PF0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT
65633. BIF_BX_PF0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK
65634. BIF_BX_PF0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT
65635. BIF_BX_PF0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK
65636. BIF_BX_PF0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT
65637. BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
65638. BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
65639. BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
65640. BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
65641. BIF_BX_PF0_BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK
65642. BIF_BX_PF0_BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT
65643. BIF_BX_PF0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK
65644. BIF_BX_PF0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT
65645. BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK
65646. BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT
65647. BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK
65648. BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT
65649. BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK
65650. BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT
65651. BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK
65652. BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT
65653. BIF_BX_PF0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK
65654. BIF_BX_PF0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT
65655. BIF_BX_PF0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK
65656. BIF_BX_PF0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT
65657. BIF_BX_PF0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK
65658. BIF_BX_PF0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT
65659. BIF_BX_PF0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK
65660. BIF_BX_PF0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT
65661. BIF_BX_PF0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK
65662. BIF_BX_PF0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT
65663. BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK
65664. BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT
65665. BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK
65666. BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT
65667. BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK
65668. BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT
65669. BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK
65670. BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT
65671. BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK
65672. BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT
65673. BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK
65674. BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT
65675. BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK
65676. BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT
65677. BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK
65678. BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT
65679. BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK
65680. BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT
65681. BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK
65682. BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT
65683. BIF_BX_PF0_BIF_FB_EN__FB_READ_EN_MASK
65684. BIF_BX_PF0_BIF_FB_EN__FB_READ_EN__SHIFT
65685. BIF_BX_PF0_BIF_FB_EN__FB_WRITE_EN_MASK
65686. BIF_BX_PF0_BIF_FB_EN__FB_WRITE_EN__SHIFT
65687. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK
65688. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT
65689. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK
65690. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT
65691. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK
65692. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT
65693. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK
65694. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT
65695. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK
65696. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT
65697. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK
65698. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT
65699. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK
65700. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT
65701. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK
65702. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT
65703. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK
65704. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT
65705. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK
65706. BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT
65707. BIF_BX_PF0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK
65708. BIF_BX_PF0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT
65709. BIF_BX_PF0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK
65710. BIF_BX_PF0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT
65711. BIF_BX_PF0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK
65712. BIF_BX_PF0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT
65713. BIF_BX_PF0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK
65714. BIF_BX_PF0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT
65715. BIF_BX_PF0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK
65716. BIF_BX_PF0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT
65717. BIF_BX_PF0_BIF_RB_BASE__ADDR_MASK
65718. BIF_BX_PF0_BIF_RB_BASE__ADDR__SHIFT
65719. BIF_BX_PF0_BIF_RB_CNTL__BIF_RB_TRAN_MASK
65720. BIF_BX_PF0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT
65721. BIF_BX_PF0_BIF_RB_CNTL__RB_ENABLE_MASK
65722. BIF_BX_PF0_BIF_RB_CNTL__RB_ENABLE__SHIFT
65723. BIF_BX_PF0_BIF_RB_CNTL__RB_SIZE_MASK
65724. BIF_BX_PF0_BIF_RB_CNTL__RB_SIZE__SHIFT
65725. BIF_BX_PF0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK
65726. BIF_BX_PF0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT
65727. BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK
65728. BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT
65729. BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK
65730. BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT
65731. BIF_BX_PF0_BIF_RB_RPTR__OFFSET_MASK
65732. BIF_BX_PF0_BIF_RB_RPTR__OFFSET__SHIFT
65733. BIF_BX_PF0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK
65734. BIF_BX_PF0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT
65735. BIF_BX_PF0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK
65736. BIF_BX_PF0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT
65737. BIF_BX_PF0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK
65738. BIF_BX_PF0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT
65739. BIF_BX_PF0_BIF_RB_WPTR__OFFSET_MASK
65740. BIF_BX_PF0_BIF_RB_WPTR__OFFSET__SHIFT
65741. BIF_BX_PF0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK
65742. BIF_BX_PF0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT
65743. BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK
65744. BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT
65745. BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK
65746. BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT
65747. BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK
65748. BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT
65749. BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK
65750. BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT
65751. BIF_BX_PF0_BIF_SCRATCH0__BIF_SCRATCH0_MASK
65752. BIF_BX_PF0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT
65753. BIF_BX_PF0_BIF_SCRATCH1__BIF_SCRATCH1_MASK
65754. BIF_BX_PF0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT
65755. BIF_BX_PF0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK
65756. BIF_BX_PF0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT
65757. BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
65758. BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
65759. BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
65760. BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
65761. BIF_BX_PF0_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK
65762. BIF_BX_PF0_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT
65763. BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK
65764. BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT
65765. BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK
65766. BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT
65767. BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK
65768. BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT
65769. BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK
65770. BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT
65771. BIF_BX_PF0_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK
65772. BIF_BX_PF0_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT
65773. BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK
65774. BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT
65775. BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK
65776. BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT
65777. BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK
65778. BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT
65779. BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK
65780. BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT
65781. BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK
65782. BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT
65783. BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK
65784. BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT
65785. BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK
65786. BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT
65787. BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK
65788. BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT
65789. BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK
65790. BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT
65791. BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK
65792. BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT
65793. BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK
65794. BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT
65795. BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK
65796. BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT
65797. BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK
65798. BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT
65799. BIF_BX_PF0_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK
65800. BIF_BX_PF0_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT
65801. BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK
65802. BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT
65803. BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK
65804. BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT
65805. BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK
65806. BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT
65807. BIF_BX_PF0_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK
65808. BIF_BX_PF0_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT
65809. BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK
65810. BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT
65811. BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK
65812. BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT
65813. BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK
65814. BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT
65815. BIF_BX_PF0_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK
65816. BIF_BX_PF0_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT
65817. BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK
65818. BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT
65819. BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK
65820. BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT
65821. BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK
65822. BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT
65823. BIF_BX_PF0_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK
65824. BIF_BX_PF0_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT
65825. BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK
65826. BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT
65827. BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK
65828. BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT
65829. BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK
65830. BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT
65831. BIF_BX_PF0_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK
65832. BIF_BX_PF0_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT
65833. BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK
65834. BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT
65835. BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK
65836. BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT
65837. BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK
65838. BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT
65839. BIF_BX_PF0_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK
65840. BIF_BX_PF0_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT
65841. BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK
65842. BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT
65843. BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK
65844. BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT
65845. BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK
65846. BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT
65847. BIF_BX_PF0_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK
65848. BIF_BX_PF0_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT
65849. BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK
65850. BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT
65851. BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK
65852. BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT
65853. BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK
65854. BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT
65855. BIF_BX_PF0_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK
65856. BIF_BX_PF0_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT
65857. BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK
65858. BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT
65859. BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK
65860. BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT
65861. BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK
65862. BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT
65863. BIF_BX_PF0_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK
65864. BIF_BX_PF0_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT
65865. BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK
65866. BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT
65867. BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK
65868. BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT
65869. BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK
65870. BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT
65871. BIF_BX_PF0_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK
65872. BIF_BX_PF0_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT
65873. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
65874. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
65875. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
65876. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
65877. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
65878. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
65879. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
65880. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
65881. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
65882. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
65883. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
65884. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
65885. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
65886. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
65887. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
65888. BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
65889. BIF_BX_PF0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK
65890. BIF_BX_PF0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT
65891. BIF_BX_PF0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK
65892. BIF_BX_PF0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT
65893. BIF_BX_PF0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK
65894. BIF_BX_PF0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT
65895. BIF_BX_PF0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK
65896. BIF_BX_PF0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT
65897. BIF_BX_PF0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK
65898. BIF_BX_PF0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT
65899. BIF_BX_PF0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK
65900. BIF_BX_PF0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT
65901. BIF_BX_PF0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK
65902. BIF_BX_PF0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT
65903. BIF_BX_PF0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK
65904. BIF_BX_PF0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT
65905. BIF_BX_PF0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK
65906. BIF_BX_PF0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT
65907. BIF_BX_PF0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK
65908. BIF_BX_PF0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT
65909. BIF_BX_PF0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK
65910. BIF_BX_PF0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT
65911. BIF_BX_PF0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK
65912. BIF_BX_PF0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT
65913. BIF_BX_PF0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK
65914. BIF_BX_PF0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT
65915. BIF_BX_PF0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK
65916. BIF_BX_PF0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT
65917. BIF_BX_PF0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK
65918. BIF_BX_PF0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT
65919. BIF_BX_PF0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK
65920. BIF_BX_PF0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT
65921. BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK
65922. BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT
65923. BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK
65924. BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT
65925. BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK
65926. BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT
65927. BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK
65928. BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT
65929. BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK
65930. BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT
65931. BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK
65932. BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT
65933. BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK
65934. BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT
65935. BIF_BX_PF0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK
65936. BIF_BX_PF0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT
65937. BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_DN_MASK
65938. BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_DN__SHIFT
65939. BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_EP_MASK
65940. BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_EP__SHIFT
65941. BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_SWUS_MASK
65942. BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT
65943. BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK
65944. BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT
65945. BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK
65946. BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT
65947. BIF_BX_PF0_BUS_CNTL__RD_STALL_IO_WR_MASK
65948. BIF_BX_PF0_BUS_CNTL__RD_STALL_IO_WR__SHIFT
65949. BIF_BX_PF0_BUS_CNTL__SET_AZ_TC_MASK
65950. BIF_BX_PF0_BUS_CNTL__SET_AZ_TC__SHIFT
65951. BIF_BX_PF0_BUS_CNTL__SET_MC_TC_MASK
65952. BIF_BX_PF0_BUS_CNTL__SET_MC_TC__SHIFT
65953. BIF_BX_PF0_BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK
65954. BIF_BX_PF0_BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT
65955. BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK
65956. BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT
65957. BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK
65958. BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT
65959. BIF_BX_PF0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK
65960. BIF_BX_PF0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT
65961. BIF_BX_PF0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK
65962. BIF_BX_PF0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT
65963. BIF_BX_PF0_BUS_CNTL__ZERO_BE_RD_EN_MASK
65964. BIF_BX_PF0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT
65965. BIF_BX_PF0_BUS_CNTL__ZERO_BE_WR_EN_MASK
65966. BIF_BX_PF0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT
65967. BIF_BX_PF0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK
65968. BIF_BX_PF0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT
65969. BIF_BX_PF0_BX_RESET_EN__COR_RESET_EN_MASK
65970. BIF_BX_PF0_BX_RESET_EN__COR_RESET_EN__SHIFT
65971. BIF_BX_PF0_BX_RESET_EN__FLR_TWICE_EN_MASK
65972. BIF_BX_PF0_BX_RESET_EN__FLR_TWICE_EN__SHIFT
65973. BIF_BX_PF0_BX_RESET_EN__REG_RESET_EN_MASK
65974. BIF_BX_PF0_BX_RESET_EN__REG_RESET_EN__SHIFT
65975. BIF_BX_PF0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK
65976. BIF_BX_PF0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT
65977. BIF_BX_PF0_BX_RESET_EN__STY_RESET_EN_MASK
65978. BIF_BX_PF0_BX_RESET_EN__STY_RESET_EN__SHIFT
65979. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK
65980. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT
65981. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK
65982. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT
65983. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK
65984. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT
65985. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK
65986. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT
65987. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK
65988. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT
65989. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK
65990. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT
65991. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK
65992. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT
65993. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK
65994. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT
65995. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK
65996. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT
65997. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK
65998. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT
65999. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK
66000. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT
66001. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK
66002. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT
66003. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK
66004. BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT
66005. BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
66006. BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
66007. BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
66008. BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
66009. BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
66010. BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
66011. BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
66012. BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
66013. BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
66014. BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
66015. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK
66016. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT
66017. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK
66018. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT
66019. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK
66020. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT
66021. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK
66022. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT
66023. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK
66024. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT
66025. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK
66026. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT
66027. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK
66028. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT
66029. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK
66030. BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT
66031. BIF_BX_PF0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK
66032. BIF_BX_PF0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT
66033. BIF_BX_PF0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK
66034. BIF_BX_PF0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT
66035. BIF_BX_PF0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK
66036. BIF_BX_PF0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT
66037. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK
66038. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT
66039. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK
66040. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT
66041. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK
66042. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT
66043. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK
66044. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT
66045. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK
66046. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT
66047. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK
66048. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT
66049. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK
66050. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT
66051. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK
66052. BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT
66053. BIF_BX_PF0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK
66054. BIF_BX_PF0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT
66055. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK
66056. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT
66057. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK
66058. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT
66059. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK
66060. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT
66061. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK
66062. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT
66063. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK
66064. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT
66065. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK
66066. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT
66067. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK
66068. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT
66069. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK
66070. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT
66071. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK
66072. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT
66073. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK
66074. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT
66075. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK
66076. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
66077. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
66078. BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
66079. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK
66080. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT
66081. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK
66082. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT
66083. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK
66084. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT
66085. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK
66086. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT
66087. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK
66088. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT
66089. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK
66090. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT
66091. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK
66092. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT
66093. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK
66094. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT
66095. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK
66096. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT
66097. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK
66098. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT
66099. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK
66100. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
66101. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK
66102. BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
66103. BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
66104. BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
66105. BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
66106. BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
66107. BIF_BX_PF0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK
66108. BIF_BX_PF0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT
66109. BIF_BX_PF0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK
66110. BIF_BX_PF0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT
66111. BIF_BX_PF0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK
66112. BIF_BX_PF0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT
66113. BIF_BX_PF0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK
66114. BIF_BX_PF0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT
66115. BIF_BX_PF0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK
66116. BIF_BX_PF0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT
66117. BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK
66118. BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT
66119. BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK
66120. BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT
66121. BIF_BX_PF0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK
66122. BIF_BX_PF0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT
66123. BIF_BX_PF0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK
66124. BIF_BX_PF0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT
66125. BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
66126. BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
66127. BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
66128. BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
66129. BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
66130. BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
66131. BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
66132. BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
66133. BIF_BX_PF0_MAILBOX_INDEX__MAILBOX_INDEX_MASK
66134. BIF_BX_PF0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT
66135. BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
66136. BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
66137. BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
66138. BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
66139. BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
66140. BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
66141. BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
66142. BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
66143. BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
66144. BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
66145. BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
66146. BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
66147. BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
66148. BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
66149. BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
66150. BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
66151. BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
66152. BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
66153. BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
66154. BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
66155. BIF_BX_PF0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK
66156. BIF_BX_PF0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT
66157. BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK
66158. BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT
66159. BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK
66160. BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT
66161. BIF_BX_PF0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK
66162. BIF_BX_PF0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT
66163. BIF_BX_PF0_MM_DATA__MM_DATA_MASK
66164. BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT
66165. BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK
66166. BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
66167. BIF_BX_PF0_MM_INDEX__MM_APER_MASK
66168. BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT
66169. BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK
66170. BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT
66171. BIF_BX_PF0_PCIE_DATA2__PCIE_DATA2_MASK
66172. BIF_BX_PF0_PCIE_DATA2__PCIE_DATA2__SHIFT
66173. BIF_BX_PF0_PCIE_DATA__PCIE_DATA_MASK
66174. BIF_BX_PF0_PCIE_DATA__PCIE_DATA__SHIFT
66175. BIF_BX_PF0_PCIE_INDEX2__PCIE_INDEX2_MASK
66176. BIF_BX_PF0_PCIE_INDEX2__PCIE_INDEX2__SHIFT
66177. BIF_BX_PF0_PCIE_INDEX__PCIE_INDEX_MASK
66178. BIF_BX_PF0_PCIE_INDEX__PCIE_INDEX__SHIFT
66179. BIF_BX_PF0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK
66180. BIF_BX_PF0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT
66181. BIF_BX_PF0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK
66182. BIF_BX_PF0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT
66183. BIF_BX_PF0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK
66184. BIF_BX_PF0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT
66185. BIF_BX_PF0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK
66186. BIF_BX_PF0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT
66187. BIF_BX_PF0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK
66188. BIF_BX_PF0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT
66189. BIF_BX_PF0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK
66190. BIF_BX_PF0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT
66191. BIF_BX_PF0_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK
66192. BIF_BX_PF0_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT
66193. BIF_BX_PF0_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK
66194. BIF_BX_PF0_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT
66195. BIF_BX_PF0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK
66196. BIF_BX_PF0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT
66197. BIF_BX_PF1_BACO_CNTL__BACO_AUTO_EXIT_MASK
66198. BIF_BX_PF1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT
66199. BIF_BX_PF1_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK
66200. BIF_BX_PF1_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT
66201. BIF_BX_PF1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK
66202. BIF_BX_PF1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT
66203. BIF_BX_PF1_BACO_CNTL__BACO_DUMMY_EN_MASK
66204. BIF_BX_PF1_BACO_CNTL__BACO_DUMMY_EN__SHIFT
66205. BIF_BX_PF1_BACO_CNTL__BACO_EN_MASK
66206. BIF_BX_PF1_BACO_CNTL__BACO_EN__SHIFT
66207. BIF_BX_PF1_BACO_CNTL__BACO_MODE_MASK
66208. BIF_BX_PF1_BACO_CNTL__BACO_MODE__SHIFT
66209. BIF_BX_PF1_BACO_CNTL__BACO_POWER_OFF_MASK
66210. BIF_BX_PF1_BACO_CNTL__BACO_POWER_OFF__SHIFT
66211. BIF_BX_PF1_BACO_CNTL__BACO_RST_INTR_MASK_MASK
66212. BIF_BX_PF1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT
66213. BIF_BX_PF1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK
66214. BIF_BX_PF1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT
66215. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
66216. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
66217. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
66218. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
66219. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
66220. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
66221. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
66222. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
66223. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
66224. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
66225. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
66226. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
66227. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
66228. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
66229. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
66230. BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
66231. BIF_BX_PF1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK
66232. BIF_BX_PF1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT
66233. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK
66234. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT
66235. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK
66236. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT
66237. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK
66238. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT
66239. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK
66240. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT
66241. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK
66242. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT
66243. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK
66244. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT
66245. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK
66246. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT
66247. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK
66248. BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT
66249. BIF_BX_PF1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK
66250. BIF_BX_PF1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT
66251. BIF_BX_PF1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK
66252. BIF_BX_PF1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT
66253. BIF_BX_PF1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK
66254. BIF_BX_PF1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT
66255. BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
66256. BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
66257. BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
66258. BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
66259. BIF_BX_PF1_BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK
66260. BIF_BX_PF1_BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT
66261. BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK
66262. BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT
66263. BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK
66264. BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT
66265. BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK
66266. BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT
66267. BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK
66268. BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT
66269. BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK
66270. BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT
66271. BIF_BX_PF1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK
66272. BIF_BX_PF1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT
66273. BIF_BX_PF1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK
66274. BIF_BX_PF1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT
66275. BIF_BX_PF1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK
66276. BIF_BX_PF1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT
66277. BIF_BX_PF1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK
66278. BIF_BX_PF1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT
66279. BIF_BX_PF1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK
66280. BIF_BX_PF1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT
66281. BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK
66282. BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT
66283. BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK
66284. BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT
66285. BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK
66286. BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT
66287. BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK
66288. BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT
66289. BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK
66290. BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT
66291. BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK
66292. BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT
66293. BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK
66294. BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT
66295. BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK
66296. BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT
66297. BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK
66298. BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT
66299. BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK
66300. BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT
66301. BIF_BX_PF1_BIF_FB_EN__FB_READ_EN_MASK
66302. BIF_BX_PF1_BIF_FB_EN__FB_READ_EN__SHIFT
66303. BIF_BX_PF1_BIF_FB_EN__FB_WRITE_EN_MASK
66304. BIF_BX_PF1_BIF_FB_EN__FB_WRITE_EN__SHIFT
66305. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK
66306. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT
66307. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK
66308. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT
66309. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK
66310. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT
66311. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK
66312. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT
66313. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK
66314. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT
66315. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK
66316. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT
66317. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK
66318. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT
66319. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK
66320. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT
66321. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK
66322. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT
66323. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK
66324. BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT
66325. BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK
66326. BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT
66327. BIF_BX_PF1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK
66328. BIF_BX_PF1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT
66329. BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK
66330. BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT
66331. BIF_BX_PF1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK
66332. BIF_BX_PF1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT
66333. BIF_BX_PF1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK
66334. BIF_BX_PF1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT
66335. BIF_BX_PF1_BIF_RB_BASE__ADDR_MASK
66336. BIF_BX_PF1_BIF_RB_BASE__ADDR__SHIFT
66337. BIF_BX_PF1_BIF_RB_CNTL__BIF_RB_TRAN_MASK
66338. BIF_BX_PF1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT
66339. BIF_BX_PF1_BIF_RB_CNTL__RB_ENABLE_MASK
66340. BIF_BX_PF1_BIF_RB_CNTL__RB_ENABLE__SHIFT
66341. BIF_BX_PF1_BIF_RB_CNTL__RB_SIZE_MASK
66342. BIF_BX_PF1_BIF_RB_CNTL__RB_SIZE__SHIFT
66343. BIF_BX_PF1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK
66344. BIF_BX_PF1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT
66345. BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK
66346. BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT
66347. BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK
66348. BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT
66349. BIF_BX_PF1_BIF_RB_RPTR__OFFSET_MASK
66350. BIF_BX_PF1_BIF_RB_RPTR__OFFSET__SHIFT
66351. BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK
66352. BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT
66353. BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK
66354. BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT
66355. BIF_BX_PF1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK
66356. BIF_BX_PF1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT
66357. BIF_BX_PF1_BIF_RB_WPTR__OFFSET_MASK
66358. BIF_BX_PF1_BIF_RB_WPTR__OFFSET__SHIFT
66359. BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK
66360. BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT
66361. BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK
66362. BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT
66363. BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK
66364. BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT
66365. BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK
66366. BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT
66367. BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK
66368. BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT
66369. BIF_BX_PF1_BIF_SCRATCH0__BIF_SCRATCH0_MASK
66370. BIF_BX_PF1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT
66371. BIF_BX_PF1_BIF_SCRATCH1__BIF_SCRATCH1_MASK
66372. BIF_BX_PF1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT
66373. BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK
66374. BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT
66375. BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
66376. BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
66377. BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
66378. BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
66379. BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK
66380. BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT
66381. BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK
66382. BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT
66383. BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK
66384. BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT
66385. BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK
66386. BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT
66387. BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK
66388. BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT
66389. BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK
66390. BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT
66391. BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK
66392. BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT
66393. BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK
66394. BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT
66395. BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK
66396. BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT
66397. BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK
66398. BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT
66399. BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK
66400. BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT
66401. BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK
66402. BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT
66403. BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK
66404. BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT
66405. BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK
66406. BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT
66407. BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK
66408. BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT
66409. BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK
66410. BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT
66411. BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK
66412. BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT
66413. BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK
66414. BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT
66415. BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK
66416. BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT
66417. BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK
66418. BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT
66419. BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK
66420. BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT
66421. BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK
66422. BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT
66423. BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK
66424. BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT
66425. BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK
66426. BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT
66427. BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK
66428. BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT
66429. BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK
66430. BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT
66431. BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK
66432. BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT
66433. BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK
66434. BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT
66435. BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK
66436. BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT
66437. BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK
66438. BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT
66439. BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK
66440. BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT
66441. BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK
66442. BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT
66443. BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK
66444. BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT
66445. BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK
66446. BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT
66447. BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK
66448. BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT
66449. BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK
66450. BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT
66451. BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK
66452. BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT
66453. BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK
66454. BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT
66455. BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK
66456. BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT
66457. BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK
66458. BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT
66459. BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK
66460. BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT
66461. BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK
66462. BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT
66463. BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK
66464. BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT
66465. BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK
66466. BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT
66467. BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK
66468. BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT
66469. BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK
66470. BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT
66471. BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK
66472. BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT
66473. BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK
66474. BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT
66475. BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK
66476. BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT
66477. BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK
66478. BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT
66479. BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK
66480. BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT
66481. BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK
66482. BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT
66483. BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK
66484. BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT
66485. BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK
66486. BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT
66487. BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK
66488. BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT
66489. BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK
66490. BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT
66491. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
66492. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
66493. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
66494. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
66495. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
66496. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
66497. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
66498. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
66499. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
66500. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
66501. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
66502. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
66503. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
66504. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
66505. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
66506. BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
66507. BIF_BX_PF1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK
66508. BIF_BX_PF1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT
66509. BIF_BX_PF1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK
66510. BIF_BX_PF1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT
66511. BIF_BX_PF1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK
66512. BIF_BX_PF1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT
66513. BIF_BX_PF1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK
66514. BIF_BX_PF1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT
66515. BIF_BX_PF1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK
66516. BIF_BX_PF1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT
66517. BIF_BX_PF1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK
66518. BIF_BX_PF1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT
66519. BIF_BX_PF1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK
66520. BIF_BX_PF1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT
66521. BIF_BX_PF1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK
66522. BIF_BX_PF1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT
66523. BIF_BX_PF1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK
66524. BIF_BX_PF1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT
66525. BIF_BX_PF1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK
66526. BIF_BX_PF1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT
66527. BIF_BX_PF1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK
66528. BIF_BX_PF1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT
66529. BIF_BX_PF1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK
66530. BIF_BX_PF1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT
66531. BIF_BX_PF1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK
66532. BIF_BX_PF1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT
66533. BIF_BX_PF1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK
66534. BIF_BX_PF1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT
66535. BIF_BX_PF1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK
66536. BIF_BX_PF1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT
66537. BIF_BX_PF1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK
66538. BIF_BX_PF1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT
66539. BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK
66540. BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT
66541. BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK
66542. BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT
66543. BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK
66544. BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT
66545. BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK
66546. BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT
66547. BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK
66548. BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT
66549. BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK
66550. BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT
66551. BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK
66552. BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT
66553. BIF_BX_PF1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK
66554. BIF_BX_PF1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT
66555. BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_DN_MASK
66556. BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_DN__SHIFT
66557. BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_EP_MASK
66558. BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_EP__SHIFT
66559. BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_SWUS_MASK
66560. BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT
66561. BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK
66562. BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT
66563. BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK
66564. BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT
66565. BIF_BX_PF1_BUS_CNTL__RD_STALL_IO_WR_MASK
66566. BIF_BX_PF1_BUS_CNTL__RD_STALL_IO_WR__SHIFT
66567. BIF_BX_PF1_BUS_CNTL__SET_AZ_TC_MASK
66568. BIF_BX_PF1_BUS_CNTL__SET_AZ_TC__SHIFT
66569. BIF_BX_PF1_BUS_CNTL__SET_MC_TC_MASK
66570. BIF_BX_PF1_BUS_CNTL__SET_MC_TC__SHIFT
66571. BIF_BX_PF1_BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK
66572. BIF_BX_PF1_BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT
66573. BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK
66574. BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT
66575. BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK
66576. BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT
66577. BIF_BX_PF1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK
66578. BIF_BX_PF1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT
66579. BIF_BX_PF1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK
66580. BIF_BX_PF1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT
66581. BIF_BX_PF1_BUS_CNTL__ZERO_BE_RD_EN_MASK
66582. BIF_BX_PF1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT
66583. BIF_BX_PF1_BUS_CNTL__ZERO_BE_WR_EN_MASK
66584. BIF_BX_PF1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT
66585. BIF_BX_PF1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK
66586. BIF_BX_PF1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT
66587. BIF_BX_PF1_BX_RESET_EN__COR_RESET_EN_MASK
66588. BIF_BX_PF1_BX_RESET_EN__COR_RESET_EN__SHIFT
66589. BIF_BX_PF1_BX_RESET_EN__FLR_TWICE_EN_MASK
66590. BIF_BX_PF1_BX_RESET_EN__FLR_TWICE_EN__SHIFT
66591. BIF_BX_PF1_BX_RESET_EN__REG_RESET_EN_MASK
66592. BIF_BX_PF1_BX_RESET_EN__REG_RESET_EN__SHIFT
66593. BIF_BX_PF1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK
66594. BIF_BX_PF1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT
66595. BIF_BX_PF1_BX_RESET_EN__STY_RESET_EN_MASK
66596. BIF_BX_PF1_BX_RESET_EN__STY_RESET_EN__SHIFT
66597. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK
66598. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT
66599. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK
66600. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT
66601. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK
66602. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT
66603. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK
66604. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT
66605. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK
66606. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT
66607. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK
66608. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT
66609. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK
66610. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT
66611. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK
66612. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT
66613. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK
66614. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT
66615. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK
66616. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT
66617. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK
66618. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT
66619. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK
66620. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT
66621. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK
66622. BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT
66623. BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
66624. BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
66625. BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
66626. BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
66627. BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
66628. BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
66629. BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
66630. BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
66631. BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
66632. BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
66633. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK
66634. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT
66635. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK
66636. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT
66637. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK
66638. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT
66639. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK
66640. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT
66641. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK
66642. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT
66643. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK
66644. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT
66645. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK
66646. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT
66647. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK
66648. BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT
66649. BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK
66650. BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT
66651. BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK
66652. BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT
66653. BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK
66654. BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT
66655. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK
66656. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT
66657. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK
66658. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT
66659. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK
66660. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT
66661. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK
66662. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT
66663. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK
66664. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT
66665. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK
66666. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT
66667. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK
66668. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT
66669. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK
66670. BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT
66671. BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK
66672. BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT
66673. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK
66674. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT
66675. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK
66676. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT
66677. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK
66678. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT
66679. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK
66680. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT
66681. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK
66682. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT
66683. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK
66684. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT
66685. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK
66686. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT
66687. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK
66688. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT
66689. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK
66690. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT
66691. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK
66692. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT
66693. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK
66694. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
66695. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK
66696. BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
66697. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK
66698. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT
66699. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK
66700. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT
66701. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK
66702. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT
66703. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK
66704. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT
66705. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK
66706. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT
66707. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK
66708. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT
66709. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK
66710. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT
66711. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK
66712. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT
66713. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK
66714. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT
66715. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK
66716. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT
66717. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK
66718. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
66719. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK
66720. BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
66721. BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
66722. BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
66723. BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
66724. BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
66725. BIF_BX_PF1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK
66726. BIF_BX_PF1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT
66727. BIF_BX_PF1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK
66728. BIF_BX_PF1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT
66729. BIF_BX_PF1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK
66730. BIF_BX_PF1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT
66731. BIF_BX_PF1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK
66732. BIF_BX_PF1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT
66733. BIF_BX_PF1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK
66734. BIF_BX_PF1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT
66735. BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK
66736. BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT
66737. BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK
66738. BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT
66739. BIF_BX_PF1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK
66740. BIF_BX_PF1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT
66741. BIF_BX_PF1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK
66742. BIF_BX_PF1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT
66743. BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
66744. BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
66745. BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
66746. BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
66747. BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
66748. BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
66749. BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
66750. BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
66751. BIF_BX_PF1_MAILBOX_INDEX__MAILBOX_INDEX_MASK
66752. BIF_BX_PF1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT
66753. BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
66754. BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
66755. BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
66756. BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
66757. BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
66758. BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
66759. BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
66760. BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
66761. BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
66762. BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
66763. BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
66764. BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
66765. BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
66766. BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
66767. BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
66768. BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
66769. BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
66770. BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
66771. BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
66772. BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
66773. BIF_BX_PF1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK
66774. BIF_BX_PF1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT
66775. BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK
66776. BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT
66777. BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK
66778. BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT
66779. BIF_BX_PF1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK
66780. BIF_BX_PF1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT
66781. BIF_BX_PF1_MM_DATA__MM_DATA_MASK
66782. BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT
66783. BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK
66784. BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
66785. BIF_BX_PF1_MM_INDEX__MM_APER_MASK
66786. BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT
66787. BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK
66788. BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT
66789. BIF_BX_PF1_PCIE_DATA2__PCIE_DATA2_MASK
66790. BIF_BX_PF1_PCIE_DATA2__PCIE_DATA2__SHIFT
66791. BIF_BX_PF1_PCIE_DATA__PCIE_DATA_MASK
66792. BIF_BX_PF1_PCIE_DATA__PCIE_DATA__SHIFT
66793. BIF_BX_PF1_PCIE_INDEX2__PCIE_INDEX2_MASK
66794. BIF_BX_PF1_PCIE_INDEX2__PCIE_INDEX2__SHIFT
66795. BIF_BX_PF1_PCIE_INDEX__PCIE_INDEX_MASK
66796. BIF_BX_PF1_PCIE_INDEX__PCIE_INDEX__SHIFT
66797. BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK
66798. BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT
66799. BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK
66800. BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT
66801. BIF_BX_PF1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK
66802. BIF_BX_PF1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT
66803. BIF_BX_PF1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK
66804. BIF_BX_PF1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT
66805. BIF_BX_PF1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK
66806. BIF_BX_PF1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT
66807. BIF_BX_PF1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK
66808. BIF_BX_PF1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT
66809. BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK
66810. BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT
66811. BIF_BX_PF1_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK
66812. BIF_BX_PF1_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT
66813. BIF_BX_PF1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK
66814. BIF_BX_PF1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT
66815. BIF_BX_PF3_MM_DATA__MM_DATA_MASK
66816. BIF_BX_PF3_MM_DATA__MM_DATA__SHIFT
66817. BIF_BX_PF3_MM_INDEX_HI__MM_OFFSET_HI_MASK
66818. BIF_BX_PF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
66819. BIF_BX_PF3_MM_INDEX__MM_APER_MASK
66820. BIF_BX_PF3_MM_INDEX__MM_APER__SHIFT
66821. BIF_BX_PF3_MM_INDEX__MM_OFFSET_MASK
66822. BIF_BX_PF3_MM_INDEX__MM_OFFSET__SHIFT
66823. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK
66824. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT
66825. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK
66826. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT
66827. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK
66828. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT
66829. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK
66830. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT
66831. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK
66832. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT
66833. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK
66834. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT
66835. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK
66836. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT
66837. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK
66838. BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT
66839. BIF_BX_PF_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK
66840. BIF_BX_PF_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT
66841. BIF_BX_PF_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK
66842. BIF_BX_PF_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT
66843. BIF_BX_PF_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
66844. BIF_BX_PF_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
66845. BIF_BX_PF_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
66846. BIF_BX_PF_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
66847. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
66848. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
66849. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
66850. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
66851. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
66852. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
66853. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
66854. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
66855. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
66856. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
66857. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
66858. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
66859. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
66860. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
66861. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
66862. BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
66863. BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK
66864. BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT
66865. BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK
66866. BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT
66867. BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK
66868. BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT
66869. BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK
66870. BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT
66871. BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK
66872. BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT
66873. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK
66874. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0__SHIFT
66875. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK
66876. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1__SHIFT
66877. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK
66878. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2__SHIFT
66879. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK
66880. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3__SHIFT
66881. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK
66882. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4__SHIFT
66883. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK
66884. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5__SHIFT
66885. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK
66886. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6__SHIFT
66887. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK
66888. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7__SHIFT
66889. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK
66890. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8__SHIFT
66891. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK
66892. BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9__SHIFT
66893. BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK
66894. BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
66895. BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK
66896. BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
66897. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP0_MASK
66898. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP0__SHIFT
66899. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP1_MASK
66900. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP1__SHIFT
66901. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP2_MASK
66902. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP2__SHIFT
66903. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP3_MASK
66904. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP3__SHIFT
66905. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP4_MASK
66906. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP4__SHIFT
66907. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP5_MASK
66908. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP5__SHIFT
66909. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP6_MASK
66910. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP6__SHIFT
66911. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP7_MASK
66912. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP7__SHIFT
66913. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP8_MASK
66914. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP8__SHIFT
66915. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP9_MASK
66916. BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP9__SHIFT
66917. BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA0_MASK
66918. BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
66919. BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA1_MASK
66920. BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
66921. BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
66922. BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
66923. BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
66924. BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
66925. BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_ACK_MASK
66926. BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT
66927. BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_VALID_MASK
66928. BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT
66929. BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_ACK_MASK
66930. BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT
66931. BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_VALID_MASK
66932. BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT
66933. BIF_BX_PF_MAILBOX_INT_CNTL__ACK_INT_EN_MASK
66934. BIF_BX_PF_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT
66935. BIF_BX_PF_MAILBOX_INT_CNTL__VALID_INT_EN_MASK
66936. BIF_BX_PF_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT
66937. BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK
66938. BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT
66939. BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK
66940. BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT
66941. BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK
66942. BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT
66943. BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK
66944. BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT
66945. BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK
66946. BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT
66947. BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK
66948. BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT
66949. BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK
66950. BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT
66951. BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK
66952. BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT
66953. BIF_BX_PF_MM_DATA__MM_DATA_MASK
66954. BIF_BX_PF_MM_DATA__MM_DATA__SHIFT
66955. BIF_BX_PF_MM_INDEX_HI__MM_OFFSET_HI_MASK
66956. BIF_BX_PF_MM_INDEX_HI__MM_OFFSET_HI__SHIFT
66957. BIF_BX_PF_MM_INDEX__MM_APER_MASK
66958. BIF_BX_PF_MM_INDEX__MM_APER__SHIFT
66959. BIF_BX_PF_MM_INDEX__MM_OFFSET_MASK
66960. BIF_BX_PF_MM_INDEX__MM_OFFSET__SHIFT
66961. BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK
66962. BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT
66963. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN_MASK
66964. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN__SHIFT
66965. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_IGNORE_QUICKSIM_MASK
66966. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_IGNORE_QUICKSIM__SHIFT
66967. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN_MASK
66968. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN__SHIFT
66969. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_MASK
66970. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL__SHIFT
66971. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD_MASK
66972. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD__SHIFT
66973. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU_MASK
66974. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU__SHIFT
66975. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD_MASK
66976. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD__SHIFT
66977. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU_MASK
66978. BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU__SHIFT
66979. BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
66980. BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
66981. BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
66982. BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
66983. BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
66984. BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
66985. BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
66986. BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
66987. BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK
66988. BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT
66989. BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK
66990. BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT
66991. BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK
66992. BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT
66993. BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK
66994. BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT
66995. BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK
66996. BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT
66997. BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK
66998. BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT
66999. BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK
67000. BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT
67001. BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK
67002. BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT
67003. BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK
67004. BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT
67005. BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK
67006. BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT
67007. BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
67008. BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
67009. BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK
67010. BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT
67011. BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
67012. BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
67013. BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK
67014. BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT
67015. BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK
67016. BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT
67017. BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK
67018. BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT
67019. BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK
67020. BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT
67021. BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK
67022. BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT
67023. BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK
67024. BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT
67025. BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
67026. BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
67027. BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK
67028. BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT
67029. BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
67030. BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
67031. BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK
67032. BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT
67033. BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK
67034. BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
67035. BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK
67036. BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT
67037. BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK
67038. BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT
67039. BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK
67040. BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK
67041. BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT
67042. BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT
67043. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
67044. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
67045. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
67046. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
67047. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
67048. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
67049. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
67050. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
67051. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
67052. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
67053. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
67054. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
67055. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
67056. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
67057. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
67058. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
67059. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
67060. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
67061. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
67062. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
67063. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
67064. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
67065. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
67066. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
67067. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
67068. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
67069. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
67070. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
67071. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
67072. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
67073. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
67074. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
67075. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
67076. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
67077. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
67078. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
67079. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
67080. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
67081. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
67082. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
67083. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
67084. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
67085. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
67086. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
67087. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK
67088. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
67089. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK
67090. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
67091. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
67092. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
67093. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
67094. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
67095. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
67096. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
67097. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK
67098. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
67099. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
67100. BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
67101. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
67102. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
67103. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
67104. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
67105. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
67106. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
67107. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
67108. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
67109. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
67110. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
67111. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
67112. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
67113. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
67114. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
67115. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
67116. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
67117. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
67118. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
67119. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK
67120. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT
67121. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK
67122. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT
67123. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
67124. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
67125. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
67126. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
67127. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK
67128. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
67129. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
67130. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
67131. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
67132. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
67133. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK
67134. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
67135. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
67136. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
67137. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
67138. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
67139. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
67140. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
67141. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
67142. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
67143. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
67144. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
67145. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
67146. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
67147. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK
67148. BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
67149. BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK
67150. BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT
67151. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK
67152. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT
67153. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK
67154. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT
67155. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK
67156. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT
67157. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
67158. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
67159. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK
67160. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT
67161. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
67162. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
67163. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
67164. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
67165. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK
67166. BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT
67167. BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK
67168. BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT
67169. BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK
67170. BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT
67171. BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
67172. BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
67173. BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
67174. BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
67175. BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK
67176. BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT
67177. BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK
67178. BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT
67179. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK
67180. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT
67181. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK
67182. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT
67183. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK
67184. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT
67185. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK
67186. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT
67187. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK
67188. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT
67189. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK
67190. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT
67191. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK
67192. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT
67193. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK
67194. BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT
67195. BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK
67196. BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT
67197. BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK
67198. BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT
67199. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK
67200. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT
67201. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK
67202. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT
67203. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK
67204. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT
67205. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK
67206. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT
67207. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK
67208. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT
67209. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK
67210. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT
67211. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK
67212. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT
67213. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK
67214. BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT
67215. BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK
67216. BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT
67217. BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK
67218. BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT
67219. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK
67220. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT
67221. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK
67222. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT
67223. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK
67224. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT
67225. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK
67226. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT
67227. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK
67228. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT
67229. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK
67230. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT
67231. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK
67232. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT
67233. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK
67234. BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT
67235. BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK
67236. BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT
67237. BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK
67238. BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT
67239. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK
67240. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT
67241. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK
67242. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT
67243. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK
67244. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT
67245. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK
67246. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT
67247. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK
67248. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT
67249. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK
67250. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT
67251. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK
67252. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT
67253. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK
67254. BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT
67255. BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK
67256. BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT
67257. BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK
67258. BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT
67259. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK
67260. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT
67261. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK
67262. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT
67263. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK
67264. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT
67265. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK
67266. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT
67267. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK
67268. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT
67269. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK
67270. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT
67271. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK
67272. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT
67273. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK
67274. BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT
67275. BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK
67276. BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT
67277. BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK
67278. BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT
67279. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK
67280. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT
67281. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK
67282. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT
67283. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK
67284. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT
67285. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK
67286. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT
67287. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK
67288. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT
67289. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK
67290. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT
67291. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK
67292. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT
67293. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK
67294. BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT
67295. BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK
67296. BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT
67297. BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK
67298. BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT
67299. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK
67300. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT
67301. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK
67302. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT
67303. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK
67304. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT
67305. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK
67306. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT
67307. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK
67308. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT
67309. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK
67310. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT
67311. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK
67312. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT
67313. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK
67314. BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT
67315. BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK
67316. BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT
67317. BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK
67318. BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT
67319. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK
67320. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT
67321. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK
67322. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT
67323. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK
67324. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT
67325. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK
67326. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT
67327. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK
67328. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT
67329. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK
67330. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT
67331. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK
67332. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT
67333. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK
67334. BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT
67335. BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK
67336. BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT
67337. BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK
67338. BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT
67339. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK
67340. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT
67341. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK
67342. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT
67343. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK
67344. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT
67345. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK
67346. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT
67347. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK
67348. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT
67349. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK
67350. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT
67351. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK
67352. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT
67353. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK
67354. BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT
67355. BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK
67356. BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT
67357. BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK
67358. BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT
67359. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK
67360. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT
67361. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK
67362. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT
67363. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK
67364. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT
67365. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK
67366. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT
67367. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK
67368. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT
67369. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK
67370. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT
67371. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK
67372. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT
67373. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK
67374. BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT
67375. BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK
67376. BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT
67377. BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK
67378. BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT
67379. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK
67380. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT
67381. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK
67382. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT
67383. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK
67384. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT
67385. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK
67386. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT
67387. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK
67388. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT
67389. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK
67390. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT
67391. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK
67392. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT
67393. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK
67394. BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT
67395. BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK
67396. BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT
67397. BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK
67398. BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT
67399. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK
67400. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT
67401. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK
67402. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT
67403. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK
67404. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT
67405. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK
67406. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT
67407. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK
67408. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT
67409. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK
67410. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT
67411. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK
67412. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT
67413. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK
67414. BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT
67415. BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK
67416. BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT
67417. BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK
67418. BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT
67419. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK
67420. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT
67421. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK
67422. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT
67423. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK
67424. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT
67425. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK
67426. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT
67427. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK
67428. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT
67429. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK
67430. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT
67431. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK
67432. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT
67433. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK
67434. BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT
67435. BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK
67436. BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT
67437. BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK
67438. BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT
67439. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK
67440. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT
67441. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK
67442. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT
67443. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK
67444. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT
67445. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK
67446. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT
67447. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK
67448. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT
67449. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK
67450. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT
67451. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK
67452. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT
67453. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK
67454. BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT
67455. BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK
67456. BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT
67457. BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK
67458. BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT
67459. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK
67460. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT
67461. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK
67462. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT
67463. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK
67464. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT
67465. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK
67466. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT
67467. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK
67468. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT
67469. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK
67470. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT
67471. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK
67472. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT
67473. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK
67474. BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT
67475. BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK
67476. BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT
67477. BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK
67478. BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT
67479. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK
67480. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT
67481. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK
67482. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT
67483. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK
67484. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT
67485. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK
67486. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT
67487. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK
67488. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT
67489. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK
67490. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT
67491. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK
67492. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT
67493. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK
67494. BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT
67495. BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK
67496. BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT
67497. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
67498. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
67499. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
67500. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
67501. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
67502. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
67503. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
67504. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
67505. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RESERVED_MASK
67506. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RESERVED__SHIFT
67507. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
67508. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
67509. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
67510. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
67511. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
67512. BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
67513. BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK
67514. BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT
67515. BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
67516. BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
67517. BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
67518. BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
67519. BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
67520. BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
67521. BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
67522. BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
67523. BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK
67524. BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
67525. BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
67526. BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
67527. BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK
67528. BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT
67529. BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK
67530. BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT
67531. BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK
67532. BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT
67533. BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK
67534. BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT
67535. BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
67536. BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
67537. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
67538. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
67539. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
67540. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
67541. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
67542. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
67543. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
67544. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
67545. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
67546. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
67547. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
67548. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
67549. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
67550. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
67551. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK
67552. BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
67553. BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK
67554. BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT
67555. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
67556. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
67557. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
67558. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
67559. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
67560. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
67561. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK
67562. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
67563. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
67564. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
67565. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
67566. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
67567. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
67568. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
67569. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK
67570. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT
67571. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK
67572. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT
67573. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
67574. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
67575. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK
67576. BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT
67577. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
67578. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
67579. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
67580. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
67581. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
67582. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
67583. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
67584. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
67585. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
67586. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
67587. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
67588. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
67589. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
67590. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
67591. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
67592. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
67593. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
67594. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
67595. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
67596. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
67597. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
67598. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
67599. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
67600. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
67601. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
67602. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
67603. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
67604. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
67605. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
67606. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
67607. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
67608. BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
67609. BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK
67610. BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT
67611. BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK
67612. BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT
67613. BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK
67614. BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT
67615. BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK
67616. BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT
67617. BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK
67618. BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT
67619. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
67620. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
67621. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK
67622. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT
67623. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
67624. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
67625. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
67626. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
67627. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK
67628. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT
67629. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
67630. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
67631. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
67632. BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
67633. BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK
67634. BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT
67635. BIF_CFG_DEV0_EPF0_0_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
67636. BIF_CFG_DEV0_EPF0_0_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
67637. BIF_CFG_DEV0_EPF0_0_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
67638. BIF_CFG_DEV0_EPF0_0_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
67639. BIF_CFG_DEV0_EPF0_0_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
67640. BIF_CFG_DEV0_EPF0_0_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
67641. BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK
67642. BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT
67643. BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK
67644. BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT
67645. BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK
67646. BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT
67647. BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK
67648. BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT
67649. BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK
67650. BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT
67651. BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK
67652. BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT
67653. BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK
67654. BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
67655. BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK
67656. BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
67657. BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
67658. BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
67659. BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
67660. BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
67661. BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK
67662. BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
67663. BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
67664. BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
67665. BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
67666. BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
67667. BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
67668. BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
67669. BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK
67670. BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT
67671. BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK
67672. BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
67673. BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK
67674. BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT
67675. BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK
67676. BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT
67677. BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
67678. BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
67679. BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
67680. BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
67681. BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK
67682. BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
67683. BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK
67684. BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT
67685. BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
67686. BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
67687. BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
67688. BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
67689. BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
67690. BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
67691. BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
67692. BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
67693. BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK
67694. BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT
67695. BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK
67696. BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
67697. BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK
67698. BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT
67699. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
67700. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
67701. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
67702. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
67703. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
67704. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
67705. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
67706. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
67707. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
67708. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
67709. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
67710. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
67711. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
67712. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
67713. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
67714. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
67715. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
67716. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
67717. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
67718. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
67719. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
67720. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
67721. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
67722. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
67723. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
67724. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
67725. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
67726. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
67727. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
67728. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
67729. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
67730. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
67731. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
67732. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
67733. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
67734. BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
67735. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
67736. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
67737. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
67738. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
67739. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
67740. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
67741. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
67742. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
67743. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
67744. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
67745. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
67746. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
67747. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
67748. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
67749. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
67750. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
67751. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
67752. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
67753. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
67754. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
67755. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
67756. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
67757. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
67758. BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
67759. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
67760. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
67761. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
67762. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
67763. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
67764. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
67765. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
67766. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
67767. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
67768. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
67769. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
67770. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
67771. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
67772. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
67773. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
67774. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
67775. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
67776. BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
67777. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
67778. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
67779. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
67780. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
67781. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
67782. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
67783. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
67784. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
67785. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK
67786. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT
67787. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
67788. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
67789. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
67790. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
67791. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
67792. BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
67793. BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
67794. BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
67795. BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK
67796. BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
67797. BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK
67798. BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
67799. BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
67800. BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
67801. BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
67802. BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
67803. BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK
67804. BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
67805. BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK
67806. BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
67807. BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
67808. BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
67809. BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
67810. BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
67811. BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK
67812. BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
67813. BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK
67814. BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
67815. BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
67816. BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
67817. BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
67818. BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
67819. BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK
67820. BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
67821. BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK
67822. BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
67823. BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
67824. BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
67825. BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
67826. BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
67827. BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK
67828. BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
67829. BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK
67830. BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
67831. BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
67832. BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
67833. BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
67834. BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
67835. BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK
67836. BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
67837. BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK
67838. BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
67839. BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
67840. BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
67841. BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
67842. BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
67843. BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
67844. BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
67845. BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
67846. BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
67847. BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK
67848. BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT
67849. BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK
67850. BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
67851. BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK
67852. BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT
67853. BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
67854. BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
67855. BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
67856. BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
67857. BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK
67858. BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT
67859. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
67860. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
67861. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
67862. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
67863. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
67864. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
67865. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
67866. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
67867. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
67868. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
67869. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
67870. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
67871. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
67872. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
67873. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
67874. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
67875. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
67876. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
67877. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
67878. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
67879. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
67880. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
67881. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
67882. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
67883. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
67884. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
67885. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
67886. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
67887. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
67888. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
67889. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
67890. BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
67891. BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
67892. BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
67893. BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
67894. BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
67895. BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
67896. BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
67897. BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
67898. BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
67899. BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
67900. BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
67901. BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK
67902. BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT
67903. BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK
67904. BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT
67905. BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK
67906. BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT
67907. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
67908. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
67909. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
67910. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
67911. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
67912. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
67913. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
67914. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
67915. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
67916. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
67917. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
67918. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
67919. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
67920. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
67921. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
67922. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
67923. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
67924. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
67925. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
67926. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
67927. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
67928. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
67929. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
67930. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
67931. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
67932. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
67933. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
67934. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
67935. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
67936. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
67937. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
67938. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
67939. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
67940. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
67941. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
67942. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
67943. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
67944. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
67945. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
67946. BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
67947. BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK
67948. BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
67949. BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK
67950. BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
67951. BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK
67952. BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
67953. BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK
67954. BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
67955. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
67956. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
67957. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
67958. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
67959. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
67960. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
67961. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
67962. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
67963. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
67964. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
67965. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
67966. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
67967. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
67968. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
67969. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
67970. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
67971. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
67972. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
67973. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
67974. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
67975. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
67976. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
67977. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
67978. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
67979. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
67980. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
67981. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
67982. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
67983. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
67984. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
67985. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
67986. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
67987. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
67988. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
67989. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
67990. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
67991. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
67992. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
67993. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
67994. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
67995. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
67996. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
67997. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
67998. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
67999. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
68000. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
68001. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
68002. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
68003. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
68004. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
68005. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
68006. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
68007. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
68008. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
68009. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
68010. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
68011. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
68012. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
68013. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
68014. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
68015. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
68016. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
68017. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
68018. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
68019. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
68020. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
68021. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
68022. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
68023. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
68024. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
68025. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
68026. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
68027. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
68028. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
68029. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
68030. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
68031. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
68032. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
68033. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
68034. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
68035. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
68036. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
68037. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
68038. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
68039. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
68040. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
68041. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
68042. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
68043. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
68044. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
68045. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
68046. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
68047. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
68048. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
68049. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
68050. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
68051. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
68052. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
68053. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
68054. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
68055. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
68056. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
68057. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
68058. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
68059. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
68060. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
68061. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
68062. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
68063. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
68064. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
68065. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
68066. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
68067. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
68068. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
68069. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
68070. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
68071. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
68072. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
68073. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
68074. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
68075. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
68076. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
68077. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
68078. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
68079. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
68080. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
68081. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
68082. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
68083. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
68084. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
68085. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
68086. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
68087. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
68088. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
68089. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
68090. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
68091. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
68092. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
68093. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
68094. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
68095. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
68096. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
68097. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
68098. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
68099. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
68100. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
68101. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
68102. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
68103. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
68104. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
68105. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
68106. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
68107. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
68108. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
68109. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
68110. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
68111. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
68112. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
68113. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
68114. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
68115. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
68116. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
68117. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
68118. BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
68119. BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
68120. BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
68121. BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
68122. BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
68123. BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
68124. BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
68125. BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__RESERVED_MASK
68126. BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__RESERVED__SHIFT
68127. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
68128. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
68129. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
68130. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
68131. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
68132. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
68133. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
68134. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
68135. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
68136. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
68137. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
68138. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
68139. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
68140. BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
68141. BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
68142. BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
68143. BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
68144. BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
68145. BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
68146. BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
68147. BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
68148. BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
68149. BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
68150. BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
68151. BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
68152. BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
68153. BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
68154. BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
68155. BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
68156. BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
68157. BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
68158. BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
68159. BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
68160. BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
68161. BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
68162. BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
68163. BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK
68164. BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
68165. BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK
68166. BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT
68167. BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK
68168. BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT
68169. BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
68170. BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
68171. BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
68172. BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
68173. BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
68174. BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
68175. BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
68176. BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
68177. BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
68178. BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
68179. BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
68180. BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
68181. BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK
68182. BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT
68183. BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK
68184. BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT
68185. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK
68186. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT
68187. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK
68188. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT
68189. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK
68190. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT
68191. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK
68192. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT
68193. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK
68194. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT
68195. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK
68196. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT
68197. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK
68198. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT
68199. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK
68200. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT
68201. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK
68202. BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT
68203. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
68204. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
68205. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
68206. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
68207. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
68208. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
68209. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK
68210. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
68211. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
68212. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
68213. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
68214. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
68215. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
68216. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
68217. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
68218. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
68219. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
68220. BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
68221. BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
68222. BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
68223. BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
68224. BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
68225. BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
68226. BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
68227. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
68228. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
68229. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
68230. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
68231. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
68232. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
68233. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
68234. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
68235. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
68236. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
68237. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
68238. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
68239. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
68240. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
68241. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
68242. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
68243. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
68244. BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
68245. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
68246. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
68247. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
68248. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
68249. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
68250. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
68251. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
68252. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
68253. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
68254. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
68255. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
68256. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
68257. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
68258. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
68259. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK
68260. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
68261. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
68262. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
68263. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
68264. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
68265. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
68266. BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
68267. BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
68268. BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
68269. BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
68270. BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
68271. BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
68272. BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
68273. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK
68274. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT
68275. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK
68276. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT
68277. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK
68278. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT
68279. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
68280. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
68281. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK
68282. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT
68283. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK
68284. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT
68285. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK
68286. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT
68287. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK
68288. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT
68289. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK
68290. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT
68291. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK
68292. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
68293. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK
68294. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT
68295. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK
68296. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT
68297. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK
68298. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT
68299. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK
68300. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT
68301. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK
68302. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT
68303. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK
68304. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT
68305. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK
68306. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT
68307. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK
68308. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT
68309. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK
68310. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT
68311. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK
68312. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT
68313. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK
68314. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT
68315. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK
68316. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT
68317. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK
68318. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT
68319. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK
68320. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT
68321. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK
68322. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT
68323. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK
68324. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT
68325. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK
68326. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT
68327. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK
68328. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT
68329. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK
68330. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT
68331. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK
68332. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT
68333. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK
68334. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT
68335. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK
68336. BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT
68337. BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
68338. BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
68339. BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
68340. BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
68341. BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
68342. BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
68343. BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
68344. BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
68345. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
68346. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
68347. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
68348. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
68349. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
68350. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
68351. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
68352. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
68353. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
68354. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
68355. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
68356. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
68357. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
68358. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
68359. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
68360. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
68361. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
68362. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
68363. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
68364. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
68365. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
68366. BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
68367. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
68368. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
68369. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
68370. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
68371. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
68372. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
68373. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
68374. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
68375. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
68376. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
68377. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
68378. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
68379. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
68380. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
68381. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
68382. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
68383. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
68384. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
68385. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
68386. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
68387. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
68388. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
68389. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
68390. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
68391. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
68392. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
68393. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
68394. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
68395. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
68396. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
68397. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
68398. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
68399. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
68400. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
68401. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
68402. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
68403. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
68404. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
68405. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
68406. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
68407. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
68408. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
68409. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
68410. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
68411. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
68412. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
68413. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
68414. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
68415. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
68416. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
68417. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
68418. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
68419. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
68420. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
68421. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
68422. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
68423. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
68424. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
68425. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
68426. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
68427. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
68428. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
68429. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
68430. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
68431. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
68432. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
68433. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
68434. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
68435. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
68436. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
68437. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
68438. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
68439. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
68440. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
68441. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
68442. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
68443. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
68444. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
68445. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
68446. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
68447. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
68448. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
68449. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
68450. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
68451. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
68452. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
68453. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
68454. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
68455. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
68456. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
68457. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
68458. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
68459. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
68460. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
68461. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
68462. BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
68463. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
68464. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
68465. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
68466. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
68467. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
68468. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
68469. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
68470. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
68471. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
68472. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
68473. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
68474. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
68475. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
68476. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
68477. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
68478. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
68479. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
68480. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
68481. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
68482. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
68483. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
68484. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
68485. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
68486. BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
68487. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
68488. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
68489. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
68490. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
68491. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
68492. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
68493. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
68494. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
68495. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
68496. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
68497. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
68498. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
68499. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
68500. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
68501. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
68502. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
68503. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
68504. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
68505. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
68506. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
68507. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
68508. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
68509. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
68510. BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
68511. BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
68512. BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
68513. BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
68514. BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
68515. BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
68516. BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
68517. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
68518. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
68519. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
68520. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
68521. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK
68522. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT
68523. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK
68524. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT
68525. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK
68526. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT
68527. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
68528. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
68529. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
68530. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
68531. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
68532. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
68533. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK
68534. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT
68535. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK
68536. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT
68537. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK
68538. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT
68539. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK
68540. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT
68541. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK
68542. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT
68543. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK
68544. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT
68545. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK
68546. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT
68547. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK
68548. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT
68549. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK
68550. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT
68551. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK
68552. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT
68553. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK
68554. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT
68555. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK
68556. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT
68557. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK
68558. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT
68559. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK
68560. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT
68561. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK
68562. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT
68563. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK
68564. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT
68565. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK
68566. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT
68567. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK
68568. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT
68569. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK
68570. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT
68571. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK
68572. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT
68573. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK
68574. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT
68575. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK
68576. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT
68577. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK
68578. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT
68579. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK
68580. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT
68581. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK
68582. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT
68583. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK
68584. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT
68585. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK
68586. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT
68587. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK
68588. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT
68589. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK
68590. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT
68591. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK
68592. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT
68593. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK
68594. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT
68595. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK
68596. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT
68597. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK
68598. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT
68599. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK
68600. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT
68601. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK
68602. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT
68603. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK
68604. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT
68605. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK
68606. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT
68607. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK
68608. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT
68609. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK
68610. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT
68611. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK
68612. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT
68613. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK
68614. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT
68615. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK
68616. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT
68617. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK
68618. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT
68619. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK
68620. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT
68621. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK
68622. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT
68623. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK
68624. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT
68625. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK
68626. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT
68627. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK
68628. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT
68629. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK
68630. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT
68631. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK
68632. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT
68633. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK
68634. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT
68635. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK
68636. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT
68637. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK
68638. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT
68639. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK
68640. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT
68641. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK
68642. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT
68643. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK
68644. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT
68645. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK
68646. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT
68647. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK
68648. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT
68649. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK
68650. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT
68651. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK
68652. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT
68653. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK
68654. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT
68655. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK
68656. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT
68657. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK
68658. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT
68659. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK
68660. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT
68661. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK
68662. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT
68663. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK
68664. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT
68665. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK
68666. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT
68667. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK
68668. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT
68669. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK
68670. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT
68671. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK
68672. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT
68673. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK
68674. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT
68675. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK
68676. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT
68677. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK
68678. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT
68679. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK
68680. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT
68681. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK
68682. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT
68683. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK
68684. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT
68685. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK
68686. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT
68687. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK
68688. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT
68689. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK
68690. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT
68691. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK
68692. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT
68693. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK
68694. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT
68695. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK
68696. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT
68697. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK
68698. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT
68699. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK
68700. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT
68701. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK
68702. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT
68703. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK
68704. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT
68705. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK
68706. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT
68707. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK
68708. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT
68709. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK
68710. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT
68711. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK
68712. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT
68713. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK
68714. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT
68715. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK
68716. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT
68717. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK
68718. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT
68719. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK
68720. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT
68721. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK
68722. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT
68723. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK
68724. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT
68725. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK
68726. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT
68727. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK
68728. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT
68729. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK
68730. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT
68731. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK
68732. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT
68733. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK
68734. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT
68735. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK
68736. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
68737. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK
68738. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
68739. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK
68740. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT
68741. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK
68742. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT
68743. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK
68744. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT
68745. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK
68746. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT
68747. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK
68748. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
68749. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK
68750. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
68751. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK
68752. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT
68753. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK
68754. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT
68755. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK
68756. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
68757. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK
68758. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
68759. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK
68760. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT
68761. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK
68762. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT
68763. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK
68764. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
68765. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK
68766. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
68767. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK
68768. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT
68769. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK
68770. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT
68771. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK
68772. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT
68773. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK
68774. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT
68775. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK
68776. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT
68777. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK
68778. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT
68779. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK
68780. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT
68781. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK
68782. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT
68783. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK
68784. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT
68785. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK
68786. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT
68787. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK
68788. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT
68789. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK
68790. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT
68791. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK
68792. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT
68793. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK
68794. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT
68795. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK
68796. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT
68797. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK
68798. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT
68799. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK
68800. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT
68801. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK
68802. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT
68803. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK
68804. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT
68805. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK
68806. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT
68807. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK
68808. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT
68809. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK
68810. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT
68811. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK
68812. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT
68813. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK
68814. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT
68815. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK
68816. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT
68817. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK
68818. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT
68819. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK
68820. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT
68821. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK
68822. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT
68823. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK
68824. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT
68825. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK
68826. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT
68827. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK
68828. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT
68829. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK
68830. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT
68831. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK
68832. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT
68833. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK
68834. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT
68835. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK
68836. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT
68837. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK
68838. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT
68839. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK
68840. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT
68841. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK
68842. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT
68843. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK
68844. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT
68845. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK
68846. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT
68847. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK
68848. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT
68849. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK
68850. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT
68851. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK
68852. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT
68853. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK
68854. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT
68855. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK
68856. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT
68857. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK
68858. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT
68859. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK
68860. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT
68861. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK
68862. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT
68863. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK
68864. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT
68865. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK
68866. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT
68867. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK
68868. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT
68869. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK
68870. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT
68871. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK
68872. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT
68873. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK
68874. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT
68875. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK
68876. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT
68877. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK
68878. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT
68879. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK
68880. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT
68881. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK
68882. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT
68883. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK
68884. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT
68885. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK
68886. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT
68887. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK
68888. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT
68889. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK
68890. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT
68891. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK
68892. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT
68893. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK
68894. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT
68895. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK
68896. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT
68897. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK
68898. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT
68899. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK
68900. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT
68901. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK
68902. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT
68903. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK
68904. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT
68905. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK
68906. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT
68907. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK
68908. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT
68909. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK
68910. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT
68911. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK
68912. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT
68913. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK
68914. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT
68915. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK
68916. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT
68917. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK
68918. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT
68919. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK
68920. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT
68921. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK
68922. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT
68923. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK
68924. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT
68925. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK
68926. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT
68927. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK
68928. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT
68929. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK
68930. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT
68931. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK
68932. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT
68933. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK
68934. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT
68935. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK
68936. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT
68937. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK
68938. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT
68939. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK
68940. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT
68941. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK
68942. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT
68943. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK
68944. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT
68945. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK
68946. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT
68947. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK
68948. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT
68949. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK
68950. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT
68951. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK
68952. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT
68953. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK
68954. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT
68955. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK
68956. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT
68957. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK
68958. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT
68959. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK
68960. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT
68961. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK
68962. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT
68963. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK
68964. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT
68965. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK
68966. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT
68967. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK
68968. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT
68969. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK
68970. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT
68971. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK
68972. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT
68973. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK
68974. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT
68975. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK
68976. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT
68977. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
68978. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
68979. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
68980. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
68981. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
68982. BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
68983. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK
68984. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
68985. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK
68986. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT
68987. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK
68988. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT
68989. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK
68990. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT
68991. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK
68992. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
68993. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK
68994. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT
68995. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK
68996. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT
68997. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK
68998. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT
68999. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK
69000. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
69001. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK
69002. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT
69003. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK
69004. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT
69005. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK
69006. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT
69007. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK
69008. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
69009. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK
69010. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT
69011. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK
69012. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT
69013. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK
69014. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT
69015. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK
69016. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
69017. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK
69018. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT
69019. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK
69020. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT
69021. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK
69022. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT
69023. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK
69024. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
69025. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK
69026. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT
69027. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK
69028. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT
69029. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK
69030. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT
69031. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK
69032. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
69033. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK
69034. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
69035. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
69036. BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
69037. BIF_CFG_DEV0_EPF0_0_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
69038. BIF_CFG_DEV0_EPF0_0_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
69039. BIF_CFG_DEV0_EPF0_0_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
69040. BIF_CFG_DEV0_EPF0_0_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
69041. BIF_CFG_DEV0_EPF0_0_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
69042. BIF_CFG_DEV0_EPF0_0_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
69043. BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK
69044. BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT
69045. BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK
69046. BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
69047. BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK
69048. BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT
69049. BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK
69050. BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT
69051. BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK
69052. BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT
69053. BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
69054. BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
69055. BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
69056. BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
69057. BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK
69058. BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT
69059. BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK
69060. BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT
69061. BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK
69062. BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT
69063. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
69064. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
69065. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
69066. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
69067. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
69068. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
69069. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
69070. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
69071. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
69072. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
69073. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK
69074. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT
69075. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK
69076. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
69077. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK
69078. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
69079. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK
69080. BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
69081. BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK
69082. BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
69083. BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK
69084. BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT
69085. BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK
69086. BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT
69087. BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK
69088. BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
69089. BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK
69090. BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT
69091. BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK
69092. BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT
69093. BIF_CFG_DEV0_EPF0_0_SLOT_CAP2__RESERVED_MASK
69094. BIF_CFG_DEV0_EPF0_0_SLOT_CAP2__RESERVED__SHIFT
69095. BIF_CFG_DEV0_EPF0_0_SLOT_CNTL2__RESERVED_MASK
69096. BIF_CFG_DEV0_EPF0_0_SLOT_CNTL2__RESERVED__SHIFT
69097. BIF_CFG_DEV0_EPF0_0_SLOT_STATUS2__RESERVED_MASK
69098. BIF_CFG_DEV0_EPF0_0_SLOT_STATUS2__RESERVED__SHIFT
69099. BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK
69100. BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT
69101. BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK
69102. BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT
69103. BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK
69104. BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT
69105. BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK
69106. BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT
69107. BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK
69108. BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT
69109. BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
69110. BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
69111. BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK
69112. BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
69113. BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK
69114. BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT
69115. BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_EN_MASK
69116. BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_EN__SHIFT
69117. BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK
69118. BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
69119. BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK
69120. BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
69121. BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
69122. BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
69123. BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK
69124. BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
69125. BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK
69126. BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT
69127. BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK
69128. BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT
69129. BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK
69130. BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT
69131. BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK
69132. BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
69133. BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK
69134. BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT
69135. BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
69136. BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
69137. BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
69138. BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
69139. BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
69140. BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
69141. BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
69142. BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
69143. BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK
69144. BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT
69145. BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK
69146. BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT
69147. BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK
69148. BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT
69149. BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK
69150. BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT
69151. BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK
69152. BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT
69153. BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK
69154. BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT
69155. BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS_MASK
69156. BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT
69157. BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP_MASK
69158. BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP__SHIFT
69159. BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP_MASK
69160. BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP__SHIFT
69161. BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT_MASK
69162. BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT__SHIFT
69163. BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
69164. BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
69165. BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR_MASK
69166. BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR__SHIFT
69167. BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
69168. BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
69169. BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING_MASK
69170. BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING__SHIFT
69171. BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN_MASK
69172. BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT
69173. BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN_MASK
69174. BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT
69175. BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS_MASK
69176. BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS__SHIFT
69177. BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN_MASK
69178. BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT
69179. BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK
69180. BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT
69181. BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
69182. BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
69183. BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK
69184. BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT
69185. BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
69186. BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
69187. BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN_MASK
69188. BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN__SHIFT
69189. BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK
69190. BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
69191. BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK
69192. BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT
69193. BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK
69194. BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT
69195. BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK
69196. BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK
69197. BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT
69198. BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT
69199. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
69200. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
69201. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
69202. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
69203. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
69204. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
69205. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
69206. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
69207. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
69208. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
69209. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
69210. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
69211. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
69212. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
69213. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
69214. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
69215. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
69216. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
69217. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
69218. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
69219. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
69220. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
69221. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
69222. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
69223. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
69224. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
69225. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
69226. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
69227. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
69228. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
69229. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
69230. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
69231. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
69232. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
69233. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
69234. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
69235. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
69236. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
69237. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
69238. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
69239. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
69240. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
69241. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
69242. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
69243. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK
69244. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
69245. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK
69246. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
69247. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
69248. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
69249. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
69250. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
69251. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
69252. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
69253. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK
69254. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
69255. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
69256. BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
69257. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
69258. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
69259. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
69260. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
69261. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
69262. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
69263. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
69264. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
69265. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
69266. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
69267. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
69268. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
69269. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
69270. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
69271. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
69272. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
69273. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
69274. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
69275. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK
69276. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT
69277. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK
69278. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT
69279. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
69280. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
69281. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
69282. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
69283. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK
69284. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
69285. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
69286. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
69287. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
69288. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
69289. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK
69290. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
69291. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
69292. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
69293. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
69294. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
69295. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
69296. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
69297. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
69298. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
69299. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
69300. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
69301. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
69302. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
69303. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK
69304. BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
69305. BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID_MASK
69306. BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT
69307. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED_MASK
69308. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT
69309. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK
69310. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT
69311. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK
69312. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT
69313. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
69314. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
69315. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK
69316. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT
69317. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
69318. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
69319. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
69320. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
69321. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK
69322. BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT
69323. BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE_MASK
69324. BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE__SHIFT
69325. BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE_MASK
69326. BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE__SHIFT
69327. BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
69328. BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
69329. BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
69330. BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
69331. BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK
69332. BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT
69333. BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK
69334. BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT
69335. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK
69336. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT
69337. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK
69338. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT
69339. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK
69340. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT
69341. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK
69342. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT
69343. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK
69344. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT
69345. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK
69346. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT
69347. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK
69348. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT
69349. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK
69350. BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT
69351. BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK
69352. BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT
69353. BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK
69354. BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT
69355. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK
69356. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT
69357. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK
69358. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT
69359. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK
69360. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT
69361. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK
69362. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT
69363. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK
69364. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT
69365. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK
69366. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT
69367. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK
69368. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT
69369. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK
69370. BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT
69371. BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK
69372. BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT
69373. BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK
69374. BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT
69375. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK
69376. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT
69377. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK
69378. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT
69379. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK
69380. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT
69381. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK
69382. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT
69383. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK
69384. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT
69385. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK
69386. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT
69387. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK
69388. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT
69389. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK
69390. BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT
69391. BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK
69392. BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT
69393. BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK
69394. BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT
69395. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK
69396. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT
69397. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK
69398. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT
69399. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK
69400. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT
69401. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK
69402. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT
69403. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK
69404. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT
69405. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK
69406. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT
69407. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK
69408. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT
69409. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK
69410. BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT
69411. BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK
69412. BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT
69413. BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK
69414. BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT
69415. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK
69416. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT
69417. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK
69418. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT
69419. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK
69420. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT
69421. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK
69422. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT
69423. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK
69424. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT
69425. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK
69426. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT
69427. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK
69428. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT
69429. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK
69430. BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT
69431. BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK
69432. BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT
69433. BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK
69434. BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT
69435. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK
69436. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT
69437. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK
69438. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT
69439. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK
69440. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT
69441. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK
69442. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT
69443. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK
69444. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT
69445. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK
69446. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT
69447. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK
69448. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT
69449. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK
69450. BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT
69451. BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK
69452. BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT
69453. BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK
69454. BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT
69455. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK
69456. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT
69457. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK
69458. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT
69459. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK
69460. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT
69461. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK
69462. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT
69463. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK
69464. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT
69465. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK
69466. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT
69467. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK
69468. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT
69469. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK
69470. BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT
69471. BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK
69472. BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT
69473. BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK
69474. BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT
69475. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK
69476. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT
69477. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK
69478. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT
69479. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK
69480. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT
69481. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK
69482. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT
69483. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK
69484. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT
69485. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK
69486. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT
69487. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK
69488. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT
69489. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK
69490. BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT
69491. BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK
69492. BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT
69493. BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK
69494. BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT
69495. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK
69496. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT
69497. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK
69498. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT
69499. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK
69500. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT
69501. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK
69502. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT
69503. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK
69504. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT
69505. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK
69506. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT
69507. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK
69508. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT
69509. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK
69510. BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT
69511. BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK
69512. BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT
69513. BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK
69514. BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT
69515. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK
69516. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT
69517. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK
69518. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT
69519. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK
69520. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT
69521. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK
69522. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT
69523. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK
69524. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT
69525. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK
69526. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT
69527. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK
69528. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT
69529. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK
69530. BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT
69531. BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK
69532. BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT
69533. BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK
69534. BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT
69535. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK
69536. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT
69537. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK
69538. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT
69539. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK
69540. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT
69541. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK
69542. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT
69543. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK
69544. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT
69545. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK
69546. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT
69547. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK
69548. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT
69549. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK
69550. BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT
69551. BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK
69552. BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT
69553. BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK
69554. BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT
69555. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK
69556. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT
69557. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK
69558. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT
69559. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK
69560. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT
69561. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK
69562. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT
69563. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK
69564. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT
69565. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK
69566. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT
69567. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK
69568. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT
69569. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK
69570. BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT
69571. BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK
69572. BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT
69573. BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK
69574. BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT
69575. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK
69576. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT
69577. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK
69578. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT
69579. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK
69580. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT
69581. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK
69582. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT
69583. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK
69584. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT
69585. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK
69586. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT
69587. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK
69588. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT
69589. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK
69590. BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT
69591. BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK
69592. BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT
69593. BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK
69594. BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT
69595. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK
69596. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT
69597. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK
69598. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT
69599. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK
69600. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT
69601. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK
69602. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT
69603. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK
69604. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT
69605. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK
69606. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT
69607. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK
69608. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT
69609. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK
69610. BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT
69611. BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK
69612. BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT
69613. BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK
69614. BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT
69615. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK
69616. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT
69617. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK
69618. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT
69619. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK
69620. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT
69621. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK
69622. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT
69623. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK
69624. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT
69625. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK
69626. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT
69627. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK
69628. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT
69629. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK
69630. BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT
69631. BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK
69632. BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT
69633. BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK
69634. BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT
69635. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK
69636. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT
69637. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK
69638. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT
69639. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK
69640. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT
69641. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK
69642. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT
69643. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK
69644. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT
69645. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK
69646. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT
69647. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK
69648. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT
69649. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK
69650. BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT
69651. BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER_MASK
69652. BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT
69653. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
69654. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
69655. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
69656. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
69657. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
69658. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
69659. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
69660. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
69661. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RESERVED_MASK
69662. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RESERVED__SHIFT
69663. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
69664. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
69665. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
69666. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
69667. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
69668. BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
69669. BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED_MASK
69670. BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED__SHIFT
69671. BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
69672. BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
69673. BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
69674. BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
69675. BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
69676. BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
69677. BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
69678. BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
69679. BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK
69680. BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
69681. BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
69682. BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
69683. BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED_MASK
69684. BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT
69685. BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH_MASK
69686. BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT
69687. BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT_MASK
69688. BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT
69689. BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER_MASK
69690. BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT
69691. BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
69692. BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
69693. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
69694. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
69695. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
69696. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
69697. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
69698. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
69699. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
69700. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
69701. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
69702. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
69703. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
69704. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
69705. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
69706. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
69707. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK
69708. BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
69709. BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED_MASK
69710. BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED__SHIFT
69711. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
69712. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
69713. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
69714. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
69715. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
69716. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
69717. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK
69718. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
69719. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
69720. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
69721. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
69722. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
69723. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
69724. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
69725. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS_MASK
69726. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT
69727. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL_MASK
69728. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT
69729. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
69730. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
69731. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK
69732. BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT
69733. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
69734. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
69735. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
69736. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
69737. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
69738. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
69739. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
69740. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
69741. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
69742. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
69743. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
69744. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
69745. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
69746. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
69747. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
69748. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
69749. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
69750. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
69751. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
69752. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
69753. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
69754. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
69755. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
69756. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
69757. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
69758. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
69759. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
69760. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
69761. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
69762. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
69763. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
69764. BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
69765. BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK
69766. BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT
69767. BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK
69768. BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT
69769. BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK
69770. BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT
69771. BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK
69772. BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT
69773. BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK
69774. BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT
69775. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
69776. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
69777. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK
69778. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT
69779. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
69780. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
69781. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
69782. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
69783. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK
69784. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT
69785. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
69786. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
69787. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
69788. BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
69789. BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK
69790. BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT
69791. BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK
69792. BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT
69793. BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK
69794. BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT
69795. BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK
69796. BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT
69797. BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT_MASK
69798. BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT
69799. BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT_MASK
69800. BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT
69801. BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK
69802. BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT
69803. BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK
69804. BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
69805. BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK
69806. BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
69807. BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
69808. BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
69809. BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
69810. BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
69811. BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK
69812. BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
69813. BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
69814. BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
69815. BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
69816. BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
69817. BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
69818. BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
69819. BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK
69820. BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT
69821. BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK
69822. BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
69823. BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK
69824. BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT
69825. BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK_MASK
69826. BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK__SHIFT
69827. BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
69828. BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
69829. BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
69830. BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
69831. BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK
69832. BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
69833. BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK
69834. BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT
69835. BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
69836. BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
69837. BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
69838. BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
69839. BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
69840. BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
69841. BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
69842. BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
69843. BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK
69844. BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT
69845. BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK
69846. BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
69847. BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING_MASK
69848. BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT
69849. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
69850. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
69851. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
69852. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
69853. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
69854. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
69855. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
69856. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
69857. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
69858. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
69859. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
69860. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
69861. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
69862. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
69863. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
69864. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
69865. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
69866. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
69867. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
69868. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
69869. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
69870. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
69871. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
69872. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
69873. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
69874. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
69875. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
69876. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
69877. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
69878. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
69879. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
69880. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
69881. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
69882. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
69883. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
69884. BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
69885. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
69886. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
69887. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
69888. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
69889. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
69890. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
69891. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
69892. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
69893. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
69894. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
69895. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
69896. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
69897. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
69898. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
69899. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
69900. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
69901. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
69902. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
69903. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
69904. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
69905. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
69906. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
69907. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
69908. BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
69909. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
69910. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
69911. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
69912. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
69913. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
69914. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
69915. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
69916. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
69917. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
69918. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
69919. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
69920. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
69921. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
69922. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
69923. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
69924. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
69925. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
69926. BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
69927. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
69928. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
69929. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
69930. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
69931. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
69932. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
69933. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
69934. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
69935. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU_MASK
69936. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU__SHIFT
69937. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
69938. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
69939. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
69940. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
69941. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
69942. BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
69943. BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
69944. BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
69945. BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK
69946. BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
69947. BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK
69948. BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
69949. BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
69950. BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
69951. BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
69952. BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
69953. BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK
69954. BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
69955. BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK
69956. BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
69957. BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
69958. BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
69959. BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
69960. BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
69961. BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK
69962. BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
69963. BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK
69964. BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
69965. BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
69966. BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
69967. BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
69968. BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
69969. BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK
69970. BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
69971. BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK
69972. BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
69973. BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
69974. BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
69975. BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
69976. BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
69977. BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK
69978. BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
69979. BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK
69980. BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
69981. BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
69982. BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
69983. BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
69984. BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
69985. BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK
69986. BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
69987. BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK
69988. BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
69989. BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
69990. BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
69991. BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
69992. BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
69993. BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
69994. BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
69995. BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
69996. BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
69997. BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK
69998. BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT
69999. BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK
70000. BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
70001. BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK
70002. BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT
70003. BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
70004. BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
70005. BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
70006. BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
70007. BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION_MASK
70008. BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION__SHIFT
70009. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
70010. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
70011. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
70012. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
70013. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
70014. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
70015. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
70016. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
70017. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
70018. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
70019. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
70020. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
70021. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
70022. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
70023. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
70024. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
70025. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
70026. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
70027. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
70028. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
70029. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
70030. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
70031. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
70032. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
70033. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
70034. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
70035. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
70036. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
70037. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
70038. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
70039. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
70040. BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
70041. BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
70042. BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
70043. BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
70044. BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
70045. BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
70046. BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
70047. BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
70048. BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
70049. BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
70050. BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
70051. BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK
70052. BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT
70053. BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK
70054. BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT
70055. BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK
70056. BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT
70057. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
70058. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
70059. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
70060. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
70061. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
70062. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
70063. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
70064. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
70065. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
70066. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
70067. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
70068. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
70069. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
70070. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
70071. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
70072. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
70073. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
70074. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
70075. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
70076. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
70077. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
70078. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
70079. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
70080. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
70081. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
70082. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
70083. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
70084. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
70085. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
70086. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
70087. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
70088. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
70089. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
70090. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
70091. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
70092. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
70093. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
70094. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
70095. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
70096. BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
70097. BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK
70098. BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
70099. BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK
70100. BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
70101. BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK
70102. BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
70103. BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK
70104. BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
70105. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70106. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70107. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70108. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70109. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
70110. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
70111. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70112. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70113. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70114. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70115. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70116. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70117. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70118. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70119. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
70120. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
70121. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70122. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70123. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70124. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70125. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70126. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70127. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70128. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70129. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
70130. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
70131. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70132. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70133. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70134. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70135. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70136. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70137. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70138. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70139. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
70140. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
70141. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70142. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70143. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70144. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70145. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70146. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70147. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70148. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70149. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
70150. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
70151. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70152. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70153. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70154. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70155. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70156. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70157. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70158. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70159. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
70160. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
70161. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70162. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70163. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70164. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70165. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70166. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70167. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70168. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70169. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
70170. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
70171. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70172. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70173. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70174. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70175. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70176. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70177. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70178. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70179. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
70180. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
70181. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70182. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70183. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70184. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70185. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70186. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70187. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70188. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70189. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
70190. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
70191. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70192. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70193. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70194. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70195. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70196. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70197. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70198. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70199. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
70200. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
70201. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70202. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70203. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70204. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70205. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70206. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70207. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70208. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70209. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
70210. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
70211. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70212. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70213. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70214. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70215. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70216. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70217. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70218. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70219. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
70220. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
70221. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70222. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70223. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70224. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70225. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70226. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70227. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70228. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70229. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
70230. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
70231. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70232. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70233. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70234. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70235. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70236. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70237. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70238. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70239. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
70240. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
70241. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70242. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70243. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70244. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70245. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70246. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70247. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70248. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70249. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
70250. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
70251. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70252. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70253. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70254. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70255. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
70256. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
70257. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
70258. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
70259. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
70260. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
70261. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
70262. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
70263. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
70264. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
70265. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
70266. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
70267. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
70268. BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
70269. BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
70270. BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
70271. BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
70272. BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
70273. BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
70274. BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
70275. BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__RESERVED_MASK
70276. BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__RESERVED__SHIFT
70277. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
70278. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
70279. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
70280. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
70281. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
70282. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
70283. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
70284. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
70285. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
70286. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
70287. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
70288. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
70289. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
70290. BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
70291. BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
70292. BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
70293. BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
70294. BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
70295. BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
70296. BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
70297. BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
70298. BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
70299. BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
70300. BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
70301. BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
70302. BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
70303. BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
70304. BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
70305. BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
70306. BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
70307. BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
70308. BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
70309. BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
70310. BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
70311. BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
70312. BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
70313. BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK
70314. BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
70315. BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK
70316. BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT
70317. BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE_MASK
70318. BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT
70319. BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
70320. BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
70321. BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
70322. BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
70323. BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
70324. BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
70325. BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
70326. BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
70327. BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
70328. BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
70329. BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
70330. BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
70331. BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK
70332. BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT
70333. BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK
70334. BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT
70335. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK
70336. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT
70337. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK
70338. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT
70339. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK
70340. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT
70341. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK
70342. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT
70343. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK
70344. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT
70345. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK
70346. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT
70347. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK
70348. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT
70349. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK
70350. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT
70351. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK
70352. BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT
70353. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
70354. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
70355. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
70356. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
70357. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
70358. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
70359. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK
70360. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
70361. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
70362. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
70363. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
70364. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
70365. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
70366. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
70367. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
70368. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
70369. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
70370. BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
70371. BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
70372. BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
70373. BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
70374. BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
70375. BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
70376. BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
70377. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
70378. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
70379. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
70380. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
70381. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
70382. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
70383. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
70384. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
70385. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
70386. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
70387. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
70388. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
70389. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
70390. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
70391. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
70392. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
70393. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
70394. BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
70395. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
70396. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
70397. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
70398. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
70399. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
70400. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
70401. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
70402. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
70403. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
70404. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
70405. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
70406. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
70407. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
70408. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
70409. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK
70410. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
70411. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
70412. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
70413. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
70414. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
70415. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
70416. BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
70417. BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
70418. BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
70419. BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
70420. BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
70421. BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
70422. BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
70423. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK
70424. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT
70425. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK
70426. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT
70427. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK
70428. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT
70429. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
70430. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
70431. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK
70432. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT
70433. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK
70434. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT
70435. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK
70436. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT
70437. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK
70438. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT
70439. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK
70440. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT
70441. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK
70442. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
70443. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK
70444. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT
70445. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK
70446. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT
70447. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK
70448. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT
70449. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK
70450. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT
70451. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK
70452. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT
70453. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK
70454. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT
70455. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK
70456. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT
70457. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK
70458. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT
70459. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK
70460. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT
70461. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK
70462. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT
70463. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK
70464. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT
70465. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK
70466. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT
70467. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK
70468. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT
70469. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK
70470. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT
70471. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK
70472. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT
70473. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK
70474. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT
70475. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK
70476. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT
70477. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK
70478. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT
70479. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK
70480. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT
70481. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK
70482. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT
70483. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK
70484. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT
70485. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK
70486. BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT
70487. BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
70488. BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
70489. BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
70490. BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
70491. BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
70492. BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
70493. BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
70494. BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
70495. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
70496. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
70497. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
70498. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
70499. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
70500. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
70501. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
70502. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
70503. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
70504. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
70505. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
70506. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
70507. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
70508. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
70509. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
70510. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
70511. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
70512. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
70513. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
70514. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
70515. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
70516. BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
70517. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
70518. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
70519. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
70520. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
70521. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
70522. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
70523. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
70524. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
70525. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
70526. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
70527. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
70528. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
70529. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
70530. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
70531. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
70532. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
70533. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
70534. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
70535. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
70536. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
70537. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
70538. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
70539. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
70540. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
70541. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
70542. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
70543. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
70544. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
70545. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
70546. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
70547. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
70548. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
70549. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
70550. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
70551. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
70552. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
70553. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
70554. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
70555. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
70556. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
70557. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
70558. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
70559. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
70560. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
70561. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
70562. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
70563. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
70564. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
70565. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
70566. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
70567. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
70568. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
70569. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
70570. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
70571. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
70572. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
70573. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
70574. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
70575. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
70576. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
70577. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
70578. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
70579. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
70580. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
70581. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
70582. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
70583. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
70584. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
70585. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
70586. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
70587. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
70588. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
70589. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
70590. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
70591. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
70592. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
70593. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
70594. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
70595. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
70596. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
70597. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
70598. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
70599. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
70600. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
70601. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
70602. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
70603. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
70604. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
70605. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
70606. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
70607. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
70608. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
70609. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
70610. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
70611. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
70612. BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
70613. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
70614. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
70615. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
70616. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
70617. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
70618. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
70619. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
70620. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
70621. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
70622. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
70623. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
70624. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
70625. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
70626. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
70627. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
70628. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
70629. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
70630. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
70631. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
70632. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
70633. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
70634. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
70635. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
70636. BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
70637. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
70638. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
70639. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
70640. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
70641. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
70642. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
70643. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
70644. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
70645. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
70646. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
70647. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
70648. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
70649. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
70650. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
70651. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
70652. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
70653. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
70654. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
70655. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
70656. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
70657. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
70658. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
70659. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
70660. BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
70661. BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
70662. BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
70663. BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
70664. BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
70665. BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
70666. BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
70667. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
70668. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
70669. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
70670. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
70671. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK
70672. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT
70673. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK
70674. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT
70675. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK
70676. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT
70677. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
70678. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
70679. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
70680. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
70681. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
70682. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
70683. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK
70684. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT
70685. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK
70686. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT
70687. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK
70688. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT
70689. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK
70690. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT
70691. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK
70692. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT
70693. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK
70694. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT
70695. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK
70696. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT
70697. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK
70698. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT
70699. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK
70700. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT
70701. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK
70702. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT
70703. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK
70704. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT
70705. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK
70706. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT
70707. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK
70708. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT
70709. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK
70710. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT
70711. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK
70712. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT
70713. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK
70714. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT
70715. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK
70716. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT
70717. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK
70718. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT
70719. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK
70720. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT
70721. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK
70722. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT
70723. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK
70724. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT
70725. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK
70726. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT
70727. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK
70728. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT
70729. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK
70730. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT
70731. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK
70732. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT
70733. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK
70734. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT
70735. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK
70736. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT
70737. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK
70738. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT
70739. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK
70740. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT
70741. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK
70742. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT
70743. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK
70744. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT
70745. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK
70746. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT
70747. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK
70748. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT
70749. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK
70750. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT
70751. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK
70752. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT
70753. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK
70754. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT
70755. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK
70756. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT
70757. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK
70758. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT
70759. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK
70760. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT
70761. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK
70762. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT
70763. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK
70764. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT
70765. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK
70766. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT
70767. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK
70768. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT
70769. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK
70770. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT
70771. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK
70772. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT
70773. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK
70774. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT
70775. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK
70776. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT
70777. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK
70778. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT
70779. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK
70780. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT
70781. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK
70782. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT
70783. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK
70784. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT
70785. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK
70786. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT
70787. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK
70788. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT
70789. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK
70790. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT
70791. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK
70792. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT
70793. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK
70794. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT
70795. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK
70796. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT
70797. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK
70798. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT
70799. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK
70800. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT
70801. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK
70802. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT
70803. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK
70804. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT
70805. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK
70806. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT
70807. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK
70808. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT
70809. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK
70810. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT
70811. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK
70812. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT
70813. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK
70814. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT
70815. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK
70816. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT
70817. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK
70818. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT
70819. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK
70820. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT
70821. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK
70822. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT
70823. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK
70824. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT
70825. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK
70826. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT
70827. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK
70828. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT
70829. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK
70830. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT
70831. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK
70832. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT
70833. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK
70834. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT
70835. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK
70836. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT
70837. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK
70838. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT
70839. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK
70840. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT
70841. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK
70842. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT
70843. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK
70844. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT
70845. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK
70846. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT
70847. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK
70848. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT
70849. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK
70850. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT
70851. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK
70852. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT
70853. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK
70854. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT
70855. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK
70856. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT
70857. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK
70858. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT
70859. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK
70860. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT
70861. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK
70862. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT
70863. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK
70864. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT
70865. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK
70866. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT
70867. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK
70868. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT
70869. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK
70870. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT
70871. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK
70872. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT
70873. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK
70874. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT
70875. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK
70876. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT
70877. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK
70878. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT
70879. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK
70880. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT
70881. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK
70882. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT
70883. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK
70884. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT
70885. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK
70886. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
70887. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK
70888. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
70889. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK
70890. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT
70891. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK
70892. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT
70893. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK
70894. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT
70895. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK
70896. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT
70897. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK
70898. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
70899. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK
70900. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
70901. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK
70902. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT
70903. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK
70904. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT
70905. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK
70906. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
70907. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK
70908. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
70909. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK
70910. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT
70911. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK
70912. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT
70913. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK
70914. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
70915. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK
70916. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
70917. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK
70918. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT
70919. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK
70920. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT
70921. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK
70922. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT
70923. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK
70924. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT
70925. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK
70926. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT
70927. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK
70928. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT
70929. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK
70930. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT
70931. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK
70932. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT
70933. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK
70934. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT
70935. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK
70936. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT
70937. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK
70938. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT
70939. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK
70940. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT
70941. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK
70942. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT
70943. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK
70944. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT
70945. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK
70946. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT
70947. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK
70948. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT
70949. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK
70950. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT
70951. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK
70952. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT
70953. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK
70954. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT
70955. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK
70956. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT
70957. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK
70958. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT
70959. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK
70960. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT
70961. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK
70962. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT
70963. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK
70964. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT
70965. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK
70966. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT
70967. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK
70968. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT
70969. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK
70970. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT
70971. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK
70972. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT
70973. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK
70974. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT
70975. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK
70976. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT
70977. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK
70978. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT
70979. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK
70980. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT
70981. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK
70982. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT
70983. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK
70984. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT
70985. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK
70986. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT
70987. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK
70988. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT
70989. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK
70990. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT
70991. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK
70992. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT
70993. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK
70994. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT
70995. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK
70996. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT
70997. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK
70998. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT
70999. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK
71000. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT
71001. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK
71002. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT
71003. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK
71004. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT
71005. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK
71006. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT
71007. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK
71008. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT
71009. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK
71010. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT
71011. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK
71012. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT
71013. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK
71014. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT
71015. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK
71016. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT
71017. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK
71018. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT
71019. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK
71020. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT
71021. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK
71022. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT
71023. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK
71024. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT
71025. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK
71026. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT
71027. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK
71028. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT
71029. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK
71030. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT
71031. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK
71032. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT
71033. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK
71034. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT
71035. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK
71036. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT
71037. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK
71038. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT
71039. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK
71040. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT
71041. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK
71042. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT
71043. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK
71044. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT
71045. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK
71046. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT
71047. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK
71048. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT
71049. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK
71050. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT
71051. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK
71052. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT
71053. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK
71054. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT
71055. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK
71056. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT
71057. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK
71058. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT
71059. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK
71060. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT
71061. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK
71062. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT
71063. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK
71064. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT
71065. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK
71066. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT
71067. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK
71068. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT
71069. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK
71070. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT
71071. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK
71072. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT
71073. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK
71074. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT
71075. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK
71076. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT
71077. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK
71078. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT
71079. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK
71080. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT
71081. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK
71082. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT
71083. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK
71084. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT
71085. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK
71086. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT
71087. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK
71088. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT
71089. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK
71090. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT
71091. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK
71092. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT
71093. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK
71094. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT
71095. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK
71096. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT
71097. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK
71098. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT
71099. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK
71100. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT
71101. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK
71102. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT
71103. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK
71104. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT
71105. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK
71106. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT
71107. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK
71108. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT
71109. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK
71110. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT
71111. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK
71112. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT
71113. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK
71114. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT
71115. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK
71116. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT
71117. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK
71118. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT
71119. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK
71120. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT
71121. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK
71122. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT
71123. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK
71124. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT
71125. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK
71126. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT
71127. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
71128. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
71129. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
71130. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
71131. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
71132. BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
71133. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK
71134. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
71135. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK
71136. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT
71137. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK
71138. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT
71139. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK
71140. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT
71141. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK
71142. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
71143. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK
71144. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT
71145. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK
71146. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT
71147. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK
71148. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT
71149. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK
71150. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
71151. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK
71152. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT
71153. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK
71154. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT
71155. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK
71156. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT
71157. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK
71158. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
71159. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK
71160. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT
71161. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK
71162. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT
71163. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK
71164. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT
71165. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK
71166. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
71167. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK
71168. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT
71169. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK
71170. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT
71171. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK
71172. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT
71173. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK
71174. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
71175. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK
71176. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT
71177. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK
71178. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT
71179. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK
71180. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT
71181. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK
71182. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
71183. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK
71184. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
71185. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
71186. BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
71187. BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK
71188. BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT
71189. BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK
71190. BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
71191. BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT_MASK
71192. BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT
71193. BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT_MASK
71194. BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT
71195. BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT_MASK
71196. BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT
71197. BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
71198. BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
71199. BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
71200. BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
71201. BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK_MASK
71202. BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT
71203. BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT_MASK
71204. BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT
71205. BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION_MASK
71206. BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION__SHIFT
71207. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
71208. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
71209. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
71210. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
71211. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
71212. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
71213. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
71214. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
71215. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
71216. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
71217. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK
71218. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT
71219. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK
71220. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
71221. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK
71222. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
71223. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK
71224. BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
71225. BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK
71226. BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
71227. BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK
71228. BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT
71229. BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK
71230. BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT
71231. BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK
71232. BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
71233. BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK
71234. BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT
71235. BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK
71236. BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT
71237. BIF_CFG_DEV0_EPF0_1_SLOT_CAP2__RESERVED_MASK
71238. BIF_CFG_DEV0_EPF0_1_SLOT_CAP2__RESERVED__SHIFT
71239. BIF_CFG_DEV0_EPF0_1_SLOT_CNTL2__RESERVED_MASK
71240. BIF_CFG_DEV0_EPF0_1_SLOT_CNTL2__RESERVED__SHIFT
71241. BIF_CFG_DEV0_EPF0_1_SLOT_STATUS2__RESERVED_MASK
71242. BIF_CFG_DEV0_EPF0_1_SLOT_STATUS2__RESERVED__SHIFT
71243. BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST_MASK
71244. BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST__SHIFT
71245. BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING_MASK
71246. BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT
71247. BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK
71248. BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT
71249. BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS_MASK
71250. BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS__SHIFT
71251. BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS_MASK
71252. BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS__SHIFT
71253. BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
71254. BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
71255. BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK
71256. BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
71257. BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP_MASK
71258. BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP__SHIFT
71259. BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_EN_MASK
71260. BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_EN__SHIFT
71261. BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK
71262. BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
71263. BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK
71264. BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
71265. BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
71266. BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
71267. BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK
71268. BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
71269. BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS_MASK
71270. BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT
71271. BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK
71272. BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT
71273. BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK
71274. BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT
71275. BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK
71276. BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
71277. BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID_MASK
71278. BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT
71279. BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
71280. BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
71281. BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
71282. BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
71283. BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID_MASK
71284. BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
71285. BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
71286. BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
71287. BIF_CFG_DEV0_EPF0_2_BASE_ADDR_1__BASE_ADDR_MASK
71288. BIF_CFG_DEV0_EPF0_2_BASE_ADDR_1__BASE_ADDR__SHIFT
71289. BIF_CFG_DEV0_EPF0_2_BASE_ADDR_2__BASE_ADDR_MASK
71290. BIF_CFG_DEV0_EPF0_2_BASE_ADDR_2__BASE_ADDR__SHIFT
71291. BIF_CFG_DEV0_EPF0_2_BASE_ADDR_3__BASE_ADDR_MASK
71292. BIF_CFG_DEV0_EPF0_2_BASE_ADDR_3__BASE_ADDR__SHIFT
71293. BIF_CFG_DEV0_EPF0_2_BASE_ADDR_4__BASE_ADDR_MASK
71294. BIF_CFG_DEV0_EPF0_2_BASE_ADDR_4__BASE_ADDR__SHIFT
71295. BIF_CFG_DEV0_EPF0_2_BASE_ADDR_5__BASE_ADDR_MASK
71296. BIF_CFG_DEV0_EPF0_2_BASE_ADDR_5__BASE_ADDR__SHIFT
71297. BIF_CFG_DEV0_EPF0_2_BASE_ADDR_6__BASE_ADDR_MASK
71298. BIF_CFG_DEV0_EPF0_2_BASE_ADDR_6__BASE_ADDR__SHIFT
71299. BIF_CFG_DEV0_EPF0_2_BASE_CLASS__BASE_CLASS_MASK
71300. BIF_CFG_DEV0_EPF0_2_BASE_CLASS__BASE_CLASS__SHIFT
71301. BIF_CFG_DEV0_EPF0_2_BIST__BIST_CAP_MASK
71302. BIF_CFG_DEV0_EPF0_2_BIST__BIST_CAP__SHIFT
71303. BIF_CFG_DEV0_EPF0_2_BIST__BIST_COMP_MASK
71304. BIF_CFG_DEV0_EPF0_2_BIST__BIST_COMP__SHIFT
71305. BIF_CFG_DEV0_EPF0_2_BIST__BIST_STRT_MASK
71306. BIF_CFG_DEV0_EPF0_2_BIST__BIST_STRT__SHIFT
71307. BIF_CFG_DEV0_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
71308. BIF_CFG_DEV0_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
71309. BIF_CFG_DEV0_EPF0_2_CAP_PTR__CAP_PTR_MASK
71310. BIF_CFG_DEV0_EPF0_2_CAP_PTR__CAP_PTR__SHIFT
71311. BIF_CFG_DEV0_EPF0_2_COMMAND__AD_STEPPING_MASK
71312. BIF_CFG_DEV0_EPF0_2_COMMAND__AD_STEPPING__SHIFT
71313. BIF_CFG_DEV0_EPF0_2_COMMAND__BUS_MASTER_EN_MASK
71314. BIF_CFG_DEV0_EPF0_2_COMMAND__BUS_MASTER_EN__SHIFT
71315. BIF_CFG_DEV0_EPF0_2_COMMAND__FAST_B2B_EN_MASK
71316. BIF_CFG_DEV0_EPF0_2_COMMAND__FAST_B2B_EN__SHIFT
71317. BIF_CFG_DEV0_EPF0_2_COMMAND__INT_DIS_MASK
71318. BIF_CFG_DEV0_EPF0_2_COMMAND__INT_DIS__SHIFT
71319. BIF_CFG_DEV0_EPF0_2_COMMAND__IO_ACCESS_EN_MASK
71320. BIF_CFG_DEV0_EPF0_2_COMMAND__IO_ACCESS_EN__SHIFT
71321. BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_ACCESS_EN_MASK
71322. BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_ACCESS_EN__SHIFT
71323. BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
71324. BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
71325. BIF_CFG_DEV0_EPF0_2_COMMAND__PAL_SNOOP_EN_MASK
71326. BIF_CFG_DEV0_EPF0_2_COMMAND__PAL_SNOOP_EN__SHIFT
71327. BIF_CFG_DEV0_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
71328. BIF_CFG_DEV0_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
71329. BIF_CFG_DEV0_EPF0_2_COMMAND__SERR_EN_MASK
71330. BIF_CFG_DEV0_EPF0_2_COMMAND__SERR_EN__SHIFT
71331. BIF_CFG_DEV0_EPF0_2_COMMAND__SPECIAL_CYCLE_EN_MASK
71332. BIF_CFG_DEV0_EPF0_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
71333. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
71334. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
71335. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
71336. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
71337. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
71338. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
71339. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
71340. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
71341. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
71342. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
71343. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
71344. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
71345. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
71346. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
71347. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
71348. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
71349. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
71350. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
71351. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
71352. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
71353. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
71354. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
71355. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
71356. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
71357. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
71358. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
71359. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
71360. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
71361. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
71362. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
71363. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
71364. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
71365. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__EXTENDED_TAG_MASK
71366. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
71367. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__FLR_CAPABLE_MASK
71368. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
71369. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
71370. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
71371. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
71372. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
71373. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
71374. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
71375. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__PHANTOM_FUNC_MASK
71376. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
71377. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
71378. BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
71379. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
71380. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
71381. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
71382. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
71383. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
71384. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
71385. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
71386. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
71387. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
71388. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
71389. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
71390. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
71391. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
71392. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
71393. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
71394. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
71395. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__LTR_EN_MASK
71396. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__LTR_EN__SHIFT
71397. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__OBFF_EN_MASK
71398. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__OBFF_EN__SHIFT
71399. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
71400. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
71401. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__CORR_ERR_EN_MASK
71402. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
71403. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
71404. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
71405. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
71406. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
71407. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__INITIATE_FLR_MASK
71408. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__INITIATE_FLR__SHIFT
71409. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
71410. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
71411. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
71412. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
71413. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
71414. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
71415. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
71416. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
71417. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
71418. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
71419. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
71420. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
71421. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__USR_REPORT_EN_MASK
71422. BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
71423. BIF_CFG_DEV0_EPF0_2_DEVICE_ID__DEVICE_ID_MASK
71424. BIF_CFG_DEV0_EPF0_2_DEVICE_ID__DEVICE_ID__SHIFT
71425. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS2__RESERVED_MASK
71426. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS2__RESERVED__SHIFT
71427. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__AUX_PWR_MASK
71428. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__AUX_PWR__SHIFT
71429. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__CORR_ERR_MASK
71430. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__CORR_ERR__SHIFT
71431. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__FATAL_ERR_MASK
71432. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__FATAL_ERR__SHIFT
71433. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
71434. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
71435. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
71436. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
71437. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__USR_DETECTED_MASK
71438. BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__USR_DETECTED__SHIFT
71439. BIF_CFG_DEV0_EPF0_2_HEADER__DEVICE_TYPE_MASK
71440. BIF_CFG_DEV0_EPF0_2_HEADER__DEVICE_TYPE__SHIFT
71441. BIF_CFG_DEV0_EPF0_2_HEADER__HEADER_TYPE_MASK
71442. BIF_CFG_DEV0_EPF0_2_HEADER__HEADER_TYPE__SHIFT
71443. BIF_CFG_DEV0_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
71444. BIF_CFG_DEV0_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
71445. BIF_CFG_DEV0_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
71446. BIF_CFG_DEV0_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
71447. BIF_CFG_DEV0_EPF0_2_LATENCY__LATENCY_TIMER_MASK
71448. BIF_CFG_DEV0_EPF0_2_LATENCY__LATENCY_TIMER__SHIFT
71449. BIF_CFG_DEV0_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
71450. BIF_CFG_DEV0_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
71451. BIF_CFG_DEV0_EPF0_2_LINK_CAP2__RESERVED_MASK
71452. BIF_CFG_DEV0_EPF0_2_LINK_CAP2__RESERVED__SHIFT
71453. BIF_CFG_DEV0_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
71454. BIF_CFG_DEV0_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
71455. BIF_CFG_DEV0_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
71456. BIF_CFG_DEV0_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
71457. BIF_CFG_DEV0_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
71458. BIF_CFG_DEV0_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
71459. BIF_CFG_DEV0_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
71460. BIF_CFG_DEV0_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
71461. BIF_CFG_DEV0_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
71462. BIF_CFG_DEV0_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
71463. BIF_CFG_DEV0_EPF0_2_LINK_CAP__L1_EXIT_LATENCY_MASK
71464. BIF_CFG_DEV0_EPF0_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
71465. BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
71466. BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
71467. BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_SPEED_MASK
71468. BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_SPEED__SHIFT
71469. BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_WIDTH_MASK
71470. BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_WIDTH__SHIFT
71471. BIF_CFG_DEV0_EPF0_2_LINK_CAP__PM_SUPPORT_MASK
71472. BIF_CFG_DEV0_EPF0_2_LINK_CAP__PM_SUPPORT__SHIFT
71473. BIF_CFG_DEV0_EPF0_2_LINK_CAP__PORT_NUMBER_MASK
71474. BIF_CFG_DEV0_EPF0_2_LINK_CAP__PORT_NUMBER__SHIFT
71475. BIF_CFG_DEV0_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
71476. BIF_CFG_DEV0_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
71477. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
71478. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
71479. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
71480. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
71481. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
71482. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
71483. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
71484. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
71485. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
71486. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
71487. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
71488. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
71489. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
71490. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
71491. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__XMIT_MARGIN_MASK
71492. BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
71493. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
71494. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
71495. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
71496. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
71497. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__EXTENDED_SYNC_MASK
71498. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
71499. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
71500. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
71501. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
71502. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
71503. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
71504. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
71505. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_DIS_MASK
71506. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_DIS__SHIFT
71507. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__PM_CONTROL_MASK
71508. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__PM_CONTROL__SHIFT
71509. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
71510. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
71511. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__RETRAIN_LINK_MASK
71512. BIF_CFG_DEV0_EPF0_2_LINK_CNTL__RETRAIN_LINK__SHIFT
71513. BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
71514. BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
71515. BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
71516. BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
71517. BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
71518. BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
71519. BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
71520. BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
71521. BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
71522. BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
71523. BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
71524. BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
71525. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
71526. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
71527. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__DL_ACTIVE_MASK
71528. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__DL_ACTIVE__SHIFT
71529. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
71530. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
71531. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
71532. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
71533. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_TRAINING_MASK
71534. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_TRAINING__SHIFT
71535. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
71536. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
71537. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
71538. BIF_CFG_DEV0_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
71539. BIF_CFG_DEV0_EPF0_2_MAX_LATENCY__MAX_LAT_MASK
71540. BIF_CFG_DEV0_EPF0_2_MAX_LATENCY__MAX_LAT__SHIFT
71541. BIF_CFG_DEV0_EPF0_2_MIN_GRANT__MIN_GNT_MASK
71542. BIF_CFG_DEV0_EPF0_2_MIN_GRANT__MIN_GNT__SHIFT
71543. BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__CAP_ID_MASK
71544. BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__CAP_ID__SHIFT
71545. BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__NEXT_PTR_MASK
71546. BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT
71547. BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_EN_MASK
71548. BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT
71549. BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
71550. BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
71551. BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
71552. BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
71553. BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_BIR_MASK
71554. BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT
71555. BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK
71556. BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
71557. BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK
71558. BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
71559. BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
71560. BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
71561. BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__CAP_ID_MASK
71562. BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__CAP_ID__SHIFT
71563. BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__NEXT_PTR_MASK
71564. BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
71565. BIF_CFG_DEV0_EPF0_2_MSI_MASK_64__MSI_MASK_64_MASK
71566. BIF_CFG_DEV0_EPF0_2_MSI_MASK_64__MSI_MASK_64__SHIFT
71567. BIF_CFG_DEV0_EPF0_2_MSI_MASK__MSI_MASK_MASK
71568. BIF_CFG_DEV0_EPF0_2_MSI_MASK__MSI_MASK__SHIFT
71569. BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
71570. BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
71571. BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
71572. BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
71573. BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_64BIT_MASK
71574. BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
71575. BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_EN_MASK
71576. BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_EN__SHIFT
71577. BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
71578. BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
71579. BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
71580. BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
71581. BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
71582. BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
71583. BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
71584. BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
71585. BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA__MSI_DATA_MASK
71586. BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA__MSI_DATA__SHIFT
71587. BIF_CFG_DEV0_EPF0_2_MSI_PENDING_64__MSI_PENDING_64_MASK
71588. BIF_CFG_DEV0_EPF0_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT
71589. BIF_CFG_DEV0_EPF0_2_MSI_PENDING__MSI_PENDING_MASK
71590. BIF_CFG_DEV0_EPF0_2_MSI_PENDING__MSI_PENDING__SHIFT
71591. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
71592. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
71593. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
71594. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
71595. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
71596. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
71597. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
71598. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
71599. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
71600. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
71601. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
71602. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
71603. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
71604. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
71605. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
71606. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
71607. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
71608. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
71609. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
71610. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
71611. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
71612. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
71613. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
71614. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
71615. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
71616. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
71617. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
71618. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
71619. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
71620. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
71621. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
71622. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
71623. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
71624. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
71625. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
71626. BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
71627. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
71628. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
71629. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
71630. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
71631. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
71632. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
71633. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
71634. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
71635. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
71636. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
71637. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
71638. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
71639. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
71640. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
71641. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
71642. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
71643. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
71644. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
71645. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
71646. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
71647. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
71648. BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
71649. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
71650. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
71651. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
71652. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
71653. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
71654. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
71655. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
71656. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
71657. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
71658. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
71659. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
71660. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
71661. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
71662. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
71663. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
71664. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
71665. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
71666. BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
71667. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
71668. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
71669. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
71670. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
71671. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
71672. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
71673. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__ATC_ENABLE_MASK
71674. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
71675. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__STU_MASK
71676. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__STU__SHIFT
71677. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
71678. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
71679. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
71680. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
71681. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
71682. BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
71683. BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
71684. BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
71685. BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK
71686. BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
71687. BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK
71688. BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
71689. BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
71690. BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
71691. BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
71692. BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
71693. BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK
71694. BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
71695. BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK
71696. BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
71697. BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
71698. BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
71699. BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
71700. BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
71701. BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK
71702. BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
71703. BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK
71704. BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
71705. BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
71706. BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
71707. BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
71708. BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
71709. BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK
71710. BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
71711. BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK
71712. BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
71713. BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
71714. BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
71715. BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
71716. BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
71717. BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK
71718. BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
71719. BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK
71720. BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
71721. BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
71722. BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
71723. BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
71724. BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
71725. BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK
71726. BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
71727. BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK
71728. BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
71729. BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
71730. BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
71731. BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
71732. BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
71733. BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
71734. BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
71735. BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
71736. BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
71737. BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__CAP_ID_MASK
71738. BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__CAP_ID__SHIFT
71739. BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__NEXT_PTR_MASK
71740. BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
71741. BIF_CFG_DEV0_EPF0_2_PCIE_CAP__DEVICE_TYPE_MASK
71742. BIF_CFG_DEV0_EPF0_2_PCIE_CAP__DEVICE_TYPE__SHIFT
71743. BIF_CFG_DEV0_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
71744. BIF_CFG_DEV0_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
71745. BIF_CFG_DEV0_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
71746. BIF_CFG_DEV0_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
71747. BIF_CFG_DEV0_EPF0_2_PCIE_CAP__VERSION_MASK
71748. BIF_CFG_DEV0_EPF0_2_PCIE_CAP__VERSION__SHIFT
71749. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
71750. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
71751. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
71752. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
71753. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
71754. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
71755. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
71756. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
71757. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
71758. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
71759. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
71760. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
71761. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
71762. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
71763. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
71764. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
71765. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
71766. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
71767. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
71768. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
71769. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
71770. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
71771. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
71772. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
71773. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
71774. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
71775. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
71776. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
71777. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
71778. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
71779. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
71780. BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
71781. BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
71782. BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
71783. BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
71784. BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
71785. BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
71786. BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
71787. BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
71788. BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
71789. BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
71790. BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
71791. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
71792. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
71793. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
71794. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
71795. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
71796. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
71797. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
71798. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
71799. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
71800. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
71801. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
71802. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
71803. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
71804. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
71805. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
71806. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
71807. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
71808. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
71809. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
71810. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
71811. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
71812. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
71813. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
71814. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
71815. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
71816. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
71817. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
71818. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
71819. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
71820. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
71821. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
71822. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
71823. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
71824. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
71825. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
71826. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
71827. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
71828. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
71829. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
71830. BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
71831. BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG0__TLP_HDR_MASK
71832. BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
71833. BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG1__TLP_HDR_MASK
71834. BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
71835. BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG2__TLP_HDR_MASK
71836. BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
71837. BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG3__TLP_HDR_MASK
71838. BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
71839. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71840. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71841. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71842. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71843. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
71844. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
71845. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71846. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71847. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71848. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71849. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71850. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71851. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71852. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71853. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
71854. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
71855. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71856. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71857. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71858. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71859. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71860. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71861. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71862. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71863. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
71864. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
71865. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71866. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71867. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71868. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71869. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71870. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71871. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71872. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71873. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
71874. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
71875. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71876. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71877. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71878. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71879. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71880. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71881. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71882. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71883. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
71884. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
71885. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71886. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71887. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71888. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71889. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71890. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71891. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71892. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71893. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
71894. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
71895. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71896. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71897. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71898. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71899. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71900. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71901. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71902. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71903. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
71904. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
71905. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71906. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71907. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71908. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71909. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71910. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71911. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71912. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71913. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
71914. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
71915. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71916. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71917. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71918. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71919. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71920. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71921. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71922. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71923. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
71924. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
71925. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71926. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71927. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71928. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71929. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71930. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71931. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71932. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71933. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
71934. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
71935. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71936. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71937. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71938. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71939. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71940. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71941. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71942. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71943. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
71944. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
71945. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71946. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71947. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71948. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71949. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71950. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71951. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71952. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71953. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
71954. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
71955. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71956. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71957. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71958. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71959. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71960. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71961. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71962. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71963. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
71964. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
71965. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71966. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71967. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71968. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71969. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71970. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71971. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71972. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71973. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
71974. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
71975. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71976. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71977. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71978. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71979. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71980. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71981. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71982. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71983. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
71984. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
71985. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71986. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71987. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71988. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71989. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
71990. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
71991. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
71992. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
71993. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
71994. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
71995. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
71996. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
71997. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
71998. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
71999. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
72000. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
72001. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
72002. BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
72003. BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
72004. BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
72005. BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
72006. BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
72007. BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__RESERVED_MASK
72008. BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__RESERVED__SHIFT
72009. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
72010. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
72011. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
72012. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
72013. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
72014. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
72015. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
72016. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
72017. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
72018. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
72019. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
72020. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
72021. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
72022. BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
72023. BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
72024. BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
72025. BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
72026. BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
72027. BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
72028. BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
72029. BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
72030. BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
72031. BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
72032. BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
72033. BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
72034. BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
72035. BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
72036. BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
72037. BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
72038. BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
72039. BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK
72040. BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
72041. BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK
72042. BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT
72043. BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_ENABLE_MASK
72044. BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT
72045. BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
72046. BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
72047. BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
72048. BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
72049. BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
72050. BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
72051. BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
72052. BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
72053. BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
72054. BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
72055. BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
72056. BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
72057. BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK
72058. BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT
72059. BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK
72060. BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT
72061. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK
72062. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT
72063. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK
72064. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT
72065. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK
72066. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT
72067. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK
72068. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT
72069. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK
72070. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT
72071. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK
72072. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT
72073. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK
72074. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT
72075. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__STOPPED_MASK
72076. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT
72077. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK
72078. BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT
72079. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
72080. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
72081. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
72082. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
72083. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
72084. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
72085. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_ENABLE_MASK
72086. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
72087. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
72088. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
72089. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
72090. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
72091. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
72092. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
72093. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
72094. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
72095. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
72096. BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
72097. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
72098. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
72099. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
72100. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
72101. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
72102. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
72103. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
72104. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
72105. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
72106. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
72107. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
72108. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
72109. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
72110. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
72111. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
72112. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
72113. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
72114. BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
72115. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
72116. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
72117. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
72118. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
72119. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
72120. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
72121. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
72122. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
72123. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
72124. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
72125. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
72126. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
72127. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
72128. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
72129. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK
72130. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
72131. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
72132. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
72133. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
72134. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
72135. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
72136. BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
72137. BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
72138. BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
72139. BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
72140. BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
72141. BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
72142. BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
72143. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK
72144. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT
72145. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK
72146. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT
72147. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK
72148. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT
72149. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK
72150. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT
72151. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK
72152. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT
72153. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK
72154. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT
72155. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK
72156. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT
72157. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK
72158. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT
72159. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK
72160. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT
72161. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK
72162. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT
72163. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK
72164. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT
72165. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK
72166. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT
72167. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK
72168. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT
72169. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK
72170. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT
72171. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK
72172. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT
72173. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK
72174. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT
72175. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK
72176. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT
72177. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK
72178. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT
72179. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK
72180. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT
72181. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK
72182. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT
72183. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK
72184. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT
72185. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK
72186. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT
72187. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK
72188. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT
72189. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK
72190. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT
72191. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK
72192. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT
72193. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK
72194. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT
72195. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK
72196. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT
72197. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK
72198. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT
72199. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK
72200. BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT
72201. BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
72202. BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
72203. BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
72204. BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
72205. BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
72206. BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
72207. BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
72208. BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
72209. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
72210. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
72211. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
72212. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
72213. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
72214. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
72215. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
72216. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
72217. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
72218. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
72219. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
72220. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
72221. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
72222. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
72223. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
72224. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
72225. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
72226. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
72227. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
72228. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
72229. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
72230. BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
72231. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
72232. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
72233. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
72234. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
72235. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
72236. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
72237. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
72238. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
72239. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
72240. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
72241. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
72242. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
72243. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
72244. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
72245. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
72246. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
72247. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
72248. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
72249. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
72250. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
72251. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
72252. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
72253. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
72254. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
72255. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
72256. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
72257. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
72258. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
72259. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
72260. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
72261. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
72262. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
72263. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
72264. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
72265. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
72266. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
72267. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
72268. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
72269. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
72270. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
72271. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
72272. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
72273. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
72274. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
72275. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
72276. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
72277. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
72278. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
72279. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
72280. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
72281. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
72282. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
72283. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
72284. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
72285. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
72286. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
72287. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
72288. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
72289. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
72290. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
72291. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
72292. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
72293. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
72294. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
72295. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
72296. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
72297. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
72298. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
72299. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
72300. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
72301. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
72302. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
72303. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
72304. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
72305. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
72306. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
72307. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
72308. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
72309. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
72310. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
72311. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
72312. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
72313. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
72314. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
72315. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
72316. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
72317. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
72318. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
72319. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
72320. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
72321. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
72322. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
72323. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
72324. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
72325. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
72326. BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
72327. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
72328. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
72329. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
72330. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
72331. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
72332. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
72333. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
72334. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
72335. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
72336. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
72337. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
72338. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
72339. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
72340. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
72341. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
72342. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
72343. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
72344. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
72345. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
72346. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
72347. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
72348. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
72349. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
72350. BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
72351. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
72352. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
72353. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
72354. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
72355. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
72356. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
72357. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
72358. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
72359. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
72360. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
72361. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
72362. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
72363. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
72364. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
72365. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
72366. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
72367. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
72368. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
72369. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
72370. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
72371. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
72372. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
72373. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
72374. BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
72375. BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
72376. BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
72377. BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
72378. BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
72379. BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
72380. BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
72381. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
72382. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
72383. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
72384. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
72385. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK
72386. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT
72387. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK
72388. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT
72389. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK
72390. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT
72391. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
72392. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
72393. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
72394. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
72395. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
72396. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
72397. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK
72398. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT
72399. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK
72400. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT
72401. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK
72402. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT
72403. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK
72404. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT
72405. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK
72406. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT
72407. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK
72408. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT
72409. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK
72410. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT
72411. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK
72412. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT
72413. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK
72414. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT
72415. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK
72416. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT
72417. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK
72418. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT
72419. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK
72420. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT
72421. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK
72422. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT
72423. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK
72424. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT
72425. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK
72426. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT
72427. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK
72428. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT
72429. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK
72430. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT
72431. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK
72432. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT
72433. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK
72434. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT
72435. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK
72436. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT
72437. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK
72438. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT
72439. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK
72440. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT
72441. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK
72442. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT
72443. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK
72444. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT
72445. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK
72446. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT
72447. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK
72448. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT
72449. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK
72450. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT
72451. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK
72452. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT
72453. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK
72454. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT
72455. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK
72456. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT
72457. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK
72458. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT
72459. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK
72460. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT
72461. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK
72462. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT
72463. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK
72464. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT
72465. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK
72466. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT
72467. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK
72468. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT
72469. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK
72470. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT
72471. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK
72472. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT
72473. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK
72474. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT
72475. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK
72476. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT
72477. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK
72478. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT
72479. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK
72480. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT
72481. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK
72482. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT
72483. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK
72484. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT
72485. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK
72486. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT
72487. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK
72488. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT
72489. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK
72490. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT
72491. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK
72492. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT
72493. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK
72494. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT
72495. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK
72496. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT
72497. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK
72498. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT
72499. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK
72500. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT
72501. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK
72502. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT
72503. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK
72504. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT
72505. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK
72506. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT
72507. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK
72508. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT
72509. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK
72510. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT
72511. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK
72512. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT
72513. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK
72514. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT
72515. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK
72516. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT
72517. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK
72518. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT
72519. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK
72520. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT
72521. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK
72522. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT
72523. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK
72524. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT
72525. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK
72526. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT
72527. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK
72528. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT
72529. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK
72530. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT
72531. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK
72532. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
72533. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK
72534. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
72535. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK
72536. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT
72537. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK
72538. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT
72539. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK
72540. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT
72541. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK
72542. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT
72543. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK
72544. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
72545. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK
72546. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
72547. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK
72548. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT
72549. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK
72550. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT
72551. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK
72552. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
72553. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK
72554. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
72555. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK
72556. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT
72557. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK
72558. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT
72559. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK
72560. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT
72561. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK
72562. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT
72563. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK
72564. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT
72565. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK
72566. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT
72567. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK
72568. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT
72569. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK
72570. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT
72571. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK
72572. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT
72573. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK
72574. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT
72575. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK
72576. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT
72577. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK
72578. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT
72579. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK
72580. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT
72581. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK
72582. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT
72583. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK
72584. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT
72585. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK
72586. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT
72587. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK
72588. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT
72589. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK
72590. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT
72591. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK
72592. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT
72593. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK
72594. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT
72595. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK
72596. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT
72597. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK
72598. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT
72599. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK
72600. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT
72601. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK
72602. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT
72603. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK
72604. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT
72605. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK
72606. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT
72607. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK
72608. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT
72609. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK
72610. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT
72611. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK
72612. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT
72613. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK
72614. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT
72615. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK
72616. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT
72617. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK
72618. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT
72619. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK
72620. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT
72621. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK
72622. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT
72623. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK
72624. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT
72625. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK
72626. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT
72627. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK
72628. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT
72629. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK
72630. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT
72631. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK
72632. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT
72633. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK
72634. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT
72635. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK
72636. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT
72637. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK
72638. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT
72639. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK
72640. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT
72641. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK
72642. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT
72643. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK
72644. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT
72645. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK
72646. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT
72647. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK
72648. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT
72649. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK
72650. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT
72651. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK
72652. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT
72653. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK
72654. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT
72655. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK
72656. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT
72657. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK
72658. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT
72659. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK
72660. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT
72661. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK
72662. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT
72663. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK
72664. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT
72665. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK
72666. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT
72667. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK
72668. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT
72669. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK
72670. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT
72671. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK
72672. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT
72673. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK
72674. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT
72675. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK
72676. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT
72677. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
72678. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
72679. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
72680. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
72681. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
72682. BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
72683. BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__CAP_ID_MASK
72684. BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__CAP_ID__SHIFT
72685. BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__NEXT_PTR_MASK
72686. BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
72687. BIF_CFG_DEV0_EPF0_2_PMI_CAP__AUX_CURRENT_MASK
72688. BIF_CFG_DEV0_EPF0_2_PMI_CAP__AUX_CURRENT__SHIFT
72689. BIF_CFG_DEV0_EPF0_2_PMI_CAP__D1_SUPPORT_MASK
72690. BIF_CFG_DEV0_EPF0_2_PMI_CAP__D1_SUPPORT__SHIFT
72691. BIF_CFG_DEV0_EPF0_2_PMI_CAP__D2_SUPPORT_MASK
72692. BIF_CFG_DEV0_EPF0_2_PMI_CAP__D2_SUPPORT__SHIFT
72693. BIF_CFG_DEV0_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
72694. BIF_CFG_DEV0_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
72695. BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_CLOCK_MASK
72696. BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_CLOCK__SHIFT
72697. BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_SUPPORT_MASK
72698. BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_SUPPORT__SHIFT
72699. BIF_CFG_DEV0_EPF0_2_PMI_CAP__VERSION_MASK
72700. BIF_CFG_DEV0_EPF0_2_PMI_CAP__VERSION__SHIFT
72701. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
72702. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
72703. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
72704. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
72705. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
72706. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
72707. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
72708. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
72709. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
72710. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
72711. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_EN_MASK
72712. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_EN__SHIFT
72713. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_STATUS_MASK
72714. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
72715. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PMI_DATA_MASK
72716. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
72717. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__POWER_STATE_MASK
72718. BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
72719. BIF_CFG_DEV0_EPF0_2_PROG_INTERFACE__PROG_INTERFACE_MASK
72720. BIF_CFG_DEV0_EPF0_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
72721. BIF_CFG_DEV0_EPF0_2_REVISION_ID__MAJOR_REV_ID_MASK
72722. BIF_CFG_DEV0_EPF0_2_REVISION_ID__MAJOR_REV_ID__SHIFT
72723. BIF_CFG_DEV0_EPF0_2_REVISION_ID__MINOR_REV_ID_MASK
72724. BIF_CFG_DEV0_EPF0_2_REVISION_ID__MINOR_REV_ID__SHIFT
72725. BIF_CFG_DEV0_EPF0_2_ROM_BASE_ADDR__BASE_ADDR_MASK
72726. BIF_CFG_DEV0_EPF0_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT
72727. BIF_CFG_DEV0_EPF0_2_SLOT_CAP2__RESERVED_MASK
72728. BIF_CFG_DEV0_EPF0_2_SLOT_CAP2__RESERVED__SHIFT
72729. BIF_CFG_DEV0_EPF0_2_SLOT_CNTL2__RESERVED_MASK
72730. BIF_CFG_DEV0_EPF0_2_SLOT_CNTL2__RESERVED__SHIFT
72731. BIF_CFG_DEV0_EPF0_2_SLOT_STATUS2__RESERVED_MASK
72732. BIF_CFG_DEV0_EPF0_2_SLOT_STATUS2__RESERVED__SHIFT
72733. BIF_CFG_DEV0_EPF0_2_STATUS__CAP_LIST_MASK
72734. BIF_CFG_DEV0_EPF0_2_STATUS__CAP_LIST__SHIFT
72735. BIF_CFG_DEV0_EPF0_2_STATUS__DEVSEL_TIMING_MASK
72736. BIF_CFG_DEV0_EPF0_2_STATUS__DEVSEL_TIMING__SHIFT
72737. BIF_CFG_DEV0_EPF0_2_STATUS__FAST_BACK_CAPABLE_MASK
72738. BIF_CFG_DEV0_EPF0_2_STATUS__FAST_BACK_CAPABLE__SHIFT
72739. BIF_CFG_DEV0_EPF0_2_STATUS__INT_STATUS_MASK
72740. BIF_CFG_DEV0_EPF0_2_STATUS__INT_STATUS__SHIFT
72741. BIF_CFG_DEV0_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
72742. BIF_CFG_DEV0_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
72743. BIF_CFG_DEV0_EPF0_2_STATUS__PARITY_ERROR_DETECTED_MASK
72744. BIF_CFG_DEV0_EPF0_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
72745. BIF_CFG_DEV0_EPF0_2_STATUS__PCI_66_EN_MASK
72746. BIF_CFG_DEV0_EPF0_2_STATUS__PCI_66_EN__SHIFT
72747. BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_MASTER_ABORT_MASK
72748. BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
72749. BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_TARGET_ABORT_MASK
72750. BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
72751. BIF_CFG_DEV0_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
72752. BIF_CFG_DEV0_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
72753. BIF_CFG_DEV0_EPF0_2_STATUS__SIGNAL_TARGET_ABORT_MASK
72754. BIF_CFG_DEV0_EPF0_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
72755. BIF_CFG_DEV0_EPF0_2_SUB_CLASS__SUB_CLASS_MASK
72756. BIF_CFG_DEV0_EPF0_2_SUB_CLASS__SUB_CLASS__SHIFT
72757. BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__CAP_ID_MASK
72758. BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__CAP_ID__SHIFT
72759. BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__LENGTH_MASK
72760. BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__LENGTH__SHIFT
72761. BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR_MASK
72762. BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
72763. BIF_CFG_DEV0_EPF0_2_VENDOR_ID__VENDOR_ID_MASK
72764. BIF_CFG_DEV0_EPF0_2_VENDOR_ID__VENDOR_ID__SHIFT
72765. BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
72766. BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
72767. BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
72768. BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
72769. BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_ID_MASK
72770. BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
72771. BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
72772. BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
72773. BIF_CFG_DEV0_EPF0_3_BASE_ADDR_1__BASE_ADDR_MASK
72774. BIF_CFG_DEV0_EPF0_3_BASE_ADDR_1__BASE_ADDR__SHIFT
72775. BIF_CFG_DEV0_EPF0_3_BASE_ADDR_2__BASE_ADDR_MASK
72776. BIF_CFG_DEV0_EPF0_3_BASE_ADDR_2__BASE_ADDR__SHIFT
72777. BIF_CFG_DEV0_EPF0_3_BASE_ADDR_3__BASE_ADDR_MASK
72778. BIF_CFG_DEV0_EPF0_3_BASE_ADDR_3__BASE_ADDR__SHIFT
72779. BIF_CFG_DEV0_EPF0_3_BASE_ADDR_4__BASE_ADDR_MASK
72780. BIF_CFG_DEV0_EPF0_3_BASE_ADDR_4__BASE_ADDR__SHIFT
72781. BIF_CFG_DEV0_EPF0_3_BASE_ADDR_5__BASE_ADDR_MASK
72782. BIF_CFG_DEV0_EPF0_3_BASE_ADDR_5__BASE_ADDR__SHIFT
72783. BIF_CFG_DEV0_EPF0_3_BASE_ADDR_6__BASE_ADDR_MASK
72784. BIF_CFG_DEV0_EPF0_3_BASE_ADDR_6__BASE_ADDR__SHIFT
72785. BIF_CFG_DEV0_EPF0_3_BASE_CLASS__BASE_CLASS_MASK
72786. BIF_CFG_DEV0_EPF0_3_BASE_CLASS__BASE_CLASS__SHIFT
72787. BIF_CFG_DEV0_EPF0_3_BIST__BIST_CAP_MASK
72788. BIF_CFG_DEV0_EPF0_3_BIST__BIST_CAP__SHIFT
72789. BIF_CFG_DEV0_EPF0_3_BIST__BIST_COMP_MASK
72790. BIF_CFG_DEV0_EPF0_3_BIST__BIST_COMP__SHIFT
72791. BIF_CFG_DEV0_EPF0_3_BIST__BIST_STRT_MASK
72792. BIF_CFG_DEV0_EPF0_3_BIST__BIST_STRT__SHIFT
72793. BIF_CFG_DEV0_EPF0_3_CACHE_LINE__CACHE_LINE_SIZE_MASK
72794. BIF_CFG_DEV0_EPF0_3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
72795. BIF_CFG_DEV0_EPF0_3_CAP_PTR__CAP_PTR_MASK
72796. BIF_CFG_DEV0_EPF0_3_CAP_PTR__CAP_PTR__SHIFT
72797. BIF_CFG_DEV0_EPF0_3_COMMAND__AD_STEPPING_MASK
72798. BIF_CFG_DEV0_EPF0_3_COMMAND__AD_STEPPING__SHIFT
72799. BIF_CFG_DEV0_EPF0_3_COMMAND__BUS_MASTER_EN_MASK
72800. BIF_CFG_DEV0_EPF0_3_COMMAND__BUS_MASTER_EN__SHIFT
72801. BIF_CFG_DEV0_EPF0_3_COMMAND__FAST_B2B_EN_MASK
72802. BIF_CFG_DEV0_EPF0_3_COMMAND__FAST_B2B_EN__SHIFT
72803. BIF_CFG_DEV0_EPF0_3_COMMAND__INT_DIS_MASK
72804. BIF_CFG_DEV0_EPF0_3_COMMAND__INT_DIS__SHIFT
72805. BIF_CFG_DEV0_EPF0_3_COMMAND__IO_ACCESS_EN_MASK
72806. BIF_CFG_DEV0_EPF0_3_COMMAND__IO_ACCESS_EN__SHIFT
72807. BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_ACCESS_EN_MASK
72808. BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_ACCESS_EN__SHIFT
72809. BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
72810. BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
72811. BIF_CFG_DEV0_EPF0_3_COMMAND__PAL_SNOOP_EN_MASK
72812. BIF_CFG_DEV0_EPF0_3_COMMAND__PAL_SNOOP_EN__SHIFT
72813. BIF_CFG_DEV0_EPF0_3_COMMAND__PARITY_ERROR_RESPONSE_MASK
72814. BIF_CFG_DEV0_EPF0_3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
72815. BIF_CFG_DEV0_EPF0_3_COMMAND__SERR_EN_MASK
72816. BIF_CFG_DEV0_EPF0_3_COMMAND__SERR_EN__SHIFT
72817. BIF_CFG_DEV0_EPF0_3_COMMAND__SPECIAL_CYCLE_EN_MASK
72818. BIF_CFG_DEV0_EPF0_3_COMMAND__SPECIAL_CYCLE_EN__SHIFT
72819. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
72820. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
72821. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
72822. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
72823. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
72824. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
72825. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
72826. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
72827. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
72828. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
72829. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
72830. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
72831. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
72832. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
72833. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
72834. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
72835. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
72836. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
72837. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__LTR_SUPPORTED_MASK
72838. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
72839. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
72840. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
72841. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
72842. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
72843. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__OBFF_SUPPORTED_MASK
72844. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
72845. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
72846. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
72847. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
72848. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
72849. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
72850. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
72851. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__EXTENDED_TAG_MASK
72852. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__EXTENDED_TAG__SHIFT
72853. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__FLR_CAPABLE_MASK
72854. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__FLR_CAPABLE__SHIFT
72855. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
72856. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
72857. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
72858. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
72859. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
72860. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
72861. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__PHANTOM_FUNC_MASK
72862. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__PHANTOM_FUNC__SHIFT
72863. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
72864. BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
72865. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
72866. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
72867. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
72868. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
72869. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
72870. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
72871. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
72872. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
72873. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
72874. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
72875. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
72876. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
72877. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
72878. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
72879. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
72880. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
72881. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__LTR_EN_MASK
72882. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__LTR_EN__SHIFT
72883. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__OBFF_EN_MASK
72884. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__OBFF_EN__SHIFT
72885. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
72886. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
72887. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__CORR_ERR_EN_MASK
72888. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__CORR_ERR_EN__SHIFT
72889. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
72890. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
72891. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__FATAL_ERR_EN_MASK
72892. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
72893. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__INITIATE_FLR_MASK
72894. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__INITIATE_FLR__SHIFT
72895. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
72896. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
72897. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
72898. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
72899. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
72900. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
72901. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NO_SNOOP_EN_MASK
72902. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
72903. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
72904. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
72905. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__RELAXED_ORD_EN_MASK
72906. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
72907. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__USR_REPORT_EN_MASK
72908. BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__USR_REPORT_EN__SHIFT
72909. BIF_CFG_DEV0_EPF0_3_DEVICE_ID__DEVICE_ID_MASK
72910. BIF_CFG_DEV0_EPF0_3_DEVICE_ID__DEVICE_ID__SHIFT
72911. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS2__RESERVED_MASK
72912. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS2__RESERVED__SHIFT
72913. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__AUX_PWR_MASK
72914. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__AUX_PWR__SHIFT
72915. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__CORR_ERR_MASK
72916. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__CORR_ERR__SHIFT
72917. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__FATAL_ERR_MASK
72918. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__FATAL_ERR__SHIFT
72919. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__NON_FATAL_ERR_MASK
72920. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
72921. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
72922. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
72923. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__USR_DETECTED_MASK
72924. BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__USR_DETECTED__SHIFT
72925. BIF_CFG_DEV0_EPF0_3_HEADER__DEVICE_TYPE_MASK
72926. BIF_CFG_DEV0_EPF0_3_HEADER__DEVICE_TYPE__SHIFT
72927. BIF_CFG_DEV0_EPF0_3_HEADER__HEADER_TYPE_MASK
72928. BIF_CFG_DEV0_EPF0_3_HEADER__HEADER_TYPE__SHIFT
72929. BIF_CFG_DEV0_EPF0_3_INTERRUPT_LINE__INTERRUPT_LINE_MASK
72930. BIF_CFG_DEV0_EPF0_3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
72931. BIF_CFG_DEV0_EPF0_3_INTERRUPT_PIN__INTERRUPT_PIN_MASK
72932. BIF_CFG_DEV0_EPF0_3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
72933. BIF_CFG_DEV0_EPF0_3_LATENCY__LATENCY_TIMER_MASK
72934. BIF_CFG_DEV0_EPF0_3_LATENCY__LATENCY_TIMER__SHIFT
72935. BIF_CFG_DEV0_EPF0_3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
72936. BIF_CFG_DEV0_EPF0_3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
72937. BIF_CFG_DEV0_EPF0_3_LINK_CAP2__RESERVED_MASK
72938. BIF_CFG_DEV0_EPF0_3_LINK_CAP2__RESERVED__SHIFT
72939. BIF_CFG_DEV0_EPF0_3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
72940. BIF_CFG_DEV0_EPF0_3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
72941. BIF_CFG_DEV0_EPF0_3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
72942. BIF_CFG_DEV0_EPF0_3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
72943. BIF_CFG_DEV0_EPF0_3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
72944. BIF_CFG_DEV0_EPF0_3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
72945. BIF_CFG_DEV0_EPF0_3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
72946. BIF_CFG_DEV0_EPF0_3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
72947. BIF_CFG_DEV0_EPF0_3_LINK_CAP__L0S_EXIT_LATENCY_MASK
72948. BIF_CFG_DEV0_EPF0_3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
72949. BIF_CFG_DEV0_EPF0_3_LINK_CAP__L1_EXIT_LATENCY_MASK
72950. BIF_CFG_DEV0_EPF0_3_LINK_CAP__L1_EXIT_LATENCY__SHIFT
72951. BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
72952. BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
72953. BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_SPEED_MASK
72954. BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_SPEED__SHIFT
72955. BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_WIDTH_MASK
72956. BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_WIDTH__SHIFT
72957. BIF_CFG_DEV0_EPF0_3_LINK_CAP__PM_SUPPORT_MASK
72958. BIF_CFG_DEV0_EPF0_3_LINK_CAP__PM_SUPPORT__SHIFT
72959. BIF_CFG_DEV0_EPF0_3_LINK_CAP__PORT_NUMBER_MASK
72960. BIF_CFG_DEV0_EPF0_3_LINK_CAP__PORT_NUMBER__SHIFT
72961. BIF_CFG_DEV0_EPF0_3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
72962. BIF_CFG_DEV0_EPF0_3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
72963. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
72964. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
72965. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_SOS_MASK
72966. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
72967. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_COMPLIANCE_MASK
72968. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
72969. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
72970. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
72971. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
72972. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
72973. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
72974. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
72975. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__TARGET_LINK_SPEED_MASK
72976. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
72977. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__XMIT_MARGIN_MASK
72978. BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__XMIT_MARGIN__SHIFT
72979. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
72980. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
72981. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__COMMON_CLOCK_CFG_MASK
72982. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
72983. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__EXTENDED_SYNC_MASK
72984. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__EXTENDED_SYNC__SHIFT
72985. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
72986. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
72987. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
72988. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
72989. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
72990. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
72991. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_DIS_MASK
72992. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_DIS__SHIFT
72993. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__PM_CONTROL_MASK
72994. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__PM_CONTROL__SHIFT
72995. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__READ_CPL_BOUNDARY_MASK
72996. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
72997. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__RETRAIN_LINK_MASK
72998. BIF_CFG_DEV0_EPF0_3_LINK_CNTL__RETRAIN_LINK__SHIFT
72999. BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
73000. BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
73001. BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
73002. BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
73003. BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
73004. BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
73005. BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
73006. BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
73007. BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
73008. BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
73009. BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
73010. BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
73011. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__CURRENT_LINK_SPEED_MASK
73012. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
73013. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__DL_ACTIVE_MASK
73014. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__DL_ACTIVE__SHIFT
73015. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
73016. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
73017. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
73018. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
73019. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_TRAINING_MASK
73020. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_TRAINING__SHIFT
73021. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
73022. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
73023. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__SLOT_CLOCK_CFG_MASK
73024. BIF_CFG_DEV0_EPF0_3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
73025. BIF_CFG_DEV0_EPF0_3_MAX_LATENCY__MAX_LAT_MASK
73026. BIF_CFG_DEV0_EPF0_3_MAX_LATENCY__MAX_LAT__SHIFT
73027. BIF_CFG_DEV0_EPF0_3_MIN_GRANT__MIN_GNT_MASK
73028. BIF_CFG_DEV0_EPF0_3_MIN_GRANT__MIN_GNT__SHIFT
73029. BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__CAP_ID_MASK
73030. BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__CAP_ID__SHIFT
73031. BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__NEXT_PTR_MASK
73032. BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__NEXT_PTR__SHIFT
73033. BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_EN_MASK
73034. BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_EN__SHIFT
73035. BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
73036. BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
73037. BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
73038. BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
73039. BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_BIR_MASK
73040. BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_BIR__SHIFT
73041. BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_OFFSET_MASK
73042. BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
73043. BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_BIR_MASK
73044. BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
73045. BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
73046. BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
73047. BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__CAP_ID_MASK
73048. BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__CAP_ID__SHIFT
73049. BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__NEXT_PTR_MASK
73050. BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__NEXT_PTR__SHIFT
73051. BIF_CFG_DEV0_EPF0_3_MSI_MASK_64__MSI_MASK_64_MASK
73052. BIF_CFG_DEV0_EPF0_3_MSI_MASK_64__MSI_MASK_64__SHIFT
73053. BIF_CFG_DEV0_EPF0_3_MSI_MASK__MSI_MASK_MASK
73054. BIF_CFG_DEV0_EPF0_3_MSI_MASK__MSI_MASK__SHIFT
73055. BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
73056. BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
73057. BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
73058. BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
73059. BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_64BIT_MASK
73060. BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_64BIT__SHIFT
73061. BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_EN_MASK
73062. BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_EN__SHIFT
73063. BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
73064. BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
73065. BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
73066. BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
73067. BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
73068. BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
73069. BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_64__MSI_DATA_64_MASK
73070. BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
73071. BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA__MSI_DATA_MASK
73072. BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA__MSI_DATA__SHIFT
73073. BIF_CFG_DEV0_EPF0_3_MSI_PENDING_64__MSI_PENDING_64_MASK
73074. BIF_CFG_DEV0_EPF0_3_MSI_PENDING_64__MSI_PENDING_64__SHIFT
73075. BIF_CFG_DEV0_EPF0_3_MSI_PENDING__MSI_PENDING_MASK
73076. BIF_CFG_DEV0_EPF0_3_MSI_PENDING__MSI_PENDING__SHIFT
73077. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
73078. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
73079. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
73080. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
73081. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
73082. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
73083. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
73084. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
73085. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
73086. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
73087. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
73088. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
73089. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
73090. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
73091. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
73092. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
73093. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
73094. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
73095. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
73096. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
73097. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
73098. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
73099. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
73100. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
73101. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
73102. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
73103. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
73104. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
73105. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
73106. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
73107. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
73108. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
73109. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
73110. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
73111. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
73112. BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
73113. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
73114. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
73115. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
73116. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
73117. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
73118. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
73119. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
73120. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
73121. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
73122. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
73123. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
73124. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
73125. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
73126. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
73127. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
73128. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
73129. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
73130. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
73131. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
73132. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
73133. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
73134. BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
73135. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
73136. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
73137. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
73138. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
73139. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
73140. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
73141. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
73142. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
73143. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
73144. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
73145. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
73146. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
73147. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
73148. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
73149. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
73150. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
73151. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
73152. BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
73153. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
73154. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
73155. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
73156. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
73157. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
73158. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
73159. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__ATC_ENABLE_MASK
73160. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
73161. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__STU_MASK
73162. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__STU__SHIFT
73163. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
73164. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
73165. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
73166. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
73167. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
73168. BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
73169. BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
73170. BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
73171. BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_INDEX_MASK
73172. BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
73173. BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_SIZE_MASK
73174. BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
73175. BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
73176. BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
73177. BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
73178. BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
73179. BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_INDEX_MASK
73180. BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
73181. BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_SIZE_MASK
73182. BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
73183. BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
73184. BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
73185. BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
73186. BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
73187. BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_INDEX_MASK
73188. BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
73189. BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_SIZE_MASK
73190. BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
73191. BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
73192. BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
73193. BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
73194. BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
73195. BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_INDEX_MASK
73196. BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
73197. BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_SIZE_MASK
73198. BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
73199. BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
73200. BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
73201. BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
73202. BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
73203. BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_INDEX_MASK
73204. BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
73205. BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_SIZE_MASK
73206. BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
73207. BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
73208. BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
73209. BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
73210. BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
73211. BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_INDEX_MASK
73212. BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
73213. BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_SIZE_MASK
73214. BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
73215. BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
73216. BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
73217. BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
73218. BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
73219. BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
73220. BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
73221. BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
73222. BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
73223. BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__CAP_ID_MASK
73224. BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__CAP_ID__SHIFT
73225. BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__NEXT_PTR_MASK
73226. BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__NEXT_PTR__SHIFT
73227. BIF_CFG_DEV0_EPF0_3_PCIE_CAP__DEVICE_TYPE_MASK
73228. BIF_CFG_DEV0_EPF0_3_PCIE_CAP__DEVICE_TYPE__SHIFT
73229. BIF_CFG_DEV0_EPF0_3_PCIE_CAP__INT_MESSAGE_NUM_MASK
73230. BIF_CFG_DEV0_EPF0_3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
73231. BIF_CFG_DEV0_EPF0_3_PCIE_CAP__SLOT_IMPLEMENTED_MASK
73232. BIF_CFG_DEV0_EPF0_3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
73233. BIF_CFG_DEV0_EPF0_3_PCIE_CAP__VERSION_MASK
73234. BIF_CFG_DEV0_EPF0_3_PCIE_CAP__VERSION__SHIFT
73235. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
73236. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
73237. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
73238. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
73239. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
73240. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
73241. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
73242. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
73243. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
73244. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
73245. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
73246. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
73247. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
73248. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
73249. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
73250. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
73251. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
73252. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
73253. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
73254. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
73255. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
73256. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
73257. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
73258. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
73259. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
73260. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
73261. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
73262. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
73263. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
73264. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
73265. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
73266. BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
73267. BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
73268. BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
73269. BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
73270. BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
73271. BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
73272. BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
73273. BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
73274. BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
73275. BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
73276. BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
73277. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
73278. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
73279. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
73280. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
73281. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
73282. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
73283. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
73284. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
73285. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
73286. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
73287. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
73288. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
73289. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
73290. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
73291. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
73292. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
73293. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
73294. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
73295. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
73296. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
73297. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
73298. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
73299. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
73300. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
73301. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
73302. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
73303. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
73304. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
73305. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
73306. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
73307. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
73308. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
73309. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
73310. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
73311. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
73312. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
73313. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
73314. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
73315. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
73316. BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
73317. BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG0__TLP_HDR_MASK
73318. BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG0__TLP_HDR__SHIFT
73319. BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG1__TLP_HDR_MASK
73320. BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG1__TLP_HDR__SHIFT
73321. BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG2__TLP_HDR_MASK
73322. BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG2__TLP_HDR__SHIFT
73323. BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG3__TLP_HDR_MASK
73324. BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG3__TLP_HDR__SHIFT
73325. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73326. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73327. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73328. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73329. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
73330. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
73331. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73332. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73333. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73334. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73335. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73336. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73337. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73338. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73339. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
73340. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
73341. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73342. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73343. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73344. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73345. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73346. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73347. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73348. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73349. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
73350. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
73351. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73352. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73353. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73354. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73355. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73356. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73357. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73358. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73359. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
73360. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
73361. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73362. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73363. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73364. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73365. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73366. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73367. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73368. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73369. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
73370. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
73371. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73372. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73373. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73374. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73375. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73376. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73377. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73378. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73379. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
73380. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
73381. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73382. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73383. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73384. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73385. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73386. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73387. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73388. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73389. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
73390. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
73391. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73392. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73393. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73394. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73395. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73396. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73397. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73398. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73399. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
73400. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
73401. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73402. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73403. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73404. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73405. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73406. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73407. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73408. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73409. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
73410. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
73411. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73412. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73413. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73414. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73415. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73416. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73417. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73418. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73419. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
73420. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
73421. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73422. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73423. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73424. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73425. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73426. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73427. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73428. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73429. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
73430. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
73431. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73432. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73433. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73434. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73435. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73436. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73437. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73438. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73439. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
73440. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
73441. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73442. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73443. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73444. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73445. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73446. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73447. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73448. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73449. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
73450. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
73451. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73452. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73453. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73454. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73455. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73456. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73457. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73458. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73459. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
73460. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
73461. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73462. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73463. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73464. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73465. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73466. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73467. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73468. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73469. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
73470. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
73471. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73472. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73473. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73474. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73475. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
73476. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
73477. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
73478. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
73479. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
73480. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
73481. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
73482. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
73483. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
73484. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
73485. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
73486. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
73487. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
73488. BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
73489. BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
73490. BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
73491. BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
73492. BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
73493. BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__RESERVED_MASK
73494. BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__RESERVED__SHIFT
73495. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
73496. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
73497. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
73498. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
73499. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
73500. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
73501. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
73502. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
73503. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
73504. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
73505. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
73506. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
73507. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
73508. BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
73509. BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
73510. BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
73511. BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
73512. BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
73513. BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
73514. BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
73515. BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
73516. BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
73517. BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
73518. BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
73519. BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
73520. BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
73521. BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
73522. BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
73523. BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
73524. BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
73525. BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_MAX_GROUP_MASK
73526. BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
73527. BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK
73528. BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT
73529. BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_ENABLE_MASK
73530. BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_ENABLE__SHIFT
73531. BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
73532. BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
73533. BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
73534. BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
73535. BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
73536. BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
73537. BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
73538. BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
73539. BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
73540. BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
73541. BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
73542. BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
73543. BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK
73544. BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT
73545. BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK
73546. BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT
73547. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK
73548. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT
73549. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK
73550. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT
73551. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK
73552. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT
73553. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK
73554. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT
73555. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK
73556. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT
73557. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK
73558. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT
73559. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK
73560. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT
73561. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__STOPPED_MASK
73562. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT
73563. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK
73564. BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT
73565. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
73566. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
73567. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
73568. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
73569. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
73570. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
73571. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_ENABLE_MASK
73572. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
73573. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
73574. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
73575. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
73576. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
73577. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
73578. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
73579. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
73580. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
73581. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
73582. BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
73583. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
73584. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
73585. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
73586. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
73587. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
73588. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
73589. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
73590. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
73591. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
73592. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
73593. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
73594. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
73595. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
73596. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
73597. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
73598. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
73599. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
73600. BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
73601. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
73602. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
73603. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
73604. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
73605. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
73606. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
73607. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
73608. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
73609. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
73610. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
73611. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
73612. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
73613. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
73614. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
73615. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__TYPE_MASK
73616. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
73617. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
73618. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
73619. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
73620. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
73621. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
73622. BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
73623. BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
73624. BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
73625. BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
73626. BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
73627. BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
73628. BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
73629. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK
73630. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT
73631. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK
73632. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT
73633. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK
73634. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT
73635. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK
73636. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT
73637. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK
73638. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT
73639. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK
73640. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT
73641. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK
73642. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT
73643. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK
73644. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT
73645. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK
73646. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT
73647. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK
73648. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT
73649. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK
73650. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT
73651. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK
73652. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT
73653. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK
73654. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT
73655. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK
73656. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT
73657. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK
73658. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT
73659. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK
73660. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT
73661. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK
73662. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT
73663. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK
73664. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT
73665. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK
73666. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT
73667. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK
73668. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT
73669. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK
73670. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT
73671. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK
73672. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT
73673. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK
73674. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT
73675. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK
73676. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT
73677. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK
73678. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT
73679. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK
73680. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT
73681. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK
73682. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT
73683. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK
73684. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT
73685. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK
73686. BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT
73687. BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
73688. BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
73689. BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
73690. BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
73691. BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
73692. BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
73693. BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
73694. BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
73695. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
73696. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
73697. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
73698. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
73699. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
73700. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
73701. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
73702. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
73703. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
73704. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
73705. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
73706. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
73707. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
73708. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
73709. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
73710. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
73711. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
73712. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
73713. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
73714. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
73715. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
73716. BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
73717. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
73718. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
73719. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
73720. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
73721. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
73722. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
73723. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
73724. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
73725. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
73726. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
73727. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
73728. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
73729. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
73730. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
73731. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
73732. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
73733. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
73734. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
73735. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
73736. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
73737. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
73738. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
73739. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
73740. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
73741. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
73742. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
73743. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
73744. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
73745. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
73746. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
73747. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
73748. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
73749. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
73750. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
73751. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
73752. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
73753. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
73754. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
73755. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
73756. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
73757. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
73758. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
73759. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
73760. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
73761. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
73762. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
73763. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
73764. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
73765. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
73766. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
73767. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
73768. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
73769. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
73770. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
73771. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
73772. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
73773. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
73774. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
73775. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
73776. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
73777. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
73778. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
73779. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
73780. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
73781. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
73782. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
73783. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
73784. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
73785. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
73786. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
73787. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
73788. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
73789. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
73790. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
73791. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
73792. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
73793. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
73794. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
73795. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
73796. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
73797. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
73798. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
73799. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
73800. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
73801. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
73802. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
73803. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
73804. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
73805. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
73806. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
73807. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
73808. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
73809. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
73810. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
73811. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
73812. BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
73813. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
73814. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
73815. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
73816. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
73817. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
73818. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
73819. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
73820. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
73821. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
73822. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
73823. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
73824. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
73825. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
73826. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
73827. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
73828. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
73829. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
73830. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
73831. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
73832. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
73833. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
73834. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
73835. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
73836. BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
73837. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
73838. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
73839. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
73840. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
73841. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
73842. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
73843. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
73844. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
73845. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
73846. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
73847. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
73848. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
73849. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
73850. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
73851. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
73852. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
73853. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
73854. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
73855. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
73856. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
73857. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
73858. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
73859. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
73860. BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
73861. BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
73862. BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
73863. BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
73864. BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
73865. BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
73866. BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
73867. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
73868. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
73869. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
73870. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
73871. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK
73872. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT
73873. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK
73874. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT
73875. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK
73876. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT
73877. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
73878. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
73879. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
73880. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
73881. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
73882. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
73883. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK
73884. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT
73885. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK
73886. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT
73887. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK
73888. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT
73889. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK
73890. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT
73891. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK
73892. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT
73893. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK
73894. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT
73895. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK
73896. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT
73897. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK
73898. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT
73899. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK
73900. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT
73901. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK
73902. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT
73903. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK
73904. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT
73905. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK
73906. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT
73907. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK
73908. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT
73909. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK
73910. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT
73911. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK
73912. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT
73913. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK
73914. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT
73915. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK
73916. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT
73917. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK
73918. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT
73919. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK
73920. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT
73921. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK
73922. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT
73923. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK
73924. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT
73925. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK
73926. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT
73927. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK
73928. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT
73929. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK
73930. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT
73931. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK
73932. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT
73933. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK
73934. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT
73935. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK
73936. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT
73937. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK
73938. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT
73939. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK
73940. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT
73941. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK
73942. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT
73943. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK
73944. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT
73945. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK
73946. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT
73947. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK
73948. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT
73949. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK
73950. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT
73951. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK
73952. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT
73953. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK
73954. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT
73955. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK
73956. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT
73957. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK
73958. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT
73959. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK
73960. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT
73961. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK
73962. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT
73963. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK
73964. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT
73965. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK
73966. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT
73967. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK
73968. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT
73969. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK
73970. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT
73971. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK
73972. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT
73973. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK
73974. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT
73975. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK
73976. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT
73977. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK
73978. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT
73979. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK
73980. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT
73981. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK
73982. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT
73983. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK
73984. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT
73985. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK
73986. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT
73987. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK
73988. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT
73989. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK
73990. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT
73991. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK
73992. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT
73993. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK
73994. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT
73995. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK
73996. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT
73997. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK
73998. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT
73999. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK
74000. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT
74001. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK
74002. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT
74003. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK
74004. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT
74005. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK
74006. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT
74007. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK
74008. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT
74009. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK
74010. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT
74011. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK
74012. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT
74013. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK
74014. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT
74015. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK
74016. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT
74017. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK
74018. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
74019. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK
74020. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
74021. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK
74022. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT
74023. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK
74024. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT
74025. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK
74026. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT
74027. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK
74028. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT
74029. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK
74030. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
74031. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK
74032. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
74033. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK
74034. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT
74035. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK
74036. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT
74037. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK
74038. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
74039. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK
74040. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
74041. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK
74042. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT
74043. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK
74044. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT
74045. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK
74046. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT
74047. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK
74048. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT
74049. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK
74050. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT
74051. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK
74052. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT
74053. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK
74054. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT
74055. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK
74056. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT
74057. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK
74058. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT
74059. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK
74060. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT
74061. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK
74062. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT
74063. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK
74064. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT
74065. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK
74066. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT
74067. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK
74068. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT
74069. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK
74070. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT
74071. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK
74072. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT
74073. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK
74074. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT
74075. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK
74076. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT
74077. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK
74078. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT
74079. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK
74080. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT
74081. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK
74082. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT
74083. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK
74084. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT
74085. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK
74086. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT
74087. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK
74088. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT
74089. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK
74090. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT
74091. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK
74092. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT
74093. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK
74094. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT
74095. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK
74096. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT
74097. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK
74098. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT
74099. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK
74100. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT
74101. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK
74102. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT
74103. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK
74104. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT
74105. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK
74106. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT
74107. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK
74108. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT
74109. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK
74110. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT
74111. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK
74112. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT
74113. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK
74114. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT
74115. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK
74116. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT
74117. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK
74118. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT
74119. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK
74120. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT
74121. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK
74122. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT
74123. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK
74124. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT
74125. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK
74126. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT
74127. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK
74128. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT
74129. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK
74130. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT
74131. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK
74132. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT
74133. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK
74134. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT
74135. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK
74136. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT
74137. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK
74138. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT
74139. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK
74140. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT
74141. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK
74142. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT
74143. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK
74144. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT
74145. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK
74146. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT
74147. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK
74148. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT
74149. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK
74150. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT
74151. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK
74152. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT
74153. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK
74154. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT
74155. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK
74156. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT
74157. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK
74158. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT
74159. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK
74160. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT
74161. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK
74162. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT
74163. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
74164. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
74165. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
74166. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
74167. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
74168. BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
74169. BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__CAP_ID_MASK
74170. BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__CAP_ID__SHIFT
74171. BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__NEXT_PTR_MASK
74172. BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__NEXT_PTR__SHIFT
74173. BIF_CFG_DEV0_EPF0_3_PMI_CAP__AUX_CURRENT_MASK
74174. BIF_CFG_DEV0_EPF0_3_PMI_CAP__AUX_CURRENT__SHIFT
74175. BIF_CFG_DEV0_EPF0_3_PMI_CAP__D1_SUPPORT_MASK
74176. BIF_CFG_DEV0_EPF0_3_PMI_CAP__D1_SUPPORT__SHIFT
74177. BIF_CFG_DEV0_EPF0_3_PMI_CAP__D2_SUPPORT_MASK
74178. BIF_CFG_DEV0_EPF0_3_PMI_CAP__D2_SUPPORT__SHIFT
74179. BIF_CFG_DEV0_EPF0_3_PMI_CAP__DEV_SPECIFIC_INIT_MASK
74180. BIF_CFG_DEV0_EPF0_3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
74181. BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_CLOCK_MASK
74182. BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_CLOCK__SHIFT
74183. BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_SUPPORT_MASK
74184. BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_SUPPORT__SHIFT
74185. BIF_CFG_DEV0_EPF0_3_PMI_CAP__VERSION_MASK
74186. BIF_CFG_DEV0_EPF0_3_PMI_CAP__VERSION__SHIFT
74187. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
74188. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
74189. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
74190. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
74191. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SCALE_MASK
74192. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
74193. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SELECT_MASK
74194. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
74195. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
74196. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
74197. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_EN_MASK
74198. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_EN__SHIFT
74199. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_STATUS_MASK
74200. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_STATUS__SHIFT
74201. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PMI_DATA_MASK
74202. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PMI_DATA__SHIFT
74203. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__POWER_STATE_MASK
74204. BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__POWER_STATE__SHIFT
74205. BIF_CFG_DEV0_EPF0_3_PROG_INTERFACE__PROG_INTERFACE_MASK
74206. BIF_CFG_DEV0_EPF0_3_PROG_INTERFACE__PROG_INTERFACE__SHIFT
74207. BIF_CFG_DEV0_EPF0_3_REVISION_ID__MAJOR_REV_ID_MASK
74208. BIF_CFG_DEV0_EPF0_3_REVISION_ID__MAJOR_REV_ID__SHIFT
74209. BIF_CFG_DEV0_EPF0_3_REVISION_ID__MINOR_REV_ID_MASK
74210. BIF_CFG_DEV0_EPF0_3_REVISION_ID__MINOR_REV_ID__SHIFT
74211. BIF_CFG_DEV0_EPF0_3_ROM_BASE_ADDR__BASE_ADDR_MASK
74212. BIF_CFG_DEV0_EPF0_3_ROM_BASE_ADDR__BASE_ADDR__SHIFT
74213. BIF_CFG_DEV0_EPF0_3_SLOT_CAP2__RESERVED_MASK
74214. BIF_CFG_DEV0_EPF0_3_SLOT_CAP2__RESERVED__SHIFT
74215. BIF_CFG_DEV0_EPF0_3_SLOT_CNTL2__RESERVED_MASK
74216. BIF_CFG_DEV0_EPF0_3_SLOT_CNTL2__RESERVED__SHIFT
74217. BIF_CFG_DEV0_EPF0_3_SLOT_STATUS2__RESERVED_MASK
74218. BIF_CFG_DEV0_EPF0_3_SLOT_STATUS2__RESERVED__SHIFT
74219. BIF_CFG_DEV0_EPF0_3_STATUS__CAP_LIST_MASK
74220. BIF_CFG_DEV0_EPF0_3_STATUS__CAP_LIST__SHIFT
74221. BIF_CFG_DEV0_EPF0_3_STATUS__DEVSEL_TIMING_MASK
74222. BIF_CFG_DEV0_EPF0_3_STATUS__DEVSEL_TIMING__SHIFT
74223. BIF_CFG_DEV0_EPF0_3_STATUS__FAST_BACK_CAPABLE_MASK
74224. BIF_CFG_DEV0_EPF0_3_STATUS__FAST_BACK_CAPABLE__SHIFT
74225. BIF_CFG_DEV0_EPF0_3_STATUS__INT_STATUS_MASK
74226. BIF_CFG_DEV0_EPF0_3_STATUS__INT_STATUS__SHIFT
74227. BIF_CFG_DEV0_EPF0_3_STATUS__MASTER_DATA_PARITY_ERROR_MASK
74228. BIF_CFG_DEV0_EPF0_3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
74229. BIF_CFG_DEV0_EPF0_3_STATUS__PARITY_ERROR_DETECTED_MASK
74230. BIF_CFG_DEV0_EPF0_3_STATUS__PARITY_ERROR_DETECTED__SHIFT
74231. BIF_CFG_DEV0_EPF0_3_STATUS__PCI_66_EN_MASK
74232. BIF_CFG_DEV0_EPF0_3_STATUS__PCI_66_EN__SHIFT
74233. BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_MASTER_ABORT_MASK
74234. BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_MASTER_ABORT__SHIFT
74235. BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_TARGET_ABORT_MASK
74236. BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_TARGET_ABORT__SHIFT
74237. BIF_CFG_DEV0_EPF0_3_STATUS__SIGNALED_SYSTEM_ERROR_MASK
74238. BIF_CFG_DEV0_EPF0_3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
74239. BIF_CFG_DEV0_EPF0_3_STATUS__SIGNAL_TARGET_ABORT_MASK
74240. BIF_CFG_DEV0_EPF0_3_STATUS__SIGNAL_TARGET_ABORT__SHIFT
74241. BIF_CFG_DEV0_EPF0_3_SUB_CLASS__SUB_CLASS_MASK
74242. BIF_CFG_DEV0_EPF0_3_SUB_CLASS__SUB_CLASS__SHIFT
74243. BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__CAP_ID_MASK
74244. BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__CAP_ID__SHIFT
74245. BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__LENGTH_MASK
74246. BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__LENGTH__SHIFT
74247. BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__NEXT_PTR_MASK
74248. BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
74249. BIF_CFG_DEV0_EPF0_3_VENDOR_ID__VENDOR_ID_MASK
74250. BIF_CFG_DEV0_EPF0_3_VENDOR_ID__VENDOR_ID__SHIFT
74251. BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
74252. BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
74253. BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
74254. BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
74255. BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK
74256. BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
74257. BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
74258. BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
74259. BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK
74260. BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT
74261. BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK
74262. BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT
74263. BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK
74264. BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT
74265. BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK
74266. BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT
74267. BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK
74268. BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT
74269. BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK
74270. BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT
74271. BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK
74272. BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT
74273. BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK
74274. BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT
74275. BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK
74276. BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT
74277. BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK
74278. BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT
74279. BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK
74280. BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
74281. BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK
74282. BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT
74283. BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
74284. BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
74285. BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK
74286. BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT
74287. BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK
74288. BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT
74289. BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK
74290. BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT
74291. BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK
74292. BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT
74293. BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK
74294. BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT
74295. BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK
74296. BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT
74297. BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
74298. BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
74299. BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK
74300. BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT
74301. BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK
74302. BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
74303. BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK
74304. BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT
74305. BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK
74306. BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
74307. BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK
74308. BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT
74309. BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK
74310. BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT
74311. BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK
74312. BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK
74313. BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT
74314. BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT
74315. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
74316. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
74317. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
74318. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
74319. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
74320. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
74321. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
74322. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
74323. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
74324. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
74325. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
74326. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
74327. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
74328. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
74329. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
74330. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
74331. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
74332. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
74333. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
74334. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
74335. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
74336. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
74337. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK
74338. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
74339. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
74340. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
74341. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK
74342. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
74343. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
74344. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
74345. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
74346. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
74347. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
74348. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
74349. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
74350. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
74351. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
74352. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
74353. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
74354. BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
74355. BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
74356. BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
74357. BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
74358. BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
74359. BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK
74360. BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT
74361. BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK
74362. BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT
74363. BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
74364. BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
74365. BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
74366. BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
74367. BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
74368. BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
74369. BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK
74370. BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
74371. BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
74372. BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
74373. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
74374. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
74375. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
74376. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
74377. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
74378. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
74379. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
74380. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
74381. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
74382. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
74383. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
74384. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
74385. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
74386. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
74387. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
74388. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
74389. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
74390. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
74391. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK
74392. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT
74393. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK
74394. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT
74395. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
74396. BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
74397. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
74398. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
74399. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK
74400. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
74401. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
74402. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
74403. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK
74404. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
74405. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK
74406. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT
74407. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
74408. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
74409. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
74410. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
74411. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
74412. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
74413. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK
74414. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
74415. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
74416. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
74417. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
74418. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
74419. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK
74420. BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
74421. BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK
74422. BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT
74423. BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK
74424. BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT
74425. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK
74426. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT
74427. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK
74428. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT
74429. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
74430. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
74431. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK
74432. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT
74433. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK
74434. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
74435. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
74436. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
74437. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK
74438. BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT
74439. BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK
74440. BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT
74441. BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK
74442. BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT
74443. BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
74444. BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
74445. BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
74446. BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
74447. BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK
74448. BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT
74449. BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK
74450. BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT
74451. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK
74452. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT
74453. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK
74454. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT
74455. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK
74456. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT
74457. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK
74458. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT
74459. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK
74460. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT
74461. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK
74462. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT
74463. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK
74464. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT
74465. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK
74466. BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT
74467. BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK
74468. BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT
74469. BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK
74470. BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT
74471. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK
74472. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT
74473. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK
74474. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT
74475. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK
74476. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT
74477. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK
74478. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT
74479. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK
74480. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT
74481. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK
74482. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT
74483. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK
74484. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT
74485. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK
74486. BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT
74487. BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK
74488. BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT
74489. BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK
74490. BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT
74491. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK
74492. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT
74493. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK
74494. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT
74495. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK
74496. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT
74497. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK
74498. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT
74499. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK
74500. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT
74501. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK
74502. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT
74503. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK
74504. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT
74505. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK
74506. BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT
74507. BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK
74508. BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT
74509. BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK
74510. BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT
74511. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK
74512. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT
74513. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK
74514. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT
74515. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK
74516. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT
74517. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK
74518. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT
74519. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK
74520. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT
74521. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK
74522. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT
74523. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK
74524. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT
74525. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK
74526. BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT
74527. BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK
74528. BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT
74529. BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK
74530. BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT
74531. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK
74532. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT
74533. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK
74534. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT
74535. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK
74536. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT
74537. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK
74538. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT
74539. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK
74540. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT
74541. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK
74542. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT
74543. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK
74544. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT
74545. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK
74546. BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT
74547. BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK
74548. BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT
74549. BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK
74550. BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT
74551. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK
74552. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT
74553. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK
74554. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT
74555. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK
74556. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT
74557. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK
74558. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT
74559. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK
74560. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT
74561. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK
74562. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT
74563. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK
74564. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT
74565. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK
74566. BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT
74567. BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK
74568. BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT
74569. BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK
74570. BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT
74571. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK
74572. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT
74573. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK
74574. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT
74575. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK
74576. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT
74577. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK
74578. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT
74579. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK
74580. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT
74581. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK
74582. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT
74583. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK
74584. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT
74585. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK
74586. BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT
74587. BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK
74588. BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT
74589. BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK
74590. BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT
74591. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK
74592. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT
74593. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK
74594. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT
74595. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK
74596. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT
74597. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK
74598. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT
74599. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK
74600. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT
74601. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK
74602. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT
74603. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK
74604. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT
74605. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK
74606. BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT
74607. BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK
74608. BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT
74609. BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK
74610. BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT
74611. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK
74612. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT
74613. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK
74614. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT
74615. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK
74616. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT
74617. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK
74618. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT
74619. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK
74620. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT
74621. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK
74622. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT
74623. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK
74624. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT
74625. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK
74626. BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT
74627. BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK
74628. BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT
74629. BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK
74630. BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT
74631. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK
74632. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT
74633. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK
74634. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT
74635. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK
74636. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT
74637. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK
74638. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT
74639. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK
74640. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT
74641. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK
74642. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT
74643. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK
74644. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT
74645. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK
74646. BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT
74647. BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK
74648. BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT
74649. BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK
74650. BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT
74651. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK
74652. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT
74653. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK
74654. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT
74655. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK
74656. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT
74657. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK
74658. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT
74659. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK
74660. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT
74661. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK
74662. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT
74663. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK
74664. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT
74665. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK
74666. BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT
74667. BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK
74668. BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT
74669. BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK
74670. BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT
74671. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK
74672. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT
74673. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK
74674. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT
74675. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK
74676. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT
74677. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK
74678. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT
74679. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK
74680. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT
74681. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK
74682. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT
74683. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK
74684. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT
74685. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK
74686. BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT
74687. BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK
74688. BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT
74689. BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK
74690. BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT
74691. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK
74692. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT
74693. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK
74694. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT
74695. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK
74696. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT
74697. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK
74698. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT
74699. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK
74700. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT
74701. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK
74702. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT
74703. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK
74704. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT
74705. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK
74706. BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT
74707. BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK
74708. BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT
74709. BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK
74710. BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT
74711. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK
74712. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT
74713. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK
74714. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT
74715. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK
74716. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT
74717. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK
74718. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT
74719. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK
74720. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT
74721. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK
74722. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT
74723. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK
74724. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT
74725. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK
74726. BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT
74727. BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK
74728. BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT
74729. BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK
74730. BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT
74731. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK
74732. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT
74733. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK
74734. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT
74735. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK
74736. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT
74737. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK
74738. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT
74739. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK
74740. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT
74741. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK
74742. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT
74743. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK
74744. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT
74745. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK
74746. BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT
74747. BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK
74748. BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT
74749. BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK
74750. BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT
74751. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK
74752. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT
74753. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK
74754. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT
74755. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK
74756. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT
74757. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK
74758. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT
74759. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK
74760. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT
74761. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK
74762. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT
74763. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK
74764. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT
74765. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK
74766. BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT
74767. BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK
74768. BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT
74769. BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
74770. BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
74771. BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
74772. BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
74773. BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
74774. BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
74775. BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
74776. BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
74777. BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
74778. BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
74779. BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
74780. BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
74781. BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
74782. BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
74783. BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK
74784. BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT
74785. BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
74786. BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
74787. BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
74788. BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
74789. BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
74790. BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
74791. BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK
74792. BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
74793. BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK
74794. BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
74795. BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
74796. BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
74797. BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK
74798. BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT
74799. BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK
74800. BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT
74801. BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK
74802. BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT
74803. BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK
74804. BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT
74805. BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
74806. BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
74807. BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
74808. BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
74809. BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK
74810. BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
74811. BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
74812. BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
74813. BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
74814. BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
74815. BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
74816. BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
74817. BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
74818. BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
74819. BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
74820. BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
74821. BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK
74822. BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT
74823. BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK
74824. BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT
74825. BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
74826. BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
74827. BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
74828. BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
74829. BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
74830. BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
74831. BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK
74832. BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT
74833. BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
74834. BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
74835. BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
74836. BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
74837. BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
74838. BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
74839. BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK
74840. BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT
74841. BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK
74842. BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT
74843. BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
74844. BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
74845. BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK
74846. BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT
74847. BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
74848. BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
74849. BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
74850. BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
74851. BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
74852. BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
74853. BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
74854. BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
74855. BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
74856. BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
74857. BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
74858. BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
74859. BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
74860. BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
74861. BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
74862. BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
74863. BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
74864. BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
74865. BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
74866. BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
74867. BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
74868. BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
74869. BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK
74870. BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT
74871. BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK
74872. BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT
74873. BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK
74874. BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT
74875. BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK
74876. BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT
74877. BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK
74878. BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT
74879. BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
74880. BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
74881. BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK
74882. BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT
74883. BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
74884. BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
74885. BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
74886. BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
74887. BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK
74888. BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT
74889. BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
74890. BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
74891. BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
74892. BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
74893. BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK
74894. BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT
74895. BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK
74896. BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT
74897. BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK
74898. BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT
74899. BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK
74900. BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT
74901. BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK
74902. BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT
74903. BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK
74904. BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT
74905. BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK
74906. BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT
74907. BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK
74908. BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
74909. BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK
74910. BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
74911. BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
74912. BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
74913. BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
74914. BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
74915. BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK
74916. BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
74917. BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
74918. BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
74919. BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
74920. BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
74921. BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
74922. BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
74923. BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK
74924. BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT
74925. BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK
74926. BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT
74927. BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK
74928. BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT
74929. BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK
74930. BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT
74931. BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
74932. BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
74933. BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
74934. BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
74935. BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK
74936. BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
74937. BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK
74938. BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT
74939. BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
74940. BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
74941. BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
74942. BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
74943. BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
74944. BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
74945. BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
74946. BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
74947. BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK
74948. BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT
74949. BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK
74950. BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
74951. BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK
74952. BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT
74953. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
74954. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
74955. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
74956. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
74957. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
74958. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
74959. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
74960. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
74961. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
74962. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
74963. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
74964. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
74965. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
74966. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
74967. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
74968. BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
74969. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
74970. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
74971. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
74972. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
74973. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
74974. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
74975. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
74976. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
74977. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
74978. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
74979. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
74980. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
74981. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
74982. BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
74983. BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
74984. BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
74985. BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
74986. BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
74987. BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
74988. BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
74989. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
74990. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
74991. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
74992. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
74993. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
74994. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
74995. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
74996. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
74997. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
74998. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
74999. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
75000. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
75001. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
75002. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
75003. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
75004. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
75005. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
75006. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
75007. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
75008. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
75009. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
75010. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
75011. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
75012. BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
75013. BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
75014. BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
75015. BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
75016. BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
75017. BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
75018. BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
75019. BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
75020. BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
75021. BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
75022. BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
75023. BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
75024. BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
75025. BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
75026. BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
75027. BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
75028. BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
75029. BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
75030. BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
75031. BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
75032. BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
75033. BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
75034. BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
75035. BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
75036. BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
75037. BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
75038. BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
75039. BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK
75040. BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT
75041. BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
75042. BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
75043. BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
75044. BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
75045. BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
75046. BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
75047. BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
75048. BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
75049. BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK
75050. BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
75051. BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK
75052. BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
75053. BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
75054. BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
75055. BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
75056. BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
75057. BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK
75058. BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
75059. BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK
75060. BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
75061. BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
75062. BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
75063. BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
75064. BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
75065. BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK
75066. BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
75067. BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK
75068. BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
75069. BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
75070. BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
75071. BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
75072. BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
75073. BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK
75074. BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
75075. BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK
75076. BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
75077. BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
75078. BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
75079. BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
75080. BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
75081. BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK
75082. BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
75083. BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK
75084. BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
75085. BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
75086. BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
75087. BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
75088. BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
75089. BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK
75090. BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
75091. BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK
75092. BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
75093. BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
75094. BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
75095. BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
75096. BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
75097. BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
75098. BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
75099. BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
75100. BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
75101. BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK
75102. BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT
75103. BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK
75104. BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
75105. BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK
75106. BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT
75107. BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK
75108. BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
75109. BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
75110. BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
75111. BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK
75112. BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT
75113. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
75114. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
75115. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
75116. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
75117. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
75118. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
75119. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
75120. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
75121. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
75122. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
75123. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
75124. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
75125. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
75126. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
75127. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
75128. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
75129. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
75130. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
75131. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
75132. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
75133. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
75134. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
75135. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
75136. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
75137. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
75138. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
75139. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
75140. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
75141. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
75142. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
75143. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
75144. BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
75145. BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
75146. BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
75147. BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
75148. BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
75149. BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
75150. BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
75151. BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
75152. BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
75153. BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
75154. BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
75155. BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK
75156. BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT
75157. BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK
75158. BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT
75159. BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK
75160. BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT
75161. BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
75162. BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
75163. BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
75164. BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
75165. BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
75166. BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
75167. BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
75168. BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
75169. BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
75170. BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
75171. BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
75172. BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
75173. BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
75174. BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
75175. BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
75176. BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
75177. BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
75178. BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
75179. BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
75180. BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
75181. BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
75182. BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
75183. BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
75184. BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
75185. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
75186. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
75187. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
75188. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
75189. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
75190. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
75191. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
75192. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
75193. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
75194. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
75195. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
75196. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
75197. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
75198. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
75199. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
75200. BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
75201. BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK
75202. BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
75203. BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK
75204. BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
75205. BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK
75206. BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
75207. BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK
75208. BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
75209. BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75210. BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75211. BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75212. BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75213. BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
75214. BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
75215. BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75216. BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75217. BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75218. BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75219. BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75220. BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75221. BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75222. BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75223. BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
75224. BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
75225. BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75226. BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75227. BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75228. BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75229. BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75230. BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75231. BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75232. BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75233. BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
75234. BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
75235. BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75236. BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75237. BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75238. BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75239. BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75240. BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75241. BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75242. BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75243. BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
75244. BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
75245. BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75246. BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75247. BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75248. BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75249. BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75250. BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75251. BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75252. BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75253. BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
75254. BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
75255. BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75256. BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75257. BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75258. BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75259. BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75260. BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75261. BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75262. BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75263. BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
75264. BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
75265. BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75266. BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75267. BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75268. BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75269. BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75270. BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75271. BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75272. BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75273. BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
75274. BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
75275. BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75276. BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75277. BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75278. BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75279. BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75280. BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75281. BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75282. BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75283. BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
75284. BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
75285. BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75286. BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75287. BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75288. BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75289. BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75290. BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75291. BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75292. BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75293. BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
75294. BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
75295. BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75296. BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75297. BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75298. BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75299. BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75300. BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75301. BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75302. BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75303. BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
75304. BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
75305. BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75306. BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75307. BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75308. BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75309. BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75310. BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75311. BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75312. BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75313. BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
75314. BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
75315. BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75316. BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75317. BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75318. BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75319. BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75320. BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75321. BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75322. BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75323. BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
75324. BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
75325. BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75326. BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75327. BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75328. BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75329. BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75330. BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75331. BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75332. BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75333. BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
75334. BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
75335. BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75336. BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75337. BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75338. BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75339. BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75340. BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75341. BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75342. BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75343. BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
75344. BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
75345. BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75346. BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75347. BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75348. BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75349. BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75350. BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75351. BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75352. BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75353. BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
75354. BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
75355. BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75356. BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75357. BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75358. BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75359. BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
75360. BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
75361. BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
75362. BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
75363. BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
75364. BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
75365. BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
75366. BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
75367. BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
75368. BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
75369. BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
75370. BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
75371. BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
75372. BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
75373. BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
75374. BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
75375. BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
75376. BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
75377. BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
75378. BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
75379. BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
75380. BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
75381. BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
75382. BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
75383. BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
75384. BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
75385. BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
75386. BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
75387. BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
75388. BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
75389. BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
75390. BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
75391. BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
75392. BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
75393. BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
75394. BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
75395. BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
75396. BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
75397. BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
75398. BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
75399. BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
75400. BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
75401. BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
75402. BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
75403. BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
75404. BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
75405. BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
75406. BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
75407. BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
75408. BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
75409. BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
75410. BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
75411. BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
75412. BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
75413. BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
75414. BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
75415. BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK
75416. BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
75417. BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK
75418. BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT
75419. BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK
75420. BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT
75421. BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
75422. BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
75423. BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
75424. BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
75425. BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
75426. BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
75427. BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
75428. BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
75429. BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
75430. BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
75431. BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
75432. BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
75433. BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK
75434. BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT
75435. BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK
75436. BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT
75437. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK
75438. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT
75439. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK
75440. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT
75441. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK
75442. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT
75443. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK
75444. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT
75445. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK
75446. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT
75447. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK
75448. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT
75449. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK
75450. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT
75451. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK
75452. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT
75453. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK
75454. BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT
75455. BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
75456. BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
75457. BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
75458. BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
75459. BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
75460. BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
75461. BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK
75462. BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
75463. BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
75464. BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
75465. BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
75466. BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
75467. BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
75468. BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
75469. BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
75470. BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
75471. BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
75472. BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
75473. BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
75474. BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
75475. BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
75476. BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
75477. BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
75478. BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
75479. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
75480. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
75481. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
75482. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
75483. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
75484. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
75485. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
75486. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
75487. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
75488. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
75489. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
75490. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
75491. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
75492. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
75493. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
75494. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
75495. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
75496. BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
75497. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
75498. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
75499. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
75500. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
75501. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
75502. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
75503. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
75504. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
75505. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
75506. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
75507. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
75508. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
75509. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
75510. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
75511. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK
75512. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
75513. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
75514. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
75515. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
75516. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
75517. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
75518. BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
75519. BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
75520. BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
75521. BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
75522. BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
75523. BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
75524. BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
75525. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK
75526. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT
75527. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK
75528. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT
75529. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK
75530. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT
75531. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
75532. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
75533. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK
75534. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT
75535. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK
75536. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT
75537. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK
75538. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT
75539. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK
75540. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT
75541. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK
75542. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT
75543. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK
75544. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
75545. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK
75546. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT
75547. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK
75548. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT
75549. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK
75550. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT
75551. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK
75552. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT
75553. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK
75554. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT
75555. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK
75556. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT
75557. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK
75558. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT
75559. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK
75560. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT
75561. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK
75562. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT
75563. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK
75564. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT
75565. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK
75566. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT
75567. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK
75568. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT
75569. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK
75570. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT
75571. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK
75572. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT
75573. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK
75574. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT
75575. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK
75576. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT
75577. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK
75578. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT
75579. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK
75580. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT
75581. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK
75582. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT
75583. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK
75584. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT
75585. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK
75586. BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT
75587. BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
75588. BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
75589. BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
75590. BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
75591. BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
75592. BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
75593. BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
75594. BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
75595. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
75596. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
75597. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
75598. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
75599. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
75600. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
75601. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
75602. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
75603. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
75604. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
75605. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
75606. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
75607. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
75608. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
75609. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
75610. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
75611. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
75612. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
75613. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
75614. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
75615. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
75616. BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
75617. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
75618. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
75619. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
75620. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
75621. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
75622. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
75623. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
75624. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
75625. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
75626. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
75627. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
75628. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
75629. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
75630. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
75631. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
75632. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
75633. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
75634. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
75635. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
75636. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
75637. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
75638. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
75639. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
75640. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
75641. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
75642. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
75643. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
75644. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
75645. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
75646. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
75647. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
75648. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
75649. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
75650. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
75651. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
75652. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
75653. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
75654. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
75655. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
75656. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
75657. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
75658. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
75659. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
75660. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
75661. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
75662. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
75663. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
75664. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
75665. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
75666. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
75667. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
75668. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
75669. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
75670. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
75671. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
75672. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
75673. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
75674. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
75675. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
75676. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
75677. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
75678. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
75679. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
75680. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
75681. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
75682. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
75683. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
75684. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
75685. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
75686. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
75687. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
75688. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
75689. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
75690. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
75691. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
75692. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
75693. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
75694. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
75695. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
75696. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
75697. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
75698. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
75699. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
75700. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
75701. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
75702. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
75703. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
75704. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
75705. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
75706. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
75707. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
75708. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
75709. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
75710. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
75711. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
75712. BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
75713. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
75714. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
75715. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
75716. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
75717. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
75718. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
75719. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
75720. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
75721. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
75722. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
75723. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
75724. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
75725. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
75726. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
75727. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
75728. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
75729. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
75730. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
75731. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
75732. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
75733. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
75734. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
75735. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
75736. BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
75737. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
75738. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
75739. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
75740. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
75741. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
75742. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
75743. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
75744. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
75745. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
75746. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
75747. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
75748. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
75749. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
75750. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
75751. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
75752. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
75753. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
75754. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
75755. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
75756. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
75757. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
75758. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
75759. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
75760. BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
75761. BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
75762. BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
75763. BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
75764. BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
75765. BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
75766. BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
75767. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
75768. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
75769. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
75770. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
75771. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK
75772. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT
75773. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK
75774. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT
75775. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK
75776. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT
75777. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
75778. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
75779. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
75780. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
75781. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
75782. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
75783. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK
75784. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT
75785. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK
75786. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT
75787. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK
75788. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT
75789. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK
75790. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT
75791. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK
75792. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT
75793. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK
75794. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT
75795. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK
75796. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT
75797. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK
75798. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT
75799. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK
75800. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT
75801. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK
75802. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT
75803. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK
75804. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT
75805. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK
75806. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT
75807. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK
75808. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT
75809. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK
75810. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT
75811. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK
75812. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT
75813. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK
75814. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT
75815. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK
75816. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT
75817. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK
75818. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT
75819. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK
75820. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT
75821. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK
75822. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT
75823. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK
75824. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT
75825. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK
75826. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT
75827. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK
75828. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT
75829. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK
75830. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT
75831. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK
75832. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT
75833. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK
75834. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT
75835. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK
75836. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT
75837. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK
75838. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT
75839. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK
75840. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT
75841. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK
75842. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT
75843. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK
75844. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT
75845. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK
75846. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT
75847. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK
75848. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT
75849. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK
75850. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT
75851. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK
75852. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT
75853. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK
75854. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT
75855. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK
75856. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT
75857. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK
75858. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT
75859. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK
75860. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT
75861. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK
75862. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT
75863. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK
75864. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT
75865. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK
75866. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT
75867. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK
75868. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT
75869. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK
75870. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT
75871. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK
75872. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT
75873. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK
75874. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT
75875. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK
75876. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT
75877. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK
75878. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT
75879. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK
75880. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT
75881. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK
75882. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT
75883. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK
75884. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT
75885. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK
75886. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT
75887. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK
75888. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT
75889. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK
75890. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT
75891. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK
75892. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT
75893. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK
75894. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT
75895. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK
75896. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT
75897. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK
75898. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT
75899. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK
75900. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT
75901. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK
75902. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT
75903. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK
75904. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT
75905. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK
75906. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT
75907. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK
75908. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT
75909. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK
75910. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT
75911. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK
75912. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT
75913. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK
75914. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT
75915. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK
75916. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT
75917. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK
75918. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT
75919. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK
75920. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT
75921. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK
75922. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT
75923. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK
75924. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT
75925. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK
75926. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT
75927. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK
75928. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT
75929. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK
75930. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT
75931. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK
75932. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT
75933. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK
75934. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT
75935. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK
75936. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT
75937. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK
75938. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT
75939. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK
75940. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT
75941. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK
75942. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT
75943. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK
75944. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT
75945. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK
75946. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT
75947. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK
75948. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT
75949. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK
75950. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT
75951. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK
75952. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT
75953. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK
75954. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT
75955. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK
75956. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT
75957. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK
75958. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT
75959. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK
75960. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT
75961. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK
75962. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT
75963. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK
75964. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT
75965. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK
75966. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT
75967. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK
75968. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT
75969. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK
75970. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT
75971. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK
75972. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT
75973. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK
75974. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT
75975. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK
75976. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT
75977. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK
75978. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT
75979. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK
75980. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT
75981. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK
75982. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT
75983. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK
75984. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT
75985. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK
75986. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
75987. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK
75988. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
75989. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK
75990. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT
75991. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK
75992. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT
75993. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK
75994. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT
75995. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK
75996. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT
75997. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK
75998. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
75999. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK
76000. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
76001. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK
76002. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT
76003. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK
76004. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT
76005. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK
76006. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
76007. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK
76008. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
76009. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK
76010. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT
76011. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK
76012. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT
76013. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK
76014. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
76015. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK
76016. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
76017. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK
76018. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT
76019. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK
76020. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT
76021. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK
76022. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT
76023. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK
76024. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT
76025. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK
76026. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT
76027. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK
76028. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT
76029. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK
76030. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT
76031. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK
76032. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT
76033. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK
76034. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT
76035. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK
76036. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT
76037. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK
76038. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT
76039. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK
76040. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT
76041. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK
76042. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT
76043. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK
76044. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT
76045. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK
76046. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT
76047. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK
76048. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT
76049. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK
76050. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT
76051. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK
76052. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT
76053. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK
76054. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT
76055. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK
76056. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT
76057. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK
76058. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT
76059. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK
76060. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT
76061. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK
76062. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT
76063. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK
76064. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT
76065. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK
76066. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT
76067. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK
76068. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT
76069. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK
76070. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT
76071. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK
76072. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT
76073. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK
76074. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT
76075. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK
76076. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT
76077. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK
76078. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT
76079. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK
76080. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT
76081. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK
76082. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT
76083. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK
76084. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT
76085. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK
76086. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT
76087. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK
76088. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT
76089. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK
76090. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT
76091. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK
76092. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT
76093. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK
76094. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT
76095. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK
76096. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT
76097. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK
76098. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT
76099. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK
76100. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT
76101. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK
76102. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT
76103. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK
76104. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT
76105. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK
76106. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT
76107. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK
76108. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT
76109. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK
76110. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT
76111. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK
76112. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT
76113. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK
76114. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT
76115. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK
76116. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT
76117. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK
76118. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT
76119. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK
76120. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT
76121. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK
76122. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT
76123. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK
76124. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT
76125. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK
76126. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT
76127. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK
76128. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT
76129. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK
76130. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT
76131. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK
76132. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT
76133. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK
76134. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT
76135. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK
76136. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT
76137. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK
76138. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT
76139. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK
76140. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT
76141. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK
76142. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT
76143. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK
76144. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT
76145. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK
76146. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT
76147. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK
76148. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT
76149. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK
76150. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT
76151. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK
76152. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT
76153. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK
76154. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT
76155. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK
76156. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT
76157. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK
76158. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT
76159. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK
76160. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT
76161. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK
76162. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT
76163. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK
76164. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT
76165. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK
76166. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT
76167. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK
76168. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT
76169. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK
76170. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT
76171. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK
76172. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT
76173. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK
76174. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT
76175. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK
76176. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT
76177. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK
76178. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT
76179. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK
76180. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT
76181. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK
76182. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT
76183. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK
76184. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT
76185. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK
76186. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT
76187. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK
76188. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT
76189. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK
76190. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT
76191. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK
76192. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT
76193. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK
76194. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT
76195. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK
76196. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT
76197. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK
76198. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT
76199. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK
76200. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT
76201. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK
76202. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT
76203. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK
76204. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT
76205. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK
76206. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT
76207. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK
76208. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT
76209. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK
76210. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT
76211. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK
76212. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT
76213. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK
76214. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT
76215. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK
76216. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT
76217. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK
76218. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT
76219. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK
76220. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT
76221. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK
76222. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT
76223. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK
76224. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT
76225. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK
76226. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT
76227. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
76228. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
76229. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
76230. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
76231. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
76232. BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
76233. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK
76234. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
76235. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK
76236. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT
76237. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK
76238. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT
76239. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK
76240. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT
76241. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK
76242. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
76243. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK
76244. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT
76245. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK
76246. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT
76247. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK
76248. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT
76249. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK
76250. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
76251. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK
76252. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT
76253. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK
76254. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT
76255. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK
76256. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT
76257. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK
76258. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
76259. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK
76260. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT
76261. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK
76262. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT
76263. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK
76264. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT
76265. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK
76266. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
76267. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK
76268. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT
76269. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK
76270. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT
76271. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK
76272. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT
76273. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK
76274. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
76275. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK
76276. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT
76277. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK
76278. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT
76279. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK
76280. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT
76281. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK
76282. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
76283. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK
76284. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
76285. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
76286. BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
76287. BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK
76288. BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT
76289. BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK
76290. BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT
76291. BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK
76292. BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT
76293. BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK
76294. BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT
76295. BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK
76296. BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT
76297. BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
76298. BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
76299. BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
76300. BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
76301. BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK
76302. BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT
76303. BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK
76304. BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT
76305. BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK
76306. BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT
76307. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
76308. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
76309. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
76310. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
76311. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK
76312. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
76313. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK
76314. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
76315. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
76316. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
76317. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK
76318. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT
76319. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK
76320. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
76321. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK
76322. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
76323. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK
76324. BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
76325. BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK
76326. BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
76327. BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK
76328. BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT
76329. BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK
76330. BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT
76331. BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK
76332. BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
76333. BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK
76334. BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT
76335. BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK
76336. BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT
76337. BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK
76338. BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT
76339. BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK
76340. BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT
76341. BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK
76342. BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT
76343. BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK
76344. BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT
76345. BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK
76346. BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT
76347. BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
76348. BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
76349. BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK
76350. BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT
76351. BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK
76352. BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT
76353. BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK
76354. BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
76355. BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK
76356. BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
76357. BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
76358. BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
76359. BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK
76360. BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
76361. BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK
76362. BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT
76363. BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK
76364. BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT
76365. BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK
76366. BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT
76367. BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK
76368. BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
76369. BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK
76370. BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT
76371. BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
76372. BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
76373. BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
76374. BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
76375. BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR_MASK
76376. BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT
76377. BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR_MASK
76378. BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT
76379. BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR_MASK
76380. BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT
76381. BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR_MASK
76382. BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT
76383. BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR_MASK
76384. BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT
76385. BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR_MASK
76386. BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT
76387. BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS_MASK
76388. BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS__SHIFT
76389. BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP_MASK
76390. BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP__SHIFT
76391. BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP_MASK
76392. BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP__SHIFT
76393. BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT_MASK
76394. BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT__SHIFT
76395. BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
76396. BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
76397. BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR_MASK
76398. BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR__SHIFT
76399. BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
76400. BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
76401. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING_MASK
76402. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING__SHIFT
76403. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN_MASK
76404. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN__SHIFT
76405. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN_MASK
76406. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN__SHIFT
76407. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS_MASK
76408. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS__SHIFT
76409. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN_MASK
76410. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN__SHIFT
76411. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN_MASK
76412. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN__SHIFT
76413. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
76414. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
76415. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN_MASK
76416. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN__SHIFT
76417. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
76418. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
76419. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN_MASK
76420. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN__SHIFT
76421. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK
76422. BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
76423. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
76424. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
76425. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
76426. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
76427. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
76428. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
76429. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
76430. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
76431. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
76432. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
76433. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
76434. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
76435. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
76436. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
76437. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
76438. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
76439. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
76440. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
76441. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
76442. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
76443. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
76444. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
76445. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
76446. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
76447. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
76448. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
76449. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
76450. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
76451. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
76452. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
76453. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
76454. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
76455. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
76456. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
76457. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
76458. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
76459. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
76460. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
76461. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
76462. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
76463. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
76464. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
76465. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
76466. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
76467. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG_MASK
76468. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
76469. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE_MASK
76470. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
76471. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
76472. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
76473. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
76474. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
76475. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
76476. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
76477. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK
76478. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
76479. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
76480. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
76481. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
76482. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
76483. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
76484. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
76485. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
76486. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
76487. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
76488. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
76489. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
76490. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
76491. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
76492. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
76493. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
76494. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
76495. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
76496. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
76497. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
76498. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
76499. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN_MASK
76500. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN__SHIFT
76501. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN_MASK
76502. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT
76503. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
76504. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
76505. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
76506. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
76507. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK
76508. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
76509. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
76510. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
76511. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
76512. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
76513. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR_MASK
76514. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
76515. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
76516. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
76517. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
76518. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
76519. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
76520. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
76521. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
76522. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
76523. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
76524. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
76525. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
76526. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
76527. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK
76528. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
76529. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID_MASK
76530. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID__SHIFT
76531. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED_MASK
76532. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED__SHIFT
76533. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR_MASK
76534. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR__SHIFT
76535. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR_MASK
76536. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR__SHIFT
76537. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
76538. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
76539. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR_MASK
76540. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT
76541. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
76542. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
76543. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
76544. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
76545. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED_MASK
76546. BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT
76547. BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE_MASK
76548. BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE__SHIFT
76549. BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE_MASK
76550. BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE__SHIFT
76551. BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
76552. BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
76553. BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
76554. BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
76555. BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER_MASK
76556. BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER__SHIFT
76557. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
76558. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
76559. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
76560. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
76561. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
76562. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
76563. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
76564. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
76565. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RESERVED_MASK
76566. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RESERVED__SHIFT
76567. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
76568. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
76569. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
76570. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
76571. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
76572. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
76573. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
76574. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
76575. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
76576. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
76577. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
76578. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
76579. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
76580. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
76581. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK
76582. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
76583. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
76584. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
76585. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED_MASK
76586. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED__SHIFT
76587. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH_MASK
76588. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH__SHIFT
76589. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT_MASK
76590. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT__SHIFT
76591. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER_MASK
76592. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER__SHIFT
76593. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
76594. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
76595. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
76596. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
76597. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
76598. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
76599. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
76600. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
76601. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
76602. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
76603. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
76604. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
76605. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
76606. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
76607. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
76608. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
76609. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN_MASK
76610. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
76611. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
76612. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
76613. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
76614. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
76615. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
76616. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
76617. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC_MASK
76618. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
76619. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
76620. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
76621. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
76622. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
76623. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
76624. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
76625. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS_MASK
76626. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS__SHIFT
76627. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL_MASK
76628. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL__SHIFT
76629. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
76630. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
76631. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK_MASK
76632. BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT
76633. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
76634. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
76635. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
76636. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
76637. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
76638. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
76639. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
76640. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
76641. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
76642. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
76643. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
76644. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
76645. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
76646. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
76647. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
76648. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
76649. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
76650. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
76651. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
76652. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
76653. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
76654. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
76655. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
76656. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
76657. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
76658. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
76659. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
76660. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
76661. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
76662. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
76663. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
76664. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
76665. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
76666. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
76667. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE_MASK
76668. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE__SHIFT
76669. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
76670. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
76671. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
76672. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
76673. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING_MASK
76674. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING__SHIFT
76675. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
76676. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
76677. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
76678. BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
76679. BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY__MAX_LAT_MASK
76680. BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY__MAX_LAT__SHIFT
76681. BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT__MIN_GNT_MASK
76682. BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT__MIN_GNT__SHIFT
76683. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID_MASK
76684. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT
76685. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK
76686. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
76687. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK
76688. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
76689. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
76690. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
76691. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
76692. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
76693. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK
76694. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
76695. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
76696. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
76697. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
76698. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
76699. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
76700. BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
76701. BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID_MASK
76702. BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID__SHIFT
76703. BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR_MASK
76704. BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
76705. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64_MASK
76706. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT
76707. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK_MASK
76708. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK__SHIFT
76709. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
76710. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
76711. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
76712. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
76713. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK
76714. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
76715. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN_MASK
76716. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT
76717. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
76718. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
76719. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
76720. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
76721. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
76722. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
76723. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
76724. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
76725. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA_MASK
76726. BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT
76727. BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK
76728. BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
76729. BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING_MASK
76730. BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING__SHIFT
76731. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
76732. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
76733. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
76734. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
76735. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
76736. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
76737. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
76738. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
76739. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
76740. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
76741. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
76742. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
76743. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
76744. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
76745. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
76746. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
76747. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
76748. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
76749. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
76750. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
76751. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
76752. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
76753. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
76754. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
76755. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
76756. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
76757. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
76758. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
76759. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
76760. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
76761. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
76762. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
76763. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
76764. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
76765. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
76766. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
76767. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
76768. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
76769. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
76770. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
76771. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
76772. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
76773. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
76774. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
76775. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
76776. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
76777. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
76778. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
76779. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
76780. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
76781. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__STU_MASK
76782. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__STU__SHIFT
76783. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
76784. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
76785. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
76786. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
76787. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
76788. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
76789. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID_MASK
76790. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT
76791. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK
76792. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
76793. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE_MASK
76794. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT
76795. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
76796. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
76797. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
76798. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
76799. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION_MASK
76800. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION__SHIFT
76801. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
76802. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
76803. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
76804. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
76805. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
76806. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
76807. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
76808. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
76809. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
76810. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
76811. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
76812. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
76813. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
76814. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
76815. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
76816. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
76817. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
76818. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
76819. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
76820. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
76821. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
76822. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
76823. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
76824. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
76825. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
76826. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
76827. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
76828. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
76829. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
76830. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
76831. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
76832. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
76833. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK
76834. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
76835. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK
76836. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
76837. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK
76838. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
76839. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK
76840. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
76841. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
76842. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
76843. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
76844. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
76845. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
76846. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
76847. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
76848. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
76849. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
76850. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
76851. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
76852. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
76853. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
76854. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
76855. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
76856. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
76857. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
76858. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
76859. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
76860. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
76861. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
76862. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
76863. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
76864. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
76865. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
76866. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
76867. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
76868. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
76869. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
76870. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
76871. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
76872. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
76873. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
76874. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
76875. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
76876. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
76877. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
76878. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
76879. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
76880. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
76881. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
76882. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
76883. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
76884. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
76885. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
76886. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
76887. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
76888. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
76889. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
76890. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
76891. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
76892. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
76893. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
76894. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
76895. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
76896. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
76897. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
76898. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
76899. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
76900. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
76901. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
76902. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
76903. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
76904. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
76905. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
76906. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
76907. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
76908. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
76909. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
76910. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
76911. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
76912. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
76913. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
76914. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
76915. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
76916. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
76917. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
76918. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
76919. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
76920. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
76921. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
76922. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
76923. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
76924. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
76925. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
76926. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
76927. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
76928. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
76929. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
76930. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
76931. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
76932. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
76933. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
76934. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
76935. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
76936. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
76937. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
76938. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
76939. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
76940. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
76941. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
76942. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
76943. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
76944. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
76945. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
76946. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
76947. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
76948. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
76949. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
76950. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
76951. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
76952. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
76953. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
76954. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
76955. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
76956. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
76957. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
76958. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
76959. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
76960. BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
76961. BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK
76962. BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
76963. BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID_MASK
76964. BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT
76965. BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID_MASK
76966. BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID__SHIFT
76967. BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK
76968. BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
76969. BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2__RESERVED_MASK
76970. BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2__RESERVED__SHIFT
76971. BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2__RESERVED_MASK
76972. BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2__RESERVED__SHIFT
76973. BIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2__RESERVED_MASK
76974. BIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2__RESERVED__SHIFT
76975. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST_MASK
76976. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST__SHIFT
76977. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING_MASK
76978. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING__SHIFT
76979. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE_MASK
76980. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT
76981. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__IMMEDIATE_READINESS_MASK
76982. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__IMMEDIATE_READINESS__SHIFT
76983. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS_MASK
76984. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS__SHIFT
76985. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
76986. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
76987. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED_MASK
76988. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
76989. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_CAP_MASK
76990. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_CAP__SHIFT
76991. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_EN_MASK
76992. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_EN__SHIFT
76993. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK
76994. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
76995. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK
76996. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
76997. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
76998. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
76999. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK
77000. BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
77001. BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS_MASK
77002. BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS__SHIFT
77003. BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID_MASK
77004. BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID__SHIFT
77005. BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
77006. BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
77007. BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
77008. BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
77009. BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR_MASK
77010. BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT
77011. BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR_MASK
77012. BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT
77013. BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR_MASK
77014. BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT
77015. BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR_MASK
77016. BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT
77017. BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR_MASK
77018. BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT
77019. BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR_MASK
77020. BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT
77021. BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS_MASK
77022. BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS__SHIFT
77023. BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP_MASK
77024. BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP__SHIFT
77025. BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP_MASK
77026. BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP__SHIFT
77027. BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT_MASK
77028. BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT__SHIFT
77029. BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
77030. BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
77031. BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR_MASK
77032. BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR__SHIFT
77033. BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
77034. BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
77035. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING_MASK
77036. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING__SHIFT
77037. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN_MASK
77038. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN__SHIFT
77039. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN_MASK
77040. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN__SHIFT
77041. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS_MASK
77042. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS__SHIFT
77043. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN_MASK
77044. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN__SHIFT
77045. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN_MASK
77046. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN__SHIFT
77047. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
77048. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
77049. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN_MASK
77050. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN__SHIFT
77051. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
77052. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
77053. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN_MASK
77054. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN__SHIFT
77055. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK
77056. BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
77057. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
77058. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
77059. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
77060. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
77061. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
77062. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
77063. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
77064. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
77065. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
77066. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
77067. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
77068. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
77069. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
77070. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
77071. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
77072. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
77073. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
77074. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
77075. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
77076. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
77077. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
77078. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
77079. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
77080. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
77081. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
77082. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
77083. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
77084. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
77085. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
77086. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
77087. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
77088. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
77089. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
77090. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
77091. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
77092. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
77093. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
77094. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
77095. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
77096. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
77097. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
77098. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
77099. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
77100. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
77101. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG_MASK
77102. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
77103. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE_MASK
77104. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
77105. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
77106. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
77107. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
77108. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
77109. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
77110. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
77111. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK
77112. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
77113. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
77114. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
77115. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
77116. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
77117. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
77118. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
77119. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
77120. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
77121. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
77122. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
77123. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
77124. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
77125. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
77126. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
77127. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
77128. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
77129. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
77130. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
77131. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
77132. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
77133. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN_MASK
77134. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN__SHIFT
77135. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN_MASK
77136. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT
77137. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
77138. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
77139. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
77140. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
77141. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK
77142. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
77143. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
77144. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
77145. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
77146. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
77147. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR_MASK
77148. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
77149. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
77150. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
77151. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
77152. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
77153. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
77154. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
77155. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
77156. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
77157. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
77158. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
77159. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
77160. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
77161. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK
77162. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
77163. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID_MASK
77164. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID__SHIFT
77165. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED_MASK
77166. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED__SHIFT
77167. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR_MASK
77168. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR__SHIFT
77169. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR_MASK
77170. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR__SHIFT
77171. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
77172. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
77173. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR_MASK
77174. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT
77175. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
77176. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
77177. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
77178. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
77179. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED_MASK
77180. BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT
77181. BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE_MASK
77182. BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE__SHIFT
77183. BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE_MASK
77184. BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE__SHIFT
77185. BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
77186. BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
77187. BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
77188. BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
77189. BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER_MASK
77190. BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER__SHIFT
77191. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
77192. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
77193. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
77194. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
77195. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
77196. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
77197. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
77198. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
77199. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RESERVED_MASK
77200. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RESERVED__SHIFT
77201. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
77202. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
77203. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
77204. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
77205. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
77206. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
77207. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
77208. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
77209. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
77210. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
77211. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
77212. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
77213. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
77214. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
77215. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK
77216. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
77217. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
77218. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
77219. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED_MASK
77220. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED__SHIFT
77221. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH_MASK
77222. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH__SHIFT
77223. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT_MASK
77224. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT__SHIFT
77225. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER_MASK
77226. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER__SHIFT
77227. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
77228. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
77229. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
77230. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
77231. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
77232. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
77233. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
77234. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
77235. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
77236. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
77237. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
77238. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
77239. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
77240. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
77241. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
77242. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
77243. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN_MASK
77244. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
77245. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
77246. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
77247. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
77248. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
77249. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
77250. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
77251. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC_MASK
77252. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
77253. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
77254. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
77255. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
77256. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
77257. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
77258. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
77259. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS_MASK
77260. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS__SHIFT
77261. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL_MASK
77262. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL__SHIFT
77263. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
77264. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
77265. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK_MASK
77266. BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT
77267. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
77268. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
77269. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
77270. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
77271. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
77272. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
77273. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
77274. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
77275. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
77276. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
77277. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
77278. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
77279. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
77280. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
77281. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
77282. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
77283. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
77284. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
77285. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
77286. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
77287. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
77288. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
77289. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
77290. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
77291. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
77292. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
77293. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
77294. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
77295. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
77296. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
77297. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
77298. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
77299. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
77300. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
77301. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE_MASK
77302. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE__SHIFT
77303. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
77304. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
77305. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
77306. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
77307. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING_MASK
77308. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING__SHIFT
77309. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
77310. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
77311. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
77312. BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
77313. BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY__MAX_LAT_MASK
77314. BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY__MAX_LAT__SHIFT
77315. BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT__MIN_GNT_MASK
77316. BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT__MIN_GNT__SHIFT
77317. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID_MASK
77318. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT
77319. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK
77320. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
77321. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK
77322. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
77323. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
77324. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
77325. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
77326. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
77327. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK
77328. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
77329. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
77330. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
77331. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
77332. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
77333. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
77334. BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
77335. BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID_MASK
77336. BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID__SHIFT
77337. BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR_MASK
77338. BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
77339. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64_MASK
77340. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT
77341. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK_MASK
77342. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK__SHIFT
77343. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
77344. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
77345. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
77346. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
77347. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK
77348. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
77349. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN_MASK
77350. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT
77351. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
77352. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
77353. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
77354. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
77355. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
77356. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
77357. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
77358. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
77359. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA_MASK
77360. BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT
77361. BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK
77362. BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
77363. BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING_MASK
77364. BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING__SHIFT
77365. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
77366. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
77367. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
77368. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
77369. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
77370. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
77371. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
77372. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
77373. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
77374. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
77375. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
77376. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
77377. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
77378. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
77379. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
77380. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
77381. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
77382. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
77383. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
77384. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
77385. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
77386. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
77387. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
77388. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
77389. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
77390. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
77391. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
77392. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
77393. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
77394. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
77395. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
77396. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
77397. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
77398. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
77399. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
77400. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
77401. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
77402. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
77403. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
77404. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
77405. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
77406. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
77407. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
77408. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
77409. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
77410. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
77411. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
77412. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
77413. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
77414. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
77415. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__STU_MASK
77416. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__STU__SHIFT
77417. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
77418. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
77419. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
77420. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
77421. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
77422. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
77423. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID_MASK
77424. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT
77425. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK
77426. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
77427. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE_MASK
77428. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT
77429. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
77430. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
77431. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
77432. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
77433. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION_MASK
77434. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION__SHIFT
77435. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
77436. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
77437. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
77438. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
77439. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
77440. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
77441. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
77442. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
77443. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
77444. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
77445. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
77446. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
77447. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
77448. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
77449. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
77450. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
77451. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
77452. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
77453. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
77454. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
77455. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
77456. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
77457. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
77458. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
77459. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
77460. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
77461. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
77462. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
77463. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
77464. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
77465. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
77466. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
77467. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK
77468. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
77469. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK
77470. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
77471. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK
77472. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
77473. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK
77474. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
77475. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
77476. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
77477. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
77478. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
77479. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
77480. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
77481. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
77482. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
77483. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
77484. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
77485. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
77486. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
77487. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
77488. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
77489. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
77490. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
77491. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
77492. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
77493. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
77494. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
77495. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
77496. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
77497. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
77498. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
77499. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
77500. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
77501. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
77502. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
77503. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
77504. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
77505. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
77506. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
77507. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
77508. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
77509. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
77510. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
77511. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
77512. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
77513. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
77514. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
77515. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
77516. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
77517. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
77518. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
77519. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
77520. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
77521. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
77522. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
77523. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
77524. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
77525. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
77526. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
77527. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
77528. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
77529. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
77530. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
77531. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
77532. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
77533. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
77534. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
77535. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
77536. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
77537. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
77538. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
77539. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
77540. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
77541. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
77542. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
77543. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
77544. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
77545. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
77546. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
77547. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
77548. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
77549. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
77550. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
77551. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
77552. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
77553. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
77554. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
77555. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
77556. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
77557. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
77558. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
77559. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
77560. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
77561. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
77562. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
77563. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
77564. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
77565. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
77566. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
77567. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
77568. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
77569. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
77570. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
77571. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
77572. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
77573. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
77574. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
77575. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
77576. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
77577. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
77578. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
77579. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
77580. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
77581. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
77582. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
77583. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
77584. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
77585. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
77586. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
77587. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
77588. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
77589. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
77590. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
77591. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
77592. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
77593. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
77594. BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
77595. BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK
77596. BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
77597. BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID_MASK
77598. BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT
77599. BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID_MASK
77600. BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID__SHIFT
77601. BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK
77602. BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
77603. BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CAP2__RESERVED_MASK
77604. BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CAP2__RESERVED__SHIFT
77605. BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CNTL2__RESERVED_MASK
77606. BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CNTL2__RESERVED__SHIFT
77607. BIF_CFG_DEV0_EPF0_VF0_1_SLOT_STATUS2__RESERVED_MASK
77608. BIF_CFG_DEV0_EPF0_VF0_1_SLOT_STATUS2__RESERVED__SHIFT
77609. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST_MASK
77610. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST__SHIFT
77611. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING_MASK
77612. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING__SHIFT
77613. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE_MASK
77614. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT
77615. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__IMMEDIATE_READINESS_MASK
77616. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__IMMEDIATE_READINESS__SHIFT
77617. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS_MASK
77618. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS__SHIFT
77619. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
77620. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
77621. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED_MASK
77622. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
77623. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_CAP_MASK
77624. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_CAP__SHIFT
77625. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_EN_MASK
77626. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_EN__SHIFT
77627. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK
77628. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
77629. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK
77630. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
77631. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
77632. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
77633. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK
77634. BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
77635. BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS_MASK
77636. BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS__SHIFT
77637. BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID_MASK
77638. BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID__SHIFT
77639. BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK
77640. BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
77641. BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
77642. BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
77643. BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK
77644. BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT
77645. BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK
77646. BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT
77647. BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK
77648. BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT
77649. BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK
77650. BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT
77651. BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK
77652. BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT
77653. BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK
77654. BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT
77655. BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK
77656. BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT
77657. BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK
77658. BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT
77659. BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK
77660. BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT
77661. BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK
77662. BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT
77663. BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK
77664. BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
77665. BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK
77666. BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT
77667. BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
77668. BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
77669. BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK
77670. BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT
77671. BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK
77672. BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT
77673. BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK
77674. BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT
77675. BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK
77676. BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT
77677. BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK
77678. BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT
77679. BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK
77680. BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT
77681. BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
77682. BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
77683. BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK
77684. BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT
77685. BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK
77686. BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
77687. BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK
77688. BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT
77689. BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK
77690. BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
77691. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
77692. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
77693. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
77694. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
77695. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
77696. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
77697. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
77698. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
77699. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
77700. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
77701. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
77702. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
77703. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
77704. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
77705. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
77706. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
77707. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
77708. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
77709. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
77710. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
77711. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
77712. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
77713. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK
77714. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
77715. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
77716. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
77717. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK
77718. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
77719. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
77720. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
77721. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
77722. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
77723. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
77724. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
77725. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
77726. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
77727. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
77728. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
77729. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
77730. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
77731. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
77732. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
77733. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
77734. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
77735. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK
77736. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT
77737. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK
77738. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT
77739. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
77740. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
77741. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
77742. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
77743. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
77744. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
77745. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK
77746. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
77747. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
77748. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
77749. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
77750. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
77751. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
77752. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
77753. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
77754. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
77755. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
77756. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
77757. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
77758. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
77759. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
77760. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
77761. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
77762. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
77763. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
77764. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
77765. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
77766. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
77767. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK
77768. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT
77769. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK
77770. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT
77771. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
77772. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
77773. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
77774. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
77775. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK
77776. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
77777. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
77778. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
77779. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK
77780. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
77781. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK
77782. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT
77783. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
77784. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
77785. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
77786. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
77787. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
77788. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
77789. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK
77790. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
77791. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
77792. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
77793. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
77794. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
77795. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK
77796. BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
77797. BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK
77798. BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT
77799. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK
77800. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT
77801. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK
77802. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT
77803. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK
77804. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT
77805. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
77806. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
77807. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK
77808. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT
77809. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK
77810. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
77811. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
77812. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
77813. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK
77814. BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT
77815. BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE_MASK
77816. BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE__SHIFT
77817. BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE_MASK
77818. BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE__SHIFT
77819. BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
77820. BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
77821. BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
77822. BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
77823. BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK
77824. BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT
77825. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
77826. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
77827. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
77828. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
77829. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
77830. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
77831. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
77832. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
77833. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
77834. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
77835. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
77836. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
77837. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
77838. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
77839. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
77840. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
77841. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
77842. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
77843. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
77844. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
77845. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK
77846. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
77847. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK
77848. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
77849. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
77850. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
77851. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK
77852. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT
77853. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK
77854. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT
77855. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK
77856. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT
77857. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK
77858. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT
77859. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
77860. BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
77861. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
77862. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
77863. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK
77864. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
77865. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
77866. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
77867. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
77868. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
77869. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
77870. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
77871. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
77872. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
77873. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
77874. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
77875. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK
77876. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT
77877. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
77878. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
77879. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
77880. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
77881. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
77882. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
77883. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK
77884. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT
77885. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
77886. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
77887. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
77888. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
77889. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
77890. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
77891. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK
77892. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT
77893. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK
77894. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT
77895. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
77896. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
77897. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK
77898. BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT
77899. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
77900. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
77901. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
77902. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
77903. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
77904. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
77905. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
77906. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
77907. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
77908. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
77909. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
77910. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
77911. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
77912. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
77913. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
77914. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
77915. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
77916. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
77917. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
77918. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
77919. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
77920. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
77921. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
77922. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
77923. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK
77924. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT
77925. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
77926. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
77927. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
77928. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
77929. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK
77930. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT
77931. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
77932. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
77933. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
77934. BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
77935. BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK
77936. BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT
77937. BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK
77938. BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT
77939. BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK
77940. BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT
77941. BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK
77942. BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
77943. BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK
77944. BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
77945. BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
77946. BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
77947. BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
77948. BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
77949. BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK
77950. BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
77951. BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
77952. BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
77953. BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
77954. BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
77955. BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
77956. BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
77957. BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK
77958. BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT
77959. BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK
77960. BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT
77961. BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK
77962. BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT
77963. BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK
77964. BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT
77965. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
77966. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
77967. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
77968. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
77969. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK
77970. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
77971. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK
77972. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT
77973. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
77974. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
77975. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
77976. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
77977. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
77978. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
77979. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
77980. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
77981. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK
77982. BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT
77983. BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK
77984. BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
77985. BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK
77986. BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT
77987. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
77988. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
77989. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
77990. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
77991. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
77992. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
77993. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
77994. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
77995. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
77996. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
77997. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
77998. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
77999. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
78000. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
78001. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
78002. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
78003. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
78004. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
78005. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
78006. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
78007. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
78008. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
78009. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
78010. BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
78011. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
78012. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
78013. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
78014. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
78015. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
78016. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
78017. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
78018. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
78019. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
78020. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
78021. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
78022. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
78023. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
78024. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
78025. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
78026. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
78027. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
78028. BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
78029. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
78030. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
78031. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
78032. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
78033. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
78034. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
78035. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
78036. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
78037. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU_MASK
78038. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU__SHIFT
78039. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
78040. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
78041. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
78042. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
78043. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
78044. BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
78045. BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK
78046. BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT
78047. BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK
78048. BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
78049. BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK
78050. BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT
78051. BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK
78052. BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
78053. BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
78054. BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
78055. BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK
78056. BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT
78057. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
78058. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
78059. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
78060. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
78061. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
78062. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
78063. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
78064. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
78065. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
78066. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
78067. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
78068. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
78069. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
78070. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
78071. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
78072. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
78073. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
78074. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
78075. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
78076. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
78077. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
78078. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
78079. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
78080. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
78081. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
78082. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
78083. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
78084. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
78085. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
78086. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
78087. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
78088. BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
78089. BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK
78090. BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
78091. BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK
78092. BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
78093. BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK
78094. BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
78095. BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK
78096. BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
78097. BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
78098. BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
78099. BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
78100. BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
78101. BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
78102. BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
78103. BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
78104. BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
78105. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
78106. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
78107. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
78108. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
78109. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
78110. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
78111. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
78112. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
78113. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
78114. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
78115. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
78116. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
78117. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
78118. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
78119. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
78120. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
78121. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
78122. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
78123. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
78124. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
78125. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
78126. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
78127. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
78128. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
78129. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
78130. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
78131. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
78132. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
78133. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
78134. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
78135. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
78136. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
78137. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
78138. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
78139. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
78140. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
78141. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
78142. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
78143. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
78144. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
78145. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
78146. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
78147. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
78148. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
78149. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
78150. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
78151. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
78152. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
78153. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
78154. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
78155. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
78156. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
78157. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
78158. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
78159. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
78160. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
78161. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
78162. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
78163. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
78164. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
78165. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
78166. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
78167. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
78168. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
78169. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
78170. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
78171. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
78172. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
78173. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
78174. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
78175. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
78176. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
78177. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
78178. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
78179. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
78180. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
78181. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
78182. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
78183. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
78184. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
78185. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
78186. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
78187. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
78188. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
78189. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
78190. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
78191. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
78192. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
78193. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
78194. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
78195. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
78196. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
78197. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
78198. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
78199. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
78200. BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
78201. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
78202. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
78203. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
78204. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
78205. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
78206. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
78207. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
78208. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
78209. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
78210. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
78211. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
78212. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
78213. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
78214. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
78215. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
78216. BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
78217. BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK
78218. BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
78219. BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK
78220. BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT
78221. BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK
78222. BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT
78223. BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK
78224. BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
78225. BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK
78226. BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT
78227. BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK
78228. BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT
78229. BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK
78230. BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT
78231. BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK
78232. BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT
78233. BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK
78234. BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT
78235. BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
78236. BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
78237. BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK
78238. BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT
78239. BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK
78240. BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT
78241. BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK
78242. BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
78243. BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK
78244. BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
78245. BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
78246. BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
78247. BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK
78248. BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
78249. BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK
78250. BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT
78251. BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK
78252. BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT
78253. BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
78254. BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
78255. BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
78256. BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
78257. BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR_MASK
78258. BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR__SHIFT
78259. BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR_MASK
78260. BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR__SHIFT
78261. BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR_MASK
78262. BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR__SHIFT
78263. BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR_MASK
78264. BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR__SHIFT
78265. BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR_MASK
78266. BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR__SHIFT
78267. BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR_MASK
78268. BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR__SHIFT
78269. BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS_MASK
78270. BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS__SHIFT
78271. BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP_MASK
78272. BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP__SHIFT
78273. BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP_MASK
78274. BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP__SHIFT
78275. BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT_MASK
78276. BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT__SHIFT
78277. BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
78278. BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
78279. BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR_MASK
78280. BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR__SHIFT
78281. BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
78282. BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
78283. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING_MASK
78284. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING__SHIFT
78285. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN_MASK
78286. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN__SHIFT
78287. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN_MASK
78288. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN__SHIFT
78289. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS_MASK
78290. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS__SHIFT
78291. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN_MASK
78292. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN__SHIFT
78293. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN_MASK
78294. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN__SHIFT
78295. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
78296. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
78297. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN_MASK
78298. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN__SHIFT
78299. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
78300. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
78301. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN_MASK
78302. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN__SHIFT
78303. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN_MASK
78304. BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
78305. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
78306. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
78307. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
78308. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
78309. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
78310. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
78311. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
78312. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
78313. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
78314. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
78315. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
78316. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
78317. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
78318. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
78319. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
78320. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
78321. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
78322. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
78323. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
78324. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
78325. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
78326. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
78327. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
78328. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
78329. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
78330. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
78331. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
78332. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
78333. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
78334. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
78335. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
78336. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
78337. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
78338. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
78339. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
78340. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
78341. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
78342. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
78343. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
78344. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
78345. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
78346. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
78347. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
78348. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
78349. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG_MASK
78350. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
78351. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE_MASK
78352. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
78353. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
78354. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
78355. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
78356. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
78357. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
78358. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
78359. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC_MASK
78360. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
78361. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
78362. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
78363. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
78364. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
78365. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
78366. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
78367. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
78368. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
78369. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
78370. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
78371. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
78372. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
78373. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
78374. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
78375. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
78376. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
78377. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
78378. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
78379. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
78380. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
78381. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN_MASK
78382. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN__SHIFT
78383. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN_MASK
78384. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN__SHIFT
78385. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
78386. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
78387. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
78388. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
78389. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN_MASK
78390. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
78391. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
78392. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
78393. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
78394. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
78395. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR_MASK
78396. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
78397. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
78398. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
78399. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
78400. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
78401. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
78402. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
78403. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
78404. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
78405. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
78406. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
78407. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
78408. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
78409. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN_MASK
78410. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
78411. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID_MASK
78412. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID__SHIFT
78413. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED_MASK
78414. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED__SHIFT
78415. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR_MASK
78416. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR__SHIFT
78417. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR_MASK
78418. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR__SHIFT
78419. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
78420. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
78421. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR_MASK
78422. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR__SHIFT
78423. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
78424. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
78425. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
78426. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
78427. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED_MASK
78428. BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED__SHIFT
78429. BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE_MASK
78430. BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE__SHIFT
78431. BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE_MASK
78432. BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE__SHIFT
78433. BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
78434. BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
78435. BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
78436. BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
78437. BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER_MASK
78438. BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER__SHIFT
78439. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
78440. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
78441. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
78442. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
78443. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
78444. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
78445. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
78446. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
78447. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RESERVED_MASK
78448. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RESERVED__SHIFT
78449. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
78450. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
78451. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
78452. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
78453. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
78454. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
78455. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
78456. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
78457. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
78458. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
78459. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
78460. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
78461. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
78462. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
78463. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY_MASK
78464. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
78465. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
78466. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
78467. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED_MASK
78468. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED__SHIFT
78469. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH_MASK
78470. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH__SHIFT
78471. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT_MASK
78472. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT__SHIFT
78473. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER_MASK
78474. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER__SHIFT
78475. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
78476. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
78477. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
78478. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
78479. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
78480. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
78481. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
78482. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
78483. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
78484. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
78485. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
78486. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
78487. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
78488. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
78489. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
78490. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
78491. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN_MASK
78492. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
78493. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
78494. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
78495. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
78496. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
78497. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
78498. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
78499. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC_MASK
78500. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
78501. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
78502. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
78503. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
78504. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
78505. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
78506. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
78507. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS_MASK
78508. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS__SHIFT
78509. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL_MASK
78510. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL__SHIFT
78511. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
78512. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
78513. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK_MASK
78514. BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK__SHIFT
78515. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
78516. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
78517. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
78518. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
78519. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
78520. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
78521. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
78522. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
78523. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
78524. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
78525. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
78526. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
78527. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
78528. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
78529. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
78530. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
78531. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
78532. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
78533. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
78534. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
78535. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
78536. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
78537. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
78538. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
78539. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
78540. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
78541. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
78542. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
78543. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
78544. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
78545. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
78546. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
78547. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
78548. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
78549. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE_MASK
78550. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE__SHIFT
78551. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
78552. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
78553. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
78554. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
78555. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING_MASK
78556. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING__SHIFT
78557. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
78558. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
78559. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
78560. BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
78561. BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY__MAX_LAT_MASK
78562. BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY__MAX_LAT__SHIFT
78563. BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT__MIN_GNT_MASK
78564. BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT__MIN_GNT__SHIFT
78565. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID_MASK
78566. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID__SHIFT
78567. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR_MASK
78568. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
78569. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN_MASK
78570. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
78571. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
78572. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
78573. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
78574. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
78575. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR_MASK
78576. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
78577. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
78578. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
78579. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
78580. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
78581. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
78582. BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
78583. BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID_MASK
78584. BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID__SHIFT
78585. BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR_MASK
78586. BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
78587. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64_MASK
78588. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64__SHIFT
78589. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK_MASK
78590. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK__SHIFT
78591. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
78592. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
78593. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
78594. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
78595. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT_MASK
78596. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
78597. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN_MASK
78598. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN__SHIFT
78599. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
78600. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
78601. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
78602. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
78603. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
78604. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
78605. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
78606. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
78607. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA_MASK
78608. BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA__SHIFT
78609. BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64_MASK
78610. BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
78611. BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING_MASK
78612. BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING__SHIFT
78613. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
78614. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
78615. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
78616. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
78617. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
78618. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
78619. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
78620. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
78621. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
78622. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
78623. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
78624. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
78625. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
78626. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
78627. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
78628. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
78629. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
78630. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
78631. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
78632. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
78633. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
78634. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
78635. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
78636. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
78637. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
78638. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
78639. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
78640. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
78641. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
78642. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
78643. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
78644. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
78645. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
78646. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
78647. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
78648. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
78649. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
78650. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
78651. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
78652. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
78653. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
78654. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
78655. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
78656. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
78657. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
78658. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
78659. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
78660. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
78661. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
78662. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
78663. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__STU_MASK
78664. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__STU__SHIFT
78665. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
78666. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
78667. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
78668. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
78669. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
78670. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
78671. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID_MASK
78672. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID__SHIFT
78673. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR_MASK
78674. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
78675. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE_MASK
78676. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE__SHIFT
78677. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
78678. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
78679. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
78680. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
78681. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION_MASK
78682. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION__SHIFT
78683. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
78684. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
78685. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
78686. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
78687. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
78688. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
78689. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
78690. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
78691. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
78692. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
78693. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
78694. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
78695. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
78696. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
78697. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
78698. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
78699. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
78700. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
78701. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
78702. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
78703. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
78704. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
78705. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
78706. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
78707. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
78708. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
78709. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
78710. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
78711. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
78712. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
78713. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
78714. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
78715. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR_MASK
78716. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
78717. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR_MASK
78718. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
78719. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR_MASK
78720. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
78721. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR_MASK
78722. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
78723. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
78724. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
78725. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
78726. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
78727. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
78728. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
78729. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
78730. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
78731. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
78732. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
78733. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
78734. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
78735. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
78736. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
78737. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
78738. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
78739. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
78740. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
78741. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
78742. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
78743. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
78744. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
78745. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
78746. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
78747. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
78748. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
78749. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
78750. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
78751. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
78752. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
78753. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
78754. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
78755. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
78756. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
78757. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
78758. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
78759. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
78760. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
78761. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
78762. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
78763. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
78764. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
78765. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
78766. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
78767. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
78768. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
78769. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
78770. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
78771. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
78772. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
78773. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
78774. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
78775. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
78776. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
78777. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
78778. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
78779. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
78780. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
78781. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
78782. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
78783. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
78784. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
78785. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
78786. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
78787. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
78788. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
78789. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
78790. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
78791. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
78792. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
78793. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
78794. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
78795. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
78796. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
78797. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
78798. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
78799. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
78800. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
78801. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
78802. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
78803. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
78804. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
78805. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
78806. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
78807. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
78808. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
78809. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
78810. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
78811. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
78812. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
78813. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
78814. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
78815. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
78816. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
78817. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
78818. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
78819. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
78820. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
78821. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
78822. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
78823. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
78824. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
78825. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
78826. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
78827. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
78828. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
78829. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
78830. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
78831. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
78832. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
78833. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
78834. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
78835. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
78836. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
78837. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
78838. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
78839. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
78840. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
78841. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
78842. BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
78843. BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE_MASK
78844. BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
78845. BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID_MASK
78846. BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID__SHIFT
78847. BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID_MASK
78848. BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID__SHIFT
78849. BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR_MASK
78850. BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
78851. BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2__RESERVED_MASK
78852. BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2__RESERVED__SHIFT
78853. BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2__RESERVED_MASK
78854. BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2__RESERVED__SHIFT
78855. BIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2__RESERVED_MASK
78856. BIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2__RESERVED__SHIFT
78857. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST_MASK
78858. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST__SHIFT
78859. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING_MASK
78860. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING__SHIFT
78861. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE_MASK
78862. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE__SHIFT
78863. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__IMMEDIATE_READINESS_MASK
78864. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__IMMEDIATE_READINESS__SHIFT
78865. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS_MASK
78866. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS__SHIFT
78867. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
78868. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
78869. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED_MASK
78870. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
78871. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_CAP_MASK
78872. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_CAP__SHIFT
78873. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_EN_MASK
78874. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_EN__SHIFT
78875. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT_MASK
78876. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
78877. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT_MASK
78878. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
78879. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
78880. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
78881. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT_MASK
78882. BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
78883. BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS_MASK
78884. BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS__SHIFT
78885. BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID_MASK
78886. BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID__SHIFT
78887. BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
78888. BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
78889. BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
78890. BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
78891. BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR_MASK
78892. BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR__SHIFT
78893. BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR_MASK
78894. BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR__SHIFT
78895. BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR_MASK
78896. BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR__SHIFT
78897. BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR_MASK
78898. BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR__SHIFT
78899. BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR_MASK
78900. BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR__SHIFT
78901. BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR_MASK
78902. BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR__SHIFT
78903. BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS_MASK
78904. BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS__SHIFT
78905. BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP_MASK
78906. BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP__SHIFT
78907. BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP_MASK
78908. BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP__SHIFT
78909. BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT_MASK
78910. BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT__SHIFT
78911. BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
78912. BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
78913. BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR_MASK
78914. BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR__SHIFT
78915. BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
78916. BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
78917. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING_MASK
78918. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING__SHIFT
78919. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN_MASK
78920. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN__SHIFT
78921. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN_MASK
78922. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN__SHIFT
78923. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS_MASK
78924. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS__SHIFT
78925. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN_MASK
78926. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN__SHIFT
78927. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN_MASK
78928. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN__SHIFT
78929. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
78930. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
78931. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN_MASK
78932. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN__SHIFT
78933. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
78934. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
78935. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN_MASK
78936. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN__SHIFT
78937. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN_MASK
78938. BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
78939. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
78940. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
78941. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
78942. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
78943. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
78944. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
78945. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
78946. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
78947. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
78948. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
78949. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
78950. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
78951. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
78952. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
78953. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
78954. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
78955. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
78956. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
78957. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
78958. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
78959. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
78960. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
78961. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
78962. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
78963. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
78964. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
78965. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
78966. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
78967. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
78968. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
78969. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
78970. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
78971. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
78972. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
78973. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
78974. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
78975. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
78976. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
78977. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
78978. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
78979. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
78980. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
78981. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
78982. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
78983. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG_MASK
78984. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
78985. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE_MASK
78986. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
78987. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
78988. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
78989. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
78990. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
78991. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
78992. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
78993. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC_MASK
78994. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
78995. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
78996. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
78997. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
78998. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
78999. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
79000. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
79001. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
79002. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
79003. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
79004. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
79005. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
79006. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
79007. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
79008. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
79009. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
79010. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
79011. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
79012. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
79013. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
79014. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
79015. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN_MASK
79016. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN__SHIFT
79017. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN_MASK
79018. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN__SHIFT
79019. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
79020. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
79021. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
79022. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
79023. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN_MASK
79024. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
79025. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
79026. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
79027. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
79028. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
79029. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR_MASK
79030. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
79031. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
79032. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
79033. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
79034. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
79035. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
79036. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
79037. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
79038. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
79039. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
79040. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
79041. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
79042. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
79043. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN_MASK
79044. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
79045. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID_MASK
79046. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID__SHIFT
79047. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED_MASK
79048. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED__SHIFT
79049. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR_MASK
79050. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR__SHIFT
79051. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR_MASK
79052. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR__SHIFT
79053. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
79054. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
79055. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR_MASK
79056. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR__SHIFT
79057. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
79058. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
79059. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
79060. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
79061. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED_MASK
79062. BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED__SHIFT
79063. BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE_MASK
79064. BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE__SHIFT
79065. BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE_MASK
79066. BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE__SHIFT
79067. BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
79068. BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
79069. BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
79070. BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
79071. BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER_MASK
79072. BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER__SHIFT
79073. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
79074. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
79075. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
79076. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
79077. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
79078. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
79079. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
79080. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
79081. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RESERVED_MASK
79082. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RESERVED__SHIFT
79083. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
79084. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
79085. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
79086. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
79087. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
79088. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
79089. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
79090. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
79091. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
79092. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
79093. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
79094. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
79095. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
79096. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
79097. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY_MASK
79098. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
79099. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
79100. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
79101. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED_MASK
79102. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED__SHIFT
79103. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH_MASK
79104. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH__SHIFT
79105. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT_MASK
79106. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT__SHIFT
79107. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER_MASK
79108. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER__SHIFT
79109. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
79110. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
79111. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
79112. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
79113. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
79114. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
79115. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
79116. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
79117. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
79118. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
79119. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
79120. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
79121. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
79122. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
79123. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
79124. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
79125. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN_MASK
79126. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
79127. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
79128. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
79129. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
79130. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
79131. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
79132. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
79133. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC_MASK
79134. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
79135. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
79136. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
79137. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
79138. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
79139. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
79140. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
79141. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS_MASK
79142. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS__SHIFT
79143. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL_MASK
79144. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL__SHIFT
79145. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
79146. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
79147. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK_MASK
79148. BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK__SHIFT
79149. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
79150. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
79151. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
79152. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
79153. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
79154. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
79155. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
79156. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
79157. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
79158. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
79159. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
79160. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
79161. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
79162. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
79163. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
79164. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
79165. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
79166. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
79167. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
79168. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
79169. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
79170. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
79171. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
79172. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
79173. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
79174. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
79175. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
79176. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
79177. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
79178. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
79179. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
79180. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
79181. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
79182. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
79183. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE_MASK
79184. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE__SHIFT
79185. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
79186. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
79187. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
79188. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
79189. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING_MASK
79190. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING__SHIFT
79191. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
79192. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
79193. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
79194. BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
79195. BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY__MAX_LAT_MASK
79196. BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY__MAX_LAT__SHIFT
79197. BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT__MIN_GNT_MASK
79198. BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT__MIN_GNT__SHIFT
79199. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID_MASK
79200. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID__SHIFT
79201. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR_MASK
79202. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
79203. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN_MASK
79204. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
79205. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
79206. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
79207. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
79208. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
79209. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR_MASK
79210. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
79211. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
79212. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
79213. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
79214. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
79215. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
79216. BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
79217. BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID_MASK
79218. BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID__SHIFT
79219. BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR_MASK
79220. BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
79221. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64_MASK
79222. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64__SHIFT
79223. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK_MASK
79224. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK__SHIFT
79225. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
79226. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
79227. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
79228. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
79229. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT_MASK
79230. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
79231. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN_MASK
79232. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN__SHIFT
79233. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
79234. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
79235. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
79236. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
79237. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
79238. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
79239. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
79240. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
79241. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA_MASK
79242. BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA__SHIFT
79243. BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64_MASK
79244. BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
79245. BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING_MASK
79246. BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING__SHIFT
79247. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
79248. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
79249. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
79250. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
79251. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
79252. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
79253. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
79254. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
79255. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
79256. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
79257. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
79258. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
79259. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
79260. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
79261. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
79262. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
79263. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
79264. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
79265. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
79266. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
79267. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
79268. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
79269. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
79270. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
79271. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
79272. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
79273. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
79274. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
79275. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
79276. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
79277. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
79278. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
79279. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
79280. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
79281. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
79282. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
79283. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
79284. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
79285. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
79286. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
79287. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
79288. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
79289. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
79290. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
79291. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
79292. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
79293. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
79294. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
79295. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
79296. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
79297. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__STU_MASK
79298. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__STU__SHIFT
79299. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
79300. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
79301. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
79302. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
79303. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
79304. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
79305. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID_MASK
79306. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID__SHIFT
79307. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR_MASK
79308. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
79309. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE_MASK
79310. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE__SHIFT
79311. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
79312. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
79313. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
79314. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
79315. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION_MASK
79316. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION__SHIFT
79317. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
79318. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
79319. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
79320. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
79321. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
79322. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
79323. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
79324. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
79325. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
79326. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
79327. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
79328. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
79329. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
79330. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
79331. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
79332. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
79333. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
79334. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
79335. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
79336. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
79337. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
79338. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
79339. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
79340. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
79341. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
79342. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
79343. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
79344. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
79345. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
79346. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
79347. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
79348. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
79349. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR_MASK
79350. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
79351. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR_MASK
79352. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
79353. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR_MASK
79354. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
79355. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR_MASK
79356. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
79357. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
79358. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
79359. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
79360. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
79361. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
79362. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
79363. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
79364. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
79365. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
79366. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
79367. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
79368. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
79369. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
79370. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
79371. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
79372. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
79373. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
79374. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
79375. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
79376. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
79377. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
79378. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
79379. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
79380. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
79381. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
79382. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
79383. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
79384. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
79385. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
79386. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
79387. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
79388. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
79389. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
79390. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
79391. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
79392. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
79393. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
79394. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
79395. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
79396. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
79397. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
79398. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
79399. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
79400. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
79401. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
79402. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
79403. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
79404. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
79405. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
79406. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
79407. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
79408. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
79409. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
79410. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
79411. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
79412. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
79413. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
79414. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
79415. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
79416. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
79417. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
79418. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
79419. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
79420. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
79421. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
79422. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
79423. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
79424. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
79425. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
79426. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
79427. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
79428. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
79429. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
79430. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
79431. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
79432. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
79433. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
79434. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
79435. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
79436. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
79437. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
79438. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
79439. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
79440. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
79441. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
79442. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
79443. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
79444. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
79445. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
79446. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
79447. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
79448. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
79449. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
79450. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
79451. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
79452. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
79453. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
79454. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
79455. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
79456. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
79457. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
79458. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
79459. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
79460. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
79461. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
79462. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
79463. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
79464. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
79465. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
79466. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
79467. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
79468. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
79469. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
79470. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
79471. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
79472. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
79473. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
79474. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
79475. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
79476. BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
79477. BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE_MASK
79478. BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
79479. BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID_MASK
79480. BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID__SHIFT
79481. BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID_MASK
79482. BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID__SHIFT
79483. BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR_MASK
79484. BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
79485. BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CAP2__RESERVED_MASK
79486. BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CAP2__RESERVED__SHIFT
79487. BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CNTL2__RESERVED_MASK
79488. BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CNTL2__RESERVED__SHIFT
79489. BIF_CFG_DEV0_EPF0_VF10_1_SLOT_STATUS2__RESERVED_MASK
79490. BIF_CFG_DEV0_EPF0_VF10_1_SLOT_STATUS2__RESERVED__SHIFT
79491. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST_MASK
79492. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST__SHIFT
79493. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING_MASK
79494. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING__SHIFT
79495. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE_MASK
79496. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE__SHIFT
79497. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__IMMEDIATE_READINESS_MASK
79498. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__IMMEDIATE_READINESS__SHIFT
79499. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS_MASK
79500. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS__SHIFT
79501. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
79502. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
79503. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED_MASK
79504. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
79505. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_CAP_MASK
79506. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_CAP__SHIFT
79507. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_EN_MASK
79508. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_EN__SHIFT
79509. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT_MASK
79510. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
79511. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT_MASK
79512. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
79513. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
79514. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
79515. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT_MASK
79516. BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
79517. BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS_MASK
79518. BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS__SHIFT
79519. BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID_MASK
79520. BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID__SHIFT
79521. BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_ID_MASK
79522. BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
79523. BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
79524. BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
79525. BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1__BASE_ADDR_MASK
79526. BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1__BASE_ADDR__SHIFT
79527. BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2__BASE_ADDR_MASK
79528. BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2__BASE_ADDR__SHIFT
79529. BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3__BASE_ADDR_MASK
79530. BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3__BASE_ADDR__SHIFT
79531. BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4__BASE_ADDR_MASK
79532. BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4__BASE_ADDR__SHIFT
79533. BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5__BASE_ADDR_MASK
79534. BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5__BASE_ADDR__SHIFT
79535. BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6__BASE_ADDR_MASK
79536. BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6__BASE_ADDR__SHIFT
79537. BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS__BASE_CLASS_MASK
79538. BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS__BASE_CLASS__SHIFT
79539. BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_CAP_MASK
79540. BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_CAP__SHIFT
79541. BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_COMP_MASK
79542. BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_COMP__SHIFT
79543. BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_STRT_MASK
79544. BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_STRT__SHIFT
79545. BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE__CACHE_LINE_SIZE_MASK
79546. BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
79547. BIF_CFG_DEV0_EPF0_VF10_CAP_PTR__CAP_PTR_MASK
79548. BIF_CFG_DEV0_EPF0_VF10_CAP_PTR__CAP_PTR__SHIFT
79549. BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
79550. BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
79551. BIF_CFG_DEV0_EPF0_VF10_COMMAND__AD_STEPPING_MASK
79552. BIF_CFG_DEV0_EPF0_VF10_COMMAND__AD_STEPPING__SHIFT
79553. BIF_CFG_DEV0_EPF0_VF10_COMMAND__BUS_MASTER_EN_MASK
79554. BIF_CFG_DEV0_EPF0_VF10_COMMAND__BUS_MASTER_EN__SHIFT
79555. BIF_CFG_DEV0_EPF0_VF10_COMMAND__FAST_B2B_EN_MASK
79556. BIF_CFG_DEV0_EPF0_VF10_COMMAND__FAST_B2B_EN__SHIFT
79557. BIF_CFG_DEV0_EPF0_VF10_COMMAND__INT_DIS_MASK
79558. BIF_CFG_DEV0_EPF0_VF10_COMMAND__INT_DIS__SHIFT
79559. BIF_CFG_DEV0_EPF0_VF10_COMMAND__IO_ACCESS_EN_MASK
79560. BIF_CFG_DEV0_EPF0_VF10_COMMAND__IO_ACCESS_EN__SHIFT
79561. BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_ACCESS_EN_MASK
79562. BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_ACCESS_EN__SHIFT
79563. BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
79564. BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
79565. BIF_CFG_DEV0_EPF0_VF10_COMMAND__PAL_SNOOP_EN_MASK
79566. BIF_CFG_DEV0_EPF0_VF10_COMMAND__PAL_SNOOP_EN__SHIFT
79567. BIF_CFG_DEV0_EPF0_VF10_COMMAND__PARITY_ERROR_RESPONSE_MASK
79568. BIF_CFG_DEV0_EPF0_VF10_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
79569. BIF_CFG_DEV0_EPF0_VF10_COMMAND__SERR_EN_MASK
79570. BIF_CFG_DEV0_EPF0_VF10_COMMAND__SERR_EN__SHIFT
79571. BIF_CFG_DEV0_EPF0_VF10_COMMAND__SPECIAL_CYCLE_EN_MASK
79572. BIF_CFG_DEV0_EPF0_VF10_COMMAND__SPECIAL_CYCLE_EN__SHIFT
79573. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
79574. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
79575. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
79576. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
79577. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
79578. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
79579. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
79580. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
79581. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
79582. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
79583. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
79584. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
79585. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
79586. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
79587. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
79588. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
79589. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
79590. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
79591. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
79592. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
79593. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
79594. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
79595. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__FRS_SUPPORTED_MASK
79596. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
79597. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
79598. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
79599. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LTR_SUPPORTED_MASK
79600. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
79601. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
79602. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
79603. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
79604. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
79605. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__OBFF_SUPPORTED_MASK
79606. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
79607. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
79608. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
79609. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
79610. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
79611. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
79612. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
79613. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
79614. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
79615. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
79616. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
79617. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__EXTENDED_TAG_MASK
79618. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__EXTENDED_TAG__SHIFT
79619. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__FLR_CAPABLE_MASK
79620. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__FLR_CAPABLE__SHIFT
79621. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
79622. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
79623. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
79624. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
79625. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
79626. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
79627. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__PHANTOM_FUNC_MASK
79628. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__PHANTOM_FUNC__SHIFT
79629. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
79630. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
79631. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
79632. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
79633. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
79634. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
79635. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
79636. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
79637. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
79638. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
79639. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
79640. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
79641. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
79642. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
79643. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
79644. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
79645. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
79646. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
79647. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
79648. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
79649. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__LTR_EN_MASK
79650. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__LTR_EN__SHIFT
79651. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__OBFF_EN_MASK
79652. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__OBFF_EN__SHIFT
79653. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
79654. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
79655. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
79656. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
79657. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__CORR_ERR_EN_MASK
79658. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__CORR_ERR_EN__SHIFT
79659. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
79660. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
79661. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__FATAL_ERR_EN_MASK
79662. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
79663. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__INITIATE_FLR_MASK
79664. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__INITIATE_FLR__SHIFT
79665. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
79666. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
79667. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
79668. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
79669. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
79670. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
79671. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NO_SNOOP_EN_MASK
79672. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
79673. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
79674. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
79675. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__RELAXED_ORD_EN_MASK
79676. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
79677. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__USR_REPORT_EN_MASK
79678. BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__USR_REPORT_EN__SHIFT
79679. BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID__DEVICE_ID_MASK
79680. BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID__DEVICE_ID__SHIFT
79681. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2__RESERVED_MASK
79682. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2__RESERVED__SHIFT
79683. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__AUX_PWR_MASK
79684. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__AUX_PWR__SHIFT
79685. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__CORR_ERR_MASK
79686. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__CORR_ERR__SHIFT
79687. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
79688. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
79689. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__FATAL_ERR_MASK
79690. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__FATAL_ERR__SHIFT
79691. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__NON_FATAL_ERR_MASK
79692. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
79693. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
79694. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
79695. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__USR_DETECTED_MASK
79696. BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__USR_DETECTED__SHIFT
79697. BIF_CFG_DEV0_EPF0_VF10_HEADER__DEVICE_TYPE_MASK
79698. BIF_CFG_DEV0_EPF0_VF10_HEADER__DEVICE_TYPE__SHIFT
79699. BIF_CFG_DEV0_EPF0_VF10_HEADER__HEADER_TYPE_MASK
79700. BIF_CFG_DEV0_EPF0_VF10_HEADER__HEADER_TYPE__SHIFT
79701. BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE__INTERRUPT_LINE_MASK
79702. BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
79703. BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN__INTERRUPT_PIN_MASK
79704. BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
79705. BIF_CFG_DEV0_EPF0_VF10_LATENCY__LATENCY_TIMER_MASK
79706. BIF_CFG_DEV0_EPF0_VF10_LATENCY__LATENCY_TIMER__SHIFT
79707. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
79708. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
79709. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
79710. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
79711. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
79712. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
79713. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
79714. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
79715. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
79716. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
79717. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
79718. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
79719. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
79720. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
79721. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
79722. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
79723. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
79724. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
79725. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
79726. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
79727. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L0S_EXIT_LATENCY_MASK
79728. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
79729. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L1_EXIT_LATENCY_MASK
79730. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L1_EXIT_LATENCY__SHIFT
79731. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
79732. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
79733. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_SPEED_MASK
79734. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_SPEED__SHIFT
79735. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_WIDTH_MASK
79736. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_WIDTH__SHIFT
79737. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PM_SUPPORT_MASK
79738. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PM_SUPPORT__SHIFT
79739. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PORT_NUMBER_MASK
79740. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PORT_NUMBER__SHIFT
79741. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
79742. BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
79743. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
79744. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
79745. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_SOS_MASK
79746. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
79747. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_COMPLIANCE_MASK
79748. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
79749. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
79750. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
79751. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
79752. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
79753. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
79754. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
79755. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__TARGET_LINK_SPEED_MASK
79756. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
79757. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__XMIT_MARGIN_MASK
79758. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__XMIT_MARGIN__SHIFT
79759. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
79760. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
79761. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__COMMON_CLOCK_CFG_MASK
79762. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
79763. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
79764. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
79765. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__EXTENDED_SYNC_MASK
79766. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__EXTENDED_SYNC__SHIFT
79767. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
79768. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
79769. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
79770. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
79771. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
79772. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
79773. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_DIS_MASK
79774. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_DIS__SHIFT
79775. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PM_CONTROL_MASK
79776. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PM_CONTROL__SHIFT
79777. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__READ_CPL_BOUNDARY_MASK
79778. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
79779. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__RETRAIN_LINK_MASK
79780. BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__RETRAIN_LINK__SHIFT
79781. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
79782. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
79783. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
79784. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
79785. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
79786. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
79787. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
79788. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
79789. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
79790. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
79791. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
79792. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
79793. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
79794. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
79795. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
79796. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
79797. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
79798. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
79799. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
79800. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
79801. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
79802. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
79803. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__CURRENT_LINK_SPEED_MASK
79804. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
79805. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__DL_ACTIVE_MASK
79806. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__DL_ACTIVE__SHIFT
79807. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
79808. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
79809. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
79810. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
79811. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_TRAINING_MASK
79812. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_TRAINING__SHIFT
79813. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
79814. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
79815. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__SLOT_CLOCK_CFG_MASK
79816. BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
79817. BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY__MAX_LAT_MASK
79818. BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY__MAX_LAT__SHIFT
79819. BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT__MIN_GNT_MASK
79820. BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT__MIN_GNT__SHIFT
79821. BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__CAP_ID_MASK
79822. BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__CAP_ID__SHIFT
79823. BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__NEXT_PTR_MASK
79824. BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__NEXT_PTR__SHIFT
79825. BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_EN_MASK
79826. BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_EN__SHIFT
79827. BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
79828. BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
79829. BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
79830. BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
79831. BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_BIR_MASK
79832. BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_BIR__SHIFT
79833. BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_OFFSET_MASK
79834. BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
79835. BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_BIR_MASK
79836. BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
79837. BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
79838. BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
79839. BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__CAP_ID_MASK
79840. BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__CAP_ID__SHIFT
79841. BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__NEXT_PTR_MASK
79842. BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__NEXT_PTR__SHIFT
79843. BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64__MSI_MASK_64_MASK
79844. BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64__MSI_MASK_64__SHIFT
79845. BIF_CFG_DEV0_EPF0_VF10_MSI_MASK__MSI_MASK_MASK
79846. BIF_CFG_DEV0_EPF0_VF10_MSI_MASK__MSI_MASK__SHIFT
79847. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
79848. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
79849. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
79850. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
79851. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_64BIT_MASK
79852. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_64BIT__SHIFT
79853. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EN_MASK
79854. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EN__SHIFT
79855. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
79856. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
79857. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
79858. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
79859. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
79860. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
79861. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64__MSI_DATA_64_MASK
79862. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
79863. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA__MSI_DATA_MASK
79864. BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA__MSI_DATA__SHIFT
79865. BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64__MSI_PENDING_64_MASK
79866. BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64__MSI_PENDING_64__SHIFT
79867. BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING__MSI_PENDING_MASK
79868. BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING__MSI_PENDING__SHIFT
79869. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
79870. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
79871. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
79872. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
79873. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
79874. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
79875. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
79876. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
79877. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
79878. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
79879. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
79880. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
79881. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
79882. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
79883. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
79884. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
79885. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
79886. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
79887. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
79888. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
79889. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
79890. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
79891. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
79892. BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
79893. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
79894. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
79895. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
79896. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
79897. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
79898. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
79899. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
79900. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
79901. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
79902. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
79903. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
79904. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
79905. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
79906. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
79907. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
79908. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
79909. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
79910. BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
79911. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
79912. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
79913. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
79914. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
79915. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
79916. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
79917. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL__ATC_ENABLE_MASK
79918. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
79919. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL__STU_MASK
79920. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL__STU__SHIFT
79921. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
79922. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
79923. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
79924. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
79925. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
79926. BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
79927. BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__CAP_ID_MASK
79928. BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__CAP_ID__SHIFT
79929. BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__NEXT_PTR_MASK
79930. BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__NEXT_PTR__SHIFT
79931. BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__DEVICE_TYPE_MASK
79932. BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__DEVICE_TYPE__SHIFT
79933. BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__INT_MESSAGE_NUM_MASK
79934. BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
79935. BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__SLOT_IMPLEMENTED_MASK
79936. BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
79937. BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__VERSION_MASK
79938. BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__VERSION__SHIFT
79939. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
79940. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
79941. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
79942. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
79943. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
79944. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
79945. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
79946. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
79947. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
79948. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
79949. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
79950. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
79951. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
79952. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
79953. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
79954. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
79955. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
79956. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
79957. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
79958. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
79959. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
79960. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
79961. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
79962. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
79963. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
79964. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
79965. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
79966. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
79967. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
79968. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
79969. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
79970. BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
79971. BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0__TLP_HDR_MASK
79972. BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0__TLP_HDR__SHIFT
79973. BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1__TLP_HDR_MASK
79974. BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1__TLP_HDR__SHIFT
79975. BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2__TLP_HDR_MASK
79976. BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2__TLP_HDR__SHIFT
79977. BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3__TLP_HDR_MASK
79978. BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3__TLP_HDR__SHIFT
79979. BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
79980. BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
79981. BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
79982. BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
79983. BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
79984. BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
79985. BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
79986. BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
79987. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
79988. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
79989. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
79990. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
79991. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
79992. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
79993. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
79994. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
79995. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
79996. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
79997. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
79998. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
79999. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
80000. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
80001. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
80002. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
80003. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
80004. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
80005. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
80006. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
80007. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
80008. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
80009. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
80010. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
80011. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
80012. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
80013. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
80014. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
80015. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
80016. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
80017. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
80018. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
80019. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
80020. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
80021. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
80022. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
80023. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
80024. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
80025. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
80026. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
80027. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
80028. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
80029. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
80030. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
80031. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
80032. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
80033. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
80034. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
80035. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
80036. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
80037. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
80038. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
80039. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
80040. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
80041. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
80042. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
80043. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
80044. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
80045. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
80046. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
80047. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
80048. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
80049. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
80050. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
80051. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
80052. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
80053. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
80054. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
80055. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
80056. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
80057. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
80058. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
80059. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
80060. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
80061. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
80062. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
80063. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
80064. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
80065. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
80066. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
80067. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
80068. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
80069. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
80070. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
80071. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
80072. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
80073. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
80074. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
80075. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
80076. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
80077. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
80078. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
80079. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
80080. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
80081. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
80082. BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
80083. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
80084. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
80085. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
80086. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
80087. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
80088. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
80089. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
80090. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
80091. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
80092. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
80093. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
80094. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
80095. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
80096. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
80097. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
80098. BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
80099. BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE__PROG_INTERFACE_MASK
80100. BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE__PROG_INTERFACE__SHIFT
80101. BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MAJOR_REV_ID_MASK
80102. BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MAJOR_REV_ID__SHIFT
80103. BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MINOR_REV_ID_MASK
80104. BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MINOR_REV_ID__SHIFT
80105. BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__BASE_ADDR_MASK
80106. BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__BASE_ADDR__SHIFT
80107. BIF_CFG_DEV0_EPF0_VF10_STATUS__CAP_LIST_MASK
80108. BIF_CFG_DEV0_EPF0_VF10_STATUS__CAP_LIST__SHIFT
80109. BIF_CFG_DEV0_EPF0_VF10_STATUS__DEVSEL_TIMING_MASK
80110. BIF_CFG_DEV0_EPF0_VF10_STATUS__DEVSEL_TIMING__SHIFT
80111. BIF_CFG_DEV0_EPF0_VF10_STATUS__FAST_BACK_CAPABLE_MASK
80112. BIF_CFG_DEV0_EPF0_VF10_STATUS__FAST_BACK_CAPABLE__SHIFT
80113. BIF_CFG_DEV0_EPF0_VF10_STATUS__IMMEDIATE_READINESS_MASK
80114. BIF_CFG_DEV0_EPF0_VF10_STATUS__IMMEDIATE_READINESS__SHIFT
80115. BIF_CFG_DEV0_EPF0_VF10_STATUS__INT_STATUS_MASK
80116. BIF_CFG_DEV0_EPF0_VF10_STATUS__INT_STATUS__SHIFT
80117. BIF_CFG_DEV0_EPF0_VF10_STATUS__MASTER_DATA_PARITY_ERROR_MASK
80118. BIF_CFG_DEV0_EPF0_VF10_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
80119. BIF_CFG_DEV0_EPF0_VF10_STATUS__PARITY_ERROR_DETECTED_MASK
80120. BIF_CFG_DEV0_EPF0_VF10_STATUS__PARITY_ERROR_DETECTED__SHIFT
80121. BIF_CFG_DEV0_EPF0_VF10_STATUS__PCI_66_CAP_MASK
80122. BIF_CFG_DEV0_EPF0_VF10_STATUS__PCI_66_CAP__SHIFT
80123. BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_MASTER_ABORT_MASK
80124. BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_MASTER_ABORT__SHIFT
80125. BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_TARGET_ABORT_MASK
80126. BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_TARGET_ABORT__SHIFT
80127. BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNALED_SYSTEM_ERROR_MASK
80128. BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
80129. BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNAL_TARGET_ABORT_MASK
80130. BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNAL_TARGET_ABORT__SHIFT
80131. BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS__SUB_CLASS_MASK
80132. BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS__SUB_CLASS__SHIFT
80133. BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID__VENDOR_ID_MASK
80134. BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID__VENDOR_ID__SHIFT
80135. BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
80136. BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
80137. BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
80138. BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
80139. BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR_MASK
80140. BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR__SHIFT
80141. BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR_MASK
80142. BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR__SHIFT
80143. BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR_MASK
80144. BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR__SHIFT
80145. BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR_MASK
80146. BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR__SHIFT
80147. BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR_MASK
80148. BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR__SHIFT
80149. BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR_MASK
80150. BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR__SHIFT
80151. BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS_MASK
80152. BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS__SHIFT
80153. BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP_MASK
80154. BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP__SHIFT
80155. BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP_MASK
80156. BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP__SHIFT
80157. BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT_MASK
80158. BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT__SHIFT
80159. BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
80160. BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
80161. BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR_MASK
80162. BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR__SHIFT
80163. BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
80164. BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
80165. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING_MASK
80166. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING__SHIFT
80167. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN_MASK
80168. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN__SHIFT
80169. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN_MASK
80170. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN__SHIFT
80171. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS_MASK
80172. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS__SHIFT
80173. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN_MASK
80174. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN__SHIFT
80175. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN_MASK
80176. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN__SHIFT
80177. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
80178. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
80179. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN_MASK
80180. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN__SHIFT
80181. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
80182. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
80183. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN_MASK
80184. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN__SHIFT
80185. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN_MASK
80186. BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
80187. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
80188. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
80189. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
80190. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
80191. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
80192. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
80193. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
80194. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
80195. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
80196. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
80197. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
80198. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
80199. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
80200. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
80201. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
80202. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
80203. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
80204. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
80205. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
80206. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
80207. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
80208. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
80209. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
80210. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
80211. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
80212. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
80213. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
80214. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
80215. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
80216. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
80217. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
80218. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
80219. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
80220. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
80221. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
80222. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
80223. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
80224. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
80225. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
80226. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
80227. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
80228. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
80229. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
80230. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
80231. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG_MASK
80232. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
80233. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE_MASK
80234. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
80235. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
80236. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
80237. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
80238. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
80239. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
80240. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
80241. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC_MASK
80242. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
80243. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
80244. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
80245. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
80246. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
80247. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
80248. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
80249. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
80250. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
80251. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
80252. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
80253. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
80254. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
80255. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
80256. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
80257. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
80258. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
80259. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
80260. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
80261. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
80262. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
80263. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN_MASK
80264. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN__SHIFT
80265. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN_MASK
80266. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN__SHIFT
80267. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
80268. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
80269. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
80270. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
80271. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN_MASK
80272. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
80273. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
80274. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
80275. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
80276. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
80277. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR_MASK
80278. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
80279. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
80280. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
80281. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
80282. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
80283. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
80284. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
80285. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
80286. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
80287. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
80288. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
80289. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
80290. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
80291. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN_MASK
80292. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
80293. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID_MASK
80294. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID__SHIFT
80295. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED_MASK
80296. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED__SHIFT
80297. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR_MASK
80298. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR__SHIFT
80299. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR_MASK
80300. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR__SHIFT
80301. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
80302. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
80303. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR_MASK
80304. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR__SHIFT
80305. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
80306. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
80307. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
80308. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
80309. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED_MASK
80310. BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED__SHIFT
80311. BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE_MASK
80312. BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE__SHIFT
80313. BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE_MASK
80314. BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE__SHIFT
80315. BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
80316. BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
80317. BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
80318. BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
80319. BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER_MASK
80320. BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER__SHIFT
80321. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
80322. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
80323. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
80324. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
80325. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
80326. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
80327. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
80328. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
80329. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RESERVED_MASK
80330. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RESERVED__SHIFT
80331. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
80332. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
80333. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
80334. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
80335. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
80336. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
80337. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
80338. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
80339. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
80340. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
80341. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
80342. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
80343. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
80344. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
80345. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY_MASK
80346. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
80347. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
80348. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
80349. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED_MASK
80350. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED__SHIFT
80351. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH_MASK
80352. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH__SHIFT
80353. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT_MASK
80354. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT__SHIFT
80355. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER_MASK
80356. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER__SHIFT
80357. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
80358. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
80359. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
80360. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
80361. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
80362. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
80363. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
80364. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
80365. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
80366. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
80367. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
80368. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
80369. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
80370. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
80371. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
80372. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
80373. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN_MASK
80374. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
80375. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
80376. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
80377. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
80378. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
80379. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
80380. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
80381. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC_MASK
80382. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
80383. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
80384. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
80385. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
80386. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
80387. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
80388. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
80389. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS_MASK
80390. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS__SHIFT
80391. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL_MASK
80392. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL__SHIFT
80393. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
80394. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
80395. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK_MASK
80396. BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK__SHIFT
80397. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
80398. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
80399. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
80400. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
80401. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
80402. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
80403. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
80404. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
80405. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
80406. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
80407. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
80408. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
80409. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
80410. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
80411. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
80412. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
80413. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
80414. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
80415. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
80416. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
80417. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
80418. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
80419. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
80420. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
80421. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
80422. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
80423. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
80424. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
80425. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
80426. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
80427. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
80428. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
80429. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
80430. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
80431. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE_MASK
80432. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE__SHIFT
80433. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
80434. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
80435. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
80436. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
80437. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING_MASK
80438. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING__SHIFT
80439. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
80440. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
80441. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
80442. BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
80443. BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY__MAX_LAT_MASK
80444. BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY__MAX_LAT__SHIFT
80445. BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT__MIN_GNT_MASK
80446. BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT__MIN_GNT__SHIFT
80447. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID_MASK
80448. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID__SHIFT
80449. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR_MASK
80450. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
80451. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN_MASK
80452. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
80453. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
80454. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
80455. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
80456. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
80457. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR_MASK
80458. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
80459. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
80460. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
80461. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
80462. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
80463. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
80464. BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
80465. BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID_MASK
80466. BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID__SHIFT
80467. BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR_MASK
80468. BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
80469. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64_MASK
80470. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64__SHIFT
80471. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK_MASK
80472. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK__SHIFT
80473. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
80474. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
80475. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
80476. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
80477. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT_MASK
80478. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
80479. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN_MASK
80480. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN__SHIFT
80481. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
80482. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
80483. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
80484. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
80485. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
80486. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
80487. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
80488. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
80489. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA_MASK
80490. BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA__SHIFT
80491. BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64_MASK
80492. BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
80493. BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING_MASK
80494. BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING__SHIFT
80495. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
80496. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
80497. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
80498. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
80499. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
80500. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
80501. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
80502. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
80503. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
80504. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
80505. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
80506. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
80507. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
80508. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
80509. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
80510. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
80511. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
80512. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
80513. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
80514. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
80515. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
80516. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
80517. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
80518. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
80519. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
80520. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
80521. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
80522. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
80523. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
80524. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
80525. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
80526. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
80527. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
80528. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
80529. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
80530. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
80531. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
80532. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
80533. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
80534. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
80535. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
80536. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
80537. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
80538. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
80539. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
80540. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
80541. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
80542. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
80543. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
80544. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
80545. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__STU_MASK
80546. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__STU__SHIFT
80547. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
80548. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
80549. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
80550. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
80551. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
80552. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
80553. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID_MASK
80554. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID__SHIFT
80555. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR_MASK
80556. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
80557. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE_MASK
80558. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE__SHIFT
80559. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
80560. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
80561. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
80562. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
80563. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION_MASK
80564. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION__SHIFT
80565. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
80566. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
80567. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
80568. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
80569. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
80570. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
80571. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
80572. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
80573. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
80574. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
80575. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
80576. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
80577. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
80578. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
80579. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
80580. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
80581. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
80582. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
80583. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
80584. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
80585. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
80586. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
80587. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
80588. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
80589. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
80590. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
80591. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
80592. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
80593. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
80594. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
80595. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
80596. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
80597. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR_MASK
80598. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
80599. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR_MASK
80600. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
80601. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR_MASK
80602. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
80603. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR_MASK
80604. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
80605. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
80606. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
80607. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
80608. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
80609. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
80610. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
80611. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
80612. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
80613. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
80614. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
80615. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
80616. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
80617. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
80618. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
80619. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
80620. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
80621. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
80622. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
80623. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
80624. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
80625. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
80626. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
80627. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
80628. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
80629. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
80630. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
80631. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
80632. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
80633. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
80634. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
80635. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
80636. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
80637. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
80638. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
80639. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
80640. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
80641. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
80642. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
80643. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
80644. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
80645. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
80646. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
80647. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
80648. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
80649. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
80650. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
80651. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
80652. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
80653. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
80654. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
80655. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
80656. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
80657. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
80658. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
80659. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
80660. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
80661. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
80662. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
80663. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
80664. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
80665. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
80666. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
80667. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
80668. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
80669. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
80670. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
80671. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
80672. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
80673. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
80674. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
80675. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
80676. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
80677. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
80678. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
80679. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
80680. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
80681. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
80682. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
80683. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
80684. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
80685. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
80686. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
80687. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
80688. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
80689. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
80690. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
80691. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
80692. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
80693. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
80694. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
80695. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
80696. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
80697. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
80698. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
80699. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
80700. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
80701. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
80702. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
80703. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
80704. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
80705. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
80706. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
80707. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
80708. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
80709. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
80710. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
80711. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
80712. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
80713. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
80714. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
80715. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
80716. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
80717. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
80718. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
80719. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
80720. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
80721. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
80722. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
80723. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
80724. BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
80725. BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE_MASK
80726. BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
80727. BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID_MASK
80728. BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID__SHIFT
80729. BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID_MASK
80730. BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID__SHIFT
80731. BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR_MASK
80732. BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
80733. BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2__RESERVED_MASK
80734. BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2__RESERVED__SHIFT
80735. BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2__RESERVED_MASK
80736. BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2__RESERVED__SHIFT
80737. BIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2__RESERVED_MASK
80738. BIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2__RESERVED__SHIFT
80739. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST_MASK
80740. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST__SHIFT
80741. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING_MASK
80742. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING__SHIFT
80743. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE_MASK
80744. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE__SHIFT
80745. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__IMMEDIATE_READINESS_MASK
80746. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__IMMEDIATE_READINESS__SHIFT
80747. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS_MASK
80748. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS__SHIFT
80749. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
80750. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
80751. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED_MASK
80752. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
80753. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_CAP_MASK
80754. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_CAP__SHIFT
80755. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_EN_MASK
80756. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_EN__SHIFT
80757. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT_MASK
80758. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
80759. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT_MASK
80760. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
80761. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
80762. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
80763. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT_MASK
80764. BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
80765. BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS_MASK
80766. BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS__SHIFT
80767. BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID_MASK
80768. BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID__SHIFT
80769. BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
80770. BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
80771. BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
80772. BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
80773. BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR_MASK
80774. BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR__SHIFT
80775. BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR_MASK
80776. BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR__SHIFT
80777. BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR_MASK
80778. BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR__SHIFT
80779. BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR_MASK
80780. BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR__SHIFT
80781. BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR_MASK
80782. BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR__SHIFT
80783. BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR_MASK
80784. BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR__SHIFT
80785. BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS_MASK
80786. BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS__SHIFT
80787. BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP_MASK
80788. BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP__SHIFT
80789. BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP_MASK
80790. BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP__SHIFT
80791. BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT_MASK
80792. BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT__SHIFT
80793. BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
80794. BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
80795. BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR_MASK
80796. BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR__SHIFT
80797. BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
80798. BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
80799. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING_MASK
80800. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING__SHIFT
80801. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN_MASK
80802. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN__SHIFT
80803. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN_MASK
80804. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN__SHIFT
80805. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS_MASK
80806. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS__SHIFT
80807. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN_MASK
80808. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN__SHIFT
80809. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN_MASK
80810. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN__SHIFT
80811. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
80812. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
80813. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN_MASK
80814. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN__SHIFT
80815. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
80816. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
80817. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN_MASK
80818. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN__SHIFT
80819. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN_MASK
80820. BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
80821. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
80822. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
80823. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
80824. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
80825. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
80826. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
80827. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
80828. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
80829. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
80830. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
80831. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
80832. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
80833. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
80834. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
80835. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
80836. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
80837. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
80838. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
80839. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
80840. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
80841. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
80842. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
80843. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
80844. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
80845. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
80846. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
80847. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
80848. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
80849. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
80850. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
80851. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
80852. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
80853. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
80854. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
80855. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
80856. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
80857. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
80858. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
80859. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
80860. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
80861. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
80862. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
80863. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
80864. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
80865. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG_MASK
80866. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
80867. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE_MASK
80868. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
80869. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
80870. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
80871. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
80872. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
80873. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
80874. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
80875. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC_MASK
80876. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
80877. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
80878. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
80879. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
80880. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
80881. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
80882. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
80883. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
80884. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
80885. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
80886. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
80887. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
80888. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
80889. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
80890. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
80891. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
80892. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
80893. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
80894. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
80895. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
80896. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
80897. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN_MASK
80898. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN__SHIFT
80899. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN_MASK
80900. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN__SHIFT
80901. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
80902. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
80903. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
80904. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
80905. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN_MASK
80906. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
80907. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
80908. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
80909. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
80910. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
80911. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR_MASK
80912. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
80913. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
80914. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
80915. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
80916. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
80917. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
80918. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
80919. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
80920. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
80921. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
80922. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
80923. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
80924. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
80925. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN_MASK
80926. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
80927. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID_MASK
80928. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID__SHIFT
80929. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED_MASK
80930. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED__SHIFT
80931. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR_MASK
80932. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR__SHIFT
80933. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR_MASK
80934. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR__SHIFT
80935. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
80936. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
80937. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR_MASK
80938. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR__SHIFT
80939. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
80940. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
80941. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
80942. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
80943. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED_MASK
80944. BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED__SHIFT
80945. BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE_MASK
80946. BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE__SHIFT
80947. BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE_MASK
80948. BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE__SHIFT
80949. BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
80950. BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
80951. BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
80952. BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
80953. BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER_MASK
80954. BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER__SHIFT
80955. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
80956. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
80957. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
80958. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
80959. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
80960. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
80961. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
80962. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
80963. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RESERVED_MASK
80964. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RESERVED__SHIFT
80965. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
80966. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
80967. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
80968. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
80969. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
80970. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
80971. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
80972. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
80973. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
80974. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
80975. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
80976. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
80977. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
80978. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
80979. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY_MASK
80980. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
80981. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
80982. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
80983. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED_MASK
80984. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED__SHIFT
80985. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH_MASK
80986. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH__SHIFT
80987. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT_MASK
80988. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT__SHIFT
80989. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER_MASK
80990. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER__SHIFT
80991. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
80992. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
80993. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
80994. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
80995. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
80996. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
80997. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
80998. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
80999. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
81000. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
81001. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
81002. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
81003. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
81004. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
81005. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
81006. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
81007. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN_MASK
81008. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
81009. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
81010. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
81011. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
81012. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
81013. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
81014. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
81015. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC_MASK
81016. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
81017. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
81018. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
81019. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
81020. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
81021. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
81022. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
81023. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS_MASK
81024. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS__SHIFT
81025. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL_MASK
81026. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL__SHIFT
81027. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
81028. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
81029. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK_MASK
81030. BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK__SHIFT
81031. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
81032. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
81033. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
81034. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
81035. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
81036. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
81037. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
81038. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
81039. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
81040. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
81041. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
81042. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
81043. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
81044. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
81045. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
81046. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
81047. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
81048. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
81049. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
81050. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
81051. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
81052. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
81053. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
81054. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
81055. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
81056. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
81057. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
81058. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
81059. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
81060. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
81061. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
81062. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
81063. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
81064. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
81065. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE_MASK
81066. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE__SHIFT
81067. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
81068. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
81069. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
81070. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
81071. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING_MASK
81072. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING__SHIFT
81073. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
81074. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
81075. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
81076. BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
81077. BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY__MAX_LAT_MASK
81078. BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY__MAX_LAT__SHIFT
81079. BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT__MIN_GNT_MASK
81080. BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT__MIN_GNT__SHIFT
81081. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID_MASK
81082. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID__SHIFT
81083. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR_MASK
81084. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
81085. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN_MASK
81086. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
81087. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
81088. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
81089. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
81090. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
81091. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR_MASK
81092. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
81093. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
81094. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
81095. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
81096. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
81097. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
81098. BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
81099. BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID_MASK
81100. BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID__SHIFT
81101. BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR_MASK
81102. BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
81103. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64_MASK
81104. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64__SHIFT
81105. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK_MASK
81106. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK__SHIFT
81107. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
81108. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
81109. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
81110. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
81111. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT_MASK
81112. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
81113. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN_MASK
81114. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN__SHIFT
81115. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
81116. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
81117. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
81118. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
81119. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
81120. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
81121. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
81122. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
81123. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA_MASK
81124. BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA__SHIFT
81125. BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64_MASK
81126. BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
81127. BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING_MASK
81128. BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING__SHIFT
81129. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
81130. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
81131. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
81132. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
81133. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
81134. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
81135. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
81136. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
81137. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
81138. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
81139. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
81140. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
81141. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
81142. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
81143. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
81144. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
81145. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
81146. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
81147. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
81148. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
81149. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
81150. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
81151. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
81152. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
81153. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
81154. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
81155. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
81156. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
81157. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
81158. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
81159. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
81160. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
81161. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
81162. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
81163. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
81164. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
81165. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
81166. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
81167. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
81168. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
81169. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
81170. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
81171. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
81172. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
81173. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
81174. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
81175. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
81176. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
81177. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
81178. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
81179. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__STU_MASK
81180. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__STU__SHIFT
81181. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
81182. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
81183. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
81184. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
81185. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
81186. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
81187. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID_MASK
81188. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID__SHIFT
81189. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR_MASK
81190. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
81191. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE_MASK
81192. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE__SHIFT
81193. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
81194. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
81195. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
81196. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
81197. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION_MASK
81198. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION__SHIFT
81199. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
81200. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
81201. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
81202. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
81203. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
81204. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
81205. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
81206. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
81207. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
81208. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
81209. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
81210. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
81211. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
81212. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
81213. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
81214. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
81215. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
81216. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
81217. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
81218. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
81219. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
81220. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
81221. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
81222. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
81223. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
81224. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
81225. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
81226. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
81227. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
81228. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
81229. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
81230. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
81231. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR_MASK
81232. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
81233. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR_MASK
81234. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
81235. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR_MASK
81236. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
81237. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR_MASK
81238. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
81239. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
81240. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
81241. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
81242. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
81243. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
81244. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
81245. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
81246. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
81247. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
81248. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
81249. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
81250. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
81251. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
81252. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
81253. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
81254. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
81255. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
81256. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
81257. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
81258. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
81259. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
81260. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
81261. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
81262. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
81263. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
81264. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
81265. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
81266. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
81267. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
81268. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
81269. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
81270. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
81271. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
81272. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
81273. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
81274. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
81275. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
81276. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
81277. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
81278. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
81279. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
81280. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
81281. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
81282. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
81283. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
81284. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
81285. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
81286. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
81287. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
81288. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
81289. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
81290. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
81291. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
81292. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
81293. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
81294. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
81295. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
81296. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
81297. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
81298. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
81299. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
81300. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
81301. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
81302. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
81303. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
81304. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
81305. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
81306. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
81307. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
81308. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
81309. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
81310. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
81311. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
81312. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
81313. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
81314. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
81315. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
81316. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
81317. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
81318. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
81319. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
81320. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
81321. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
81322. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
81323. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
81324. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
81325. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
81326. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
81327. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
81328. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
81329. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
81330. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
81331. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
81332. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
81333. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
81334. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
81335. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
81336. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
81337. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
81338. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
81339. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
81340. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
81341. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
81342. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
81343. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
81344. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
81345. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
81346. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
81347. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
81348. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
81349. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
81350. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
81351. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
81352. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
81353. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
81354. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
81355. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
81356. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
81357. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
81358. BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
81359. BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE_MASK
81360. BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
81361. BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID_MASK
81362. BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID__SHIFT
81363. BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID_MASK
81364. BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID__SHIFT
81365. BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR_MASK
81366. BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
81367. BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CAP2__RESERVED_MASK
81368. BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CAP2__RESERVED__SHIFT
81369. BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CNTL2__RESERVED_MASK
81370. BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CNTL2__RESERVED__SHIFT
81371. BIF_CFG_DEV0_EPF0_VF11_1_SLOT_STATUS2__RESERVED_MASK
81372. BIF_CFG_DEV0_EPF0_VF11_1_SLOT_STATUS2__RESERVED__SHIFT
81373. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST_MASK
81374. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST__SHIFT
81375. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING_MASK
81376. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING__SHIFT
81377. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE_MASK
81378. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE__SHIFT
81379. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__IMMEDIATE_READINESS_MASK
81380. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__IMMEDIATE_READINESS__SHIFT
81381. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS_MASK
81382. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS__SHIFT
81383. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
81384. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
81385. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED_MASK
81386. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
81387. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_CAP_MASK
81388. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_CAP__SHIFT
81389. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_EN_MASK
81390. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_EN__SHIFT
81391. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT_MASK
81392. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
81393. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT_MASK
81394. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
81395. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
81396. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
81397. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT_MASK
81398. BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
81399. BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS_MASK
81400. BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS__SHIFT
81401. BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID_MASK
81402. BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID__SHIFT
81403. BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_ID_MASK
81404. BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
81405. BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
81406. BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
81407. BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1__BASE_ADDR_MASK
81408. BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1__BASE_ADDR__SHIFT
81409. BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2__BASE_ADDR_MASK
81410. BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2__BASE_ADDR__SHIFT
81411. BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3__BASE_ADDR_MASK
81412. BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3__BASE_ADDR__SHIFT
81413. BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4__BASE_ADDR_MASK
81414. BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4__BASE_ADDR__SHIFT
81415. BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5__BASE_ADDR_MASK
81416. BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5__BASE_ADDR__SHIFT
81417. BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6__BASE_ADDR_MASK
81418. BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6__BASE_ADDR__SHIFT
81419. BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS__BASE_CLASS_MASK
81420. BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS__BASE_CLASS__SHIFT
81421. BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_CAP_MASK
81422. BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_CAP__SHIFT
81423. BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_COMP_MASK
81424. BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_COMP__SHIFT
81425. BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_STRT_MASK
81426. BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_STRT__SHIFT
81427. BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE__CACHE_LINE_SIZE_MASK
81428. BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
81429. BIF_CFG_DEV0_EPF0_VF11_CAP_PTR__CAP_PTR_MASK
81430. BIF_CFG_DEV0_EPF0_VF11_CAP_PTR__CAP_PTR__SHIFT
81431. BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
81432. BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
81433. BIF_CFG_DEV0_EPF0_VF11_COMMAND__AD_STEPPING_MASK
81434. BIF_CFG_DEV0_EPF0_VF11_COMMAND__AD_STEPPING__SHIFT
81435. BIF_CFG_DEV0_EPF0_VF11_COMMAND__BUS_MASTER_EN_MASK
81436. BIF_CFG_DEV0_EPF0_VF11_COMMAND__BUS_MASTER_EN__SHIFT
81437. BIF_CFG_DEV0_EPF0_VF11_COMMAND__FAST_B2B_EN_MASK
81438. BIF_CFG_DEV0_EPF0_VF11_COMMAND__FAST_B2B_EN__SHIFT
81439. BIF_CFG_DEV0_EPF0_VF11_COMMAND__INT_DIS_MASK
81440. BIF_CFG_DEV0_EPF0_VF11_COMMAND__INT_DIS__SHIFT
81441. BIF_CFG_DEV0_EPF0_VF11_COMMAND__IO_ACCESS_EN_MASK
81442. BIF_CFG_DEV0_EPF0_VF11_COMMAND__IO_ACCESS_EN__SHIFT
81443. BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_ACCESS_EN_MASK
81444. BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_ACCESS_EN__SHIFT
81445. BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
81446. BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
81447. BIF_CFG_DEV0_EPF0_VF11_COMMAND__PAL_SNOOP_EN_MASK
81448. BIF_CFG_DEV0_EPF0_VF11_COMMAND__PAL_SNOOP_EN__SHIFT
81449. BIF_CFG_DEV0_EPF0_VF11_COMMAND__PARITY_ERROR_RESPONSE_MASK
81450. BIF_CFG_DEV0_EPF0_VF11_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
81451. BIF_CFG_DEV0_EPF0_VF11_COMMAND__SERR_EN_MASK
81452. BIF_CFG_DEV0_EPF0_VF11_COMMAND__SERR_EN__SHIFT
81453. BIF_CFG_DEV0_EPF0_VF11_COMMAND__SPECIAL_CYCLE_EN_MASK
81454. BIF_CFG_DEV0_EPF0_VF11_COMMAND__SPECIAL_CYCLE_EN__SHIFT
81455. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
81456. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
81457. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
81458. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
81459. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
81460. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
81461. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
81462. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
81463. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
81464. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
81465. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
81466. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
81467. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
81468. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
81469. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
81470. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
81471. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
81472. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
81473. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
81474. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
81475. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
81476. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
81477. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__FRS_SUPPORTED_MASK
81478. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
81479. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
81480. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
81481. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LTR_SUPPORTED_MASK
81482. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
81483. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
81484. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
81485. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
81486. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
81487. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__OBFF_SUPPORTED_MASK
81488. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
81489. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
81490. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
81491. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
81492. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
81493. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
81494. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
81495. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
81496. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
81497. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
81498. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
81499. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__EXTENDED_TAG_MASK
81500. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__EXTENDED_TAG__SHIFT
81501. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__FLR_CAPABLE_MASK
81502. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__FLR_CAPABLE__SHIFT
81503. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
81504. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
81505. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
81506. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
81507. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
81508. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
81509. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__PHANTOM_FUNC_MASK
81510. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__PHANTOM_FUNC__SHIFT
81511. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
81512. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
81513. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
81514. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
81515. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
81516. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
81517. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
81518. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
81519. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
81520. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
81521. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
81522. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
81523. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
81524. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
81525. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
81526. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
81527. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
81528. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
81529. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
81530. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
81531. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__LTR_EN_MASK
81532. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__LTR_EN__SHIFT
81533. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__OBFF_EN_MASK
81534. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__OBFF_EN__SHIFT
81535. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
81536. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
81537. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
81538. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
81539. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__CORR_ERR_EN_MASK
81540. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__CORR_ERR_EN__SHIFT
81541. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
81542. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
81543. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__FATAL_ERR_EN_MASK
81544. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
81545. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__INITIATE_FLR_MASK
81546. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__INITIATE_FLR__SHIFT
81547. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
81548. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
81549. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
81550. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
81551. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
81552. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
81553. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NO_SNOOP_EN_MASK
81554. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
81555. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
81556. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
81557. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__RELAXED_ORD_EN_MASK
81558. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
81559. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__USR_REPORT_EN_MASK
81560. BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__USR_REPORT_EN__SHIFT
81561. BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID__DEVICE_ID_MASK
81562. BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID__DEVICE_ID__SHIFT
81563. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2__RESERVED_MASK
81564. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2__RESERVED__SHIFT
81565. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__AUX_PWR_MASK
81566. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__AUX_PWR__SHIFT
81567. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__CORR_ERR_MASK
81568. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__CORR_ERR__SHIFT
81569. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
81570. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
81571. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__FATAL_ERR_MASK
81572. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__FATAL_ERR__SHIFT
81573. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__NON_FATAL_ERR_MASK
81574. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
81575. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
81576. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
81577. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__USR_DETECTED_MASK
81578. BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__USR_DETECTED__SHIFT
81579. BIF_CFG_DEV0_EPF0_VF11_HEADER__DEVICE_TYPE_MASK
81580. BIF_CFG_DEV0_EPF0_VF11_HEADER__DEVICE_TYPE__SHIFT
81581. BIF_CFG_DEV0_EPF0_VF11_HEADER__HEADER_TYPE_MASK
81582. BIF_CFG_DEV0_EPF0_VF11_HEADER__HEADER_TYPE__SHIFT
81583. BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE__INTERRUPT_LINE_MASK
81584. BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
81585. BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN__INTERRUPT_PIN_MASK
81586. BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
81587. BIF_CFG_DEV0_EPF0_VF11_LATENCY__LATENCY_TIMER_MASK
81588. BIF_CFG_DEV0_EPF0_VF11_LATENCY__LATENCY_TIMER__SHIFT
81589. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
81590. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
81591. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
81592. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
81593. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
81594. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
81595. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
81596. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
81597. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
81598. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
81599. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
81600. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
81601. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
81602. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
81603. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
81604. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
81605. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
81606. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
81607. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
81608. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
81609. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L0S_EXIT_LATENCY_MASK
81610. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
81611. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L1_EXIT_LATENCY_MASK
81612. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L1_EXIT_LATENCY__SHIFT
81613. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
81614. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
81615. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_SPEED_MASK
81616. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_SPEED__SHIFT
81617. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_WIDTH_MASK
81618. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_WIDTH__SHIFT
81619. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PM_SUPPORT_MASK
81620. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PM_SUPPORT__SHIFT
81621. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PORT_NUMBER_MASK
81622. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PORT_NUMBER__SHIFT
81623. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
81624. BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
81625. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
81626. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
81627. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_SOS_MASK
81628. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
81629. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_COMPLIANCE_MASK
81630. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
81631. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
81632. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
81633. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
81634. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
81635. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
81636. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
81637. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__TARGET_LINK_SPEED_MASK
81638. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
81639. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__XMIT_MARGIN_MASK
81640. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__XMIT_MARGIN__SHIFT
81641. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
81642. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
81643. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__COMMON_CLOCK_CFG_MASK
81644. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
81645. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
81646. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
81647. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__EXTENDED_SYNC_MASK
81648. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__EXTENDED_SYNC__SHIFT
81649. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
81650. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
81651. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
81652. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
81653. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
81654. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
81655. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_DIS_MASK
81656. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_DIS__SHIFT
81657. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PM_CONTROL_MASK
81658. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PM_CONTROL__SHIFT
81659. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__READ_CPL_BOUNDARY_MASK
81660. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
81661. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__RETRAIN_LINK_MASK
81662. BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__RETRAIN_LINK__SHIFT
81663. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
81664. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
81665. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
81666. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
81667. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
81668. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
81669. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
81670. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
81671. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
81672. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
81673. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
81674. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
81675. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
81676. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
81677. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
81678. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
81679. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
81680. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
81681. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
81682. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
81683. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
81684. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
81685. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__CURRENT_LINK_SPEED_MASK
81686. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
81687. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__DL_ACTIVE_MASK
81688. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__DL_ACTIVE__SHIFT
81689. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
81690. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
81691. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
81692. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
81693. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_TRAINING_MASK
81694. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_TRAINING__SHIFT
81695. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
81696. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
81697. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__SLOT_CLOCK_CFG_MASK
81698. BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
81699. BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY__MAX_LAT_MASK
81700. BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY__MAX_LAT__SHIFT
81701. BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT__MIN_GNT_MASK
81702. BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT__MIN_GNT__SHIFT
81703. BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__CAP_ID_MASK
81704. BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__CAP_ID__SHIFT
81705. BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__NEXT_PTR_MASK
81706. BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__NEXT_PTR__SHIFT
81707. BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_EN_MASK
81708. BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_EN__SHIFT
81709. BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
81710. BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
81711. BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
81712. BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
81713. BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_BIR_MASK
81714. BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_BIR__SHIFT
81715. BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_OFFSET_MASK
81716. BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
81717. BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_BIR_MASK
81718. BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
81719. BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
81720. BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
81721. BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__CAP_ID_MASK
81722. BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__CAP_ID__SHIFT
81723. BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__NEXT_PTR_MASK
81724. BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__NEXT_PTR__SHIFT
81725. BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64__MSI_MASK_64_MASK
81726. BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64__MSI_MASK_64__SHIFT
81727. BIF_CFG_DEV0_EPF0_VF11_MSI_MASK__MSI_MASK_MASK
81728. BIF_CFG_DEV0_EPF0_VF11_MSI_MASK__MSI_MASK__SHIFT
81729. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
81730. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
81731. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
81732. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
81733. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_64BIT_MASK
81734. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_64BIT__SHIFT
81735. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EN_MASK
81736. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EN__SHIFT
81737. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
81738. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
81739. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
81740. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
81741. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
81742. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
81743. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64__MSI_DATA_64_MASK
81744. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
81745. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA__MSI_DATA_MASK
81746. BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA__MSI_DATA__SHIFT
81747. BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64__MSI_PENDING_64_MASK
81748. BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64__MSI_PENDING_64__SHIFT
81749. BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING__MSI_PENDING_MASK
81750. BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING__MSI_PENDING__SHIFT
81751. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
81752. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
81753. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
81754. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
81755. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
81756. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
81757. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
81758. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
81759. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
81760. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
81761. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
81762. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
81763. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
81764. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
81765. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
81766. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
81767. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
81768. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
81769. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
81770. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
81771. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
81772. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
81773. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
81774. BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
81775. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
81776. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
81777. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
81778. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
81779. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
81780. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
81781. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
81782. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
81783. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
81784. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
81785. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
81786. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
81787. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
81788. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
81789. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
81790. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
81791. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
81792. BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
81793. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
81794. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
81795. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
81796. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
81797. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
81798. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
81799. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL__ATC_ENABLE_MASK
81800. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
81801. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL__STU_MASK
81802. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL__STU__SHIFT
81803. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
81804. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
81805. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
81806. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
81807. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
81808. BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
81809. BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__CAP_ID_MASK
81810. BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__CAP_ID__SHIFT
81811. BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__NEXT_PTR_MASK
81812. BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__NEXT_PTR__SHIFT
81813. BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__DEVICE_TYPE_MASK
81814. BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__DEVICE_TYPE__SHIFT
81815. BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__INT_MESSAGE_NUM_MASK
81816. BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
81817. BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__SLOT_IMPLEMENTED_MASK
81818. BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
81819. BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__VERSION_MASK
81820. BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__VERSION__SHIFT
81821. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
81822. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
81823. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
81824. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
81825. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
81826. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
81827. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
81828. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
81829. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
81830. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
81831. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
81832. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
81833. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
81834. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
81835. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
81836. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
81837. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
81838. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
81839. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
81840. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
81841. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
81842. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
81843. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
81844. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
81845. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
81846. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
81847. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
81848. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
81849. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
81850. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
81851. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
81852. BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
81853. BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0__TLP_HDR_MASK
81854. BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0__TLP_HDR__SHIFT
81855. BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1__TLP_HDR_MASK
81856. BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1__TLP_HDR__SHIFT
81857. BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2__TLP_HDR_MASK
81858. BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2__TLP_HDR__SHIFT
81859. BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3__TLP_HDR_MASK
81860. BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3__TLP_HDR__SHIFT
81861. BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
81862. BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
81863. BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
81864. BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
81865. BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
81866. BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
81867. BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
81868. BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
81869. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
81870. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
81871. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
81872. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
81873. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
81874. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
81875. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
81876. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
81877. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
81878. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
81879. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
81880. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
81881. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
81882. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
81883. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
81884. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
81885. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
81886. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
81887. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
81888. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
81889. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
81890. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
81891. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
81892. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
81893. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
81894. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
81895. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
81896. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
81897. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
81898. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
81899. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
81900. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
81901. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
81902. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
81903. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
81904. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
81905. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
81906. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
81907. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
81908. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
81909. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
81910. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
81911. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
81912. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
81913. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
81914. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
81915. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
81916. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
81917. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
81918. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
81919. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
81920. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
81921. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
81922. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
81923. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
81924. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
81925. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
81926. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
81927. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
81928. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
81929. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
81930. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
81931. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
81932. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
81933. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
81934. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
81935. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
81936. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
81937. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
81938. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
81939. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
81940. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
81941. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
81942. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
81943. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
81944. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
81945. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
81946. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
81947. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
81948. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
81949. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
81950. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
81951. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
81952. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
81953. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
81954. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
81955. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
81956. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
81957. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
81958. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
81959. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
81960. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
81961. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
81962. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
81963. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
81964. BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
81965. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
81966. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
81967. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
81968. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
81969. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
81970. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
81971. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
81972. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
81973. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
81974. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
81975. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
81976. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
81977. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
81978. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
81979. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
81980. BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
81981. BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE__PROG_INTERFACE_MASK
81982. BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE__PROG_INTERFACE__SHIFT
81983. BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MAJOR_REV_ID_MASK
81984. BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MAJOR_REV_ID__SHIFT
81985. BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MINOR_REV_ID_MASK
81986. BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MINOR_REV_ID__SHIFT
81987. BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__BASE_ADDR_MASK
81988. BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__BASE_ADDR__SHIFT
81989. BIF_CFG_DEV0_EPF0_VF11_STATUS__CAP_LIST_MASK
81990. BIF_CFG_DEV0_EPF0_VF11_STATUS__CAP_LIST__SHIFT
81991. BIF_CFG_DEV0_EPF0_VF11_STATUS__DEVSEL_TIMING_MASK
81992. BIF_CFG_DEV0_EPF0_VF11_STATUS__DEVSEL_TIMING__SHIFT
81993. BIF_CFG_DEV0_EPF0_VF11_STATUS__FAST_BACK_CAPABLE_MASK
81994. BIF_CFG_DEV0_EPF0_VF11_STATUS__FAST_BACK_CAPABLE__SHIFT
81995. BIF_CFG_DEV0_EPF0_VF11_STATUS__IMMEDIATE_READINESS_MASK
81996. BIF_CFG_DEV0_EPF0_VF11_STATUS__IMMEDIATE_READINESS__SHIFT
81997. BIF_CFG_DEV0_EPF0_VF11_STATUS__INT_STATUS_MASK
81998. BIF_CFG_DEV0_EPF0_VF11_STATUS__INT_STATUS__SHIFT
81999. BIF_CFG_DEV0_EPF0_VF11_STATUS__MASTER_DATA_PARITY_ERROR_MASK
82000. BIF_CFG_DEV0_EPF0_VF11_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
82001. BIF_CFG_DEV0_EPF0_VF11_STATUS__PARITY_ERROR_DETECTED_MASK
82002. BIF_CFG_DEV0_EPF0_VF11_STATUS__PARITY_ERROR_DETECTED__SHIFT
82003. BIF_CFG_DEV0_EPF0_VF11_STATUS__PCI_66_CAP_MASK
82004. BIF_CFG_DEV0_EPF0_VF11_STATUS__PCI_66_CAP__SHIFT
82005. BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_MASTER_ABORT_MASK
82006. BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_MASTER_ABORT__SHIFT
82007. BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_TARGET_ABORT_MASK
82008. BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_TARGET_ABORT__SHIFT
82009. BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNALED_SYSTEM_ERROR_MASK
82010. BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
82011. BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNAL_TARGET_ABORT_MASK
82012. BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNAL_TARGET_ABORT__SHIFT
82013. BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS__SUB_CLASS_MASK
82014. BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS__SUB_CLASS__SHIFT
82015. BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID__VENDOR_ID_MASK
82016. BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID__VENDOR_ID__SHIFT
82017. BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
82018. BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
82019. BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
82020. BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
82021. BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR_MASK
82022. BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR__SHIFT
82023. BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR_MASK
82024. BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR__SHIFT
82025. BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR_MASK
82026. BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR__SHIFT
82027. BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR_MASK
82028. BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR__SHIFT
82029. BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR_MASK
82030. BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR__SHIFT
82031. BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR_MASK
82032. BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR__SHIFT
82033. BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS_MASK
82034. BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS__SHIFT
82035. BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP_MASK
82036. BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP__SHIFT
82037. BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP_MASK
82038. BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP__SHIFT
82039. BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT_MASK
82040. BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT__SHIFT
82041. BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
82042. BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
82043. BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR_MASK
82044. BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR__SHIFT
82045. BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
82046. BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
82047. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING_MASK
82048. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING__SHIFT
82049. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN_MASK
82050. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN__SHIFT
82051. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN_MASK
82052. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN__SHIFT
82053. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS_MASK
82054. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS__SHIFT
82055. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN_MASK
82056. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN__SHIFT
82057. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN_MASK
82058. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN__SHIFT
82059. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
82060. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
82061. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN_MASK
82062. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN__SHIFT
82063. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
82064. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
82065. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN_MASK
82066. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN__SHIFT
82067. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN_MASK
82068. BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
82069. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
82070. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
82071. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
82072. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
82073. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
82074. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
82075. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
82076. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
82077. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
82078. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
82079. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
82080. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
82081. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
82082. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
82083. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
82084. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
82085. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
82086. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
82087. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
82088. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
82089. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
82090. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
82091. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
82092. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
82093. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
82094. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
82095. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
82096. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
82097. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
82098. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
82099. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
82100. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
82101. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
82102. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
82103. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
82104. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
82105. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
82106. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
82107. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
82108. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
82109. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
82110. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
82111. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
82112. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
82113. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG_MASK
82114. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
82115. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE_MASK
82116. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
82117. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
82118. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
82119. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
82120. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
82121. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
82122. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
82123. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC_MASK
82124. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
82125. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
82126. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
82127. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
82128. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
82129. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
82130. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
82131. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
82132. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
82133. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
82134. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
82135. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
82136. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
82137. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
82138. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
82139. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
82140. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
82141. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
82142. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
82143. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
82144. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
82145. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN_MASK
82146. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN__SHIFT
82147. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN_MASK
82148. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN__SHIFT
82149. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
82150. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
82151. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
82152. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
82153. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN_MASK
82154. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
82155. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
82156. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
82157. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
82158. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
82159. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR_MASK
82160. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
82161. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
82162. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
82163. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
82164. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
82165. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
82166. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
82167. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
82168. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
82169. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
82170. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
82171. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
82172. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
82173. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN_MASK
82174. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
82175. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID_MASK
82176. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID__SHIFT
82177. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED_MASK
82178. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED__SHIFT
82179. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR_MASK
82180. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR__SHIFT
82181. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR_MASK
82182. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR__SHIFT
82183. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
82184. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
82185. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR_MASK
82186. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR__SHIFT
82187. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
82188. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
82189. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
82190. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
82191. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED_MASK
82192. BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED__SHIFT
82193. BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE_MASK
82194. BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE__SHIFT
82195. BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE_MASK
82196. BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE__SHIFT
82197. BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
82198. BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
82199. BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
82200. BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
82201. BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER_MASK
82202. BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER__SHIFT
82203. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
82204. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
82205. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
82206. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
82207. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
82208. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
82209. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
82210. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
82211. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RESERVED_MASK
82212. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RESERVED__SHIFT
82213. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
82214. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
82215. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
82216. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
82217. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
82218. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
82219. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
82220. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
82221. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
82222. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
82223. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
82224. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
82225. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
82226. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
82227. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY_MASK
82228. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
82229. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
82230. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
82231. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED_MASK
82232. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED__SHIFT
82233. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH_MASK
82234. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH__SHIFT
82235. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT_MASK
82236. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT__SHIFT
82237. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER_MASK
82238. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER__SHIFT
82239. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
82240. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
82241. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
82242. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
82243. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
82244. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
82245. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
82246. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
82247. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
82248. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
82249. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
82250. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
82251. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
82252. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
82253. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
82254. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
82255. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN_MASK
82256. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
82257. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
82258. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
82259. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
82260. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
82261. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
82262. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
82263. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC_MASK
82264. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
82265. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
82266. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
82267. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
82268. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
82269. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
82270. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
82271. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS_MASK
82272. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS__SHIFT
82273. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL_MASK
82274. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL__SHIFT
82275. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
82276. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
82277. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK_MASK
82278. BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK__SHIFT
82279. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
82280. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
82281. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
82282. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
82283. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
82284. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
82285. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
82286. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
82287. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
82288. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
82289. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
82290. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
82291. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
82292. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
82293. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
82294. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
82295. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
82296. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
82297. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
82298. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
82299. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
82300. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
82301. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
82302. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
82303. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
82304. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
82305. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
82306. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
82307. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
82308. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
82309. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
82310. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
82311. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
82312. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
82313. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE_MASK
82314. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE__SHIFT
82315. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
82316. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
82317. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
82318. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
82319. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING_MASK
82320. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING__SHIFT
82321. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
82322. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
82323. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
82324. BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
82325. BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY__MAX_LAT_MASK
82326. BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY__MAX_LAT__SHIFT
82327. BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT__MIN_GNT_MASK
82328. BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT__MIN_GNT__SHIFT
82329. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID_MASK
82330. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID__SHIFT
82331. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR_MASK
82332. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
82333. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN_MASK
82334. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
82335. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
82336. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
82337. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
82338. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
82339. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR_MASK
82340. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
82341. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
82342. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
82343. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
82344. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
82345. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
82346. BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
82347. BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID_MASK
82348. BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID__SHIFT
82349. BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR_MASK
82350. BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
82351. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64_MASK
82352. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64__SHIFT
82353. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK_MASK
82354. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK__SHIFT
82355. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
82356. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
82357. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
82358. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
82359. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT_MASK
82360. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
82361. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN_MASK
82362. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN__SHIFT
82363. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
82364. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
82365. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
82366. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
82367. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
82368. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
82369. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
82370. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
82371. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA_MASK
82372. BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA__SHIFT
82373. BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64_MASK
82374. BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
82375. BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING_MASK
82376. BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING__SHIFT
82377. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
82378. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
82379. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
82380. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
82381. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
82382. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
82383. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
82384. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
82385. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
82386. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
82387. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
82388. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
82389. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
82390. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
82391. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
82392. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
82393. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
82394. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
82395. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
82396. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
82397. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
82398. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
82399. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
82400. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
82401. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
82402. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
82403. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
82404. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
82405. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
82406. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
82407. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
82408. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
82409. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
82410. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
82411. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
82412. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
82413. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
82414. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
82415. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
82416. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
82417. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
82418. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
82419. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
82420. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
82421. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
82422. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
82423. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
82424. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
82425. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
82426. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
82427. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__STU_MASK
82428. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__STU__SHIFT
82429. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
82430. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
82431. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
82432. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
82433. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
82434. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
82435. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID_MASK
82436. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID__SHIFT
82437. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR_MASK
82438. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
82439. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE_MASK
82440. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE__SHIFT
82441. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
82442. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
82443. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
82444. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
82445. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION_MASK
82446. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION__SHIFT
82447. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
82448. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
82449. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
82450. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
82451. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
82452. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
82453. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
82454. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
82455. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
82456. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
82457. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
82458. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
82459. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
82460. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
82461. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
82462. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
82463. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
82464. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
82465. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
82466. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
82467. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
82468. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
82469. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
82470. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
82471. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
82472. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
82473. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
82474. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
82475. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
82476. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
82477. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
82478. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
82479. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR_MASK
82480. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
82481. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR_MASK
82482. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
82483. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR_MASK
82484. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
82485. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR_MASK
82486. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
82487. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
82488. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
82489. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
82490. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
82491. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
82492. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
82493. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
82494. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
82495. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
82496. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
82497. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
82498. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
82499. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
82500. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
82501. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
82502. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
82503. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
82504. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
82505. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
82506. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
82507. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
82508. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
82509. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
82510. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
82511. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
82512. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
82513. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
82514. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
82515. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
82516. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
82517. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
82518. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
82519. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
82520. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
82521. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
82522. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
82523. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
82524. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
82525. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
82526. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
82527. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
82528. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
82529. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
82530. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
82531. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
82532. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
82533. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
82534. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
82535. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
82536. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
82537. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
82538. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
82539. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
82540. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
82541. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
82542. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
82543. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
82544. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
82545. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
82546. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
82547. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
82548. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
82549. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
82550. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
82551. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
82552. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
82553. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
82554. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
82555. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
82556. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
82557. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
82558. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
82559. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
82560. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
82561. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
82562. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
82563. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
82564. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
82565. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
82566. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
82567. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
82568. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
82569. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
82570. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
82571. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
82572. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
82573. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
82574. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
82575. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
82576. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
82577. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
82578. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
82579. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
82580. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
82581. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
82582. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
82583. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
82584. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
82585. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
82586. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
82587. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
82588. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
82589. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
82590. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
82591. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
82592. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
82593. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
82594. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
82595. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
82596. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
82597. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
82598. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
82599. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
82600. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
82601. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
82602. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
82603. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
82604. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
82605. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
82606. BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
82607. BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE_MASK
82608. BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
82609. BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID_MASK
82610. BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID__SHIFT
82611. BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID_MASK
82612. BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID__SHIFT
82613. BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR_MASK
82614. BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
82615. BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2__RESERVED_MASK
82616. BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2__RESERVED__SHIFT
82617. BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2__RESERVED_MASK
82618. BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2__RESERVED__SHIFT
82619. BIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2__RESERVED_MASK
82620. BIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2__RESERVED__SHIFT
82621. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST_MASK
82622. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST__SHIFT
82623. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING_MASK
82624. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING__SHIFT
82625. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE_MASK
82626. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE__SHIFT
82627. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__IMMEDIATE_READINESS_MASK
82628. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__IMMEDIATE_READINESS__SHIFT
82629. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS_MASK
82630. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS__SHIFT
82631. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
82632. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
82633. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED_MASK
82634. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
82635. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_CAP_MASK
82636. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_CAP__SHIFT
82637. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_EN_MASK
82638. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_EN__SHIFT
82639. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT_MASK
82640. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
82641. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT_MASK
82642. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
82643. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
82644. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
82645. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT_MASK
82646. BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
82647. BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS_MASK
82648. BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS__SHIFT
82649. BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID_MASK
82650. BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID__SHIFT
82651. BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
82652. BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
82653. BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
82654. BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
82655. BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR_MASK
82656. BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR__SHIFT
82657. BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR_MASK
82658. BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR__SHIFT
82659. BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR_MASK
82660. BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR__SHIFT
82661. BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR_MASK
82662. BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR__SHIFT
82663. BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR_MASK
82664. BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR__SHIFT
82665. BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR_MASK
82666. BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR__SHIFT
82667. BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS_MASK
82668. BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS__SHIFT
82669. BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP_MASK
82670. BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP__SHIFT
82671. BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP_MASK
82672. BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP__SHIFT
82673. BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT_MASK
82674. BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT__SHIFT
82675. BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
82676. BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
82677. BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR_MASK
82678. BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR__SHIFT
82679. BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
82680. BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
82681. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING_MASK
82682. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING__SHIFT
82683. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN_MASK
82684. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN__SHIFT
82685. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN_MASK
82686. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN__SHIFT
82687. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS_MASK
82688. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS__SHIFT
82689. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN_MASK
82690. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN__SHIFT
82691. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN_MASK
82692. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN__SHIFT
82693. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
82694. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
82695. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN_MASK
82696. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN__SHIFT
82697. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
82698. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
82699. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN_MASK
82700. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN__SHIFT
82701. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN_MASK
82702. BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
82703. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
82704. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
82705. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
82706. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
82707. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
82708. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
82709. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
82710. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
82711. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
82712. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
82713. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
82714. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
82715. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
82716. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
82717. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
82718. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
82719. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
82720. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
82721. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
82722. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
82723. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
82724. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
82725. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
82726. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
82727. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
82728. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
82729. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
82730. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
82731. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
82732. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
82733. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
82734. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
82735. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
82736. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
82737. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
82738. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
82739. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
82740. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
82741. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
82742. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
82743. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
82744. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
82745. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
82746. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
82747. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG_MASK
82748. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
82749. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE_MASK
82750. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
82751. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
82752. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
82753. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
82754. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
82755. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
82756. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
82757. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC_MASK
82758. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
82759. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
82760. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
82761. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
82762. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
82763. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
82764. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
82765. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
82766. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
82767. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
82768. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
82769. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
82770. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
82771. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
82772. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
82773. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
82774. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
82775. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
82776. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
82777. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
82778. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
82779. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN_MASK
82780. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN__SHIFT
82781. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN_MASK
82782. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN__SHIFT
82783. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
82784. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
82785. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
82786. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
82787. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN_MASK
82788. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
82789. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
82790. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
82791. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
82792. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
82793. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR_MASK
82794. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
82795. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
82796. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
82797. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
82798. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
82799. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
82800. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
82801. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
82802. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
82803. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
82804. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
82805. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
82806. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
82807. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN_MASK
82808. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
82809. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID_MASK
82810. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID__SHIFT
82811. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED_MASK
82812. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED__SHIFT
82813. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR_MASK
82814. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR__SHIFT
82815. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR_MASK
82816. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR__SHIFT
82817. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
82818. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
82819. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR_MASK
82820. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR__SHIFT
82821. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
82822. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
82823. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
82824. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
82825. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED_MASK
82826. BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED__SHIFT
82827. BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE_MASK
82828. BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE__SHIFT
82829. BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE_MASK
82830. BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE__SHIFT
82831. BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
82832. BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
82833. BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
82834. BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
82835. BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER_MASK
82836. BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER__SHIFT
82837. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
82838. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
82839. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
82840. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
82841. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
82842. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
82843. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
82844. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
82845. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RESERVED_MASK
82846. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RESERVED__SHIFT
82847. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
82848. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
82849. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
82850. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
82851. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
82852. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
82853. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
82854. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
82855. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
82856. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
82857. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
82858. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
82859. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
82860. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
82861. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY_MASK
82862. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
82863. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
82864. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
82865. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED_MASK
82866. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED__SHIFT
82867. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH_MASK
82868. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH__SHIFT
82869. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT_MASK
82870. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT__SHIFT
82871. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER_MASK
82872. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER__SHIFT
82873. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
82874. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
82875. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
82876. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
82877. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
82878. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
82879. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
82880. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
82881. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
82882. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
82883. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
82884. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
82885. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
82886. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
82887. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
82888. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
82889. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN_MASK
82890. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
82891. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
82892. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
82893. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
82894. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
82895. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
82896. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
82897. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC_MASK
82898. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
82899. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
82900. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
82901. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
82902. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
82903. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
82904. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
82905. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS_MASK
82906. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS__SHIFT
82907. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL_MASK
82908. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL__SHIFT
82909. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
82910. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
82911. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK_MASK
82912. BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK__SHIFT
82913. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
82914. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
82915. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
82916. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
82917. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
82918. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
82919. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
82920. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
82921. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
82922. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
82923. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
82924. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
82925. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
82926. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
82927. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
82928. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
82929. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
82930. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
82931. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
82932. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
82933. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
82934. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
82935. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
82936. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
82937. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
82938. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
82939. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
82940. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
82941. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
82942. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
82943. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
82944. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
82945. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
82946. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
82947. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE_MASK
82948. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE__SHIFT
82949. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
82950. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
82951. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
82952. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
82953. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING_MASK
82954. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING__SHIFT
82955. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
82956. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
82957. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
82958. BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
82959. BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY__MAX_LAT_MASK
82960. BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY__MAX_LAT__SHIFT
82961. BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT__MIN_GNT_MASK
82962. BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT__MIN_GNT__SHIFT
82963. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID_MASK
82964. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID__SHIFT
82965. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR_MASK
82966. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
82967. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN_MASK
82968. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
82969. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
82970. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
82971. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
82972. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
82973. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR_MASK
82974. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
82975. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
82976. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
82977. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
82978. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
82979. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
82980. BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
82981. BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID_MASK
82982. BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID__SHIFT
82983. BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR_MASK
82984. BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
82985. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64_MASK
82986. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64__SHIFT
82987. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK_MASK
82988. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK__SHIFT
82989. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
82990. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
82991. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
82992. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
82993. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT_MASK
82994. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
82995. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN_MASK
82996. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN__SHIFT
82997. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
82998. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
82999. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
83000. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
83001. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
83002. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
83003. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
83004. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
83005. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA_MASK
83006. BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA__SHIFT
83007. BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64_MASK
83008. BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
83009. BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING_MASK
83010. BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING__SHIFT
83011. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
83012. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
83013. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
83014. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
83015. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
83016. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
83017. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
83018. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
83019. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
83020. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
83021. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
83022. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
83023. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
83024. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
83025. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
83026. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
83027. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
83028. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
83029. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
83030. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
83031. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
83032. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
83033. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
83034. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
83035. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
83036. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
83037. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
83038. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
83039. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
83040. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
83041. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
83042. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
83043. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
83044. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
83045. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
83046. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
83047. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
83048. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
83049. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
83050. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
83051. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
83052. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
83053. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
83054. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
83055. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
83056. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
83057. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
83058. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
83059. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
83060. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
83061. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__STU_MASK
83062. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__STU__SHIFT
83063. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
83064. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
83065. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
83066. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
83067. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
83068. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
83069. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID_MASK
83070. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID__SHIFT
83071. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR_MASK
83072. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
83073. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE_MASK
83074. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE__SHIFT
83075. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
83076. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
83077. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
83078. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
83079. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION_MASK
83080. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION__SHIFT
83081. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
83082. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
83083. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
83084. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
83085. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
83086. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
83087. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
83088. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
83089. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
83090. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
83091. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
83092. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
83093. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
83094. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
83095. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
83096. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
83097. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
83098. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
83099. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
83100. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
83101. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
83102. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
83103. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
83104. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
83105. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
83106. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
83107. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
83108. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
83109. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
83110. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
83111. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
83112. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
83113. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR_MASK
83114. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
83115. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR_MASK
83116. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
83117. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR_MASK
83118. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
83119. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR_MASK
83120. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
83121. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
83122. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
83123. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
83124. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
83125. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
83126. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
83127. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
83128. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
83129. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
83130. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
83131. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
83132. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
83133. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
83134. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
83135. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
83136. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
83137. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
83138. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
83139. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
83140. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
83141. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
83142. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
83143. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
83144. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
83145. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
83146. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
83147. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
83148. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
83149. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
83150. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
83151. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
83152. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
83153. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
83154. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
83155. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
83156. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
83157. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
83158. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
83159. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
83160. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
83161. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
83162. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
83163. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
83164. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
83165. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
83166. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
83167. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
83168. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
83169. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
83170. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
83171. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
83172. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
83173. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
83174. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
83175. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
83176. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
83177. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
83178. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
83179. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
83180. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
83181. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
83182. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
83183. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
83184. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
83185. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
83186. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
83187. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
83188. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
83189. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
83190. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
83191. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
83192. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
83193. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
83194. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
83195. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
83196. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
83197. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
83198. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
83199. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
83200. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
83201. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
83202. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
83203. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
83204. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
83205. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
83206. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
83207. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
83208. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
83209. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
83210. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
83211. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
83212. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
83213. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
83214. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
83215. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
83216. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
83217. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
83218. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
83219. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
83220. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
83221. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
83222. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
83223. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
83224. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
83225. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
83226. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
83227. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
83228. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
83229. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
83230. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
83231. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
83232. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
83233. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
83234. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
83235. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
83236. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
83237. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
83238. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
83239. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
83240. BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
83241. BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE_MASK
83242. BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
83243. BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID_MASK
83244. BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID__SHIFT
83245. BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID_MASK
83246. BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID__SHIFT
83247. BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR_MASK
83248. BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
83249. BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CAP2__RESERVED_MASK
83250. BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CAP2__RESERVED__SHIFT
83251. BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CNTL2__RESERVED_MASK
83252. BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CNTL2__RESERVED__SHIFT
83253. BIF_CFG_DEV0_EPF0_VF12_1_SLOT_STATUS2__RESERVED_MASK
83254. BIF_CFG_DEV0_EPF0_VF12_1_SLOT_STATUS2__RESERVED__SHIFT
83255. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST_MASK
83256. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST__SHIFT
83257. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING_MASK
83258. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING__SHIFT
83259. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE_MASK
83260. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE__SHIFT
83261. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__IMMEDIATE_READINESS_MASK
83262. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__IMMEDIATE_READINESS__SHIFT
83263. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS_MASK
83264. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS__SHIFT
83265. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
83266. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
83267. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED_MASK
83268. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
83269. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_CAP_MASK
83270. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_CAP__SHIFT
83271. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_EN_MASK
83272. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_EN__SHIFT
83273. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT_MASK
83274. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
83275. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT_MASK
83276. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
83277. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
83278. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
83279. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT_MASK
83280. BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
83281. BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS_MASK
83282. BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS__SHIFT
83283. BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID_MASK
83284. BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID__SHIFT
83285. BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_ID_MASK
83286. BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
83287. BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
83288. BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
83289. BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1__BASE_ADDR_MASK
83290. BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1__BASE_ADDR__SHIFT
83291. BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2__BASE_ADDR_MASK
83292. BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2__BASE_ADDR__SHIFT
83293. BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3__BASE_ADDR_MASK
83294. BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3__BASE_ADDR__SHIFT
83295. BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4__BASE_ADDR_MASK
83296. BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4__BASE_ADDR__SHIFT
83297. BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5__BASE_ADDR_MASK
83298. BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5__BASE_ADDR__SHIFT
83299. BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6__BASE_ADDR_MASK
83300. BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6__BASE_ADDR__SHIFT
83301. BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS__BASE_CLASS_MASK
83302. BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS__BASE_CLASS__SHIFT
83303. BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_CAP_MASK
83304. BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_CAP__SHIFT
83305. BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_COMP_MASK
83306. BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_COMP__SHIFT
83307. BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_STRT_MASK
83308. BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_STRT__SHIFT
83309. BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE__CACHE_LINE_SIZE_MASK
83310. BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
83311. BIF_CFG_DEV0_EPF0_VF12_CAP_PTR__CAP_PTR_MASK
83312. BIF_CFG_DEV0_EPF0_VF12_CAP_PTR__CAP_PTR__SHIFT
83313. BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
83314. BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
83315. BIF_CFG_DEV0_EPF0_VF12_COMMAND__AD_STEPPING_MASK
83316. BIF_CFG_DEV0_EPF0_VF12_COMMAND__AD_STEPPING__SHIFT
83317. BIF_CFG_DEV0_EPF0_VF12_COMMAND__BUS_MASTER_EN_MASK
83318. BIF_CFG_DEV0_EPF0_VF12_COMMAND__BUS_MASTER_EN__SHIFT
83319. BIF_CFG_DEV0_EPF0_VF12_COMMAND__FAST_B2B_EN_MASK
83320. BIF_CFG_DEV0_EPF0_VF12_COMMAND__FAST_B2B_EN__SHIFT
83321. BIF_CFG_DEV0_EPF0_VF12_COMMAND__INT_DIS_MASK
83322. BIF_CFG_DEV0_EPF0_VF12_COMMAND__INT_DIS__SHIFT
83323. BIF_CFG_DEV0_EPF0_VF12_COMMAND__IO_ACCESS_EN_MASK
83324. BIF_CFG_DEV0_EPF0_VF12_COMMAND__IO_ACCESS_EN__SHIFT
83325. BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_ACCESS_EN_MASK
83326. BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_ACCESS_EN__SHIFT
83327. BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
83328. BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
83329. BIF_CFG_DEV0_EPF0_VF12_COMMAND__PAL_SNOOP_EN_MASK
83330. BIF_CFG_DEV0_EPF0_VF12_COMMAND__PAL_SNOOP_EN__SHIFT
83331. BIF_CFG_DEV0_EPF0_VF12_COMMAND__PARITY_ERROR_RESPONSE_MASK
83332. BIF_CFG_DEV0_EPF0_VF12_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
83333. BIF_CFG_DEV0_EPF0_VF12_COMMAND__SERR_EN_MASK
83334. BIF_CFG_DEV0_EPF0_VF12_COMMAND__SERR_EN__SHIFT
83335. BIF_CFG_DEV0_EPF0_VF12_COMMAND__SPECIAL_CYCLE_EN_MASK
83336. BIF_CFG_DEV0_EPF0_VF12_COMMAND__SPECIAL_CYCLE_EN__SHIFT
83337. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
83338. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
83339. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
83340. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
83341. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
83342. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
83343. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
83344. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
83345. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
83346. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
83347. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
83348. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
83349. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
83350. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
83351. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
83352. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
83353. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
83354. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
83355. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
83356. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
83357. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
83358. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
83359. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__FRS_SUPPORTED_MASK
83360. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
83361. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
83362. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
83363. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LTR_SUPPORTED_MASK
83364. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
83365. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
83366. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
83367. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
83368. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
83369. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__OBFF_SUPPORTED_MASK
83370. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
83371. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
83372. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
83373. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
83374. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
83375. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
83376. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
83377. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
83378. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
83379. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
83380. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
83381. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__EXTENDED_TAG_MASK
83382. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__EXTENDED_TAG__SHIFT
83383. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__FLR_CAPABLE_MASK
83384. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__FLR_CAPABLE__SHIFT
83385. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
83386. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
83387. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
83388. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
83389. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
83390. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
83391. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__PHANTOM_FUNC_MASK
83392. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__PHANTOM_FUNC__SHIFT
83393. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
83394. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
83395. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
83396. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
83397. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
83398. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
83399. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
83400. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
83401. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
83402. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
83403. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
83404. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
83405. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
83406. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
83407. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
83408. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
83409. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
83410. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
83411. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
83412. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
83413. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__LTR_EN_MASK
83414. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__LTR_EN__SHIFT
83415. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__OBFF_EN_MASK
83416. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__OBFF_EN__SHIFT
83417. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
83418. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
83419. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
83420. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
83421. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__CORR_ERR_EN_MASK
83422. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__CORR_ERR_EN__SHIFT
83423. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
83424. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
83425. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__FATAL_ERR_EN_MASK
83426. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
83427. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__INITIATE_FLR_MASK
83428. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__INITIATE_FLR__SHIFT
83429. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
83430. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
83431. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
83432. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
83433. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
83434. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
83435. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NO_SNOOP_EN_MASK
83436. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
83437. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
83438. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
83439. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__RELAXED_ORD_EN_MASK
83440. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
83441. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__USR_REPORT_EN_MASK
83442. BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__USR_REPORT_EN__SHIFT
83443. BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID__DEVICE_ID_MASK
83444. BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID__DEVICE_ID__SHIFT
83445. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2__RESERVED_MASK
83446. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2__RESERVED__SHIFT
83447. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__AUX_PWR_MASK
83448. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__AUX_PWR__SHIFT
83449. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__CORR_ERR_MASK
83450. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__CORR_ERR__SHIFT
83451. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
83452. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
83453. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__FATAL_ERR_MASK
83454. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__FATAL_ERR__SHIFT
83455. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__NON_FATAL_ERR_MASK
83456. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
83457. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
83458. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
83459. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__USR_DETECTED_MASK
83460. BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__USR_DETECTED__SHIFT
83461. BIF_CFG_DEV0_EPF0_VF12_HEADER__DEVICE_TYPE_MASK
83462. BIF_CFG_DEV0_EPF0_VF12_HEADER__DEVICE_TYPE__SHIFT
83463. BIF_CFG_DEV0_EPF0_VF12_HEADER__HEADER_TYPE_MASK
83464. BIF_CFG_DEV0_EPF0_VF12_HEADER__HEADER_TYPE__SHIFT
83465. BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE__INTERRUPT_LINE_MASK
83466. BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
83467. BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN__INTERRUPT_PIN_MASK
83468. BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
83469. BIF_CFG_DEV0_EPF0_VF12_LATENCY__LATENCY_TIMER_MASK
83470. BIF_CFG_DEV0_EPF0_VF12_LATENCY__LATENCY_TIMER__SHIFT
83471. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
83472. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
83473. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
83474. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
83475. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
83476. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
83477. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
83478. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
83479. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
83480. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
83481. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
83482. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
83483. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
83484. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
83485. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
83486. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
83487. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
83488. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
83489. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
83490. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
83491. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L0S_EXIT_LATENCY_MASK
83492. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
83493. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L1_EXIT_LATENCY_MASK
83494. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L1_EXIT_LATENCY__SHIFT
83495. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
83496. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
83497. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_SPEED_MASK
83498. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_SPEED__SHIFT
83499. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_WIDTH_MASK
83500. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_WIDTH__SHIFT
83501. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PM_SUPPORT_MASK
83502. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PM_SUPPORT__SHIFT
83503. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PORT_NUMBER_MASK
83504. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PORT_NUMBER__SHIFT
83505. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
83506. BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
83507. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
83508. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
83509. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_SOS_MASK
83510. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
83511. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_COMPLIANCE_MASK
83512. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
83513. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
83514. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
83515. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
83516. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
83517. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
83518. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
83519. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__TARGET_LINK_SPEED_MASK
83520. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
83521. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__XMIT_MARGIN_MASK
83522. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__XMIT_MARGIN__SHIFT
83523. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
83524. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
83525. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__COMMON_CLOCK_CFG_MASK
83526. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
83527. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
83528. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
83529. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__EXTENDED_SYNC_MASK
83530. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__EXTENDED_SYNC__SHIFT
83531. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
83532. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
83533. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
83534. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
83535. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
83536. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
83537. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_DIS_MASK
83538. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_DIS__SHIFT
83539. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PM_CONTROL_MASK
83540. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PM_CONTROL__SHIFT
83541. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__READ_CPL_BOUNDARY_MASK
83542. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
83543. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__RETRAIN_LINK_MASK
83544. BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__RETRAIN_LINK__SHIFT
83545. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
83546. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
83547. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
83548. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
83549. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
83550. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
83551. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
83552. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
83553. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
83554. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
83555. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
83556. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
83557. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
83558. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
83559. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
83560. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
83561. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
83562. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
83563. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
83564. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
83565. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
83566. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
83567. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__CURRENT_LINK_SPEED_MASK
83568. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
83569. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__DL_ACTIVE_MASK
83570. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__DL_ACTIVE__SHIFT
83571. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
83572. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
83573. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
83574. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
83575. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_TRAINING_MASK
83576. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_TRAINING__SHIFT
83577. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
83578. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
83579. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__SLOT_CLOCK_CFG_MASK
83580. BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
83581. BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY__MAX_LAT_MASK
83582. BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY__MAX_LAT__SHIFT
83583. BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT__MIN_GNT_MASK
83584. BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT__MIN_GNT__SHIFT
83585. BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__CAP_ID_MASK
83586. BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__CAP_ID__SHIFT
83587. BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__NEXT_PTR_MASK
83588. BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__NEXT_PTR__SHIFT
83589. BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_EN_MASK
83590. BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_EN__SHIFT
83591. BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
83592. BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
83593. BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
83594. BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
83595. BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_BIR_MASK
83596. BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_BIR__SHIFT
83597. BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_OFFSET_MASK
83598. BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
83599. BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_BIR_MASK
83600. BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
83601. BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
83602. BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
83603. BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__CAP_ID_MASK
83604. BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__CAP_ID__SHIFT
83605. BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__NEXT_PTR_MASK
83606. BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__NEXT_PTR__SHIFT
83607. BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64__MSI_MASK_64_MASK
83608. BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64__MSI_MASK_64__SHIFT
83609. BIF_CFG_DEV0_EPF0_VF12_MSI_MASK__MSI_MASK_MASK
83610. BIF_CFG_DEV0_EPF0_VF12_MSI_MASK__MSI_MASK__SHIFT
83611. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
83612. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
83613. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
83614. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
83615. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_64BIT_MASK
83616. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_64BIT__SHIFT
83617. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EN_MASK
83618. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EN__SHIFT
83619. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
83620. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
83621. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
83622. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
83623. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
83624. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
83625. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64__MSI_DATA_64_MASK
83626. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
83627. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA__MSI_DATA_MASK
83628. BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA__MSI_DATA__SHIFT
83629. BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64__MSI_PENDING_64_MASK
83630. BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64__MSI_PENDING_64__SHIFT
83631. BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING__MSI_PENDING_MASK
83632. BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING__MSI_PENDING__SHIFT
83633. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
83634. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
83635. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
83636. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
83637. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
83638. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
83639. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
83640. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
83641. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
83642. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
83643. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
83644. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
83645. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
83646. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
83647. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
83648. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
83649. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
83650. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
83651. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
83652. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
83653. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
83654. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
83655. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
83656. BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
83657. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
83658. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
83659. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
83660. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
83661. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
83662. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
83663. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
83664. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
83665. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
83666. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
83667. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
83668. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
83669. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
83670. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
83671. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
83672. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
83673. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
83674. BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
83675. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
83676. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
83677. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
83678. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
83679. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
83680. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
83681. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL__ATC_ENABLE_MASK
83682. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
83683. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL__STU_MASK
83684. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL__STU__SHIFT
83685. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
83686. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
83687. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
83688. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
83689. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
83690. BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
83691. BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__CAP_ID_MASK
83692. BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__CAP_ID__SHIFT
83693. BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__NEXT_PTR_MASK
83694. BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__NEXT_PTR__SHIFT
83695. BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__DEVICE_TYPE_MASK
83696. BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__DEVICE_TYPE__SHIFT
83697. BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__INT_MESSAGE_NUM_MASK
83698. BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
83699. BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__SLOT_IMPLEMENTED_MASK
83700. BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
83701. BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__VERSION_MASK
83702. BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__VERSION__SHIFT
83703. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
83704. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
83705. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
83706. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
83707. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
83708. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
83709. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
83710. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
83711. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
83712. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
83713. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
83714. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
83715. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
83716. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
83717. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
83718. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
83719. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
83720. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
83721. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
83722. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
83723. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
83724. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
83725. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
83726. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
83727. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
83728. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
83729. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
83730. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
83731. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
83732. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
83733. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
83734. BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
83735. BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0__TLP_HDR_MASK
83736. BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0__TLP_HDR__SHIFT
83737. BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1__TLP_HDR_MASK
83738. BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1__TLP_HDR__SHIFT
83739. BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2__TLP_HDR_MASK
83740. BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2__TLP_HDR__SHIFT
83741. BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3__TLP_HDR_MASK
83742. BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3__TLP_HDR__SHIFT
83743. BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
83744. BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
83745. BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
83746. BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
83747. BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
83748. BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
83749. BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
83750. BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
83751. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
83752. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
83753. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
83754. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
83755. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
83756. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
83757. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
83758. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
83759. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
83760. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
83761. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
83762. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
83763. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
83764. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
83765. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
83766. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
83767. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
83768. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
83769. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
83770. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
83771. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
83772. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
83773. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
83774. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
83775. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
83776. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
83777. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
83778. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
83779. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
83780. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
83781. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
83782. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
83783. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
83784. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
83785. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
83786. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
83787. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
83788. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
83789. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
83790. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
83791. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
83792. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
83793. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
83794. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
83795. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
83796. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
83797. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
83798. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
83799. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
83800. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
83801. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
83802. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
83803. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
83804. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
83805. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
83806. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
83807. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
83808. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
83809. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
83810. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
83811. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
83812. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
83813. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
83814. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
83815. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
83816. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
83817. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
83818. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
83819. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
83820. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
83821. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
83822. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
83823. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
83824. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
83825. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
83826. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
83827. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
83828. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
83829. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
83830. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
83831. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
83832. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
83833. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
83834. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
83835. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
83836. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
83837. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
83838. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
83839. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
83840. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
83841. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
83842. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
83843. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
83844. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
83845. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
83846. BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
83847. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
83848. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
83849. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
83850. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
83851. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
83852. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
83853. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
83854. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
83855. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
83856. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
83857. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
83858. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
83859. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
83860. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
83861. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
83862. BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
83863. BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE__PROG_INTERFACE_MASK
83864. BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE__PROG_INTERFACE__SHIFT
83865. BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MAJOR_REV_ID_MASK
83866. BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MAJOR_REV_ID__SHIFT
83867. BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MINOR_REV_ID_MASK
83868. BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MINOR_REV_ID__SHIFT
83869. BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__BASE_ADDR_MASK
83870. BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__BASE_ADDR__SHIFT
83871. BIF_CFG_DEV0_EPF0_VF12_STATUS__CAP_LIST_MASK
83872. BIF_CFG_DEV0_EPF0_VF12_STATUS__CAP_LIST__SHIFT
83873. BIF_CFG_DEV0_EPF0_VF12_STATUS__DEVSEL_TIMING_MASK
83874. BIF_CFG_DEV0_EPF0_VF12_STATUS__DEVSEL_TIMING__SHIFT
83875. BIF_CFG_DEV0_EPF0_VF12_STATUS__FAST_BACK_CAPABLE_MASK
83876. BIF_CFG_DEV0_EPF0_VF12_STATUS__FAST_BACK_CAPABLE__SHIFT
83877. BIF_CFG_DEV0_EPF0_VF12_STATUS__IMMEDIATE_READINESS_MASK
83878. BIF_CFG_DEV0_EPF0_VF12_STATUS__IMMEDIATE_READINESS__SHIFT
83879. BIF_CFG_DEV0_EPF0_VF12_STATUS__INT_STATUS_MASK
83880. BIF_CFG_DEV0_EPF0_VF12_STATUS__INT_STATUS__SHIFT
83881. BIF_CFG_DEV0_EPF0_VF12_STATUS__MASTER_DATA_PARITY_ERROR_MASK
83882. BIF_CFG_DEV0_EPF0_VF12_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
83883. BIF_CFG_DEV0_EPF0_VF12_STATUS__PARITY_ERROR_DETECTED_MASK
83884. BIF_CFG_DEV0_EPF0_VF12_STATUS__PARITY_ERROR_DETECTED__SHIFT
83885. BIF_CFG_DEV0_EPF0_VF12_STATUS__PCI_66_CAP_MASK
83886. BIF_CFG_DEV0_EPF0_VF12_STATUS__PCI_66_CAP__SHIFT
83887. BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_MASTER_ABORT_MASK
83888. BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_MASTER_ABORT__SHIFT
83889. BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_TARGET_ABORT_MASK
83890. BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_TARGET_ABORT__SHIFT
83891. BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNALED_SYSTEM_ERROR_MASK
83892. BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
83893. BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNAL_TARGET_ABORT_MASK
83894. BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNAL_TARGET_ABORT__SHIFT
83895. BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS__SUB_CLASS_MASK
83896. BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS__SUB_CLASS__SHIFT
83897. BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID__VENDOR_ID_MASK
83898. BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID__VENDOR_ID__SHIFT
83899. BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
83900. BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
83901. BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
83902. BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
83903. BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR_MASK
83904. BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR__SHIFT
83905. BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR_MASK
83906. BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR__SHIFT
83907. BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR_MASK
83908. BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR__SHIFT
83909. BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR_MASK
83910. BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR__SHIFT
83911. BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR_MASK
83912. BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR__SHIFT
83913. BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR_MASK
83914. BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR__SHIFT
83915. BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS_MASK
83916. BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS__SHIFT
83917. BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP_MASK
83918. BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP__SHIFT
83919. BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP_MASK
83920. BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP__SHIFT
83921. BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT_MASK
83922. BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT__SHIFT
83923. BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
83924. BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
83925. BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR_MASK
83926. BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR__SHIFT
83927. BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
83928. BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
83929. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING_MASK
83930. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING__SHIFT
83931. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN_MASK
83932. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN__SHIFT
83933. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN_MASK
83934. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN__SHIFT
83935. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS_MASK
83936. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS__SHIFT
83937. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN_MASK
83938. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN__SHIFT
83939. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN_MASK
83940. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN__SHIFT
83941. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
83942. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
83943. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN_MASK
83944. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN__SHIFT
83945. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
83946. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
83947. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN_MASK
83948. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN__SHIFT
83949. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN_MASK
83950. BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
83951. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
83952. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
83953. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
83954. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
83955. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
83956. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
83957. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
83958. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
83959. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
83960. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
83961. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
83962. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
83963. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
83964. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
83965. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
83966. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
83967. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
83968. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
83969. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
83970. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
83971. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
83972. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
83973. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
83974. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
83975. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
83976. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
83977. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
83978. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
83979. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
83980. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
83981. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
83982. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
83983. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
83984. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
83985. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
83986. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
83987. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
83988. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
83989. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
83990. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
83991. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
83992. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
83993. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
83994. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
83995. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG_MASK
83996. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
83997. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE_MASK
83998. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
83999. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
84000. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
84001. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
84002. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
84003. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
84004. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
84005. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC_MASK
84006. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
84007. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
84008. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
84009. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
84010. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
84011. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
84012. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
84013. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
84014. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
84015. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
84016. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
84017. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
84018. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
84019. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
84020. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
84021. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
84022. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
84023. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
84024. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
84025. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
84026. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
84027. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN_MASK
84028. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN__SHIFT
84029. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN_MASK
84030. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN__SHIFT
84031. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
84032. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
84033. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
84034. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
84035. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN_MASK
84036. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
84037. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
84038. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
84039. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
84040. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
84041. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR_MASK
84042. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
84043. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
84044. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
84045. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
84046. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
84047. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
84048. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
84049. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
84050. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
84051. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
84052. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
84053. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
84054. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
84055. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN_MASK
84056. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
84057. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID_MASK
84058. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID__SHIFT
84059. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED_MASK
84060. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED__SHIFT
84061. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR_MASK
84062. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR__SHIFT
84063. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR_MASK
84064. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR__SHIFT
84065. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
84066. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
84067. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR_MASK
84068. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR__SHIFT
84069. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
84070. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
84071. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
84072. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
84073. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED_MASK
84074. BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED__SHIFT
84075. BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE_MASK
84076. BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE__SHIFT
84077. BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE_MASK
84078. BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE__SHIFT
84079. BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
84080. BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
84081. BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
84082. BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
84083. BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER_MASK
84084. BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER__SHIFT
84085. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
84086. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
84087. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
84088. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
84089. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
84090. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
84091. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
84092. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
84093. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RESERVED_MASK
84094. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RESERVED__SHIFT
84095. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
84096. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
84097. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
84098. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
84099. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
84100. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
84101. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
84102. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
84103. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
84104. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
84105. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
84106. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
84107. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
84108. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
84109. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY_MASK
84110. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
84111. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
84112. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
84113. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED_MASK
84114. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED__SHIFT
84115. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH_MASK
84116. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH__SHIFT
84117. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT_MASK
84118. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT__SHIFT
84119. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER_MASK
84120. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER__SHIFT
84121. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
84122. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
84123. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
84124. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
84125. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
84126. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
84127. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
84128. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
84129. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
84130. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
84131. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
84132. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
84133. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
84134. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
84135. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
84136. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
84137. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN_MASK
84138. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
84139. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
84140. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
84141. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
84142. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
84143. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
84144. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
84145. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC_MASK
84146. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
84147. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
84148. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
84149. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
84150. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
84151. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
84152. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
84153. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS_MASK
84154. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS__SHIFT
84155. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL_MASK
84156. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL__SHIFT
84157. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
84158. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
84159. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK_MASK
84160. BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK__SHIFT
84161. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
84162. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
84163. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
84164. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
84165. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
84166. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
84167. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
84168. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
84169. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
84170. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
84171. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
84172. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
84173. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
84174. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
84175. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
84176. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
84177. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
84178. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
84179. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
84180. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
84181. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
84182. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
84183. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
84184. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
84185. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
84186. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
84187. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
84188. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
84189. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
84190. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
84191. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
84192. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
84193. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
84194. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
84195. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE_MASK
84196. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE__SHIFT
84197. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
84198. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
84199. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
84200. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
84201. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING_MASK
84202. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING__SHIFT
84203. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
84204. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
84205. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
84206. BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
84207. BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY__MAX_LAT_MASK
84208. BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY__MAX_LAT__SHIFT
84209. BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT__MIN_GNT_MASK
84210. BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT__MIN_GNT__SHIFT
84211. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID_MASK
84212. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID__SHIFT
84213. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR_MASK
84214. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
84215. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN_MASK
84216. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
84217. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
84218. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
84219. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
84220. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
84221. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR_MASK
84222. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
84223. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
84224. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
84225. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
84226. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
84227. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
84228. BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
84229. BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID_MASK
84230. BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID__SHIFT
84231. BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR_MASK
84232. BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
84233. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64_MASK
84234. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64__SHIFT
84235. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK_MASK
84236. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK__SHIFT
84237. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
84238. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
84239. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
84240. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
84241. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT_MASK
84242. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
84243. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN_MASK
84244. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN__SHIFT
84245. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
84246. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
84247. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
84248. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
84249. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
84250. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
84251. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
84252. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
84253. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA_MASK
84254. BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA__SHIFT
84255. BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64_MASK
84256. BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
84257. BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING_MASK
84258. BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING__SHIFT
84259. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
84260. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
84261. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
84262. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
84263. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
84264. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
84265. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
84266. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
84267. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
84268. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
84269. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
84270. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
84271. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
84272. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
84273. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
84274. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
84275. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
84276. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
84277. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
84278. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
84279. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
84280. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
84281. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
84282. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
84283. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
84284. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
84285. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
84286. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
84287. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
84288. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
84289. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
84290. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
84291. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
84292. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
84293. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
84294. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
84295. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
84296. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
84297. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
84298. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
84299. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
84300. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
84301. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
84302. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
84303. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
84304. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
84305. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
84306. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
84307. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
84308. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
84309. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__STU_MASK
84310. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__STU__SHIFT
84311. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
84312. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
84313. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
84314. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
84315. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
84316. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
84317. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID_MASK
84318. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID__SHIFT
84319. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR_MASK
84320. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
84321. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE_MASK
84322. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE__SHIFT
84323. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
84324. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
84325. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
84326. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
84327. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION_MASK
84328. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION__SHIFT
84329. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
84330. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
84331. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
84332. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
84333. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
84334. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
84335. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
84336. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
84337. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
84338. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
84339. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
84340. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
84341. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
84342. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
84343. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
84344. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
84345. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
84346. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
84347. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
84348. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
84349. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
84350. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
84351. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
84352. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
84353. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
84354. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
84355. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
84356. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
84357. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
84358. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
84359. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
84360. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
84361. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR_MASK
84362. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
84363. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR_MASK
84364. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
84365. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR_MASK
84366. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
84367. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR_MASK
84368. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
84369. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
84370. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
84371. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
84372. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
84373. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
84374. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
84375. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
84376. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
84377. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
84378. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
84379. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
84380. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
84381. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
84382. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
84383. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
84384. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
84385. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
84386. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
84387. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
84388. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
84389. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
84390. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
84391. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
84392. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
84393. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
84394. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
84395. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
84396. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
84397. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
84398. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
84399. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
84400. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
84401. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
84402. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
84403. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
84404. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
84405. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
84406. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
84407. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
84408. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
84409. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
84410. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
84411. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
84412. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
84413. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
84414. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
84415. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
84416. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
84417. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
84418. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
84419. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
84420. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
84421. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
84422. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
84423. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
84424. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
84425. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
84426. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
84427. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
84428. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
84429. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
84430. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
84431. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
84432. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
84433. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
84434. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
84435. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
84436. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
84437. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
84438. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
84439. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
84440. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
84441. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
84442. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
84443. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
84444. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
84445. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
84446. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
84447. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
84448. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
84449. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
84450. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
84451. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
84452. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
84453. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
84454. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
84455. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
84456. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
84457. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
84458. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
84459. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
84460. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
84461. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
84462. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
84463. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
84464. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
84465. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
84466. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
84467. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
84468. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
84469. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
84470. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
84471. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
84472. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
84473. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
84474. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
84475. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
84476. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
84477. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
84478. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
84479. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
84480. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
84481. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
84482. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
84483. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
84484. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
84485. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
84486. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
84487. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
84488. BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
84489. BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE_MASK
84490. BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
84491. BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID_MASK
84492. BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID__SHIFT
84493. BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID_MASK
84494. BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID__SHIFT
84495. BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR_MASK
84496. BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
84497. BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2__RESERVED_MASK
84498. BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2__RESERVED__SHIFT
84499. BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2__RESERVED_MASK
84500. BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2__RESERVED__SHIFT
84501. BIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2__RESERVED_MASK
84502. BIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2__RESERVED__SHIFT
84503. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST_MASK
84504. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST__SHIFT
84505. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING_MASK
84506. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING__SHIFT
84507. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE_MASK
84508. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE__SHIFT
84509. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__IMMEDIATE_READINESS_MASK
84510. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__IMMEDIATE_READINESS__SHIFT
84511. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS_MASK
84512. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS__SHIFT
84513. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
84514. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
84515. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED_MASK
84516. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
84517. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_CAP_MASK
84518. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_CAP__SHIFT
84519. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_EN_MASK
84520. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_EN__SHIFT
84521. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT_MASK
84522. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
84523. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT_MASK
84524. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
84525. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
84526. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
84527. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT_MASK
84528. BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
84529. BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS_MASK
84530. BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS__SHIFT
84531. BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID_MASK
84532. BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID__SHIFT
84533. BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
84534. BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
84535. BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
84536. BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
84537. BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR_MASK
84538. BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR__SHIFT
84539. BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR_MASK
84540. BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR__SHIFT
84541. BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR_MASK
84542. BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR__SHIFT
84543. BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR_MASK
84544. BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR__SHIFT
84545. BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR_MASK
84546. BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR__SHIFT
84547. BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR_MASK
84548. BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR__SHIFT
84549. BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS_MASK
84550. BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS__SHIFT
84551. BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP_MASK
84552. BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP__SHIFT
84553. BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP_MASK
84554. BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP__SHIFT
84555. BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT_MASK
84556. BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT__SHIFT
84557. BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
84558. BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
84559. BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR_MASK
84560. BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR__SHIFT
84561. BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
84562. BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
84563. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING_MASK
84564. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING__SHIFT
84565. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN_MASK
84566. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN__SHIFT
84567. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN_MASK
84568. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN__SHIFT
84569. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS_MASK
84570. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS__SHIFT
84571. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN_MASK
84572. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN__SHIFT
84573. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN_MASK
84574. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN__SHIFT
84575. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
84576. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
84577. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN_MASK
84578. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN__SHIFT
84579. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
84580. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
84581. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN_MASK
84582. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN__SHIFT
84583. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN_MASK
84584. BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
84585. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
84586. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
84587. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
84588. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
84589. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
84590. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
84591. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
84592. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
84593. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
84594. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
84595. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
84596. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
84597. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
84598. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
84599. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
84600. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
84601. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
84602. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
84603. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
84604. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
84605. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
84606. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
84607. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
84608. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
84609. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
84610. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
84611. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
84612. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
84613. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
84614. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
84615. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
84616. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
84617. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
84618. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
84619. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
84620. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
84621. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
84622. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
84623. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
84624. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
84625. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
84626. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
84627. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
84628. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
84629. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG_MASK
84630. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
84631. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE_MASK
84632. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
84633. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
84634. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
84635. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
84636. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
84637. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
84638. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
84639. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC_MASK
84640. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
84641. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
84642. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
84643. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
84644. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
84645. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
84646. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
84647. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
84648. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
84649. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
84650. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
84651. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
84652. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
84653. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
84654. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
84655. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
84656. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
84657. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
84658. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
84659. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
84660. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
84661. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN_MASK
84662. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN__SHIFT
84663. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN_MASK
84664. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN__SHIFT
84665. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
84666. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
84667. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
84668. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
84669. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN_MASK
84670. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
84671. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
84672. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
84673. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
84674. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
84675. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR_MASK
84676. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
84677. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
84678. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
84679. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
84680. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
84681. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
84682. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
84683. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
84684. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
84685. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
84686. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
84687. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
84688. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
84689. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN_MASK
84690. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
84691. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID_MASK
84692. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID__SHIFT
84693. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED_MASK
84694. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED__SHIFT
84695. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR_MASK
84696. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR__SHIFT
84697. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR_MASK
84698. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR__SHIFT
84699. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
84700. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
84701. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR_MASK
84702. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR__SHIFT
84703. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
84704. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
84705. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
84706. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
84707. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED_MASK
84708. BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED__SHIFT
84709. BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE_MASK
84710. BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE__SHIFT
84711. BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE_MASK
84712. BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE__SHIFT
84713. BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
84714. BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
84715. BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
84716. BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
84717. BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER_MASK
84718. BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER__SHIFT
84719. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
84720. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
84721. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
84722. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
84723. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
84724. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
84725. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
84726. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
84727. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RESERVED_MASK
84728. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RESERVED__SHIFT
84729. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
84730. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
84731. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
84732. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
84733. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
84734. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
84735. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
84736. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
84737. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
84738. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
84739. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
84740. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
84741. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
84742. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
84743. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY_MASK
84744. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
84745. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
84746. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
84747. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED_MASK
84748. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED__SHIFT
84749. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH_MASK
84750. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH__SHIFT
84751. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT_MASK
84752. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT__SHIFT
84753. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER_MASK
84754. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER__SHIFT
84755. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
84756. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
84757. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
84758. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
84759. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
84760. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
84761. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
84762. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
84763. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
84764. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
84765. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
84766. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
84767. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
84768. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
84769. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
84770. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
84771. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN_MASK
84772. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
84773. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
84774. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
84775. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
84776. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
84777. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
84778. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
84779. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC_MASK
84780. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
84781. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
84782. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
84783. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
84784. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
84785. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
84786. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
84787. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS_MASK
84788. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS__SHIFT
84789. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL_MASK
84790. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL__SHIFT
84791. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
84792. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
84793. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK_MASK
84794. BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK__SHIFT
84795. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
84796. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
84797. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
84798. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
84799. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
84800. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
84801. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
84802. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
84803. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
84804. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
84805. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
84806. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
84807. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
84808. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
84809. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
84810. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
84811. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
84812. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
84813. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
84814. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
84815. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
84816. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
84817. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
84818. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
84819. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
84820. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
84821. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
84822. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
84823. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
84824. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
84825. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
84826. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
84827. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
84828. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
84829. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE_MASK
84830. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE__SHIFT
84831. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
84832. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
84833. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
84834. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
84835. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING_MASK
84836. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING__SHIFT
84837. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
84838. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
84839. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
84840. BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
84841. BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY__MAX_LAT_MASK
84842. BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY__MAX_LAT__SHIFT
84843. BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT__MIN_GNT_MASK
84844. BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT__MIN_GNT__SHIFT
84845. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID_MASK
84846. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID__SHIFT
84847. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR_MASK
84848. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
84849. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN_MASK
84850. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
84851. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
84852. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
84853. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
84854. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
84855. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR_MASK
84856. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
84857. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
84858. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
84859. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
84860. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
84861. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
84862. BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
84863. BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID_MASK
84864. BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID__SHIFT
84865. BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR_MASK
84866. BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
84867. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64_MASK
84868. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64__SHIFT
84869. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK_MASK
84870. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK__SHIFT
84871. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
84872. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
84873. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
84874. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
84875. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT_MASK
84876. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
84877. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN_MASK
84878. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN__SHIFT
84879. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
84880. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
84881. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
84882. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
84883. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
84884. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
84885. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
84886. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
84887. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA_MASK
84888. BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA__SHIFT
84889. BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64_MASK
84890. BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
84891. BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING_MASK
84892. BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING__SHIFT
84893. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
84894. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
84895. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
84896. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
84897. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
84898. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
84899. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
84900. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
84901. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
84902. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
84903. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
84904. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
84905. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
84906. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
84907. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
84908. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
84909. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
84910. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
84911. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
84912. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
84913. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
84914. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
84915. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
84916. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
84917. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
84918. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
84919. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
84920. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
84921. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
84922. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
84923. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
84924. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
84925. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
84926. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
84927. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
84928. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
84929. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
84930. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
84931. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
84932. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
84933. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
84934. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
84935. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
84936. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
84937. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
84938. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
84939. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
84940. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
84941. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
84942. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
84943. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__STU_MASK
84944. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__STU__SHIFT
84945. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
84946. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
84947. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
84948. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
84949. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
84950. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
84951. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID_MASK
84952. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID__SHIFT
84953. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR_MASK
84954. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
84955. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE_MASK
84956. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE__SHIFT
84957. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
84958. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
84959. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
84960. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
84961. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION_MASK
84962. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION__SHIFT
84963. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
84964. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
84965. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
84966. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
84967. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
84968. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
84969. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
84970. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
84971. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
84972. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
84973. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
84974. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
84975. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
84976. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
84977. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
84978. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
84979. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
84980. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
84981. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
84982. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
84983. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
84984. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
84985. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
84986. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
84987. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
84988. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
84989. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
84990. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
84991. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
84992. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
84993. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
84994. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
84995. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR_MASK
84996. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
84997. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR_MASK
84998. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
84999. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR_MASK
85000. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
85001. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR_MASK
85002. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
85003. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
85004. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
85005. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
85006. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
85007. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
85008. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
85009. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
85010. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
85011. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
85012. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
85013. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
85014. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
85015. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
85016. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
85017. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
85018. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
85019. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
85020. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
85021. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
85022. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
85023. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
85024. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
85025. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
85026. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
85027. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
85028. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
85029. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
85030. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
85031. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
85032. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
85033. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
85034. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
85035. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
85036. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
85037. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
85038. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
85039. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
85040. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
85041. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
85042. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
85043. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
85044. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
85045. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
85046. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
85047. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
85048. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
85049. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
85050. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
85051. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
85052. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
85053. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
85054. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
85055. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
85056. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
85057. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
85058. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
85059. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
85060. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
85061. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
85062. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
85063. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
85064. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
85065. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
85066. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
85067. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
85068. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
85069. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
85070. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
85071. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
85072. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
85073. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
85074. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
85075. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
85076. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
85077. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
85078. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
85079. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
85080. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
85081. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
85082. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
85083. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
85084. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
85085. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
85086. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
85087. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
85088. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
85089. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
85090. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
85091. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
85092. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
85093. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
85094. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
85095. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
85096. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
85097. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
85098. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
85099. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
85100. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
85101. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
85102. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
85103. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
85104. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
85105. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
85106. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
85107. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
85108. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
85109. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
85110. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
85111. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
85112. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
85113. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
85114. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
85115. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
85116. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
85117. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
85118. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
85119. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
85120. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
85121. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
85122. BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
85123. BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE_MASK
85124. BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
85125. BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID_MASK
85126. BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID__SHIFT
85127. BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID_MASK
85128. BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID__SHIFT
85129. BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR_MASK
85130. BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
85131. BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CAP2__RESERVED_MASK
85132. BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CAP2__RESERVED__SHIFT
85133. BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CNTL2__RESERVED_MASK
85134. BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CNTL2__RESERVED__SHIFT
85135. BIF_CFG_DEV0_EPF0_VF13_1_SLOT_STATUS2__RESERVED_MASK
85136. BIF_CFG_DEV0_EPF0_VF13_1_SLOT_STATUS2__RESERVED__SHIFT
85137. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST_MASK
85138. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST__SHIFT
85139. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING_MASK
85140. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING__SHIFT
85141. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE_MASK
85142. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE__SHIFT
85143. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__IMMEDIATE_READINESS_MASK
85144. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__IMMEDIATE_READINESS__SHIFT
85145. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS_MASK
85146. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS__SHIFT
85147. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
85148. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
85149. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED_MASK
85150. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
85151. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_CAP_MASK
85152. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_CAP__SHIFT
85153. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_EN_MASK
85154. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_EN__SHIFT
85155. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT_MASK
85156. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
85157. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT_MASK
85158. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
85159. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
85160. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
85161. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT_MASK
85162. BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
85163. BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS_MASK
85164. BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS__SHIFT
85165. BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID_MASK
85166. BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID__SHIFT
85167. BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_ID_MASK
85168. BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
85169. BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
85170. BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
85171. BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1__BASE_ADDR_MASK
85172. BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1__BASE_ADDR__SHIFT
85173. BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2__BASE_ADDR_MASK
85174. BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2__BASE_ADDR__SHIFT
85175. BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3__BASE_ADDR_MASK
85176. BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3__BASE_ADDR__SHIFT
85177. BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4__BASE_ADDR_MASK
85178. BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4__BASE_ADDR__SHIFT
85179. BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5__BASE_ADDR_MASK
85180. BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5__BASE_ADDR__SHIFT
85181. BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6__BASE_ADDR_MASK
85182. BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6__BASE_ADDR__SHIFT
85183. BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS__BASE_CLASS_MASK
85184. BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS__BASE_CLASS__SHIFT
85185. BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_CAP_MASK
85186. BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_CAP__SHIFT
85187. BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_COMP_MASK
85188. BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_COMP__SHIFT
85189. BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_STRT_MASK
85190. BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_STRT__SHIFT
85191. BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE__CACHE_LINE_SIZE_MASK
85192. BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
85193. BIF_CFG_DEV0_EPF0_VF13_CAP_PTR__CAP_PTR_MASK
85194. BIF_CFG_DEV0_EPF0_VF13_CAP_PTR__CAP_PTR__SHIFT
85195. BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
85196. BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
85197. BIF_CFG_DEV0_EPF0_VF13_COMMAND__AD_STEPPING_MASK
85198. BIF_CFG_DEV0_EPF0_VF13_COMMAND__AD_STEPPING__SHIFT
85199. BIF_CFG_DEV0_EPF0_VF13_COMMAND__BUS_MASTER_EN_MASK
85200. BIF_CFG_DEV0_EPF0_VF13_COMMAND__BUS_MASTER_EN__SHIFT
85201. BIF_CFG_DEV0_EPF0_VF13_COMMAND__FAST_B2B_EN_MASK
85202. BIF_CFG_DEV0_EPF0_VF13_COMMAND__FAST_B2B_EN__SHIFT
85203. BIF_CFG_DEV0_EPF0_VF13_COMMAND__INT_DIS_MASK
85204. BIF_CFG_DEV0_EPF0_VF13_COMMAND__INT_DIS__SHIFT
85205. BIF_CFG_DEV0_EPF0_VF13_COMMAND__IO_ACCESS_EN_MASK
85206. BIF_CFG_DEV0_EPF0_VF13_COMMAND__IO_ACCESS_EN__SHIFT
85207. BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_ACCESS_EN_MASK
85208. BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_ACCESS_EN__SHIFT
85209. BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
85210. BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
85211. BIF_CFG_DEV0_EPF0_VF13_COMMAND__PAL_SNOOP_EN_MASK
85212. BIF_CFG_DEV0_EPF0_VF13_COMMAND__PAL_SNOOP_EN__SHIFT
85213. BIF_CFG_DEV0_EPF0_VF13_COMMAND__PARITY_ERROR_RESPONSE_MASK
85214. BIF_CFG_DEV0_EPF0_VF13_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
85215. BIF_CFG_DEV0_EPF0_VF13_COMMAND__SERR_EN_MASK
85216. BIF_CFG_DEV0_EPF0_VF13_COMMAND__SERR_EN__SHIFT
85217. BIF_CFG_DEV0_EPF0_VF13_COMMAND__SPECIAL_CYCLE_EN_MASK
85218. BIF_CFG_DEV0_EPF0_VF13_COMMAND__SPECIAL_CYCLE_EN__SHIFT
85219. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
85220. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
85221. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
85222. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
85223. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
85224. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
85225. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
85226. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
85227. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
85228. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
85229. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
85230. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
85231. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
85232. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
85233. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
85234. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
85235. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
85236. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
85237. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
85238. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
85239. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
85240. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
85241. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__FRS_SUPPORTED_MASK
85242. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
85243. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
85244. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
85245. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LTR_SUPPORTED_MASK
85246. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
85247. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
85248. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
85249. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
85250. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
85251. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__OBFF_SUPPORTED_MASK
85252. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
85253. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
85254. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
85255. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
85256. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
85257. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
85258. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
85259. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
85260. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
85261. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
85262. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
85263. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__EXTENDED_TAG_MASK
85264. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__EXTENDED_TAG__SHIFT
85265. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__FLR_CAPABLE_MASK
85266. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__FLR_CAPABLE__SHIFT
85267. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
85268. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
85269. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
85270. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
85271. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
85272. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
85273. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__PHANTOM_FUNC_MASK
85274. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__PHANTOM_FUNC__SHIFT
85275. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
85276. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
85277. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
85278. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
85279. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
85280. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
85281. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
85282. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
85283. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
85284. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
85285. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
85286. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
85287. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
85288. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
85289. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
85290. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
85291. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
85292. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
85293. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
85294. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
85295. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__LTR_EN_MASK
85296. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__LTR_EN__SHIFT
85297. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__OBFF_EN_MASK
85298. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__OBFF_EN__SHIFT
85299. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
85300. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
85301. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
85302. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
85303. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__CORR_ERR_EN_MASK
85304. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__CORR_ERR_EN__SHIFT
85305. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
85306. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
85307. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__FATAL_ERR_EN_MASK
85308. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
85309. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__INITIATE_FLR_MASK
85310. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__INITIATE_FLR__SHIFT
85311. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
85312. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
85313. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
85314. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
85315. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
85316. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
85317. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NO_SNOOP_EN_MASK
85318. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
85319. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
85320. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
85321. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__RELAXED_ORD_EN_MASK
85322. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
85323. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__USR_REPORT_EN_MASK
85324. BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__USR_REPORT_EN__SHIFT
85325. BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID__DEVICE_ID_MASK
85326. BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID__DEVICE_ID__SHIFT
85327. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2__RESERVED_MASK
85328. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2__RESERVED__SHIFT
85329. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__AUX_PWR_MASK
85330. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__AUX_PWR__SHIFT
85331. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__CORR_ERR_MASK
85332. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__CORR_ERR__SHIFT
85333. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
85334. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
85335. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__FATAL_ERR_MASK
85336. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__FATAL_ERR__SHIFT
85337. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__NON_FATAL_ERR_MASK
85338. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
85339. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
85340. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
85341. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__USR_DETECTED_MASK
85342. BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__USR_DETECTED__SHIFT
85343. BIF_CFG_DEV0_EPF0_VF13_HEADER__DEVICE_TYPE_MASK
85344. BIF_CFG_DEV0_EPF0_VF13_HEADER__DEVICE_TYPE__SHIFT
85345. BIF_CFG_DEV0_EPF0_VF13_HEADER__HEADER_TYPE_MASK
85346. BIF_CFG_DEV0_EPF0_VF13_HEADER__HEADER_TYPE__SHIFT
85347. BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE__INTERRUPT_LINE_MASK
85348. BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
85349. BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN__INTERRUPT_PIN_MASK
85350. BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
85351. BIF_CFG_DEV0_EPF0_VF13_LATENCY__LATENCY_TIMER_MASK
85352. BIF_CFG_DEV0_EPF0_VF13_LATENCY__LATENCY_TIMER__SHIFT
85353. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
85354. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
85355. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
85356. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
85357. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
85358. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
85359. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
85360. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
85361. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
85362. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
85363. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
85364. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
85365. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
85366. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
85367. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
85368. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
85369. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
85370. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
85371. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
85372. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
85373. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L0S_EXIT_LATENCY_MASK
85374. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
85375. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L1_EXIT_LATENCY_MASK
85376. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L1_EXIT_LATENCY__SHIFT
85377. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
85378. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
85379. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_SPEED_MASK
85380. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_SPEED__SHIFT
85381. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_WIDTH_MASK
85382. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_WIDTH__SHIFT
85383. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PM_SUPPORT_MASK
85384. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PM_SUPPORT__SHIFT
85385. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PORT_NUMBER_MASK
85386. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PORT_NUMBER__SHIFT
85387. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
85388. BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
85389. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
85390. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
85391. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_SOS_MASK
85392. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
85393. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_COMPLIANCE_MASK
85394. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
85395. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
85396. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
85397. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
85398. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
85399. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
85400. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
85401. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__TARGET_LINK_SPEED_MASK
85402. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
85403. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__XMIT_MARGIN_MASK
85404. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__XMIT_MARGIN__SHIFT
85405. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
85406. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
85407. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__COMMON_CLOCK_CFG_MASK
85408. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
85409. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
85410. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
85411. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__EXTENDED_SYNC_MASK
85412. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__EXTENDED_SYNC__SHIFT
85413. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
85414. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
85415. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
85416. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
85417. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
85418. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
85419. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_DIS_MASK
85420. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_DIS__SHIFT
85421. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PM_CONTROL_MASK
85422. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PM_CONTROL__SHIFT
85423. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__READ_CPL_BOUNDARY_MASK
85424. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
85425. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__RETRAIN_LINK_MASK
85426. BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__RETRAIN_LINK__SHIFT
85427. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
85428. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
85429. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
85430. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
85431. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
85432. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
85433. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
85434. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
85435. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
85436. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
85437. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
85438. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
85439. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
85440. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
85441. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
85442. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
85443. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
85444. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
85445. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
85446. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
85447. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
85448. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
85449. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__CURRENT_LINK_SPEED_MASK
85450. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
85451. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__DL_ACTIVE_MASK
85452. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__DL_ACTIVE__SHIFT
85453. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
85454. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
85455. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
85456. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
85457. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_TRAINING_MASK
85458. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_TRAINING__SHIFT
85459. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
85460. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
85461. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__SLOT_CLOCK_CFG_MASK
85462. BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
85463. BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY__MAX_LAT_MASK
85464. BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY__MAX_LAT__SHIFT
85465. BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT__MIN_GNT_MASK
85466. BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT__MIN_GNT__SHIFT
85467. BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__CAP_ID_MASK
85468. BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__CAP_ID__SHIFT
85469. BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__NEXT_PTR_MASK
85470. BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__NEXT_PTR__SHIFT
85471. BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_EN_MASK
85472. BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_EN__SHIFT
85473. BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
85474. BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
85475. BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
85476. BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
85477. BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_BIR_MASK
85478. BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_BIR__SHIFT
85479. BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_OFFSET_MASK
85480. BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
85481. BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_BIR_MASK
85482. BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
85483. BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
85484. BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
85485. BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__CAP_ID_MASK
85486. BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__CAP_ID__SHIFT
85487. BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__NEXT_PTR_MASK
85488. BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__NEXT_PTR__SHIFT
85489. BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64__MSI_MASK_64_MASK
85490. BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64__MSI_MASK_64__SHIFT
85491. BIF_CFG_DEV0_EPF0_VF13_MSI_MASK__MSI_MASK_MASK
85492. BIF_CFG_DEV0_EPF0_VF13_MSI_MASK__MSI_MASK__SHIFT
85493. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
85494. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
85495. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
85496. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
85497. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_64BIT_MASK
85498. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_64BIT__SHIFT
85499. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EN_MASK
85500. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EN__SHIFT
85501. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
85502. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
85503. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
85504. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
85505. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
85506. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
85507. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64__MSI_DATA_64_MASK
85508. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
85509. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA__MSI_DATA_MASK
85510. BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA__MSI_DATA__SHIFT
85511. BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64__MSI_PENDING_64_MASK
85512. BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64__MSI_PENDING_64__SHIFT
85513. BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING__MSI_PENDING_MASK
85514. BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING__MSI_PENDING__SHIFT
85515. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
85516. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
85517. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
85518. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
85519. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
85520. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
85521. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
85522. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
85523. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
85524. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
85525. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
85526. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
85527. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
85528. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
85529. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
85530. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
85531. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
85532. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
85533. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
85534. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
85535. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
85536. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
85537. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
85538. BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
85539. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
85540. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
85541. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
85542. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
85543. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
85544. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
85545. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
85546. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
85547. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
85548. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
85549. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
85550. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
85551. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
85552. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
85553. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
85554. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
85555. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
85556. BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
85557. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
85558. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
85559. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
85560. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
85561. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
85562. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
85563. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL__ATC_ENABLE_MASK
85564. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
85565. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL__STU_MASK
85566. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL__STU__SHIFT
85567. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
85568. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
85569. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
85570. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
85571. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
85572. BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
85573. BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__CAP_ID_MASK
85574. BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__CAP_ID__SHIFT
85575. BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__NEXT_PTR_MASK
85576. BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__NEXT_PTR__SHIFT
85577. BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__DEVICE_TYPE_MASK
85578. BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__DEVICE_TYPE__SHIFT
85579. BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__INT_MESSAGE_NUM_MASK
85580. BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
85581. BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__SLOT_IMPLEMENTED_MASK
85582. BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
85583. BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__VERSION_MASK
85584. BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__VERSION__SHIFT
85585. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
85586. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
85587. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
85588. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
85589. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
85590. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
85591. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
85592. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
85593. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
85594. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
85595. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
85596. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
85597. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
85598. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
85599. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
85600. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
85601. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
85602. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
85603. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
85604. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
85605. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
85606. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
85607. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
85608. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
85609. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
85610. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
85611. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
85612. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
85613. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
85614. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
85615. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
85616. BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
85617. BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0__TLP_HDR_MASK
85618. BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0__TLP_HDR__SHIFT
85619. BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1__TLP_HDR_MASK
85620. BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1__TLP_HDR__SHIFT
85621. BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2__TLP_HDR_MASK
85622. BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2__TLP_HDR__SHIFT
85623. BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3__TLP_HDR_MASK
85624. BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3__TLP_HDR__SHIFT
85625. BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
85626. BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
85627. BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
85628. BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
85629. BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
85630. BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
85631. BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
85632. BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
85633. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
85634. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
85635. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
85636. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
85637. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
85638. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
85639. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
85640. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
85641. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
85642. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
85643. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
85644. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
85645. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
85646. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
85647. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
85648. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
85649. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
85650. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
85651. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
85652. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
85653. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
85654. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
85655. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
85656. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
85657. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
85658. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
85659. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
85660. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
85661. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
85662. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
85663. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
85664. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
85665. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
85666. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
85667. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
85668. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
85669. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
85670. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
85671. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
85672. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
85673. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
85674. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
85675. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
85676. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
85677. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
85678. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
85679. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
85680. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
85681. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
85682. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
85683. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
85684. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
85685. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
85686. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
85687. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
85688. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
85689. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
85690. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
85691. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
85692. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
85693. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
85694. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
85695. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
85696. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
85697. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
85698. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
85699. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
85700. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
85701. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
85702. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
85703. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
85704. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
85705. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
85706. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
85707. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
85708. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
85709. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
85710. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
85711. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
85712. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
85713. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
85714. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
85715. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
85716. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
85717. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
85718. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
85719. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
85720. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
85721. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
85722. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
85723. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
85724. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
85725. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
85726. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
85727. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
85728. BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
85729. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
85730. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
85731. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
85732. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
85733. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
85734. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
85735. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
85736. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
85737. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
85738. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
85739. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
85740. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
85741. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
85742. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
85743. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
85744. BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
85745. BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE__PROG_INTERFACE_MASK
85746. BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE__PROG_INTERFACE__SHIFT
85747. BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MAJOR_REV_ID_MASK
85748. BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MAJOR_REV_ID__SHIFT
85749. BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MINOR_REV_ID_MASK
85750. BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MINOR_REV_ID__SHIFT
85751. BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__BASE_ADDR_MASK
85752. BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__BASE_ADDR__SHIFT
85753. BIF_CFG_DEV0_EPF0_VF13_STATUS__CAP_LIST_MASK
85754. BIF_CFG_DEV0_EPF0_VF13_STATUS__CAP_LIST__SHIFT
85755. BIF_CFG_DEV0_EPF0_VF13_STATUS__DEVSEL_TIMING_MASK
85756. BIF_CFG_DEV0_EPF0_VF13_STATUS__DEVSEL_TIMING__SHIFT
85757. BIF_CFG_DEV0_EPF0_VF13_STATUS__FAST_BACK_CAPABLE_MASK
85758. BIF_CFG_DEV0_EPF0_VF13_STATUS__FAST_BACK_CAPABLE__SHIFT
85759. BIF_CFG_DEV0_EPF0_VF13_STATUS__IMMEDIATE_READINESS_MASK
85760. BIF_CFG_DEV0_EPF0_VF13_STATUS__IMMEDIATE_READINESS__SHIFT
85761. BIF_CFG_DEV0_EPF0_VF13_STATUS__INT_STATUS_MASK
85762. BIF_CFG_DEV0_EPF0_VF13_STATUS__INT_STATUS__SHIFT
85763. BIF_CFG_DEV0_EPF0_VF13_STATUS__MASTER_DATA_PARITY_ERROR_MASK
85764. BIF_CFG_DEV0_EPF0_VF13_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
85765. BIF_CFG_DEV0_EPF0_VF13_STATUS__PARITY_ERROR_DETECTED_MASK
85766. BIF_CFG_DEV0_EPF0_VF13_STATUS__PARITY_ERROR_DETECTED__SHIFT
85767. BIF_CFG_DEV0_EPF0_VF13_STATUS__PCI_66_CAP_MASK
85768. BIF_CFG_DEV0_EPF0_VF13_STATUS__PCI_66_CAP__SHIFT
85769. BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_MASTER_ABORT_MASK
85770. BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_MASTER_ABORT__SHIFT
85771. BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_TARGET_ABORT_MASK
85772. BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_TARGET_ABORT__SHIFT
85773. BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNALED_SYSTEM_ERROR_MASK
85774. BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
85775. BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNAL_TARGET_ABORT_MASK
85776. BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNAL_TARGET_ABORT__SHIFT
85777. BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS__SUB_CLASS_MASK
85778. BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS__SUB_CLASS__SHIFT
85779. BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID__VENDOR_ID_MASK
85780. BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID__VENDOR_ID__SHIFT
85781. BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
85782. BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
85783. BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
85784. BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
85785. BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR_MASK
85786. BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR__SHIFT
85787. BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR_MASK
85788. BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR__SHIFT
85789. BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR_MASK
85790. BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR__SHIFT
85791. BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR_MASK
85792. BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR__SHIFT
85793. BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR_MASK
85794. BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR__SHIFT
85795. BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR_MASK
85796. BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR__SHIFT
85797. BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS_MASK
85798. BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS__SHIFT
85799. BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP_MASK
85800. BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP__SHIFT
85801. BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP_MASK
85802. BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP__SHIFT
85803. BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT_MASK
85804. BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT__SHIFT
85805. BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
85806. BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
85807. BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR_MASK
85808. BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR__SHIFT
85809. BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
85810. BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
85811. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING_MASK
85812. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING__SHIFT
85813. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN_MASK
85814. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN__SHIFT
85815. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN_MASK
85816. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN__SHIFT
85817. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS_MASK
85818. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS__SHIFT
85819. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN_MASK
85820. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN__SHIFT
85821. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN_MASK
85822. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN__SHIFT
85823. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
85824. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
85825. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN_MASK
85826. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN__SHIFT
85827. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
85828. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
85829. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN_MASK
85830. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN__SHIFT
85831. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN_MASK
85832. BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
85833. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
85834. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
85835. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
85836. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
85837. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
85838. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
85839. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
85840. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
85841. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
85842. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
85843. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
85844. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
85845. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
85846. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
85847. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
85848. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
85849. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
85850. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
85851. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
85852. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
85853. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
85854. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
85855. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
85856. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
85857. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
85858. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
85859. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
85860. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
85861. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
85862. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
85863. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
85864. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
85865. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
85866. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
85867. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
85868. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
85869. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
85870. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
85871. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
85872. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
85873. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
85874. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
85875. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
85876. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
85877. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG_MASK
85878. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
85879. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE_MASK
85880. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
85881. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
85882. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
85883. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
85884. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
85885. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
85886. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
85887. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC_MASK
85888. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
85889. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
85890. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
85891. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
85892. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
85893. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
85894. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
85895. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
85896. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
85897. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
85898. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
85899. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
85900. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
85901. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
85902. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
85903. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
85904. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
85905. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
85906. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
85907. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
85908. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
85909. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN_MASK
85910. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN__SHIFT
85911. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN_MASK
85912. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN__SHIFT
85913. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
85914. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
85915. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
85916. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
85917. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN_MASK
85918. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
85919. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
85920. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
85921. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
85922. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
85923. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR_MASK
85924. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
85925. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
85926. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
85927. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
85928. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
85929. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
85930. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
85931. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
85932. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
85933. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
85934. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
85935. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
85936. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
85937. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN_MASK
85938. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
85939. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID_MASK
85940. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID__SHIFT
85941. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED_MASK
85942. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED__SHIFT
85943. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR_MASK
85944. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR__SHIFT
85945. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR_MASK
85946. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR__SHIFT
85947. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
85948. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
85949. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR_MASK
85950. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR__SHIFT
85951. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
85952. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
85953. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
85954. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
85955. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED_MASK
85956. BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED__SHIFT
85957. BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE_MASK
85958. BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE__SHIFT
85959. BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE_MASK
85960. BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE__SHIFT
85961. BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
85962. BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
85963. BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
85964. BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
85965. BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER_MASK
85966. BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER__SHIFT
85967. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
85968. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
85969. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
85970. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
85971. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
85972. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
85973. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
85974. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
85975. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RESERVED_MASK
85976. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RESERVED__SHIFT
85977. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
85978. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
85979. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
85980. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
85981. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
85982. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
85983. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
85984. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
85985. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
85986. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
85987. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
85988. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
85989. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
85990. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
85991. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY_MASK
85992. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
85993. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
85994. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
85995. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED_MASK
85996. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED__SHIFT
85997. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH_MASK
85998. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH__SHIFT
85999. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT_MASK
86000. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT__SHIFT
86001. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER_MASK
86002. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER__SHIFT
86003. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
86004. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
86005. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
86006. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
86007. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
86008. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
86009. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
86010. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
86011. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
86012. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
86013. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
86014. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
86015. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
86016. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
86017. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
86018. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
86019. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN_MASK
86020. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
86021. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
86022. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
86023. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
86024. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
86025. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
86026. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
86027. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC_MASK
86028. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
86029. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
86030. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
86031. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
86032. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
86033. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
86034. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
86035. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS_MASK
86036. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS__SHIFT
86037. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL_MASK
86038. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL__SHIFT
86039. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
86040. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
86041. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK_MASK
86042. BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK__SHIFT
86043. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
86044. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
86045. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
86046. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
86047. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
86048. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
86049. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
86050. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
86051. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
86052. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
86053. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
86054. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
86055. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
86056. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
86057. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
86058. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
86059. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
86060. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
86061. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
86062. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
86063. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
86064. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
86065. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
86066. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
86067. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
86068. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
86069. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
86070. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
86071. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
86072. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
86073. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
86074. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
86075. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
86076. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
86077. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE_MASK
86078. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE__SHIFT
86079. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
86080. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
86081. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
86082. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
86083. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING_MASK
86084. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING__SHIFT
86085. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
86086. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
86087. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
86088. BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
86089. BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY__MAX_LAT_MASK
86090. BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY__MAX_LAT__SHIFT
86091. BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT__MIN_GNT_MASK
86092. BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT__MIN_GNT__SHIFT
86093. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID_MASK
86094. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID__SHIFT
86095. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR_MASK
86096. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
86097. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN_MASK
86098. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
86099. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
86100. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
86101. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
86102. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
86103. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR_MASK
86104. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
86105. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
86106. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
86107. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
86108. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
86109. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
86110. BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
86111. BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID_MASK
86112. BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID__SHIFT
86113. BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR_MASK
86114. BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
86115. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64_MASK
86116. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64__SHIFT
86117. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK_MASK
86118. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK__SHIFT
86119. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
86120. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
86121. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
86122. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
86123. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT_MASK
86124. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
86125. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN_MASK
86126. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN__SHIFT
86127. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
86128. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
86129. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
86130. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
86131. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
86132. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
86133. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
86134. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
86135. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA_MASK
86136. BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA__SHIFT
86137. BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64_MASK
86138. BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
86139. BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING_MASK
86140. BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING__SHIFT
86141. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
86142. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
86143. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
86144. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
86145. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
86146. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
86147. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
86148. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
86149. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
86150. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
86151. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
86152. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
86153. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
86154. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
86155. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
86156. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
86157. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
86158. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
86159. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
86160. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
86161. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
86162. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
86163. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
86164. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
86165. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
86166. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
86167. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
86168. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
86169. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
86170. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
86171. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
86172. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
86173. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
86174. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
86175. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
86176. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
86177. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
86178. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
86179. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
86180. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
86181. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
86182. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
86183. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
86184. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
86185. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
86186. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
86187. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
86188. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
86189. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
86190. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
86191. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__STU_MASK
86192. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__STU__SHIFT
86193. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
86194. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
86195. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
86196. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
86197. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
86198. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
86199. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID_MASK
86200. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID__SHIFT
86201. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR_MASK
86202. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
86203. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE_MASK
86204. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE__SHIFT
86205. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
86206. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
86207. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
86208. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
86209. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION_MASK
86210. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION__SHIFT
86211. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
86212. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
86213. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
86214. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
86215. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
86216. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
86217. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
86218. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
86219. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
86220. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
86221. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
86222. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
86223. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
86224. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
86225. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
86226. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
86227. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
86228. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
86229. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
86230. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
86231. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
86232. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
86233. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
86234. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
86235. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
86236. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
86237. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
86238. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
86239. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
86240. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
86241. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
86242. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
86243. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR_MASK
86244. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
86245. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR_MASK
86246. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
86247. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR_MASK
86248. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
86249. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR_MASK
86250. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
86251. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
86252. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
86253. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
86254. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
86255. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
86256. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
86257. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
86258. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
86259. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
86260. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
86261. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
86262. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
86263. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
86264. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
86265. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
86266. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
86267. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
86268. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
86269. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
86270. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
86271. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
86272. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
86273. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
86274. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
86275. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
86276. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
86277. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
86278. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
86279. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
86280. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
86281. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
86282. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
86283. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
86284. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
86285. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
86286. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
86287. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
86288. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
86289. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
86290. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
86291. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
86292. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
86293. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
86294. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
86295. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
86296. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
86297. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
86298. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
86299. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
86300. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
86301. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
86302. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
86303. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
86304. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
86305. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
86306. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
86307. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
86308. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
86309. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
86310. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
86311. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
86312. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
86313. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
86314. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
86315. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
86316. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
86317. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
86318. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
86319. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
86320. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
86321. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
86322. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
86323. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
86324. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
86325. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
86326. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
86327. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
86328. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
86329. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
86330. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
86331. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
86332. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
86333. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
86334. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
86335. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
86336. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
86337. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
86338. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
86339. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
86340. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
86341. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
86342. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
86343. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
86344. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
86345. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
86346. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
86347. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
86348. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
86349. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
86350. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
86351. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
86352. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
86353. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
86354. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
86355. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
86356. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
86357. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
86358. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
86359. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
86360. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
86361. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
86362. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
86363. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
86364. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
86365. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
86366. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
86367. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
86368. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
86369. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
86370. BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
86371. BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE_MASK
86372. BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
86373. BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID_MASK
86374. BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID__SHIFT
86375. BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID_MASK
86376. BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID__SHIFT
86377. BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR_MASK
86378. BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
86379. BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2__RESERVED_MASK
86380. BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2__RESERVED__SHIFT
86381. BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2__RESERVED_MASK
86382. BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2__RESERVED__SHIFT
86383. BIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2__RESERVED_MASK
86384. BIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2__RESERVED__SHIFT
86385. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST_MASK
86386. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST__SHIFT
86387. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING_MASK
86388. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING__SHIFT
86389. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE_MASK
86390. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE__SHIFT
86391. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__IMMEDIATE_READINESS_MASK
86392. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__IMMEDIATE_READINESS__SHIFT
86393. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS_MASK
86394. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS__SHIFT
86395. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
86396. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
86397. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED_MASK
86398. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
86399. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_CAP_MASK
86400. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_CAP__SHIFT
86401. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_EN_MASK
86402. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_EN__SHIFT
86403. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT_MASK
86404. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
86405. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT_MASK
86406. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
86407. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
86408. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
86409. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT_MASK
86410. BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
86411. BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS_MASK
86412. BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS__SHIFT
86413. BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID_MASK
86414. BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID__SHIFT
86415. BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
86416. BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
86417. BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
86418. BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
86419. BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR_MASK
86420. BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR__SHIFT
86421. BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR_MASK
86422. BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR__SHIFT
86423. BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR_MASK
86424. BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR__SHIFT
86425. BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR_MASK
86426. BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR__SHIFT
86427. BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR_MASK
86428. BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR__SHIFT
86429. BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR_MASK
86430. BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR__SHIFT
86431. BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS_MASK
86432. BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS__SHIFT
86433. BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP_MASK
86434. BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP__SHIFT
86435. BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP_MASK
86436. BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP__SHIFT
86437. BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT_MASK
86438. BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT__SHIFT
86439. BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
86440. BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
86441. BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR_MASK
86442. BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR__SHIFT
86443. BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
86444. BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
86445. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING_MASK
86446. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING__SHIFT
86447. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN_MASK
86448. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN__SHIFT
86449. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN_MASK
86450. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN__SHIFT
86451. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS_MASK
86452. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS__SHIFT
86453. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN_MASK
86454. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN__SHIFT
86455. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN_MASK
86456. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN__SHIFT
86457. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
86458. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
86459. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN_MASK
86460. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN__SHIFT
86461. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
86462. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
86463. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN_MASK
86464. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN__SHIFT
86465. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN_MASK
86466. BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
86467. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
86468. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
86469. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
86470. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
86471. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
86472. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
86473. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
86474. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
86475. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
86476. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
86477. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
86478. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
86479. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
86480. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
86481. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
86482. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
86483. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
86484. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
86485. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
86486. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
86487. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
86488. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
86489. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
86490. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
86491. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
86492. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
86493. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
86494. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
86495. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
86496. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
86497. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
86498. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
86499. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
86500. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
86501. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
86502. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
86503. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
86504. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
86505. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
86506. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
86507. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
86508. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
86509. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
86510. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
86511. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG_MASK
86512. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
86513. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE_MASK
86514. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
86515. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
86516. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
86517. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
86518. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
86519. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
86520. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
86521. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC_MASK
86522. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
86523. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
86524. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
86525. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
86526. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
86527. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
86528. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
86529. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
86530. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
86531. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
86532. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
86533. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
86534. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
86535. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
86536. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
86537. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
86538. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
86539. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
86540. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
86541. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
86542. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
86543. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN_MASK
86544. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN__SHIFT
86545. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN_MASK
86546. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN__SHIFT
86547. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
86548. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
86549. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
86550. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
86551. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN_MASK
86552. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
86553. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
86554. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
86555. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
86556. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
86557. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR_MASK
86558. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
86559. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
86560. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
86561. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
86562. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
86563. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
86564. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
86565. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
86566. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
86567. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
86568. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
86569. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
86570. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
86571. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN_MASK
86572. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
86573. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID_MASK
86574. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID__SHIFT
86575. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED_MASK
86576. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED__SHIFT
86577. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR_MASK
86578. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR__SHIFT
86579. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR_MASK
86580. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR__SHIFT
86581. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
86582. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
86583. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR_MASK
86584. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR__SHIFT
86585. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
86586. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
86587. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
86588. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
86589. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED_MASK
86590. BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED__SHIFT
86591. BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE_MASK
86592. BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE__SHIFT
86593. BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE_MASK
86594. BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE__SHIFT
86595. BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
86596. BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
86597. BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
86598. BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
86599. BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER_MASK
86600. BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER__SHIFT
86601. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
86602. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
86603. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
86604. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
86605. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
86606. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
86607. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
86608. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
86609. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RESERVED_MASK
86610. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RESERVED__SHIFT
86611. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
86612. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
86613. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
86614. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
86615. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
86616. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
86617. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
86618. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
86619. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
86620. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
86621. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
86622. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
86623. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
86624. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
86625. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY_MASK
86626. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
86627. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
86628. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
86629. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED_MASK
86630. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED__SHIFT
86631. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH_MASK
86632. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH__SHIFT
86633. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT_MASK
86634. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT__SHIFT
86635. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER_MASK
86636. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER__SHIFT
86637. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
86638. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
86639. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
86640. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
86641. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
86642. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
86643. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
86644. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
86645. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
86646. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
86647. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
86648. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
86649. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
86650. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
86651. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
86652. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
86653. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN_MASK
86654. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
86655. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
86656. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
86657. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
86658. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
86659. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
86660. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
86661. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC_MASK
86662. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
86663. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
86664. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
86665. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
86666. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
86667. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
86668. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
86669. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS_MASK
86670. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS__SHIFT
86671. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL_MASK
86672. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL__SHIFT
86673. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
86674. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
86675. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK_MASK
86676. BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK__SHIFT
86677. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
86678. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
86679. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
86680. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
86681. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
86682. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
86683. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
86684. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
86685. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
86686. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
86687. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
86688. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
86689. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
86690. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
86691. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
86692. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
86693. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
86694. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
86695. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
86696. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
86697. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
86698. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
86699. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
86700. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
86701. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
86702. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
86703. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
86704. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
86705. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
86706. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
86707. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
86708. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
86709. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
86710. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
86711. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE_MASK
86712. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE__SHIFT
86713. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
86714. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
86715. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
86716. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
86717. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING_MASK
86718. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING__SHIFT
86719. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
86720. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
86721. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
86722. BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
86723. BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY__MAX_LAT_MASK
86724. BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY__MAX_LAT__SHIFT
86725. BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT__MIN_GNT_MASK
86726. BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT__MIN_GNT__SHIFT
86727. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID_MASK
86728. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID__SHIFT
86729. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR_MASK
86730. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
86731. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN_MASK
86732. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
86733. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
86734. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
86735. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
86736. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
86737. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR_MASK
86738. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
86739. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
86740. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
86741. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
86742. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
86743. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
86744. BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
86745. BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID_MASK
86746. BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID__SHIFT
86747. BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR_MASK
86748. BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
86749. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64_MASK
86750. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64__SHIFT
86751. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK_MASK
86752. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK__SHIFT
86753. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
86754. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
86755. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
86756. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
86757. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT_MASK
86758. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
86759. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN_MASK
86760. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN__SHIFT
86761. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
86762. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
86763. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
86764. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
86765. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
86766. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
86767. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
86768. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
86769. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA_MASK
86770. BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA__SHIFT
86771. BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64_MASK
86772. BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
86773. BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING_MASK
86774. BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING__SHIFT
86775. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
86776. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
86777. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
86778. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
86779. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
86780. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
86781. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
86782. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
86783. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
86784. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
86785. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
86786. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
86787. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
86788. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
86789. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
86790. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
86791. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
86792. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
86793. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
86794. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
86795. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
86796. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
86797. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
86798. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
86799. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
86800. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
86801. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
86802. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
86803. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
86804. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
86805. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
86806. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
86807. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
86808. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
86809. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
86810. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
86811. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
86812. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
86813. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
86814. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
86815. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
86816. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
86817. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
86818. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
86819. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
86820. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
86821. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
86822. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
86823. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
86824. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
86825. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__STU_MASK
86826. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__STU__SHIFT
86827. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
86828. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
86829. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
86830. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
86831. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
86832. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
86833. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID_MASK
86834. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID__SHIFT
86835. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR_MASK
86836. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
86837. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE_MASK
86838. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE__SHIFT
86839. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
86840. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
86841. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
86842. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
86843. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION_MASK
86844. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION__SHIFT
86845. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
86846. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
86847. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
86848. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
86849. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
86850. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
86851. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
86852. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
86853. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
86854. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
86855. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
86856. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
86857. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
86858. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
86859. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
86860. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
86861. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
86862. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
86863. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
86864. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
86865. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
86866. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
86867. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
86868. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
86869. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
86870. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
86871. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
86872. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
86873. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
86874. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
86875. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
86876. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
86877. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR_MASK
86878. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
86879. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR_MASK
86880. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
86881. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR_MASK
86882. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
86883. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR_MASK
86884. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
86885. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
86886. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
86887. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
86888. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
86889. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
86890. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
86891. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
86892. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
86893. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
86894. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
86895. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
86896. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
86897. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
86898. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
86899. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
86900. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
86901. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
86902. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
86903. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
86904. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
86905. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
86906. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
86907. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
86908. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
86909. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
86910. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
86911. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
86912. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
86913. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
86914. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
86915. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
86916. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
86917. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
86918. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
86919. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
86920. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
86921. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
86922. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
86923. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
86924. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
86925. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
86926. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
86927. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
86928. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
86929. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
86930. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
86931. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
86932. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
86933. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
86934. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
86935. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
86936. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
86937. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
86938. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
86939. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
86940. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
86941. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
86942. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
86943. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
86944. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
86945. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
86946. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
86947. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
86948. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
86949. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
86950. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
86951. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
86952. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
86953. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
86954. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
86955. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
86956. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
86957. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
86958. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
86959. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
86960. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
86961. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
86962. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
86963. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
86964. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
86965. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
86966. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
86967. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
86968. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
86969. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
86970. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
86971. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
86972. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
86973. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
86974. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
86975. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
86976. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
86977. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
86978. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
86979. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
86980. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
86981. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
86982. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
86983. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
86984. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
86985. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
86986. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
86987. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
86988. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
86989. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
86990. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
86991. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
86992. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
86993. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
86994. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
86995. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
86996. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
86997. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
86998. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
86999. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
87000. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
87001. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
87002. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
87003. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
87004. BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
87005. BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE_MASK
87006. BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
87007. BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID_MASK
87008. BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID__SHIFT
87009. BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID_MASK
87010. BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID__SHIFT
87011. BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR_MASK
87012. BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
87013. BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CAP2__RESERVED_MASK
87014. BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CAP2__RESERVED__SHIFT
87015. BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CNTL2__RESERVED_MASK
87016. BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CNTL2__RESERVED__SHIFT
87017. BIF_CFG_DEV0_EPF0_VF14_1_SLOT_STATUS2__RESERVED_MASK
87018. BIF_CFG_DEV0_EPF0_VF14_1_SLOT_STATUS2__RESERVED__SHIFT
87019. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST_MASK
87020. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST__SHIFT
87021. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING_MASK
87022. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING__SHIFT
87023. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE_MASK
87024. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE__SHIFT
87025. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__IMMEDIATE_READINESS_MASK
87026. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__IMMEDIATE_READINESS__SHIFT
87027. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS_MASK
87028. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS__SHIFT
87029. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
87030. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
87031. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED_MASK
87032. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
87033. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_CAP_MASK
87034. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_CAP__SHIFT
87035. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_EN_MASK
87036. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_EN__SHIFT
87037. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT_MASK
87038. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
87039. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT_MASK
87040. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
87041. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
87042. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
87043. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT_MASK
87044. BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
87045. BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS_MASK
87046. BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS__SHIFT
87047. BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID_MASK
87048. BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID__SHIFT
87049. BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_ID_MASK
87050. BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
87051. BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
87052. BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
87053. BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1__BASE_ADDR_MASK
87054. BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1__BASE_ADDR__SHIFT
87055. BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2__BASE_ADDR_MASK
87056. BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2__BASE_ADDR__SHIFT
87057. BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3__BASE_ADDR_MASK
87058. BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3__BASE_ADDR__SHIFT
87059. BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4__BASE_ADDR_MASK
87060. BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4__BASE_ADDR__SHIFT
87061. BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5__BASE_ADDR_MASK
87062. BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5__BASE_ADDR__SHIFT
87063. BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6__BASE_ADDR_MASK
87064. BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6__BASE_ADDR__SHIFT
87065. BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS__BASE_CLASS_MASK
87066. BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS__BASE_CLASS__SHIFT
87067. BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_CAP_MASK
87068. BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_CAP__SHIFT
87069. BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_COMP_MASK
87070. BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_COMP__SHIFT
87071. BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_STRT_MASK
87072. BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_STRT__SHIFT
87073. BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE__CACHE_LINE_SIZE_MASK
87074. BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
87075. BIF_CFG_DEV0_EPF0_VF14_CAP_PTR__CAP_PTR_MASK
87076. BIF_CFG_DEV0_EPF0_VF14_CAP_PTR__CAP_PTR__SHIFT
87077. BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
87078. BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
87079. BIF_CFG_DEV0_EPF0_VF14_COMMAND__AD_STEPPING_MASK
87080. BIF_CFG_DEV0_EPF0_VF14_COMMAND__AD_STEPPING__SHIFT
87081. BIF_CFG_DEV0_EPF0_VF14_COMMAND__BUS_MASTER_EN_MASK
87082. BIF_CFG_DEV0_EPF0_VF14_COMMAND__BUS_MASTER_EN__SHIFT
87083. BIF_CFG_DEV0_EPF0_VF14_COMMAND__FAST_B2B_EN_MASK
87084. BIF_CFG_DEV0_EPF0_VF14_COMMAND__FAST_B2B_EN__SHIFT
87085. BIF_CFG_DEV0_EPF0_VF14_COMMAND__INT_DIS_MASK
87086. BIF_CFG_DEV0_EPF0_VF14_COMMAND__INT_DIS__SHIFT
87087. BIF_CFG_DEV0_EPF0_VF14_COMMAND__IO_ACCESS_EN_MASK
87088. BIF_CFG_DEV0_EPF0_VF14_COMMAND__IO_ACCESS_EN__SHIFT
87089. BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_ACCESS_EN_MASK
87090. BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_ACCESS_EN__SHIFT
87091. BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
87092. BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
87093. BIF_CFG_DEV0_EPF0_VF14_COMMAND__PAL_SNOOP_EN_MASK
87094. BIF_CFG_DEV0_EPF0_VF14_COMMAND__PAL_SNOOP_EN__SHIFT
87095. BIF_CFG_DEV0_EPF0_VF14_COMMAND__PARITY_ERROR_RESPONSE_MASK
87096. BIF_CFG_DEV0_EPF0_VF14_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
87097. BIF_CFG_DEV0_EPF0_VF14_COMMAND__SERR_EN_MASK
87098. BIF_CFG_DEV0_EPF0_VF14_COMMAND__SERR_EN__SHIFT
87099. BIF_CFG_DEV0_EPF0_VF14_COMMAND__SPECIAL_CYCLE_EN_MASK
87100. BIF_CFG_DEV0_EPF0_VF14_COMMAND__SPECIAL_CYCLE_EN__SHIFT
87101. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
87102. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
87103. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
87104. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
87105. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
87106. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
87107. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
87108. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
87109. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
87110. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
87111. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
87112. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
87113. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
87114. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
87115. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
87116. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
87117. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
87118. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
87119. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
87120. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
87121. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
87122. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
87123. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__FRS_SUPPORTED_MASK
87124. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
87125. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
87126. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
87127. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LTR_SUPPORTED_MASK
87128. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
87129. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
87130. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
87131. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
87132. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
87133. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__OBFF_SUPPORTED_MASK
87134. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
87135. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
87136. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
87137. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
87138. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
87139. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
87140. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
87141. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
87142. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
87143. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
87144. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
87145. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__EXTENDED_TAG_MASK
87146. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__EXTENDED_TAG__SHIFT
87147. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__FLR_CAPABLE_MASK
87148. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__FLR_CAPABLE__SHIFT
87149. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
87150. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
87151. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
87152. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
87153. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
87154. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
87155. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__PHANTOM_FUNC_MASK
87156. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__PHANTOM_FUNC__SHIFT
87157. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
87158. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
87159. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
87160. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
87161. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
87162. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
87163. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
87164. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
87165. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
87166. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
87167. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
87168. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
87169. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
87170. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
87171. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
87172. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
87173. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
87174. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
87175. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
87176. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
87177. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__LTR_EN_MASK
87178. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__LTR_EN__SHIFT
87179. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__OBFF_EN_MASK
87180. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__OBFF_EN__SHIFT
87181. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
87182. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
87183. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
87184. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
87185. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__CORR_ERR_EN_MASK
87186. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__CORR_ERR_EN__SHIFT
87187. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
87188. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
87189. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__FATAL_ERR_EN_MASK
87190. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
87191. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__INITIATE_FLR_MASK
87192. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__INITIATE_FLR__SHIFT
87193. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
87194. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
87195. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
87196. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
87197. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
87198. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
87199. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NO_SNOOP_EN_MASK
87200. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
87201. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
87202. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
87203. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__RELAXED_ORD_EN_MASK
87204. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
87205. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__USR_REPORT_EN_MASK
87206. BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__USR_REPORT_EN__SHIFT
87207. BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID__DEVICE_ID_MASK
87208. BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID__DEVICE_ID__SHIFT
87209. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2__RESERVED_MASK
87210. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2__RESERVED__SHIFT
87211. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__AUX_PWR_MASK
87212. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__AUX_PWR__SHIFT
87213. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__CORR_ERR_MASK
87214. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__CORR_ERR__SHIFT
87215. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
87216. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
87217. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__FATAL_ERR_MASK
87218. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__FATAL_ERR__SHIFT
87219. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__NON_FATAL_ERR_MASK
87220. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
87221. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
87222. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
87223. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__USR_DETECTED_MASK
87224. BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__USR_DETECTED__SHIFT
87225. BIF_CFG_DEV0_EPF0_VF14_HEADER__DEVICE_TYPE_MASK
87226. BIF_CFG_DEV0_EPF0_VF14_HEADER__DEVICE_TYPE__SHIFT
87227. BIF_CFG_DEV0_EPF0_VF14_HEADER__HEADER_TYPE_MASK
87228. BIF_CFG_DEV0_EPF0_VF14_HEADER__HEADER_TYPE__SHIFT
87229. BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE__INTERRUPT_LINE_MASK
87230. BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
87231. BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN__INTERRUPT_PIN_MASK
87232. BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
87233. BIF_CFG_DEV0_EPF0_VF14_LATENCY__LATENCY_TIMER_MASK
87234. BIF_CFG_DEV0_EPF0_VF14_LATENCY__LATENCY_TIMER__SHIFT
87235. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
87236. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
87237. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
87238. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
87239. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
87240. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
87241. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
87242. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
87243. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
87244. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
87245. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
87246. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
87247. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
87248. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
87249. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
87250. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
87251. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
87252. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
87253. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
87254. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
87255. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L0S_EXIT_LATENCY_MASK
87256. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
87257. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L1_EXIT_LATENCY_MASK
87258. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L1_EXIT_LATENCY__SHIFT
87259. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
87260. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
87261. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_SPEED_MASK
87262. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_SPEED__SHIFT
87263. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_WIDTH_MASK
87264. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_WIDTH__SHIFT
87265. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PM_SUPPORT_MASK
87266. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PM_SUPPORT__SHIFT
87267. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PORT_NUMBER_MASK
87268. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PORT_NUMBER__SHIFT
87269. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
87270. BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
87271. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
87272. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
87273. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_SOS_MASK
87274. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
87275. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_COMPLIANCE_MASK
87276. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
87277. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
87278. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
87279. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
87280. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
87281. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
87282. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
87283. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__TARGET_LINK_SPEED_MASK
87284. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
87285. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__XMIT_MARGIN_MASK
87286. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__XMIT_MARGIN__SHIFT
87287. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
87288. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
87289. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__COMMON_CLOCK_CFG_MASK
87290. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
87291. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
87292. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
87293. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__EXTENDED_SYNC_MASK
87294. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__EXTENDED_SYNC__SHIFT
87295. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
87296. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
87297. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
87298. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
87299. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
87300. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
87301. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_DIS_MASK
87302. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_DIS__SHIFT
87303. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PM_CONTROL_MASK
87304. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PM_CONTROL__SHIFT
87305. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__READ_CPL_BOUNDARY_MASK
87306. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
87307. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__RETRAIN_LINK_MASK
87308. BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__RETRAIN_LINK__SHIFT
87309. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
87310. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
87311. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
87312. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
87313. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
87314. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
87315. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
87316. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
87317. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
87318. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
87319. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
87320. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
87321. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
87322. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
87323. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
87324. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
87325. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
87326. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
87327. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
87328. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
87329. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
87330. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
87331. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__CURRENT_LINK_SPEED_MASK
87332. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
87333. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__DL_ACTIVE_MASK
87334. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__DL_ACTIVE__SHIFT
87335. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
87336. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
87337. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
87338. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
87339. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_TRAINING_MASK
87340. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_TRAINING__SHIFT
87341. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
87342. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
87343. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__SLOT_CLOCK_CFG_MASK
87344. BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
87345. BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY__MAX_LAT_MASK
87346. BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY__MAX_LAT__SHIFT
87347. BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT__MIN_GNT_MASK
87348. BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT__MIN_GNT__SHIFT
87349. BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__CAP_ID_MASK
87350. BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__CAP_ID__SHIFT
87351. BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__NEXT_PTR_MASK
87352. BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__NEXT_PTR__SHIFT
87353. BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_EN_MASK
87354. BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_EN__SHIFT
87355. BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
87356. BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
87357. BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
87358. BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
87359. BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_BIR_MASK
87360. BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_BIR__SHIFT
87361. BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_OFFSET_MASK
87362. BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
87363. BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_BIR_MASK
87364. BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
87365. BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
87366. BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
87367. BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__CAP_ID_MASK
87368. BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__CAP_ID__SHIFT
87369. BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__NEXT_PTR_MASK
87370. BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__NEXT_PTR__SHIFT
87371. BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64__MSI_MASK_64_MASK
87372. BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64__MSI_MASK_64__SHIFT
87373. BIF_CFG_DEV0_EPF0_VF14_MSI_MASK__MSI_MASK_MASK
87374. BIF_CFG_DEV0_EPF0_VF14_MSI_MASK__MSI_MASK__SHIFT
87375. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
87376. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
87377. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
87378. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
87379. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_64BIT_MASK
87380. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_64BIT__SHIFT
87381. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EN_MASK
87382. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EN__SHIFT
87383. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
87384. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
87385. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
87386. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
87387. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
87388. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
87389. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64__MSI_DATA_64_MASK
87390. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
87391. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA__MSI_DATA_MASK
87392. BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA__MSI_DATA__SHIFT
87393. BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64__MSI_PENDING_64_MASK
87394. BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64__MSI_PENDING_64__SHIFT
87395. BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING__MSI_PENDING_MASK
87396. BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING__MSI_PENDING__SHIFT
87397. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
87398. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
87399. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
87400. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
87401. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
87402. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
87403. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
87404. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
87405. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
87406. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
87407. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
87408. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
87409. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
87410. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
87411. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
87412. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
87413. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
87414. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
87415. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
87416. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
87417. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
87418. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
87419. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
87420. BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
87421. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
87422. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
87423. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
87424. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
87425. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
87426. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
87427. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
87428. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
87429. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
87430. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
87431. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
87432. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
87433. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
87434. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
87435. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
87436. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
87437. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
87438. BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
87439. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
87440. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
87441. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
87442. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
87443. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
87444. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
87445. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL__ATC_ENABLE_MASK
87446. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
87447. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL__STU_MASK
87448. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL__STU__SHIFT
87449. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
87450. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
87451. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
87452. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
87453. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
87454. BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
87455. BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__CAP_ID_MASK
87456. BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__CAP_ID__SHIFT
87457. BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__NEXT_PTR_MASK
87458. BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__NEXT_PTR__SHIFT
87459. BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__DEVICE_TYPE_MASK
87460. BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__DEVICE_TYPE__SHIFT
87461. BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__INT_MESSAGE_NUM_MASK
87462. BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
87463. BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__SLOT_IMPLEMENTED_MASK
87464. BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
87465. BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__VERSION_MASK
87466. BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__VERSION__SHIFT
87467. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
87468. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
87469. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
87470. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
87471. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
87472. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
87473. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
87474. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
87475. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
87476. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
87477. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
87478. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
87479. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
87480. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
87481. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
87482. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
87483. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
87484. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
87485. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
87486. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
87487. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
87488. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
87489. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
87490. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
87491. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
87492. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
87493. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
87494. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
87495. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
87496. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
87497. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
87498. BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
87499. BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0__TLP_HDR_MASK
87500. BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0__TLP_HDR__SHIFT
87501. BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1__TLP_HDR_MASK
87502. BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1__TLP_HDR__SHIFT
87503. BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2__TLP_HDR_MASK
87504. BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2__TLP_HDR__SHIFT
87505. BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3__TLP_HDR_MASK
87506. BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3__TLP_HDR__SHIFT
87507. BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
87508. BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
87509. BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
87510. BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
87511. BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
87512. BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
87513. BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
87514. BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
87515. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
87516. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
87517. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
87518. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
87519. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
87520. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
87521. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
87522. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
87523. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
87524. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
87525. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
87526. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
87527. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
87528. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
87529. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
87530. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
87531. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
87532. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
87533. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
87534. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
87535. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
87536. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
87537. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
87538. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
87539. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
87540. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
87541. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
87542. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
87543. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
87544. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
87545. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
87546. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
87547. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
87548. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
87549. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
87550. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
87551. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
87552. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
87553. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
87554. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
87555. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
87556. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
87557. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
87558. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
87559. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
87560. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
87561. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
87562. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
87563. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
87564. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
87565. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
87566. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
87567. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
87568. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
87569. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
87570. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
87571. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
87572. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
87573. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
87574. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
87575. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
87576. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
87577. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
87578. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
87579. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
87580. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
87581. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
87582. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
87583. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
87584. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
87585. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
87586. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
87587. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
87588. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
87589. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
87590. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
87591. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
87592. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
87593. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
87594. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
87595. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
87596. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
87597. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
87598. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
87599. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
87600. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
87601. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
87602. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
87603. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
87604. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
87605. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
87606. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
87607. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
87608. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
87609. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
87610. BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
87611. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
87612. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
87613. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
87614. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
87615. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
87616. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
87617. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
87618. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
87619. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
87620. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
87621. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
87622. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
87623. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
87624. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
87625. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
87626. BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
87627. BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE__PROG_INTERFACE_MASK
87628. BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE__PROG_INTERFACE__SHIFT
87629. BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MAJOR_REV_ID_MASK
87630. BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MAJOR_REV_ID__SHIFT
87631. BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MINOR_REV_ID_MASK
87632. BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MINOR_REV_ID__SHIFT
87633. BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__BASE_ADDR_MASK
87634. BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__BASE_ADDR__SHIFT
87635. BIF_CFG_DEV0_EPF0_VF14_STATUS__CAP_LIST_MASK
87636. BIF_CFG_DEV0_EPF0_VF14_STATUS__CAP_LIST__SHIFT
87637. BIF_CFG_DEV0_EPF0_VF14_STATUS__DEVSEL_TIMING_MASK
87638. BIF_CFG_DEV0_EPF0_VF14_STATUS__DEVSEL_TIMING__SHIFT
87639. BIF_CFG_DEV0_EPF0_VF14_STATUS__FAST_BACK_CAPABLE_MASK
87640. BIF_CFG_DEV0_EPF0_VF14_STATUS__FAST_BACK_CAPABLE__SHIFT
87641. BIF_CFG_DEV0_EPF0_VF14_STATUS__IMMEDIATE_READINESS_MASK
87642. BIF_CFG_DEV0_EPF0_VF14_STATUS__IMMEDIATE_READINESS__SHIFT
87643. BIF_CFG_DEV0_EPF0_VF14_STATUS__INT_STATUS_MASK
87644. BIF_CFG_DEV0_EPF0_VF14_STATUS__INT_STATUS__SHIFT
87645. BIF_CFG_DEV0_EPF0_VF14_STATUS__MASTER_DATA_PARITY_ERROR_MASK
87646. BIF_CFG_DEV0_EPF0_VF14_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
87647. BIF_CFG_DEV0_EPF0_VF14_STATUS__PARITY_ERROR_DETECTED_MASK
87648. BIF_CFG_DEV0_EPF0_VF14_STATUS__PARITY_ERROR_DETECTED__SHIFT
87649. BIF_CFG_DEV0_EPF0_VF14_STATUS__PCI_66_CAP_MASK
87650. BIF_CFG_DEV0_EPF0_VF14_STATUS__PCI_66_CAP__SHIFT
87651. BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_MASTER_ABORT_MASK
87652. BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_MASTER_ABORT__SHIFT
87653. BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_TARGET_ABORT_MASK
87654. BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_TARGET_ABORT__SHIFT
87655. BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNALED_SYSTEM_ERROR_MASK
87656. BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
87657. BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNAL_TARGET_ABORT_MASK
87658. BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNAL_TARGET_ABORT__SHIFT
87659. BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS__SUB_CLASS_MASK
87660. BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS__SUB_CLASS__SHIFT
87661. BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID__VENDOR_ID_MASK
87662. BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID__VENDOR_ID__SHIFT
87663. BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
87664. BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
87665. BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
87666. BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
87667. BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR_MASK
87668. BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR__SHIFT
87669. BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR_MASK
87670. BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR__SHIFT
87671. BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR_MASK
87672. BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR__SHIFT
87673. BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR_MASK
87674. BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR__SHIFT
87675. BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR_MASK
87676. BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR__SHIFT
87677. BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR_MASK
87678. BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR__SHIFT
87679. BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS_MASK
87680. BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS__SHIFT
87681. BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP_MASK
87682. BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP__SHIFT
87683. BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP_MASK
87684. BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP__SHIFT
87685. BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT_MASK
87686. BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT__SHIFT
87687. BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
87688. BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
87689. BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR_MASK
87690. BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR__SHIFT
87691. BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
87692. BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
87693. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING_MASK
87694. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING__SHIFT
87695. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN_MASK
87696. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN__SHIFT
87697. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN_MASK
87698. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN__SHIFT
87699. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS_MASK
87700. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS__SHIFT
87701. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN_MASK
87702. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN__SHIFT
87703. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN_MASK
87704. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN__SHIFT
87705. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
87706. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
87707. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN_MASK
87708. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN__SHIFT
87709. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
87710. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
87711. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN_MASK
87712. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN__SHIFT
87713. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN_MASK
87714. BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
87715. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
87716. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
87717. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
87718. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
87719. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
87720. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
87721. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
87722. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
87723. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
87724. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
87725. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
87726. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
87727. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
87728. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
87729. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
87730. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
87731. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
87732. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
87733. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
87734. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
87735. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
87736. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
87737. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
87738. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
87739. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
87740. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
87741. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
87742. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
87743. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
87744. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
87745. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
87746. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
87747. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
87748. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
87749. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
87750. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
87751. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
87752. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
87753. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
87754. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
87755. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
87756. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
87757. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
87758. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
87759. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG_MASK
87760. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
87761. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE_MASK
87762. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
87763. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
87764. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
87765. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
87766. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
87767. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
87768. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
87769. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC_MASK
87770. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
87771. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
87772. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
87773. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
87774. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
87775. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
87776. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
87777. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
87778. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
87779. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
87780. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
87781. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
87782. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
87783. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
87784. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
87785. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
87786. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
87787. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
87788. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
87789. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
87790. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
87791. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN_MASK
87792. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN__SHIFT
87793. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN_MASK
87794. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN__SHIFT
87795. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
87796. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
87797. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
87798. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
87799. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN_MASK
87800. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
87801. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
87802. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
87803. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
87804. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
87805. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR_MASK
87806. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
87807. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
87808. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
87809. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
87810. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
87811. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
87812. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
87813. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
87814. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
87815. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
87816. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
87817. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
87818. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
87819. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN_MASK
87820. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
87821. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID_MASK
87822. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID__SHIFT
87823. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED_MASK
87824. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED__SHIFT
87825. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR_MASK
87826. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR__SHIFT
87827. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR_MASK
87828. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR__SHIFT
87829. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
87830. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
87831. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR_MASK
87832. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR__SHIFT
87833. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
87834. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
87835. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
87836. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
87837. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED_MASK
87838. BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED__SHIFT
87839. BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE_MASK
87840. BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE__SHIFT
87841. BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE_MASK
87842. BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE__SHIFT
87843. BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
87844. BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
87845. BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
87846. BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
87847. BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER_MASK
87848. BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER__SHIFT
87849. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
87850. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
87851. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
87852. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
87853. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
87854. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
87855. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
87856. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
87857. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RESERVED_MASK
87858. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RESERVED__SHIFT
87859. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
87860. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
87861. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
87862. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
87863. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
87864. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
87865. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
87866. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
87867. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
87868. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
87869. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
87870. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
87871. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
87872. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
87873. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY_MASK
87874. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
87875. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
87876. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
87877. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED_MASK
87878. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED__SHIFT
87879. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH_MASK
87880. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH__SHIFT
87881. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT_MASK
87882. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT__SHIFT
87883. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER_MASK
87884. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER__SHIFT
87885. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
87886. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
87887. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
87888. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
87889. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
87890. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
87891. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
87892. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
87893. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
87894. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
87895. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
87896. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
87897. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
87898. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
87899. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
87900. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
87901. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN_MASK
87902. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
87903. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
87904. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
87905. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
87906. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
87907. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
87908. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
87909. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC_MASK
87910. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
87911. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
87912. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
87913. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
87914. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
87915. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
87916. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
87917. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS_MASK
87918. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS__SHIFT
87919. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL_MASK
87920. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL__SHIFT
87921. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
87922. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
87923. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK_MASK
87924. BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK__SHIFT
87925. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
87926. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
87927. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
87928. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
87929. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
87930. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
87931. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
87932. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
87933. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
87934. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
87935. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
87936. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
87937. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
87938. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
87939. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
87940. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
87941. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
87942. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
87943. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
87944. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
87945. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
87946. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
87947. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
87948. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
87949. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
87950. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
87951. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
87952. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
87953. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
87954. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
87955. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
87956. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
87957. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
87958. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
87959. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE_MASK
87960. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE__SHIFT
87961. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
87962. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
87963. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
87964. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
87965. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING_MASK
87966. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING__SHIFT
87967. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
87968. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
87969. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
87970. BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
87971. BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY__MAX_LAT_MASK
87972. BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY__MAX_LAT__SHIFT
87973. BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT__MIN_GNT_MASK
87974. BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT__MIN_GNT__SHIFT
87975. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID_MASK
87976. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID__SHIFT
87977. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR_MASK
87978. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
87979. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN_MASK
87980. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
87981. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
87982. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
87983. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
87984. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
87985. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR_MASK
87986. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
87987. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
87988. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
87989. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
87990. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
87991. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
87992. BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
87993. BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID_MASK
87994. BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID__SHIFT
87995. BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR_MASK
87996. BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
87997. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64_MASK
87998. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64__SHIFT
87999. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK_MASK
88000. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK__SHIFT
88001. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
88002. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
88003. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
88004. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
88005. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT_MASK
88006. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
88007. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN_MASK
88008. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN__SHIFT
88009. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
88010. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
88011. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
88012. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
88013. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
88014. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
88015. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
88016. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
88017. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA_MASK
88018. BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA__SHIFT
88019. BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64_MASK
88020. BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
88021. BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING_MASK
88022. BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING__SHIFT
88023. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
88024. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
88025. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
88026. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
88027. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
88028. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
88029. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
88030. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
88031. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
88032. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
88033. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
88034. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
88035. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
88036. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
88037. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
88038. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
88039. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
88040. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
88041. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
88042. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
88043. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
88044. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
88045. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
88046. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
88047. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
88048. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
88049. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
88050. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
88051. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
88052. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
88053. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
88054. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
88055. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
88056. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
88057. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
88058. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
88059. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
88060. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
88061. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
88062. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
88063. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
88064. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
88065. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
88066. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
88067. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
88068. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
88069. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
88070. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
88071. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
88072. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
88073. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__STU_MASK
88074. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__STU__SHIFT
88075. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
88076. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
88077. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
88078. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
88079. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
88080. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
88081. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID_MASK
88082. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID__SHIFT
88083. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR_MASK
88084. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
88085. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE_MASK
88086. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE__SHIFT
88087. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
88088. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
88089. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
88090. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
88091. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION_MASK
88092. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION__SHIFT
88093. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
88094. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
88095. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
88096. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
88097. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
88098. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
88099. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
88100. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
88101. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
88102. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
88103. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
88104. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
88105. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
88106. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
88107. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
88108. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
88109. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
88110. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
88111. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
88112. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
88113. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
88114. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
88115. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
88116. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
88117. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
88118. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
88119. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
88120. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
88121. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
88122. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
88123. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
88124. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
88125. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR_MASK
88126. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
88127. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR_MASK
88128. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
88129. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR_MASK
88130. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
88131. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR_MASK
88132. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
88133. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
88134. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
88135. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
88136. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
88137. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
88138. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
88139. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
88140. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
88141. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
88142. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
88143. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
88144. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
88145. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
88146. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
88147. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
88148. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
88149. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
88150. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
88151. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
88152. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
88153. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
88154. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
88155. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
88156. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
88157. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
88158. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
88159. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
88160. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
88161. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
88162. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
88163. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
88164. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
88165. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
88166. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
88167. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
88168. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
88169. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
88170. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
88171. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
88172. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
88173. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
88174. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
88175. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
88176. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
88177. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
88178. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
88179. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
88180. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
88181. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
88182. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
88183. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
88184. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
88185. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
88186. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
88187. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
88188. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
88189. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
88190. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
88191. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
88192. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
88193. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
88194. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
88195. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
88196. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
88197. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
88198. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
88199. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
88200. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
88201. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
88202. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
88203. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
88204. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
88205. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
88206. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
88207. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
88208. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
88209. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
88210. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
88211. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
88212. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
88213. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
88214. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
88215. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
88216. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
88217. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
88218. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
88219. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
88220. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
88221. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
88222. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
88223. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
88224. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
88225. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
88226. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
88227. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
88228. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
88229. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
88230. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
88231. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
88232. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
88233. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
88234. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
88235. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
88236. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
88237. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
88238. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
88239. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
88240. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
88241. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
88242. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
88243. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
88244. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
88245. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
88246. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
88247. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
88248. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
88249. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
88250. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
88251. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
88252. BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
88253. BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE_MASK
88254. BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
88255. BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID_MASK
88256. BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID__SHIFT
88257. BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID_MASK
88258. BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID__SHIFT
88259. BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR_MASK
88260. BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
88261. BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2__RESERVED_MASK
88262. BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2__RESERVED__SHIFT
88263. BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2__RESERVED_MASK
88264. BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2__RESERVED__SHIFT
88265. BIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2__RESERVED_MASK
88266. BIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2__RESERVED__SHIFT
88267. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST_MASK
88268. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST__SHIFT
88269. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING_MASK
88270. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING__SHIFT
88271. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE_MASK
88272. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE__SHIFT
88273. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__IMMEDIATE_READINESS_MASK
88274. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__IMMEDIATE_READINESS__SHIFT
88275. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS_MASK
88276. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS__SHIFT
88277. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
88278. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
88279. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED_MASK
88280. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
88281. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_CAP_MASK
88282. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_CAP__SHIFT
88283. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_EN_MASK
88284. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_EN__SHIFT
88285. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT_MASK
88286. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
88287. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT_MASK
88288. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
88289. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
88290. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
88291. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT_MASK
88292. BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
88293. BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS_MASK
88294. BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS__SHIFT
88295. BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID_MASK
88296. BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID__SHIFT
88297. BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
88298. BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
88299. BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
88300. BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
88301. BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR_MASK
88302. BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR__SHIFT
88303. BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR_MASK
88304. BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR__SHIFT
88305. BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR_MASK
88306. BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR__SHIFT
88307. BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR_MASK
88308. BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR__SHIFT
88309. BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR_MASK
88310. BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR__SHIFT
88311. BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR_MASK
88312. BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR__SHIFT
88313. BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS_MASK
88314. BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS__SHIFT
88315. BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP_MASK
88316. BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP__SHIFT
88317. BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP_MASK
88318. BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP__SHIFT
88319. BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT_MASK
88320. BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT__SHIFT
88321. BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
88322. BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
88323. BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR_MASK
88324. BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR__SHIFT
88325. BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
88326. BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
88327. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING_MASK
88328. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING__SHIFT
88329. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN_MASK
88330. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN__SHIFT
88331. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN_MASK
88332. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN__SHIFT
88333. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS_MASK
88334. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS__SHIFT
88335. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN_MASK
88336. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN__SHIFT
88337. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN_MASK
88338. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN__SHIFT
88339. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
88340. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
88341. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN_MASK
88342. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN__SHIFT
88343. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
88344. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
88345. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN_MASK
88346. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN__SHIFT
88347. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN_MASK
88348. BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
88349. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
88350. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
88351. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
88352. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
88353. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
88354. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
88355. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
88356. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
88357. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
88358. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
88359. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
88360. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
88361. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
88362. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
88363. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
88364. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
88365. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
88366. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
88367. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
88368. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
88369. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
88370. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
88371. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
88372. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
88373. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
88374. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
88375. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
88376. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
88377. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
88378. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
88379. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
88380. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
88381. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
88382. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
88383. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
88384. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
88385. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
88386. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
88387. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
88388. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
88389. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
88390. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
88391. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
88392. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
88393. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG_MASK
88394. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
88395. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE_MASK
88396. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
88397. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
88398. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
88399. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
88400. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
88401. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
88402. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
88403. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC_MASK
88404. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
88405. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
88406. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
88407. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
88408. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
88409. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
88410. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
88411. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
88412. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
88413. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
88414. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
88415. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
88416. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
88417. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
88418. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
88419. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
88420. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
88421. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
88422. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
88423. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
88424. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
88425. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN_MASK
88426. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN__SHIFT
88427. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN_MASK
88428. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN__SHIFT
88429. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
88430. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
88431. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
88432. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
88433. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN_MASK
88434. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
88435. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
88436. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
88437. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
88438. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
88439. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR_MASK
88440. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
88441. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
88442. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
88443. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
88444. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
88445. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
88446. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
88447. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
88448. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
88449. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
88450. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
88451. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
88452. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
88453. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN_MASK
88454. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
88455. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID_MASK
88456. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID__SHIFT
88457. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED_MASK
88458. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED__SHIFT
88459. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR_MASK
88460. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR__SHIFT
88461. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR_MASK
88462. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR__SHIFT
88463. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
88464. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
88465. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR_MASK
88466. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR__SHIFT
88467. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
88468. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
88469. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
88470. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
88471. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED_MASK
88472. BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED__SHIFT
88473. BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE_MASK
88474. BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE__SHIFT
88475. BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE_MASK
88476. BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE__SHIFT
88477. BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
88478. BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
88479. BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
88480. BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
88481. BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER_MASK
88482. BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER__SHIFT
88483. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
88484. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
88485. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
88486. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
88487. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
88488. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
88489. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
88490. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
88491. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RESERVED_MASK
88492. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RESERVED__SHIFT
88493. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
88494. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
88495. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
88496. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
88497. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
88498. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
88499. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
88500. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
88501. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
88502. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
88503. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
88504. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
88505. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
88506. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
88507. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY_MASK
88508. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
88509. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
88510. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
88511. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED_MASK
88512. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED__SHIFT
88513. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH_MASK
88514. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH__SHIFT
88515. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT_MASK
88516. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT__SHIFT
88517. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER_MASK
88518. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER__SHIFT
88519. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
88520. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
88521. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
88522. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
88523. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
88524. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
88525. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
88526. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
88527. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
88528. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
88529. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
88530. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
88531. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
88532. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
88533. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
88534. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
88535. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN_MASK
88536. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
88537. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
88538. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
88539. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
88540. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
88541. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
88542. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
88543. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC_MASK
88544. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
88545. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
88546. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
88547. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
88548. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
88549. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
88550. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
88551. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS_MASK
88552. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS__SHIFT
88553. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL_MASK
88554. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL__SHIFT
88555. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
88556. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
88557. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK_MASK
88558. BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK__SHIFT
88559. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
88560. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
88561. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
88562. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
88563. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
88564. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
88565. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
88566. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
88567. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
88568. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
88569. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
88570. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
88571. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
88572. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
88573. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
88574. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
88575. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
88576. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
88577. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
88578. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
88579. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
88580. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
88581. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
88582. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
88583. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
88584. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
88585. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
88586. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
88587. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
88588. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
88589. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
88590. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
88591. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
88592. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
88593. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE_MASK
88594. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE__SHIFT
88595. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
88596. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
88597. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
88598. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
88599. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING_MASK
88600. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING__SHIFT
88601. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
88602. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
88603. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
88604. BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
88605. BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY__MAX_LAT_MASK
88606. BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY__MAX_LAT__SHIFT
88607. BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT__MIN_GNT_MASK
88608. BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT__MIN_GNT__SHIFT
88609. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID_MASK
88610. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID__SHIFT
88611. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR_MASK
88612. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
88613. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN_MASK
88614. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
88615. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
88616. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
88617. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
88618. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
88619. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR_MASK
88620. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
88621. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
88622. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
88623. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
88624. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
88625. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
88626. BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
88627. BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID_MASK
88628. BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID__SHIFT
88629. BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR_MASK
88630. BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
88631. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64_MASK
88632. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64__SHIFT
88633. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK_MASK
88634. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK__SHIFT
88635. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
88636. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
88637. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
88638. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
88639. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT_MASK
88640. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
88641. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN_MASK
88642. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN__SHIFT
88643. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
88644. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
88645. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
88646. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
88647. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
88648. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
88649. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
88650. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
88651. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA_MASK
88652. BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA__SHIFT
88653. BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64_MASK
88654. BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
88655. BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING_MASK
88656. BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING__SHIFT
88657. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
88658. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
88659. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
88660. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
88661. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
88662. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
88663. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
88664. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
88665. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
88666. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
88667. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
88668. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
88669. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
88670. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
88671. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
88672. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
88673. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
88674. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
88675. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
88676. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
88677. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
88678. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
88679. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
88680. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
88681. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
88682. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
88683. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
88684. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
88685. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
88686. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
88687. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
88688. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
88689. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
88690. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
88691. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
88692. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
88693. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
88694. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
88695. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
88696. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
88697. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
88698. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
88699. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
88700. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
88701. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
88702. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
88703. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
88704. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
88705. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
88706. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
88707. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__STU_MASK
88708. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__STU__SHIFT
88709. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
88710. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
88711. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
88712. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
88713. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
88714. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
88715. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID_MASK
88716. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID__SHIFT
88717. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR_MASK
88718. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
88719. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE_MASK
88720. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE__SHIFT
88721. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
88722. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
88723. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
88724. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
88725. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION_MASK
88726. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION__SHIFT
88727. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
88728. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
88729. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
88730. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
88731. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
88732. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
88733. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
88734. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
88735. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
88736. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
88737. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
88738. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
88739. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
88740. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
88741. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
88742. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
88743. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
88744. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
88745. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
88746. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
88747. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
88748. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
88749. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
88750. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
88751. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
88752. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
88753. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
88754. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
88755. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
88756. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
88757. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
88758. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
88759. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR_MASK
88760. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
88761. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR_MASK
88762. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
88763. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR_MASK
88764. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
88765. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR_MASK
88766. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
88767. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
88768. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
88769. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
88770. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
88771. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
88772. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
88773. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
88774. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
88775. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
88776. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
88777. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
88778. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
88779. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
88780. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
88781. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
88782. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
88783. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
88784. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
88785. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
88786. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
88787. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
88788. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
88789. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
88790. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
88791. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
88792. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
88793. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
88794. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
88795. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
88796. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
88797. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
88798. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
88799. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
88800. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
88801. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
88802. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
88803. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
88804. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
88805. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
88806. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
88807. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
88808. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
88809. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
88810. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
88811. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
88812. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
88813. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
88814. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
88815. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
88816. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
88817. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
88818. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
88819. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
88820. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
88821. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
88822. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
88823. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
88824. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
88825. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
88826. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
88827. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
88828. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
88829. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
88830. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
88831. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
88832. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
88833. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
88834. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
88835. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
88836. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
88837. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
88838. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
88839. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
88840. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
88841. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
88842. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
88843. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
88844. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
88845. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
88846. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
88847. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
88848. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
88849. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
88850. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
88851. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
88852. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
88853. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
88854. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
88855. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
88856. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
88857. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
88858. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
88859. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
88860. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
88861. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
88862. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
88863. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
88864. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
88865. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
88866. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
88867. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
88868. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
88869. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
88870. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
88871. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
88872. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
88873. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
88874. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
88875. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
88876. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
88877. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
88878. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
88879. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
88880. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
88881. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
88882. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
88883. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
88884. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
88885. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
88886. BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
88887. BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE_MASK
88888. BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
88889. BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID_MASK
88890. BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID__SHIFT
88891. BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID_MASK
88892. BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID__SHIFT
88893. BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR_MASK
88894. BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
88895. BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CAP2__RESERVED_MASK
88896. BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CAP2__RESERVED__SHIFT
88897. BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CNTL2__RESERVED_MASK
88898. BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CNTL2__RESERVED__SHIFT
88899. BIF_CFG_DEV0_EPF0_VF15_1_SLOT_STATUS2__RESERVED_MASK
88900. BIF_CFG_DEV0_EPF0_VF15_1_SLOT_STATUS2__RESERVED__SHIFT
88901. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST_MASK
88902. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST__SHIFT
88903. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING_MASK
88904. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING__SHIFT
88905. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE_MASK
88906. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE__SHIFT
88907. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__IMMEDIATE_READINESS_MASK
88908. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__IMMEDIATE_READINESS__SHIFT
88909. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS_MASK
88910. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS__SHIFT
88911. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
88912. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
88913. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED_MASK
88914. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
88915. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_CAP_MASK
88916. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_CAP__SHIFT
88917. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_EN_MASK
88918. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_EN__SHIFT
88919. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT_MASK
88920. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
88921. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT_MASK
88922. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
88923. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
88924. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
88925. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT_MASK
88926. BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
88927. BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS_MASK
88928. BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS__SHIFT
88929. BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID_MASK
88930. BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID__SHIFT
88931. BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_ID_MASK
88932. BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
88933. BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
88934. BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
88935. BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1__BASE_ADDR_MASK
88936. BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1__BASE_ADDR__SHIFT
88937. BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2__BASE_ADDR_MASK
88938. BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2__BASE_ADDR__SHIFT
88939. BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3__BASE_ADDR_MASK
88940. BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3__BASE_ADDR__SHIFT
88941. BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4__BASE_ADDR_MASK
88942. BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4__BASE_ADDR__SHIFT
88943. BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5__BASE_ADDR_MASK
88944. BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5__BASE_ADDR__SHIFT
88945. BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6__BASE_ADDR_MASK
88946. BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6__BASE_ADDR__SHIFT
88947. BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS__BASE_CLASS_MASK
88948. BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS__BASE_CLASS__SHIFT
88949. BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_CAP_MASK
88950. BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_CAP__SHIFT
88951. BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_COMP_MASK
88952. BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_COMP__SHIFT
88953. BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_STRT_MASK
88954. BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_STRT__SHIFT
88955. BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE__CACHE_LINE_SIZE_MASK
88956. BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
88957. BIF_CFG_DEV0_EPF0_VF15_CAP_PTR__CAP_PTR_MASK
88958. BIF_CFG_DEV0_EPF0_VF15_CAP_PTR__CAP_PTR__SHIFT
88959. BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
88960. BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
88961. BIF_CFG_DEV0_EPF0_VF15_COMMAND__AD_STEPPING_MASK
88962. BIF_CFG_DEV0_EPF0_VF15_COMMAND__AD_STEPPING__SHIFT
88963. BIF_CFG_DEV0_EPF0_VF15_COMMAND__BUS_MASTER_EN_MASK
88964. BIF_CFG_DEV0_EPF0_VF15_COMMAND__BUS_MASTER_EN__SHIFT
88965. BIF_CFG_DEV0_EPF0_VF15_COMMAND__FAST_B2B_EN_MASK
88966. BIF_CFG_DEV0_EPF0_VF15_COMMAND__FAST_B2B_EN__SHIFT
88967. BIF_CFG_DEV0_EPF0_VF15_COMMAND__INT_DIS_MASK
88968. BIF_CFG_DEV0_EPF0_VF15_COMMAND__INT_DIS__SHIFT
88969. BIF_CFG_DEV0_EPF0_VF15_COMMAND__IO_ACCESS_EN_MASK
88970. BIF_CFG_DEV0_EPF0_VF15_COMMAND__IO_ACCESS_EN__SHIFT
88971. BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_ACCESS_EN_MASK
88972. BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_ACCESS_EN__SHIFT
88973. BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
88974. BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
88975. BIF_CFG_DEV0_EPF0_VF15_COMMAND__PAL_SNOOP_EN_MASK
88976. BIF_CFG_DEV0_EPF0_VF15_COMMAND__PAL_SNOOP_EN__SHIFT
88977. BIF_CFG_DEV0_EPF0_VF15_COMMAND__PARITY_ERROR_RESPONSE_MASK
88978. BIF_CFG_DEV0_EPF0_VF15_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
88979. BIF_CFG_DEV0_EPF0_VF15_COMMAND__SERR_EN_MASK
88980. BIF_CFG_DEV0_EPF0_VF15_COMMAND__SERR_EN__SHIFT
88981. BIF_CFG_DEV0_EPF0_VF15_COMMAND__SPECIAL_CYCLE_EN_MASK
88982. BIF_CFG_DEV0_EPF0_VF15_COMMAND__SPECIAL_CYCLE_EN__SHIFT
88983. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
88984. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
88985. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
88986. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
88987. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
88988. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
88989. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
88990. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
88991. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
88992. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
88993. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
88994. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
88995. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
88996. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
88997. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
88998. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
88999. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
89000. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
89001. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
89002. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
89003. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
89004. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
89005. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__FRS_SUPPORTED_MASK
89006. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
89007. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
89008. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
89009. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LTR_SUPPORTED_MASK
89010. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
89011. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
89012. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
89013. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
89014. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
89015. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__OBFF_SUPPORTED_MASK
89016. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
89017. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
89018. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
89019. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
89020. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
89021. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
89022. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
89023. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
89024. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
89025. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
89026. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
89027. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__EXTENDED_TAG_MASK
89028. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__EXTENDED_TAG__SHIFT
89029. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__FLR_CAPABLE_MASK
89030. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__FLR_CAPABLE__SHIFT
89031. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
89032. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
89033. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
89034. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
89035. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
89036. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
89037. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__PHANTOM_FUNC_MASK
89038. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__PHANTOM_FUNC__SHIFT
89039. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
89040. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
89041. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
89042. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
89043. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
89044. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
89045. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
89046. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
89047. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
89048. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
89049. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
89050. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
89051. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
89052. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
89053. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
89054. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
89055. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
89056. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
89057. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
89058. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
89059. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__LTR_EN_MASK
89060. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__LTR_EN__SHIFT
89061. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__OBFF_EN_MASK
89062. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__OBFF_EN__SHIFT
89063. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
89064. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
89065. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
89066. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
89067. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__CORR_ERR_EN_MASK
89068. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__CORR_ERR_EN__SHIFT
89069. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
89070. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
89071. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__FATAL_ERR_EN_MASK
89072. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
89073. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__INITIATE_FLR_MASK
89074. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__INITIATE_FLR__SHIFT
89075. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
89076. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
89077. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
89078. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
89079. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
89080. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
89081. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NO_SNOOP_EN_MASK
89082. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
89083. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
89084. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
89085. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__RELAXED_ORD_EN_MASK
89086. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
89087. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__USR_REPORT_EN_MASK
89088. BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__USR_REPORT_EN__SHIFT
89089. BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID__DEVICE_ID_MASK
89090. BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID__DEVICE_ID__SHIFT
89091. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2__RESERVED_MASK
89092. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2__RESERVED__SHIFT
89093. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__AUX_PWR_MASK
89094. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__AUX_PWR__SHIFT
89095. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__CORR_ERR_MASK
89096. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__CORR_ERR__SHIFT
89097. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
89098. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
89099. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__FATAL_ERR_MASK
89100. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__FATAL_ERR__SHIFT
89101. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__NON_FATAL_ERR_MASK
89102. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
89103. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
89104. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
89105. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__USR_DETECTED_MASK
89106. BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__USR_DETECTED__SHIFT
89107. BIF_CFG_DEV0_EPF0_VF15_HEADER__DEVICE_TYPE_MASK
89108. BIF_CFG_DEV0_EPF0_VF15_HEADER__DEVICE_TYPE__SHIFT
89109. BIF_CFG_DEV0_EPF0_VF15_HEADER__HEADER_TYPE_MASK
89110. BIF_CFG_DEV0_EPF0_VF15_HEADER__HEADER_TYPE__SHIFT
89111. BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE__INTERRUPT_LINE_MASK
89112. BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
89113. BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN__INTERRUPT_PIN_MASK
89114. BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
89115. BIF_CFG_DEV0_EPF0_VF15_LATENCY__LATENCY_TIMER_MASK
89116. BIF_CFG_DEV0_EPF0_VF15_LATENCY__LATENCY_TIMER__SHIFT
89117. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
89118. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
89119. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
89120. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
89121. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
89122. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
89123. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
89124. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
89125. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
89126. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
89127. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
89128. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
89129. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
89130. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
89131. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
89132. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
89133. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
89134. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
89135. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
89136. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
89137. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L0S_EXIT_LATENCY_MASK
89138. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
89139. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L1_EXIT_LATENCY_MASK
89140. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L1_EXIT_LATENCY__SHIFT
89141. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
89142. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
89143. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_SPEED_MASK
89144. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_SPEED__SHIFT
89145. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_WIDTH_MASK
89146. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_WIDTH__SHIFT
89147. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PM_SUPPORT_MASK
89148. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PM_SUPPORT__SHIFT
89149. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PORT_NUMBER_MASK
89150. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PORT_NUMBER__SHIFT
89151. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
89152. BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
89153. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
89154. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
89155. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_SOS_MASK
89156. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
89157. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_COMPLIANCE_MASK
89158. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
89159. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
89160. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
89161. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
89162. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
89163. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
89164. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
89165. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__TARGET_LINK_SPEED_MASK
89166. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
89167. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__XMIT_MARGIN_MASK
89168. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__XMIT_MARGIN__SHIFT
89169. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
89170. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
89171. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__COMMON_CLOCK_CFG_MASK
89172. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
89173. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
89174. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
89175. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__EXTENDED_SYNC_MASK
89176. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__EXTENDED_SYNC__SHIFT
89177. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
89178. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
89179. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
89180. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
89181. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
89182. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
89183. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_DIS_MASK
89184. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_DIS__SHIFT
89185. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PM_CONTROL_MASK
89186. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PM_CONTROL__SHIFT
89187. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__READ_CPL_BOUNDARY_MASK
89188. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
89189. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__RETRAIN_LINK_MASK
89190. BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__RETRAIN_LINK__SHIFT
89191. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
89192. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
89193. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
89194. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
89195. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
89196. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
89197. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
89198. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
89199. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
89200. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
89201. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
89202. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
89203. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
89204. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
89205. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
89206. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
89207. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
89208. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
89209. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
89210. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
89211. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
89212. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
89213. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__CURRENT_LINK_SPEED_MASK
89214. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
89215. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__DL_ACTIVE_MASK
89216. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__DL_ACTIVE__SHIFT
89217. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
89218. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
89219. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
89220. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
89221. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_TRAINING_MASK
89222. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_TRAINING__SHIFT
89223. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
89224. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
89225. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__SLOT_CLOCK_CFG_MASK
89226. BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
89227. BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY__MAX_LAT_MASK
89228. BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY__MAX_LAT__SHIFT
89229. BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT__MIN_GNT_MASK
89230. BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT__MIN_GNT__SHIFT
89231. BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__CAP_ID_MASK
89232. BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__CAP_ID__SHIFT
89233. BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__NEXT_PTR_MASK
89234. BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__NEXT_PTR__SHIFT
89235. BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_EN_MASK
89236. BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_EN__SHIFT
89237. BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
89238. BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
89239. BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
89240. BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
89241. BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_BIR_MASK
89242. BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_BIR__SHIFT
89243. BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_OFFSET_MASK
89244. BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
89245. BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_BIR_MASK
89246. BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
89247. BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
89248. BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
89249. BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__CAP_ID_MASK
89250. BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__CAP_ID__SHIFT
89251. BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__NEXT_PTR_MASK
89252. BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__NEXT_PTR__SHIFT
89253. BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64__MSI_MASK_64_MASK
89254. BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64__MSI_MASK_64__SHIFT
89255. BIF_CFG_DEV0_EPF0_VF15_MSI_MASK__MSI_MASK_MASK
89256. BIF_CFG_DEV0_EPF0_VF15_MSI_MASK__MSI_MASK__SHIFT
89257. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
89258. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
89259. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
89260. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
89261. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_64BIT_MASK
89262. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_64BIT__SHIFT
89263. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EN_MASK
89264. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EN__SHIFT
89265. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
89266. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
89267. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
89268. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
89269. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
89270. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
89271. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64__MSI_DATA_64_MASK
89272. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
89273. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA__MSI_DATA_MASK
89274. BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA__MSI_DATA__SHIFT
89275. BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64__MSI_PENDING_64_MASK
89276. BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64__MSI_PENDING_64__SHIFT
89277. BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING__MSI_PENDING_MASK
89278. BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING__MSI_PENDING__SHIFT
89279. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
89280. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
89281. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
89282. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
89283. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
89284. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
89285. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
89286. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
89287. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
89288. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
89289. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
89290. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
89291. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
89292. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
89293. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
89294. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
89295. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
89296. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
89297. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
89298. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
89299. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
89300. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
89301. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
89302. BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
89303. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
89304. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
89305. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
89306. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
89307. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
89308. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
89309. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
89310. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
89311. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
89312. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
89313. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
89314. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
89315. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
89316. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
89317. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
89318. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
89319. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
89320. BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
89321. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
89322. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
89323. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
89324. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
89325. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
89326. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
89327. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL__ATC_ENABLE_MASK
89328. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
89329. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL__STU_MASK
89330. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL__STU__SHIFT
89331. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
89332. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
89333. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
89334. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
89335. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
89336. BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
89337. BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__CAP_ID_MASK
89338. BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__CAP_ID__SHIFT
89339. BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__NEXT_PTR_MASK
89340. BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__NEXT_PTR__SHIFT
89341. BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__DEVICE_TYPE_MASK
89342. BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__DEVICE_TYPE__SHIFT
89343. BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__INT_MESSAGE_NUM_MASK
89344. BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
89345. BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__SLOT_IMPLEMENTED_MASK
89346. BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
89347. BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__VERSION_MASK
89348. BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__VERSION__SHIFT
89349. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
89350. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
89351. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
89352. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
89353. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
89354. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
89355. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
89356. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
89357. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
89358. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
89359. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
89360. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
89361. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
89362. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
89363. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
89364. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
89365. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
89366. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
89367. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
89368. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
89369. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
89370. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
89371. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
89372. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
89373. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
89374. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
89375. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
89376. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
89377. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
89378. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
89379. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
89380. BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
89381. BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0__TLP_HDR_MASK
89382. BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0__TLP_HDR__SHIFT
89383. BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1__TLP_HDR_MASK
89384. BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1__TLP_HDR__SHIFT
89385. BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2__TLP_HDR_MASK
89386. BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2__TLP_HDR__SHIFT
89387. BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3__TLP_HDR_MASK
89388. BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3__TLP_HDR__SHIFT
89389. BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
89390. BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
89391. BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
89392. BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
89393. BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
89394. BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
89395. BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
89396. BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
89397. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
89398. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
89399. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
89400. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
89401. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
89402. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
89403. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
89404. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
89405. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
89406. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
89407. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
89408. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
89409. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
89410. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
89411. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
89412. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
89413. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
89414. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
89415. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
89416. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
89417. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
89418. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
89419. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
89420. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
89421. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
89422. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
89423. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
89424. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
89425. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
89426. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
89427. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
89428. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
89429. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
89430. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
89431. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
89432. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
89433. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
89434. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
89435. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
89436. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
89437. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
89438. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
89439. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
89440. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
89441. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
89442. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
89443. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
89444. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
89445. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
89446. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
89447. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
89448. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
89449. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
89450. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
89451. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
89452. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
89453. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
89454. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
89455. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
89456. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
89457. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
89458. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
89459. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
89460. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
89461. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
89462. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
89463. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
89464. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
89465. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
89466. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
89467. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
89468. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
89469. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
89470. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
89471. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
89472. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
89473. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
89474. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
89475. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
89476. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
89477. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
89478. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
89479. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
89480. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
89481. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
89482. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
89483. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
89484. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
89485. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
89486. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
89487. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
89488. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
89489. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
89490. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
89491. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
89492. BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
89493. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
89494. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
89495. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
89496. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
89497. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
89498. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
89499. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
89500. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
89501. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
89502. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
89503. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
89504. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
89505. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
89506. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
89507. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
89508. BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
89509. BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE__PROG_INTERFACE_MASK
89510. BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE__PROG_INTERFACE__SHIFT
89511. BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MAJOR_REV_ID_MASK
89512. BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MAJOR_REV_ID__SHIFT
89513. BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MINOR_REV_ID_MASK
89514. BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MINOR_REV_ID__SHIFT
89515. BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__BASE_ADDR_MASK
89516. BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__BASE_ADDR__SHIFT
89517. BIF_CFG_DEV0_EPF0_VF15_STATUS__CAP_LIST_MASK
89518. BIF_CFG_DEV0_EPF0_VF15_STATUS__CAP_LIST__SHIFT
89519. BIF_CFG_DEV0_EPF0_VF15_STATUS__DEVSEL_TIMING_MASK
89520. BIF_CFG_DEV0_EPF0_VF15_STATUS__DEVSEL_TIMING__SHIFT
89521. BIF_CFG_DEV0_EPF0_VF15_STATUS__FAST_BACK_CAPABLE_MASK
89522. BIF_CFG_DEV0_EPF0_VF15_STATUS__FAST_BACK_CAPABLE__SHIFT
89523. BIF_CFG_DEV0_EPF0_VF15_STATUS__IMMEDIATE_READINESS_MASK
89524. BIF_CFG_DEV0_EPF0_VF15_STATUS__IMMEDIATE_READINESS__SHIFT
89525. BIF_CFG_DEV0_EPF0_VF15_STATUS__INT_STATUS_MASK
89526. BIF_CFG_DEV0_EPF0_VF15_STATUS__INT_STATUS__SHIFT
89527. BIF_CFG_DEV0_EPF0_VF15_STATUS__MASTER_DATA_PARITY_ERROR_MASK
89528. BIF_CFG_DEV0_EPF0_VF15_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
89529. BIF_CFG_DEV0_EPF0_VF15_STATUS__PARITY_ERROR_DETECTED_MASK
89530. BIF_CFG_DEV0_EPF0_VF15_STATUS__PARITY_ERROR_DETECTED__SHIFT
89531. BIF_CFG_DEV0_EPF0_VF15_STATUS__PCI_66_CAP_MASK
89532. BIF_CFG_DEV0_EPF0_VF15_STATUS__PCI_66_CAP__SHIFT
89533. BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_MASTER_ABORT_MASK
89534. BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_MASTER_ABORT__SHIFT
89535. BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_TARGET_ABORT_MASK
89536. BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_TARGET_ABORT__SHIFT
89537. BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNALED_SYSTEM_ERROR_MASK
89538. BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
89539. BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNAL_TARGET_ABORT_MASK
89540. BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNAL_TARGET_ABORT__SHIFT
89541. BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS__SUB_CLASS_MASK
89542. BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS__SUB_CLASS__SHIFT
89543. BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID__VENDOR_ID_MASK
89544. BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID__VENDOR_ID__SHIFT
89545. BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
89546. BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
89547. BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
89548. BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
89549. BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1__BASE_ADDR_MASK
89550. BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1__BASE_ADDR__SHIFT
89551. BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2__BASE_ADDR_MASK
89552. BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2__BASE_ADDR__SHIFT
89553. BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3__BASE_ADDR_MASK
89554. BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3__BASE_ADDR__SHIFT
89555. BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4__BASE_ADDR_MASK
89556. BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4__BASE_ADDR__SHIFT
89557. BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5__BASE_ADDR_MASK
89558. BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5__BASE_ADDR__SHIFT
89559. BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6__BASE_ADDR_MASK
89560. BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6__BASE_ADDR__SHIFT
89561. BIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS__BASE_CLASS_MASK
89562. BIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS__BASE_CLASS__SHIFT
89563. BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_CAP_MASK
89564. BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_CAP__SHIFT
89565. BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_COMP_MASK
89566. BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_COMP__SHIFT
89567. BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_STRT_MASK
89568. BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_STRT__SHIFT
89569. BIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
89570. BIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
89571. BIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR__CAP_PTR_MASK
89572. BIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR__CAP_PTR__SHIFT
89573. BIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
89574. BIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
89575. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__AD_STEPPING_MASK
89576. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__AD_STEPPING__SHIFT
89577. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__BUS_MASTER_EN_MASK
89578. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__BUS_MASTER_EN__SHIFT
89579. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__FAST_B2B_EN_MASK
89580. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__FAST_B2B_EN__SHIFT
89581. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__INT_DIS_MASK
89582. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__INT_DIS__SHIFT
89583. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__IO_ACCESS_EN_MASK
89584. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__IO_ACCESS_EN__SHIFT
89585. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__MEM_ACCESS_EN_MASK
89586. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__MEM_ACCESS_EN__SHIFT
89587. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
89588. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
89589. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__PAL_SNOOP_EN_MASK
89590. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__PAL_SNOOP_EN__SHIFT
89591. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
89592. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
89593. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__SERR_EN_MASK
89594. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__SERR_EN__SHIFT
89595. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__SPECIAL_CYCLE_EN_MASK
89596. BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
89597. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
89598. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
89599. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
89600. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
89601. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
89602. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
89603. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
89604. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
89605. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
89606. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
89607. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
89608. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
89609. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
89610. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
89611. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
89612. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
89613. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
89614. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
89615. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
89616. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
89617. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
89618. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
89619. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
89620. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
89621. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
89622. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
89623. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
89624. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
89625. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
89626. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
89627. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
89628. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
89629. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
89630. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
89631. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
89632. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
89633. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
89634. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
89635. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
89636. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
89637. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
89638. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
89639. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
89640. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
89641. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__EXTENDED_TAG_MASK
89642. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
89643. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__FLR_CAPABLE_MASK
89644. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
89645. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
89646. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
89647. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
89648. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
89649. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
89650. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
89651. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__PHANTOM_FUNC_MASK
89652. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
89653. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
89654. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
89655. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
89656. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
89657. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
89658. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
89659. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
89660. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
89661. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
89662. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
89663. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
89664. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
89665. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
89666. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
89667. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
89668. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
89669. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
89670. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
89671. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
89672. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
89673. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__LTR_EN_MASK
89674. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__LTR_EN__SHIFT
89675. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__OBFF_EN_MASK
89676. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__OBFF_EN__SHIFT
89677. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
89678. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
89679. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
89680. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
89681. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__CORR_ERR_EN_MASK
89682. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
89683. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
89684. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
89685. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
89686. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
89687. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__INITIATE_FLR_MASK
89688. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
89689. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
89690. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
89691. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
89692. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
89693. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
89694. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
89695. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
89696. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
89697. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
89698. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
89699. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
89700. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
89701. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__USR_REPORT_EN_MASK
89702. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
89703. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID__DEVICE_ID_MASK
89704. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID__DEVICE_ID__SHIFT
89705. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2__RESERVED_MASK
89706. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2__RESERVED__SHIFT
89707. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__AUX_PWR_MASK
89708. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__AUX_PWR__SHIFT
89709. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__CORR_ERR_MASK
89710. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__CORR_ERR__SHIFT
89711. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
89712. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
89713. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__FATAL_ERR_MASK
89714. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__FATAL_ERR__SHIFT
89715. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
89716. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
89717. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
89718. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
89719. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__USR_DETECTED_MASK
89720. BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__USR_DETECTED__SHIFT
89721. BIF_CFG_DEV0_EPF0_VF16_0_HEADER__DEVICE_TYPE_MASK
89722. BIF_CFG_DEV0_EPF0_VF16_0_HEADER__DEVICE_TYPE__SHIFT
89723. BIF_CFG_DEV0_EPF0_VF16_0_HEADER__HEADER_TYPE_MASK
89724. BIF_CFG_DEV0_EPF0_VF16_0_HEADER__HEADER_TYPE__SHIFT
89725. BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
89726. BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
89727. BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
89728. BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
89729. BIF_CFG_DEV0_EPF0_VF16_0_LATENCY__LATENCY_TIMER_MASK
89730. BIF_CFG_DEV0_EPF0_VF16_0_LATENCY__LATENCY_TIMER__SHIFT
89731. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
89732. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
89733. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
89734. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
89735. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
89736. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
89737. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
89738. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
89739. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
89740. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
89741. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
89742. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
89743. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
89744. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
89745. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
89746. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
89747. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
89748. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
89749. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
89750. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
89751. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
89752. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
89753. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__L1_EXIT_LATENCY_MASK
89754. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
89755. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
89756. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
89757. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_SPEED_MASK
89758. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_SPEED__SHIFT
89759. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_WIDTH_MASK
89760. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_WIDTH__SHIFT
89761. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__PM_SUPPORT_MASK
89762. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__PM_SUPPORT__SHIFT
89763. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__PORT_NUMBER_MASK
89764. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__PORT_NUMBER__SHIFT
89765. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
89766. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
89767. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
89768. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
89769. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
89770. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
89771. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
89772. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
89773. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
89774. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
89775. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
89776. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
89777. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
89778. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
89779. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
89780. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
89781. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__XMIT_MARGIN_MASK
89782. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
89783. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
89784. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
89785. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
89786. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
89787. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
89788. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
89789. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__EXTENDED_SYNC_MASK
89790. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
89791. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
89792. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
89793. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
89794. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
89795. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
89796. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
89797. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_DIS_MASK
89798. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_DIS__SHIFT
89799. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__PM_CONTROL_MASK
89800. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__PM_CONTROL__SHIFT
89801. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
89802. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
89803. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__RETRAIN_LINK_MASK
89804. BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__RETRAIN_LINK__SHIFT
89805. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
89806. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
89807. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
89808. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
89809. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
89810. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
89811. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
89812. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
89813. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
89814. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
89815. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
89816. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
89817. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
89818. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
89819. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
89820. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
89821. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
89822. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
89823. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
89824. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
89825. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
89826. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
89827. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
89828. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
89829. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__DL_ACTIVE_MASK
89830. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__DL_ACTIVE__SHIFT
89831. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
89832. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
89833. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
89834. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
89835. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_TRAINING_MASK
89836. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_TRAINING__SHIFT
89837. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
89838. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
89839. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
89840. BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
89841. BIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY__MAX_LAT_MASK
89842. BIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY__MAX_LAT__SHIFT
89843. BIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT__MIN_GNT_MASK
89844. BIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT__MIN_GNT__SHIFT
89845. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST__CAP_ID_MASK
89846. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST__CAP_ID__SHIFT
89847. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST__NEXT_PTR_MASK
89848. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
89849. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_EN_MASK
89850. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
89851. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
89852. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
89853. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
89854. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
89855. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA__MSIX_PBA_BIR_MASK
89856. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
89857. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
89858. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
89859. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
89860. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
89861. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
89862. BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
89863. BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST__CAP_ID_MASK
89864. BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST__CAP_ID__SHIFT
89865. BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST__NEXT_PTR_MASK
89866. BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
89867. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64__MSI_MASK_64_MASK
89868. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64__MSI_MASK_64__SHIFT
89869. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK__MSI_MASK_MASK
89870. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK__MSI_MASK__SHIFT
89871. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
89872. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
89873. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
89874. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
89875. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_64BIT_MASK
89876. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
89877. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_EN_MASK
89878. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_EN__SHIFT
89879. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
89880. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
89881. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
89882. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
89883. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
89884. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
89885. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
89886. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
89887. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA__MSI_DATA_MASK
89888. BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA__MSI_DATA__SHIFT
89889. BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64__MSI_PENDING_64_MASK
89890. BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
89891. BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING__MSI_PENDING_MASK
89892. BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING__MSI_PENDING__SHIFT
89893. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
89894. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
89895. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
89896. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
89897. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
89898. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
89899. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
89900. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
89901. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
89902. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
89903. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
89904. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
89905. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
89906. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
89907. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
89908. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
89909. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
89910. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
89911. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
89912. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
89913. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
89914. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
89915. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
89916. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
89917. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
89918. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
89919. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
89920. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
89921. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
89922. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
89923. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
89924. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
89925. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
89926. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
89927. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
89928. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
89929. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
89930. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
89931. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
89932. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
89933. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
89934. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
89935. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
89936. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
89937. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
89938. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
89939. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
89940. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
89941. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
89942. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
89943. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL__STU_MASK
89944. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL__STU__SHIFT
89945. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
89946. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
89947. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
89948. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
89949. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
89950. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
89951. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST__CAP_ID_MASK
89952. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST__CAP_ID__SHIFT
89953. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST__NEXT_PTR_MASK
89954. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
89955. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__DEVICE_TYPE_MASK
89956. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__DEVICE_TYPE__SHIFT
89957. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
89958. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
89959. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
89960. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
89961. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__VERSION_MASK
89962. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__VERSION__SHIFT
89963. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
89964. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
89965. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
89966. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
89967. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
89968. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
89969. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
89970. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
89971. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
89972. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
89973. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
89974. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
89975. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
89976. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
89977. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
89978. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
89979. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
89980. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
89981. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
89982. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
89983. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
89984. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
89985. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
89986. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
89987. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
89988. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
89989. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
89990. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
89991. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
89992. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
89993. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
89994. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
89995. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0__TLP_HDR_MASK
89996. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
89997. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1__TLP_HDR_MASK
89998. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
89999. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2__TLP_HDR_MASK
90000. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
90001. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3__TLP_HDR_MASK
90002. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
90003. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
90004. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
90005. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
90006. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
90007. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
90008. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
90009. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
90010. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
90011. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
90012. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
90013. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
90014. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
90015. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
90016. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
90017. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
90018. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
90019. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
90020. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
90021. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
90022. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
90023. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
90024. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
90025. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
90026. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
90027. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
90028. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
90029. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
90030. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
90031. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
90032. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
90033. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
90034. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
90035. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
90036. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
90037. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
90038. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
90039. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
90040. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
90041. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
90042. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
90043. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
90044. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
90045. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
90046. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
90047. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
90048. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
90049. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
90050. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
90051. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
90052. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
90053. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
90054. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
90055. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
90056. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
90057. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
90058. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
90059. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
90060. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
90061. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
90062. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
90063. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
90064. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
90065. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
90066. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
90067. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
90068. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
90069. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
90070. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
90071. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
90072. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
90073. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
90074. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
90075. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
90076. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
90077. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
90078. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
90079. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
90080. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
90081. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
90082. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
90083. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
90084. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
90085. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
90086. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
90087. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
90088. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
90089. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
90090. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
90091. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
90092. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
90093. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
90094. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
90095. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
90096. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
90097. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
90098. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
90099. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
90100. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
90101. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
90102. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
90103. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
90104. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
90105. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
90106. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
90107. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
90108. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
90109. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
90110. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
90111. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
90112. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
90113. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
90114. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
90115. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
90116. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
90117. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
90118. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
90119. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
90120. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
90121. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
90122. BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
90123. BIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE__PROG_INTERFACE_MASK
90124. BIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
90125. BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID__MAJOR_REV_ID_MASK
90126. BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID__MAJOR_REV_ID__SHIFT
90127. BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID__MINOR_REV_ID_MASK
90128. BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID__MINOR_REV_ID__SHIFT
90129. BIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR__BASE_ADDR_MASK
90130. BIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
90131. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__CAP_LIST_MASK
90132. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__CAP_LIST__SHIFT
90133. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__DEVSEL_TIMING_MASK
90134. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__DEVSEL_TIMING__SHIFT
90135. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__FAST_BACK_CAPABLE_MASK
90136. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__FAST_BACK_CAPABLE__SHIFT
90137. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__IMMEDIATE_READINESS_MASK
90138. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__IMMEDIATE_READINESS__SHIFT
90139. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__INT_STATUS_MASK
90140. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__INT_STATUS__SHIFT
90141. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
90142. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
90143. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__PARITY_ERROR_DETECTED_MASK
90144. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
90145. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__PCI_66_CAP_MASK
90146. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__PCI_66_CAP__SHIFT
90147. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__RECEIVED_MASTER_ABORT_MASK
90148. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
90149. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__RECEIVED_TARGET_ABORT_MASK
90150. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
90151. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
90152. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
90153. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__SIGNAL_TARGET_ABORT_MASK
90154. BIF_CFG_DEV0_EPF0_VF16_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
90155. BIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS__SUB_CLASS_MASK
90156. BIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS__SUB_CLASS__SHIFT
90157. BIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID__VENDOR_ID_MASK
90158. BIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID__VENDOR_ID__SHIFT
90159. BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
90160. BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
90161. BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
90162. BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
90163. BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1__BASE_ADDR_MASK
90164. BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1__BASE_ADDR__SHIFT
90165. BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2__BASE_ADDR_MASK
90166. BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2__BASE_ADDR__SHIFT
90167. BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3__BASE_ADDR_MASK
90168. BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3__BASE_ADDR__SHIFT
90169. BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4__BASE_ADDR_MASK
90170. BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4__BASE_ADDR__SHIFT
90171. BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5__BASE_ADDR_MASK
90172. BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5__BASE_ADDR__SHIFT
90173. BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6__BASE_ADDR_MASK
90174. BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6__BASE_ADDR__SHIFT
90175. BIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS__BASE_CLASS_MASK
90176. BIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS__BASE_CLASS__SHIFT
90177. BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_CAP_MASK
90178. BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_CAP__SHIFT
90179. BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_COMP_MASK
90180. BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_COMP__SHIFT
90181. BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_STRT_MASK
90182. BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_STRT__SHIFT
90183. BIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
90184. BIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
90185. BIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR__CAP_PTR_MASK
90186. BIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR__CAP_PTR__SHIFT
90187. BIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
90188. BIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
90189. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__AD_STEPPING_MASK
90190. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__AD_STEPPING__SHIFT
90191. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__BUS_MASTER_EN_MASK
90192. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__BUS_MASTER_EN__SHIFT
90193. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__FAST_B2B_EN_MASK
90194. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__FAST_B2B_EN__SHIFT
90195. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__INT_DIS_MASK
90196. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__INT_DIS__SHIFT
90197. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__IO_ACCESS_EN_MASK
90198. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__IO_ACCESS_EN__SHIFT
90199. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__MEM_ACCESS_EN_MASK
90200. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__MEM_ACCESS_EN__SHIFT
90201. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
90202. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
90203. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__PAL_SNOOP_EN_MASK
90204. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__PAL_SNOOP_EN__SHIFT
90205. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
90206. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
90207. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__SERR_EN_MASK
90208. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__SERR_EN__SHIFT
90209. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__SPECIAL_CYCLE_EN_MASK
90210. BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
90211. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
90212. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
90213. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
90214. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
90215. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
90216. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
90217. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
90218. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
90219. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
90220. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
90221. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
90222. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
90223. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
90224. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
90225. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
90226. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
90227. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
90228. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
90229. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
90230. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
90231. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
90232. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
90233. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
90234. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
90235. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
90236. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
90237. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
90238. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
90239. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
90240. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
90241. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
90242. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
90243. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
90244. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
90245. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
90246. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
90247. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
90248. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
90249. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
90250. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
90251. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
90252. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
90253. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
90254. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
90255. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__EXTENDED_TAG_MASK
90256. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
90257. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__FLR_CAPABLE_MASK
90258. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
90259. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
90260. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
90261. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
90262. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
90263. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
90264. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
90265. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__PHANTOM_FUNC_MASK
90266. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
90267. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
90268. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
90269. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
90270. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
90271. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
90272. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
90273. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
90274. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
90275. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
90276. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
90277. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
90278. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
90279. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
90280. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
90281. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
90282. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
90283. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
90284. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
90285. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
90286. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
90287. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__LTR_EN_MASK
90288. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__LTR_EN__SHIFT
90289. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__OBFF_EN_MASK
90290. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__OBFF_EN__SHIFT
90291. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
90292. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
90293. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
90294. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
90295. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__CORR_ERR_EN_MASK
90296. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
90297. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
90298. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
90299. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
90300. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
90301. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__INITIATE_FLR_MASK
90302. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
90303. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
90304. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
90305. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
90306. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
90307. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
90308. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
90309. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
90310. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
90311. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
90312. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
90313. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
90314. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
90315. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__USR_REPORT_EN_MASK
90316. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
90317. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID__DEVICE_ID_MASK
90318. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID__DEVICE_ID__SHIFT
90319. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2__RESERVED_MASK
90320. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2__RESERVED__SHIFT
90321. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__AUX_PWR_MASK
90322. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__AUX_PWR__SHIFT
90323. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__CORR_ERR_MASK
90324. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__CORR_ERR__SHIFT
90325. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
90326. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
90327. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__FATAL_ERR_MASK
90328. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__FATAL_ERR__SHIFT
90329. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
90330. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
90331. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
90332. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
90333. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__USR_DETECTED_MASK
90334. BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__USR_DETECTED__SHIFT
90335. BIF_CFG_DEV0_EPF0_VF16_1_HEADER__DEVICE_TYPE_MASK
90336. BIF_CFG_DEV0_EPF0_VF16_1_HEADER__DEVICE_TYPE__SHIFT
90337. BIF_CFG_DEV0_EPF0_VF16_1_HEADER__HEADER_TYPE_MASK
90338. BIF_CFG_DEV0_EPF0_VF16_1_HEADER__HEADER_TYPE__SHIFT
90339. BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
90340. BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
90341. BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
90342. BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
90343. BIF_CFG_DEV0_EPF0_VF16_1_LATENCY__LATENCY_TIMER_MASK
90344. BIF_CFG_DEV0_EPF0_VF16_1_LATENCY__LATENCY_TIMER__SHIFT
90345. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
90346. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
90347. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
90348. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
90349. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
90350. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
90351. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
90352. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
90353. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
90354. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
90355. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
90356. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
90357. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
90358. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
90359. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
90360. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
90361. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
90362. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
90363. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
90364. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
90365. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
90366. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
90367. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__L1_EXIT_LATENCY_MASK
90368. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
90369. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
90370. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
90371. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_SPEED_MASK
90372. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_SPEED__SHIFT
90373. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_WIDTH_MASK
90374. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_WIDTH__SHIFT
90375. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__PM_SUPPORT_MASK
90376. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__PM_SUPPORT__SHIFT
90377. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__PORT_NUMBER_MASK
90378. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__PORT_NUMBER__SHIFT
90379. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
90380. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
90381. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
90382. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
90383. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
90384. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
90385. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
90386. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
90387. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
90388. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
90389. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
90390. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
90391. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
90392. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
90393. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
90394. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
90395. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__XMIT_MARGIN_MASK
90396. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
90397. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
90398. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
90399. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
90400. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
90401. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
90402. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
90403. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__EXTENDED_SYNC_MASK
90404. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
90405. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
90406. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
90407. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
90408. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
90409. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
90410. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
90411. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_DIS_MASK
90412. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_DIS__SHIFT
90413. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__PM_CONTROL_MASK
90414. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__PM_CONTROL__SHIFT
90415. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
90416. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
90417. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__RETRAIN_LINK_MASK
90418. BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__RETRAIN_LINK__SHIFT
90419. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
90420. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
90421. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
90422. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
90423. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
90424. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
90425. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
90426. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
90427. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
90428. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
90429. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
90430. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
90431. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
90432. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
90433. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
90434. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
90435. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
90436. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
90437. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
90438. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
90439. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
90440. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
90441. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
90442. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
90443. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__DL_ACTIVE_MASK
90444. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__DL_ACTIVE__SHIFT
90445. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
90446. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
90447. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
90448. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
90449. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_TRAINING_MASK
90450. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_TRAINING__SHIFT
90451. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
90452. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
90453. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
90454. BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
90455. BIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY__MAX_LAT_MASK
90456. BIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY__MAX_LAT__SHIFT
90457. BIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT__MIN_GNT_MASK
90458. BIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT__MIN_GNT__SHIFT
90459. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST__CAP_ID_MASK
90460. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST__CAP_ID__SHIFT
90461. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST__NEXT_PTR_MASK
90462. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
90463. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_EN_MASK
90464. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
90465. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
90466. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
90467. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
90468. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
90469. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA__MSIX_PBA_BIR_MASK
90470. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
90471. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
90472. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
90473. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
90474. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
90475. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
90476. BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
90477. BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST__CAP_ID_MASK
90478. BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST__CAP_ID__SHIFT
90479. BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST__NEXT_PTR_MASK
90480. BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
90481. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64__MSI_MASK_64_MASK
90482. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64__MSI_MASK_64__SHIFT
90483. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK__MSI_MASK_MASK
90484. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK__MSI_MASK__SHIFT
90485. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
90486. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
90487. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
90488. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
90489. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_64BIT_MASK
90490. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
90491. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_EN_MASK
90492. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_EN__SHIFT
90493. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
90494. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
90495. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
90496. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
90497. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
90498. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
90499. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
90500. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
90501. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA__MSI_DATA_MASK
90502. BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA__MSI_DATA__SHIFT
90503. BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64__MSI_PENDING_64_MASK
90504. BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
90505. BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING__MSI_PENDING_MASK
90506. BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING__MSI_PENDING__SHIFT
90507. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
90508. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
90509. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
90510. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
90511. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
90512. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
90513. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
90514. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
90515. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
90516. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
90517. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
90518. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
90519. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
90520. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
90521. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
90522. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
90523. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
90524. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
90525. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
90526. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
90527. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
90528. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
90529. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
90530. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
90531. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
90532. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
90533. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
90534. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
90535. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
90536. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
90537. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
90538. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
90539. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
90540. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
90541. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
90542. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
90543. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
90544. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
90545. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
90546. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
90547. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
90548. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
90549. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
90550. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
90551. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
90552. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
90553. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
90554. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
90555. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
90556. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
90557. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL__STU_MASK
90558. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL__STU__SHIFT
90559. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
90560. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
90561. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
90562. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
90563. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
90564. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
90565. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST__CAP_ID_MASK
90566. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST__CAP_ID__SHIFT
90567. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST__NEXT_PTR_MASK
90568. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
90569. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__DEVICE_TYPE_MASK
90570. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__DEVICE_TYPE__SHIFT
90571. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
90572. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
90573. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
90574. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
90575. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__VERSION_MASK
90576. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__VERSION__SHIFT
90577. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
90578. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
90579. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
90580. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
90581. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
90582. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
90583. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
90584. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
90585. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
90586. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
90587. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
90588. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
90589. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
90590. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
90591. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
90592. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
90593. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
90594. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
90595. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
90596. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
90597. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
90598. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
90599. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
90600. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
90601. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
90602. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
90603. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
90604. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
90605. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
90606. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
90607. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
90608. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
90609. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0__TLP_HDR_MASK
90610. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
90611. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1__TLP_HDR_MASK
90612. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
90613. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2__TLP_HDR_MASK
90614. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
90615. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3__TLP_HDR_MASK
90616. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
90617. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
90618. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
90619. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
90620. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
90621. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
90622. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
90623. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
90624. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
90625. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
90626. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
90627. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
90628. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
90629. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
90630. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
90631. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
90632. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
90633. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
90634. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
90635. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
90636. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
90637. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
90638. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
90639. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
90640. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
90641. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
90642. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
90643. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
90644. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
90645. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
90646. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
90647. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
90648. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
90649. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
90650. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
90651. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
90652. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
90653. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
90654. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
90655. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
90656. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
90657. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
90658. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
90659. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
90660. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
90661. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
90662. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
90663. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
90664. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
90665. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
90666. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
90667. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
90668. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
90669. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
90670. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
90671. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
90672. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
90673. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
90674. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
90675. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
90676. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
90677. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
90678. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
90679. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
90680. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
90681. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
90682. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
90683. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
90684. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
90685. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
90686. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
90687. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
90688. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
90689. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
90690. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
90691. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
90692. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
90693. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
90694. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
90695. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
90696. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
90697. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
90698. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
90699. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
90700. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
90701. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
90702. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
90703. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
90704. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
90705. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
90706. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
90707. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
90708. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
90709. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
90710. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
90711. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
90712. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
90713. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
90714. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
90715. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
90716. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
90717. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
90718. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
90719. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
90720. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
90721. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
90722. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
90723. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
90724. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
90725. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
90726. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
90727. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
90728. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
90729. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
90730. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
90731. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
90732. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
90733. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
90734. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
90735. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
90736. BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
90737. BIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE__PROG_INTERFACE_MASK
90738. BIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
90739. BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID__MAJOR_REV_ID_MASK
90740. BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID__MAJOR_REV_ID__SHIFT
90741. BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID__MINOR_REV_ID_MASK
90742. BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID__MINOR_REV_ID__SHIFT
90743. BIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR__BASE_ADDR_MASK
90744. BIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
90745. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__CAP_LIST_MASK
90746. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__CAP_LIST__SHIFT
90747. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__DEVSEL_TIMING_MASK
90748. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__DEVSEL_TIMING__SHIFT
90749. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__FAST_BACK_CAPABLE_MASK
90750. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__FAST_BACK_CAPABLE__SHIFT
90751. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__IMMEDIATE_READINESS_MASK
90752. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__IMMEDIATE_READINESS__SHIFT
90753. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__INT_STATUS_MASK
90754. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__INT_STATUS__SHIFT
90755. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
90756. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
90757. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__PARITY_ERROR_DETECTED_MASK
90758. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
90759. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__PCI_66_CAP_MASK
90760. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__PCI_66_CAP__SHIFT
90761. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__RECEIVED_MASTER_ABORT_MASK
90762. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
90763. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__RECEIVED_TARGET_ABORT_MASK
90764. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
90765. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
90766. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
90767. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__SIGNAL_TARGET_ABORT_MASK
90768. BIF_CFG_DEV0_EPF0_VF16_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
90769. BIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS__SUB_CLASS_MASK
90770. BIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS__SUB_CLASS__SHIFT
90771. BIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID__VENDOR_ID_MASK
90772. BIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID__VENDOR_ID__SHIFT
90773. BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID__SUBSYSTEM_ID_MASK
90774. BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
90775. BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
90776. BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
90777. BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_1__BASE_ADDR_MASK
90778. BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_1__BASE_ADDR__SHIFT
90779. BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_2__BASE_ADDR_MASK
90780. BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_2__BASE_ADDR__SHIFT
90781. BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_3__BASE_ADDR_MASK
90782. BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_3__BASE_ADDR__SHIFT
90783. BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_4__BASE_ADDR_MASK
90784. BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_4__BASE_ADDR__SHIFT
90785. BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_5__BASE_ADDR_MASK
90786. BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_5__BASE_ADDR__SHIFT
90787. BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_6__BASE_ADDR_MASK
90788. BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_6__BASE_ADDR__SHIFT
90789. BIF_CFG_DEV0_EPF0_VF16_BASE_CLASS__BASE_CLASS_MASK
90790. BIF_CFG_DEV0_EPF0_VF16_BASE_CLASS__BASE_CLASS__SHIFT
90791. BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_CAP_MASK
90792. BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_CAP__SHIFT
90793. BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_COMP_MASK
90794. BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_COMP__SHIFT
90795. BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_STRT_MASK
90796. BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_STRT__SHIFT
90797. BIF_CFG_DEV0_EPF0_VF16_CACHE_LINE__CACHE_LINE_SIZE_MASK
90798. BIF_CFG_DEV0_EPF0_VF16_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
90799. BIF_CFG_DEV0_EPF0_VF16_CAP_PTR__CAP_PTR_MASK
90800. BIF_CFG_DEV0_EPF0_VF16_CAP_PTR__CAP_PTR__SHIFT
90801. BIF_CFG_DEV0_EPF0_VF16_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
90802. BIF_CFG_DEV0_EPF0_VF16_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
90803. BIF_CFG_DEV0_EPF0_VF16_COMMAND__AD_STEPPING_MASK
90804. BIF_CFG_DEV0_EPF0_VF16_COMMAND__AD_STEPPING__SHIFT
90805. BIF_CFG_DEV0_EPF0_VF16_COMMAND__BUS_MASTER_EN_MASK
90806. BIF_CFG_DEV0_EPF0_VF16_COMMAND__BUS_MASTER_EN__SHIFT
90807. BIF_CFG_DEV0_EPF0_VF16_COMMAND__FAST_B2B_EN_MASK
90808. BIF_CFG_DEV0_EPF0_VF16_COMMAND__FAST_B2B_EN__SHIFT
90809. BIF_CFG_DEV0_EPF0_VF16_COMMAND__INT_DIS_MASK
90810. BIF_CFG_DEV0_EPF0_VF16_COMMAND__INT_DIS__SHIFT
90811. BIF_CFG_DEV0_EPF0_VF16_COMMAND__IO_ACCESS_EN_MASK
90812. BIF_CFG_DEV0_EPF0_VF16_COMMAND__IO_ACCESS_EN__SHIFT
90813. BIF_CFG_DEV0_EPF0_VF16_COMMAND__MEM_ACCESS_EN_MASK
90814. BIF_CFG_DEV0_EPF0_VF16_COMMAND__MEM_ACCESS_EN__SHIFT
90815. BIF_CFG_DEV0_EPF0_VF16_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
90816. BIF_CFG_DEV0_EPF0_VF16_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
90817. BIF_CFG_DEV0_EPF0_VF16_COMMAND__PAL_SNOOP_EN_MASK
90818. BIF_CFG_DEV0_EPF0_VF16_COMMAND__PAL_SNOOP_EN__SHIFT
90819. BIF_CFG_DEV0_EPF0_VF16_COMMAND__PARITY_ERROR_RESPONSE_MASK
90820. BIF_CFG_DEV0_EPF0_VF16_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
90821. BIF_CFG_DEV0_EPF0_VF16_COMMAND__SERR_EN_MASK
90822. BIF_CFG_DEV0_EPF0_VF16_COMMAND__SERR_EN__SHIFT
90823. BIF_CFG_DEV0_EPF0_VF16_COMMAND__SPECIAL_CYCLE_EN_MASK
90824. BIF_CFG_DEV0_EPF0_VF16_COMMAND__SPECIAL_CYCLE_EN__SHIFT
90825. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
90826. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
90827. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
90828. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
90829. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
90830. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
90831. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
90832. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
90833. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
90834. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
90835. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
90836. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
90837. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
90838. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
90839. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
90840. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
90841. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
90842. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
90843. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
90844. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
90845. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
90846. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
90847. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__FRS_SUPPORTED_MASK
90848. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
90849. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
90850. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
90851. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__LTR_SUPPORTED_MASK
90852. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
90853. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
90854. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
90855. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
90856. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
90857. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__OBFF_SUPPORTED_MASK
90858. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
90859. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
90860. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
90861. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
90862. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
90863. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
90864. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
90865. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
90866. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
90867. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
90868. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
90869. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__EXTENDED_TAG_MASK
90870. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__EXTENDED_TAG__SHIFT
90871. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__FLR_CAPABLE_MASK
90872. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__FLR_CAPABLE__SHIFT
90873. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
90874. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
90875. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
90876. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
90877. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
90878. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
90879. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__PHANTOM_FUNC_MASK
90880. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__PHANTOM_FUNC__SHIFT
90881. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
90882. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
90883. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
90884. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
90885. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
90886. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
90887. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
90888. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
90889. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
90890. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
90891. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
90892. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
90893. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
90894. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
90895. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
90896. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
90897. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
90898. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
90899. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
90900. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
90901. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__LTR_EN_MASK
90902. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__LTR_EN__SHIFT
90903. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__OBFF_EN_MASK
90904. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__OBFF_EN__SHIFT
90905. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
90906. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
90907. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
90908. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
90909. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__CORR_ERR_EN_MASK
90910. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__CORR_ERR_EN__SHIFT
90911. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
90912. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
90913. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__FATAL_ERR_EN_MASK
90914. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
90915. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__INITIATE_FLR_MASK
90916. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__INITIATE_FLR__SHIFT
90917. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
90918. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
90919. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
90920. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
90921. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
90922. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
90923. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__NO_SNOOP_EN_MASK
90924. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
90925. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
90926. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
90927. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__RELAXED_ORD_EN_MASK
90928. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
90929. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__USR_REPORT_EN_MASK
90930. BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__USR_REPORT_EN__SHIFT
90931. BIF_CFG_DEV0_EPF0_VF16_DEVICE_ID__DEVICE_ID_MASK
90932. BIF_CFG_DEV0_EPF0_VF16_DEVICE_ID__DEVICE_ID__SHIFT
90933. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS2__RESERVED_MASK
90934. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS2__RESERVED__SHIFT
90935. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__AUX_PWR_MASK
90936. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__AUX_PWR__SHIFT
90937. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__CORR_ERR_MASK
90938. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__CORR_ERR__SHIFT
90939. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
90940. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
90941. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__FATAL_ERR_MASK
90942. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__FATAL_ERR__SHIFT
90943. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__NON_FATAL_ERR_MASK
90944. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
90945. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
90946. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
90947. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__USR_DETECTED_MASK
90948. BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__USR_DETECTED__SHIFT
90949. BIF_CFG_DEV0_EPF0_VF16_HEADER__DEVICE_TYPE_MASK
90950. BIF_CFG_DEV0_EPF0_VF16_HEADER__DEVICE_TYPE__SHIFT
90951. BIF_CFG_DEV0_EPF0_VF16_HEADER__HEADER_TYPE_MASK
90952. BIF_CFG_DEV0_EPF0_VF16_HEADER__HEADER_TYPE__SHIFT
90953. BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_LINE__INTERRUPT_LINE_MASK
90954. BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
90955. BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_PIN__INTERRUPT_PIN_MASK
90956. BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
90957. BIF_CFG_DEV0_EPF0_VF16_LATENCY__LATENCY_TIMER_MASK
90958. BIF_CFG_DEV0_EPF0_VF16_LATENCY__LATENCY_TIMER__SHIFT
90959. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
90960. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
90961. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
90962. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
90963. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
90964. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
90965. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
90966. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
90967. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
90968. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
90969. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
90970. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
90971. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
90972. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
90973. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
90974. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
90975. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
90976. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
90977. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
90978. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
90979. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__L0S_EXIT_LATENCY_MASK
90980. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
90981. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__L1_EXIT_LATENCY_MASK
90982. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__L1_EXIT_LATENCY__SHIFT
90983. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
90984. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
90985. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_SPEED_MASK
90986. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_SPEED__SHIFT
90987. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_WIDTH_MASK
90988. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_WIDTH__SHIFT
90989. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__PM_SUPPORT_MASK
90990. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__PM_SUPPORT__SHIFT
90991. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__PORT_NUMBER_MASK
90992. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__PORT_NUMBER__SHIFT
90993. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
90994. BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
90995. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
90996. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
90997. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__COMPLIANCE_SOS_MASK
90998. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
90999. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__ENTER_COMPLIANCE_MASK
91000. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
91001. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
91002. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
91003. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
91004. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
91005. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
91006. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
91007. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__TARGET_LINK_SPEED_MASK
91008. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
91009. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__XMIT_MARGIN_MASK
91010. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__XMIT_MARGIN__SHIFT
91011. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
91012. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
91013. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__COMMON_CLOCK_CFG_MASK
91014. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
91015. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
91016. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
91017. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__EXTENDED_SYNC_MASK
91018. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__EXTENDED_SYNC__SHIFT
91019. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
91020. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
91021. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
91022. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
91023. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
91024. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
91025. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_DIS_MASK
91026. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_DIS__SHIFT
91027. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__PM_CONTROL_MASK
91028. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__PM_CONTROL__SHIFT
91029. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__READ_CPL_BOUNDARY_MASK
91030. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
91031. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__RETRAIN_LINK_MASK
91032. BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__RETRAIN_LINK__SHIFT
91033. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
91034. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
91035. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
91036. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
91037. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
91038. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
91039. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
91040. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
91041. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
91042. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
91043. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
91044. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
91045. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
91046. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
91047. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
91048. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
91049. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
91050. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
91051. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
91052. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
91053. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
91054. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
91055. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__CURRENT_LINK_SPEED_MASK
91056. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
91057. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__DL_ACTIVE_MASK
91058. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__DL_ACTIVE__SHIFT
91059. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
91060. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
91061. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
91062. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
91063. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_TRAINING_MASK
91064. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_TRAINING__SHIFT
91065. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
91066. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
91067. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__SLOT_CLOCK_CFG_MASK
91068. BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
91069. BIF_CFG_DEV0_EPF0_VF16_MAX_LATENCY__MAX_LAT_MASK
91070. BIF_CFG_DEV0_EPF0_VF16_MAX_LATENCY__MAX_LAT__SHIFT
91071. BIF_CFG_DEV0_EPF0_VF16_MIN_GRANT__MIN_GNT_MASK
91072. BIF_CFG_DEV0_EPF0_VF16_MIN_GRANT__MIN_GNT__SHIFT
91073. BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST__CAP_ID_MASK
91074. BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST__CAP_ID__SHIFT
91075. BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST__NEXT_PTR_MASK
91076. BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST__NEXT_PTR__SHIFT
91077. BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_EN_MASK
91078. BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_EN__SHIFT
91079. BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
91080. BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
91081. BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
91082. BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
91083. BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA__MSIX_PBA_BIR_MASK
91084. BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA__MSIX_PBA_BIR__SHIFT
91085. BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA__MSIX_PBA_OFFSET_MASK
91086. BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
91087. BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE__MSIX_TABLE_BIR_MASK
91088. BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
91089. BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
91090. BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
91091. BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST__CAP_ID_MASK
91092. BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST__CAP_ID__SHIFT
91093. BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST__NEXT_PTR_MASK
91094. BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST__NEXT_PTR__SHIFT
91095. BIF_CFG_DEV0_EPF0_VF16_MSI_MASK_64__MSI_MASK_64_MASK
91096. BIF_CFG_DEV0_EPF0_VF16_MSI_MASK_64__MSI_MASK_64__SHIFT
91097. BIF_CFG_DEV0_EPF0_VF16_MSI_MASK__MSI_MASK_MASK
91098. BIF_CFG_DEV0_EPF0_VF16_MSI_MASK__MSI_MASK__SHIFT
91099. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
91100. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
91101. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
91102. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
91103. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_64BIT_MASK
91104. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_64BIT__SHIFT
91105. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_EN_MASK
91106. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_EN__SHIFT
91107. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
91108. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
91109. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
91110. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
91111. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
91112. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
91113. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA_64__MSI_DATA_64_MASK
91114. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
91115. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA__MSI_DATA_MASK
91116. BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA__MSI_DATA__SHIFT
91117. BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING_64__MSI_PENDING_64_MASK
91118. BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING_64__MSI_PENDING_64__SHIFT
91119. BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING__MSI_PENDING_MASK
91120. BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING__MSI_PENDING__SHIFT
91121. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
91122. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
91123. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
91124. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
91125. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
91126. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
91127. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
91128. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
91129. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
91130. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
91131. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
91132. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
91133. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
91134. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
91135. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
91136. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
91137. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
91138. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
91139. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
91140. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
91141. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
91142. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
91143. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
91144. BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
91145. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
91146. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
91147. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
91148. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
91149. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
91150. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
91151. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
91152. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
91153. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
91154. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
91155. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
91156. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
91157. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
91158. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
91159. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
91160. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
91161. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
91162. BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
91163. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
91164. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
91165. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
91166. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
91167. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
91168. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
91169. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL__ATC_ENABLE_MASK
91170. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
91171. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL__STU_MASK
91172. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL__STU__SHIFT
91173. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
91174. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
91175. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
91176. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
91177. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
91178. BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
91179. BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST__CAP_ID_MASK
91180. BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST__CAP_ID__SHIFT
91181. BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST__NEXT_PTR_MASK
91182. BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST__NEXT_PTR__SHIFT
91183. BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__DEVICE_TYPE_MASK
91184. BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__DEVICE_TYPE__SHIFT
91185. BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__INT_MESSAGE_NUM_MASK
91186. BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
91187. BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__SLOT_IMPLEMENTED_MASK
91188. BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
91189. BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__VERSION_MASK
91190. BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__VERSION__SHIFT
91191. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
91192. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
91193. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
91194. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
91195. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
91196. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
91197. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
91198. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
91199. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
91200. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
91201. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
91202. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
91203. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
91204. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
91205. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
91206. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
91207. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
91208. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
91209. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
91210. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
91211. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
91212. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
91213. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
91214. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
91215. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
91216. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
91217. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
91218. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
91219. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
91220. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
91221. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
91222. BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
91223. BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG0__TLP_HDR_MASK
91224. BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG0__TLP_HDR__SHIFT
91225. BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG1__TLP_HDR_MASK
91226. BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG1__TLP_HDR__SHIFT
91227. BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG2__TLP_HDR_MASK
91228. BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG2__TLP_HDR__SHIFT
91229. BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG3__TLP_HDR_MASK
91230. BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG3__TLP_HDR__SHIFT
91231. BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
91232. BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
91233. BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
91234. BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
91235. BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
91236. BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
91237. BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
91238. BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
91239. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
91240. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
91241. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
91242. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
91243. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
91244. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
91245. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
91246. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
91247. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
91248. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
91249. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
91250. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
91251. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
91252. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
91253. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
91254. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
91255. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
91256. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
91257. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
91258. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
91259. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
91260. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
91261. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
91262. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
91263. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
91264. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
91265. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
91266. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
91267. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
91268. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
91269. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
91270. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
91271. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
91272. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
91273. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
91274. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
91275. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
91276. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
91277. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
91278. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
91279. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
91280. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
91281. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
91282. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
91283. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
91284. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
91285. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
91286. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
91287. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
91288. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
91289. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
91290. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
91291. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
91292. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
91293. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
91294. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
91295. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
91296. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
91297. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
91298. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
91299. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
91300. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
91301. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
91302. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
91303. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
91304. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
91305. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
91306. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
91307. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
91308. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
91309. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
91310. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
91311. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
91312. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
91313. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
91314. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
91315. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
91316. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
91317. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
91318. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
91319. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
91320. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
91321. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
91322. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
91323. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
91324. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
91325. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
91326. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
91327. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
91328. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
91329. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
91330. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
91331. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
91332. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
91333. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
91334. BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
91335. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
91336. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
91337. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
91338. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
91339. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
91340. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
91341. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
91342. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
91343. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
91344. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
91345. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
91346. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
91347. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
91348. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
91349. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
91350. BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
91351. BIF_CFG_DEV0_EPF0_VF16_PROG_INTERFACE__PROG_INTERFACE_MASK
91352. BIF_CFG_DEV0_EPF0_VF16_PROG_INTERFACE__PROG_INTERFACE__SHIFT
91353. BIF_CFG_DEV0_EPF0_VF16_REVISION_ID__MAJOR_REV_ID_MASK
91354. BIF_CFG_DEV0_EPF0_VF16_REVISION_ID__MAJOR_REV_ID__SHIFT
91355. BIF_CFG_DEV0_EPF0_VF16_REVISION_ID__MINOR_REV_ID_MASK
91356. BIF_CFG_DEV0_EPF0_VF16_REVISION_ID__MINOR_REV_ID__SHIFT
91357. BIF_CFG_DEV0_EPF0_VF16_ROM_BASE_ADDR__BASE_ADDR_MASK
91358. BIF_CFG_DEV0_EPF0_VF16_ROM_BASE_ADDR__BASE_ADDR__SHIFT
91359. BIF_CFG_DEV0_EPF0_VF16_STATUS__CAP_LIST_MASK
91360. BIF_CFG_DEV0_EPF0_VF16_STATUS__CAP_LIST__SHIFT
91361. BIF_CFG_DEV0_EPF0_VF16_STATUS__DEVSEL_TIMING_MASK
91362. BIF_CFG_DEV0_EPF0_VF16_STATUS__DEVSEL_TIMING__SHIFT
91363. BIF_CFG_DEV0_EPF0_VF16_STATUS__FAST_BACK_CAPABLE_MASK
91364. BIF_CFG_DEV0_EPF0_VF16_STATUS__FAST_BACK_CAPABLE__SHIFT
91365. BIF_CFG_DEV0_EPF0_VF16_STATUS__IMMEDIATE_READINESS_MASK
91366. BIF_CFG_DEV0_EPF0_VF16_STATUS__IMMEDIATE_READINESS__SHIFT
91367. BIF_CFG_DEV0_EPF0_VF16_STATUS__INT_STATUS_MASK
91368. BIF_CFG_DEV0_EPF0_VF16_STATUS__INT_STATUS__SHIFT
91369. BIF_CFG_DEV0_EPF0_VF16_STATUS__MASTER_DATA_PARITY_ERROR_MASK
91370. BIF_CFG_DEV0_EPF0_VF16_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
91371. BIF_CFG_DEV0_EPF0_VF16_STATUS__PARITY_ERROR_DETECTED_MASK
91372. BIF_CFG_DEV0_EPF0_VF16_STATUS__PARITY_ERROR_DETECTED__SHIFT
91373. BIF_CFG_DEV0_EPF0_VF16_STATUS__PCI_66_CAP_MASK
91374. BIF_CFG_DEV0_EPF0_VF16_STATUS__PCI_66_CAP__SHIFT
91375. BIF_CFG_DEV0_EPF0_VF16_STATUS__RECEIVED_MASTER_ABORT_MASK
91376. BIF_CFG_DEV0_EPF0_VF16_STATUS__RECEIVED_MASTER_ABORT__SHIFT
91377. BIF_CFG_DEV0_EPF0_VF16_STATUS__RECEIVED_TARGET_ABORT_MASK
91378. BIF_CFG_DEV0_EPF0_VF16_STATUS__RECEIVED_TARGET_ABORT__SHIFT
91379. BIF_CFG_DEV0_EPF0_VF16_STATUS__SIGNALED_SYSTEM_ERROR_MASK
91380. BIF_CFG_DEV0_EPF0_VF16_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
91381. BIF_CFG_DEV0_EPF0_VF16_STATUS__SIGNAL_TARGET_ABORT_MASK
91382. BIF_CFG_DEV0_EPF0_VF16_STATUS__SIGNAL_TARGET_ABORT__SHIFT
91383. BIF_CFG_DEV0_EPF0_VF16_SUB_CLASS__SUB_CLASS_MASK
91384. BIF_CFG_DEV0_EPF0_VF16_SUB_CLASS__SUB_CLASS__SHIFT
91385. BIF_CFG_DEV0_EPF0_VF16_VENDOR_ID__VENDOR_ID_MASK
91386. BIF_CFG_DEV0_EPF0_VF16_VENDOR_ID__VENDOR_ID__SHIFT
91387. BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
91388. BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
91389. BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
91390. BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
91391. BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1__BASE_ADDR_MASK
91392. BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1__BASE_ADDR__SHIFT
91393. BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2__BASE_ADDR_MASK
91394. BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2__BASE_ADDR__SHIFT
91395. BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3__BASE_ADDR_MASK
91396. BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3__BASE_ADDR__SHIFT
91397. BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4__BASE_ADDR_MASK
91398. BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4__BASE_ADDR__SHIFT
91399. BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5__BASE_ADDR_MASK
91400. BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5__BASE_ADDR__SHIFT
91401. BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6__BASE_ADDR_MASK
91402. BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6__BASE_ADDR__SHIFT
91403. BIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS__BASE_CLASS_MASK
91404. BIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS__BASE_CLASS__SHIFT
91405. BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_CAP_MASK
91406. BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_CAP__SHIFT
91407. BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_COMP_MASK
91408. BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_COMP__SHIFT
91409. BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_STRT_MASK
91410. BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_STRT__SHIFT
91411. BIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
91412. BIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
91413. BIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR__CAP_PTR_MASK
91414. BIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR__CAP_PTR__SHIFT
91415. BIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
91416. BIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
91417. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__AD_STEPPING_MASK
91418. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__AD_STEPPING__SHIFT
91419. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__BUS_MASTER_EN_MASK
91420. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__BUS_MASTER_EN__SHIFT
91421. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__FAST_B2B_EN_MASK
91422. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__FAST_B2B_EN__SHIFT
91423. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__INT_DIS_MASK
91424. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__INT_DIS__SHIFT
91425. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__IO_ACCESS_EN_MASK
91426. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__IO_ACCESS_EN__SHIFT
91427. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__MEM_ACCESS_EN_MASK
91428. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__MEM_ACCESS_EN__SHIFT
91429. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
91430. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
91431. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__PAL_SNOOP_EN_MASK
91432. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__PAL_SNOOP_EN__SHIFT
91433. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
91434. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
91435. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__SERR_EN_MASK
91436. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__SERR_EN__SHIFT
91437. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__SPECIAL_CYCLE_EN_MASK
91438. BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
91439. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
91440. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
91441. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
91442. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
91443. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
91444. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
91445. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
91446. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
91447. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
91448. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
91449. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
91450. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
91451. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
91452. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
91453. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
91454. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
91455. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
91456. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
91457. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
91458. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
91459. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
91460. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
91461. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
91462. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
91463. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
91464. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
91465. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
91466. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
91467. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
91468. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
91469. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
91470. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
91471. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
91472. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
91473. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
91474. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
91475. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
91476. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
91477. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
91478. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
91479. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
91480. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
91481. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
91482. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
91483. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__EXTENDED_TAG_MASK
91484. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
91485. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__FLR_CAPABLE_MASK
91486. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
91487. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
91488. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
91489. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
91490. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
91491. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
91492. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
91493. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__PHANTOM_FUNC_MASK
91494. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
91495. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
91496. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
91497. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
91498. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
91499. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
91500. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
91501. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
91502. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
91503. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
91504. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
91505. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
91506. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
91507. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
91508. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
91509. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
91510. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
91511. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
91512. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
91513. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
91514. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
91515. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__LTR_EN_MASK
91516. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__LTR_EN__SHIFT
91517. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__OBFF_EN_MASK
91518. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__OBFF_EN__SHIFT
91519. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
91520. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
91521. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
91522. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
91523. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__CORR_ERR_EN_MASK
91524. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
91525. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
91526. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
91527. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
91528. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
91529. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__INITIATE_FLR_MASK
91530. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
91531. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
91532. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
91533. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
91534. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
91535. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
91536. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
91537. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
91538. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
91539. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
91540. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
91541. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
91542. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
91543. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__USR_REPORT_EN_MASK
91544. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
91545. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID__DEVICE_ID_MASK
91546. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID__DEVICE_ID__SHIFT
91547. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2__RESERVED_MASK
91548. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2__RESERVED__SHIFT
91549. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__AUX_PWR_MASK
91550. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__AUX_PWR__SHIFT
91551. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__CORR_ERR_MASK
91552. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__CORR_ERR__SHIFT
91553. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
91554. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
91555. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__FATAL_ERR_MASK
91556. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__FATAL_ERR__SHIFT
91557. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
91558. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
91559. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
91560. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
91561. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__USR_DETECTED_MASK
91562. BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__USR_DETECTED__SHIFT
91563. BIF_CFG_DEV0_EPF0_VF17_0_HEADER__DEVICE_TYPE_MASK
91564. BIF_CFG_DEV0_EPF0_VF17_0_HEADER__DEVICE_TYPE__SHIFT
91565. BIF_CFG_DEV0_EPF0_VF17_0_HEADER__HEADER_TYPE_MASK
91566. BIF_CFG_DEV0_EPF0_VF17_0_HEADER__HEADER_TYPE__SHIFT
91567. BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
91568. BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
91569. BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
91570. BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
91571. BIF_CFG_DEV0_EPF0_VF17_0_LATENCY__LATENCY_TIMER_MASK
91572. BIF_CFG_DEV0_EPF0_VF17_0_LATENCY__LATENCY_TIMER__SHIFT
91573. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
91574. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
91575. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
91576. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
91577. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
91578. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
91579. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
91580. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
91581. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
91582. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
91583. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
91584. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
91585. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
91586. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
91587. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
91588. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
91589. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
91590. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
91591. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
91592. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
91593. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
91594. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
91595. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__L1_EXIT_LATENCY_MASK
91596. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
91597. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
91598. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
91599. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_SPEED_MASK
91600. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_SPEED__SHIFT
91601. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_WIDTH_MASK
91602. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_WIDTH__SHIFT
91603. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__PM_SUPPORT_MASK
91604. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__PM_SUPPORT__SHIFT
91605. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__PORT_NUMBER_MASK
91606. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__PORT_NUMBER__SHIFT
91607. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
91608. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
91609. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
91610. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
91611. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
91612. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
91613. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
91614. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
91615. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
91616. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
91617. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
91618. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
91619. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
91620. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
91621. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
91622. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
91623. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__XMIT_MARGIN_MASK
91624. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
91625. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
91626. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
91627. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
91628. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
91629. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
91630. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
91631. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__EXTENDED_SYNC_MASK
91632. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
91633. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
91634. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
91635. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
91636. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
91637. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
91638. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
91639. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_DIS_MASK
91640. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_DIS__SHIFT
91641. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__PM_CONTROL_MASK
91642. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__PM_CONTROL__SHIFT
91643. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
91644. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
91645. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__RETRAIN_LINK_MASK
91646. BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__RETRAIN_LINK__SHIFT
91647. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
91648. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
91649. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
91650. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
91651. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
91652. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
91653. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
91654. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
91655. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
91656. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
91657. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
91658. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
91659. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
91660. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
91661. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
91662. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
91663. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
91664. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
91665. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
91666. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
91667. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
91668. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
91669. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
91670. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
91671. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__DL_ACTIVE_MASK
91672. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__DL_ACTIVE__SHIFT
91673. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
91674. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
91675. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
91676. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
91677. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_TRAINING_MASK
91678. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_TRAINING__SHIFT
91679. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
91680. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
91681. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
91682. BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
91683. BIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY__MAX_LAT_MASK
91684. BIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY__MAX_LAT__SHIFT
91685. BIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT__MIN_GNT_MASK
91686. BIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT__MIN_GNT__SHIFT
91687. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST__CAP_ID_MASK
91688. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST__CAP_ID__SHIFT
91689. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST__NEXT_PTR_MASK
91690. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
91691. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_EN_MASK
91692. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
91693. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
91694. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
91695. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
91696. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
91697. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA__MSIX_PBA_BIR_MASK
91698. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
91699. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
91700. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
91701. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
91702. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
91703. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
91704. BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
91705. BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST__CAP_ID_MASK
91706. BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST__CAP_ID__SHIFT
91707. BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST__NEXT_PTR_MASK
91708. BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
91709. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64__MSI_MASK_64_MASK
91710. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64__MSI_MASK_64__SHIFT
91711. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK__MSI_MASK_MASK
91712. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK__MSI_MASK__SHIFT
91713. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
91714. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
91715. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
91716. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
91717. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_64BIT_MASK
91718. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
91719. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_EN_MASK
91720. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_EN__SHIFT
91721. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
91722. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
91723. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
91724. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
91725. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
91726. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
91727. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
91728. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
91729. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA__MSI_DATA_MASK
91730. BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA__MSI_DATA__SHIFT
91731. BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64__MSI_PENDING_64_MASK
91732. BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
91733. BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING__MSI_PENDING_MASK
91734. BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING__MSI_PENDING__SHIFT
91735. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
91736. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
91737. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
91738. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
91739. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
91740. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
91741. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
91742. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
91743. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
91744. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
91745. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
91746. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
91747. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
91748. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
91749. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
91750. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
91751. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
91752. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
91753. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
91754. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
91755. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
91756. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
91757. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
91758. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
91759. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
91760. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
91761. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
91762. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
91763. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
91764. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
91765. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
91766. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
91767. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
91768. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
91769. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
91770. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
91771. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
91772. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
91773. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
91774. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
91775. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
91776. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
91777. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
91778. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
91779. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
91780. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
91781. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
91782. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
91783. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
91784. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
91785. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL__STU_MASK
91786. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL__STU__SHIFT
91787. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
91788. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
91789. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
91790. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
91791. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
91792. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
91793. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST__CAP_ID_MASK
91794. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST__CAP_ID__SHIFT
91795. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST__NEXT_PTR_MASK
91796. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
91797. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__DEVICE_TYPE_MASK
91798. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__DEVICE_TYPE__SHIFT
91799. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
91800. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
91801. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
91802. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
91803. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__VERSION_MASK
91804. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__VERSION__SHIFT
91805. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
91806. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
91807. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
91808. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
91809. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
91810. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
91811. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
91812. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
91813. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
91814. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
91815. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
91816. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
91817. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
91818. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
91819. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
91820. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
91821. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
91822. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
91823. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
91824. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
91825. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
91826. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
91827. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
91828. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
91829. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
91830. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
91831. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
91832. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
91833. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
91834. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
91835. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
91836. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
91837. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0__TLP_HDR_MASK
91838. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
91839. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1__TLP_HDR_MASK
91840. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
91841. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2__TLP_HDR_MASK
91842. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
91843. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3__TLP_HDR_MASK
91844. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
91845. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
91846. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
91847. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
91848. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
91849. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
91850. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
91851. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
91852. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
91853. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
91854. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
91855. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
91856. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
91857. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
91858. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
91859. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
91860. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
91861. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
91862. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
91863. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
91864. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
91865. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
91866. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
91867. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
91868. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
91869. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
91870. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
91871. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
91872. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
91873. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
91874. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
91875. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
91876. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
91877. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
91878. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
91879. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
91880. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
91881. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
91882. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
91883. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
91884. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
91885. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
91886. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
91887. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
91888. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
91889. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
91890. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
91891. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
91892. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
91893. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
91894. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
91895. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
91896. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
91897. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
91898. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
91899. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
91900. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
91901. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
91902. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
91903. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
91904. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
91905. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
91906. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
91907. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
91908. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
91909. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
91910. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
91911. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
91912. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
91913. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
91914. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
91915. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
91916. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
91917. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
91918. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
91919. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
91920. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
91921. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
91922. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
91923. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
91924. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
91925. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
91926. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
91927. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
91928. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
91929. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
91930. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
91931. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
91932. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
91933. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
91934. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
91935. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
91936. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
91937. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
91938. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
91939. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
91940. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
91941. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
91942. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
91943. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
91944. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
91945. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
91946. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
91947. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
91948. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
91949. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
91950. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
91951. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
91952. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
91953. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
91954. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
91955. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
91956. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
91957. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
91958. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
91959. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
91960. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
91961. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
91962. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
91963. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
91964. BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
91965. BIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE__PROG_INTERFACE_MASK
91966. BIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
91967. BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID__MAJOR_REV_ID_MASK
91968. BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID__MAJOR_REV_ID__SHIFT
91969. BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID__MINOR_REV_ID_MASK
91970. BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID__MINOR_REV_ID__SHIFT
91971. BIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR__BASE_ADDR_MASK
91972. BIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
91973. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__CAP_LIST_MASK
91974. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__CAP_LIST__SHIFT
91975. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__DEVSEL_TIMING_MASK
91976. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__DEVSEL_TIMING__SHIFT
91977. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__FAST_BACK_CAPABLE_MASK
91978. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__FAST_BACK_CAPABLE__SHIFT
91979. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__IMMEDIATE_READINESS_MASK
91980. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__IMMEDIATE_READINESS__SHIFT
91981. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__INT_STATUS_MASK
91982. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__INT_STATUS__SHIFT
91983. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
91984. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
91985. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__PARITY_ERROR_DETECTED_MASK
91986. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
91987. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__PCI_66_CAP_MASK
91988. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__PCI_66_CAP__SHIFT
91989. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__RECEIVED_MASTER_ABORT_MASK
91990. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
91991. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__RECEIVED_TARGET_ABORT_MASK
91992. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
91993. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
91994. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
91995. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__SIGNAL_TARGET_ABORT_MASK
91996. BIF_CFG_DEV0_EPF0_VF17_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
91997. BIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS__SUB_CLASS_MASK
91998. BIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS__SUB_CLASS__SHIFT
91999. BIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID__VENDOR_ID_MASK
92000. BIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID__VENDOR_ID__SHIFT
92001. BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
92002. BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
92003. BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
92004. BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
92005. BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1__BASE_ADDR_MASK
92006. BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1__BASE_ADDR__SHIFT
92007. BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2__BASE_ADDR_MASK
92008. BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2__BASE_ADDR__SHIFT
92009. BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3__BASE_ADDR_MASK
92010. BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3__BASE_ADDR__SHIFT
92011. BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4__BASE_ADDR_MASK
92012. BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4__BASE_ADDR__SHIFT
92013. BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5__BASE_ADDR_MASK
92014. BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5__BASE_ADDR__SHIFT
92015. BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6__BASE_ADDR_MASK
92016. BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6__BASE_ADDR__SHIFT
92017. BIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS__BASE_CLASS_MASK
92018. BIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS__BASE_CLASS__SHIFT
92019. BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_CAP_MASK
92020. BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_CAP__SHIFT
92021. BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_COMP_MASK
92022. BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_COMP__SHIFT
92023. BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_STRT_MASK
92024. BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_STRT__SHIFT
92025. BIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
92026. BIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
92027. BIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR__CAP_PTR_MASK
92028. BIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR__CAP_PTR__SHIFT
92029. BIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
92030. BIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
92031. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__AD_STEPPING_MASK
92032. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__AD_STEPPING__SHIFT
92033. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__BUS_MASTER_EN_MASK
92034. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__BUS_MASTER_EN__SHIFT
92035. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__FAST_B2B_EN_MASK
92036. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__FAST_B2B_EN__SHIFT
92037. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__INT_DIS_MASK
92038. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__INT_DIS__SHIFT
92039. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__IO_ACCESS_EN_MASK
92040. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__IO_ACCESS_EN__SHIFT
92041. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__MEM_ACCESS_EN_MASK
92042. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__MEM_ACCESS_EN__SHIFT
92043. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
92044. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
92045. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__PAL_SNOOP_EN_MASK
92046. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__PAL_SNOOP_EN__SHIFT
92047. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
92048. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
92049. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__SERR_EN_MASK
92050. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__SERR_EN__SHIFT
92051. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__SPECIAL_CYCLE_EN_MASK
92052. BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
92053. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
92054. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
92055. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
92056. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
92057. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
92058. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
92059. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
92060. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
92061. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
92062. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
92063. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
92064. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
92065. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
92066. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
92067. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
92068. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
92069. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
92070. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
92071. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
92072. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
92073. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
92074. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
92075. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
92076. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
92077. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
92078. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
92079. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
92080. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
92081. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
92082. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
92083. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
92084. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
92085. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
92086. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
92087. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
92088. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
92089. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
92090. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
92091. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
92092. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
92093. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
92094. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
92095. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
92096. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
92097. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__EXTENDED_TAG_MASK
92098. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
92099. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__FLR_CAPABLE_MASK
92100. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
92101. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
92102. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
92103. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
92104. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
92105. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
92106. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
92107. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__PHANTOM_FUNC_MASK
92108. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
92109. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
92110. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
92111. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
92112. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
92113. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
92114. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
92115. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
92116. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
92117. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
92118. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
92119. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
92120. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
92121. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
92122. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
92123. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
92124. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
92125. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
92126. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
92127. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
92128. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
92129. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__LTR_EN_MASK
92130. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__LTR_EN__SHIFT
92131. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__OBFF_EN_MASK
92132. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__OBFF_EN__SHIFT
92133. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
92134. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
92135. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
92136. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
92137. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__CORR_ERR_EN_MASK
92138. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
92139. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
92140. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
92141. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
92142. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
92143. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__INITIATE_FLR_MASK
92144. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
92145. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
92146. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
92147. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
92148. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
92149. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
92150. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
92151. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
92152. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
92153. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
92154. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
92155. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
92156. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
92157. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__USR_REPORT_EN_MASK
92158. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
92159. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID__DEVICE_ID_MASK
92160. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID__DEVICE_ID__SHIFT
92161. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2__RESERVED_MASK
92162. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2__RESERVED__SHIFT
92163. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__AUX_PWR_MASK
92164. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__AUX_PWR__SHIFT
92165. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__CORR_ERR_MASK
92166. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__CORR_ERR__SHIFT
92167. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
92168. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
92169. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__FATAL_ERR_MASK
92170. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__FATAL_ERR__SHIFT
92171. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
92172. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
92173. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
92174. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
92175. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__USR_DETECTED_MASK
92176. BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__USR_DETECTED__SHIFT
92177. BIF_CFG_DEV0_EPF0_VF17_1_HEADER__DEVICE_TYPE_MASK
92178. BIF_CFG_DEV0_EPF0_VF17_1_HEADER__DEVICE_TYPE__SHIFT
92179. BIF_CFG_DEV0_EPF0_VF17_1_HEADER__HEADER_TYPE_MASK
92180. BIF_CFG_DEV0_EPF0_VF17_1_HEADER__HEADER_TYPE__SHIFT
92181. BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
92182. BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
92183. BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
92184. BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
92185. BIF_CFG_DEV0_EPF0_VF17_1_LATENCY__LATENCY_TIMER_MASK
92186. BIF_CFG_DEV0_EPF0_VF17_1_LATENCY__LATENCY_TIMER__SHIFT
92187. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
92188. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
92189. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
92190. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
92191. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
92192. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
92193. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
92194. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
92195. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
92196. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
92197. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
92198. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
92199. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
92200. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
92201. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
92202. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
92203. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
92204. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
92205. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
92206. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
92207. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
92208. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
92209. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__L1_EXIT_LATENCY_MASK
92210. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
92211. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
92212. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
92213. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_SPEED_MASK
92214. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_SPEED__SHIFT
92215. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_WIDTH_MASK
92216. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_WIDTH__SHIFT
92217. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__PM_SUPPORT_MASK
92218. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__PM_SUPPORT__SHIFT
92219. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__PORT_NUMBER_MASK
92220. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__PORT_NUMBER__SHIFT
92221. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
92222. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
92223. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
92224. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
92225. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
92226. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
92227. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
92228. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
92229. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
92230. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
92231. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
92232. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
92233. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
92234. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
92235. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
92236. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
92237. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__XMIT_MARGIN_MASK
92238. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
92239. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
92240. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
92241. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
92242. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
92243. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
92244. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
92245. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__EXTENDED_SYNC_MASK
92246. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
92247. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
92248. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
92249. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
92250. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
92251. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
92252. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
92253. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_DIS_MASK
92254. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_DIS__SHIFT
92255. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__PM_CONTROL_MASK
92256. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__PM_CONTROL__SHIFT
92257. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
92258. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
92259. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__RETRAIN_LINK_MASK
92260. BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__RETRAIN_LINK__SHIFT
92261. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
92262. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
92263. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
92264. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
92265. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
92266. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
92267. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
92268. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
92269. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
92270. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
92271. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
92272. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
92273. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
92274. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
92275. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
92276. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
92277. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
92278. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
92279. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
92280. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
92281. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
92282. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
92283. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
92284. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
92285. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__DL_ACTIVE_MASK
92286. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__DL_ACTIVE__SHIFT
92287. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
92288. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
92289. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
92290. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
92291. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_TRAINING_MASK
92292. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_TRAINING__SHIFT
92293. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
92294. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
92295. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
92296. BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
92297. BIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY__MAX_LAT_MASK
92298. BIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY__MAX_LAT__SHIFT
92299. BIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT__MIN_GNT_MASK
92300. BIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT__MIN_GNT__SHIFT
92301. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST__CAP_ID_MASK
92302. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST__CAP_ID__SHIFT
92303. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST__NEXT_PTR_MASK
92304. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
92305. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_EN_MASK
92306. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
92307. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
92308. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
92309. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
92310. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
92311. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA__MSIX_PBA_BIR_MASK
92312. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
92313. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
92314. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
92315. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
92316. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
92317. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
92318. BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
92319. BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST__CAP_ID_MASK
92320. BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST__CAP_ID__SHIFT
92321. BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST__NEXT_PTR_MASK
92322. BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
92323. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64__MSI_MASK_64_MASK
92324. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64__MSI_MASK_64__SHIFT
92325. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK__MSI_MASK_MASK
92326. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK__MSI_MASK__SHIFT
92327. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
92328. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
92329. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
92330. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
92331. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_64BIT_MASK
92332. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
92333. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_EN_MASK
92334. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_EN__SHIFT
92335. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
92336. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
92337. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
92338. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
92339. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
92340. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
92341. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
92342. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
92343. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA__MSI_DATA_MASK
92344. BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA__MSI_DATA__SHIFT
92345. BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64__MSI_PENDING_64_MASK
92346. BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
92347. BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING__MSI_PENDING_MASK
92348. BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING__MSI_PENDING__SHIFT
92349. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
92350. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
92351. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
92352. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
92353. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
92354. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
92355. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
92356. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
92357. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
92358. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
92359. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
92360. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
92361. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
92362. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
92363. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
92364. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
92365. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
92366. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
92367. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
92368. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
92369. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
92370. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
92371. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
92372. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
92373. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
92374. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
92375. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
92376. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
92377. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
92378. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
92379. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
92380. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
92381. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
92382. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
92383. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
92384. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
92385. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
92386. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
92387. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
92388. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
92389. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
92390. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
92391. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
92392. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
92393. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
92394. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
92395. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
92396. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
92397. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
92398. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
92399. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL__STU_MASK
92400. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL__STU__SHIFT
92401. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
92402. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
92403. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
92404. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
92405. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
92406. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
92407. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST__CAP_ID_MASK
92408. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST__CAP_ID__SHIFT
92409. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST__NEXT_PTR_MASK
92410. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
92411. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__DEVICE_TYPE_MASK
92412. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__DEVICE_TYPE__SHIFT
92413. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
92414. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
92415. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
92416. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
92417. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__VERSION_MASK
92418. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__VERSION__SHIFT
92419. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
92420. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
92421. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
92422. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
92423. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
92424. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
92425. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
92426. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
92427. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
92428. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
92429. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
92430. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
92431. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
92432. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
92433. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
92434. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
92435. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
92436. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
92437. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
92438. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
92439. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
92440. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
92441. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
92442. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
92443. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
92444. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
92445. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
92446. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
92447. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
92448. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
92449. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
92450. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
92451. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0__TLP_HDR_MASK
92452. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
92453. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1__TLP_HDR_MASK
92454. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
92455. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2__TLP_HDR_MASK
92456. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
92457. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3__TLP_HDR_MASK
92458. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
92459. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
92460. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
92461. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
92462. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
92463. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
92464. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
92465. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
92466. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
92467. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
92468. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
92469. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
92470. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
92471. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
92472. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
92473. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
92474. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
92475. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
92476. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
92477. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
92478. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
92479. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
92480. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
92481. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
92482. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
92483. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
92484. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
92485. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
92486. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
92487. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
92488. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
92489. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
92490. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
92491. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
92492. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
92493. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
92494. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
92495. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
92496. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
92497. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
92498. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
92499. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
92500. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
92501. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
92502. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
92503. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
92504. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
92505. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
92506. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
92507. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
92508. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
92509. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
92510. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
92511. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
92512. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
92513. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
92514. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
92515. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
92516. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
92517. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
92518. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
92519. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
92520. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
92521. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
92522. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
92523. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
92524. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
92525. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
92526. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
92527. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
92528. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
92529. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
92530. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
92531. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
92532. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
92533. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
92534. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
92535. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
92536. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
92537. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
92538. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
92539. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
92540. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
92541. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
92542. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
92543. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
92544. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
92545. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
92546. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
92547. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
92548. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
92549. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
92550. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
92551. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
92552. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
92553. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
92554. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
92555. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
92556. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
92557. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
92558. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
92559. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
92560. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
92561. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
92562. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
92563. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
92564. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
92565. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
92566. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
92567. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
92568. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
92569. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
92570. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
92571. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
92572. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
92573. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
92574. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
92575. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
92576. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
92577. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
92578. BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
92579. BIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE__PROG_INTERFACE_MASK
92580. BIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
92581. BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID__MAJOR_REV_ID_MASK
92582. BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID__MAJOR_REV_ID__SHIFT
92583. BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID__MINOR_REV_ID_MASK
92584. BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID__MINOR_REV_ID__SHIFT
92585. BIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR__BASE_ADDR_MASK
92586. BIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
92587. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__CAP_LIST_MASK
92588. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__CAP_LIST__SHIFT
92589. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__DEVSEL_TIMING_MASK
92590. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__DEVSEL_TIMING__SHIFT
92591. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__FAST_BACK_CAPABLE_MASK
92592. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__FAST_BACK_CAPABLE__SHIFT
92593. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__IMMEDIATE_READINESS_MASK
92594. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__IMMEDIATE_READINESS__SHIFT
92595. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__INT_STATUS_MASK
92596. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__INT_STATUS__SHIFT
92597. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
92598. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
92599. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__PARITY_ERROR_DETECTED_MASK
92600. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
92601. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__PCI_66_CAP_MASK
92602. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__PCI_66_CAP__SHIFT
92603. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__RECEIVED_MASTER_ABORT_MASK
92604. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
92605. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__RECEIVED_TARGET_ABORT_MASK
92606. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
92607. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
92608. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
92609. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__SIGNAL_TARGET_ABORT_MASK
92610. BIF_CFG_DEV0_EPF0_VF17_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
92611. BIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS__SUB_CLASS_MASK
92612. BIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS__SUB_CLASS__SHIFT
92613. BIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID__VENDOR_ID_MASK
92614. BIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID__VENDOR_ID__SHIFT
92615. BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID__SUBSYSTEM_ID_MASK
92616. BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
92617. BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
92618. BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
92619. BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_1__BASE_ADDR_MASK
92620. BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_1__BASE_ADDR__SHIFT
92621. BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_2__BASE_ADDR_MASK
92622. BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_2__BASE_ADDR__SHIFT
92623. BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_3__BASE_ADDR_MASK
92624. BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_3__BASE_ADDR__SHIFT
92625. BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_4__BASE_ADDR_MASK
92626. BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_4__BASE_ADDR__SHIFT
92627. BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_5__BASE_ADDR_MASK
92628. BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_5__BASE_ADDR__SHIFT
92629. BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_6__BASE_ADDR_MASK
92630. BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_6__BASE_ADDR__SHIFT
92631. BIF_CFG_DEV0_EPF0_VF17_BASE_CLASS__BASE_CLASS_MASK
92632. BIF_CFG_DEV0_EPF0_VF17_BASE_CLASS__BASE_CLASS__SHIFT
92633. BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_CAP_MASK
92634. BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_CAP__SHIFT
92635. BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_COMP_MASK
92636. BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_COMP__SHIFT
92637. BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_STRT_MASK
92638. BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_STRT__SHIFT
92639. BIF_CFG_DEV0_EPF0_VF17_CACHE_LINE__CACHE_LINE_SIZE_MASK
92640. BIF_CFG_DEV0_EPF0_VF17_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
92641. BIF_CFG_DEV0_EPF0_VF17_CAP_PTR__CAP_PTR_MASK
92642. BIF_CFG_DEV0_EPF0_VF17_CAP_PTR__CAP_PTR__SHIFT
92643. BIF_CFG_DEV0_EPF0_VF17_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
92644. BIF_CFG_DEV0_EPF0_VF17_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
92645. BIF_CFG_DEV0_EPF0_VF17_COMMAND__AD_STEPPING_MASK
92646. BIF_CFG_DEV0_EPF0_VF17_COMMAND__AD_STEPPING__SHIFT
92647. BIF_CFG_DEV0_EPF0_VF17_COMMAND__BUS_MASTER_EN_MASK
92648. BIF_CFG_DEV0_EPF0_VF17_COMMAND__BUS_MASTER_EN__SHIFT
92649. BIF_CFG_DEV0_EPF0_VF17_COMMAND__FAST_B2B_EN_MASK
92650. BIF_CFG_DEV0_EPF0_VF17_COMMAND__FAST_B2B_EN__SHIFT
92651. BIF_CFG_DEV0_EPF0_VF17_COMMAND__INT_DIS_MASK
92652. BIF_CFG_DEV0_EPF0_VF17_COMMAND__INT_DIS__SHIFT
92653. BIF_CFG_DEV0_EPF0_VF17_COMMAND__IO_ACCESS_EN_MASK
92654. BIF_CFG_DEV0_EPF0_VF17_COMMAND__IO_ACCESS_EN__SHIFT
92655. BIF_CFG_DEV0_EPF0_VF17_COMMAND__MEM_ACCESS_EN_MASK
92656. BIF_CFG_DEV0_EPF0_VF17_COMMAND__MEM_ACCESS_EN__SHIFT
92657. BIF_CFG_DEV0_EPF0_VF17_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
92658. BIF_CFG_DEV0_EPF0_VF17_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
92659. BIF_CFG_DEV0_EPF0_VF17_COMMAND__PAL_SNOOP_EN_MASK
92660. BIF_CFG_DEV0_EPF0_VF17_COMMAND__PAL_SNOOP_EN__SHIFT
92661. BIF_CFG_DEV0_EPF0_VF17_COMMAND__PARITY_ERROR_RESPONSE_MASK
92662. BIF_CFG_DEV0_EPF0_VF17_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
92663. BIF_CFG_DEV0_EPF0_VF17_COMMAND__SERR_EN_MASK
92664. BIF_CFG_DEV0_EPF0_VF17_COMMAND__SERR_EN__SHIFT
92665. BIF_CFG_DEV0_EPF0_VF17_COMMAND__SPECIAL_CYCLE_EN_MASK
92666. BIF_CFG_DEV0_EPF0_VF17_COMMAND__SPECIAL_CYCLE_EN__SHIFT
92667. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
92668. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
92669. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
92670. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
92671. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
92672. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
92673. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
92674. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
92675. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
92676. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
92677. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
92678. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
92679. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
92680. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
92681. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
92682. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
92683. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
92684. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
92685. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
92686. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
92687. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
92688. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
92689. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__FRS_SUPPORTED_MASK
92690. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
92691. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
92692. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
92693. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__LTR_SUPPORTED_MASK
92694. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
92695. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
92696. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
92697. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
92698. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
92699. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__OBFF_SUPPORTED_MASK
92700. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
92701. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
92702. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
92703. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
92704. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
92705. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
92706. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
92707. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
92708. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
92709. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
92710. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
92711. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__EXTENDED_TAG_MASK
92712. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__EXTENDED_TAG__SHIFT
92713. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__FLR_CAPABLE_MASK
92714. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__FLR_CAPABLE__SHIFT
92715. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
92716. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
92717. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
92718. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
92719. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
92720. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
92721. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__PHANTOM_FUNC_MASK
92722. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__PHANTOM_FUNC__SHIFT
92723. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
92724. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
92725. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
92726. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
92727. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
92728. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
92729. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
92730. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
92731. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
92732. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
92733. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
92734. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
92735. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
92736. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
92737. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
92738. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
92739. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
92740. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
92741. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
92742. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
92743. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__LTR_EN_MASK
92744. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__LTR_EN__SHIFT
92745. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__OBFF_EN_MASK
92746. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__OBFF_EN__SHIFT
92747. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
92748. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
92749. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
92750. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
92751. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__CORR_ERR_EN_MASK
92752. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__CORR_ERR_EN__SHIFT
92753. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
92754. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
92755. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__FATAL_ERR_EN_MASK
92756. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
92757. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__INITIATE_FLR_MASK
92758. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__INITIATE_FLR__SHIFT
92759. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
92760. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
92761. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
92762. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
92763. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
92764. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
92765. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__NO_SNOOP_EN_MASK
92766. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
92767. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
92768. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
92769. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__RELAXED_ORD_EN_MASK
92770. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
92771. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__USR_REPORT_EN_MASK
92772. BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__USR_REPORT_EN__SHIFT
92773. BIF_CFG_DEV0_EPF0_VF17_DEVICE_ID__DEVICE_ID_MASK
92774. BIF_CFG_DEV0_EPF0_VF17_DEVICE_ID__DEVICE_ID__SHIFT
92775. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS2__RESERVED_MASK
92776. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS2__RESERVED__SHIFT
92777. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__AUX_PWR_MASK
92778. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__AUX_PWR__SHIFT
92779. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__CORR_ERR_MASK
92780. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__CORR_ERR__SHIFT
92781. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
92782. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
92783. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__FATAL_ERR_MASK
92784. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__FATAL_ERR__SHIFT
92785. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__NON_FATAL_ERR_MASK
92786. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
92787. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
92788. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
92789. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__USR_DETECTED_MASK
92790. BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__USR_DETECTED__SHIFT
92791. BIF_CFG_DEV0_EPF0_VF17_HEADER__DEVICE_TYPE_MASK
92792. BIF_CFG_DEV0_EPF0_VF17_HEADER__DEVICE_TYPE__SHIFT
92793. BIF_CFG_DEV0_EPF0_VF17_HEADER__HEADER_TYPE_MASK
92794. BIF_CFG_DEV0_EPF0_VF17_HEADER__HEADER_TYPE__SHIFT
92795. BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_LINE__INTERRUPT_LINE_MASK
92796. BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
92797. BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_PIN__INTERRUPT_PIN_MASK
92798. BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
92799. BIF_CFG_DEV0_EPF0_VF17_LATENCY__LATENCY_TIMER_MASK
92800. BIF_CFG_DEV0_EPF0_VF17_LATENCY__LATENCY_TIMER__SHIFT
92801. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
92802. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
92803. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
92804. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
92805. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
92806. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
92807. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
92808. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
92809. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
92810. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
92811. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
92812. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
92813. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
92814. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
92815. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
92816. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
92817. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
92818. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
92819. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
92820. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
92821. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__L0S_EXIT_LATENCY_MASK
92822. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
92823. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__L1_EXIT_LATENCY_MASK
92824. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__L1_EXIT_LATENCY__SHIFT
92825. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
92826. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
92827. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_SPEED_MASK
92828. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_SPEED__SHIFT
92829. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_WIDTH_MASK
92830. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_WIDTH__SHIFT
92831. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__PM_SUPPORT_MASK
92832. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__PM_SUPPORT__SHIFT
92833. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__PORT_NUMBER_MASK
92834. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__PORT_NUMBER__SHIFT
92835. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
92836. BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
92837. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
92838. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
92839. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__COMPLIANCE_SOS_MASK
92840. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
92841. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__ENTER_COMPLIANCE_MASK
92842. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
92843. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
92844. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
92845. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
92846. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
92847. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
92848. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
92849. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__TARGET_LINK_SPEED_MASK
92850. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
92851. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__XMIT_MARGIN_MASK
92852. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__XMIT_MARGIN__SHIFT
92853. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
92854. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
92855. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__COMMON_CLOCK_CFG_MASK
92856. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
92857. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
92858. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
92859. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__EXTENDED_SYNC_MASK
92860. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__EXTENDED_SYNC__SHIFT
92861. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
92862. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
92863. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
92864. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
92865. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
92866. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
92867. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_DIS_MASK
92868. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_DIS__SHIFT
92869. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__PM_CONTROL_MASK
92870. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__PM_CONTROL__SHIFT
92871. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__READ_CPL_BOUNDARY_MASK
92872. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
92873. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__RETRAIN_LINK_MASK
92874. BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__RETRAIN_LINK__SHIFT
92875. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
92876. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
92877. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
92878. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
92879. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
92880. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
92881. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
92882. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
92883. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
92884. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
92885. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
92886. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
92887. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
92888. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
92889. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
92890. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
92891. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
92892. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
92893. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
92894. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
92895. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
92896. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
92897. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__CURRENT_LINK_SPEED_MASK
92898. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
92899. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__DL_ACTIVE_MASK
92900. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__DL_ACTIVE__SHIFT
92901. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
92902. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
92903. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
92904. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
92905. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_TRAINING_MASK
92906. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_TRAINING__SHIFT
92907. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
92908. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
92909. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__SLOT_CLOCK_CFG_MASK
92910. BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
92911. BIF_CFG_DEV0_EPF0_VF17_MAX_LATENCY__MAX_LAT_MASK
92912. BIF_CFG_DEV0_EPF0_VF17_MAX_LATENCY__MAX_LAT__SHIFT
92913. BIF_CFG_DEV0_EPF0_VF17_MIN_GRANT__MIN_GNT_MASK
92914. BIF_CFG_DEV0_EPF0_VF17_MIN_GRANT__MIN_GNT__SHIFT
92915. BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST__CAP_ID_MASK
92916. BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST__CAP_ID__SHIFT
92917. BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST__NEXT_PTR_MASK
92918. BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST__NEXT_PTR__SHIFT
92919. BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_EN_MASK
92920. BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_EN__SHIFT
92921. BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
92922. BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
92923. BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
92924. BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
92925. BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA__MSIX_PBA_BIR_MASK
92926. BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA__MSIX_PBA_BIR__SHIFT
92927. BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA__MSIX_PBA_OFFSET_MASK
92928. BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
92929. BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE__MSIX_TABLE_BIR_MASK
92930. BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
92931. BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
92932. BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
92933. BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST__CAP_ID_MASK
92934. BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST__CAP_ID__SHIFT
92935. BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST__NEXT_PTR_MASK
92936. BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST__NEXT_PTR__SHIFT
92937. BIF_CFG_DEV0_EPF0_VF17_MSI_MASK_64__MSI_MASK_64_MASK
92938. BIF_CFG_DEV0_EPF0_VF17_MSI_MASK_64__MSI_MASK_64__SHIFT
92939. BIF_CFG_DEV0_EPF0_VF17_MSI_MASK__MSI_MASK_MASK
92940. BIF_CFG_DEV0_EPF0_VF17_MSI_MASK__MSI_MASK__SHIFT
92941. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
92942. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
92943. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
92944. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
92945. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_64BIT_MASK
92946. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_64BIT__SHIFT
92947. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_EN_MASK
92948. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_EN__SHIFT
92949. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
92950. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
92951. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
92952. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
92953. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
92954. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
92955. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA_64__MSI_DATA_64_MASK
92956. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
92957. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA__MSI_DATA_MASK
92958. BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA__MSI_DATA__SHIFT
92959. BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING_64__MSI_PENDING_64_MASK
92960. BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING_64__MSI_PENDING_64__SHIFT
92961. BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING__MSI_PENDING_MASK
92962. BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING__MSI_PENDING__SHIFT
92963. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
92964. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
92965. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
92966. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
92967. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
92968. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
92969. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
92970. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
92971. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
92972. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
92973. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
92974. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
92975. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
92976. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
92977. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
92978. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
92979. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
92980. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
92981. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
92982. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
92983. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
92984. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
92985. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
92986. BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
92987. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
92988. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
92989. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
92990. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
92991. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
92992. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
92993. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
92994. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
92995. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
92996. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
92997. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
92998. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
92999. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
93000. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
93001. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
93002. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
93003. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
93004. BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
93005. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
93006. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
93007. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
93008. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
93009. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
93010. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
93011. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL__ATC_ENABLE_MASK
93012. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
93013. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL__STU_MASK
93014. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL__STU__SHIFT
93015. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
93016. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
93017. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
93018. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
93019. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
93020. BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
93021. BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST__CAP_ID_MASK
93022. BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST__CAP_ID__SHIFT
93023. BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST__NEXT_PTR_MASK
93024. BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST__NEXT_PTR__SHIFT
93025. BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__DEVICE_TYPE_MASK
93026. BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__DEVICE_TYPE__SHIFT
93027. BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__INT_MESSAGE_NUM_MASK
93028. BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
93029. BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__SLOT_IMPLEMENTED_MASK
93030. BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
93031. BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__VERSION_MASK
93032. BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__VERSION__SHIFT
93033. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
93034. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
93035. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
93036. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
93037. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
93038. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
93039. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
93040. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
93041. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
93042. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
93043. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
93044. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
93045. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
93046. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
93047. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
93048. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
93049. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
93050. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
93051. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
93052. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
93053. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
93054. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
93055. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
93056. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
93057. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
93058. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
93059. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
93060. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
93061. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
93062. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
93063. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
93064. BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
93065. BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG0__TLP_HDR_MASK
93066. BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG0__TLP_HDR__SHIFT
93067. BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG1__TLP_HDR_MASK
93068. BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG1__TLP_HDR__SHIFT
93069. BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG2__TLP_HDR_MASK
93070. BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG2__TLP_HDR__SHIFT
93071. BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG3__TLP_HDR_MASK
93072. BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG3__TLP_HDR__SHIFT
93073. BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
93074. BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
93075. BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
93076. BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
93077. BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
93078. BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
93079. BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
93080. BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
93081. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
93082. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
93083. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
93084. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
93085. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
93086. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
93087. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
93088. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
93089. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
93090. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
93091. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
93092. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
93093. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
93094. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
93095. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
93096. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
93097. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
93098. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
93099. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
93100. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
93101. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
93102. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
93103. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
93104. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
93105. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
93106. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
93107. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
93108. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
93109. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
93110. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
93111. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
93112. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
93113. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
93114. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
93115. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
93116. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
93117. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
93118. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
93119. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
93120. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
93121. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
93122. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
93123. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
93124. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
93125. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
93126. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
93127. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
93128. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
93129. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
93130. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
93131. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
93132. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
93133. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
93134. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
93135. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
93136. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
93137. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
93138. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
93139. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
93140. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
93141. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
93142. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
93143. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
93144. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
93145. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
93146. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
93147. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
93148. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
93149. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
93150. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
93151. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
93152. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
93153. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
93154. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
93155. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
93156. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
93157. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
93158. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
93159. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
93160. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
93161. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
93162. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
93163. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
93164. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
93165. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
93166. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
93167. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
93168. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
93169. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
93170. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
93171. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
93172. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
93173. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
93174. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
93175. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
93176. BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
93177. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
93178. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
93179. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
93180. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
93181. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
93182. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
93183. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
93184. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
93185. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
93186. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
93187. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
93188. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
93189. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
93190. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
93191. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
93192. BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
93193. BIF_CFG_DEV0_EPF0_VF17_PROG_INTERFACE__PROG_INTERFACE_MASK
93194. BIF_CFG_DEV0_EPF0_VF17_PROG_INTERFACE__PROG_INTERFACE__SHIFT
93195. BIF_CFG_DEV0_EPF0_VF17_REVISION_ID__MAJOR_REV_ID_MASK
93196. BIF_CFG_DEV0_EPF0_VF17_REVISION_ID__MAJOR_REV_ID__SHIFT
93197. BIF_CFG_DEV0_EPF0_VF17_REVISION_ID__MINOR_REV_ID_MASK
93198. BIF_CFG_DEV0_EPF0_VF17_REVISION_ID__MINOR_REV_ID__SHIFT
93199. BIF_CFG_DEV0_EPF0_VF17_ROM_BASE_ADDR__BASE_ADDR_MASK
93200. BIF_CFG_DEV0_EPF0_VF17_ROM_BASE_ADDR__BASE_ADDR__SHIFT
93201. BIF_CFG_DEV0_EPF0_VF17_STATUS__CAP_LIST_MASK
93202. BIF_CFG_DEV0_EPF0_VF17_STATUS__CAP_LIST__SHIFT
93203. BIF_CFG_DEV0_EPF0_VF17_STATUS__DEVSEL_TIMING_MASK
93204. BIF_CFG_DEV0_EPF0_VF17_STATUS__DEVSEL_TIMING__SHIFT
93205. BIF_CFG_DEV0_EPF0_VF17_STATUS__FAST_BACK_CAPABLE_MASK
93206. BIF_CFG_DEV0_EPF0_VF17_STATUS__FAST_BACK_CAPABLE__SHIFT
93207. BIF_CFG_DEV0_EPF0_VF17_STATUS__IMMEDIATE_READINESS_MASK
93208. BIF_CFG_DEV0_EPF0_VF17_STATUS__IMMEDIATE_READINESS__SHIFT
93209. BIF_CFG_DEV0_EPF0_VF17_STATUS__INT_STATUS_MASK
93210. BIF_CFG_DEV0_EPF0_VF17_STATUS__INT_STATUS__SHIFT
93211. BIF_CFG_DEV0_EPF0_VF17_STATUS__MASTER_DATA_PARITY_ERROR_MASK
93212. BIF_CFG_DEV0_EPF0_VF17_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
93213. BIF_CFG_DEV0_EPF0_VF17_STATUS__PARITY_ERROR_DETECTED_MASK
93214. BIF_CFG_DEV0_EPF0_VF17_STATUS__PARITY_ERROR_DETECTED__SHIFT
93215. BIF_CFG_DEV0_EPF0_VF17_STATUS__PCI_66_CAP_MASK
93216. BIF_CFG_DEV0_EPF0_VF17_STATUS__PCI_66_CAP__SHIFT
93217. BIF_CFG_DEV0_EPF0_VF17_STATUS__RECEIVED_MASTER_ABORT_MASK
93218. BIF_CFG_DEV0_EPF0_VF17_STATUS__RECEIVED_MASTER_ABORT__SHIFT
93219. BIF_CFG_DEV0_EPF0_VF17_STATUS__RECEIVED_TARGET_ABORT_MASK
93220. BIF_CFG_DEV0_EPF0_VF17_STATUS__RECEIVED_TARGET_ABORT__SHIFT
93221. BIF_CFG_DEV0_EPF0_VF17_STATUS__SIGNALED_SYSTEM_ERROR_MASK
93222. BIF_CFG_DEV0_EPF0_VF17_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
93223. BIF_CFG_DEV0_EPF0_VF17_STATUS__SIGNAL_TARGET_ABORT_MASK
93224. BIF_CFG_DEV0_EPF0_VF17_STATUS__SIGNAL_TARGET_ABORT__SHIFT
93225. BIF_CFG_DEV0_EPF0_VF17_SUB_CLASS__SUB_CLASS_MASK
93226. BIF_CFG_DEV0_EPF0_VF17_SUB_CLASS__SUB_CLASS__SHIFT
93227. BIF_CFG_DEV0_EPF0_VF17_VENDOR_ID__VENDOR_ID_MASK
93228. BIF_CFG_DEV0_EPF0_VF17_VENDOR_ID__VENDOR_ID__SHIFT
93229. BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
93230. BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
93231. BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
93232. BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
93233. BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1__BASE_ADDR_MASK
93234. BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1__BASE_ADDR__SHIFT
93235. BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2__BASE_ADDR_MASK
93236. BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2__BASE_ADDR__SHIFT
93237. BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3__BASE_ADDR_MASK
93238. BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3__BASE_ADDR__SHIFT
93239. BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4__BASE_ADDR_MASK
93240. BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4__BASE_ADDR__SHIFT
93241. BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5__BASE_ADDR_MASK
93242. BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5__BASE_ADDR__SHIFT
93243. BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6__BASE_ADDR_MASK
93244. BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6__BASE_ADDR__SHIFT
93245. BIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS__BASE_CLASS_MASK
93246. BIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS__BASE_CLASS__SHIFT
93247. BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_CAP_MASK
93248. BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_CAP__SHIFT
93249. BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_COMP_MASK
93250. BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_COMP__SHIFT
93251. BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_STRT_MASK
93252. BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_STRT__SHIFT
93253. BIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
93254. BIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
93255. BIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR__CAP_PTR_MASK
93256. BIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR__CAP_PTR__SHIFT
93257. BIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
93258. BIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
93259. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__AD_STEPPING_MASK
93260. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__AD_STEPPING__SHIFT
93261. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__BUS_MASTER_EN_MASK
93262. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__BUS_MASTER_EN__SHIFT
93263. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__FAST_B2B_EN_MASK
93264. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__FAST_B2B_EN__SHIFT
93265. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__INT_DIS_MASK
93266. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__INT_DIS__SHIFT
93267. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__IO_ACCESS_EN_MASK
93268. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__IO_ACCESS_EN__SHIFT
93269. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__MEM_ACCESS_EN_MASK
93270. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__MEM_ACCESS_EN__SHIFT
93271. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
93272. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
93273. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__PAL_SNOOP_EN_MASK
93274. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__PAL_SNOOP_EN__SHIFT
93275. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
93276. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
93277. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__SERR_EN_MASK
93278. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__SERR_EN__SHIFT
93279. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__SPECIAL_CYCLE_EN_MASK
93280. BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
93281. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
93282. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
93283. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
93284. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
93285. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
93286. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
93287. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
93288. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
93289. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
93290. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
93291. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
93292. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
93293. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
93294. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
93295. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
93296. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
93297. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
93298. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
93299. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
93300. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
93301. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
93302. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
93303. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
93304. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
93305. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
93306. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
93307. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
93308. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
93309. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
93310. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
93311. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
93312. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
93313. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
93314. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
93315. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
93316. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
93317. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
93318. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
93319. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
93320. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
93321. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
93322. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
93323. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
93324. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
93325. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__EXTENDED_TAG_MASK
93326. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
93327. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__FLR_CAPABLE_MASK
93328. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
93329. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
93330. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
93331. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
93332. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
93333. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
93334. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
93335. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__PHANTOM_FUNC_MASK
93336. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
93337. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
93338. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
93339. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
93340. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
93341. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
93342. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
93343. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
93344. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
93345. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
93346. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
93347. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
93348. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
93349. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
93350. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
93351. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
93352. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
93353. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
93354. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
93355. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
93356. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
93357. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__LTR_EN_MASK
93358. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__LTR_EN__SHIFT
93359. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__OBFF_EN_MASK
93360. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__OBFF_EN__SHIFT
93361. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
93362. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
93363. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
93364. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
93365. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__CORR_ERR_EN_MASK
93366. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
93367. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
93368. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
93369. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
93370. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
93371. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__INITIATE_FLR_MASK
93372. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
93373. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
93374. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
93375. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
93376. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
93377. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
93378. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
93379. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
93380. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
93381. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
93382. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
93383. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
93384. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
93385. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__USR_REPORT_EN_MASK
93386. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
93387. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID__DEVICE_ID_MASK
93388. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID__DEVICE_ID__SHIFT
93389. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2__RESERVED_MASK
93390. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2__RESERVED__SHIFT
93391. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__AUX_PWR_MASK
93392. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__AUX_PWR__SHIFT
93393. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__CORR_ERR_MASK
93394. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__CORR_ERR__SHIFT
93395. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
93396. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
93397. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__FATAL_ERR_MASK
93398. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__FATAL_ERR__SHIFT
93399. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
93400. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
93401. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
93402. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
93403. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__USR_DETECTED_MASK
93404. BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__USR_DETECTED__SHIFT
93405. BIF_CFG_DEV0_EPF0_VF18_0_HEADER__DEVICE_TYPE_MASK
93406. BIF_CFG_DEV0_EPF0_VF18_0_HEADER__DEVICE_TYPE__SHIFT
93407. BIF_CFG_DEV0_EPF0_VF18_0_HEADER__HEADER_TYPE_MASK
93408. BIF_CFG_DEV0_EPF0_VF18_0_HEADER__HEADER_TYPE__SHIFT
93409. BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
93410. BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
93411. BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
93412. BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
93413. BIF_CFG_DEV0_EPF0_VF18_0_LATENCY__LATENCY_TIMER_MASK
93414. BIF_CFG_DEV0_EPF0_VF18_0_LATENCY__LATENCY_TIMER__SHIFT
93415. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
93416. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
93417. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
93418. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
93419. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
93420. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
93421. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
93422. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
93423. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
93424. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
93425. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
93426. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
93427. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
93428. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
93429. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
93430. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
93431. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
93432. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
93433. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
93434. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
93435. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
93436. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
93437. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__L1_EXIT_LATENCY_MASK
93438. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
93439. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
93440. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
93441. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_SPEED_MASK
93442. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_SPEED__SHIFT
93443. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_WIDTH_MASK
93444. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_WIDTH__SHIFT
93445. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__PM_SUPPORT_MASK
93446. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__PM_SUPPORT__SHIFT
93447. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__PORT_NUMBER_MASK
93448. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__PORT_NUMBER__SHIFT
93449. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
93450. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
93451. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
93452. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
93453. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
93454. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
93455. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
93456. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
93457. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
93458. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
93459. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
93460. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
93461. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
93462. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
93463. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
93464. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
93465. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__XMIT_MARGIN_MASK
93466. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
93467. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
93468. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
93469. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
93470. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
93471. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
93472. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
93473. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__EXTENDED_SYNC_MASK
93474. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
93475. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
93476. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
93477. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
93478. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
93479. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
93480. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
93481. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_DIS_MASK
93482. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_DIS__SHIFT
93483. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__PM_CONTROL_MASK
93484. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__PM_CONTROL__SHIFT
93485. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
93486. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
93487. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__RETRAIN_LINK_MASK
93488. BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__RETRAIN_LINK__SHIFT
93489. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
93490. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
93491. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
93492. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
93493. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
93494. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
93495. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
93496. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
93497. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
93498. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
93499. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
93500. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
93501. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
93502. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
93503. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
93504. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
93505. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
93506. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
93507. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
93508. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
93509. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
93510. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
93511. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
93512. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
93513. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__DL_ACTIVE_MASK
93514. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__DL_ACTIVE__SHIFT
93515. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
93516. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
93517. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
93518. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
93519. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_TRAINING_MASK
93520. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_TRAINING__SHIFT
93521. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
93522. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
93523. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
93524. BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
93525. BIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY__MAX_LAT_MASK
93526. BIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY__MAX_LAT__SHIFT
93527. BIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT__MIN_GNT_MASK
93528. BIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT__MIN_GNT__SHIFT
93529. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST__CAP_ID_MASK
93530. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST__CAP_ID__SHIFT
93531. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST__NEXT_PTR_MASK
93532. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
93533. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_EN_MASK
93534. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
93535. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
93536. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
93537. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
93538. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
93539. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA__MSIX_PBA_BIR_MASK
93540. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
93541. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
93542. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
93543. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
93544. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
93545. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
93546. BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
93547. BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST__CAP_ID_MASK
93548. BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST__CAP_ID__SHIFT
93549. BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST__NEXT_PTR_MASK
93550. BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
93551. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64__MSI_MASK_64_MASK
93552. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64__MSI_MASK_64__SHIFT
93553. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK__MSI_MASK_MASK
93554. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK__MSI_MASK__SHIFT
93555. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
93556. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
93557. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
93558. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
93559. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_64BIT_MASK
93560. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
93561. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_EN_MASK
93562. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_EN__SHIFT
93563. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
93564. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
93565. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
93566. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
93567. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
93568. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
93569. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
93570. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
93571. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA__MSI_DATA_MASK
93572. BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA__MSI_DATA__SHIFT
93573. BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64__MSI_PENDING_64_MASK
93574. BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
93575. BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING__MSI_PENDING_MASK
93576. BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING__MSI_PENDING__SHIFT
93577. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
93578. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
93579. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
93580. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
93581. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
93582. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
93583. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
93584. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
93585. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
93586. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
93587. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
93588. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
93589. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
93590. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
93591. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
93592. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
93593. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
93594. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
93595. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
93596. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
93597. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
93598. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
93599. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
93600. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
93601. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
93602. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
93603. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
93604. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
93605. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
93606. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
93607. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
93608. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
93609. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
93610. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
93611. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
93612. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
93613. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
93614. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
93615. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
93616. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
93617. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
93618. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
93619. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
93620. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
93621. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
93622. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
93623. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
93624. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
93625. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
93626. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
93627. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL__STU_MASK
93628. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL__STU__SHIFT
93629. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
93630. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
93631. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
93632. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
93633. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
93634. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
93635. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST__CAP_ID_MASK
93636. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST__CAP_ID__SHIFT
93637. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST__NEXT_PTR_MASK
93638. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
93639. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__DEVICE_TYPE_MASK
93640. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__DEVICE_TYPE__SHIFT
93641. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
93642. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
93643. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
93644. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
93645. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__VERSION_MASK
93646. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__VERSION__SHIFT
93647. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
93648. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
93649. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
93650. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
93651. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
93652. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
93653. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
93654. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
93655. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
93656. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
93657. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
93658. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
93659. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
93660. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
93661. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
93662. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
93663. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
93664. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
93665. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
93666. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
93667. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
93668. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
93669. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
93670. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
93671. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
93672. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
93673. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
93674. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
93675. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
93676. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
93677. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
93678. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
93679. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0__TLP_HDR_MASK
93680. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
93681. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1__TLP_HDR_MASK
93682. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
93683. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2__TLP_HDR_MASK
93684. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
93685. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3__TLP_HDR_MASK
93686. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
93687. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
93688. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
93689. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
93690. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
93691. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
93692. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
93693. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
93694. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
93695. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
93696. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
93697. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
93698. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
93699. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
93700. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
93701. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
93702. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
93703. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
93704. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
93705. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
93706. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
93707. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
93708. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
93709. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
93710. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
93711. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
93712. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
93713. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
93714. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
93715. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
93716. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
93717. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
93718. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
93719. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
93720. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
93721. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
93722. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
93723. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
93724. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
93725. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
93726. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
93727. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
93728. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
93729. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
93730. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
93731. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
93732. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
93733. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
93734. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
93735. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
93736. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
93737. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
93738. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
93739. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
93740. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
93741. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
93742. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
93743. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
93744. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
93745. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
93746. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
93747. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
93748. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
93749. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
93750. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
93751. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
93752. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
93753. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
93754. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
93755. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
93756. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
93757. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
93758. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
93759. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
93760. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
93761. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
93762. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
93763. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
93764. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
93765. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
93766. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
93767. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
93768. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
93769. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
93770. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
93771. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
93772. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
93773. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
93774. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
93775. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
93776. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
93777. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
93778. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
93779. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
93780. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
93781. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
93782. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
93783. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
93784. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
93785. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
93786. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
93787. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
93788. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
93789. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
93790. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
93791. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
93792. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
93793. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
93794. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
93795. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
93796. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
93797. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
93798. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
93799. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
93800. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
93801. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
93802. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
93803. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
93804. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
93805. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
93806. BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
93807. BIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE__PROG_INTERFACE_MASK
93808. BIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
93809. BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID__MAJOR_REV_ID_MASK
93810. BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID__MAJOR_REV_ID__SHIFT
93811. BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID__MINOR_REV_ID_MASK
93812. BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID__MINOR_REV_ID__SHIFT
93813. BIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR__BASE_ADDR_MASK
93814. BIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
93815. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__CAP_LIST_MASK
93816. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__CAP_LIST__SHIFT
93817. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__DEVSEL_TIMING_MASK
93818. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__DEVSEL_TIMING__SHIFT
93819. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__FAST_BACK_CAPABLE_MASK
93820. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__FAST_BACK_CAPABLE__SHIFT
93821. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__IMMEDIATE_READINESS_MASK
93822. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__IMMEDIATE_READINESS__SHIFT
93823. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__INT_STATUS_MASK
93824. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__INT_STATUS__SHIFT
93825. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
93826. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
93827. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__PARITY_ERROR_DETECTED_MASK
93828. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
93829. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__PCI_66_CAP_MASK
93830. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__PCI_66_CAP__SHIFT
93831. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__RECEIVED_MASTER_ABORT_MASK
93832. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
93833. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__RECEIVED_TARGET_ABORT_MASK
93834. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
93835. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
93836. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
93837. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__SIGNAL_TARGET_ABORT_MASK
93838. BIF_CFG_DEV0_EPF0_VF18_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
93839. BIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS__SUB_CLASS_MASK
93840. BIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS__SUB_CLASS__SHIFT
93841. BIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID__VENDOR_ID_MASK
93842. BIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID__VENDOR_ID__SHIFT
93843. BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
93844. BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
93845. BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
93846. BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
93847. BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1__BASE_ADDR_MASK
93848. BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1__BASE_ADDR__SHIFT
93849. BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2__BASE_ADDR_MASK
93850. BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2__BASE_ADDR__SHIFT
93851. BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3__BASE_ADDR_MASK
93852. BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3__BASE_ADDR__SHIFT
93853. BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4__BASE_ADDR_MASK
93854. BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4__BASE_ADDR__SHIFT
93855. BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5__BASE_ADDR_MASK
93856. BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5__BASE_ADDR__SHIFT
93857. BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6__BASE_ADDR_MASK
93858. BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6__BASE_ADDR__SHIFT
93859. BIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS__BASE_CLASS_MASK
93860. BIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS__BASE_CLASS__SHIFT
93861. BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_CAP_MASK
93862. BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_CAP__SHIFT
93863. BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_COMP_MASK
93864. BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_COMP__SHIFT
93865. BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_STRT_MASK
93866. BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_STRT__SHIFT
93867. BIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
93868. BIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
93869. BIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR__CAP_PTR_MASK
93870. BIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR__CAP_PTR__SHIFT
93871. BIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
93872. BIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
93873. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__AD_STEPPING_MASK
93874. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__AD_STEPPING__SHIFT
93875. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__BUS_MASTER_EN_MASK
93876. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__BUS_MASTER_EN__SHIFT
93877. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__FAST_B2B_EN_MASK
93878. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__FAST_B2B_EN__SHIFT
93879. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__INT_DIS_MASK
93880. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__INT_DIS__SHIFT
93881. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__IO_ACCESS_EN_MASK
93882. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__IO_ACCESS_EN__SHIFT
93883. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__MEM_ACCESS_EN_MASK
93884. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__MEM_ACCESS_EN__SHIFT
93885. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
93886. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
93887. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__PAL_SNOOP_EN_MASK
93888. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__PAL_SNOOP_EN__SHIFT
93889. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
93890. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
93891. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__SERR_EN_MASK
93892. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__SERR_EN__SHIFT
93893. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__SPECIAL_CYCLE_EN_MASK
93894. BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
93895. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
93896. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
93897. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
93898. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
93899. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
93900. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
93901. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
93902. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
93903. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
93904. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
93905. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
93906. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
93907. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
93908. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
93909. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
93910. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
93911. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
93912. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
93913. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
93914. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
93915. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
93916. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
93917. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
93918. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
93919. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
93920. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
93921. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
93922. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
93923. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
93924. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
93925. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
93926. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
93927. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
93928. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
93929. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
93930. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
93931. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
93932. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
93933. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
93934. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
93935. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
93936. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
93937. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
93938. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
93939. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__EXTENDED_TAG_MASK
93940. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
93941. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__FLR_CAPABLE_MASK
93942. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
93943. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
93944. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
93945. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
93946. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
93947. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
93948. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
93949. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__PHANTOM_FUNC_MASK
93950. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
93951. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
93952. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
93953. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
93954. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
93955. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
93956. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
93957. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
93958. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
93959. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
93960. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
93961. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
93962. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
93963. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
93964. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
93965. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
93966. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
93967. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
93968. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
93969. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
93970. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
93971. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__LTR_EN_MASK
93972. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__LTR_EN__SHIFT
93973. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__OBFF_EN_MASK
93974. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__OBFF_EN__SHIFT
93975. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
93976. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
93977. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
93978. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
93979. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__CORR_ERR_EN_MASK
93980. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
93981. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
93982. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
93983. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
93984. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
93985. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__INITIATE_FLR_MASK
93986. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
93987. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
93988. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
93989. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
93990. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
93991. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
93992. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
93993. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
93994. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
93995. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
93996. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
93997. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
93998. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
93999. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__USR_REPORT_EN_MASK
94000. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
94001. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID__DEVICE_ID_MASK
94002. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID__DEVICE_ID__SHIFT
94003. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2__RESERVED_MASK
94004. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2__RESERVED__SHIFT
94005. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__AUX_PWR_MASK
94006. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__AUX_PWR__SHIFT
94007. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__CORR_ERR_MASK
94008. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__CORR_ERR__SHIFT
94009. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
94010. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
94011. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__FATAL_ERR_MASK
94012. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__FATAL_ERR__SHIFT
94013. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
94014. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
94015. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
94016. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
94017. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__USR_DETECTED_MASK
94018. BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__USR_DETECTED__SHIFT
94019. BIF_CFG_DEV0_EPF0_VF18_1_HEADER__DEVICE_TYPE_MASK
94020. BIF_CFG_DEV0_EPF0_VF18_1_HEADER__DEVICE_TYPE__SHIFT
94021. BIF_CFG_DEV0_EPF0_VF18_1_HEADER__HEADER_TYPE_MASK
94022. BIF_CFG_DEV0_EPF0_VF18_1_HEADER__HEADER_TYPE__SHIFT
94023. BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
94024. BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
94025. BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
94026. BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
94027. BIF_CFG_DEV0_EPF0_VF18_1_LATENCY__LATENCY_TIMER_MASK
94028. BIF_CFG_DEV0_EPF0_VF18_1_LATENCY__LATENCY_TIMER__SHIFT
94029. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
94030. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
94031. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
94032. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
94033. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
94034. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
94035. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
94036. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
94037. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
94038. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
94039. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
94040. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
94041. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
94042. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
94043. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
94044. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
94045. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
94046. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
94047. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
94048. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
94049. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
94050. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
94051. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__L1_EXIT_LATENCY_MASK
94052. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
94053. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
94054. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
94055. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_SPEED_MASK
94056. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_SPEED__SHIFT
94057. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_WIDTH_MASK
94058. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_WIDTH__SHIFT
94059. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__PM_SUPPORT_MASK
94060. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__PM_SUPPORT__SHIFT
94061. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__PORT_NUMBER_MASK
94062. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__PORT_NUMBER__SHIFT
94063. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
94064. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
94065. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
94066. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
94067. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
94068. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
94069. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
94070. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
94071. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
94072. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
94073. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
94074. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
94075. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
94076. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
94077. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
94078. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
94079. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__XMIT_MARGIN_MASK
94080. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
94081. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
94082. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
94083. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
94084. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
94085. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
94086. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
94087. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__EXTENDED_SYNC_MASK
94088. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
94089. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
94090. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
94091. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
94092. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
94093. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
94094. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
94095. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_DIS_MASK
94096. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_DIS__SHIFT
94097. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__PM_CONTROL_MASK
94098. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__PM_CONTROL__SHIFT
94099. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
94100. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
94101. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__RETRAIN_LINK_MASK
94102. BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__RETRAIN_LINK__SHIFT
94103. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
94104. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
94105. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
94106. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
94107. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
94108. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
94109. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
94110. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
94111. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
94112. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
94113. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
94114. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
94115. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
94116. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
94117. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
94118. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
94119. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
94120. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
94121. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
94122. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
94123. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
94124. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
94125. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
94126. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
94127. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__DL_ACTIVE_MASK
94128. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__DL_ACTIVE__SHIFT
94129. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
94130. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
94131. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
94132. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
94133. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_TRAINING_MASK
94134. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_TRAINING__SHIFT
94135. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
94136. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
94137. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
94138. BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
94139. BIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY__MAX_LAT_MASK
94140. BIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY__MAX_LAT__SHIFT
94141. BIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT__MIN_GNT_MASK
94142. BIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT__MIN_GNT__SHIFT
94143. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST__CAP_ID_MASK
94144. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST__CAP_ID__SHIFT
94145. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST__NEXT_PTR_MASK
94146. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
94147. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_EN_MASK
94148. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
94149. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
94150. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
94151. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
94152. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
94153. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA__MSIX_PBA_BIR_MASK
94154. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
94155. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
94156. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
94157. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
94158. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
94159. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
94160. BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
94161. BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST__CAP_ID_MASK
94162. BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST__CAP_ID__SHIFT
94163. BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST__NEXT_PTR_MASK
94164. BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
94165. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64__MSI_MASK_64_MASK
94166. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64__MSI_MASK_64__SHIFT
94167. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK__MSI_MASK_MASK
94168. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK__MSI_MASK__SHIFT
94169. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
94170. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
94171. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
94172. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
94173. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_64BIT_MASK
94174. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
94175. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_EN_MASK
94176. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_EN__SHIFT
94177. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
94178. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
94179. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
94180. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
94181. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
94182. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
94183. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
94184. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
94185. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA__MSI_DATA_MASK
94186. BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA__MSI_DATA__SHIFT
94187. BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64__MSI_PENDING_64_MASK
94188. BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
94189. BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING__MSI_PENDING_MASK
94190. BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING__MSI_PENDING__SHIFT
94191. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
94192. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
94193. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
94194. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
94195. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
94196. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
94197. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
94198. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
94199. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
94200. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
94201. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
94202. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
94203. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
94204. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
94205. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
94206. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
94207. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
94208. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
94209. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
94210. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
94211. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
94212. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
94213. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
94214. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
94215. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
94216. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
94217. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
94218. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
94219. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
94220. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
94221. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
94222. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
94223. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
94224. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
94225. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
94226. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
94227. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
94228. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
94229. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
94230. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
94231. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
94232. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
94233. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
94234. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
94235. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
94236. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
94237. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
94238. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
94239. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
94240. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
94241. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL__STU_MASK
94242. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL__STU__SHIFT
94243. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
94244. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
94245. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
94246. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
94247. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
94248. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
94249. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST__CAP_ID_MASK
94250. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST__CAP_ID__SHIFT
94251. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST__NEXT_PTR_MASK
94252. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
94253. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__DEVICE_TYPE_MASK
94254. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__DEVICE_TYPE__SHIFT
94255. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
94256. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
94257. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
94258. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
94259. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__VERSION_MASK
94260. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__VERSION__SHIFT
94261. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
94262. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
94263. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
94264. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
94265. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
94266. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
94267. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
94268. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
94269. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
94270. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
94271. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
94272. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
94273. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
94274. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
94275. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
94276. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
94277. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
94278. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
94279. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
94280. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
94281. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
94282. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
94283. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
94284. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
94285. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
94286. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
94287. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
94288. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
94289. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
94290. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
94291. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
94292. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
94293. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0__TLP_HDR_MASK
94294. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
94295. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1__TLP_HDR_MASK
94296. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
94297. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2__TLP_HDR_MASK
94298. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
94299. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3__TLP_HDR_MASK
94300. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
94301. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
94302. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
94303. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
94304. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
94305. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
94306. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
94307. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
94308. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
94309. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
94310. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
94311. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
94312. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
94313. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
94314. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
94315. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
94316. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
94317. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
94318. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
94319. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
94320. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
94321. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
94322. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
94323. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
94324. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
94325. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
94326. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
94327. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
94328. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
94329. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
94330. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
94331. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
94332. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
94333. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
94334. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
94335. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
94336. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
94337. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
94338. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
94339. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
94340. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
94341. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
94342. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
94343. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
94344. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
94345. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
94346. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
94347. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
94348. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
94349. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
94350. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
94351. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
94352. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
94353. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
94354. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
94355. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
94356. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
94357. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
94358. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
94359. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
94360. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
94361. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
94362. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
94363. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
94364. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
94365. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
94366. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
94367. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
94368. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
94369. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
94370. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
94371. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
94372. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
94373. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
94374. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
94375. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
94376. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
94377. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
94378. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
94379. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
94380. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
94381. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
94382. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
94383. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
94384. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
94385. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
94386. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
94387. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
94388. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
94389. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
94390. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
94391. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
94392. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
94393. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
94394. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
94395. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
94396. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
94397. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
94398. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
94399. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
94400. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
94401. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
94402. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
94403. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
94404. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
94405. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
94406. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
94407. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
94408. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
94409. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
94410. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
94411. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
94412. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
94413. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
94414. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
94415. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
94416. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
94417. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
94418. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
94419. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
94420. BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
94421. BIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE__PROG_INTERFACE_MASK
94422. BIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
94423. BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID__MAJOR_REV_ID_MASK
94424. BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID__MAJOR_REV_ID__SHIFT
94425. BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID__MINOR_REV_ID_MASK
94426. BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID__MINOR_REV_ID__SHIFT
94427. BIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR__BASE_ADDR_MASK
94428. BIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
94429. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__CAP_LIST_MASK
94430. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__CAP_LIST__SHIFT
94431. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__DEVSEL_TIMING_MASK
94432. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__DEVSEL_TIMING__SHIFT
94433. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__FAST_BACK_CAPABLE_MASK
94434. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__FAST_BACK_CAPABLE__SHIFT
94435. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__IMMEDIATE_READINESS_MASK
94436. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__IMMEDIATE_READINESS__SHIFT
94437. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__INT_STATUS_MASK
94438. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__INT_STATUS__SHIFT
94439. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
94440. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
94441. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__PARITY_ERROR_DETECTED_MASK
94442. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
94443. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__PCI_66_CAP_MASK
94444. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__PCI_66_CAP__SHIFT
94445. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__RECEIVED_MASTER_ABORT_MASK
94446. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
94447. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__RECEIVED_TARGET_ABORT_MASK
94448. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
94449. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
94450. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
94451. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__SIGNAL_TARGET_ABORT_MASK
94452. BIF_CFG_DEV0_EPF0_VF18_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
94453. BIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS__SUB_CLASS_MASK
94454. BIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS__SUB_CLASS__SHIFT
94455. BIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID__VENDOR_ID_MASK
94456. BIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID__VENDOR_ID__SHIFT
94457. BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID__SUBSYSTEM_ID_MASK
94458. BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
94459. BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
94460. BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
94461. BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_1__BASE_ADDR_MASK
94462. BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_1__BASE_ADDR__SHIFT
94463. BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_2__BASE_ADDR_MASK
94464. BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_2__BASE_ADDR__SHIFT
94465. BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_3__BASE_ADDR_MASK
94466. BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_3__BASE_ADDR__SHIFT
94467. BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_4__BASE_ADDR_MASK
94468. BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_4__BASE_ADDR__SHIFT
94469. BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_5__BASE_ADDR_MASK
94470. BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_5__BASE_ADDR__SHIFT
94471. BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_6__BASE_ADDR_MASK
94472. BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_6__BASE_ADDR__SHIFT
94473. BIF_CFG_DEV0_EPF0_VF18_BASE_CLASS__BASE_CLASS_MASK
94474. BIF_CFG_DEV0_EPF0_VF18_BASE_CLASS__BASE_CLASS__SHIFT
94475. BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_CAP_MASK
94476. BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_CAP__SHIFT
94477. BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_COMP_MASK
94478. BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_COMP__SHIFT
94479. BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_STRT_MASK
94480. BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_STRT__SHIFT
94481. BIF_CFG_DEV0_EPF0_VF18_CACHE_LINE__CACHE_LINE_SIZE_MASK
94482. BIF_CFG_DEV0_EPF0_VF18_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
94483. BIF_CFG_DEV0_EPF0_VF18_CAP_PTR__CAP_PTR_MASK
94484. BIF_CFG_DEV0_EPF0_VF18_CAP_PTR__CAP_PTR__SHIFT
94485. BIF_CFG_DEV0_EPF0_VF18_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
94486. BIF_CFG_DEV0_EPF0_VF18_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
94487. BIF_CFG_DEV0_EPF0_VF18_COMMAND__AD_STEPPING_MASK
94488. BIF_CFG_DEV0_EPF0_VF18_COMMAND__AD_STEPPING__SHIFT
94489. BIF_CFG_DEV0_EPF0_VF18_COMMAND__BUS_MASTER_EN_MASK
94490. BIF_CFG_DEV0_EPF0_VF18_COMMAND__BUS_MASTER_EN__SHIFT
94491. BIF_CFG_DEV0_EPF0_VF18_COMMAND__FAST_B2B_EN_MASK
94492. BIF_CFG_DEV0_EPF0_VF18_COMMAND__FAST_B2B_EN__SHIFT
94493. BIF_CFG_DEV0_EPF0_VF18_COMMAND__INT_DIS_MASK
94494. BIF_CFG_DEV0_EPF0_VF18_COMMAND__INT_DIS__SHIFT
94495. BIF_CFG_DEV0_EPF0_VF18_COMMAND__IO_ACCESS_EN_MASK
94496. BIF_CFG_DEV0_EPF0_VF18_COMMAND__IO_ACCESS_EN__SHIFT
94497. BIF_CFG_DEV0_EPF0_VF18_COMMAND__MEM_ACCESS_EN_MASK
94498. BIF_CFG_DEV0_EPF0_VF18_COMMAND__MEM_ACCESS_EN__SHIFT
94499. BIF_CFG_DEV0_EPF0_VF18_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
94500. BIF_CFG_DEV0_EPF0_VF18_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
94501. BIF_CFG_DEV0_EPF0_VF18_COMMAND__PAL_SNOOP_EN_MASK
94502. BIF_CFG_DEV0_EPF0_VF18_COMMAND__PAL_SNOOP_EN__SHIFT
94503. BIF_CFG_DEV0_EPF0_VF18_COMMAND__PARITY_ERROR_RESPONSE_MASK
94504. BIF_CFG_DEV0_EPF0_VF18_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
94505. BIF_CFG_DEV0_EPF0_VF18_COMMAND__SERR_EN_MASK
94506. BIF_CFG_DEV0_EPF0_VF18_COMMAND__SERR_EN__SHIFT
94507. BIF_CFG_DEV0_EPF0_VF18_COMMAND__SPECIAL_CYCLE_EN_MASK
94508. BIF_CFG_DEV0_EPF0_VF18_COMMAND__SPECIAL_CYCLE_EN__SHIFT
94509. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
94510. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
94511. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
94512. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
94513. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
94514. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
94515. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
94516. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
94517. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
94518. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
94519. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
94520. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
94521. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
94522. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
94523. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
94524. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
94525. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
94526. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
94527. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
94528. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
94529. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
94530. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
94531. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__FRS_SUPPORTED_MASK
94532. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
94533. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
94534. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
94535. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__LTR_SUPPORTED_MASK
94536. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
94537. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
94538. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
94539. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
94540. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
94541. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__OBFF_SUPPORTED_MASK
94542. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
94543. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
94544. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
94545. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
94546. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
94547. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
94548. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
94549. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
94550. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
94551. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
94552. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
94553. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__EXTENDED_TAG_MASK
94554. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__EXTENDED_TAG__SHIFT
94555. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__FLR_CAPABLE_MASK
94556. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__FLR_CAPABLE__SHIFT
94557. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
94558. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
94559. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
94560. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
94561. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
94562. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
94563. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__PHANTOM_FUNC_MASK
94564. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__PHANTOM_FUNC__SHIFT
94565. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
94566. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
94567. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
94568. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
94569. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
94570. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
94571. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
94572. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
94573. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
94574. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
94575. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
94576. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
94577. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
94578. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
94579. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
94580. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
94581. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
94582. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
94583. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
94584. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
94585. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__LTR_EN_MASK
94586. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__LTR_EN__SHIFT
94587. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__OBFF_EN_MASK
94588. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__OBFF_EN__SHIFT
94589. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
94590. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
94591. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
94592. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
94593. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__CORR_ERR_EN_MASK
94594. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__CORR_ERR_EN__SHIFT
94595. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
94596. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
94597. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__FATAL_ERR_EN_MASK
94598. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
94599. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__INITIATE_FLR_MASK
94600. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__INITIATE_FLR__SHIFT
94601. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
94602. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
94603. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
94604. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
94605. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
94606. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
94607. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__NO_SNOOP_EN_MASK
94608. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
94609. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
94610. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
94611. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__RELAXED_ORD_EN_MASK
94612. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
94613. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__USR_REPORT_EN_MASK
94614. BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__USR_REPORT_EN__SHIFT
94615. BIF_CFG_DEV0_EPF0_VF18_DEVICE_ID__DEVICE_ID_MASK
94616. BIF_CFG_DEV0_EPF0_VF18_DEVICE_ID__DEVICE_ID__SHIFT
94617. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS2__RESERVED_MASK
94618. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS2__RESERVED__SHIFT
94619. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__AUX_PWR_MASK
94620. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__AUX_PWR__SHIFT
94621. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__CORR_ERR_MASK
94622. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__CORR_ERR__SHIFT
94623. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
94624. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
94625. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__FATAL_ERR_MASK
94626. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__FATAL_ERR__SHIFT
94627. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__NON_FATAL_ERR_MASK
94628. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
94629. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
94630. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
94631. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__USR_DETECTED_MASK
94632. BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__USR_DETECTED__SHIFT
94633. BIF_CFG_DEV0_EPF0_VF18_HEADER__DEVICE_TYPE_MASK
94634. BIF_CFG_DEV0_EPF0_VF18_HEADER__DEVICE_TYPE__SHIFT
94635. BIF_CFG_DEV0_EPF0_VF18_HEADER__HEADER_TYPE_MASK
94636. BIF_CFG_DEV0_EPF0_VF18_HEADER__HEADER_TYPE__SHIFT
94637. BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_LINE__INTERRUPT_LINE_MASK
94638. BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
94639. BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_PIN__INTERRUPT_PIN_MASK
94640. BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
94641. BIF_CFG_DEV0_EPF0_VF18_LATENCY__LATENCY_TIMER_MASK
94642. BIF_CFG_DEV0_EPF0_VF18_LATENCY__LATENCY_TIMER__SHIFT
94643. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
94644. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
94645. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
94646. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
94647. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
94648. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
94649. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
94650. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
94651. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
94652. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
94653. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
94654. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
94655. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
94656. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
94657. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
94658. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
94659. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
94660. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
94661. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
94662. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
94663. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__L0S_EXIT_LATENCY_MASK
94664. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
94665. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__L1_EXIT_LATENCY_MASK
94666. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__L1_EXIT_LATENCY__SHIFT
94667. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
94668. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
94669. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_SPEED_MASK
94670. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_SPEED__SHIFT
94671. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_WIDTH_MASK
94672. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_WIDTH__SHIFT
94673. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__PM_SUPPORT_MASK
94674. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__PM_SUPPORT__SHIFT
94675. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__PORT_NUMBER_MASK
94676. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__PORT_NUMBER__SHIFT
94677. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
94678. BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
94679. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
94680. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
94681. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__COMPLIANCE_SOS_MASK
94682. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
94683. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__ENTER_COMPLIANCE_MASK
94684. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
94685. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
94686. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
94687. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
94688. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
94689. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
94690. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
94691. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__TARGET_LINK_SPEED_MASK
94692. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
94693. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__XMIT_MARGIN_MASK
94694. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__XMIT_MARGIN__SHIFT
94695. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
94696. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
94697. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__COMMON_CLOCK_CFG_MASK
94698. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
94699. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
94700. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
94701. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__EXTENDED_SYNC_MASK
94702. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__EXTENDED_SYNC__SHIFT
94703. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
94704. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
94705. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
94706. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
94707. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
94708. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
94709. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_DIS_MASK
94710. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_DIS__SHIFT
94711. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__PM_CONTROL_MASK
94712. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__PM_CONTROL__SHIFT
94713. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__READ_CPL_BOUNDARY_MASK
94714. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
94715. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__RETRAIN_LINK_MASK
94716. BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__RETRAIN_LINK__SHIFT
94717. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
94718. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
94719. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
94720. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
94721. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
94722. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
94723. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
94724. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
94725. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
94726. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
94727. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
94728. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
94729. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
94730. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
94731. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
94732. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
94733. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
94734. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
94735. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
94736. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
94737. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
94738. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
94739. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__CURRENT_LINK_SPEED_MASK
94740. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
94741. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__DL_ACTIVE_MASK
94742. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__DL_ACTIVE__SHIFT
94743. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
94744. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
94745. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
94746. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
94747. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_TRAINING_MASK
94748. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_TRAINING__SHIFT
94749. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
94750. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
94751. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__SLOT_CLOCK_CFG_MASK
94752. BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
94753. BIF_CFG_DEV0_EPF0_VF18_MAX_LATENCY__MAX_LAT_MASK
94754. BIF_CFG_DEV0_EPF0_VF18_MAX_LATENCY__MAX_LAT__SHIFT
94755. BIF_CFG_DEV0_EPF0_VF18_MIN_GRANT__MIN_GNT_MASK
94756. BIF_CFG_DEV0_EPF0_VF18_MIN_GRANT__MIN_GNT__SHIFT
94757. BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST__CAP_ID_MASK
94758. BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST__CAP_ID__SHIFT
94759. BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST__NEXT_PTR_MASK
94760. BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST__NEXT_PTR__SHIFT
94761. BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_EN_MASK
94762. BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_EN__SHIFT
94763. BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
94764. BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
94765. BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
94766. BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
94767. BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA__MSIX_PBA_BIR_MASK
94768. BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA__MSIX_PBA_BIR__SHIFT
94769. BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA__MSIX_PBA_OFFSET_MASK
94770. BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
94771. BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE__MSIX_TABLE_BIR_MASK
94772. BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
94773. BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
94774. BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
94775. BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST__CAP_ID_MASK
94776. BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST__CAP_ID__SHIFT
94777. BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST__NEXT_PTR_MASK
94778. BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST__NEXT_PTR__SHIFT
94779. BIF_CFG_DEV0_EPF0_VF18_MSI_MASK_64__MSI_MASK_64_MASK
94780. BIF_CFG_DEV0_EPF0_VF18_MSI_MASK_64__MSI_MASK_64__SHIFT
94781. BIF_CFG_DEV0_EPF0_VF18_MSI_MASK__MSI_MASK_MASK
94782. BIF_CFG_DEV0_EPF0_VF18_MSI_MASK__MSI_MASK__SHIFT
94783. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
94784. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
94785. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
94786. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
94787. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_64BIT_MASK
94788. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_64BIT__SHIFT
94789. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_EN_MASK
94790. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_EN__SHIFT
94791. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
94792. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
94793. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
94794. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
94795. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
94796. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
94797. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA_64__MSI_DATA_64_MASK
94798. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
94799. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA__MSI_DATA_MASK
94800. BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA__MSI_DATA__SHIFT
94801. BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING_64__MSI_PENDING_64_MASK
94802. BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING_64__MSI_PENDING_64__SHIFT
94803. BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING__MSI_PENDING_MASK
94804. BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING__MSI_PENDING__SHIFT
94805. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
94806. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
94807. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
94808. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
94809. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
94810. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
94811. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
94812. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
94813. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
94814. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
94815. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
94816. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
94817. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
94818. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
94819. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
94820. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
94821. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
94822. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
94823. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
94824. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
94825. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
94826. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
94827. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
94828. BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
94829. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
94830. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
94831. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
94832. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
94833. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
94834. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
94835. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
94836. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
94837. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
94838. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
94839. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
94840. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
94841. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
94842. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
94843. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
94844. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
94845. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
94846. BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
94847. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
94848. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
94849. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
94850. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
94851. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
94852. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
94853. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL__ATC_ENABLE_MASK
94854. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
94855. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL__STU_MASK
94856. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL__STU__SHIFT
94857. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
94858. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
94859. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
94860. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
94861. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
94862. BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
94863. BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST__CAP_ID_MASK
94864. BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST__CAP_ID__SHIFT
94865. BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST__NEXT_PTR_MASK
94866. BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST__NEXT_PTR__SHIFT
94867. BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__DEVICE_TYPE_MASK
94868. BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__DEVICE_TYPE__SHIFT
94869. BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__INT_MESSAGE_NUM_MASK
94870. BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
94871. BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__SLOT_IMPLEMENTED_MASK
94872. BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
94873. BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__VERSION_MASK
94874. BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__VERSION__SHIFT
94875. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
94876. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
94877. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
94878. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
94879. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
94880. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
94881. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
94882. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
94883. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
94884. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
94885. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
94886. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
94887. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
94888. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
94889. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
94890. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
94891. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
94892. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
94893. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
94894. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
94895. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
94896. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
94897. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
94898. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
94899. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
94900. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
94901. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
94902. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
94903. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
94904. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
94905. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
94906. BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
94907. BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG0__TLP_HDR_MASK
94908. BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG0__TLP_HDR__SHIFT
94909. BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG1__TLP_HDR_MASK
94910. BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG1__TLP_HDR__SHIFT
94911. BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG2__TLP_HDR_MASK
94912. BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG2__TLP_HDR__SHIFT
94913. BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG3__TLP_HDR_MASK
94914. BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG3__TLP_HDR__SHIFT
94915. BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
94916. BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
94917. BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
94918. BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
94919. BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
94920. BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
94921. BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
94922. BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
94923. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
94924. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
94925. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
94926. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
94927. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
94928. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
94929. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
94930. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
94931. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
94932. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
94933. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
94934. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
94935. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
94936. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
94937. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
94938. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
94939. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
94940. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
94941. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
94942. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
94943. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
94944. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
94945. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
94946. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
94947. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
94948. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
94949. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
94950. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
94951. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
94952. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
94953. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
94954. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
94955. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
94956. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
94957. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
94958. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
94959. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
94960. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
94961. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
94962. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
94963. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
94964. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
94965. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
94966. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
94967. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
94968. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
94969. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
94970. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
94971. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
94972. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
94973. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
94974. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
94975. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
94976. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
94977. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
94978. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
94979. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
94980. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
94981. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
94982. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
94983. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
94984. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
94985. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
94986. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
94987. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
94988. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
94989. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
94990. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
94991. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
94992. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
94993. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
94994. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
94995. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
94996. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
94997. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
94998. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
94999. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
95000. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
95001. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
95002. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
95003. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
95004. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
95005. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
95006. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
95007. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
95008. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
95009. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
95010. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
95011. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
95012. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
95013. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
95014. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
95015. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
95016. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
95017. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
95018. BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
95019. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
95020. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
95021. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
95022. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
95023. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
95024. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
95025. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
95026. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
95027. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
95028. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
95029. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
95030. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
95031. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
95032. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
95033. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
95034. BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
95035. BIF_CFG_DEV0_EPF0_VF18_PROG_INTERFACE__PROG_INTERFACE_MASK
95036. BIF_CFG_DEV0_EPF0_VF18_PROG_INTERFACE__PROG_INTERFACE__SHIFT
95037. BIF_CFG_DEV0_EPF0_VF18_REVISION_ID__MAJOR_REV_ID_MASK
95038. BIF_CFG_DEV0_EPF0_VF18_REVISION_ID__MAJOR_REV_ID__SHIFT
95039. BIF_CFG_DEV0_EPF0_VF18_REVISION_ID__MINOR_REV_ID_MASK
95040. BIF_CFG_DEV0_EPF0_VF18_REVISION_ID__MINOR_REV_ID__SHIFT
95041. BIF_CFG_DEV0_EPF0_VF18_ROM_BASE_ADDR__BASE_ADDR_MASK
95042. BIF_CFG_DEV0_EPF0_VF18_ROM_BASE_ADDR__BASE_ADDR__SHIFT
95043. BIF_CFG_DEV0_EPF0_VF18_STATUS__CAP_LIST_MASK
95044. BIF_CFG_DEV0_EPF0_VF18_STATUS__CAP_LIST__SHIFT
95045. BIF_CFG_DEV0_EPF0_VF18_STATUS__DEVSEL_TIMING_MASK
95046. BIF_CFG_DEV0_EPF0_VF18_STATUS__DEVSEL_TIMING__SHIFT
95047. BIF_CFG_DEV0_EPF0_VF18_STATUS__FAST_BACK_CAPABLE_MASK
95048. BIF_CFG_DEV0_EPF0_VF18_STATUS__FAST_BACK_CAPABLE__SHIFT
95049. BIF_CFG_DEV0_EPF0_VF18_STATUS__IMMEDIATE_READINESS_MASK
95050. BIF_CFG_DEV0_EPF0_VF18_STATUS__IMMEDIATE_READINESS__SHIFT
95051. BIF_CFG_DEV0_EPF0_VF18_STATUS__INT_STATUS_MASK
95052. BIF_CFG_DEV0_EPF0_VF18_STATUS__INT_STATUS__SHIFT
95053. BIF_CFG_DEV0_EPF0_VF18_STATUS__MASTER_DATA_PARITY_ERROR_MASK
95054. BIF_CFG_DEV0_EPF0_VF18_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
95055. BIF_CFG_DEV0_EPF0_VF18_STATUS__PARITY_ERROR_DETECTED_MASK
95056. BIF_CFG_DEV0_EPF0_VF18_STATUS__PARITY_ERROR_DETECTED__SHIFT
95057. BIF_CFG_DEV0_EPF0_VF18_STATUS__PCI_66_CAP_MASK
95058. BIF_CFG_DEV0_EPF0_VF18_STATUS__PCI_66_CAP__SHIFT
95059. BIF_CFG_DEV0_EPF0_VF18_STATUS__RECEIVED_MASTER_ABORT_MASK
95060. BIF_CFG_DEV0_EPF0_VF18_STATUS__RECEIVED_MASTER_ABORT__SHIFT
95061. BIF_CFG_DEV0_EPF0_VF18_STATUS__RECEIVED_TARGET_ABORT_MASK
95062. BIF_CFG_DEV0_EPF0_VF18_STATUS__RECEIVED_TARGET_ABORT__SHIFT
95063. BIF_CFG_DEV0_EPF0_VF18_STATUS__SIGNALED_SYSTEM_ERROR_MASK
95064. BIF_CFG_DEV0_EPF0_VF18_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
95065. BIF_CFG_DEV0_EPF0_VF18_STATUS__SIGNAL_TARGET_ABORT_MASK
95066. BIF_CFG_DEV0_EPF0_VF18_STATUS__SIGNAL_TARGET_ABORT__SHIFT
95067. BIF_CFG_DEV0_EPF0_VF18_SUB_CLASS__SUB_CLASS_MASK
95068. BIF_CFG_DEV0_EPF0_VF18_SUB_CLASS__SUB_CLASS__SHIFT
95069. BIF_CFG_DEV0_EPF0_VF18_VENDOR_ID__VENDOR_ID_MASK
95070. BIF_CFG_DEV0_EPF0_VF18_VENDOR_ID__VENDOR_ID__SHIFT
95071. BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
95072. BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
95073. BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
95074. BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
95075. BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1__BASE_ADDR_MASK
95076. BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1__BASE_ADDR__SHIFT
95077. BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2__BASE_ADDR_MASK
95078. BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2__BASE_ADDR__SHIFT
95079. BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3__BASE_ADDR_MASK
95080. BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3__BASE_ADDR__SHIFT
95081. BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4__BASE_ADDR_MASK
95082. BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4__BASE_ADDR__SHIFT
95083. BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5__BASE_ADDR_MASK
95084. BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5__BASE_ADDR__SHIFT
95085. BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6__BASE_ADDR_MASK
95086. BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6__BASE_ADDR__SHIFT
95087. BIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS__BASE_CLASS_MASK
95088. BIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS__BASE_CLASS__SHIFT
95089. BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_CAP_MASK
95090. BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_CAP__SHIFT
95091. BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_COMP_MASK
95092. BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_COMP__SHIFT
95093. BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_STRT_MASK
95094. BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_STRT__SHIFT
95095. BIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
95096. BIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
95097. BIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR__CAP_PTR_MASK
95098. BIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR__CAP_PTR__SHIFT
95099. BIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
95100. BIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
95101. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__AD_STEPPING_MASK
95102. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__AD_STEPPING__SHIFT
95103. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__BUS_MASTER_EN_MASK
95104. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__BUS_MASTER_EN__SHIFT
95105. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__FAST_B2B_EN_MASK
95106. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__FAST_B2B_EN__SHIFT
95107. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__INT_DIS_MASK
95108. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__INT_DIS__SHIFT
95109. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__IO_ACCESS_EN_MASK
95110. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__IO_ACCESS_EN__SHIFT
95111. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__MEM_ACCESS_EN_MASK
95112. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__MEM_ACCESS_EN__SHIFT
95113. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
95114. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
95115. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__PAL_SNOOP_EN_MASK
95116. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__PAL_SNOOP_EN__SHIFT
95117. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
95118. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
95119. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__SERR_EN_MASK
95120. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__SERR_EN__SHIFT
95121. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__SPECIAL_CYCLE_EN_MASK
95122. BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
95123. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
95124. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
95125. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
95126. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
95127. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
95128. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
95129. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
95130. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
95131. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
95132. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
95133. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
95134. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
95135. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
95136. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
95137. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
95138. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
95139. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
95140. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
95141. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
95142. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
95143. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
95144. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
95145. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
95146. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
95147. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
95148. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
95149. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
95150. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
95151. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
95152. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
95153. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
95154. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
95155. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
95156. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
95157. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
95158. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
95159. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
95160. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
95161. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
95162. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
95163. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
95164. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
95165. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
95166. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
95167. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__EXTENDED_TAG_MASK
95168. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
95169. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__FLR_CAPABLE_MASK
95170. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
95171. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
95172. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
95173. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
95174. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
95175. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
95176. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
95177. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__PHANTOM_FUNC_MASK
95178. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
95179. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
95180. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
95181. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
95182. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
95183. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
95184. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
95185. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
95186. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
95187. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
95188. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
95189. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
95190. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
95191. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
95192. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
95193. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
95194. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
95195. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
95196. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
95197. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
95198. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
95199. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__LTR_EN_MASK
95200. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__LTR_EN__SHIFT
95201. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__OBFF_EN_MASK
95202. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__OBFF_EN__SHIFT
95203. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
95204. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
95205. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
95206. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
95207. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__CORR_ERR_EN_MASK
95208. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
95209. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
95210. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
95211. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
95212. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
95213. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__INITIATE_FLR_MASK
95214. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
95215. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
95216. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
95217. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
95218. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
95219. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
95220. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
95221. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
95222. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
95223. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
95224. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
95225. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
95226. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
95227. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__USR_REPORT_EN_MASK
95228. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
95229. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID__DEVICE_ID_MASK
95230. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID__DEVICE_ID__SHIFT
95231. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2__RESERVED_MASK
95232. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2__RESERVED__SHIFT
95233. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__AUX_PWR_MASK
95234. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__AUX_PWR__SHIFT
95235. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__CORR_ERR_MASK
95236. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__CORR_ERR__SHIFT
95237. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
95238. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
95239. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__FATAL_ERR_MASK
95240. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__FATAL_ERR__SHIFT
95241. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
95242. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
95243. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
95244. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
95245. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__USR_DETECTED_MASK
95246. BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__USR_DETECTED__SHIFT
95247. BIF_CFG_DEV0_EPF0_VF19_0_HEADER__DEVICE_TYPE_MASK
95248. BIF_CFG_DEV0_EPF0_VF19_0_HEADER__DEVICE_TYPE__SHIFT
95249. BIF_CFG_DEV0_EPF0_VF19_0_HEADER__HEADER_TYPE_MASK
95250. BIF_CFG_DEV0_EPF0_VF19_0_HEADER__HEADER_TYPE__SHIFT
95251. BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
95252. BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
95253. BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
95254. BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
95255. BIF_CFG_DEV0_EPF0_VF19_0_LATENCY__LATENCY_TIMER_MASK
95256. BIF_CFG_DEV0_EPF0_VF19_0_LATENCY__LATENCY_TIMER__SHIFT
95257. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
95258. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
95259. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
95260. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
95261. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
95262. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
95263. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
95264. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
95265. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
95266. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
95267. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
95268. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
95269. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
95270. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
95271. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
95272. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
95273. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
95274. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
95275. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
95276. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
95277. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
95278. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
95279. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__L1_EXIT_LATENCY_MASK
95280. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
95281. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
95282. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
95283. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_SPEED_MASK
95284. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_SPEED__SHIFT
95285. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_WIDTH_MASK
95286. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_WIDTH__SHIFT
95287. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__PM_SUPPORT_MASK
95288. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__PM_SUPPORT__SHIFT
95289. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__PORT_NUMBER_MASK
95290. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__PORT_NUMBER__SHIFT
95291. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
95292. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
95293. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
95294. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
95295. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
95296. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
95297. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
95298. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
95299. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
95300. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
95301. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
95302. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
95303. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
95304. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
95305. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
95306. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
95307. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__XMIT_MARGIN_MASK
95308. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
95309. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
95310. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
95311. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
95312. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
95313. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
95314. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
95315. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__EXTENDED_SYNC_MASK
95316. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
95317. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
95318. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
95319. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
95320. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
95321. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
95322. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
95323. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_DIS_MASK
95324. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_DIS__SHIFT
95325. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__PM_CONTROL_MASK
95326. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__PM_CONTROL__SHIFT
95327. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
95328. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
95329. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__RETRAIN_LINK_MASK
95330. BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__RETRAIN_LINK__SHIFT
95331. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
95332. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
95333. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
95334. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
95335. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
95336. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
95337. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
95338. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
95339. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
95340. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
95341. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
95342. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
95343. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
95344. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
95345. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
95346. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
95347. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
95348. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
95349. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
95350. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
95351. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
95352. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
95353. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
95354. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
95355. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__DL_ACTIVE_MASK
95356. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__DL_ACTIVE__SHIFT
95357. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
95358. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
95359. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
95360. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
95361. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_TRAINING_MASK
95362. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_TRAINING__SHIFT
95363. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
95364. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
95365. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
95366. BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
95367. BIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY__MAX_LAT_MASK
95368. BIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY__MAX_LAT__SHIFT
95369. BIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT__MIN_GNT_MASK
95370. BIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT__MIN_GNT__SHIFT
95371. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST__CAP_ID_MASK
95372. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST__CAP_ID__SHIFT
95373. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST__NEXT_PTR_MASK
95374. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
95375. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_EN_MASK
95376. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
95377. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
95378. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
95379. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
95380. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
95381. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA__MSIX_PBA_BIR_MASK
95382. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
95383. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
95384. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
95385. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
95386. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
95387. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
95388. BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
95389. BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST__CAP_ID_MASK
95390. BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST__CAP_ID__SHIFT
95391. BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST__NEXT_PTR_MASK
95392. BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
95393. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64__MSI_MASK_64_MASK
95394. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64__MSI_MASK_64__SHIFT
95395. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK__MSI_MASK_MASK
95396. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK__MSI_MASK__SHIFT
95397. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
95398. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
95399. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
95400. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
95401. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_64BIT_MASK
95402. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
95403. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_EN_MASK
95404. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_EN__SHIFT
95405. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
95406. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
95407. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
95408. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
95409. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
95410. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
95411. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
95412. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
95413. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA__MSI_DATA_MASK
95414. BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA__MSI_DATA__SHIFT
95415. BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64__MSI_PENDING_64_MASK
95416. BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
95417. BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING__MSI_PENDING_MASK
95418. BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING__MSI_PENDING__SHIFT
95419. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
95420. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
95421. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
95422. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
95423. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
95424. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
95425. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
95426. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
95427. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
95428. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
95429. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
95430. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
95431. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
95432. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
95433. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
95434. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
95435. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
95436. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
95437. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
95438. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
95439. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
95440. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
95441. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
95442. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
95443. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
95444. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
95445. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
95446. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
95447. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
95448. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
95449. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
95450. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
95451. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
95452. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
95453. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
95454. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
95455. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
95456. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
95457. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
95458. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
95459. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
95460. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
95461. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
95462. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
95463. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
95464. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
95465. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
95466. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
95467. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
95468. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
95469. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL__STU_MASK
95470. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL__STU__SHIFT
95471. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
95472. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
95473. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
95474. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
95475. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
95476. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
95477. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST__CAP_ID_MASK
95478. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST__CAP_ID__SHIFT
95479. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST__NEXT_PTR_MASK
95480. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
95481. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__DEVICE_TYPE_MASK
95482. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__DEVICE_TYPE__SHIFT
95483. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
95484. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
95485. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
95486. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
95487. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__VERSION_MASK
95488. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__VERSION__SHIFT
95489. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
95490. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
95491. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
95492. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
95493. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
95494. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
95495. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
95496. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
95497. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
95498. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
95499. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
95500. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
95501. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
95502. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
95503. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
95504. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
95505. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
95506. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
95507. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
95508. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
95509. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
95510. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
95511. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
95512. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
95513. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
95514. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
95515. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
95516. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
95517. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
95518. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
95519. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
95520. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
95521. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0__TLP_HDR_MASK
95522. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
95523. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1__TLP_HDR_MASK
95524. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
95525. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2__TLP_HDR_MASK
95526. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
95527. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3__TLP_HDR_MASK
95528. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
95529. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
95530. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
95531. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
95532. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
95533. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
95534. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
95535. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
95536. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
95537. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
95538. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
95539. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
95540. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
95541. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
95542. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
95543. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
95544. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
95545. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
95546. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
95547. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
95548. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
95549. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
95550. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
95551. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
95552. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
95553. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
95554. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
95555. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
95556. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
95557. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
95558. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
95559. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
95560. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
95561. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
95562. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
95563. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
95564. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
95565. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
95566. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
95567. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
95568. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
95569. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
95570. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
95571. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
95572. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
95573. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
95574. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
95575. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
95576. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
95577. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
95578. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
95579. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
95580. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
95581. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
95582. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
95583. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
95584. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
95585. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
95586. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
95587. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
95588. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
95589. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
95590. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
95591. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
95592. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
95593. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
95594. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
95595. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
95596. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
95597. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
95598. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
95599. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
95600. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
95601. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
95602. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
95603. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
95604. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
95605. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
95606. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
95607. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
95608. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
95609. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
95610. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
95611. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
95612. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
95613. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
95614. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
95615. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
95616. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
95617. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
95618. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
95619. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
95620. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
95621. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
95622. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
95623. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
95624. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
95625. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
95626. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
95627. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
95628. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
95629. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
95630. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
95631. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
95632. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
95633. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
95634. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
95635. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
95636. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
95637. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
95638. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
95639. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
95640. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
95641. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
95642. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
95643. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
95644. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
95645. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
95646. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
95647. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
95648. BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
95649. BIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE__PROG_INTERFACE_MASK
95650. BIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
95651. BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID__MAJOR_REV_ID_MASK
95652. BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID__MAJOR_REV_ID__SHIFT
95653. BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID__MINOR_REV_ID_MASK
95654. BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID__MINOR_REV_ID__SHIFT
95655. BIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR__BASE_ADDR_MASK
95656. BIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
95657. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__CAP_LIST_MASK
95658. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__CAP_LIST__SHIFT
95659. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__DEVSEL_TIMING_MASK
95660. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__DEVSEL_TIMING__SHIFT
95661. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__FAST_BACK_CAPABLE_MASK
95662. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__FAST_BACK_CAPABLE__SHIFT
95663. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__IMMEDIATE_READINESS_MASK
95664. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__IMMEDIATE_READINESS__SHIFT
95665. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__INT_STATUS_MASK
95666. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__INT_STATUS__SHIFT
95667. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
95668. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
95669. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__PARITY_ERROR_DETECTED_MASK
95670. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
95671. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__PCI_66_CAP_MASK
95672. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__PCI_66_CAP__SHIFT
95673. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__RECEIVED_MASTER_ABORT_MASK
95674. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
95675. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__RECEIVED_TARGET_ABORT_MASK
95676. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
95677. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
95678. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
95679. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__SIGNAL_TARGET_ABORT_MASK
95680. BIF_CFG_DEV0_EPF0_VF19_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
95681. BIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS__SUB_CLASS_MASK
95682. BIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS__SUB_CLASS__SHIFT
95683. BIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID__VENDOR_ID_MASK
95684. BIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID__VENDOR_ID__SHIFT
95685. BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
95686. BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
95687. BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
95688. BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
95689. BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1__BASE_ADDR_MASK
95690. BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1__BASE_ADDR__SHIFT
95691. BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2__BASE_ADDR_MASK
95692. BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2__BASE_ADDR__SHIFT
95693. BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3__BASE_ADDR_MASK
95694. BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3__BASE_ADDR__SHIFT
95695. BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4__BASE_ADDR_MASK
95696. BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4__BASE_ADDR__SHIFT
95697. BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5__BASE_ADDR_MASK
95698. BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5__BASE_ADDR__SHIFT
95699. BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6__BASE_ADDR_MASK
95700. BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6__BASE_ADDR__SHIFT
95701. BIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS__BASE_CLASS_MASK
95702. BIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS__BASE_CLASS__SHIFT
95703. BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_CAP_MASK
95704. BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_CAP__SHIFT
95705. BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_COMP_MASK
95706. BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_COMP__SHIFT
95707. BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_STRT_MASK
95708. BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_STRT__SHIFT
95709. BIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
95710. BIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
95711. BIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR__CAP_PTR_MASK
95712. BIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR__CAP_PTR__SHIFT
95713. BIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
95714. BIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
95715. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__AD_STEPPING_MASK
95716. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__AD_STEPPING__SHIFT
95717. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__BUS_MASTER_EN_MASK
95718. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__BUS_MASTER_EN__SHIFT
95719. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__FAST_B2B_EN_MASK
95720. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__FAST_B2B_EN__SHIFT
95721. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__INT_DIS_MASK
95722. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__INT_DIS__SHIFT
95723. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__IO_ACCESS_EN_MASK
95724. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__IO_ACCESS_EN__SHIFT
95725. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__MEM_ACCESS_EN_MASK
95726. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__MEM_ACCESS_EN__SHIFT
95727. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
95728. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
95729. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__PAL_SNOOP_EN_MASK
95730. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__PAL_SNOOP_EN__SHIFT
95731. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
95732. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
95733. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__SERR_EN_MASK
95734. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__SERR_EN__SHIFT
95735. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__SPECIAL_CYCLE_EN_MASK
95736. BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
95737. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
95738. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
95739. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
95740. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
95741. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
95742. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
95743. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
95744. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
95745. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
95746. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
95747. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
95748. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
95749. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
95750. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
95751. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
95752. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
95753. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
95754. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
95755. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
95756. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
95757. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
95758. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
95759. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
95760. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
95761. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
95762. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
95763. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
95764. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
95765. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
95766. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
95767. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
95768. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
95769. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
95770. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
95771. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
95772. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
95773. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
95774. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
95775. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
95776. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
95777. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
95778. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
95779. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
95780. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
95781. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__EXTENDED_TAG_MASK
95782. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
95783. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__FLR_CAPABLE_MASK
95784. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
95785. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
95786. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
95787. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
95788. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
95789. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
95790. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
95791. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__PHANTOM_FUNC_MASK
95792. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
95793. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
95794. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
95795. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
95796. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
95797. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
95798. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
95799. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
95800. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
95801. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
95802. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
95803. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
95804. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
95805. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
95806. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
95807. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
95808. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
95809. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
95810. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
95811. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
95812. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
95813. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__LTR_EN_MASK
95814. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__LTR_EN__SHIFT
95815. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__OBFF_EN_MASK
95816. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__OBFF_EN__SHIFT
95817. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
95818. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
95819. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
95820. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
95821. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__CORR_ERR_EN_MASK
95822. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
95823. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
95824. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
95825. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
95826. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
95827. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__INITIATE_FLR_MASK
95828. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
95829. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
95830. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
95831. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
95832. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
95833. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
95834. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
95835. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
95836. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
95837. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
95838. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
95839. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
95840. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
95841. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__USR_REPORT_EN_MASK
95842. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
95843. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID__DEVICE_ID_MASK
95844. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID__DEVICE_ID__SHIFT
95845. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2__RESERVED_MASK
95846. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2__RESERVED__SHIFT
95847. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__AUX_PWR_MASK
95848. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__AUX_PWR__SHIFT
95849. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__CORR_ERR_MASK
95850. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__CORR_ERR__SHIFT
95851. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
95852. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
95853. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__FATAL_ERR_MASK
95854. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__FATAL_ERR__SHIFT
95855. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
95856. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
95857. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
95858. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
95859. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__USR_DETECTED_MASK
95860. BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__USR_DETECTED__SHIFT
95861. BIF_CFG_DEV0_EPF0_VF19_1_HEADER__DEVICE_TYPE_MASK
95862. BIF_CFG_DEV0_EPF0_VF19_1_HEADER__DEVICE_TYPE__SHIFT
95863. BIF_CFG_DEV0_EPF0_VF19_1_HEADER__HEADER_TYPE_MASK
95864. BIF_CFG_DEV0_EPF0_VF19_1_HEADER__HEADER_TYPE__SHIFT
95865. BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
95866. BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
95867. BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
95868. BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
95869. BIF_CFG_DEV0_EPF0_VF19_1_LATENCY__LATENCY_TIMER_MASK
95870. BIF_CFG_DEV0_EPF0_VF19_1_LATENCY__LATENCY_TIMER__SHIFT
95871. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
95872. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
95873. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
95874. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
95875. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
95876. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
95877. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
95878. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
95879. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
95880. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
95881. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
95882. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
95883. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
95884. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
95885. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
95886. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
95887. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
95888. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
95889. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
95890. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
95891. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
95892. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
95893. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__L1_EXIT_LATENCY_MASK
95894. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
95895. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
95896. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
95897. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_SPEED_MASK
95898. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_SPEED__SHIFT
95899. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_WIDTH_MASK
95900. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_WIDTH__SHIFT
95901. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__PM_SUPPORT_MASK
95902. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__PM_SUPPORT__SHIFT
95903. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__PORT_NUMBER_MASK
95904. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__PORT_NUMBER__SHIFT
95905. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
95906. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
95907. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
95908. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
95909. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
95910. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
95911. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
95912. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
95913. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
95914. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
95915. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
95916. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
95917. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
95918. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
95919. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
95920. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
95921. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__XMIT_MARGIN_MASK
95922. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
95923. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
95924. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
95925. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
95926. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
95927. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
95928. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
95929. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__EXTENDED_SYNC_MASK
95930. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
95931. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
95932. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
95933. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
95934. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
95935. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
95936. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
95937. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_DIS_MASK
95938. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_DIS__SHIFT
95939. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__PM_CONTROL_MASK
95940. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__PM_CONTROL__SHIFT
95941. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
95942. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
95943. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__RETRAIN_LINK_MASK
95944. BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__RETRAIN_LINK__SHIFT
95945. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
95946. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
95947. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
95948. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
95949. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
95950. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
95951. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
95952. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
95953. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
95954. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
95955. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
95956. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
95957. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
95958. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
95959. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
95960. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
95961. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
95962. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
95963. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
95964. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
95965. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
95966. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
95967. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
95968. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
95969. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__DL_ACTIVE_MASK
95970. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__DL_ACTIVE__SHIFT
95971. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
95972. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
95973. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
95974. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
95975. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_TRAINING_MASK
95976. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_TRAINING__SHIFT
95977. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
95978. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
95979. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
95980. BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
95981. BIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY__MAX_LAT_MASK
95982. BIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY__MAX_LAT__SHIFT
95983. BIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT__MIN_GNT_MASK
95984. BIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT__MIN_GNT__SHIFT
95985. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST__CAP_ID_MASK
95986. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST__CAP_ID__SHIFT
95987. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST__NEXT_PTR_MASK
95988. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
95989. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_EN_MASK
95990. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
95991. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
95992. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
95993. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
95994. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
95995. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA__MSIX_PBA_BIR_MASK
95996. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
95997. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
95998. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
95999. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
96000. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
96001. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
96002. BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
96003. BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST__CAP_ID_MASK
96004. BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST__CAP_ID__SHIFT
96005. BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST__NEXT_PTR_MASK
96006. BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
96007. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64__MSI_MASK_64_MASK
96008. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64__MSI_MASK_64__SHIFT
96009. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK__MSI_MASK_MASK
96010. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK__MSI_MASK__SHIFT
96011. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
96012. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
96013. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
96014. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
96015. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_64BIT_MASK
96016. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
96017. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_EN_MASK
96018. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_EN__SHIFT
96019. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
96020. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
96021. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
96022. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
96023. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
96024. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
96025. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
96026. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
96027. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA__MSI_DATA_MASK
96028. BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA__MSI_DATA__SHIFT
96029. BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64__MSI_PENDING_64_MASK
96030. BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
96031. BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING__MSI_PENDING_MASK
96032. BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING__MSI_PENDING__SHIFT
96033. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
96034. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
96035. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
96036. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
96037. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
96038. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
96039. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
96040. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
96041. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
96042. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
96043. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
96044. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
96045. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
96046. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
96047. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
96048. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
96049. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
96050. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
96051. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
96052. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
96053. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
96054. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
96055. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
96056. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
96057. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
96058. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
96059. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
96060. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
96061. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
96062. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
96063. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
96064. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
96065. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
96066. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
96067. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
96068. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
96069. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
96070. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
96071. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
96072. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
96073. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
96074. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
96075. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
96076. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
96077. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
96078. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
96079. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
96080. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
96081. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
96082. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
96083. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL__STU_MASK
96084. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL__STU__SHIFT
96085. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
96086. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
96087. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
96088. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
96089. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
96090. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
96091. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST__CAP_ID_MASK
96092. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST__CAP_ID__SHIFT
96093. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST__NEXT_PTR_MASK
96094. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
96095. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__DEVICE_TYPE_MASK
96096. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__DEVICE_TYPE__SHIFT
96097. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
96098. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
96099. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
96100. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
96101. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__VERSION_MASK
96102. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__VERSION__SHIFT
96103. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
96104. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
96105. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
96106. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
96107. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
96108. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
96109. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
96110. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
96111. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
96112. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
96113. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
96114. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
96115. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
96116. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
96117. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
96118. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
96119. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
96120. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
96121. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
96122. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
96123. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
96124. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
96125. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
96126. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
96127. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
96128. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
96129. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
96130. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
96131. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
96132. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
96133. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
96134. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
96135. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0__TLP_HDR_MASK
96136. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
96137. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1__TLP_HDR_MASK
96138. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
96139. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2__TLP_HDR_MASK
96140. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
96141. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3__TLP_HDR_MASK
96142. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
96143. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
96144. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
96145. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
96146. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
96147. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
96148. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
96149. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
96150. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
96151. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
96152. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
96153. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
96154. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
96155. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
96156. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
96157. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
96158. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
96159. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
96160. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
96161. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
96162. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
96163. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
96164. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
96165. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
96166. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
96167. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
96168. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
96169. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
96170. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
96171. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
96172. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
96173. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
96174. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
96175. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
96176. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
96177. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
96178. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
96179. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
96180. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
96181. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
96182. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
96183. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
96184. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
96185. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
96186. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
96187. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
96188. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
96189. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
96190. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
96191. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
96192. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
96193. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
96194. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
96195. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
96196. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
96197. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
96198. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
96199. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
96200. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
96201. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
96202. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
96203. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
96204. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
96205. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
96206. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
96207. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
96208. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
96209. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
96210. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
96211. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
96212. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
96213. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
96214. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
96215. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
96216. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
96217. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
96218. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
96219. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
96220. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
96221. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
96222. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
96223. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
96224. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
96225. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
96226. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
96227. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
96228. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
96229. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
96230. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
96231. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
96232. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
96233. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
96234. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
96235. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
96236. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
96237. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
96238. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
96239. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
96240. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
96241. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
96242. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
96243. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
96244. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
96245. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
96246. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
96247. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
96248. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
96249. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
96250. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
96251. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
96252. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
96253. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
96254. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
96255. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
96256. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
96257. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
96258. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
96259. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
96260. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
96261. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
96262. BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
96263. BIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE__PROG_INTERFACE_MASK
96264. BIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
96265. BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID__MAJOR_REV_ID_MASK
96266. BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID__MAJOR_REV_ID__SHIFT
96267. BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID__MINOR_REV_ID_MASK
96268. BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID__MINOR_REV_ID__SHIFT
96269. BIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR__BASE_ADDR_MASK
96270. BIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
96271. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__CAP_LIST_MASK
96272. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__CAP_LIST__SHIFT
96273. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__DEVSEL_TIMING_MASK
96274. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__DEVSEL_TIMING__SHIFT
96275. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__FAST_BACK_CAPABLE_MASK
96276. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__FAST_BACK_CAPABLE__SHIFT
96277. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__IMMEDIATE_READINESS_MASK
96278. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__IMMEDIATE_READINESS__SHIFT
96279. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__INT_STATUS_MASK
96280. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__INT_STATUS__SHIFT
96281. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
96282. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
96283. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__PARITY_ERROR_DETECTED_MASK
96284. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
96285. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__PCI_66_CAP_MASK
96286. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__PCI_66_CAP__SHIFT
96287. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__RECEIVED_MASTER_ABORT_MASK
96288. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
96289. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__RECEIVED_TARGET_ABORT_MASK
96290. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
96291. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
96292. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
96293. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__SIGNAL_TARGET_ABORT_MASK
96294. BIF_CFG_DEV0_EPF0_VF19_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
96295. BIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS__SUB_CLASS_MASK
96296. BIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS__SUB_CLASS__SHIFT
96297. BIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID__VENDOR_ID_MASK
96298. BIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID__VENDOR_ID__SHIFT
96299. BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID__SUBSYSTEM_ID_MASK
96300. BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
96301. BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
96302. BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
96303. BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_1__BASE_ADDR_MASK
96304. BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_1__BASE_ADDR__SHIFT
96305. BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_2__BASE_ADDR_MASK
96306. BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_2__BASE_ADDR__SHIFT
96307. BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_3__BASE_ADDR_MASK
96308. BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_3__BASE_ADDR__SHIFT
96309. BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_4__BASE_ADDR_MASK
96310. BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_4__BASE_ADDR__SHIFT
96311. BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_5__BASE_ADDR_MASK
96312. BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_5__BASE_ADDR__SHIFT
96313. BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_6__BASE_ADDR_MASK
96314. BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_6__BASE_ADDR__SHIFT
96315. BIF_CFG_DEV0_EPF0_VF19_BASE_CLASS__BASE_CLASS_MASK
96316. BIF_CFG_DEV0_EPF0_VF19_BASE_CLASS__BASE_CLASS__SHIFT
96317. BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_CAP_MASK
96318. BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_CAP__SHIFT
96319. BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_COMP_MASK
96320. BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_COMP__SHIFT
96321. BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_STRT_MASK
96322. BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_STRT__SHIFT
96323. BIF_CFG_DEV0_EPF0_VF19_CACHE_LINE__CACHE_LINE_SIZE_MASK
96324. BIF_CFG_DEV0_EPF0_VF19_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
96325. BIF_CFG_DEV0_EPF0_VF19_CAP_PTR__CAP_PTR_MASK
96326. BIF_CFG_DEV0_EPF0_VF19_CAP_PTR__CAP_PTR__SHIFT
96327. BIF_CFG_DEV0_EPF0_VF19_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
96328. BIF_CFG_DEV0_EPF0_VF19_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
96329. BIF_CFG_DEV0_EPF0_VF19_COMMAND__AD_STEPPING_MASK
96330. BIF_CFG_DEV0_EPF0_VF19_COMMAND__AD_STEPPING__SHIFT
96331. BIF_CFG_DEV0_EPF0_VF19_COMMAND__BUS_MASTER_EN_MASK
96332. BIF_CFG_DEV0_EPF0_VF19_COMMAND__BUS_MASTER_EN__SHIFT
96333. BIF_CFG_DEV0_EPF0_VF19_COMMAND__FAST_B2B_EN_MASK
96334. BIF_CFG_DEV0_EPF0_VF19_COMMAND__FAST_B2B_EN__SHIFT
96335. BIF_CFG_DEV0_EPF0_VF19_COMMAND__INT_DIS_MASK
96336. BIF_CFG_DEV0_EPF0_VF19_COMMAND__INT_DIS__SHIFT
96337. BIF_CFG_DEV0_EPF0_VF19_COMMAND__IO_ACCESS_EN_MASK
96338. BIF_CFG_DEV0_EPF0_VF19_COMMAND__IO_ACCESS_EN__SHIFT
96339. BIF_CFG_DEV0_EPF0_VF19_COMMAND__MEM_ACCESS_EN_MASK
96340. BIF_CFG_DEV0_EPF0_VF19_COMMAND__MEM_ACCESS_EN__SHIFT
96341. BIF_CFG_DEV0_EPF0_VF19_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
96342. BIF_CFG_DEV0_EPF0_VF19_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
96343. BIF_CFG_DEV0_EPF0_VF19_COMMAND__PAL_SNOOP_EN_MASK
96344. BIF_CFG_DEV0_EPF0_VF19_COMMAND__PAL_SNOOP_EN__SHIFT
96345. BIF_CFG_DEV0_EPF0_VF19_COMMAND__PARITY_ERROR_RESPONSE_MASK
96346. BIF_CFG_DEV0_EPF0_VF19_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
96347. BIF_CFG_DEV0_EPF0_VF19_COMMAND__SERR_EN_MASK
96348. BIF_CFG_DEV0_EPF0_VF19_COMMAND__SERR_EN__SHIFT
96349. BIF_CFG_DEV0_EPF0_VF19_COMMAND__SPECIAL_CYCLE_EN_MASK
96350. BIF_CFG_DEV0_EPF0_VF19_COMMAND__SPECIAL_CYCLE_EN__SHIFT
96351. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
96352. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
96353. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
96354. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
96355. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
96356. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
96357. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
96358. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
96359. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
96360. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
96361. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
96362. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
96363. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
96364. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
96365. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
96366. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
96367. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
96368. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
96369. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
96370. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
96371. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
96372. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
96373. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__FRS_SUPPORTED_MASK
96374. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
96375. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
96376. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
96377. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__LTR_SUPPORTED_MASK
96378. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
96379. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
96380. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
96381. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
96382. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
96383. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__OBFF_SUPPORTED_MASK
96384. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
96385. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
96386. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
96387. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
96388. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
96389. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
96390. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
96391. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
96392. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
96393. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
96394. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
96395. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__EXTENDED_TAG_MASK
96396. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__EXTENDED_TAG__SHIFT
96397. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__FLR_CAPABLE_MASK
96398. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__FLR_CAPABLE__SHIFT
96399. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
96400. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
96401. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
96402. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
96403. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
96404. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
96405. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__PHANTOM_FUNC_MASK
96406. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__PHANTOM_FUNC__SHIFT
96407. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
96408. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
96409. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
96410. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
96411. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
96412. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
96413. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
96414. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
96415. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
96416. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
96417. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
96418. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
96419. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
96420. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
96421. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
96422. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
96423. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
96424. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
96425. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
96426. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
96427. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__LTR_EN_MASK
96428. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__LTR_EN__SHIFT
96429. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__OBFF_EN_MASK
96430. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__OBFF_EN__SHIFT
96431. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
96432. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
96433. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
96434. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
96435. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__CORR_ERR_EN_MASK
96436. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__CORR_ERR_EN__SHIFT
96437. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
96438. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
96439. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__FATAL_ERR_EN_MASK
96440. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
96441. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__INITIATE_FLR_MASK
96442. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__INITIATE_FLR__SHIFT
96443. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
96444. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
96445. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
96446. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
96447. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
96448. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
96449. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__NO_SNOOP_EN_MASK
96450. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
96451. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
96452. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
96453. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__RELAXED_ORD_EN_MASK
96454. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
96455. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__USR_REPORT_EN_MASK
96456. BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__USR_REPORT_EN__SHIFT
96457. BIF_CFG_DEV0_EPF0_VF19_DEVICE_ID__DEVICE_ID_MASK
96458. BIF_CFG_DEV0_EPF0_VF19_DEVICE_ID__DEVICE_ID__SHIFT
96459. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS2__RESERVED_MASK
96460. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS2__RESERVED__SHIFT
96461. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__AUX_PWR_MASK
96462. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__AUX_PWR__SHIFT
96463. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__CORR_ERR_MASK
96464. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__CORR_ERR__SHIFT
96465. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
96466. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
96467. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__FATAL_ERR_MASK
96468. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__FATAL_ERR__SHIFT
96469. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__NON_FATAL_ERR_MASK
96470. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
96471. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
96472. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
96473. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__USR_DETECTED_MASK
96474. BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__USR_DETECTED__SHIFT
96475. BIF_CFG_DEV0_EPF0_VF19_HEADER__DEVICE_TYPE_MASK
96476. BIF_CFG_DEV0_EPF0_VF19_HEADER__DEVICE_TYPE__SHIFT
96477. BIF_CFG_DEV0_EPF0_VF19_HEADER__HEADER_TYPE_MASK
96478. BIF_CFG_DEV0_EPF0_VF19_HEADER__HEADER_TYPE__SHIFT
96479. BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_LINE__INTERRUPT_LINE_MASK
96480. BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
96481. BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_PIN__INTERRUPT_PIN_MASK
96482. BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
96483. BIF_CFG_DEV0_EPF0_VF19_LATENCY__LATENCY_TIMER_MASK
96484. BIF_CFG_DEV0_EPF0_VF19_LATENCY__LATENCY_TIMER__SHIFT
96485. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
96486. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
96487. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
96488. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
96489. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
96490. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
96491. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
96492. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
96493. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
96494. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
96495. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
96496. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
96497. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
96498. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
96499. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
96500. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
96501. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
96502. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
96503. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
96504. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
96505. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__L0S_EXIT_LATENCY_MASK
96506. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
96507. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__L1_EXIT_LATENCY_MASK
96508. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__L1_EXIT_LATENCY__SHIFT
96509. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
96510. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
96511. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_SPEED_MASK
96512. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_SPEED__SHIFT
96513. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_WIDTH_MASK
96514. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_WIDTH__SHIFT
96515. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__PM_SUPPORT_MASK
96516. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__PM_SUPPORT__SHIFT
96517. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__PORT_NUMBER_MASK
96518. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__PORT_NUMBER__SHIFT
96519. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
96520. BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
96521. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
96522. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
96523. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__COMPLIANCE_SOS_MASK
96524. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
96525. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__ENTER_COMPLIANCE_MASK
96526. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
96527. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
96528. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
96529. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
96530. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
96531. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
96532. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
96533. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__TARGET_LINK_SPEED_MASK
96534. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
96535. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__XMIT_MARGIN_MASK
96536. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__XMIT_MARGIN__SHIFT
96537. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
96538. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
96539. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__COMMON_CLOCK_CFG_MASK
96540. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
96541. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
96542. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
96543. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__EXTENDED_SYNC_MASK
96544. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__EXTENDED_SYNC__SHIFT
96545. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
96546. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
96547. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
96548. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
96549. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
96550. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
96551. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_DIS_MASK
96552. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_DIS__SHIFT
96553. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__PM_CONTROL_MASK
96554. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__PM_CONTROL__SHIFT
96555. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__READ_CPL_BOUNDARY_MASK
96556. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
96557. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__RETRAIN_LINK_MASK
96558. BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__RETRAIN_LINK__SHIFT
96559. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
96560. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
96561. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
96562. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
96563. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
96564. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
96565. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
96566. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
96567. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
96568. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
96569. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
96570. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
96571. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
96572. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
96573. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
96574. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
96575. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
96576. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
96577. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
96578. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
96579. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
96580. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
96581. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__CURRENT_LINK_SPEED_MASK
96582. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
96583. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__DL_ACTIVE_MASK
96584. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__DL_ACTIVE__SHIFT
96585. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
96586. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
96587. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
96588. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
96589. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_TRAINING_MASK
96590. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_TRAINING__SHIFT
96591. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
96592. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
96593. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__SLOT_CLOCK_CFG_MASK
96594. BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
96595. BIF_CFG_DEV0_EPF0_VF19_MAX_LATENCY__MAX_LAT_MASK
96596. BIF_CFG_DEV0_EPF0_VF19_MAX_LATENCY__MAX_LAT__SHIFT
96597. BIF_CFG_DEV0_EPF0_VF19_MIN_GRANT__MIN_GNT_MASK
96598. BIF_CFG_DEV0_EPF0_VF19_MIN_GRANT__MIN_GNT__SHIFT
96599. BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST__CAP_ID_MASK
96600. BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST__CAP_ID__SHIFT
96601. BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST__NEXT_PTR_MASK
96602. BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST__NEXT_PTR__SHIFT
96603. BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_EN_MASK
96604. BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_EN__SHIFT
96605. BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
96606. BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
96607. BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
96608. BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
96609. BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA__MSIX_PBA_BIR_MASK
96610. BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA__MSIX_PBA_BIR__SHIFT
96611. BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA__MSIX_PBA_OFFSET_MASK
96612. BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
96613. BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE__MSIX_TABLE_BIR_MASK
96614. BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
96615. BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
96616. BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
96617. BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST__CAP_ID_MASK
96618. BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST__CAP_ID__SHIFT
96619. BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST__NEXT_PTR_MASK
96620. BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST__NEXT_PTR__SHIFT
96621. BIF_CFG_DEV0_EPF0_VF19_MSI_MASK_64__MSI_MASK_64_MASK
96622. BIF_CFG_DEV0_EPF0_VF19_MSI_MASK_64__MSI_MASK_64__SHIFT
96623. BIF_CFG_DEV0_EPF0_VF19_MSI_MASK__MSI_MASK_MASK
96624. BIF_CFG_DEV0_EPF0_VF19_MSI_MASK__MSI_MASK__SHIFT
96625. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
96626. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
96627. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
96628. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
96629. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_64BIT_MASK
96630. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_64BIT__SHIFT
96631. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_EN_MASK
96632. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_EN__SHIFT
96633. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
96634. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
96635. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
96636. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
96637. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
96638. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
96639. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA_64__MSI_DATA_64_MASK
96640. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
96641. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA__MSI_DATA_MASK
96642. BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA__MSI_DATA__SHIFT
96643. BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING_64__MSI_PENDING_64_MASK
96644. BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING_64__MSI_PENDING_64__SHIFT
96645. BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING__MSI_PENDING_MASK
96646. BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING__MSI_PENDING__SHIFT
96647. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
96648. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
96649. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
96650. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
96651. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
96652. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
96653. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
96654. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
96655. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
96656. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
96657. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
96658. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
96659. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
96660. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
96661. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
96662. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
96663. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
96664. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
96665. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
96666. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
96667. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
96668. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
96669. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
96670. BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
96671. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
96672. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
96673. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
96674. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
96675. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
96676. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
96677. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
96678. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
96679. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
96680. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
96681. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
96682. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
96683. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
96684. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
96685. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
96686. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
96687. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
96688. BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
96689. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
96690. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
96691. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
96692. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
96693. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
96694. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
96695. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL__ATC_ENABLE_MASK
96696. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
96697. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL__STU_MASK
96698. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL__STU__SHIFT
96699. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
96700. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
96701. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
96702. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
96703. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
96704. BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
96705. BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST__CAP_ID_MASK
96706. BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST__CAP_ID__SHIFT
96707. BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST__NEXT_PTR_MASK
96708. BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST__NEXT_PTR__SHIFT
96709. BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__DEVICE_TYPE_MASK
96710. BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__DEVICE_TYPE__SHIFT
96711. BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__INT_MESSAGE_NUM_MASK
96712. BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
96713. BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__SLOT_IMPLEMENTED_MASK
96714. BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
96715. BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__VERSION_MASK
96716. BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__VERSION__SHIFT
96717. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
96718. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
96719. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
96720. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
96721. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
96722. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
96723. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
96724. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
96725. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
96726. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
96727. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
96728. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
96729. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
96730. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
96731. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
96732. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
96733. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
96734. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
96735. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
96736. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
96737. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
96738. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
96739. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
96740. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
96741. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
96742. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
96743. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
96744. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
96745. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
96746. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
96747. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
96748. BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
96749. BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG0__TLP_HDR_MASK
96750. BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG0__TLP_HDR__SHIFT
96751. BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG1__TLP_HDR_MASK
96752. BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG1__TLP_HDR__SHIFT
96753. BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG2__TLP_HDR_MASK
96754. BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG2__TLP_HDR__SHIFT
96755. BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG3__TLP_HDR_MASK
96756. BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG3__TLP_HDR__SHIFT
96757. BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
96758. BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
96759. BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
96760. BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
96761. BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
96762. BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
96763. BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
96764. BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
96765. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
96766. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
96767. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
96768. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
96769. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
96770. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
96771. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
96772. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
96773. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
96774. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
96775. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
96776. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
96777. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
96778. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
96779. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
96780. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
96781. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
96782. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
96783. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
96784. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
96785. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
96786. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
96787. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
96788. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
96789. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
96790. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
96791. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
96792. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
96793. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
96794. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
96795. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
96796. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
96797. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
96798. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
96799. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
96800. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
96801. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
96802. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
96803. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
96804. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
96805. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
96806. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
96807. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
96808. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
96809. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
96810. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
96811. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
96812. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
96813. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
96814. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
96815. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
96816. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
96817. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
96818. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
96819. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
96820. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
96821. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
96822. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
96823. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
96824. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
96825. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
96826. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
96827. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
96828. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
96829. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
96830. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
96831. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
96832. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
96833. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
96834. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
96835. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
96836. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
96837. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
96838. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
96839. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
96840. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
96841. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
96842. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
96843. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
96844. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
96845. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
96846. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
96847. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
96848. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
96849. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
96850. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
96851. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
96852. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
96853. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
96854. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
96855. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
96856. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
96857. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
96858. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
96859. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
96860. BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
96861. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
96862. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
96863. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
96864. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
96865. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
96866. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
96867. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
96868. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
96869. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
96870. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
96871. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
96872. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
96873. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
96874. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
96875. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
96876. BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
96877. BIF_CFG_DEV0_EPF0_VF19_PROG_INTERFACE__PROG_INTERFACE_MASK
96878. BIF_CFG_DEV0_EPF0_VF19_PROG_INTERFACE__PROG_INTERFACE__SHIFT
96879. BIF_CFG_DEV0_EPF0_VF19_REVISION_ID__MAJOR_REV_ID_MASK
96880. BIF_CFG_DEV0_EPF0_VF19_REVISION_ID__MAJOR_REV_ID__SHIFT
96881. BIF_CFG_DEV0_EPF0_VF19_REVISION_ID__MINOR_REV_ID_MASK
96882. BIF_CFG_DEV0_EPF0_VF19_REVISION_ID__MINOR_REV_ID__SHIFT
96883. BIF_CFG_DEV0_EPF0_VF19_ROM_BASE_ADDR__BASE_ADDR_MASK
96884. BIF_CFG_DEV0_EPF0_VF19_ROM_BASE_ADDR__BASE_ADDR__SHIFT
96885. BIF_CFG_DEV0_EPF0_VF19_STATUS__CAP_LIST_MASK
96886. BIF_CFG_DEV0_EPF0_VF19_STATUS__CAP_LIST__SHIFT
96887. BIF_CFG_DEV0_EPF0_VF19_STATUS__DEVSEL_TIMING_MASK
96888. BIF_CFG_DEV0_EPF0_VF19_STATUS__DEVSEL_TIMING__SHIFT
96889. BIF_CFG_DEV0_EPF0_VF19_STATUS__FAST_BACK_CAPABLE_MASK
96890. BIF_CFG_DEV0_EPF0_VF19_STATUS__FAST_BACK_CAPABLE__SHIFT
96891. BIF_CFG_DEV0_EPF0_VF19_STATUS__IMMEDIATE_READINESS_MASK
96892. BIF_CFG_DEV0_EPF0_VF19_STATUS__IMMEDIATE_READINESS__SHIFT
96893. BIF_CFG_DEV0_EPF0_VF19_STATUS__INT_STATUS_MASK
96894. BIF_CFG_DEV0_EPF0_VF19_STATUS__INT_STATUS__SHIFT
96895. BIF_CFG_DEV0_EPF0_VF19_STATUS__MASTER_DATA_PARITY_ERROR_MASK
96896. BIF_CFG_DEV0_EPF0_VF19_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
96897. BIF_CFG_DEV0_EPF0_VF19_STATUS__PARITY_ERROR_DETECTED_MASK
96898. BIF_CFG_DEV0_EPF0_VF19_STATUS__PARITY_ERROR_DETECTED__SHIFT
96899. BIF_CFG_DEV0_EPF0_VF19_STATUS__PCI_66_CAP_MASK
96900. BIF_CFG_DEV0_EPF0_VF19_STATUS__PCI_66_CAP__SHIFT
96901. BIF_CFG_DEV0_EPF0_VF19_STATUS__RECEIVED_MASTER_ABORT_MASK
96902. BIF_CFG_DEV0_EPF0_VF19_STATUS__RECEIVED_MASTER_ABORT__SHIFT
96903. BIF_CFG_DEV0_EPF0_VF19_STATUS__RECEIVED_TARGET_ABORT_MASK
96904. BIF_CFG_DEV0_EPF0_VF19_STATUS__RECEIVED_TARGET_ABORT__SHIFT
96905. BIF_CFG_DEV0_EPF0_VF19_STATUS__SIGNALED_SYSTEM_ERROR_MASK
96906. BIF_CFG_DEV0_EPF0_VF19_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
96907. BIF_CFG_DEV0_EPF0_VF19_STATUS__SIGNAL_TARGET_ABORT_MASK
96908. BIF_CFG_DEV0_EPF0_VF19_STATUS__SIGNAL_TARGET_ABORT__SHIFT
96909. BIF_CFG_DEV0_EPF0_VF19_SUB_CLASS__SUB_CLASS_MASK
96910. BIF_CFG_DEV0_EPF0_VF19_SUB_CLASS__SUB_CLASS__SHIFT
96911. BIF_CFG_DEV0_EPF0_VF19_VENDOR_ID__VENDOR_ID_MASK
96912. BIF_CFG_DEV0_EPF0_VF19_VENDOR_ID__VENDOR_ID__SHIFT
96913. BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
96914. BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
96915. BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
96916. BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
96917. BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR_MASK
96918. BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT
96919. BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR_MASK
96920. BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT
96921. BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR_MASK
96922. BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT
96923. BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR_MASK
96924. BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT
96925. BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR_MASK
96926. BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT
96927. BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR_MASK
96928. BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT
96929. BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS_MASK
96930. BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS__SHIFT
96931. BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP_MASK
96932. BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP__SHIFT
96933. BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP_MASK
96934. BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP__SHIFT
96935. BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT_MASK
96936. BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT__SHIFT
96937. BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
96938. BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
96939. BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR_MASK
96940. BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR__SHIFT
96941. BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
96942. BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
96943. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING_MASK
96944. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING__SHIFT
96945. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN_MASK
96946. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN__SHIFT
96947. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN_MASK
96948. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN__SHIFT
96949. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS_MASK
96950. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS__SHIFT
96951. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN_MASK
96952. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN__SHIFT
96953. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN_MASK
96954. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN__SHIFT
96955. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
96956. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
96957. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN_MASK
96958. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN__SHIFT
96959. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
96960. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
96961. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN_MASK
96962. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN__SHIFT
96963. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK
96964. BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
96965. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
96966. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
96967. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
96968. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
96969. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
96970. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
96971. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
96972. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
96973. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
96974. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
96975. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
96976. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
96977. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
96978. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
96979. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
96980. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
96981. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
96982. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
96983. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
96984. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
96985. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
96986. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
96987. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
96988. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
96989. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
96990. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
96991. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
96992. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
96993. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
96994. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
96995. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
96996. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
96997. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
96998. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
96999. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
97000. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
97001. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
97002. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
97003. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
97004. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
97005. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
97006. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
97007. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
97008. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
97009. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG_MASK
97010. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
97011. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE_MASK
97012. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
97013. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
97014. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
97015. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
97016. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
97017. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
97018. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
97019. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK
97020. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
97021. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
97022. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
97023. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
97024. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
97025. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
97026. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
97027. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
97028. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
97029. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
97030. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
97031. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
97032. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
97033. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
97034. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
97035. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
97036. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
97037. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
97038. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
97039. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
97040. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
97041. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN_MASK
97042. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN__SHIFT
97043. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN_MASK
97044. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT
97045. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
97046. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
97047. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
97048. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
97049. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK
97050. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
97051. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
97052. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
97053. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
97054. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
97055. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR_MASK
97056. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
97057. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
97058. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
97059. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
97060. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
97061. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
97062. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
97063. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
97064. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
97065. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
97066. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
97067. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
97068. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
97069. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK
97070. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
97071. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID_MASK
97072. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID__SHIFT
97073. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED_MASK
97074. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED__SHIFT
97075. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR_MASK
97076. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR__SHIFT
97077. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR_MASK
97078. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR__SHIFT
97079. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
97080. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
97081. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR_MASK
97082. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT
97083. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
97084. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
97085. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
97086. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
97087. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED_MASK
97088. BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT
97089. BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE_MASK
97090. BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE__SHIFT
97091. BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE_MASK
97092. BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE__SHIFT
97093. BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
97094. BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
97095. BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
97096. BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
97097. BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER_MASK
97098. BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER__SHIFT
97099. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
97100. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
97101. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
97102. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
97103. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
97104. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
97105. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
97106. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
97107. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RESERVED_MASK
97108. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RESERVED__SHIFT
97109. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
97110. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
97111. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
97112. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
97113. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
97114. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
97115. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
97116. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
97117. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
97118. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
97119. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
97120. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
97121. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
97122. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
97123. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK
97124. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
97125. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
97126. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
97127. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED_MASK
97128. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED__SHIFT
97129. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH_MASK
97130. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH__SHIFT
97131. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT_MASK
97132. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT__SHIFT
97133. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER_MASK
97134. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER__SHIFT
97135. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
97136. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
97137. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
97138. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
97139. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
97140. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
97141. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
97142. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
97143. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
97144. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
97145. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
97146. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
97147. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
97148. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
97149. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
97150. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
97151. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN_MASK
97152. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
97153. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
97154. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
97155. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
97156. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
97157. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
97158. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
97159. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC_MASK
97160. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
97161. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
97162. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
97163. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
97164. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
97165. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
97166. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
97167. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS_MASK
97168. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS__SHIFT
97169. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL_MASK
97170. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL__SHIFT
97171. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
97172. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
97173. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK_MASK
97174. BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT
97175. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
97176. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
97177. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
97178. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
97179. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
97180. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
97181. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
97182. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
97183. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
97184. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
97185. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
97186. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
97187. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
97188. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
97189. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
97190. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
97191. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
97192. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
97193. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
97194. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
97195. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
97196. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
97197. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
97198. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
97199. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
97200. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
97201. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
97202. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
97203. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
97204. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
97205. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
97206. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
97207. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
97208. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
97209. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE_MASK
97210. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE__SHIFT
97211. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
97212. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
97213. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
97214. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
97215. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING_MASK
97216. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING__SHIFT
97217. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
97218. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
97219. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
97220. BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
97221. BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY__MAX_LAT_MASK
97222. BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY__MAX_LAT__SHIFT
97223. BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT__MIN_GNT_MASK
97224. BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT__MIN_GNT__SHIFT
97225. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID_MASK
97226. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT
97227. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK
97228. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
97229. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK
97230. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
97231. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
97232. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
97233. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
97234. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
97235. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK
97236. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
97237. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
97238. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
97239. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
97240. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
97241. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
97242. BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
97243. BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID_MASK
97244. BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID__SHIFT
97245. BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR_MASK
97246. BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
97247. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64_MASK
97248. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT
97249. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK_MASK
97250. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK__SHIFT
97251. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
97252. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
97253. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
97254. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
97255. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK
97256. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
97257. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN_MASK
97258. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT
97259. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
97260. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
97261. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
97262. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
97263. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
97264. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
97265. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
97266. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
97267. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA_MASK
97268. BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT
97269. BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK
97270. BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
97271. BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING_MASK
97272. BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING__SHIFT
97273. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
97274. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
97275. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
97276. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
97277. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
97278. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
97279. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
97280. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
97281. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
97282. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
97283. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
97284. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
97285. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
97286. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
97287. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
97288. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
97289. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
97290. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
97291. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
97292. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
97293. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
97294. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
97295. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
97296. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
97297. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
97298. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
97299. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
97300. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
97301. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
97302. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
97303. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
97304. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
97305. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
97306. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
97307. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
97308. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
97309. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
97310. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
97311. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
97312. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
97313. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
97314. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
97315. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
97316. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
97317. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
97318. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
97319. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
97320. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
97321. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
97322. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
97323. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__STU_MASK
97324. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__STU__SHIFT
97325. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
97326. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
97327. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
97328. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
97329. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
97330. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
97331. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID_MASK
97332. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT
97333. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK
97334. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
97335. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE_MASK
97336. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT
97337. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
97338. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
97339. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
97340. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
97341. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION_MASK
97342. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION__SHIFT
97343. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
97344. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
97345. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
97346. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
97347. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
97348. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
97349. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
97350. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
97351. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
97352. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
97353. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
97354. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
97355. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
97356. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
97357. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
97358. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
97359. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
97360. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
97361. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
97362. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
97363. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
97364. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
97365. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
97366. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
97367. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
97368. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
97369. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
97370. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
97371. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
97372. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
97373. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
97374. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
97375. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK
97376. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
97377. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK
97378. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
97379. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK
97380. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
97381. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK
97382. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
97383. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
97384. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
97385. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
97386. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
97387. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
97388. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
97389. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
97390. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
97391. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
97392. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
97393. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
97394. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
97395. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
97396. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
97397. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
97398. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
97399. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
97400. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
97401. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
97402. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
97403. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
97404. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
97405. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
97406. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
97407. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
97408. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
97409. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
97410. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
97411. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
97412. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
97413. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
97414. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
97415. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
97416. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
97417. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
97418. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
97419. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
97420. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
97421. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
97422. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
97423. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
97424. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
97425. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
97426. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
97427. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
97428. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
97429. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
97430. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
97431. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
97432. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
97433. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
97434. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
97435. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
97436. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
97437. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
97438. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
97439. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
97440. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
97441. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
97442. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
97443. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
97444. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
97445. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
97446. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
97447. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
97448. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
97449. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
97450. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
97451. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
97452. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
97453. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
97454. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
97455. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
97456. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
97457. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
97458. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
97459. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
97460. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
97461. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
97462. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
97463. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
97464. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
97465. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
97466. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
97467. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
97468. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
97469. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
97470. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
97471. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
97472. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
97473. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
97474. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
97475. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
97476. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
97477. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
97478. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
97479. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
97480. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
97481. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
97482. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
97483. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
97484. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
97485. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
97486. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
97487. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
97488. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
97489. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
97490. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
97491. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
97492. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
97493. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
97494. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
97495. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
97496. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
97497. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
97498. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
97499. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
97500. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
97501. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
97502. BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
97503. BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK
97504. BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
97505. BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID_MASK
97506. BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT
97507. BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID_MASK
97508. BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID__SHIFT
97509. BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK
97510. BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
97511. BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2__RESERVED_MASK
97512. BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2__RESERVED__SHIFT
97513. BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2__RESERVED_MASK
97514. BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2__RESERVED__SHIFT
97515. BIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2__RESERVED_MASK
97516. BIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2__RESERVED__SHIFT
97517. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST_MASK
97518. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST__SHIFT
97519. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING_MASK
97520. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING__SHIFT
97521. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE_MASK
97522. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT
97523. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__IMMEDIATE_READINESS_MASK
97524. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__IMMEDIATE_READINESS__SHIFT
97525. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS_MASK
97526. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS__SHIFT
97527. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
97528. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
97529. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED_MASK
97530. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
97531. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_CAP_MASK
97532. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_CAP__SHIFT
97533. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_EN_MASK
97534. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_EN__SHIFT
97535. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK
97536. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
97537. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK
97538. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
97539. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
97540. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
97541. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK
97542. BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
97543. BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS_MASK
97544. BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS__SHIFT
97545. BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID_MASK
97546. BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID__SHIFT
97547. BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
97548. BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
97549. BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
97550. BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
97551. BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR_MASK
97552. BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT
97553. BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR_MASK
97554. BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT
97555. BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR_MASK
97556. BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT
97557. BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR_MASK
97558. BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT
97559. BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR_MASK
97560. BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT
97561. BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR_MASK
97562. BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT
97563. BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS_MASK
97564. BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS__SHIFT
97565. BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP_MASK
97566. BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP__SHIFT
97567. BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP_MASK
97568. BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP__SHIFT
97569. BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT_MASK
97570. BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT__SHIFT
97571. BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
97572. BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
97573. BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR_MASK
97574. BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR__SHIFT
97575. BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
97576. BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
97577. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING_MASK
97578. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING__SHIFT
97579. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN_MASK
97580. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN__SHIFT
97581. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN_MASK
97582. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN__SHIFT
97583. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS_MASK
97584. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS__SHIFT
97585. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN_MASK
97586. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN__SHIFT
97587. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN_MASK
97588. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN__SHIFT
97589. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
97590. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
97591. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN_MASK
97592. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN__SHIFT
97593. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
97594. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
97595. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN_MASK
97596. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN__SHIFT
97597. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK
97598. BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
97599. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
97600. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
97601. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
97602. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
97603. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
97604. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
97605. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
97606. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
97607. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
97608. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
97609. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
97610. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
97611. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
97612. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
97613. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
97614. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
97615. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
97616. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
97617. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
97618. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
97619. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
97620. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
97621. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
97622. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
97623. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
97624. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
97625. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
97626. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
97627. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
97628. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
97629. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
97630. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
97631. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
97632. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
97633. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
97634. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
97635. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
97636. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
97637. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
97638. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
97639. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
97640. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
97641. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
97642. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
97643. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG_MASK
97644. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
97645. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE_MASK
97646. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
97647. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
97648. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
97649. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
97650. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
97651. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
97652. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
97653. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK
97654. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
97655. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
97656. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
97657. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
97658. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
97659. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
97660. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
97661. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
97662. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
97663. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
97664. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
97665. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
97666. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
97667. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
97668. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
97669. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
97670. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
97671. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
97672. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
97673. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
97674. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
97675. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN_MASK
97676. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN__SHIFT
97677. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN_MASK
97678. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT
97679. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
97680. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
97681. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
97682. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
97683. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK
97684. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
97685. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
97686. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
97687. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
97688. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
97689. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR_MASK
97690. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
97691. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
97692. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
97693. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
97694. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
97695. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
97696. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
97697. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
97698. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
97699. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
97700. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
97701. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
97702. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
97703. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK
97704. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
97705. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID_MASK
97706. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID__SHIFT
97707. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED_MASK
97708. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED__SHIFT
97709. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR_MASK
97710. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR__SHIFT
97711. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR_MASK
97712. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR__SHIFT
97713. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
97714. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
97715. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR_MASK
97716. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT
97717. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
97718. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
97719. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
97720. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
97721. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED_MASK
97722. BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT
97723. BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE_MASK
97724. BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE__SHIFT
97725. BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE_MASK
97726. BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE__SHIFT
97727. BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
97728. BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
97729. BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
97730. BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
97731. BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER_MASK
97732. BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER__SHIFT
97733. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
97734. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
97735. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
97736. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
97737. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
97738. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
97739. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
97740. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
97741. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RESERVED_MASK
97742. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RESERVED__SHIFT
97743. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
97744. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
97745. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
97746. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
97747. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
97748. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
97749. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
97750. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
97751. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
97752. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
97753. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
97754. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
97755. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
97756. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
97757. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK
97758. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
97759. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
97760. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
97761. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED_MASK
97762. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED__SHIFT
97763. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH_MASK
97764. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH__SHIFT
97765. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT_MASK
97766. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT__SHIFT
97767. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER_MASK
97768. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER__SHIFT
97769. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
97770. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
97771. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
97772. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
97773. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
97774. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
97775. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
97776. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
97777. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
97778. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
97779. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
97780. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
97781. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
97782. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
97783. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
97784. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
97785. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN_MASK
97786. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
97787. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
97788. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
97789. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
97790. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
97791. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
97792. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
97793. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC_MASK
97794. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
97795. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
97796. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
97797. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
97798. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
97799. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
97800. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
97801. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS_MASK
97802. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS__SHIFT
97803. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL_MASK
97804. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL__SHIFT
97805. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
97806. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
97807. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK_MASK
97808. BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT
97809. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
97810. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
97811. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
97812. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
97813. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
97814. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
97815. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
97816. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
97817. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
97818. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
97819. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
97820. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
97821. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
97822. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
97823. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
97824. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
97825. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
97826. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
97827. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
97828. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
97829. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
97830. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
97831. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
97832. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
97833. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
97834. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
97835. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
97836. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
97837. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
97838. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
97839. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
97840. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
97841. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
97842. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
97843. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE_MASK
97844. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE__SHIFT
97845. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
97846. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
97847. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
97848. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
97849. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING_MASK
97850. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING__SHIFT
97851. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
97852. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
97853. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
97854. BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
97855. BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY__MAX_LAT_MASK
97856. BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY__MAX_LAT__SHIFT
97857. BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT__MIN_GNT_MASK
97858. BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT__MIN_GNT__SHIFT
97859. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID_MASK
97860. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT
97861. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK
97862. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
97863. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK
97864. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
97865. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
97866. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
97867. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
97868. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
97869. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK
97870. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
97871. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
97872. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
97873. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
97874. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
97875. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
97876. BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
97877. BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID_MASK
97878. BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID__SHIFT
97879. BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR_MASK
97880. BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
97881. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64_MASK
97882. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT
97883. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK_MASK
97884. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK__SHIFT
97885. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
97886. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
97887. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
97888. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
97889. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK
97890. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
97891. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN_MASK
97892. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT
97893. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
97894. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
97895. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
97896. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
97897. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
97898. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
97899. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
97900. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
97901. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA_MASK
97902. BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT
97903. BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK
97904. BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
97905. BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING_MASK
97906. BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING__SHIFT
97907. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
97908. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
97909. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
97910. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
97911. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
97912. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
97913. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
97914. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
97915. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
97916. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
97917. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
97918. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
97919. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
97920. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
97921. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
97922. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
97923. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
97924. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
97925. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
97926. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
97927. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
97928. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
97929. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
97930. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
97931. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
97932. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
97933. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
97934. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
97935. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
97936. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
97937. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
97938. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
97939. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
97940. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
97941. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
97942. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
97943. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
97944. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
97945. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
97946. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
97947. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
97948. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
97949. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
97950. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
97951. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
97952. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
97953. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
97954. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
97955. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
97956. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
97957. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__STU_MASK
97958. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__STU__SHIFT
97959. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
97960. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
97961. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
97962. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
97963. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
97964. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
97965. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID_MASK
97966. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT
97967. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK
97968. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
97969. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE_MASK
97970. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT
97971. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
97972. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
97973. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
97974. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
97975. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION_MASK
97976. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION__SHIFT
97977. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
97978. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
97979. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
97980. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
97981. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
97982. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
97983. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
97984. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
97985. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
97986. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
97987. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
97988. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
97989. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
97990. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
97991. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
97992. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
97993. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
97994. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
97995. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
97996. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
97997. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
97998. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
97999. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
98000. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
98001. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
98002. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
98003. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
98004. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
98005. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
98006. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
98007. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
98008. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
98009. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK
98010. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
98011. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK
98012. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
98013. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK
98014. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
98015. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK
98016. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
98017. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
98018. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
98019. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
98020. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
98021. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
98022. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
98023. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
98024. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
98025. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
98026. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
98027. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
98028. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
98029. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
98030. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
98031. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
98032. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
98033. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
98034. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
98035. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
98036. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
98037. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
98038. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
98039. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
98040. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
98041. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
98042. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
98043. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
98044. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
98045. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
98046. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
98047. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
98048. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
98049. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
98050. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
98051. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
98052. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
98053. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
98054. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
98055. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
98056. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
98057. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
98058. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
98059. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
98060. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
98061. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
98062. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
98063. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
98064. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
98065. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
98066. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
98067. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
98068. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
98069. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
98070. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
98071. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
98072. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
98073. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
98074. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
98075. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
98076. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
98077. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
98078. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
98079. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
98080. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
98081. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
98082. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
98083. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
98084. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
98085. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
98086. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
98087. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
98088. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
98089. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
98090. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
98091. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
98092. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
98093. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
98094. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
98095. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
98096. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
98097. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
98098. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
98099. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
98100. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
98101. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
98102. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
98103. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
98104. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
98105. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
98106. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
98107. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
98108. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
98109. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
98110. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
98111. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
98112. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
98113. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
98114. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
98115. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
98116. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
98117. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
98118. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
98119. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
98120. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
98121. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
98122. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
98123. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
98124. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
98125. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
98126. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
98127. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
98128. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
98129. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
98130. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
98131. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
98132. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
98133. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
98134. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
98135. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
98136. BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
98137. BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK
98138. BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
98139. BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID_MASK
98140. BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT
98141. BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID_MASK
98142. BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID__SHIFT
98143. BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK
98144. BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
98145. BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CAP2__RESERVED_MASK
98146. BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CAP2__RESERVED__SHIFT
98147. BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CNTL2__RESERVED_MASK
98148. BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CNTL2__RESERVED__SHIFT
98149. BIF_CFG_DEV0_EPF0_VF1_1_SLOT_STATUS2__RESERVED_MASK
98150. BIF_CFG_DEV0_EPF0_VF1_1_SLOT_STATUS2__RESERVED__SHIFT
98151. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST_MASK
98152. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST__SHIFT
98153. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING_MASK
98154. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING__SHIFT
98155. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE_MASK
98156. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT
98157. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__IMMEDIATE_READINESS_MASK
98158. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__IMMEDIATE_READINESS__SHIFT
98159. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS_MASK
98160. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS__SHIFT
98161. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
98162. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
98163. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED_MASK
98164. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
98165. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_CAP_MASK
98166. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_CAP__SHIFT
98167. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_EN_MASK
98168. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_EN__SHIFT
98169. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK
98170. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
98171. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK
98172. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
98173. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
98174. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
98175. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK
98176. BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
98177. BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS_MASK
98178. BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS__SHIFT
98179. BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID_MASK
98180. BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID__SHIFT
98181. BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK
98182. BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
98183. BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
98184. BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
98185. BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK
98186. BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT
98187. BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK
98188. BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT
98189. BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK
98190. BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT
98191. BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK
98192. BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT
98193. BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK
98194. BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT
98195. BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK
98196. BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT
98197. BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK
98198. BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT
98199. BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK
98200. BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT
98201. BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK
98202. BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT
98203. BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK
98204. BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT
98205. BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK
98206. BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
98207. BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK
98208. BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT
98209. BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
98210. BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
98211. BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK
98212. BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT
98213. BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK
98214. BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT
98215. BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK
98216. BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT
98217. BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK
98218. BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT
98219. BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK
98220. BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT
98221. BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK
98222. BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT
98223. BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
98224. BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
98225. BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK
98226. BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT
98227. BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK
98228. BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
98229. BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK
98230. BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT
98231. BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK
98232. BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
98233. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
98234. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
98235. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
98236. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
98237. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
98238. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
98239. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
98240. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
98241. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
98242. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
98243. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
98244. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
98245. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
98246. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
98247. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
98248. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
98249. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
98250. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
98251. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
98252. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
98253. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
98254. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
98255. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK
98256. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
98257. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
98258. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
98259. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK
98260. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
98261. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
98262. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
98263. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
98264. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
98265. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
98266. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
98267. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
98268. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
98269. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
98270. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
98271. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
98272. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
98273. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
98274. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
98275. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
98276. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
98277. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK
98278. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT
98279. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK
98280. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT
98281. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
98282. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
98283. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
98284. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
98285. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
98286. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
98287. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK
98288. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
98289. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
98290. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
98291. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
98292. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
98293. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
98294. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
98295. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
98296. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
98297. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
98298. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
98299. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
98300. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
98301. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
98302. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
98303. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
98304. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
98305. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
98306. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
98307. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
98308. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
98309. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK
98310. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT
98311. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK
98312. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT
98313. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
98314. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
98315. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
98316. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
98317. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK
98318. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
98319. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
98320. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
98321. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK
98322. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
98323. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK
98324. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT
98325. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
98326. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
98327. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
98328. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
98329. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
98330. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
98331. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK
98332. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
98333. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
98334. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
98335. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
98336. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
98337. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK
98338. BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
98339. BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK
98340. BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT
98341. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK
98342. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT
98343. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK
98344. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT
98345. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK
98346. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT
98347. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
98348. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
98349. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK
98350. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT
98351. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK
98352. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
98353. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
98354. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
98355. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK
98356. BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT
98357. BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE_MASK
98358. BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE__SHIFT
98359. BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE_MASK
98360. BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE__SHIFT
98361. BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
98362. BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
98363. BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
98364. BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
98365. BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK
98366. BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT
98367. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
98368. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
98369. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
98370. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
98371. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
98372. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
98373. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
98374. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
98375. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
98376. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
98377. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
98378. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
98379. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
98380. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
98381. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
98382. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
98383. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
98384. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
98385. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
98386. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
98387. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK
98388. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
98389. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK
98390. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
98391. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
98392. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
98393. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK
98394. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT
98395. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK
98396. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT
98397. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK
98398. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT
98399. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK
98400. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT
98401. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
98402. BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
98403. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
98404. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
98405. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK
98406. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
98407. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
98408. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
98409. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
98410. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
98411. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
98412. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
98413. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
98414. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
98415. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
98416. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
98417. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK
98418. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT
98419. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
98420. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
98421. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
98422. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
98423. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
98424. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
98425. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK
98426. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT
98427. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
98428. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
98429. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
98430. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
98431. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
98432. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
98433. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK
98434. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT
98435. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK
98436. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT
98437. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
98438. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
98439. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK
98440. BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT
98441. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
98442. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
98443. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
98444. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
98445. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
98446. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
98447. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
98448. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
98449. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
98450. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
98451. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
98452. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
98453. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
98454. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
98455. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
98456. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
98457. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
98458. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
98459. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
98460. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
98461. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
98462. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
98463. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
98464. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
98465. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK
98466. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT
98467. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
98468. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
98469. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
98470. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
98471. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK
98472. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT
98473. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
98474. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
98475. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
98476. BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
98477. BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK
98478. BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT
98479. BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK
98480. BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT
98481. BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK
98482. BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT
98483. BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK
98484. BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
98485. BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK
98486. BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
98487. BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
98488. BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
98489. BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
98490. BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
98491. BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK
98492. BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
98493. BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
98494. BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
98495. BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
98496. BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
98497. BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
98498. BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
98499. BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK
98500. BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT
98501. BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK
98502. BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT
98503. BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK
98504. BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT
98505. BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK
98506. BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT
98507. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
98508. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
98509. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
98510. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
98511. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK
98512. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
98513. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK
98514. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT
98515. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
98516. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
98517. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
98518. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
98519. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
98520. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
98521. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
98522. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
98523. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK
98524. BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT
98525. BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK
98526. BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
98527. BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK
98528. BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT
98529. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
98530. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
98531. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
98532. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
98533. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
98534. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
98535. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
98536. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
98537. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
98538. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
98539. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
98540. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
98541. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
98542. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
98543. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
98544. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
98545. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
98546. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
98547. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
98548. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
98549. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
98550. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
98551. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
98552. BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
98553. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
98554. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
98555. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
98556. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
98557. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
98558. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
98559. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
98560. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
98561. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
98562. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
98563. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
98564. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
98565. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
98566. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
98567. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
98568. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
98569. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
98570. BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
98571. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
98572. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
98573. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
98574. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
98575. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
98576. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
98577. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
98578. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
98579. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU_MASK
98580. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU__SHIFT
98581. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
98582. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
98583. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
98584. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
98585. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
98586. BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
98587. BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK
98588. BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT
98589. BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK
98590. BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
98591. BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK
98592. BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT
98593. BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK
98594. BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
98595. BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
98596. BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
98597. BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK
98598. BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT
98599. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
98600. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
98601. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
98602. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
98603. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
98604. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
98605. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
98606. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
98607. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
98608. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
98609. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
98610. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
98611. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
98612. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
98613. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
98614. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
98615. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
98616. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
98617. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
98618. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
98619. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
98620. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
98621. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
98622. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
98623. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
98624. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
98625. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
98626. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
98627. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
98628. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
98629. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
98630. BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
98631. BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK
98632. BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
98633. BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK
98634. BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
98635. BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK
98636. BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
98637. BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK
98638. BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
98639. BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
98640. BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
98641. BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
98642. BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
98643. BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
98644. BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
98645. BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
98646. BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
98647. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
98648. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
98649. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
98650. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
98651. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
98652. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
98653. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
98654. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
98655. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
98656. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
98657. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
98658. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
98659. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
98660. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
98661. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
98662. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
98663. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
98664. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
98665. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
98666. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
98667. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
98668. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
98669. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
98670. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
98671. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
98672. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
98673. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
98674. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
98675. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
98676. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
98677. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
98678. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
98679. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
98680. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
98681. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
98682. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
98683. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
98684. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
98685. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
98686. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
98687. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
98688. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
98689. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
98690. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
98691. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
98692. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
98693. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
98694. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
98695. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
98696. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
98697. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
98698. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
98699. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
98700. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
98701. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
98702. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
98703. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
98704. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
98705. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
98706. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
98707. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
98708. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
98709. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
98710. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
98711. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
98712. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
98713. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
98714. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
98715. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
98716. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
98717. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
98718. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
98719. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
98720. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
98721. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
98722. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
98723. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
98724. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
98725. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
98726. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
98727. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
98728. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
98729. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
98730. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
98731. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
98732. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
98733. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
98734. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
98735. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
98736. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
98737. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
98738. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
98739. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
98740. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
98741. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
98742. BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
98743. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
98744. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
98745. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
98746. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
98747. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
98748. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
98749. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
98750. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
98751. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
98752. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
98753. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
98754. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
98755. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
98756. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
98757. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
98758. BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
98759. BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK
98760. BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
98761. BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK
98762. BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT
98763. BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK
98764. BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT
98765. BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK
98766. BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
98767. BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK
98768. BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT
98769. BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK
98770. BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT
98771. BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK
98772. BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT
98773. BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK
98774. BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT
98775. BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK
98776. BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT
98777. BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
98778. BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
98779. BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK
98780. BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT
98781. BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK
98782. BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT
98783. BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK
98784. BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
98785. BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK
98786. BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
98787. BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
98788. BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
98789. BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK
98790. BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
98791. BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK
98792. BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT
98793. BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK
98794. BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT
98795. BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
98796. BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
98797. BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
98798. BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
98799. BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1__BASE_ADDR_MASK
98800. BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1__BASE_ADDR__SHIFT
98801. BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2__BASE_ADDR_MASK
98802. BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2__BASE_ADDR__SHIFT
98803. BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3__BASE_ADDR_MASK
98804. BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3__BASE_ADDR__SHIFT
98805. BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4__BASE_ADDR_MASK
98806. BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4__BASE_ADDR__SHIFT
98807. BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5__BASE_ADDR_MASK
98808. BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5__BASE_ADDR__SHIFT
98809. BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6__BASE_ADDR_MASK
98810. BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6__BASE_ADDR__SHIFT
98811. BIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS__BASE_CLASS_MASK
98812. BIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS__BASE_CLASS__SHIFT
98813. BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_CAP_MASK
98814. BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_CAP__SHIFT
98815. BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_COMP_MASK
98816. BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_COMP__SHIFT
98817. BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_STRT_MASK
98818. BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_STRT__SHIFT
98819. BIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
98820. BIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
98821. BIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR__CAP_PTR_MASK
98822. BIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR__CAP_PTR__SHIFT
98823. BIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
98824. BIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
98825. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__AD_STEPPING_MASK
98826. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__AD_STEPPING__SHIFT
98827. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__BUS_MASTER_EN_MASK
98828. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__BUS_MASTER_EN__SHIFT
98829. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__FAST_B2B_EN_MASK
98830. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__FAST_B2B_EN__SHIFT
98831. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__INT_DIS_MASK
98832. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__INT_DIS__SHIFT
98833. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__IO_ACCESS_EN_MASK
98834. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__IO_ACCESS_EN__SHIFT
98835. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__MEM_ACCESS_EN_MASK
98836. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__MEM_ACCESS_EN__SHIFT
98837. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
98838. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
98839. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__PAL_SNOOP_EN_MASK
98840. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__PAL_SNOOP_EN__SHIFT
98841. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
98842. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
98843. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__SERR_EN_MASK
98844. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__SERR_EN__SHIFT
98845. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__SPECIAL_CYCLE_EN_MASK
98846. BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
98847. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
98848. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
98849. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
98850. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
98851. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
98852. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
98853. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
98854. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
98855. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
98856. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
98857. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
98858. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
98859. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
98860. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
98861. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
98862. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
98863. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
98864. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
98865. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
98866. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
98867. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
98868. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
98869. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
98870. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
98871. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
98872. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
98873. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
98874. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
98875. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
98876. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
98877. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
98878. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
98879. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
98880. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
98881. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
98882. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
98883. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
98884. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
98885. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
98886. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
98887. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
98888. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
98889. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
98890. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
98891. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__EXTENDED_TAG_MASK
98892. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
98893. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__FLR_CAPABLE_MASK
98894. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
98895. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
98896. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
98897. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
98898. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
98899. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
98900. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
98901. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__PHANTOM_FUNC_MASK
98902. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
98903. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
98904. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
98905. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
98906. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
98907. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
98908. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
98909. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
98910. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
98911. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
98912. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
98913. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
98914. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
98915. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
98916. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
98917. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
98918. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
98919. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
98920. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
98921. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
98922. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
98923. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__LTR_EN_MASK
98924. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__LTR_EN__SHIFT
98925. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__OBFF_EN_MASK
98926. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__OBFF_EN__SHIFT
98927. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
98928. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
98929. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
98930. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
98931. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__CORR_ERR_EN_MASK
98932. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
98933. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
98934. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
98935. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
98936. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
98937. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__INITIATE_FLR_MASK
98938. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
98939. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
98940. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
98941. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
98942. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
98943. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
98944. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
98945. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
98946. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
98947. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
98948. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
98949. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
98950. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
98951. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__USR_REPORT_EN_MASK
98952. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
98953. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID__DEVICE_ID_MASK
98954. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID__DEVICE_ID__SHIFT
98955. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2__RESERVED_MASK
98956. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2__RESERVED__SHIFT
98957. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__AUX_PWR_MASK
98958. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__AUX_PWR__SHIFT
98959. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__CORR_ERR_MASK
98960. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__CORR_ERR__SHIFT
98961. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
98962. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
98963. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__FATAL_ERR_MASK
98964. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__FATAL_ERR__SHIFT
98965. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
98966. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
98967. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
98968. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
98969. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__USR_DETECTED_MASK
98970. BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__USR_DETECTED__SHIFT
98971. BIF_CFG_DEV0_EPF0_VF20_0_HEADER__DEVICE_TYPE_MASK
98972. BIF_CFG_DEV0_EPF0_VF20_0_HEADER__DEVICE_TYPE__SHIFT
98973. BIF_CFG_DEV0_EPF0_VF20_0_HEADER__HEADER_TYPE_MASK
98974. BIF_CFG_DEV0_EPF0_VF20_0_HEADER__HEADER_TYPE__SHIFT
98975. BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
98976. BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
98977. BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
98978. BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
98979. BIF_CFG_DEV0_EPF0_VF20_0_LATENCY__LATENCY_TIMER_MASK
98980. BIF_CFG_DEV0_EPF0_VF20_0_LATENCY__LATENCY_TIMER__SHIFT
98981. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
98982. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
98983. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
98984. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
98985. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
98986. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
98987. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
98988. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
98989. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
98990. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
98991. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
98992. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
98993. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
98994. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
98995. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
98996. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
98997. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
98998. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
98999. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
99000. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
99001. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
99002. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
99003. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__L1_EXIT_LATENCY_MASK
99004. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
99005. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
99006. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
99007. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_SPEED_MASK
99008. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_SPEED__SHIFT
99009. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_WIDTH_MASK
99010. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_WIDTH__SHIFT
99011. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__PM_SUPPORT_MASK
99012. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__PM_SUPPORT__SHIFT
99013. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__PORT_NUMBER_MASK
99014. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__PORT_NUMBER__SHIFT
99015. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
99016. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
99017. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
99018. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
99019. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
99020. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
99021. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
99022. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
99023. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
99024. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
99025. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
99026. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
99027. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
99028. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
99029. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
99030. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
99031. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__XMIT_MARGIN_MASK
99032. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
99033. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
99034. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
99035. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
99036. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
99037. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
99038. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
99039. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__EXTENDED_SYNC_MASK
99040. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
99041. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
99042. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
99043. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
99044. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
99045. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
99046. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
99047. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_DIS_MASK
99048. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_DIS__SHIFT
99049. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__PM_CONTROL_MASK
99050. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__PM_CONTROL__SHIFT
99051. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
99052. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
99053. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__RETRAIN_LINK_MASK
99054. BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__RETRAIN_LINK__SHIFT
99055. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
99056. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
99057. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
99058. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
99059. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
99060. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
99061. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
99062. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
99063. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
99064. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
99065. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
99066. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
99067. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
99068. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
99069. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
99070. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
99071. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
99072. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
99073. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
99074. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
99075. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
99076. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
99077. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
99078. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
99079. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__DL_ACTIVE_MASK
99080. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__DL_ACTIVE__SHIFT
99081. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
99082. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
99083. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
99084. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
99085. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_TRAINING_MASK
99086. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_TRAINING__SHIFT
99087. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
99088. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
99089. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
99090. BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
99091. BIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY__MAX_LAT_MASK
99092. BIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY__MAX_LAT__SHIFT
99093. BIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT__MIN_GNT_MASK
99094. BIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT__MIN_GNT__SHIFT
99095. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST__CAP_ID_MASK
99096. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST__CAP_ID__SHIFT
99097. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST__NEXT_PTR_MASK
99098. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
99099. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_EN_MASK
99100. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
99101. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
99102. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
99103. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
99104. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
99105. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA__MSIX_PBA_BIR_MASK
99106. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
99107. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
99108. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
99109. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
99110. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
99111. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
99112. BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
99113. BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST__CAP_ID_MASK
99114. BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST__CAP_ID__SHIFT
99115. BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST__NEXT_PTR_MASK
99116. BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
99117. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64__MSI_MASK_64_MASK
99118. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64__MSI_MASK_64__SHIFT
99119. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK__MSI_MASK_MASK
99120. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK__MSI_MASK__SHIFT
99121. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
99122. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
99123. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
99124. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
99125. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_64BIT_MASK
99126. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
99127. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_EN_MASK
99128. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_EN__SHIFT
99129. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
99130. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
99131. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
99132. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
99133. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
99134. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
99135. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
99136. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
99137. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA__MSI_DATA_MASK
99138. BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA__MSI_DATA__SHIFT
99139. BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64__MSI_PENDING_64_MASK
99140. BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
99141. BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING__MSI_PENDING_MASK
99142. BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING__MSI_PENDING__SHIFT
99143. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
99144. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
99145. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
99146. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
99147. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
99148. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
99149. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
99150. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
99151. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
99152. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
99153. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
99154. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
99155. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
99156. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
99157. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
99158. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
99159. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
99160. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
99161. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
99162. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
99163. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
99164. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
99165. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
99166. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
99167. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
99168. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
99169. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
99170. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
99171. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
99172. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
99173. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
99174. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
99175. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
99176. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
99177. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
99178. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
99179. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
99180. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
99181. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
99182. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
99183. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
99184. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
99185. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
99186. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
99187. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
99188. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
99189. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
99190. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
99191. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
99192. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
99193. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL__STU_MASK
99194. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL__STU__SHIFT
99195. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
99196. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
99197. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
99198. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
99199. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
99200. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
99201. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST__CAP_ID_MASK
99202. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST__CAP_ID__SHIFT
99203. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST__NEXT_PTR_MASK
99204. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
99205. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__DEVICE_TYPE_MASK
99206. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__DEVICE_TYPE__SHIFT
99207. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
99208. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
99209. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
99210. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
99211. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__VERSION_MASK
99212. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__VERSION__SHIFT
99213. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
99214. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
99215. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
99216. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
99217. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
99218. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
99219. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
99220. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
99221. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
99222. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
99223. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
99224. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
99225. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
99226. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
99227. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
99228. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
99229. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
99230. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
99231. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
99232. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
99233. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
99234. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
99235. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
99236. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
99237. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
99238. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
99239. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
99240. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
99241. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
99242. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
99243. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
99244. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
99245. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0__TLP_HDR_MASK
99246. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
99247. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1__TLP_HDR_MASK
99248. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
99249. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2__TLP_HDR_MASK
99250. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
99251. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3__TLP_HDR_MASK
99252. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
99253. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
99254. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
99255. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
99256. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
99257. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
99258. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
99259. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
99260. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
99261. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
99262. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
99263. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
99264. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
99265. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
99266. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
99267. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
99268. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
99269. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
99270. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
99271. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
99272. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
99273. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
99274. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
99275. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
99276. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
99277. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
99278. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
99279. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
99280. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
99281. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
99282. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
99283. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
99284. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
99285. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
99286. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
99287. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
99288. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
99289. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
99290. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
99291. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
99292. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
99293. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
99294. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
99295. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
99296. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
99297. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
99298. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
99299. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
99300. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
99301. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
99302. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
99303. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
99304. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
99305. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
99306. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
99307. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
99308. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
99309. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
99310. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
99311. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
99312. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
99313. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
99314. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
99315. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
99316. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
99317. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
99318. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
99319. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
99320. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
99321. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
99322. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
99323. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
99324. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
99325. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
99326. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
99327. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
99328. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
99329. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
99330. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
99331. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
99332. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
99333. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
99334. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
99335. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
99336. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
99337. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
99338. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
99339. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
99340. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
99341. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
99342. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
99343. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
99344. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
99345. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
99346. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
99347. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
99348. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
99349. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
99350. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
99351. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
99352. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
99353. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
99354. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
99355. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
99356. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
99357. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
99358. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
99359. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
99360. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
99361. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
99362. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
99363. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
99364. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
99365. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
99366. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
99367. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
99368. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
99369. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
99370. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
99371. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
99372. BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
99373. BIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE__PROG_INTERFACE_MASK
99374. BIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
99375. BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID__MAJOR_REV_ID_MASK
99376. BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID__MAJOR_REV_ID__SHIFT
99377. BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID__MINOR_REV_ID_MASK
99378. BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID__MINOR_REV_ID__SHIFT
99379. BIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR__BASE_ADDR_MASK
99380. BIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
99381. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__CAP_LIST_MASK
99382. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__CAP_LIST__SHIFT
99383. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__DEVSEL_TIMING_MASK
99384. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__DEVSEL_TIMING__SHIFT
99385. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__FAST_BACK_CAPABLE_MASK
99386. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__FAST_BACK_CAPABLE__SHIFT
99387. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__IMMEDIATE_READINESS_MASK
99388. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__IMMEDIATE_READINESS__SHIFT
99389. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__INT_STATUS_MASK
99390. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__INT_STATUS__SHIFT
99391. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
99392. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
99393. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__PARITY_ERROR_DETECTED_MASK
99394. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
99395. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__PCI_66_CAP_MASK
99396. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__PCI_66_CAP__SHIFT
99397. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__RECEIVED_MASTER_ABORT_MASK
99398. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
99399. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__RECEIVED_TARGET_ABORT_MASK
99400. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
99401. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
99402. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
99403. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__SIGNAL_TARGET_ABORT_MASK
99404. BIF_CFG_DEV0_EPF0_VF20_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
99405. BIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS__SUB_CLASS_MASK
99406. BIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS__SUB_CLASS__SHIFT
99407. BIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID__VENDOR_ID_MASK
99408. BIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID__VENDOR_ID__SHIFT
99409. BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
99410. BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
99411. BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
99412. BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
99413. BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1__BASE_ADDR_MASK
99414. BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1__BASE_ADDR__SHIFT
99415. BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2__BASE_ADDR_MASK
99416. BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2__BASE_ADDR__SHIFT
99417. BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3__BASE_ADDR_MASK
99418. BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3__BASE_ADDR__SHIFT
99419. BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4__BASE_ADDR_MASK
99420. BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4__BASE_ADDR__SHIFT
99421. BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5__BASE_ADDR_MASK
99422. BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5__BASE_ADDR__SHIFT
99423. BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6__BASE_ADDR_MASK
99424. BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6__BASE_ADDR__SHIFT
99425. BIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS__BASE_CLASS_MASK
99426. BIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS__BASE_CLASS__SHIFT
99427. BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_CAP_MASK
99428. BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_CAP__SHIFT
99429. BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_COMP_MASK
99430. BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_COMP__SHIFT
99431. BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_STRT_MASK
99432. BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_STRT__SHIFT
99433. BIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
99434. BIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
99435. BIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR__CAP_PTR_MASK
99436. BIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR__CAP_PTR__SHIFT
99437. BIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
99438. BIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
99439. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__AD_STEPPING_MASK
99440. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__AD_STEPPING__SHIFT
99441. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__BUS_MASTER_EN_MASK
99442. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__BUS_MASTER_EN__SHIFT
99443. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__FAST_B2B_EN_MASK
99444. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__FAST_B2B_EN__SHIFT
99445. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__INT_DIS_MASK
99446. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__INT_DIS__SHIFT
99447. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__IO_ACCESS_EN_MASK
99448. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__IO_ACCESS_EN__SHIFT
99449. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__MEM_ACCESS_EN_MASK
99450. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__MEM_ACCESS_EN__SHIFT
99451. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
99452. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
99453. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__PAL_SNOOP_EN_MASK
99454. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__PAL_SNOOP_EN__SHIFT
99455. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
99456. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
99457. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__SERR_EN_MASK
99458. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__SERR_EN__SHIFT
99459. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__SPECIAL_CYCLE_EN_MASK
99460. BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
99461. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
99462. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
99463. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
99464. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
99465. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
99466. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
99467. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
99468. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
99469. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
99470. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
99471. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
99472. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
99473. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
99474. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
99475. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
99476. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
99477. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
99478. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
99479. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
99480. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
99481. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
99482. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
99483. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
99484. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
99485. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
99486. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
99487. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
99488. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
99489. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
99490. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
99491. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
99492. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
99493. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
99494. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
99495. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
99496. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
99497. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
99498. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
99499. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
99500. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
99501. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
99502. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
99503. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
99504. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
99505. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__EXTENDED_TAG_MASK
99506. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
99507. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__FLR_CAPABLE_MASK
99508. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
99509. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
99510. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
99511. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
99512. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
99513. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
99514. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
99515. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__PHANTOM_FUNC_MASK
99516. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
99517. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
99518. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
99519. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
99520. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
99521. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
99522. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
99523. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
99524. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
99525. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
99526. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
99527. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
99528. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
99529. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
99530. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
99531. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
99532. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
99533. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
99534. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
99535. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
99536. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
99537. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__LTR_EN_MASK
99538. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__LTR_EN__SHIFT
99539. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__OBFF_EN_MASK
99540. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__OBFF_EN__SHIFT
99541. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
99542. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
99543. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
99544. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
99545. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__CORR_ERR_EN_MASK
99546. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
99547. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
99548. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
99549. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
99550. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
99551. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__INITIATE_FLR_MASK
99552. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
99553. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
99554. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
99555. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
99556. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
99557. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
99558. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
99559. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
99560. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
99561. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
99562. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
99563. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
99564. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
99565. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__USR_REPORT_EN_MASK
99566. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
99567. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID__DEVICE_ID_MASK
99568. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID__DEVICE_ID__SHIFT
99569. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2__RESERVED_MASK
99570. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2__RESERVED__SHIFT
99571. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__AUX_PWR_MASK
99572. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__AUX_PWR__SHIFT
99573. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__CORR_ERR_MASK
99574. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__CORR_ERR__SHIFT
99575. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
99576. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
99577. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__FATAL_ERR_MASK
99578. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__FATAL_ERR__SHIFT
99579. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
99580. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
99581. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
99582. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
99583. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__USR_DETECTED_MASK
99584. BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__USR_DETECTED__SHIFT
99585. BIF_CFG_DEV0_EPF0_VF20_1_HEADER__DEVICE_TYPE_MASK
99586. BIF_CFG_DEV0_EPF0_VF20_1_HEADER__DEVICE_TYPE__SHIFT
99587. BIF_CFG_DEV0_EPF0_VF20_1_HEADER__HEADER_TYPE_MASK
99588. BIF_CFG_DEV0_EPF0_VF20_1_HEADER__HEADER_TYPE__SHIFT
99589. BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
99590. BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
99591. BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
99592. BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
99593. BIF_CFG_DEV0_EPF0_VF20_1_LATENCY__LATENCY_TIMER_MASK
99594. BIF_CFG_DEV0_EPF0_VF20_1_LATENCY__LATENCY_TIMER__SHIFT
99595. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
99596. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
99597. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
99598. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
99599. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
99600. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
99601. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
99602. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
99603. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
99604. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
99605. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
99606. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
99607. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
99608. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
99609. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
99610. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
99611. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
99612. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
99613. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
99614. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
99615. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
99616. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
99617. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__L1_EXIT_LATENCY_MASK
99618. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
99619. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
99620. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
99621. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_SPEED_MASK
99622. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_SPEED__SHIFT
99623. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_WIDTH_MASK
99624. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_WIDTH__SHIFT
99625. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__PM_SUPPORT_MASK
99626. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__PM_SUPPORT__SHIFT
99627. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__PORT_NUMBER_MASK
99628. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__PORT_NUMBER__SHIFT
99629. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
99630. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
99631. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
99632. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
99633. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
99634. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
99635. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
99636. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
99637. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
99638. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
99639. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
99640. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
99641. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
99642. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
99643. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
99644. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
99645. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__XMIT_MARGIN_MASK
99646. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
99647. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
99648. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
99649. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
99650. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
99651. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
99652. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
99653. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__EXTENDED_SYNC_MASK
99654. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
99655. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
99656. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
99657. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
99658. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
99659. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
99660. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
99661. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_DIS_MASK
99662. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_DIS__SHIFT
99663. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__PM_CONTROL_MASK
99664. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__PM_CONTROL__SHIFT
99665. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
99666. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
99667. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__RETRAIN_LINK_MASK
99668. BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__RETRAIN_LINK__SHIFT
99669. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
99670. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
99671. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
99672. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
99673. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
99674. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
99675. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
99676. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
99677. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
99678. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
99679. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
99680. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
99681. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
99682. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
99683. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
99684. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
99685. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
99686. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
99687. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
99688. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
99689. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
99690. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
99691. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
99692. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
99693. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__DL_ACTIVE_MASK
99694. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__DL_ACTIVE__SHIFT
99695. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
99696. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
99697. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
99698. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
99699. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_TRAINING_MASK
99700. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_TRAINING__SHIFT
99701. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
99702. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
99703. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
99704. BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
99705. BIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY__MAX_LAT_MASK
99706. BIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY__MAX_LAT__SHIFT
99707. BIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT__MIN_GNT_MASK
99708. BIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT__MIN_GNT__SHIFT
99709. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST__CAP_ID_MASK
99710. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST__CAP_ID__SHIFT
99711. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST__NEXT_PTR_MASK
99712. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
99713. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_EN_MASK
99714. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
99715. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
99716. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
99717. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
99718. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
99719. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA__MSIX_PBA_BIR_MASK
99720. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
99721. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
99722. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
99723. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
99724. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
99725. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
99726. BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
99727. BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST__CAP_ID_MASK
99728. BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST__CAP_ID__SHIFT
99729. BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST__NEXT_PTR_MASK
99730. BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
99731. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64__MSI_MASK_64_MASK
99732. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64__MSI_MASK_64__SHIFT
99733. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK__MSI_MASK_MASK
99734. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK__MSI_MASK__SHIFT
99735. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
99736. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
99737. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
99738. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
99739. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_64BIT_MASK
99740. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
99741. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_EN_MASK
99742. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_EN__SHIFT
99743. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
99744. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
99745. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
99746. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
99747. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
99748. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
99749. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
99750. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
99751. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA__MSI_DATA_MASK
99752. BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA__MSI_DATA__SHIFT
99753. BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64__MSI_PENDING_64_MASK
99754. BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
99755. BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING__MSI_PENDING_MASK
99756. BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING__MSI_PENDING__SHIFT
99757. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
99758. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
99759. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
99760. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
99761. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
99762. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
99763. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
99764. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
99765. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
99766. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
99767. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
99768. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
99769. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
99770. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
99771. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
99772. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
99773. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
99774. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
99775. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
99776. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
99777. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
99778. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
99779. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
99780. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
99781. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
99782. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
99783. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
99784. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
99785. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
99786. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
99787. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
99788. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
99789. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
99790. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
99791. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
99792. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
99793. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
99794. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
99795. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
99796. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
99797. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
99798. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
99799. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
99800. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
99801. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
99802. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
99803. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
99804. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
99805. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
99806. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
99807. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL__STU_MASK
99808. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL__STU__SHIFT
99809. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
99810. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
99811. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
99812. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
99813. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
99814. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
99815. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST__CAP_ID_MASK
99816. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST__CAP_ID__SHIFT
99817. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST__NEXT_PTR_MASK
99818. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
99819. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__DEVICE_TYPE_MASK
99820. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__DEVICE_TYPE__SHIFT
99821. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
99822. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
99823. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
99824. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
99825. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__VERSION_MASK
99826. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__VERSION__SHIFT
99827. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
99828. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
99829. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
99830. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
99831. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
99832. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
99833. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
99834. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
99835. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
99836. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
99837. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
99838. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
99839. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
99840. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
99841. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
99842. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
99843. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
99844. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
99845. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
99846. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
99847. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
99848. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
99849. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
99850. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
99851. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
99852. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
99853. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
99854. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
99855. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
99856. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
99857. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
99858. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
99859. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0__TLP_HDR_MASK
99860. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
99861. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1__TLP_HDR_MASK
99862. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
99863. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2__TLP_HDR_MASK
99864. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
99865. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3__TLP_HDR_MASK
99866. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
99867. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
99868. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
99869. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
99870. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
99871. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
99872. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
99873. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
99874. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
99875. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
99876. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
99877. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
99878. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
99879. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
99880. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
99881. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
99882. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
99883. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
99884. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
99885. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
99886. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
99887. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
99888. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
99889. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
99890. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
99891. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
99892. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
99893. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
99894. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
99895. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
99896. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
99897. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
99898. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
99899. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
99900. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
99901. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
99902. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
99903. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
99904. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
99905. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
99906. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
99907. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
99908. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
99909. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
99910. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
99911. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
99912. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
99913. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
99914. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
99915. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
99916. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
99917. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
99918. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
99919. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
99920. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
99921. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
99922. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
99923. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
99924. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
99925. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
99926. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
99927. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
99928. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
99929. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
99930. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
99931. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
99932. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
99933. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
99934. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
99935. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
99936. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
99937. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
99938. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
99939. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
99940. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
99941. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
99942. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
99943. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
99944. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
99945. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
99946. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
99947. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
99948. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
99949. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
99950. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
99951. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
99952. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
99953. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
99954. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
99955. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
99956. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
99957. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
99958. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
99959. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
99960. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
99961. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
99962. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
99963. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
99964. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
99965. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
99966. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
99967. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
99968. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
99969. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
99970. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
99971. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
99972. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
99973. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
99974. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
99975. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
99976. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
99977. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
99978. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
99979. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
99980. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
99981. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
99982. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
99983. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
99984. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
99985. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
99986. BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
99987. BIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE__PROG_INTERFACE_MASK
99988. BIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
99989. BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID__MAJOR_REV_ID_MASK
99990. BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID__MAJOR_REV_ID__SHIFT
99991. BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID__MINOR_REV_ID_MASK
99992. BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID__MINOR_REV_ID__SHIFT
99993. BIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR__BASE_ADDR_MASK
99994. BIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
99995. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__CAP_LIST_MASK
99996. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__CAP_LIST__SHIFT
99997. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__DEVSEL_TIMING_MASK
99998. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__DEVSEL_TIMING__SHIFT
99999. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__FAST_BACK_CAPABLE_MASK
100000. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__FAST_BACK_CAPABLE__SHIFT
100001. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__IMMEDIATE_READINESS_MASK
100002. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__IMMEDIATE_READINESS__SHIFT
100003. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__INT_STATUS_MASK
100004. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__INT_STATUS__SHIFT
100005. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
100006. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
100007. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__PARITY_ERROR_DETECTED_MASK
100008. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
100009. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__PCI_66_CAP_MASK
100010. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__PCI_66_CAP__SHIFT
100011. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__RECEIVED_MASTER_ABORT_MASK
100012. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
100013. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__RECEIVED_TARGET_ABORT_MASK
100014. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
100015. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
100016. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
100017. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__SIGNAL_TARGET_ABORT_MASK
100018. BIF_CFG_DEV0_EPF0_VF20_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
100019. BIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS__SUB_CLASS_MASK
100020. BIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS__SUB_CLASS__SHIFT
100021. BIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID__VENDOR_ID_MASK
100022. BIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID__VENDOR_ID__SHIFT
100023. BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID__SUBSYSTEM_ID_MASK
100024. BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
100025. BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
100026. BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
100027. BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_1__BASE_ADDR_MASK
100028. BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_1__BASE_ADDR__SHIFT
100029. BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_2__BASE_ADDR_MASK
100030. BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_2__BASE_ADDR__SHIFT
100031. BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_3__BASE_ADDR_MASK
100032. BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_3__BASE_ADDR__SHIFT
100033. BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_4__BASE_ADDR_MASK
100034. BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_4__BASE_ADDR__SHIFT
100035. BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_5__BASE_ADDR_MASK
100036. BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_5__BASE_ADDR__SHIFT
100037. BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_6__BASE_ADDR_MASK
100038. BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_6__BASE_ADDR__SHIFT
100039. BIF_CFG_DEV0_EPF0_VF20_BASE_CLASS__BASE_CLASS_MASK
100040. BIF_CFG_DEV0_EPF0_VF20_BASE_CLASS__BASE_CLASS__SHIFT
100041. BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_CAP_MASK
100042. BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_CAP__SHIFT
100043. BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_COMP_MASK
100044. BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_COMP__SHIFT
100045. BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_STRT_MASK
100046. BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_STRT__SHIFT
100047. BIF_CFG_DEV0_EPF0_VF20_CACHE_LINE__CACHE_LINE_SIZE_MASK
100048. BIF_CFG_DEV0_EPF0_VF20_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
100049. BIF_CFG_DEV0_EPF0_VF20_CAP_PTR__CAP_PTR_MASK
100050. BIF_CFG_DEV0_EPF0_VF20_CAP_PTR__CAP_PTR__SHIFT
100051. BIF_CFG_DEV0_EPF0_VF20_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
100052. BIF_CFG_DEV0_EPF0_VF20_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
100053. BIF_CFG_DEV0_EPF0_VF20_COMMAND__AD_STEPPING_MASK
100054. BIF_CFG_DEV0_EPF0_VF20_COMMAND__AD_STEPPING__SHIFT
100055. BIF_CFG_DEV0_EPF0_VF20_COMMAND__BUS_MASTER_EN_MASK
100056. BIF_CFG_DEV0_EPF0_VF20_COMMAND__BUS_MASTER_EN__SHIFT
100057. BIF_CFG_DEV0_EPF0_VF20_COMMAND__FAST_B2B_EN_MASK
100058. BIF_CFG_DEV0_EPF0_VF20_COMMAND__FAST_B2B_EN__SHIFT
100059. BIF_CFG_DEV0_EPF0_VF20_COMMAND__INT_DIS_MASK
100060. BIF_CFG_DEV0_EPF0_VF20_COMMAND__INT_DIS__SHIFT
100061. BIF_CFG_DEV0_EPF0_VF20_COMMAND__IO_ACCESS_EN_MASK
100062. BIF_CFG_DEV0_EPF0_VF20_COMMAND__IO_ACCESS_EN__SHIFT
100063. BIF_CFG_DEV0_EPF0_VF20_COMMAND__MEM_ACCESS_EN_MASK
100064. BIF_CFG_DEV0_EPF0_VF20_COMMAND__MEM_ACCESS_EN__SHIFT
100065. BIF_CFG_DEV0_EPF0_VF20_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
100066. BIF_CFG_DEV0_EPF0_VF20_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
100067. BIF_CFG_DEV0_EPF0_VF20_COMMAND__PAL_SNOOP_EN_MASK
100068. BIF_CFG_DEV0_EPF0_VF20_COMMAND__PAL_SNOOP_EN__SHIFT
100069. BIF_CFG_DEV0_EPF0_VF20_COMMAND__PARITY_ERROR_RESPONSE_MASK
100070. BIF_CFG_DEV0_EPF0_VF20_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
100071. BIF_CFG_DEV0_EPF0_VF20_COMMAND__SERR_EN_MASK
100072. BIF_CFG_DEV0_EPF0_VF20_COMMAND__SERR_EN__SHIFT
100073. BIF_CFG_DEV0_EPF0_VF20_COMMAND__SPECIAL_CYCLE_EN_MASK
100074. BIF_CFG_DEV0_EPF0_VF20_COMMAND__SPECIAL_CYCLE_EN__SHIFT
100075. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
100076. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
100077. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
100078. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
100079. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
100080. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
100081. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
100082. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
100083. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
100084. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
100085. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
100086. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
100087. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
100088. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
100089. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
100090. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
100091. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
100092. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
100093. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
100094. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
100095. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
100096. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
100097. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__FRS_SUPPORTED_MASK
100098. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
100099. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
100100. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
100101. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__LTR_SUPPORTED_MASK
100102. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
100103. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
100104. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
100105. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
100106. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
100107. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__OBFF_SUPPORTED_MASK
100108. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
100109. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
100110. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
100111. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
100112. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
100113. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
100114. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
100115. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
100116. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
100117. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
100118. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
100119. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__EXTENDED_TAG_MASK
100120. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__EXTENDED_TAG__SHIFT
100121. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__FLR_CAPABLE_MASK
100122. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__FLR_CAPABLE__SHIFT
100123. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
100124. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
100125. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
100126. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
100127. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
100128. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
100129. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__PHANTOM_FUNC_MASK
100130. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__PHANTOM_FUNC__SHIFT
100131. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
100132. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
100133. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
100134. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
100135. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
100136. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
100137. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
100138. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
100139. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
100140. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
100141. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
100142. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
100143. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
100144. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
100145. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
100146. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
100147. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
100148. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
100149. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
100150. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
100151. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__LTR_EN_MASK
100152. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__LTR_EN__SHIFT
100153. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__OBFF_EN_MASK
100154. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__OBFF_EN__SHIFT
100155. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
100156. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
100157. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
100158. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
100159. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__CORR_ERR_EN_MASK
100160. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__CORR_ERR_EN__SHIFT
100161. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
100162. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
100163. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__FATAL_ERR_EN_MASK
100164. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
100165. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__INITIATE_FLR_MASK
100166. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__INITIATE_FLR__SHIFT
100167. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
100168. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
100169. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
100170. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
100171. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
100172. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
100173. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__NO_SNOOP_EN_MASK
100174. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
100175. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
100176. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
100177. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__RELAXED_ORD_EN_MASK
100178. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
100179. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__USR_REPORT_EN_MASK
100180. BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__USR_REPORT_EN__SHIFT
100181. BIF_CFG_DEV0_EPF0_VF20_DEVICE_ID__DEVICE_ID_MASK
100182. BIF_CFG_DEV0_EPF0_VF20_DEVICE_ID__DEVICE_ID__SHIFT
100183. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS2__RESERVED_MASK
100184. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS2__RESERVED__SHIFT
100185. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__AUX_PWR_MASK
100186. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__AUX_PWR__SHIFT
100187. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__CORR_ERR_MASK
100188. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__CORR_ERR__SHIFT
100189. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
100190. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
100191. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__FATAL_ERR_MASK
100192. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__FATAL_ERR__SHIFT
100193. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__NON_FATAL_ERR_MASK
100194. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
100195. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
100196. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
100197. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__USR_DETECTED_MASK
100198. BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__USR_DETECTED__SHIFT
100199. BIF_CFG_DEV0_EPF0_VF20_HEADER__DEVICE_TYPE_MASK
100200. BIF_CFG_DEV0_EPF0_VF20_HEADER__DEVICE_TYPE__SHIFT
100201. BIF_CFG_DEV0_EPF0_VF20_HEADER__HEADER_TYPE_MASK
100202. BIF_CFG_DEV0_EPF0_VF20_HEADER__HEADER_TYPE__SHIFT
100203. BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_LINE__INTERRUPT_LINE_MASK
100204. BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
100205. BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_PIN__INTERRUPT_PIN_MASK
100206. BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
100207. BIF_CFG_DEV0_EPF0_VF20_LATENCY__LATENCY_TIMER_MASK
100208. BIF_CFG_DEV0_EPF0_VF20_LATENCY__LATENCY_TIMER__SHIFT
100209. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
100210. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
100211. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
100212. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
100213. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
100214. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
100215. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
100216. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
100217. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
100218. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
100219. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
100220. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
100221. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
100222. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
100223. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
100224. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
100225. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
100226. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
100227. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
100228. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
100229. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__L0S_EXIT_LATENCY_MASK
100230. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
100231. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__L1_EXIT_LATENCY_MASK
100232. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__L1_EXIT_LATENCY__SHIFT
100233. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
100234. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
100235. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_SPEED_MASK
100236. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_SPEED__SHIFT
100237. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_WIDTH_MASK
100238. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_WIDTH__SHIFT
100239. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__PM_SUPPORT_MASK
100240. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__PM_SUPPORT__SHIFT
100241. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__PORT_NUMBER_MASK
100242. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__PORT_NUMBER__SHIFT
100243. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
100244. BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
100245. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
100246. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
100247. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__COMPLIANCE_SOS_MASK
100248. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
100249. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__ENTER_COMPLIANCE_MASK
100250. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
100251. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
100252. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
100253. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
100254. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
100255. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
100256. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
100257. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__TARGET_LINK_SPEED_MASK
100258. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
100259. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__XMIT_MARGIN_MASK
100260. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__XMIT_MARGIN__SHIFT
100261. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
100262. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
100263. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__COMMON_CLOCK_CFG_MASK
100264. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
100265. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
100266. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
100267. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__EXTENDED_SYNC_MASK
100268. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__EXTENDED_SYNC__SHIFT
100269. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
100270. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
100271. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
100272. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
100273. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
100274. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
100275. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_DIS_MASK
100276. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_DIS__SHIFT
100277. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__PM_CONTROL_MASK
100278. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__PM_CONTROL__SHIFT
100279. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__READ_CPL_BOUNDARY_MASK
100280. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
100281. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__RETRAIN_LINK_MASK
100282. BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__RETRAIN_LINK__SHIFT
100283. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
100284. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
100285. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
100286. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
100287. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
100288. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
100289. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
100290. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
100291. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
100292. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
100293. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
100294. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
100295. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
100296. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
100297. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
100298. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
100299. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
100300. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
100301. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
100302. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
100303. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
100304. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
100305. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__CURRENT_LINK_SPEED_MASK
100306. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
100307. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__DL_ACTIVE_MASK
100308. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__DL_ACTIVE__SHIFT
100309. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
100310. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
100311. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
100312. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
100313. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_TRAINING_MASK
100314. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_TRAINING__SHIFT
100315. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
100316. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
100317. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__SLOT_CLOCK_CFG_MASK
100318. BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
100319. BIF_CFG_DEV0_EPF0_VF20_MAX_LATENCY__MAX_LAT_MASK
100320. BIF_CFG_DEV0_EPF0_VF20_MAX_LATENCY__MAX_LAT__SHIFT
100321. BIF_CFG_DEV0_EPF0_VF20_MIN_GRANT__MIN_GNT_MASK
100322. BIF_CFG_DEV0_EPF0_VF20_MIN_GRANT__MIN_GNT__SHIFT
100323. BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST__CAP_ID_MASK
100324. BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST__CAP_ID__SHIFT
100325. BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST__NEXT_PTR_MASK
100326. BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST__NEXT_PTR__SHIFT
100327. BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_EN_MASK
100328. BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_EN__SHIFT
100329. BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
100330. BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
100331. BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
100332. BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
100333. BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA__MSIX_PBA_BIR_MASK
100334. BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA__MSIX_PBA_BIR__SHIFT
100335. BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA__MSIX_PBA_OFFSET_MASK
100336. BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
100337. BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE__MSIX_TABLE_BIR_MASK
100338. BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
100339. BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
100340. BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
100341. BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST__CAP_ID_MASK
100342. BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST__CAP_ID__SHIFT
100343. BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST__NEXT_PTR_MASK
100344. BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST__NEXT_PTR__SHIFT
100345. BIF_CFG_DEV0_EPF0_VF20_MSI_MASK_64__MSI_MASK_64_MASK
100346. BIF_CFG_DEV0_EPF0_VF20_MSI_MASK_64__MSI_MASK_64__SHIFT
100347. BIF_CFG_DEV0_EPF0_VF20_MSI_MASK__MSI_MASK_MASK
100348. BIF_CFG_DEV0_EPF0_VF20_MSI_MASK__MSI_MASK__SHIFT
100349. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
100350. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
100351. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
100352. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
100353. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_64BIT_MASK
100354. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_64BIT__SHIFT
100355. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_EN_MASK
100356. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_EN__SHIFT
100357. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
100358. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
100359. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
100360. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
100361. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
100362. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
100363. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA_64__MSI_DATA_64_MASK
100364. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
100365. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA__MSI_DATA_MASK
100366. BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA__MSI_DATA__SHIFT
100367. BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING_64__MSI_PENDING_64_MASK
100368. BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING_64__MSI_PENDING_64__SHIFT
100369. BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING__MSI_PENDING_MASK
100370. BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING__MSI_PENDING__SHIFT
100371. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
100372. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
100373. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
100374. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
100375. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
100376. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
100377. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
100378. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
100379. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
100380. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
100381. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
100382. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
100383. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
100384. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
100385. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
100386. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
100387. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
100388. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
100389. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
100390. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
100391. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
100392. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
100393. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
100394. BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
100395. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
100396. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
100397. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
100398. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
100399. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
100400. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
100401. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
100402. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
100403. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
100404. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
100405. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
100406. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
100407. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
100408. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
100409. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
100410. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
100411. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
100412. BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
100413. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
100414. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
100415. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
100416. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
100417. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
100418. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
100419. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL__ATC_ENABLE_MASK
100420. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
100421. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL__STU_MASK
100422. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL__STU__SHIFT
100423. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
100424. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
100425. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
100426. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
100427. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
100428. BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
100429. BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST__CAP_ID_MASK
100430. BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST__CAP_ID__SHIFT
100431. BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST__NEXT_PTR_MASK
100432. BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST__NEXT_PTR__SHIFT
100433. BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__DEVICE_TYPE_MASK
100434. BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__DEVICE_TYPE__SHIFT
100435. BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__INT_MESSAGE_NUM_MASK
100436. BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
100437. BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__SLOT_IMPLEMENTED_MASK
100438. BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
100439. BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__VERSION_MASK
100440. BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__VERSION__SHIFT
100441. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
100442. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
100443. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
100444. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
100445. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
100446. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
100447. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
100448. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
100449. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
100450. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
100451. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
100452. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
100453. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
100454. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
100455. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
100456. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
100457. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
100458. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
100459. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
100460. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
100461. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
100462. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
100463. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
100464. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
100465. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
100466. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
100467. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
100468. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
100469. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
100470. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
100471. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
100472. BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
100473. BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG0__TLP_HDR_MASK
100474. BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG0__TLP_HDR__SHIFT
100475. BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG1__TLP_HDR_MASK
100476. BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG1__TLP_HDR__SHIFT
100477. BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG2__TLP_HDR_MASK
100478. BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG2__TLP_HDR__SHIFT
100479. BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG3__TLP_HDR_MASK
100480. BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG3__TLP_HDR__SHIFT
100481. BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
100482. BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
100483. BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
100484. BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
100485. BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
100486. BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
100487. BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
100488. BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
100489. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
100490. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
100491. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
100492. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
100493. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
100494. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
100495. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
100496. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
100497. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
100498. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
100499. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
100500. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
100501. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
100502. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
100503. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
100504. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
100505. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
100506. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
100507. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
100508. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
100509. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
100510. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
100511. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
100512. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
100513. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
100514. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
100515. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
100516. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
100517. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
100518. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
100519. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
100520. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
100521. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
100522. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
100523. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
100524. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
100525. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
100526. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
100527. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
100528. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
100529. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
100530. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
100531. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
100532. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
100533. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
100534. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
100535. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
100536. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
100537. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
100538. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
100539. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
100540. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
100541. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
100542. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
100543. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
100544. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
100545. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
100546. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
100547. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
100548. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
100549. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
100550. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
100551. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
100552. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
100553. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
100554. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
100555. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
100556. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
100557. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
100558. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
100559. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
100560. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
100561. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
100562. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
100563. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
100564. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
100565. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
100566. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
100567. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
100568. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
100569. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
100570. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
100571. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
100572. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
100573. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
100574. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
100575. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
100576. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
100577. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
100578. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
100579. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
100580. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
100581. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
100582. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
100583. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
100584. BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
100585. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
100586. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
100587. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
100588. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
100589. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
100590. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
100591. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
100592. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
100593. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
100594. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
100595. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
100596. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
100597. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
100598. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
100599. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
100600. BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
100601. BIF_CFG_DEV0_EPF0_VF20_PROG_INTERFACE__PROG_INTERFACE_MASK
100602. BIF_CFG_DEV0_EPF0_VF20_PROG_INTERFACE__PROG_INTERFACE__SHIFT
100603. BIF_CFG_DEV0_EPF0_VF20_REVISION_ID__MAJOR_REV_ID_MASK
100604. BIF_CFG_DEV0_EPF0_VF20_REVISION_ID__MAJOR_REV_ID__SHIFT
100605. BIF_CFG_DEV0_EPF0_VF20_REVISION_ID__MINOR_REV_ID_MASK
100606. BIF_CFG_DEV0_EPF0_VF20_REVISION_ID__MINOR_REV_ID__SHIFT
100607. BIF_CFG_DEV0_EPF0_VF20_ROM_BASE_ADDR__BASE_ADDR_MASK
100608. BIF_CFG_DEV0_EPF0_VF20_ROM_BASE_ADDR__BASE_ADDR__SHIFT
100609. BIF_CFG_DEV0_EPF0_VF20_STATUS__CAP_LIST_MASK
100610. BIF_CFG_DEV0_EPF0_VF20_STATUS__CAP_LIST__SHIFT
100611. BIF_CFG_DEV0_EPF0_VF20_STATUS__DEVSEL_TIMING_MASK
100612. BIF_CFG_DEV0_EPF0_VF20_STATUS__DEVSEL_TIMING__SHIFT
100613. BIF_CFG_DEV0_EPF0_VF20_STATUS__FAST_BACK_CAPABLE_MASK
100614. BIF_CFG_DEV0_EPF0_VF20_STATUS__FAST_BACK_CAPABLE__SHIFT
100615. BIF_CFG_DEV0_EPF0_VF20_STATUS__IMMEDIATE_READINESS_MASK
100616. BIF_CFG_DEV0_EPF0_VF20_STATUS__IMMEDIATE_READINESS__SHIFT
100617. BIF_CFG_DEV0_EPF0_VF20_STATUS__INT_STATUS_MASK
100618. BIF_CFG_DEV0_EPF0_VF20_STATUS__INT_STATUS__SHIFT
100619. BIF_CFG_DEV0_EPF0_VF20_STATUS__MASTER_DATA_PARITY_ERROR_MASK
100620. BIF_CFG_DEV0_EPF0_VF20_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
100621. BIF_CFG_DEV0_EPF0_VF20_STATUS__PARITY_ERROR_DETECTED_MASK
100622. BIF_CFG_DEV0_EPF0_VF20_STATUS__PARITY_ERROR_DETECTED__SHIFT
100623. BIF_CFG_DEV0_EPF0_VF20_STATUS__PCI_66_CAP_MASK
100624. BIF_CFG_DEV0_EPF0_VF20_STATUS__PCI_66_CAP__SHIFT
100625. BIF_CFG_DEV0_EPF0_VF20_STATUS__RECEIVED_MASTER_ABORT_MASK
100626. BIF_CFG_DEV0_EPF0_VF20_STATUS__RECEIVED_MASTER_ABORT__SHIFT
100627. BIF_CFG_DEV0_EPF0_VF20_STATUS__RECEIVED_TARGET_ABORT_MASK
100628. BIF_CFG_DEV0_EPF0_VF20_STATUS__RECEIVED_TARGET_ABORT__SHIFT
100629. BIF_CFG_DEV0_EPF0_VF20_STATUS__SIGNALED_SYSTEM_ERROR_MASK
100630. BIF_CFG_DEV0_EPF0_VF20_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
100631. BIF_CFG_DEV0_EPF0_VF20_STATUS__SIGNAL_TARGET_ABORT_MASK
100632. BIF_CFG_DEV0_EPF0_VF20_STATUS__SIGNAL_TARGET_ABORT__SHIFT
100633. BIF_CFG_DEV0_EPF0_VF20_SUB_CLASS__SUB_CLASS_MASK
100634. BIF_CFG_DEV0_EPF0_VF20_SUB_CLASS__SUB_CLASS__SHIFT
100635. BIF_CFG_DEV0_EPF0_VF20_VENDOR_ID__VENDOR_ID_MASK
100636. BIF_CFG_DEV0_EPF0_VF20_VENDOR_ID__VENDOR_ID__SHIFT
100637. BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
100638. BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
100639. BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
100640. BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
100641. BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1__BASE_ADDR_MASK
100642. BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1__BASE_ADDR__SHIFT
100643. BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2__BASE_ADDR_MASK
100644. BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2__BASE_ADDR__SHIFT
100645. BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3__BASE_ADDR_MASK
100646. BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3__BASE_ADDR__SHIFT
100647. BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4__BASE_ADDR_MASK
100648. BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4__BASE_ADDR__SHIFT
100649. BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5__BASE_ADDR_MASK
100650. BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5__BASE_ADDR__SHIFT
100651. BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6__BASE_ADDR_MASK
100652. BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6__BASE_ADDR__SHIFT
100653. BIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS__BASE_CLASS_MASK
100654. BIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS__BASE_CLASS__SHIFT
100655. BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_CAP_MASK
100656. BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_CAP__SHIFT
100657. BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_COMP_MASK
100658. BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_COMP__SHIFT
100659. BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_STRT_MASK
100660. BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_STRT__SHIFT
100661. BIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
100662. BIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
100663. BIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR__CAP_PTR_MASK
100664. BIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR__CAP_PTR__SHIFT
100665. BIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
100666. BIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
100667. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__AD_STEPPING_MASK
100668. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__AD_STEPPING__SHIFT
100669. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__BUS_MASTER_EN_MASK
100670. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__BUS_MASTER_EN__SHIFT
100671. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__FAST_B2B_EN_MASK
100672. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__FAST_B2B_EN__SHIFT
100673. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__INT_DIS_MASK
100674. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__INT_DIS__SHIFT
100675. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__IO_ACCESS_EN_MASK
100676. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__IO_ACCESS_EN__SHIFT
100677. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__MEM_ACCESS_EN_MASK
100678. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__MEM_ACCESS_EN__SHIFT
100679. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
100680. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
100681. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__PAL_SNOOP_EN_MASK
100682. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__PAL_SNOOP_EN__SHIFT
100683. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
100684. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
100685. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__SERR_EN_MASK
100686. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__SERR_EN__SHIFT
100687. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__SPECIAL_CYCLE_EN_MASK
100688. BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
100689. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
100690. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
100691. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
100692. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
100693. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
100694. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
100695. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
100696. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
100697. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
100698. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
100699. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
100700. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
100701. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
100702. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
100703. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
100704. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
100705. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
100706. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
100707. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
100708. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
100709. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
100710. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
100711. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
100712. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
100713. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
100714. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
100715. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
100716. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
100717. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
100718. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
100719. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
100720. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
100721. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
100722. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
100723. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
100724. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
100725. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
100726. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
100727. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
100728. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
100729. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
100730. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
100731. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
100732. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
100733. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__EXTENDED_TAG_MASK
100734. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
100735. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__FLR_CAPABLE_MASK
100736. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
100737. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
100738. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
100739. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
100740. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
100741. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
100742. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
100743. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__PHANTOM_FUNC_MASK
100744. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
100745. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
100746. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
100747. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
100748. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
100749. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
100750. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
100751. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
100752. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
100753. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
100754. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
100755. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
100756. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
100757. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
100758. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
100759. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
100760. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
100761. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
100762. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
100763. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
100764. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
100765. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__LTR_EN_MASK
100766. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__LTR_EN__SHIFT
100767. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__OBFF_EN_MASK
100768. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__OBFF_EN__SHIFT
100769. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
100770. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
100771. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
100772. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
100773. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__CORR_ERR_EN_MASK
100774. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
100775. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
100776. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
100777. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
100778. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
100779. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__INITIATE_FLR_MASK
100780. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
100781. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
100782. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
100783. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
100784. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
100785. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
100786. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
100787. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
100788. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
100789. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
100790. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
100791. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
100792. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
100793. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__USR_REPORT_EN_MASK
100794. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
100795. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID__DEVICE_ID_MASK
100796. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID__DEVICE_ID__SHIFT
100797. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2__RESERVED_MASK
100798. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2__RESERVED__SHIFT
100799. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__AUX_PWR_MASK
100800. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__AUX_PWR__SHIFT
100801. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__CORR_ERR_MASK
100802. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__CORR_ERR__SHIFT
100803. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
100804. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
100805. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__FATAL_ERR_MASK
100806. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__FATAL_ERR__SHIFT
100807. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
100808. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
100809. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
100810. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
100811. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__USR_DETECTED_MASK
100812. BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__USR_DETECTED__SHIFT
100813. BIF_CFG_DEV0_EPF0_VF21_0_HEADER__DEVICE_TYPE_MASK
100814. BIF_CFG_DEV0_EPF0_VF21_0_HEADER__DEVICE_TYPE__SHIFT
100815. BIF_CFG_DEV0_EPF0_VF21_0_HEADER__HEADER_TYPE_MASK
100816. BIF_CFG_DEV0_EPF0_VF21_0_HEADER__HEADER_TYPE__SHIFT
100817. BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
100818. BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
100819. BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
100820. BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
100821. BIF_CFG_DEV0_EPF0_VF21_0_LATENCY__LATENCY_TIMER_MASK
100822. BIF_CFG_DEV0_EPF0_VF21_0_LATENCY__LATENCY_TIMER__SHIFT
100823. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
100824. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
100825. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
100826. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
100827. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
100828. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
100829. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
100830. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
100831. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
100832. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
100833. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
100834. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
100835. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
100836. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
100837. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
100838. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
100839. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
100840. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
100841. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
100842. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
100843. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
100844. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
100845. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__L1_EXIT_LATENCY_MASK
100846. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
100847. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
100848. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
100849. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_SPEED_MASK
100850. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_SPEED__SHIFT
100851. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_WIDTH_MASK
100852. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_WIDTH__SHIFT
100853. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__PM_SUPPORT_MASK
100854. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__PM_SUPPORT__SHIFT
100855. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__PORT_NUMBER_MASK
100856. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__PORT_NUMBER__SHIFT
100857. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
100858. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
100859. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
100860. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
100861. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
100862. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
100863. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
100864. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
100865. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
100866. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
100867. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
100868. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
100869. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
100870. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
100871. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
100872. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
100873. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__XMIT_MARGIN_MASK
100874. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
100875. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
100876. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
100877. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
100878. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
100879. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
100880. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
100881. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__EXTENDED_SYNC_MASK
100882. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
100883. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
100884. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
100885. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
100886. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
100887. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
100888. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
100889. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_DIS_MASK
100890. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_DIS__SHIFT
100891. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__PM_CONTROL_MASK
100892. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__PM_CONTROL__SHIFT
100893. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
100894. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
100895. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__RETRAIN_LINK_MASK
100896. BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__RETRAIN_LINK__SHIFT
100897. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
100898. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
100899. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
100900. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
100901. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
100902. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
100903. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
100904. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
100905. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
100906. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
100907. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
100908. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
100909. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
100910. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
100911. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
100912. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
100913. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
100914. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
100915. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
100916. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
100917. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
100918. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
100919. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
100920. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
100921. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__DL_ACTIVE_MASK
100922. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__DL_ACTIVE__SHIFT
100923. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
100924. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
100925. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
100926. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
100927. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_TRAINING_MASK
100928. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_TRAINING__SHIFT
100929. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
100930. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
100931. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
100932. BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
100933. BIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY__MAX_LAT_MASK
100934. BIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY__MAX_LAT__SHIFT
100935. BIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT__MIN_GNT_MASK
100936. BIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT__MIN_GNT__SHIFT
100937. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST__CAP_ID_MASK
100938. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST__CAP_ID__SHIFT
100939. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST__NEXT_PTR_MASK
100940. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
100941. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_EN_MASK
100942. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
100943. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
100944. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
100945. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
100946. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
100947. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA__MSIX_PBA_BIR_MASK
100948. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
100949. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
100950. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
100951. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
100952. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
100953. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
100954. BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
100955. BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST__CAP_ID_MASK
100956. BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST__CAP_ID__SHIFT
100957. BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST__NEXT_PTR_MASK
100958. BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
100959. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64__MSI_MASK_64_MASK
100960. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64__MSI_MASK_64__SHIFT
100961. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK__MSI_MASK_MASK
100962. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK__MSI_MASK__SHIFT
100963. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
100964. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
100965. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
100966. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
100967. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_64BIT_MASK
100968. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
100969. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_EN_MASK
100970. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_EN__SHIFT
100971. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
100972. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
100973. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
100974. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
100975. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
100976. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
100977. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
100978. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
100979. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA__MSI_DATA_MASK
100980. BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA__MSI_DATA__SHIFT
100981. BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64__MSI_PENDING_64_MASK
100982. BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
100983. BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING__MSI_PENDING_MASK
100984. BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING__MSI_PENDING__SHIFT
100985. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
100986. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
100987. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
100988. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
100989. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
100990. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
100991. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
100992. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
100993. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
100994. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
100995. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
100996. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
100997. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
100998. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
100999. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
101000. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
101001. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
101002. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
101003. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
101004. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
101005. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
101006. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
101007. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
101008. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
101009. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
101010. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
101011. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
101012. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
101013. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
101014. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
101015. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
101016. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
101017. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
101018. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
101019. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
101020. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
101021. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
101022. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
101023. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
101024. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
101025. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
101026. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
101027. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
101028. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
101029. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
101030. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
101031. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
101032. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
101033. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
101034. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
101035. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL__STU_MASK
101036. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL__STU__SHIFT
101037. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
101038. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
101039. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
101040. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
101041. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
101042. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
101043. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST__CAP_ID_MASK
101044. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST__CAP_ID__SHIFT
101045. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST__NEXT_PTR_MASK
101046. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
101047. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__DEVICE_TYPE_MASK
101048. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__DEVICE_TYPE__SHIFT
101049. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
101050. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
101051. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
101052. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
101053. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__VERSION_MASK
101054. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__VERSION__SHIFT
101055. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
101056. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
101057. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
101058. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
101059. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
101060. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
101061. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
101062. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
101063. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
101064. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
101065. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
101066. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
101067. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
101068. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
101069. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
101070. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
101071. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
101072. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
101073. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
101074. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
101075. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
101076. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
101077. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
101078. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
101079. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
101080. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
101081. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
101082. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
101083. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
101084. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
101085. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
101086. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
101087. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0__TLP_HDR_MASK
101088. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
101089. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1__TLP_HDR_MASK
101090. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
101091. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2__TLP_HDR_MASK
101092. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
101093. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3__TLP_HDR_MASK
101094. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
101095. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
101096. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
101097. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
101098. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
101099. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
101100. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
101101. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
101102. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
101103. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
101104. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
101105. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
101106. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
101107. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
101108. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
101109. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
101110. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
101111. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
101112. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
101113. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
101114. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
101115. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
101116. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
101117. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
101118. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
101119. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
101120. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
101121. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
101122. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
101123. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
101124. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
101125. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
101126. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
101127. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
101128. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
101129. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
101130. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
101131. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
101132. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
101133. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
101134. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
101135. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
101136. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
101137. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
101138. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
101139. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
101140. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
101141. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
101142. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
101143. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
101144. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
101145. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
101146. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
101147. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
101148. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
101149. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
101150. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
101151. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
101152. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
101153. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
101154. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
101155. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
101156. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
101157. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
101158. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
101159. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
101160. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
101161. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
101162. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
101163. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
101164. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
101165. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
101166. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
101167. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
101168. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
101169. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
101170. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
101171. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
101172. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
101173. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
101174. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
101175. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
101176. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
101177. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
101178. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
101179. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
101180. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
101181. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
101182. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
101183. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
101184. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
101185. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
101186. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
101187. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
101188. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
101189. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
101190. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
101191. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
101192. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
101193. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
101194. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
101195. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
101196. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
101197. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
101198. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
101199. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
101200. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
101201. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
101202. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
101203. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
101204. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
101205. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
101206. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
101207. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
101208. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
101209. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
101210. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
101211. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
101212. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
101213. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
101214. BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
101215. BIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE__PROG_INTERFACE_MASK
101216. BIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
101217. BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID__MAJOR_REV_ID_MASK
101218. BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID__MAJOR_REV_ID__SHIFT
101219. BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID__MINOR_REV_ID_MASK
101220. BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID__MINOR_REV_ID__SHIFT
101221. BIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR__BASE_ADDR_MASK
101222. BIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
101223. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__CAP_LIST_MASK
101224. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__CAP_LIST__SHIFT
101225. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__DEVSEL_TIMING_MASK
101226. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__DEVSEL_TIMING__SHIFT
101227. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__FAST_BACK_CAPABLE_MASK
101228. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__FAST_BACK_CAPABLE__SHIFT
101229. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__IMMEDIATE_READINESS_MASK
101230. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__IMMEDIATE_READINESS__SHIFT
101231. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__INT_STATUS_MASK
101232. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__INT_STATUS__SHIFT
101233. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
101234. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
101235. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__PARITY_ERROR_DETECTED_MASK
101236. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
101237. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__PCI_66_CAP_MASK
101238. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__PCI_66_CAP__SHIFT
101239. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__RECEIVED_MASTER_ABORT_MASK
101240. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
101241. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__RECEIVED_TARGET_ABORT_MASK
101242. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
101243. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
101244. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
101245. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__SIGNAL_TARGET_ABORT_MASK
101246. BIF_CFG_DEV0_EPF0_VF21_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
101247. BIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS__SUB_CLASS_MASK
101248. BIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS__SUB_CLASS__SHIFT
101249. BIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID__VENDOR_ID_MASK
101250. BIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID__VENDOR_ID__SHIFT
101251. BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
101252. BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
101253. BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
101254. BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
101255. BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1__BASE_ADDR_MASK
101256. BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1__BASE_ADDR__SHIFT
101257. BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2__BASE_ADDR_MASK
101258. BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2__BASE_ADDR__SHIFT
101259. BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3__BASE_ADDR_MASK
101260. BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3__BASE_ADDR__SHIFT
101261. BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4__BASE_ADDR_MASK
101262. BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4__BASE_ADDR__SHIFT
101263. BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5__BASE_ADDR_MASK
101264. BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5__BASE_ADDR__SHIFT
101265. BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6__BASE_ADDR_MASK
101266. BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6__BASE_ADDR__SHIFT
101267. BIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS__BASE_CLASS_MASK
101268. BIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS__BASE_CLASS__SHIFT
101269. BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_CAP_MASK
101270. BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_CAP__SHIFT
101271. BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_COMP_MASK
101272. BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_COMP__SHIFT
101273. BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_STRT_MASK
101274. BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_STRT__SHIFT
101275. BIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
101276. BIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
101277. BIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR__CAP_PTR_MASK
101278. BIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR__CAP_PTR__SHIFT
101279. BIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
101280. BIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
101281. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__AD_STEPPING_MASK
101282. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__AD_STEPPING__SHIFT
101283. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__BUS_MASTER_EN_MASK
101284. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__BUS_MASTER_EN__SHIFT
101285. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__FAST_B2B_EN_MASK
101286. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__FAST_B2B_EN__SHIFT
101287. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__INT_DIS_MASK
101288. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__INT_DIS__SHIFT
101289. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__IO_ACCESS_EN_MASK
101290. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__IO_ACCESS_EN__SHIFT
101291. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__MEM_ACCESS_EN_MASK
101292. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__MEM_ACCESS_EN__SHIFT
101293. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
101294. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
101295. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__PAL_SNOOP_EN_MASK
101296. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__PAL_SNOOP_EN__SHIFT
101297. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
101298. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
101299. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__SERR_EN_MASK
101300. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__SERR_EN__SHIFT
101301. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__SPECIAL_CYCLE_EN_MASK
101302. BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
101303. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
101304. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
101305. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
101306. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
101307. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
101308. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
101309. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
101310. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
101311. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
101312. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
101313. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
101314. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
101315. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
101316. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
101317. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
101318. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
101319. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
101320. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
101321. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
101322. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
101323. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
101324. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
101325. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
101326. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
101327. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
101328. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
101329. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
101330. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
101331. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
101332. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
101333. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
101334. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
101335. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
101336. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
101337. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
101338. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
101339. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
101340. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
101341. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
101342. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
101343. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
101344. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
101345. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
101346. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
101347. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__EXTENDED_TAG_MASK
101348. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
101349. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__FLR_CAPABLE_MASK
101350. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
101351. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
101352. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
101353. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
101354. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
101355. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
101356. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
101357. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__PHANTOM_FUNC_MASK
101358. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
101359. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
101360. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
101361. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
101362. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
101363. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
101364. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
101365. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
101366. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
101367. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
101368. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
101369. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
101370. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
101371. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
101372. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
101373. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
101374. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
101375. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
101376. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
101377. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
101378. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
101379. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__LTR_EN_MASK
101380. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__LTR_EN__SHIFT
101381. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__OBFF_EN_MASK
101382. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__OBFF_EN__SHIFT
101383. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
101384. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
101385. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
101386. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
101387. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__CORR_ERR_EN_MASK
101388. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
101389. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
101390. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
101391. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
101392. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
101393. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__INITIATE_FLR_MASK
101394. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
101395. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
101396. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
101397. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
101398. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
101399. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
101400. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
101401. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
101402. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
101403. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
101404. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
101405. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
101406. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
101407. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__USR_REPORT_EN_MASK
101408. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
101409. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID__DEVICE_ID_MASK
101410. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID__DEVICE_ID__SHIFT
101411. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2__RESERVED_MASK
101412. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2__RESERVED__SHIFT
101413. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__AUX_PWR_MASK
101414. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__AUX_PWR__SHIFT
101415. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__CORR_ERR_MASK
101416. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__CORR_ERR__SHIFT
101417. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
101418. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
101419. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__FATAL_ERR_MASK
101420. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__FATAL_ERR__SHIFT
101421. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
101422. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
101423. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
101424. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
101425. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__USR_DETECTED_MASK
101426. BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__USR_DETECTED__SHIFT
101427. BIF_CFG_DEV0_EPF0_VF21_1_HEADER__DEVICE_TYPE_MASK
101428. BIF_CFG_DEV0_EPF0_VF21_1_HEADER__DEVICE_TYPE__SHIFT
101429. BIF_CFG_DEV0_EPF0_VF21_1_HEADER__HEADER_TYPE_MASK
101430. BIF_CFG_DEV0_EPF0_VF21_1_HEADER__HEADER_TYPE__SHIFT
101431. BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
101432. BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
101433. BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
101434. BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
101435. BIF_CFG_DEV0_EPF0_VF21_1_LATENCY__LATENCY_TIMER_MASK
101436. BIF_CFG_DEV0_EPF0_VF21_1_LATENCY__LATENCY_TIMER__SHIFT
101437. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
101438. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
101439. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
101440. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
101441. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
101442. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
101443. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
101444. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
101445. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
101446. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
101447. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
101448. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
101449. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
101450. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
101451. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
101452. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
101453. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
101454. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
101455. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
101456. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
101457. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
101458. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
101459. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__L1_EXIT_LATENCY_MASK
101460. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
101461. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
101462. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
101463. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_SPEED_MASK
101464. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_SPEED__SHIFT
101465. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_WIDTH_MASK
101466. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_WIDTH__SHIFT
101467. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__PM_SUPPORT_MASK
101468. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__PM_SUPPORT__SHIFT
101469. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__PORT_NUMBER_MASK
101470. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__PORT_NUMBER__SHIFT
101471. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
101472. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
101473. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
101474. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
101475. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
101476. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
101477. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
101478. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
101479. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
101480. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
101481. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
101482. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
101483. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
101484. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
101485. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
101486. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
101487. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__XMIT_MARGIN_MASK
101488. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
101489. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
101490. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
101491. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
101492. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
101493. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
101494. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
101495. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__EXTENDED_SYNC_MASK
101496. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
101497. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
101498. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
101499. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
101500. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
101501. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
101502. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
101503. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_DIS_MASK
101504. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_DIS__SHIFT
101505. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__PM_CONTROL_MASK
101506. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__PM_CONTROL__SHIFT
101507. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
101508. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
101509. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__RETRAIN_LINK_MASK
101510. BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__RETRAIN_LINK__SHIFT
101511. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
101512. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
101513. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
101514. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
101515. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
101516. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
101517. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
101518. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
101519. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
101520. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
101521. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
101522. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
101523. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
101524. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
101525. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
101526. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
101527. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
101528. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
101529. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
101530. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
101531. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
101532. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
101533. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
101534. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
101535. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__DL_ACTIVE_MASK
101536. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__DL_ACTIVE__SHIFT
101537. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
101538. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
101539. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
101540. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
101541. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_TRAINING_MASK
101542. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_TRAINING__SHIFT
101543. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
101544. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
101545. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
101546. BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
101547. BIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY__MAX_LAT_MASK
101548. BIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY__MAX_LAT__SHIFT
101549. BIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT__MIN_GNT_MASK
101550. BIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT__MIN_GNT__SHIFT
101551. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST__CAP_ID_MASK
101552. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST__CAP_ID__SHIFT
101553. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST__NEXT_PTR_MASK
101554. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
101555. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_EN_MASK
101556. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
101557. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
101558. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
101559. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
101560. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
101561. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA__MSIX_PBA_BIR_MASK
101562. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
101563. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
101564. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
101565. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
101566. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
101567. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
101568. BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
101569. BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST__CAP_ID_MASK
101570. BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST__CAP_ID__SHIFT
101571. BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST__NEXT_PTR_MASK
101572. BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
101573. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64__MSI_MASK_64_MASK
101574. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64__MSI_MASK_64__SHIFT
101575. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK__MSI_MASK_MASK
101576. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK__MSI_MASK__SHIFT
101577. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
101578. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
101579. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
101580. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
101581. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_64BIT_MASK
101582. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
101583. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_EN_MASK
101584. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_EN__SHIFT
101585. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
101586. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
101587. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
101588. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
101589. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
101590. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
101591. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
101592. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
101593. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA__MSI_DATA_MASK
101594. BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA__MSI_DATA__SHIFT
101595. BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64__MSI_PENDING_64_MASK
101596. BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
101597. BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING__MSI_PENDING_MASK
101598. BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING__MSI_PENDING__SHIFT
101599. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
101600. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
101601. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
101602. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
101603. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
101604. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
101605. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
101606. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
101607. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
101608. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
101609. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
101610. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
101611. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
101612. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
101613. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
101614. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
101615. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
101616. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
101617. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
101618. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
101619. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
101620. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
101621. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
101622. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
101623. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
101624. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
101625. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
101626. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
101627. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
101628. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
101629. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
101630. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
101631. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
101632. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
101633. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
101634. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
101635. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
101636. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
101637. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
101638. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
101639. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
101640. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
101641. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
101642. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
101643. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
101644. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
101645. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
101646. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
101647. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
101648. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
101649. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL__STU_MASK
101650. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL__STU__SHIFT
101651. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
101652. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
101653. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
101654. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
101655. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
101656. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
101657. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST__CAP_ID_MASK
101658. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST__CAP_ID__SHIFT
101659. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST__NEXT_PTR_MASK
101660. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
101661. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__DEVICE_TYPE_MASK
101662. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__DEVICE_TYPE__SHIFT
101663. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
101664. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
101665. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
101666. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
101667. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__VERSION_MASK
101668. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__VERSION__SHIFT
101669. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
101670. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
101671. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
101672. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
101673. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
101674. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
101675. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
101676. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
101677. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
101678. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
101679. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
101680. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
101681. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
101682. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
101683. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
101684. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
101685. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
101686. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
101687. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
101688. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
101689. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
101690. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
101691. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
101692. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
101693. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
101694. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
101695. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
101696. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
101697. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
101698. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
101699. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
101700. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
101701. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0__TLP_HDR_MASK
101702. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
101703. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1__TLP_HDR_MASK
101704. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
101705. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2__TLP_HDR_MASK
101706. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
101707. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3__TLP_HDR_MASK
101708. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
101709. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
101710. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
101711. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
101712. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
101713. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
101714. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
101715. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
101716. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
101717. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
101718. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
101719. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
101720. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
101721. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
101722. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
101723. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
101724. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
101725. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
101726. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
101727. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
101728. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
101729. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
101730. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
101731. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
101732. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
101733. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
101734. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
101735. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
101736. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
101737. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
101738. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
101739. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
101740. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
101741. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
101742. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
101743. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
101744. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
101745. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
101746. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
101747. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
101748. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
101749. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
101750. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
101751. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
101752. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
101753. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
101754. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
101755. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
101756. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
101757. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
101758. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
101759. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
101760. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
101761. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
101762. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
101763. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
101764. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
101765. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
101766. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
101767. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
101768. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
101769. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
101770. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
101771. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
101772. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
101773. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
101774. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
101775. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
101776. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
101777. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
101778. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
101779. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
101780. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
101781. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
101782. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
101783. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
101784. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
101785. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
101786. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
101787. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
101788. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
101789. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
101790. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
101791. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
101792. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
101793. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
101794. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
101795. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
101796. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
101797. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
101798. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
101799. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
101800. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
101801. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
101802. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
101803. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
101804. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
101805. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
101806. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
101807. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
101808. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
101809. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
101810. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
101811. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
101812. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
101813. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
101814. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
101815. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
101816. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
101817. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
101818. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
101819. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
101820. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
101821. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
101822. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
101823. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
101824. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
101825. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
101826. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
101827. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
101828. BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
101829. BIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE__PROG_INTERFACE_MASK
101830. BIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
101831. BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID__MAJOR_REV_ID_MASK
101832. BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID__MAJOR_REV_ID__SHIFT
101833. BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID__MINOR_REV_ID_MASK
101834. BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID__MINOR_REV_ID__SHIFT
101835. BIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR__BASE_ADDR_MASK
101836. BIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
101837. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__CAP_LIST_MASK
101838. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__CAP_LIST__SHIFT
101839. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__DEVSEL_TIMING_MASK
101840. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__DEVSEL_TIMING__SHIFT
101841. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__FAST_BACK_CAPABLE_MASK
101842. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__FAST_BACK_CAPABLE__SHIFT
101843. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__IMMEDIATE_READINESS_MASK
101844. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__IMMEDIATE_READINESS__SHIFT
101845. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__INT_STATUS_MASK
101846. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__INT_STATUS__SHIFT
101847. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
101848. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
101849. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__PARITY_ERROR_DETECTED_MASK
101850. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
101851. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__PCI_66_CAP_MASK
101852. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__PCI_66_CAP__SHIFT
101853. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__RECEIVED_MASTER_ABORT_MASK
101854. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
101855. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__RECEIVED_TARGET_ABORT_MASK
101856. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
101857. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
101858. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
101859. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__SIGNAL_TARGET_ABORT_MASK
101860. BIF_CFG_DEV0_EPF0_VF21_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
101861. BIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS__SUB_CLASS_MASK
101862. BIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS__SUB_CLASS__SHIFT
101863. BIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID__VENDOR_ID_MASK
101864. BIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID__VENDOR_ID__SHIFT
101865. BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID__SUBSYSTEM_ID_MASK
101866. BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
101867. BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
101868. BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
101869. BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_1__BASE_ADDR_MASK
101870. BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_1__BASE_ADDR__SHIFT
101871. BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_2__BASE_ADDR_MASK
101872. BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_2__BASE_ADDR__SHIFT
101873. BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_3__BASE_ADDR_MASK
101874. BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_3__BASE_ADDR__SHIFT
101875. BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_4__BASE_ADDR_MASK
101876. BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_4__BASE_ADDR__SHIFT
101877. BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_5__BASE_ADDR_MASK
101878. BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_5__BASE_ADDR__SHIFT
101879. BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_6__BASE_ADDR_MASK
101880. BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_6__BASE_ADDR__SHIFT
101881. BIF_CFG_DEV0_EPF0_VF21_BASE_CLASS__BASE_CLASS_MASK
101882. BIF_CFG_DEV0_EPF0_VF21_BASE_CLASS__BASE_CLASS__SHIFT
101883. BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_CAP_MASK
101884. BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_CAP__SHIFT
101885. BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_COMP_MASK
101886. BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_COMP__SHIFT
101887. BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_STRT_MASK
101888. BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_STRT__SHIFT
101889. BIF_CFG_DEV0_EPF0_VF21_CACHE_LINE__CACHE_LINE_SIZE_MASK
101890. BIF_CFG_DEV0_EPF0_VF21_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
101891. BIF_CFG_DEV0_EPF0_VF21_CAP_PTR__CAP_PTR_MASK
101892. BIF_CFG_DEV0_EPF0_VF21_CAP_PTR__CAP_PTR__SHIFT
101893. BIF_CFG_DEV0_EPF0_VF21_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
101894. BIF_CFG_DEV0_EPF0_VF21_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
101895. BIF_CFG_DEV0_EPF0_VF21_COMMAND__AD_STEPPING_MASK
101896. BIF_CFG_DEV0_EPF0_VF21_COMMAND__AD_STEPPING__SHIFT
101897. BIF_CFG_DEV0_EPF0_VF21_COMMAND__BUS_MASTER_EN_MASK
101898. BIF_CFG_DEV0_EPF0_VF21_COMMAND__BUS_MASTER_EN__SHIFT
101899. BIF_CFG_DEV0_EPF0_VF21_COMMAND__FAST_B2B_EN_MASK
101900. BIF_CFG_DEV0_EPF0_VF21_COMMAND__FAST_B2B_EN__SHIFT
101901. BIF_CFG_DEV0_EPF0_VF21_COMMAND__INT_DIS_MASK
101902. BIF_CFG_DEV0_EPF0_VF21_COMMAND__INT_DIS__SHIFT
101903. BIF_CFG_DEV0_EPF0_VF21_COMMAND__IO_ACCESS_EN_MASK
101904. BIF_CFG_DEV0_EPF0_VF21_COMMAND__IO_ACCESS_EN__SHIFT
101905. BIF_CFG_DEV0_EPF0_VF21_COMMAND__MEM_ACCESS_EN_MASK
101906. BIF_CFG_DEV0_EPF0_VF21_COMMAND__MEM_ACCESS_EN__SHIFT
101907. BIF_CFG_DEV0_EPF0_VF21_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
101908. BIF_CFG_DEV0_EPF0_VF21_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
101909. BIF_CFG_DEV0_EPF0_VF21_COMMAND__PAL_SNOOP_EN_MASK
101910. BIF_CFG_DEV0_EPF0_VF21_COMMAND__PAL_SNOOP_EN__SHIFT
101911. BIF_CFG_DEV0_EPF0_VF21_COMMAND__PARITY_ERROR_RESPONSE_MASK
101912. BIF_CFG_DEV0_EPF0_VF21_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
101913. BIF_CFG_DEV0_EPF0_VF21_COMMAND__SERR_EN_MASK
101914. BIF_CFG_DEV0_EPF0_VF21_COMMAND__SERR_EN__SHIFT
101915. BIF_CFG_DEV0_EPF0_VF21_COMMAND__SPECIAL_CYCLE_EN_MASK
101916. BIF_CFG_DEV0_EPF0_VF21_COMMAND__SPECIAL_CYCLE_EN__SHIFT
101917. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
101918. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
101919. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
101920. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
101921. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
101922. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
101923. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
101924. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
101925. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
101926. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
101927. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
101928. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
101929. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
101930. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
101931. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
101932. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
101933. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
101934. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
101935. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
101936. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
101937. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
101938. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
101939. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__FRS_SUPPORTED_MASK
101940. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
101941. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
101942. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
101943. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__LTR_SUPPORTED_MASK
101944. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
101945. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
101946. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
101947. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
101948. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
101949. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__OBFF_SUPPORTED_MASK
101950. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
101951. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
101952. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
101953. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
101954. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
101955. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
101956. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
101957. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
101958. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
101959. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
101960. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
101961. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__EXTENDED_TAG_MASK
101962. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__EXTENDED_TAG__SHIFT
101963. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__FLR_CAPABLE_MASK
101964. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__FLR_CAPABLE__SHIFT
101965. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
101966. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
101967. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
101968. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
101969. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
101970. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
101971. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__PHANTOM_FUNC_MASK
101972. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__PHANTOM_FUNC__SHIFT
101973. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
101974. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
101975. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
101976. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
101977. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
101978. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
101979. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
101980. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
101981. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
101982. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
101983. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
101984. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
101985. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
101986. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
101987. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
101988. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
101989. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
101990. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
101991. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
101992. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
101993. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__LTR_EN_MASK
101994. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__LTR_EN__SHIFT
101995. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__OBFF_EN_MASK
101996. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__OBFF_EN__SHIFT
101997. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
101998. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
101999. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
102000. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
102001. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__CORR_ERR_EN_MASK
102002. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__CORR_ERR_EN__SHIFT
102003. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
102004. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
102005. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__FATAL_ERR_EN_MASK
102006. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
102007. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__INITIATE_FLR_MASK
102008. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__INITIATE_FLR__SHIFT
102009. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
102010. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
102011. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
102012. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
102013. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
102014. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
102015. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__NO_SNOOP_EN_MASK
102016. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
102017. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
102018. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
102019. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__RELAXED_ORD_EN_MASK
102020. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
102021. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__USR_REPORT_EN_MASK
102022. BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__USR_REPORT_EN__SHIFT
102023. BIF_CFG_DEV0_EPF0_VF21_DEVICE_ID__DEVICE_ID_MASK
102024. BIF_CFG_DEV0_EPF0_VF21_DEVICE_ID__DEVICE_ID__SHIFT
102025. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS2__RESERVED_MASK
102026. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS2__RESERVED__SHIFT
102027. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__AUX_PWR_MASK
102028. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__AUX_PWR__SHIFT
102029. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__CORR_ERR_MASK
102030. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__CORR_ERR__SHIFT
102031. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
102032. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
102033. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__FATAL_ERR_MASK
102034. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__FATAL_ERR__SHIFT
102035. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__NON_FATAL_ERR_MASK
102036. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
102037. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
102038. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
102039. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__USR_DETECTED_MASK
102040. BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__USR_DETECTED__SHIFT
102041. BIF_CFG_DEV0_EPF0_VF21_HEADER__DEVICE_TYPE_MASK
102042. BIF_CFG_DEV0_EPF0_VF21_HEADER__DEVICE_TYPE__SHIFT
102043. BIF_CFG_DEV0_EPF0_VF21_HEADER__HEADER_TYPE_MASK
102044. BIF_CFG_DEV0_EPF0_VF21_HEADER__HEADER_TYPE__SHIFT
102045. BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_LINE__INTERRUPT_LINE_MASK
102046. BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
102047. BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_PIN__INTERRUPT_PIN_MASK
102048. BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
102049. BIF_CFG_DEV0_EPF0_VF21_LATENCY__LATENCY_TIMER_MASK
102050. BIF_CFG_DEV0_EPF0_VF21_LATENCY__LATENCY_TIMER__SHIFT
102051. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
102052. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
102053. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
102054. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
102055. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
102056. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
102057. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
102058. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
102059. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
102060. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
102061. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
102062. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
102063. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
102064. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
102065. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
102066. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
102067. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
102068. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
102069. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
102070. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
102071. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__L0S_EXIT_LATENCY_MASK
102072. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
102073. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__L1_EXIT_LATENCY_MASK
102074. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__L1_EXIT_LATENCY__SHIFT
102075. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
102076. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
102077. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_SPEED_MASK
102078. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_SPEED__SHIFT
102079. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_WIDTH_MASK
102080. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_WIDTH__SHIFT
102081. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__PM_SUPPORT_MASK
102082. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__PM_SUPPORT__SHIFT
102083. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__PORT_NUMBER_MASK
102084. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__PORT_NUMBER__SHIFT
102085. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
102086. BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
102087. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
102088. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
102089. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__COMPLIANCE_SOS_MASK
102090. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
102091. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__ENTER_COMPLIANCE_MASK
102092. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
102093. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
102094. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
102095. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
102096. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
102097. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
102098. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
102099. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__TARGET_LINK_SPEED_MASK
102100. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
102101. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__XMIT_MARGIN_MASK
102102. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__XMIT_MARGIN__SHIFT
102103. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
102104. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
102105. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__COMMON_CLOCK_CFG_MASK
102106. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
102107. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
102108. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
102109. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__EXTENDED_SYNC_MASK
102110. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__EXTENDED_SYNC__SHIFT
102111. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
102112. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
102113. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
102114. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
102115. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
102116. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
102117. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_DIS_MASK
102118. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_DIS__SHIFT
102119. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__PM_CONTROL_MASK
102120. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__PM_CONTROL__SHIFT
102121. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__READ_CPL_BOUNDARY_MASK
102122. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
102123. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__RETRAIN_LINK_MASK
102124. BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__RETRAIN_LINK__SHIFT
102125. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
102126. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
102127. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
102128. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
102129. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
102130. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
102131. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
102132. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
102133. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
102134. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
102135. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
102136. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
102137. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
102138. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
102139. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
102140. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
102141. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
102142. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
102143. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
102144. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
102145. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
102146. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
102147. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__CURRENT_LINK_SPEED_MASK
102148. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
102149. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__DL_ACTIVE_MASK
102150. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__DL_ACTIVE__SHIFT
102151. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
102152. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
102153. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
102154. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
102155. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_TRAINING_MASK
102156. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_TRAINING__SHIFT
102157. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
102158. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
102159. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__SLOT_CLOCK_CFG_MASK
102160. BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
102161. BIF_CFG_DEV0_EPF0_VF21_MAX_LATENCY__MAX_LAT_MASK
102162. BIF_CFG_DEV0_EPF0_VF21_MAX_LATENCY__MAX_LAT__SHIFT
102163. BIF_CFG_DEV0_EPF0_VF21_MIN_GRANT__MIN_GNT_MASK
102164. BIF_CFG_DEV0_EPF0_VF21_MIN_GRANT__MIN_GNT__SHIFT
102165. BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST__CAP_ID_MASK
102166. BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST__CAP_ID__SHIFT
102167. BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST__NEXT_PTR_MASK
102168. BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST__NEXT_PTR__SHIFT
102169. BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_EN_MASK
102170. BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_EN__SHIFT
102171. BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
102172. BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
102173. BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
102174. BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
102175. BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA__MSIX_PBA_BIR_MASK
102176. BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA__MSIX_PBA_BIR__SHIFT
102177. BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA__MSIX_PBA_OFFSET_MASK
102178. BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
102179. BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE__MSIX_TABLE_BIR_MASK
102180. BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
102181. BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
102182. BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
102183. BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST__CAP_ID_MASK
102184. BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST__CAP_ID__SHIFT
102185. BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST__NEXT_PTR_MASK
102186. BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST__NEXT_PTR__SHIFT
102187. BIF_CFG_DEV0_EPF0_VF21_MSI_MASK_64__MSI_MASK_64_MASK
102188. BIF_CFG_DEV0_EPF0_VF21_MSI_MASK_64__MSI_MASK_64__SHIFT
102189. BIF_CFG_DEV0_EPF0_VF21_MSI_MASK__MSI_MASK_MASK
102190. BIF_CFG_DEV0_EPF0_VF21_MSI_MASK__MSI_MASK__SHIFT
102191. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
102192. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
102193. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
102194. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
102195. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_64BIT_MASK
102196. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_64BIT__SHIFT
102197. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_EN_MASK
102198. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_EN__SHIFT
102199. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
102200. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
102201. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
102202. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
102203. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
102204. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
102205. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA_64__MSI_DATA_64_MASK
102206. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
102207. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA__MSI_DATA_MASK
102208. BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA__MSI_DATA__SHIFT
102209. BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING_64__MSI_PENDING_64_MASK
102210. BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING_64__MSI_PENDING_64__SHIFT
102211. BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING__MSI_PENDING_MASK
102212. BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING__MSI_PENDING__SHIFT
102213. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
102214. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
102215. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
102216. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
102217. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
102218. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
102219. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
102220. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
102221. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
102222. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
102223. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
102224. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
102225. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
102226. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
102227. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
102228. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
102229. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
102230. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
102231. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
102232. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
102233. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
102234. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
102235. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
102236. BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
102237. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
102238. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
102239. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
102240. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
102241. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
102242. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
102243. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
102244. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
102245. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
102246. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
102247. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
102248. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
102249. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
102250. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
102251. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
102252. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
102253. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
102254. BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
102255. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
102256. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
102257. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
102258. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
102259. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
102260. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
102261. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL__ATC_ENABLE_MASK
102262. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
102263. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL__STU_MASK
102264. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL__STU__SHIFT
102265. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
102266. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
102267. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
102268. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
102269. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
102270. BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
102271. BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST__CAP_ID_MASK
102272. BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST__CAP_ID__SHIFT
102273. BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST__NEXT_PTR_MASK
102274. BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST__NEXT_PTR__SHIFT
102275. BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__DEVICE_TYPE_MASK
102276. BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__DEVICE_TYPE__SHIFT
102277. BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__INT_MESSAGE_NUM_MASK
102278. BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
102279. BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__SLOT_IMPLEMENTED_MASK
102280. BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
102281. BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__VERSION_MASK
102282. BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__VERSION__SHIFT
102283. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
102284. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
102285. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
102286. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
102287. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
102288. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
102289. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
102290. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
102291. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
102292. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
102293. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
102294. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
102295. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
102296. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
102297. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
102298. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
102299. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
102300. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
102301. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
102302. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
102303. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
102304. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
102305. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
102306. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
102307. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
102308. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
102309. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
102310. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
102311. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
102312. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
102313. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
102314. BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
102315. BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG0__TLP_HDR_MASK
102316. BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG0__TLP_HDR__SHIFT
102317. BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG1__TLP_HDR_MASK
102318. BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG1__TLP_HDR__SHIFT
102319. BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG2__TLP_HDR_MASK
102320. BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG2__TLP_HDR__SHIFT
102321. BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG3__TLP_HDR_MASK
102322. BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG3__TLP_HDR__SHIFT
102323. BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
102324. BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
102325. BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
102326. BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
102327. BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
102328. BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
102329. BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
102330. BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
102331. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
102332. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
102333. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
102334. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
102335. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
102336. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
102337. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
102338. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
102339. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
102340. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
102341. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
102342. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
102343. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
102344. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
102345. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
102346. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
102347. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
102348. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
102349. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
102350. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
102351. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
102352. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
102353. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
102354. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
102355. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
102356. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
102357. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
102358. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
102359. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
102360. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
102361. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
102362. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
102363. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
102364. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
102365. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
102366. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
102367. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
102368. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
102369. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
102370. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
102371. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
102372. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
102373. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
102374. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
102375. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
102376. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
102377. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
102378. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
102379. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
102380. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
102381. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
102382. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
102383. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
102384. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
102385. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
102386. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
102387. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
102388. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
102389. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
102390. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
102391. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
102392. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
102393. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
102394. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
102395. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
102396. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
102397. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
102398. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
102399. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
102400. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
102401. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
102402. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
102403. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
102404. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
102405. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
102406. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
102407. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
102408. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
102409. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
102410. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
102411. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
102412. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
102413. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
102414. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
102415. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
102416. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
102417. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
102418. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
102419. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
102420. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
102421. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
102422. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
102423. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
102424. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
102425. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
102426. BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
102427. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
102428. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
102429. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
102430. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
102431. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
102432. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
102433. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
102434. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
102435. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
102436. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
102437. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
102438. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
102439. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
102440. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
102441. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
102442. BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
102443. BIF_CFG_DEV0_EPF0_VF21_PROG_INTERFACE__PROG_INTERFACE_MASK
102444. BIF_CFG_DEV0_EPF0_VF21_PROG_INTERFACE__PROG_INTERFACE__SHIFT
102445. BIF_CFG_DEV0_EPF0_VF21_REVISION_ID__MAJOR_REV_ID_MASK
102446. BIF_CFG_DEV0_EPF0_VF21_REVISION_ID__MAJOR_REV_ID__SHIFT
102447. BIF_CFG_DEV0_EPF0_VF21_REVISION_ID__MINOR_REV_ID_MASK
102448. BIF_CFG_DEV0_EPF0_VF21_REVISION_ID__MINOR_REV_ID__SHIFT
102449. BIF_CFG_DEV0_EPF0_VF21_ROM_BASE_ADDR__BASE_ADDR_MASK
102450. BIF_CFG_DEV0_EPF0_VF21_ROM_BASE_ADDR__BASE_ADDR__SHIFT
102451. BIF_CFG_DEV0_EPF0_VF21_STATUS__CAP_LIST_MASK
102452. BIF_CFG_DEV0_EPF0_VF21_STATUS__CAP_LIST__SHIFT
102453. BIF_CFG_DEV0_EPF0_VF21_STATUS__DEVSEL_TIMING_MASK
102454. BIF_CFG_DEV0_EPF0_VF21_STATUS__DEVSEL_TIMING__SHIFT
102455. BIF_CFG_DEV0_EPF0_VF21_STATUS__FAST_BACK_CAPABLE_MASK
102456. BIF_CFG_DEV0_EPF0_VF21_STATUS__FAST_BACK_CAPABLE__SHIFT
102457. BIF_CFG_DEV0_EPF0_VF21_STATUS__IMMEDIATE_READINESS_MASK
102458. BIF_CFG_DEV0_EPF0_VF21_STATUS__IMMEDIATE_READINESS__SHIFT
102459. BIF_CFG_DEV0_EPF0_VF21_STATUS__INT_STATUS_MASK
102460. BIF_CFG_DEV0_EPF0_VF21_STATUS__INT_STATUS__SHIFT
102461. BIF_CFG_DEV0_EPF0_VF21_STATUS__MASTER_DATA_PARITY_ERROR_MASK
102462. BIF_CFG_DEV0_EPF0_VF21_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
102463. BIF_CFG_DEV0_EPF0_VF21_STATUS__PARITY_ERROR_DETECTED_MASK
102464. BIF_CFG_DEV0_EPF0_VF21_STATUS__PARITY_ERROR_DETECTED__SHIFT
102465. BIF_CFG_DEV0_EPF0_VF21_STATUS__PCI_66_CAP_MASK
102466. BIF_CFG_DEV0_EPF0_VF21_STATUS__PCI_66_CAP__SHIFT
102467. BIF_CFG_DEV0_EPF0_VF21_STATUS__RECEIVED_MASTER_ABORT_MASK
102468. BIF_CFG_DEV0_EPF0_VF21_STATUS__RECEIVED_MASTER_ABORT__SHIFT
102469. BIF_CFG_DEV0_EPF0_VF21_STATUS__RECEIVED_TARGET_ABORT_MASK
102470. BIF_CFG_DEV0_EPF0_VF21_STATUS__RECEIVED_TARGET_ABORT__SHIFT
102471. BIF_CFG_DEV0_EPF0_VF21_STATUS__SIGNALED_SYSTEM_ERROR_MASK
102472. BIF_CFG_DEV0_EPF0_VF21_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
102473. BIF_CFG_DEV0_EPF0_VF21_STATUS__SIGNAL_TARGET_ABORT_MASK
102474. BIF_CFG_DEV0_EPF0_VF21_STATUS__SIGNAL_TARGET_ABORT__SHIFT
102475. BIF_CFG_DEV0_EPF0_VF21_SUB_CLASS__SUB_CLASS_MASK
102476. BIF_CFG_DEV0_EPF0_VF21_SUB_CLASS__SUB_CLASS__SHIFT
102477. BIF_CFG_DEV0_EPF0_VF21_VENDOR_ID__VENDOR_ID_MASK
102478. BIF_CFG_DEV0_EPF0_VF21_VENDOR_ID__VENDOR_ID__SHIFT
102479. BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
102480. BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
102481. BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
102482. BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
102483. BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1__BASE_ADDR_MASK
102484. BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1__BASE_ADDR__SHIFT
102485. BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2__BASE_ADDR_MASK
102486. BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2__BASE_ADDR__SHIFT
102487. BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3__BASE_ADDR_MASK
102488. BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3__BASE_ADDR__SHIFT
102489. BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4__BASE_ADDR_MASK
102490. BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4__BASE_ADDR__SHIFT
102491. BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5__BASE_ADDR_MASK
102492. BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5__BASE_ADDR__SHIFT
102493. BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6__BASE_ADDR_MASK
102494. BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6__BASE_ADDR__SHIFT
102495. BIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS__BASE_CLASS_MASK
102496. BIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS__BASE_CLASS__SHIFT
102497. BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_CAP_MASK
102498. BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_CAP__SHIFT
102499. BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_COMP_MASK
102500. BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_COMP__SHIFT
102501. BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_STRT_MASK
102502. BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_STRT__SHIFT
102503. BIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
102504. BIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
102505. BIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR__CAP_PTR_MASK
102506. BIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR__CAP_PTR__SHIFT
102507. BIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
102508. BIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
102509. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__AD_STEPPING_MASK
102510. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__AD_STEPPING__SHIFT
102511. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__BUS_MASTER_EN_MASK
102512. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__BUS_MASTER_EN__SHIFT
102513. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__FAST_B2B_EN_MASK
102514. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__FAST_B2B_EN__SHIFT
102515. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__INT_DIS_MASK
102516. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__INT_DIS__SHIFT
102517. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__IO_ACCESS_EN_MASK
102518. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__IO_ACCESS_EN__SHIFT
102519. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__MEM_ACCESS_EN_MASK
102520. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__MEM_ACCESS_EN__SHIFT
102521. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
102522. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
102523. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__PAL_SNOOP_EN_MASK
102524. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__PAL_SNOOP_EN__SHIFT
102525. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
102526. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
102527. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__SERR_EN_MASK
102528. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__SERR_EN__SHIFT
102529. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__SPECIAL_CYCLE_EN_MASK
102530. BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
102531. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
102532. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
102533. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
102534. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
102535. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
102536. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
102537. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
102538. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
102539. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
102540. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
102541. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
102542. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
102543. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
102544. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
102545. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
102546. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
102547. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
102548. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
102549. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
102550. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
102551. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
102552. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
102553. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
102554. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
102555. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
102556. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
102557. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
102558. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
102559. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
102560. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
102561. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
102562. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
102563. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
102564. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
102565. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
102566. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
102567. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
102568. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
102569. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
102570. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
102571. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
102572. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
102573. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
102574. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
102575. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__EXTENDED_TAG_MASK
102576. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
102577. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__FLR_CAPABLE_MASK
102578. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
102579. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
102580. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
102581. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
102582. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
102583. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
102584. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
102585. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__PHANTOM_FUNC_MASK
102586. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
102587. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
102588. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
102589. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
102590. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
102591. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
102592. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
102593. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
102594. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
102595. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
102596. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
102597. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
102598. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
102599. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
102600. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
102601. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
102602. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
102603. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
102604. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
102605. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
102606. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
102607. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__LTR_EN_MASK
102608. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__LTR_EN__SHIFT
102609. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__OBFF_EN_MASK
102610. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__OBFF_EN__SHIFT
102611. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
102612. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
102613. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
102614. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
102615. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__CORR_ERR_EN_MASK
102616. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
102617. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
102618. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
102619. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
102620. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
102621. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__INITIATE_FLR_MASK
102622. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
102623. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
102624. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
102625. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
102626. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
102627. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
102628. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
102629. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
102630. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
102631. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
102632. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
102633. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
102634. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
102635. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__USR_REPORT_EN_MASK
102636. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
102637. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID__DEVICE_ID_MASK
102638. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID__DEVICE_ID__SHIFT
102639. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2__RESERVED_MASK
102640. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2__RESERVED__SHIFT
102641. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__AUX_PWR_MASK
102642. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__AUX_PWR__SHIFT
102643. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__CORR_ERR_MASK
102644. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__CORR_ERR__SHIFT
102645. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
102646. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
102647. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__FATAL_ERR_MASK
102648. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__FATAL_ERR__SHIFT
102649. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
102650. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
102651. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
102652. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
102653. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__USR_DETECTED_MASK
102654. BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__USR_DETECTED__SHIFT
102655. BIF_CFG_DEV0_EPF0_VF22_0_HEADER__DEVICE_TYPE_MASK
102656. BIF_CFG_DEV0_EPF0_VF22_0_HEADER__DEVICE_TYPE__SHIFT
102657. BIF_CFG_DEV0_EPF0_VF22_0_HEADER__HEADER_TYPE_MASK
102658. BIF_CFG_DEV0_EPF0_VF22_0_HEADER__HEADER_TYPE__SHIFT
102659. BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
102660. BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
102661. BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
102662. BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
102663. BIF_CFG_DEV0_EPF0_VF22_0_LATENCY__LATENCY_TIMER_MASK
102664. BIF_CFG_DEV0_EPF0_VF22_0_LATENCY__LATENCY_TIMER__SHIFT
102665. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
102666. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
102667. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
102668. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
102669. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
102670. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
102671. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
102672. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
102673. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
102674. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
102675. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
102676. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
102677. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
102678. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
102679. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
102680. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
102681. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
102682. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
102683. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
102684. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
102685. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
102686. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
102687. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__L1_EXIT_LATENCY_MASK
102688. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
102689. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
102690. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
102691. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_SPEED_MASK
102692. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_SPEED__SHIFT
102693. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_WIDTH_MASK
102694. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_WIDTH__SHIFT
102695. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__PM_SUPPORT_MASK
102696. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__PM_SUPPORT__SHIFT
102697. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__PORT_NUMBER_MASK
102698. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__PORT_NUMBER__SHIFT
102699. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
102700. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
102701. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
102702. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
102703. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
102704. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
102705. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
102706. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
102707. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
102708. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
102709. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
102710. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
102711. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
102712. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
102713. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
102714. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
102715. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__XMIT_MARGIN_MASK
102716. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
102717. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
102718. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
102719. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
102720. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
102721. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
102722. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
102723. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__EXTENDED_SYNC_MASK
102724. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
102725. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
102726. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
102727. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
102728. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
102729. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
102730. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
102731. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_DIS_MASK
102732. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_DIS__SHIFT
102733. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__PM_CONTROL_MASK
102734. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__PM_CONTROL__SHIFT
102735. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
102736. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
102737. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__RETRAIN_LINK_MASK
102738. BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__RETRAIN_LINK__SHIFT
102739. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
102740. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
102741. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
102742. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
102743. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
102744. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
102745. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
102746. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
102747. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
102748. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
102749. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
102750. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
102751. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
102752. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
102753. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
102754. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
102755. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
102756. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
102757. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
102758. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
102759. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
102760. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
102761. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
102762. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
102763. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__DL_ACTIVE_MASK
102764. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__DL_ACTIVE__SHIFT
102765. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
102766. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
102767. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
102768. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
102769. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_TRAINING_MASK
102770. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_TRAINING__SHIFT
102771. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
102772. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
102773. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
102774. BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
102775. BIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY__MAX_LAT_MASK
102776. BIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY__MAX_LAT__SHIFT
102777. BIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT__MIN_GNT_MASK
102778. BIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT__MIN_GNT__SHIFT
102779. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST__CAP_ID_MASK
102780. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST__CAP_ID__SHIFT
102781. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST__NEXT_PTR_MASK
102782. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
102783. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_EN_MASK
102784. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
102785. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
102786. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
102787. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
102788. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
102789. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA__MSIX_PBA_BIR_MASK
102790. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
102791. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
102792. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
102793. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
102794. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
102795. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
102796. BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
102797. BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST__CAP_ID_MASK
102798. BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST__CAP_ID__SHIFT
102799. BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST__NEXT_PTR_MASK
102800. BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
102801. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64__MSI_MASK_64_MASK
102802. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64__MSI_MASK_64__SHIFT
102803. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK__MSI_MASK_MASK
102804. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK__MSI_MASK__SHIFT
102805. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
102806. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
102807. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
102808. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
102809. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_64BIT_MASK
102810. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
102811. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_EN_MASK
102812. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_EN__SHIFT
102813. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
102814. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
102815. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
102816. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
102817. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
102818. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
102819. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
102820. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
102821. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA__MSI_DATA_MASK
102822. BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA__MSI_DATA__SHIFT
102823. BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64__MSI_PENDING_64_MASK
102824. BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
102825. BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING__MSI_PENDING_MASK
102826. BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING__MSI_PENDING__SHIFT
102827. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
102828. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
102829. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
102830. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
102831. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
102832. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
102833. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
102834. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
102835. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
102836. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
102837. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
102838. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
102839. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
102840. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
102841. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
102842. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
102843. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
102844. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
102845. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
102846. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
102847. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
102848. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
102849. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
102850. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
102851. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
102852. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
102853. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
102854. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
102855. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
102856. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
102857. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
102858. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
102859. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
102860. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
102861. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
102862. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
102863. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
102864. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
102865. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
102866. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
102867. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
102868. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
102869. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
102870. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
102871. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
102872. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
102873. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
102874. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
102875. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
102876. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
102877. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL__STU_MASK
102878. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL__STU__SHIFT
102879. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
102880. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
102881. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
102882. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
102883. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
102884. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
102885. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST__CAP_ID_MASK
102886. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST__CAP_ID__SHIFT
102887. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST__NEXT_PTR_MASK
102888. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
102889. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__DEVICE_TYPE_MASK
102890. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__DEVICE_TYPE__SHIFT
102891. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
102892. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
102893. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
102894. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
102895. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__VERSION_MASK
102896. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__VERSION__SHIFT
102897. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
102898. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
102899. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
102900. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
102901. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
102902. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
102903. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
102904. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
102905. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
102906. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
102907. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
102908. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
102909. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
102910. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
102911. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
102912. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
102913. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
102914. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
102915. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
102916. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
102917. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
102918. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
102919. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
102920. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
102921. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
102922. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
102923. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
102924. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
102925. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
102926. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
102927. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
102928. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
102929. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0__TLP_HDR_MASK
102930. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
102931. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1__TLP_HDR_MASK
102932. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
102933. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2__TLP_HDR_MASK
102934. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
102935. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3__TLP_HDR_MASK
102936. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
102937. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
102938. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
102939. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
102940. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
102941. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
102942. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
102943. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
102944. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
102945. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
102946. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
102947. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
102948. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
102949. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
102950. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
102951. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
102952. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
102953. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
102954. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
102955. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
102956. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
102957. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
102958. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
102959. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
102960. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
102961. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
102962. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
102963. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
102964. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
102965. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
102966. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
102967. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
102968. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
102969. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
102970. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
102971. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
102972. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
102973. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
102974. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
102975. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
102976. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
102977. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
102978. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
102979. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
102980. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
102981. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
102982. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
102983. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
102984. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
102985. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
102986. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
102987. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
102988. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
102989. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
102990. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
102991. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
102992. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
102993. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
102994. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
102995. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
102996. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
102997. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
102998. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
102999. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
103000. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
103001. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
103002. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
103003. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
103004. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
103005. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
103006. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
103007. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
103008. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
103009. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
103010. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
103011. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
103012. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
103013. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
103014. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
103015. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
103016. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
103017. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
103018. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
103019. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
103020. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
103021. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
103022. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
103023. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
103024. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
103025. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
103026. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
103027. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
103028. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
103029. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
103030. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
103031. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
103032. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
103033. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
103034. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
103035. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
103036. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
103037. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
103038. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
103039. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
103040. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
103041. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
103042. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
103043. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
103044. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
103045. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
103046. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
103047. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
103048. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
103049. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
103050. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
103051. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
103052. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
103053. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
103054. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
103055. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
103056. BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
103057. BIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE__PROG_INTERFACE_MASK
103058. BIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
103059. BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID__MAJOR_REV_ID_MASK
103060. BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID__MAJOR_REV_ID__SHIFT
103061. BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID__MINOR_REV_ID_MASK
103062. BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID__MINOR_REV_ID__SHIFT
103063. BIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR__BASE_ADDR_MASK
103064. BIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
103065. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__CAP_LIST_MASK
103066. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__CAP_LIST__SHIFT
103067. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__DEVSEL_TIMING_MASK
103068. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__DEVSEL_TIMING__SHIFT
103069. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__FAST_BACK_CAPABLE_MASK
103070. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__FAST_BACK_CAPABLE__SHIFT
103071. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__IMMEDIATE_READINESS_MASK
103072. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__IMMEDIATE_READINESS__SHIFT
103073. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__INT_STATUS_MASK
103074. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__INT_STATUS__SHIFT
103075. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
103076. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
103077. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__PARITY_ERROR_DETECTED_MASK
103078. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
103079. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__PCI_66_CAP_MASK
103080. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__PCI_66_CAP__SHIFT
103081. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__RECEIVED_MASTER_ABORT_MASK
103082. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
103083. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__RECEIVED_TARGET_ABORT_MASK
103084. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
103085. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
103086. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
103087. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__SIGNAL_TARGET_ABORT_MASK
103088. BIF_CFG_DEV0_EPF0_VF22_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
103089. BIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS__SUB_CLASS_MASK
103090. BIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS__SUB_CLASS__SHIFT
103091. BIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID__VENDOR_ID_MASK
103092. BIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID__VENDOR_ID__SHIFT
103093. BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
103094. BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
103095. BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
103096. BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
103097. BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1__BASE_ADDR_MASK
103098. BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1__BASE_ADDR__SHIFT
103099. BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2__BASE_ADDR_MASK
103100. BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2__BASE_ADDR__SHIFT
103101. BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3__BASE_ADDR_MASK
103102. BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3__BASE_ADDR__SHIFT
103103. BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4__BASE_ADDR_MASK
103104. BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4__BASE_ADDR__SHIFT
103105. BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5__BASE_ADDR_MASK
103106. BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5__BASE_ADDR__SHIFT
103107. BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6__BASE_ADDR_MASK
103108. BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6__BASE_ADDR__SHIFT
103109. BIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS__BASE_CLASS_MASK
103110. BIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS__BASE_CLASS__SHIFT
103111. BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_CAP_MASK
103112. BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_CAP__SHIFT
103113. BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_COMP_MASK
103114. BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_COMP__SHIFT
103115. BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_STRT_MASK
103116. BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_STRT__SHIFT
103117. BIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
103118. BIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
103119. BIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR__CAP_PTR_MASK
103120. BIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR__CAP_PTR__SHIFT
103121. BIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
103122. BIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
103123. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__AD_STEPPING_MASK
103124. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__AD_STEPPING__SHIFT
103125. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__BUS_MASTER_EN_MASK
103126. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__BUS_MASTER_EN__SHIFT
103127. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__FAST_B2B_EN_MASK
103128. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__FAST_B2B_EN__SHIFT
103129. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__INT_DIS_MASK
103130. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__INT_DIS__SHIFT
103131. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__IO_ACCESS_EN_MASK
103132. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__IO_ACCESS_EN__SHIFT
103133. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__MEM_ACCESS_EN_MASK
103134. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__MEM_ACCESS_EN__SHIFT
103135. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
103136. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
103137. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__PAL_SNOOP_EN_MASK
103138. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__PAL_SNOOP_EN__SHIFT
103139. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
103140. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
103141. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__SERR_EN_MASK
103142. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__SERR_EN__SHIFT
103143. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__SPECIAL_CYCLE_EN_MASK
103144. BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
103145. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
103146. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
103147. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
103148. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
103149. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
103150. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
103151. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
103152. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
103153. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
103154. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
103155. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
103156. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
103157. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
103158. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
103159. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
103160. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
103161. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
103162. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
103163. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
103164. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
103165. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
103166. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
103167. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
103168. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
103169. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
103170. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
103171. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
103172. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
103173. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
103174. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
103175. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
103176. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
103177. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
103178. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
103179. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
103180. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
103181. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
103182. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
103183. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
103184. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
103185. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
103186. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
103187. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
103188. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
103189. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__EXTENDED_TAG_MASK
103190. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
103191. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__FLR_CAPABLE_MASK
103192. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
103193. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
103194. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
103195. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
103196. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
103197. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
103198. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
103199. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__PHANTOM_FUNC_MASK
103200. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
103201. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
103202. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
103203. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
103204. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
103205. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
103206. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
103207. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
103208. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
103209. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
103210. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
103211. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
103212. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
103213. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
103214. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
103215. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
103216. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
103217. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
103218. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
103219. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
103220. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
103221. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__LTR_EN_MASK
103222. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__LTR_EN__SHIFT
103223. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__OBFF_EN_MASK
103224. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__OBFF_EN__SHIFT
103225. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
103226. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
103227. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
103228. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
103229. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__CORR_ERR_EN_MASK
103230. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
103231. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
103232. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
103233. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
103234. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
103235. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__INITIATE_FLR_MASK
103236. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
103237. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
103238. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
103239. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
103240. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
103241. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
103242. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
103243. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
103244. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
103245. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
103246. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
103247. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
103248. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
103249. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__USR_REPORT_EN_MASK
103250. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
103251. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID__DEVICE_ID_MASK
103252. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID__DEVICE_ID__SHIFT
103253. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2__RESERVED_MASK
103254. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2__RESERVED__SHIFT
103255. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__AUX_PWR_MASK
103256. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__AUX_PWR__SHIFT
103257. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__CORR_ERR_MASK
103258. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__CORR_ERR__SHIFT
103259. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
103260. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
103261. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__FATAL_ERR_MASK
103262. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__FATAL_ERR__SHIFT
103263. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
103264. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
103265. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
103266. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
103267. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__USR_DETECTED_MASK
103268. BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__USR_DETECTED__SHIFT
103269. BIF_CFG_DEV0_EPF0_VF22_1_HEADER__DEVICE_TYPE_MASK
103270. BIF_CFG_DEV0_EPF0_VF22_1_HEADER__DEVICE_TYPE__SHIFT
103271. BIF_CFG_DEV0_EPF0_VF22_1_HEADER__HEADER_TYPE_MASK
103272. BIF_CFG_DEV0_EPF0_VF22_1_HEADER__HEADER_TYPE__SHIFT
103273. BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
103274. BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
103275. BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
103276. BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
103277. BIF_CFG_DEV0_EPF0_VF22_1_LATENCY__LATENCY_TIMER_MASK
103278. BIF_CFG_DEV0_EPF0_VF22_1_LATENCY__LATENCY_TIMER__SHIFT
103279. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
103280. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
103281. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
103282. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
103283. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
103284. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
103285. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
103286. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
103287. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
103288. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
103289. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
103290. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
103291. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
103292. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
103293. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
103294. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
103295. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
103296. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
103297. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
103298. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
103299. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
103300. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
103301. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__L1_EXIT_LATENCY_MASK
103302. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
103303. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
103304. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
103305. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_SPEED_MASK
103306. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_SPEED__SHIFT
103307. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_WIDTH_MASK
103308. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_WIDTH__SHIFT
103309. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__PM_SUPPORT_MASK
103310. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__PM_SUPPORT__SHIFT
103311. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__PORT_NUMBER_MASK
103312. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__PORT_NUMBER__SHIFT
103313. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
103314. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
103315. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
103316. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
103317. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
103318. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
103319. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
103320. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
103321. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
103322. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
103323. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
103324. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
103325. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
103326. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
103327. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
103328. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
103329. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__XMIT_MARGIN_MASK
103330. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
103331. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
103332. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
103333. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
103334. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
103335. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
103336. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
103337. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__EXTENDED_SYNC_MASK
103338. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
103339. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
103340. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
103341. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
103342. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
103343. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
103344. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
103345. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_DIS_MASK
103346. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_DIS__SHIFT
103347. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__PM_CONTROL_MASK
103348. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__PM_CONTROL__SHIFT
103349. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
103350. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
103351. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__RETRAIN_LINK_MASK
103352. BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__RETRAIN_LINK__SHIFT
103353. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
103354. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
103355. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
103356. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
103357. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
103358. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
103359. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
103360. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
103361. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
103362. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
103363. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
103364. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
103365. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
103366. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
103367. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
103368. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
103369. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
103370. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
103371. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
103372. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
103373. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
103374. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
103375. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
103376. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
103377. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__DL_ACTIVE_MASK
103378. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__DL_ACTIVE__SHIFT
103379. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
103380. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
103381. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
103382. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
103383. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_TRAINING_MASK
103384. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_TRAINING__SHIFT
103385. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
103386. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
103387. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
103388. BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
103389. BIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY__MAX_LAT_MASK
103390. BIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY__MAX_LAT__SHIFT
103391. BIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT__MIN_GNT_MASK
103392. BIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT__MIN_GNT__SHIFT
103393. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST__CAP_ID_MASK
103394. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST__CAP_ID__SHIFT
103395. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST__NEXT_PTR_MASK
103396. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
103397. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_EN_MASK
103398. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
103399. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
103400. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
103401. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
103402. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
103403. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA__MSIX_PBA_BIR_MASK
103404. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
103405. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
103406. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
103407. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
103408. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
103409. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
103410. BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
103411. BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST__CAP_ID_MASK
103412. BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST__CAP_ID__SHIFT
103413. BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST__NEXT_PTR_MASK
103414. BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
103415. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64__MSI_MASK_64_MASK
103416. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64__MSI_MASK_64__SHIFT
103417. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK__MSI_MASK_MASK
103418. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK__MSI_MASK__SHIFT
103419. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
103420. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
103421. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
103422. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
103423. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_64BIT_MASK
103424. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
103425. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_EN_MASK
103426. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_EN__SHIFT
103427. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
103428. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
103429. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
103430. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
103431. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
103432. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
103433. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
103434. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
103435. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA__MSI_DATA_MASK
103436. BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA__MSI_DATA__SHIFT
103437. BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64__MSI_PENDING_64_MASK
103438. BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
103439. BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING__MSI_PENDING_MASK
103440. BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING__MSI_PENDING__SHIFT
103441. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
103442. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
103443. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
103444. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
103445. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
103446. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
103447. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
103448. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
103449. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
103450. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
103451. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
103452. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
103453. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
103454. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
103455. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
103456. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
103457. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
103458. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
103459. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
103460. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
103461. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
103462. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
103463. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
103464. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
103465. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
103466. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
103467. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
103468. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
103469. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
103470. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
103471. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
103472. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
103473. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
103474. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
103475. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
103476. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
103477. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
103478. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
103479. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
103480. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
103481. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
103482. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
103483. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
103484. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
103485. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
103486. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
103487. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
103488. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
103489. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
103490. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
103491. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL__STU_MASK
103492. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL__STU__SHIFT
103493. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
103494. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
103495. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
103496. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
103497. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
103498. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
103499. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST__CAP_ID_MASK
103500. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST__CAP_ID__SHIFT
103501. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST__NEXT_PTR_MASK
103502. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
103503. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__DEVICE_TYPE_MASK
103504. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__DEVICE_TYPE__SHIFT
103505. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
103506. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
103507. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
103508. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
103509. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__VERSION_MASK
103510. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__VERSION__SHIFT
103511. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
103512. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
103513. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
103514. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
103515. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
103516. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
103517. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
103518. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
103519. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
103520. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
103521. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
103522. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
103523. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
103524. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
103525. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
103526. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
103527. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
103528. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
103529. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
103530. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
103531. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
103532. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
103533. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
103534. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
103535. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
103536. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
103537. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
103538. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
103539. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
103540. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
103541. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
103542. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
103543. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0__TLP_HDR_MASK
103544. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
103545. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1__TLP_HDR_MASK
103546. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
103547. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2__TLP_HDR_MASK
103548. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
103549. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3__TLP_HDR_MASK
103550. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
103551. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
103552. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
103553. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
103554. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
103555. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
103556. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
103557. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
103558. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
103559. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
103560. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
103561. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
103562. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
103563. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
103564. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
103565. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
103566. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
103567. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
103568. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
103569. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
103570. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
103571. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
103572. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
103573. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
103574. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
103575. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
103576. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
103577. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
103578. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
103579. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
103580. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
103581. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
103582. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
103583. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
103584. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
103585. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
103586. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
103587. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
103588. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
103589. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
103590. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
103591. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
103592. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
103593. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
103594. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
103595. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
103596. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
103597. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
103598. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
103599. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
103600. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
103601. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
103602. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
103603. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
103604. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
103605. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
103606. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
103607. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
103608. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
103609. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
103610. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
103611. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
103612. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
103613. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
103614. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
103615. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
103616. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
103617. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
103618. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
103619. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
103620. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
103621. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
103622. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
103623. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
103624. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
103625. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
103626. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
103627. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
103628. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
103629. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
103630. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
103631. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
103632. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
103633. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
103634. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
103635. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
103636. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
103637. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
103638. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
103639. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
103640. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
103641. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
103642. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
103643. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
103644. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
103645. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
103646. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
103647. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
103648. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
103649. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
103650. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
103651. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
103652. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
103653. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
103654. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
103655. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
103656. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
103657. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
103658. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
103659. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
103660. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
103661. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
103662. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
103663. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
103664. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
103665. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
103666. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
103667. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
103668. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
103669. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
103670. BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
103671. BIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE__PROG_INTERFACE_MASK
103672. BIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
103673. BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID__MAJOR_REV_ID_MASK
103674. BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID__MAJOR_REV_ID__SHIFT
103675. BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID__MINOR_REV_ID_MASK
103676. BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID__MINOR_REV_ID__SHIFT
103677. BIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR__BASE_ADDR_MASK
103678. BIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
103679. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__CAP_LIST_MASK
103680. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__CAP_LIST__SHIFT
103681. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__DEVSEL_TIMING_MASK
103682. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__DEVSEL_TIMING__SHIFT
103683. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__FAST_BACK_CAPABLE_MASK
103684. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__FAST_BACK_CAPABLE__SHIFT
103685. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__IMMEDIATE_READINESS_MASK
103686. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__IMMEDIATE_READINESS__SHIFT
103687. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__INT_STATUS_MASK
103688. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__INT_STATUS__SHIFT
103689. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
103690. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
103691. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__PARITY_ERROR_DETECTED_MASK
103692. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
103693. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__PCI_66_CAP_MASK
103694. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__PCI_66_CAP__SHIFT
103695. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__RECEIVED_MASTER_ABORT_MASK
103696. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
103697. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__RECEIVED_TARGET_ABORT_MASK
103698. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
103699. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
103700. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
103701. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__SIGNAL_TARGET_ABORT_MASK
103702. BIF_CFG_DEV0_EPF0_VF22_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
103703. BIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS__SUB_CLASS_MASK
103704. BIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS__SUB_CLASS__SHIFT
103705. BIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID__VENDOR_ID_MASK
103706. BIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID__VENDOR_ID__SHIFT
103707. BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID__SUBSYSTEM_ID_MASK
103708. BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
103709. BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
103710. BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
103711. BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_1__BASE_ADDR_MASK
103712. BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_1__BASE_ADDR__SHIFT
103713. BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_2__BASE_ADDR_MASK
103714. BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_2__BASE_ADDR__SHIFT
103715. BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_3__BASE_ADDR_MASK
103716. BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_3__BASE_ADDR__SHIFT
103717. BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_4__BASE_ADDR_MASK
103718. BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_4__BASE_ADDR__SHIFT
103719. BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_5__BASE_ADDR_MASK
103720. BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_5__BASE_ADDR__SHIFT
103721. BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_6__BASE_ADDR_MASK
103722. BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_6__BASE_ADDR__SHIFT
103723. BIF_CFG_DEV0_EPF0_VF22_BASE_CLASS__BASE_CLASS_MASK
103724. BIF_CFG_DEV0_EPF0_VF22_BASE_CLASS__BASE_CLASS__SHIFT
103725. BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_CAP_MASK
103726. BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_CAP__SHIFT
103727. BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_COMP_MASK
103728. BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_COMP__SHIFT
103729. BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_STRT_MASK
103730. BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_STRT__SHIFT
103731. BIF_CFG_DEV0_EPF0_VF22_CACHE_LINE__CACHE_LINE_SIZE_MASK
103732. BIF_CFG_DEV0_EPF0_VF22_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
103733. BIF_CFG_DEV0_EPF0_VF22_CAP_PTR__CAP_PTR_MASK
103734. BIF_CFG_DEV0_EPF0_VF22_CAP_PTR__CAP_PTR__SHIFT
103735. BIF_CFG_DEV0_EPF0_VF22_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
103736. BIF_CFG_DEV0_EPF0_VF22_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
103737. BIF_CFG_DEV0_EPF0_VF22_COMMAND__AD_STEPPING_MASK
103738. BIF_CFG_DEV0_EPF0_VF22_COMMAND__AD_STEPPING__SHIFT
103739. BIF_CFG_DEV0_EPF0_VF22_COMMAND__BUS_MASTER_EN_MASK
103740. BIF_CFG_DEV0_EPF0_VF22_COMMAND__BUS_MASTER_EN__SHIFT
103741. BIF_CFG_DEV0_EPF0_VF22_COMMAND__FAST_B2B_EN_MASK
103742. BIF_CFG_DEV0_EPF0_VF22_COMMAND__FAST_B2B_EN__SHIFT
103743. BIF_CFG_DEV0_EPF0_VF22_COMMAND__INT_DIS_MASK
103744. BIF_CFG_DEV0_EPF0_VF22_COMMAND__INT_DIS__SHIFT
103745. BIF_CFG_DEV0_EPF0_VF22_COMMAND__IO_ACCESS_EN_MASK
103746. BIF_CFG_DEV0_EPF0_VF22_COMMAND__IO_ACCESS_EN__SHIFT
103747. BIF_CFG_DEV0_EPF0_VF22_COMMAND__MEM_ACCESS_EN_MASK
103748. BIF_CFG_DEV0_EPF0_VF22_COMMAND__MEM_ACCESS_EN__SHIFT
103749. BIF_CFG_DEV0_EPF0_VF22_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
103750. BIF_CFG_DEV0_EPF0_VF22_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
103751. BIF_CFG_DEV0_EPF0_VF22_COMMAND__PAL_SNOOP_EN_MASK
103752. BIF_CFG_DEV0_EPF0_VF22_COMMAND__PAL_SNOOP_EN__SHIFT
103753. BIF_CFG_DEV0_EPF0_VF22_COMMAND__PARITY_ERROR_RESPONSE_MASK
103754. BIF_CFG_DEV0_EPF0_VF22_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
103755. BIF_CFG_DEV0_EPF0_VF22_COMMAND__SERR_EN_MASK
103756. BIF_CFG_DEV0_EPF0_VF22_COMMAND__SERR_EN__SHIFT
103757. BIF_CFG_DEV0_EPF0_VF22_COMMAND__SPECIAL_CYCLE_EN_MASK
103758. BIF_CFG_DEV0_EPF0_VF22_COMMAND__SPECIAL_CYCLE_EN__SHIFT
103759. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
103760. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
103761. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
103762. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
103763. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
103764. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
103765. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
103766. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
103767. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
103768. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
103769. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
103770. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
103771. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
103772. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
103773. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
103774. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
103775. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
103776. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
103777. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
103778. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
103779. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
103780. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
103781. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__FRS_SUPPORTED_MASK
103782. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
103783. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
103784. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
103785. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__LTR_SUPPORTED_MASK
103786. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
103787. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
103788. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
103789. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
103790. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
103791. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__OBFF_SUPPORTED_MASK
103792. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
103793. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
103794. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
103795. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
103796. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
103797. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
103798. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
103799. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
103800. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
103801. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
103802. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
103803. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__EXTENDED_TAG_MASK
103804. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__EXTENDED_TAG__SHIFT
103805. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__FLR_CAPABLE_MASK
103806. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__FLR_CAPABLE__SHIFT
103807. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
103808. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
103809. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
103810. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
103811. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
103812. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
103813. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__PHANTOM_FUNC_MASK
103814. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__PHANTOM_FUNC__SHIFT
103815. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
103816. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
103817. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
103818. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
103819. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
103820. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
103821. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
103822. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
103823. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
103824. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
103825. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
103826. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
103827. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
103828. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
103829. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
103830. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
103831. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
103832. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
103833. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
103834. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
103835. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__LTR_EN_MASK
103836. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__LTR_EN__SHIFT
103837. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__OBFF_EN_MASK
103838. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__OBFF_EN__SHIFT
103839. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
103840. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
103841. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
103842. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
103843. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__CORR_ERR_EN_MASK
103844. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__CORR_ERR_EN__SHIFT
103845. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
103846. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
103847. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__FATAL_ERR_EN_MASK
103848. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
103849. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__INITIATE_FLR_MASK
103850. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__INITIATE_FLR__SHIFT
103851. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
103852. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
103853. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
103854. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
103855. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
103856. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
103857. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__NO_SNOOP_EN_MASK
103858. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
103859. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
103860. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
103861. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__RELAXED_ORD_EN_MASK
103862. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
103863. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__USR_REPORT_EN_MASK
103864. BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__USR_REPORT_EN__SHIFT
103865. BIF_CFG_DEV0_EPF0_VF22_DEVICE_ID__DEVICE_ID_MASK
103866. BIF_CFG_DEV0_EPF0_VF22_DEVICE_ID__DEVICE_ID__SHIFT
103867. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS2__RESERVED_MASK
103868. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS2__RESERVED__SHIFT
103869. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__AUX_PWR_MASK
103870. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__AUX_PWR__SHIFT
103871. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__CORR_ERR_MASK
103872. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__CORR_ERR__SHIFT
103873. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
103874. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
103875. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__FATAL_ERR_MASK
103876. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__FATAL_ERR__SHIFT
103877. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__NON_FATAL_ERR_MASK
103878. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
103879. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
103880. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
103881. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__USR_DETECTED_MASK
103882. BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__USR_DETECTED__SHIFT
103883. BIF_CFG_DEV0_EPF0_VF22_HEADER__DEVICE_TYPE_MASK
103884. BIF_CFG_DEV0_EPF0_VF22_HEADER__DEVICE_TYPE__SHIFT
103885. BIF_CFG_DEV0_EPF0_VF22_HEADER__HEADER_TYPE_MASK
103886. BIF_CFG_DEV0_EPF0_VF22_HEADER__HEADER_TYPE__SHIFT
103887. BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_LINE__INTERRUPT_LINE_MASK
103888. BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
103889. BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_PIN__INTERRUPT_PIN_MASK
103890. BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
103891. BIF_CFG_DEV0_EPF0_VF22_LATENCY__LATENCY_TIMER_MASK
103892. BIF_CFG_DEV0_EPF0_VF22_LATENCY__LATENCY_TIMER__SHIFT
103893. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
103894. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
103895. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
103896. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
103897. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
103898. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
103899. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
103900. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
103901. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
103902. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
103903. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
103904. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
103905. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
103906. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
103907. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
103908. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
103909. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
103910. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
103911. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
103912. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
103913. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__L0S_EXIT_LATENCY_MASK
103914. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
103915. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__L1_EXIT_LATENCY_MASK
103916. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__L1_EXIT_LATENCY__SHIFT
103917. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
103918. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
103919. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_SPEED_MASK
103920. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_SPEED__SHIFT
103921. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_WIDTH_MASK
103922. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_WIDTH__SHIFT
103923. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__PM_SUPPORT_MASK
103924. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__PM_SUPPORT__SHIFT
103925. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__PORT_NUMBER_MASK
103926. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__PORT_NUMBER__SHIFT
103927. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
103928. BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
103929. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
103930. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
103931. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__COMPLIANCE_SOS_MASK
103932. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
103933. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__ENTER_COMPLIANCE_MASK
103934. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
103935. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
103936. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
103937. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
103938. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
103939. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
103940. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
103941. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__TARGET_LINK_SPEED_MASK
103942. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
103943. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__XMIT_MARGIN_MASK
103944. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__XMIT_MARGIN__SHIFT
103945. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
103946. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
103947. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__COMMON_CLOCK_CFG_MASK
103948. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
103949. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
103950. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
103951. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__EXTENDED_SYNC_MASK
103952. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__EXTENDED_SYNC__SHIFT
103953. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
103954. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
103955. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
103956. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
103957. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
103958. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
103959. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_DIS_MASK
103960. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_DIS__SHIFT
103961. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__PM_CONTROL_MASK
103962. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__PM_CONTROL__SHIFT
103963. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__READ_CPL_BOUNDARY_MASK
103964. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
103965. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__RETRAIN_LINK_MASK
103966. BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__RETRAIN_LINK__SHIFT
103967. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
103968. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
103969. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
103970. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
103971. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
103972. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
103973. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
103974. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
103975. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
103976. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
103977. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
103978. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
103979. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
103980. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
103981. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
103982. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
103983. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
103984. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
103985. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
103986. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
103987. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
103988. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
103989. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__CURRENT_LINK_SPEED_MASK
103990. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
103991. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__DL_ACTIVE_MASK
103992. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__DL_ACTIVE__SHIFT
103993. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
103994. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
103995. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
103996. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
103997. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_TRAINING_MASK
103998. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_TRAINING__SHIFT
103999. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
104000. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
104001. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__SLOT_CLOCK_CFG_MASK
104002. BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
104003. BIF_CFG_DEV0_EPF0_VF22_MAX_LATENCY__MAX_LAT_MASK
104004. BIF_CFG_DEV0_EPF0_VF22_MAX_LATENCY__MAX_LAT__SHIFT
104005. BIF_CFG_DEV0_EPF0_VF22_MIN_GRANT__MIN_GNT_MASK
104006. BIF_CFG_DEV0_EPF0_VF22_MIN_GRANT__MIN_GNT__SHIFT
104007. BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST__CAP_ID_MASK
104008. BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST__CAP_ID__SHIFT
104009. BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST__NEXT_PTR_MASK
104010. BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST__NEXT_PTR__SHIFT
104011. BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_EN_MASK
104012. BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_EN__SHIFT
104013. BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
104014. BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
104015. BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
104016. BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
104017. BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA__MSIX_PBA_BIR_MASK
104018. BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA__MSIX_PBA_BIR__SHIFT
104019. BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA__MSIX_PBA_OFFSET_MASK
104020. BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
104021. BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE__MSIX_TABLE_BIR_MASK
104022. BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
104023. BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
104024. BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
104025. BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST__CAP_ID_MASK
104026. BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST__CAP_ID__SHIFT
104027. BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST__NEXT_PTR_MASK
104028. BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST__NEXT_PTR__SHIFT
104029. BIF_CFG_DEV0_EPF0_VF22_MSI_MASK_64__MSI_MASK_64_MASK
104030. BIF_CFG_DEV0_EPF0_VF22_MSI_MASK_64__MSI_MASK_64__SHIFT
104031. BIF_CFG_DEV0_EPF0_VF22_MSI_MASK__MSI_MASK_MASK
104032. BIF_CFG_DEV0_EPF0_VF22_MSI_MASK__MSI_MASK__SHIFT
104033. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
104034. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
104035. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
104036. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
104037. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_64BIT_MASK
104038. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_64BIT__SHIFT
104039. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_EN_MASK
104040. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_EN__SHIFT
104041. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
104042. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
104043. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
104044. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
104045. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
104046. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
104047. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA_64__MSI_DATA_64_MASK
104048. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
104049. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA__MSI_DATA_MASK
104050. BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA__MSI_DATA__SHIFT
104051. BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING_64__MSI_PENDING_64_MASK
104052. BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING_64__MSI_PENDING_64__SHIFT
104053. BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING__MSI_PENDING_MASK
104054. BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING__MSI_PENDING__SHIFT
104055. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
104056. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
104057. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
104058. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
104059. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
104060. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
104061. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
104062. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
104063. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
104064. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
104065. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
104066. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
104067. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
104068. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
104069. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
104070. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
104071. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
104072. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
104073. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
104074. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
104075. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
104076. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
104077. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
104078. BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
104079. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
104080. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
104081. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
104082. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
104083. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
104084. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
104085. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
104086. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
104087. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
104088. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
104089. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
104090. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
104091. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
104092. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
104093. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
104094. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
104095. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
104096. BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
104097. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
104098. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
104099. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
104100. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
104101. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
104102. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
104103. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL__ATC_ENABLE_MASK
104104. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
104105. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL__STU_MASK
104106. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL__STU__SHIFT
104107. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
104108. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
104109. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
104110. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
104111. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
104112. BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
104113. BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST__CAP_ID_MASK
104114. BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST__CAP_ID__SHIFT
104115. BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST__NEXT_PTR_MASK
104116. BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST__NEXT_PTR__SHIFT
104117. BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__DEVICE_TYPE_MASK
104118. BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__DEVICE_TYPE__SHIFT
104119. BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__INT_MESSAGE_NUM_MASK
104120. BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
104121. BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__SLOT_IMPLEMENTED_MASK
104122. BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
104123. BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__VERSION_MASK
104124. BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__VERSION__SHIFT
104125. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
104126. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
104127. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
104128. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
104129. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
104130. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
104131. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
104132. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
104133. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
104134. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
104135. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
104136. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
104137. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
104138. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
104139. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
104140. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
104141. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
104142. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
104143. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
104144. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
104145. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
104146. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
104147. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
104148. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
104149. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
104150. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
104151. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
104152. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
104153. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
104154. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
104155. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
104156. BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
104157. BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG0__TLP_HDR_MASK
104158. BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG0__TLP_HDR__SHIFT
104159. BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG1__TLP_HDR_MASK
104160. BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG1__TLP_HDR__SHIFT
104161. BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG2__TLP_HDR_MASK
104162. BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG2__TLP_HDR__SHIFT
104163. BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG3__TLP_HDR_MASK
104164. BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG3__TLP_HDR__SHIFT
104165. BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
104166. BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
104167. BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
104168. BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
104169. BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
104170. BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
104171. BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
104172. BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
104173. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
104174. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
104175. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
104176. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
104177. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
104178. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
104179. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
104180. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
104181. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
104182. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
104183. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
104184. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
104185. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
104186. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
104187. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
104188. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
104189. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
104190. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
104191. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
104192. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
104193. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
104194. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
104195. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
104196. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
104197. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
104198. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
104199. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
104200. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
104201. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
104202. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
104203. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
104204. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
104205. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
104206. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
104207. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
104208. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
104209. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
104210. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
104211. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
104212. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
104213. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
104214. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
104215. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
104216. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
104217. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
104218. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
104219. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
104220. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
104221. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
104222. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
104223. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
104224. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
104225. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
104226. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
104227. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
104228. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
104229. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
104230. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
104231. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
104232. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
104233. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
104234. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
104235. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
104236. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
104237. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
104238. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
104239. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
104240. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
104241. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
104242. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
104243. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
104244. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
104245. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
104246. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
104247. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
104248. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
104249. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
104250. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
104251. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
104252. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
104253. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
104254. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
104255. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
104256. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
104257. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
104258. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
104259. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
104260. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
104261. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
104262. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
104263. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
104264. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
104265. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
104266. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
104267. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
104268. BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
104269. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
104270. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
104271. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
104272. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
104273. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
104274. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
104275. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
104276. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
104277. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
104278. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
104279. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
104280. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
104281. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
104282. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
104283. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
104284. BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
104285. BIF_CFG_DEV0_EPF0_VF22_PROG_INTERFACE__PROG_INTERFACE_MASK
104286. BIF_CFG_DEV0_EPF0_VF22_PROG_INTERFACE__PROG_INTERFACE__SHIFT
104287. BIF_CFG_DEV0_EPF0_VF22_REVISION_ID__MAJOR_REV_ID_MASK
104288. BIF_CFG_DEV0_EPF0_VF22_REVISION_ID__MAJOR_REV_ID__SHIFT
104289. BIF_CFG_DEV0_EPF0_VF22_REVISION_ID__MINOR_REV_ID_MASK
104290. BIF_CFG_DEV0_EPF0_VF22_REVISION_ID__MINOR_REV_ID__SHIFT
104291. BIF_CFG_DEV0_EPF0_VF22_ROM_BASE_ADDR__BASE_ADDR_MASK
104292. BIF_CFG_DEV0_EPF0_VF22_ROM_BASE_ADDR__BASE_ADDR__SHIFT
104293. BIF_CFG_DEV0_EPF0_VF22_STATUS__CAP_LIST_MASK
104294. BIF_CFG_DEV0_EPF0_VF22_STATUS__CAP_LIST__SHIFT
104295. BIF_CFG_DEV0_EPF0_VF22_STATUS__DEVSEL_TIMING_MASK
104296. BIF_CFG_DEV0_EPF0_VF22_STATUS__DEVSEL_TIMING__SHIFT
104297. BIF_CFG_DEV0_EPF0_VF22_STATUS__FAST_BACK_CAPABLE_MASK
104298. BIF_CFG_DEV0_EPF0_VF22_STATUS__FAST_BACK_CAPABLE__SHIFT
104299. BIF_CFG_DEV0_EPF0_VF22_STATUS__IMMEDIATE_READINESS_MASK
104300. BIF_CFG_DEV0_EPF0_VF22_STATUS__IMMEDIATE_READINESS__SHIFT
104301. BIF_CFG_DEV0_EPF0_VF22_STATUS__INT_STATUS_MASK
104302. BIF_CFG_DEV0_EPF0_VF22_STATUS__INT_STATUS__SHIFT
104303. BIF_CFG_DEV0_EPF0_VF22_STATUS__MASTER_DATA_PARITY_ERROR_MASK
104304. BIF_CFG_DEV0_EPF0_VF22_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
104305. BIF_CFG_DEV0_EPF0_VF22_STATUS__PARITY_ERROR_DETECTED_MASK
104306. BIF_CFG_DEV0_EPF0_VF22_STATUS__PARITY_ERROR_DETECTED__SHIFT
104307. BIF_CFG_DEV0_EPF0_VF22_STATUS__PCI_66_CAP_MASK
104308. BIF_CFG_DEV0_EPF0_VF22_STATUS__PCI_66_CAP__SHIFT
104309. BIF_CFG_DEV0_EPF0_VF22_STATUS__RECEIVED_MASTER_ABORT_MASK
104310. BIF_CFG_DEV0_EPF0_VF22_STATUS__RECEIVED_MASTER_ABORT__SHIFT
104311. BIF_CFG_DEV0_EPF0_VF22_STATUS__RECEIVED_TARGET_ABORT_MASK
104312. BIF_CFG_DEV0_EPF0_VF22_STATUS__RECEIVED_TARGET_ABORT__SHIFT
104313. BIF_CFG_DEV0_EPF0_VF22_STATUS__SIGNALED_SYSTEM_ERROR_MASK
104314. BIF_CFG_DEV0_EPF0_VF22_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
104315. BIF_CFG_DEV0_EPF0_VF22_STATUS__SIGNAL_TARGET_ABORT_MASK
104316. BIF_CFG_DEV0_EPF0_VF22_STATUS__SIGNAL_TARGET_ABORT__SHIFT
104317. BIF_CFG_DEV0_EPF0_VF22_SUB_CLASS__SUB_CLASS_MASK
104318. BIF_CFG_DEV0_EPF0_VF22_SUB_CLASS__SUB_CLASS__SHIFT
104319. BIF_CFG_DEV0_EPF0_VF22_VENDOR_ID__VENDOR_ID_MASK
104320. BIF_CFG_DEV0_EPF0_VF22_VENDOR_ID__VENDOR_ID__SHIFT
104321. BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
104322. BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
104323. BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
104324. BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
104325. BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1__BASE_ADDR_MASK
104326. BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1__BASE_ADDR__SHIFT
104327. BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2__BASE_ADDR_MASK
104328. BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2__BASE_ADDR__SHIFT
104329. BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3__BASE_ADDR_MASK
104330. BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3__BASE_ADDR__SHIFT
104331. BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4__BASE_ADDR_MASK
104332. BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4__BASE_ADDR__SHIFT
104333. BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5__BASE_ADDR_MASK
104334. BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5__BASE_ADDR__SHIFT
104335. BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6__BASE_ADDR_MASK
104336. BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6__BASE_ADDR__SHIFT
104337. BIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS__BASE_CLASS_MASK
104338. BIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS__BASE_CLASS__SHIFT
104339. BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_CAP_MASK
104340. BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_CAP__SHIFT
104341. BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_COMP_MASK
104342. BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_COMP__SHIFT
104343. BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_STRT_MASK
104344. BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_STRT__SHIFT
104345. BIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
104346. BIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
104347. BIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR__CAP_PTR_MASK
104348. BIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR__CAP_PTR__SHIFT
104349. BIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
104350. BIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
104351. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__AD_STEPPING_MASK
104352. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__AD_STEPPING__SHIFT
104353. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__BUS_MASTER_EN_MASK
104354. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__BUS_MASTER_EN__SHIFT
104355. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__FAST_B2B_EN_MASK
104356. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__FAST_B2B_EN__SHIFT
104357. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__INT_DIS_MASK
104358. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__INT_DIS__SHIFT
104359. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__IO_ACCESS_EN_MASK
104360. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__IO_ACCESS_EN__SHIFT
104361. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__MEM_ACCESS_EN_MASK
104362. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__MEM_ACCESS_EN__SHIFT
104363. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
104364. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
104365. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__PAL_SNOOP_EN_MASK
104366. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__PAL_SNOOP_EN__SHIFT
104367. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
104368. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
104369. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__SERR_EN_MASK
104370. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__SERR_EN__SHIFT
104371. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__SPECIAL_CYCLE_EN_MASK
104372. BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
104373. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
104374. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
104375. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
104376. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
104377. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
104378. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
104379. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
104380. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
104381. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
104382. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
104383. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
104384. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
104385. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
104386. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
104387. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
104388. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
104389. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
104390. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
104391. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
104392. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
104393. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
104394. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
104395. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
104396. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
104397. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
104398. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
104399. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
104400. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
104401. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
104402. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
104403. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
104404. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
104405. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
104406. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
104407. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
104408. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
104409. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
104410. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
104411. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
104412. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
104413. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
104414. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
104415. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
104416. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
104417. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__EXTENDED_TAG_MASK
104418. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
104419. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__FLR_CAPABLE_MASK
104420. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
104421. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
104422. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
104423. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
104424. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
104425. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
104426. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
104427. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__PHANTOM_FUNC_MASK
104428. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
104429. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
104430. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
104431. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
104432. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
104433. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
104434. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
104435. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
104436. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
104437. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
104438. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
104439. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
104440. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
104441. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
104442. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
104443. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
104444. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
104445. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
104446. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
104447. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
104448. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
104449. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__LTR_EN_MASK
104450. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__LTR_EN__SHIFT
104451. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__OBFF_EN_MASK
104452. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__OBFF_EN__SHIFT
104453. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
104454. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
104455. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
104456. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
104457. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__CORR_ERR_EN_MASK
104458. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
104459. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
104460. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
104461. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
104462. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
104463. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__INITIATE_FLR_MASK
104464. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
104465. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
104466. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
104467. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
104468. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
104469. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
104470. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
104471. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
104472. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
104473. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
104474. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
104475. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
104476. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
104477. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__USR_REPORT_EN_MASK
104478. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
104479. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID__DEVICE_ID_MASK
104480. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID__DEVICE_ID__SHIFT
104481. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2__RESERVED_MASK
104482. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2__RESERVED__SHIFT
104483. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__AUX_PWR_MASK
104484. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__AUX_PWR__SHIFT
104485. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__CORR_ERR_MASK
104486. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__CORR_ERR__SHIFT
104487. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
104488. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
104489. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__FATAL_ERR_MASK
104490. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__FATAL_ERR__SHIFT
104491. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
104492. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
104493. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
104494. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
104495. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__USR_DETECTED_MASK
104496. BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__USR_DETECTED__SHIFT
104497. BIF_CFG_DEV0_EPF0_VF23_0_HEADER__DEVICE_TYPE_MASK
104498. BIF_CFG_DEV0_EPF0_VF23_0_HEADER__DEVICE_TYPE__SHIFT
104499. BIF_CFG_DEV0_EPF0_VF23_0_HEADER__HEADER_TYPE_MASK
104500. BIF_CFG_DEV0_EPF0_VF23_0_HEADER__HEADER_TYPE__SHIFT
104501. BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
104502. BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
104503. BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
104504. BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
104505. BIF_CFG_DEV0_EPF0_VF23_0_LATENCY__LATENCY_TIMER_MASK
104506. BIF_CFG_DEV0_EPF0_VF23_0_LATENCY__LATENCY_TIMER__SHIFT
104507. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
104508. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
104509. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
104510. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
104511. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
104512. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
104513. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
104514. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
104515. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
104516. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
104517. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
104518. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
104519. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
104520. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
104521. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
104522. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
104523. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
104524. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
104525. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
104526. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
104527. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
104528. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
104529. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__L1_EXIT_LATENCY_MASK
104530. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
104531. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
104532. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
104533. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_SPEED_MASK
104534. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_SPEED__SHIFT
104535. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_WIDTH_MASK
104536. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_WIDTH__SHIFT
104537. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__PM_SUPPORT_MASK
104538. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__PM_SUPPORT__SHIFT
104539. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__PORT_NUMBER_MASK
104540. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__PORT_NUMBER__SHIFT
104541. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
104542. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
104543. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
104544. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
104545. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
104546. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
104547. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
104548. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
104549. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
104550. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
104551. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
104552. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
104553. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
104554. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
104555. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
104556. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
104557. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__XMIT_MARGIN_MASK
104558. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
104559. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
104560. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
104561. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
104562. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
104563. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
104564. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
104565. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__EXTENDED_SYNC_MASK
104566. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
104567. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
104568. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
104569. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
104570. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
104571. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
104572. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
104573. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_DIS_MASK
104574. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_DIS__SHIFT
104575. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__PM_CONTROL_MASK
104576. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__PM_CONTROL__SHIFT
104577. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
104578. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
104579. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__RETRAIN_LINK_MASK
104580. BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__RETRAIN_LINK__SHIFT
104581. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
104582. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
104583. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
104584. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
104585. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
104586. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
104587. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
104588. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
104589. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
104590. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
104591. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
104592. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
104593. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
104594. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
104595. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
104596. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
104597. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
104598. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
104599. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
104600. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
104601. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
104602. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
104603. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
104604. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
104605. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__DL_ACTIVE_MASK
104606. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__DL_ACTIVE__SHIFT
104607. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
104608. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
104609. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
104610. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
104611. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_TRAINING_MASK
104612. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_TRAINING__SHIFT
104613. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
104614. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
104615. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
104616. BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
104617. BIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY__MAX_LAT_MASK
104618. BIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY__MAX_LAT__SHIFT
104619. BIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT__MIN_GNT_MASK
104620. BIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT__MIN_GNT__SHIFT
104621. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST__CAP_ID_MASK
104622. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST__CAP_ID__SHIFT
104623. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST__NEXT_PTR_MASK
104624. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
104625. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_EN_MASK
104626. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
104627. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
104628. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
104629. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
104630. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
104631. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA__MSIX_PBA_BIR_MASK
104632. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
104633. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
104634. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
104635. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
104636. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
104637. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
104638. BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
104639. BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST__CAP_ID_MASK
104640. BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST__CAP_ID__SHIFT
104641. BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST__NEXT_PTR_MASK
104642. BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
104643. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64__MSI_MASK_64_MASK
104644. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64__MSI_MASK_64__SHIFT
104645. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK__MSI_MASK_MASK
104646. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK__MSI_MASK__SHIFT
104647. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
104648. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
104649. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
104650. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
104651. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_64BIT_MASK
104652. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
104653. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_EN_MASK
104654. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_EN__SHIFT
104655. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
104656. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
104657. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
104658. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
104659. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
104660. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
104661. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
104662. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
104663. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA__MSI_DATA_MASK
104664. BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA__MSI_DATA__SHIFT
104665. BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64__MSI_PENDING_64_MASK
104666. BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
104667. BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING__MSI_PENDING_MASK
104668. BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING__MSI_PENDING__SHIFT
104669. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
104670. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
104671. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
104672. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
104673. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
104674. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
104675. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
104676. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
104677. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
104678. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
104679. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
104680. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
104681. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
104682. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
104683. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
104684. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
104685. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
104686. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
104687. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
104688. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
104689. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
104690. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
104691. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
104692. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
104693. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
104694. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
104695. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
104696. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
104697. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
104698. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
104699. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
104700. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
104701. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
104702. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
104703. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
104704. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
104705. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
104706. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
104707. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
104708. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
104709. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
104710. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
104711. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
104712. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
104713. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
104714. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
104715. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
104716. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
104717. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
104718. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
104719. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL__STU_MASK
104720. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL__STU__SHIFT
104721. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
104722. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
104723. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
104724. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
104725. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
104726. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
104727. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST__CAP_ID_MASK
104728. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST__CAP_ID__SHIFT
104729. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST__NEXT_PTR_MASK
104730. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
104731. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__DEVICE_TYPE_MASK
104732. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__DEVICE_TYPE__SHIFT
104733. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
104734. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
104735. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
104736. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
104737. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__VERSION_MASK
104738. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__VERSION__SHIFT
104739. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
104740. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
104741. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
104742. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
104743. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
104744. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
104745. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
104746. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
104747. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
104748. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
104749. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
104750. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
104751. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
104752. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
104753. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
104754. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
104755. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
104756. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
104757. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
104758. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
104759. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
104760. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
104761. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
104762. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
104763. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
104764. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
104765. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
104766. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
104767. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
104768. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
104769. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
104770. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
104771. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0__TLP_HDR_MASK
104772. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
104773. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1__TLP_HDR_MASK
104774. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
104775. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2__TLP_HDR_MASK
104776. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
104777. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3__TLP_HDR_MASK
104778. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
104779. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
104780. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
104781. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
104782. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
104783. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
104784. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
104785. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
104786. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
104787. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
104788. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
104789. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
104790. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
104791. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
104792. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
104793. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
104794. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
104795. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
104796. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
104797. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
104798. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
104799. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
104800. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
104801. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
104802. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
104803. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
104804. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
104805. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
104806. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
104807. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
104808. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
104809. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
104810. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
104811. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
104812. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
104813. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
104814. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
104815. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
104816. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
104817. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
104818. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
104819. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
104820. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
104821. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
104822. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
104823. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
104824. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
104825. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
104826. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
104827. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
104828. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
104829. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
104830. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
104831. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
104832. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
104833. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
104834. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
104835. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
104836. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
104837. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
104838. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
104839. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
104840. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
104841. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
104842. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
104843. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
104844. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
104845. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
104846. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
104847. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
104848. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
104849. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
104850. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
104851. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
104852. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
104853. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
104854. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
104855. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
104856. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
104857. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
104858. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
104859. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
104860. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
104861. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
104862. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
104863. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
104864. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
104865. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
104866. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
104867. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
104868. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
104869. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
104870. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
104871. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
104872. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
104873. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
104874. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
104875. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
104876. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
104877. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
104878. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
104879. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
104880. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
104881. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
104882. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
104883. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
104884. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
104885. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
104886. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
104887. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
104888. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
104889. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
104890. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
104891. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
104892. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
104893. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
104894. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
104895. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
104896. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
104897. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
104898. BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
104899. BIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE__PROG_INTERFACE_MASK
104900. BIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
104901. BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID__MAJOR_REV_ID_MASK
104902. BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID__MAJOR_REV_ID__SHIFT
104903. BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID__MINOR_REV_ID_MASK
104904. BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID__MINOR_REV_ID__SHIFT
104905. BIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR__BASE_ADDR_MASK
104906. BIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
104907. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__CAP_LIST_MASK
104908. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__CAP_LIST__SHIFT
104909. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__DEVSEL_TIMING_MASK
104910. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__DEVSEL_TIMING__SHIFT
104911. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__FAST_BACK_CAPABLE_MASK
104912. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__FAST_BACK_CAPABLE__SHIFT
104913. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__IMMEDIATE_READINESS_MASK
104914. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__IMMEDIATE_READINESS__SHIFT
104915. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__INT_STATUS_MASK
104916. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__INT_STATUS__SHIFT
104917. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
104918. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
104919. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__PARITY_ERROR_DETECTED_MASK
104920. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
104921. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__PCI_66_CAP_MASK
104922. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__PCI_66_CAP__SHIFT
104923. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__RECEIVED_MASTER_ABORT_MASK
104924. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
104925. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__RECEIVED_TARGET_ABORT_MASK
104926. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
104927. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
104928. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
104929. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__SIGNAL_TARGET_ABORT_MASK
104930. BIF_CFG_DEV0_EPF0_VF23_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
104931. BIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS__SUB_CLASS_MASK
104932. BIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS__SUB_CLASS__SHIFT
104933. BIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID__VENDOR_ID_MASK
104934. BIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID__VENDOR_ID__SHIFT
104935. BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
104936. BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
104937. BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
104938. BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
104939. BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1__BASE_ADDR_MASK
104940. BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1__BASE_ADDR__SHIFT
104941. BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2__BASE_ADDR_MASK
104942. BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2__BASE_ADDR__SHIFT
104943. BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3__BASE_ADDR_MASK
104944. BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3__BASE_ADDR__SHIFT
104945. BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4__BASE_ADDR_MASK
104946. BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4__BASE_ADDR__SHIFT
104947. BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5__BASE_ADDR_MASK
104948. BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5__BASE_ADDR__SHIFT
104949. BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6__BASE_ADDR_MASK
104950. BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6__BASE_ADDR__SHIFT
104951. BIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS__BASE_CLASS_MASK
104952. BIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS__BASE_CLASS__SHIFT
104953. BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_CAP_MASK
104954. BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_CAP__SHIFT
104955. BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_COMP_MASK
104956. BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_COMP__SHIFT
104957. BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_STRT_MASK
104958. BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_STRT__SHIFT
104959. BIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
104960. BIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
104961. BIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR__CAP_PTR_MASK
104962. BIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR__CAP_PTR__SHIFT
104963. BIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
104964. BIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
104965. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__AD_STEPPING_MASK
104966. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__AD_STEPPING__SHIFT
104967. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__BUS_MASTER_EN_MASK
104968. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__BUS_MASTER_EN__SHIFT
104969. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__FAST_B2B_EN_MASK
104970. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__FAST_B2B_EN__SHIFT
104971. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__INT_DIS_MASK
104972. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__INT_DIS__SHIFT
104973. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__IO_ACCESS_EN_MASK
104974. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__IO_ACCESS_EN__SHIFT
104975. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__MEM_ACCESS_EN_MASK
104976. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__MEM_ACCESS_EN__SHIFT
104977. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
104978. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
104979. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__PAL_SNOOP_EN_MASK
104980. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__PAL_SNOOP_EN__SHIFT
104981. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
104982. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
104983. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__SERR_EN_MASK
104984. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__SERR_EN__SHIFT
104985. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__SPECIAL_CYCLE_EN_MASK
104986. BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
104987. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
104988. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
104989. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
104990. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
104991. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
104992. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
104993. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
104994. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
104995. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
104996. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
104997. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
104998. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
104999. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
105000. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
105001. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
105002. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
105003. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
105004. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
105005. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
105006. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
105007. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
105008. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
105009. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
105010. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
105011. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
105012. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
105013. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
105014. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
105015. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
105016. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
105017. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
105018. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
105019. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
105020. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
105021. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
105022. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
105023. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
105024. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
105025. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
105026. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
105027. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
105028. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
105029. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
105030. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
105031. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__EXTENDED_TAG_MASK
105032. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
105033. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__FLR_CAPABLE_MASK
105034. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
105035. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
105036. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
105037. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
105038. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
105039. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
105040. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
105041. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__PHANTOM_FUNC_MASK
105042. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
105043. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
105044. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
105045. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
105046. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
105047. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
105048. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
105049. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
105050. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
105051. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
105052. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
105053. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
105054. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
105055. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
105056. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
105057. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
105058. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
105059. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
105060. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
105061. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
105062. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
105063. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__LTR_EN_MASK
105064. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__LTR_EN__SHIFT
105065. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__OBFF_EN_MASK
105066. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__OBFF_EN__SHIFT
105067. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
105068. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
105069. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
105070. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
105071. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__CORR_ERR_EN_MASK
105072. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
105073. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
105074. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
105075. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
105076. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
105077. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__INITIATE_FLR_MASK
105078. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
105079. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
105080. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
105081. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
105082. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
105083. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
105084. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
105085. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
105086. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
105087. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
105088. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
105089. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
105090. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
105091. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__USR_REPORT_EN_MASK
105092. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
105093. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID__DEVICE_ID_MASK
105094. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID__DEVICE_ID__SHIFT
105095. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2__RESERVED_MASK
105096. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2__RESERVED__SHIFT
105097. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__AUX_PWR_MASK
105098. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__AUX_PWR__SHIFT
105099. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__CORR_ERR_MASK
105100. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__CORR_ERR__SHIFT
105101. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
105102. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
105103. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__FATAL_ERR_MASK
105104. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__FATAL_ERR__SHIFT
105105. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
105106. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
105107. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
105108. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
105109. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__USR_DETECTED_MASK
105110. BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__USR_DETECTED__SHIFT
105111. BIF_CFG_DEV0_EPF0_VF23_1_HEADER__DEVICE_TYPE_MASK
105112. BIF_CFG_DEV0_EPF0_VF23_1_HEADER__DEVICE_TYPE__SHIFT
105113. BIF_CFG_DEV0_EPF0_VF23_1_HEADER__HEADER_TYPE_MASK
105114. BIF_CFG_DEV0_EPF0_VF23_1_HEADER__HEADER_TYPE__SHIFT
105115. BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
105116. BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
105117. BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
105118. BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
105119. BIF_CFG_DEV0_EPF0_VF23_1_LATENCY__LATENCY_TIMER_MASK
105120. BIF_CFG_DEV0_EPF0_VF23_1_LATENCY__LATENCY_TIMER__SHIFT
105121. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
105122. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
105123. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
105124. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
105125. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
105126. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
105127. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
105128. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
105129. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
105130. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
105131. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
105132. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
105133. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
105134. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
105135. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
105136. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
105137. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
105138. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
105139. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
105140. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
105141. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
105142. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
105143. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__L1_EXIT_LATENCY_MASK
105144. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
105145. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
105146. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
105147. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_SPEED_MASK
105148. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_SPEED__SHIFT
105149. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_WIDTH_MASK
105150. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_WIDTH__SHIFT
105151. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__PM_SUPPORT_MASK
105152. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__PM_SUPPORT__SHIFT
105153. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__PORT_NUMBER_MASK
105154. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__PORT_NUMBER__SHIFT
105155. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
105156. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
105157. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
105158. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
105159. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
105160. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
105161. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
105162. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
105163. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
105164. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
105165. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
105166. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
105167. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
105168. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
105169. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
105170. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
105171. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__XMIT_MARGIN_MASK
105172. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
105173. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
105174. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
105175. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
105176. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
105177. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
105178. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
105179. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__EXTENDED_SYNC_MASK
105180. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
105181. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
105182. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
105183. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
105184. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
105185. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
105186. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
105187. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_DIS_MASK
105188. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_DIS__SHIFT
105189. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__PM_CONTROL_MASK
105190. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__PM_CONTROL__SHIFT
105191. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
105192. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
105193. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__RETRAIN_LINK_MASK
105194. BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__RETRAIN_LINK__SHIFT
105195. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
105196. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
105197. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
105198. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
105199. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
105200. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
105201. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
105202. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
105203. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
105204. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
105205. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
105206. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
105207. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
105208. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
105209. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
105210. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
105211. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
105212. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
105213. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
105214. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
105215. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
105216. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
105217. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
105218. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
105219. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__DL_ACTIVE_MASK
105220. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__DL_ACTIVE__SHIFT
105221. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
105222. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
105223. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
105224. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
105225. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_TRAINING_MASK
105226. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_TRAINING__SHIFT
105227. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
105228. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
105229. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
105230. BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
105231. BIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY__MAX_LAT_MASK
105232. BIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY__MAX_LAT__SHIFT
105233. BIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT__MIN_GNT_MASK
105234. BIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT__MIN_GNT__SHIFT
105235. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST__CAP_ID_MASK
105236. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST__CAP_ID__SHIFT
105237. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST__NEXT_PTR_MASK
105238. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
105239. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_EN_MASK
105240. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
105241. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
105242. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
105243. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
105244. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
105245. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA__MSIX_PBA_BIR_MASK
105246. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
105247. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
105248. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
105249. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
105250. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
105251. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
105252. BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
105253. BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST__CAP_ID_MASK
105254. BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST__CAP_ID__SHIFT
105255. BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST__NEXT_PTR_MASK
105256. BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
105257. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64__MSI_MASK_64_MASK
105258. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64__MSI_MASK_64__SHIFT
105259. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK__MSI_MASK_MASK
105260. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK__MSI_MASK__SHIFT
105261. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
105262. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
105263. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
105264. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
105265. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_64BIT_MASK
105266. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
105267. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_EN_MASK
105268. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_EN__SHIFT
105269. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
105270. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
105271. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
105272. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
105273. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
105274. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
105275. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
105276. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
105277. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA__MSI_DATA_MASK
105278. BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA__MSI_DATA__SHIFT
105279. BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64__MSI_PENDING_64_MASK
105280. BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
105281. BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING__MSI_PENDING_MASK
105282. BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING__MSI_PENDING__SHIFT
105283. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
105284. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
105285. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
105286. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
105287. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
105288. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
105289. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
105290. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
105291. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
105292. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
105293. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
105294. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
105295. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
105296. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
105297. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
105298. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
105299. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
105300. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
105301. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
105302. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
105303. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
105304. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
105305. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
105306. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
105307. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
105308. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
105309. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
105310. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
105311. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
105312. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
105313. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
105314. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
105315. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
105316. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
105317. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
105318. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
105319. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
105320. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
105321. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
105322. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
105323. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
105324. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
105325. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
105326. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
105327. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
105328. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
105329. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
105330. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
105331. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
105332. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
105333. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL__STU_MASK
105334. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL__STU__SHIFT
105335. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
105336. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
105337. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
105338. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
105339. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
105340. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
105341. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST__CAP_ID_MASK
105342. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST__CAP_ID__SHIFT
105343. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST__NEXT_PTR_MASK
105344. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
105345. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__DEVICE_TYPE_MASK
105346. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__DEVICE_TYPE__SHIFT
105347. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
105348. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
105349. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
105350. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
105351. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__VERSION_MASK
105352. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__VERSION__SHIFT
105353. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
105354. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
105355. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
105356. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
105357. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
105358. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
105359. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
105360. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
105361. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
105362. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
105363. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
105364. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
105365. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
105366. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
105367. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
105368. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
105369. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
105370. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
105371. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
105372. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
105373. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
105374. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
105375. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
105376. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
105377. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
105378. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
105379. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
105380. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
105381. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
105382. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
105383. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
105384. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
105385. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0__TLP_HDR_MASK
105386. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
105387. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1__TLP_HDR_MASK
105388. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
105389. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2__TLP_HDR_MASK
105390. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
105391. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3__TLP_HDR_MASK
105392. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
105393. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
105394. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
105395. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
105396. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
105397. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
105398. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
105399. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
105400. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
105401. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
105402. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
105403. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
105404. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
105405. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
105406. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
105407. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
105408. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
105409. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
105410. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
105411. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
105412. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
105413. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
105414. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
105415. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
105416. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
105417. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
105418. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
105419. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
105420. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
105421. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
105422. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
105423. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
105424. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
105425. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
105426. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
105427. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
105428. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
105429. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
105430. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
105431. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
105432. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
105433. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
105434. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
105435. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
105436. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
105437. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
105438. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
105439. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
105440. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
105441. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
105442. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
105443. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
105444. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
105445. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
105446. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
105447. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
105448. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
105449. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
105450. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
105451. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
105452. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
105453. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
105454. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
105455. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
105456. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
105457. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
105458. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
105459. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
105460. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
105461. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
105462. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
105463. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
105464. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
105465. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
105466. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
105467. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
105468. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
105469. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
105470. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
105471. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
105472. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
105473. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
105474. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
105475. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
105476. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
105477. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
105478. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
105479. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
105480. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
105481. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
105482. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
105483. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
105484. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
105485. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
105486. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
105487. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
105488. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
105489. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
105490. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
105491. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
105492. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
105493. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
105494. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
105495. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
105496. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
105497. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
105498. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
105499. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
105500. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
105501. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
105502. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
105503. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
105504. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
105505. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
105506. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
105507. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
105508. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
105509. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
105510. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
105511. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
105512. BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
105513. BIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE__PROG_INTERFACE_MASK
105514. BIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
105515. BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID__MAJOR_REV_ID_MASK
105516. BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID__MAJOR_REV_ID__SHIFT
105517. BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID__MINOR_REV_ID_MASK
105518. BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID__MINOR_REV_ID__SHIFT
105519. BIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR__BASE_ADDR_MASK
105520. BIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
105521. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__CAP_LIST_MASK
105522. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__CAP_LIST__SHIFT
105523. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__DEVSEL_TIMING_MASK
105524. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__DEVSEL_TIMING__SHIFT
105525. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__FAST_BACK_CAPABLE_MASK
105526. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__FAST_BACK_CAPABLE__SHIFT
105527. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__IMMEDIATE_READINESS_MASK
105528. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__IMMEDIATE_READINESS__SHIFT
105529. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__INT_STATUS_MASK
105530. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__INT_STATUS__SHIFT
105531. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
105532. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
105533. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__PARITY_ERROR_DETECTED_MASK
105534. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
105535. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__PCI_66_CAP_MASK
105536. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__PCI_66_CAP__SHIFT
105537. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__RECEIVED_MASTER_ABORT_MASK
105538. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
105539. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__RECEIVED_TARGET_ABORT_MASK
105540. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
105541. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
105542. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
105543. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__SIGNAL_TARGET_ABORT_MASK
105544. BIF_CFG_DEV0_EPF0_VF23_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
105545. BIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS__SUB_CLASS_MASK
105546. BIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS__SUB_CLASS__SHIFT
105547. BIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID__VENDOR_ID_MASK
105548. BIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID__VENDOR_ID__SHIFT
105549. BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID__SUBSYSTEM_ID_MASK
105550. BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
105551. BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
105552. BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
105553. BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_1__BASE_ADDR_MASK
105554. BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_1__BASE_ADDR__SHIFT
105555. BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_2__BASE_ADDR_MASK
105556. BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_2__BASE_ADDR__SHIFT
105557. BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_3__BASE_ADDR_MASK
105558. BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_3__BASE_ADDR__SHIFT
105559. BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_4__BASE_ADDR_MASK
105560. BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_4__BASE_ADDR__SHIFT
105561. BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_5__BASE_ADDR_MASK
105562. BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_5__BASE_ADDR__SHIFT
105563. BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_6__BASE_ADDR_MASK
105564. BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_6__BASE_ADDR__SHIFT
105565. BIF_CFG_DEV0_EPF0_VF23_BASE_CLASS__BASE_CLASS_MASK
105566. BIF_CFG_DEV0_EPF0_VF23_BASE_CLASS__BASE_CLASS__SHIFT
105567. BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_CAP_MASK
105568. BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_CAP__SHIFT
105569. BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_COMP_MASK
105570. BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_COMP__SHIFT
105571. BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_STRT_MASK
105572. BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_STRT__SHIFT
105573. BIF_CFG_DEV0_EPF0_VF23_CACHE_LINE__CACHE_LINE_SIZE_MASK
105574. BIF_CFG_DEV0_EPF0_VF23_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
105575. BIF_CFG_DEV0_EPF0_VF23_CAP_PTR__CAP_PTR_MASK
105576. BIF_CFG_DEV0_EPF0_VF23_CAP_PTR__CAP_PTR__SHIFT
105577. BIF_CFG_DEV0_EPF0_VF23_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
105578. BIF_CFG_DEV0_EPF0_VF23_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
105579. BIF_CFG_DEV0_EPF0_VF23_COMMAND__AD_STEPPING_MASK
105580. BIF_CFG_DEV0_EPF0_VF23_COMMAND__AD_STEPPING__SHIFT
105581. BIF_CFG_DEV0_EPF0_VF23_COMMAND__BUS_MASTER_EN_MASK
105582. BIF_CFG_DEV0_EPF0_VF23_COMMAND__BUS_MASTER_EN__SHIFT
105583. BIF_CFG_DEV0_EPF0_VF23_COMMAND__FAST_B2B_EN_MASK
105584. BIF_CFG_DEV0_EPF0_VF23_COMMAND__FAST_B2B_EN__SHIFT
105585. BIF_CFG_DEV0_EPF0_VF23_COMMAND__INT_DIS_MASK
105586. BIF_CFG_DEV0_EPF0_VF23_COMMAND__INT_DIS__SHIFT
105587. BIF_CFG_DEV0_EPF0_VF23_COMMAND__IO_ACCESS_EN_MASK
105588. BIF_CFG_DEV0_EPF0_VF23_COMMAND__IO_ACCESS_EN__SHIFT
105589. BIF_CFG_DEV0_EPF0_VF23_COMMAND__MEM_ACCESS_EN_MASK
105590. BIF_CFG_DEV0_EPF0_VF23_COMMAND__MEM_ACCESS_EN__SHIFT
105591. BIF_CFG_DEV0_EPF0_VF23_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
105592. BIF_CFG_DEV0_EPF0_VF23_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
105593. BIF_CFG_DEV0_EPF0_VF23_COMMAND__PAL_SNOOP_EN_MASK
105594. BIF_CFG_DEV0_EPF0_VF23_COMMAND__PAL_SNOOP_EN__SHIFT
105595. BIF_CFG_DEV0_EPF0_VF23_COMMAND__PARITY_ERROR_RESPONSE_MASK
105596. BIF_CFG_DEV0_EPF0_VF23_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
105597. BIF_CFG_DEV0_EPF0_VF23_COMMAND__SERR_EN_MASK
105598. BIF_CFG_DEV0_EPF0_VF23_COMMAND__SERR_EN__SHIFT
105599. BIF_CFG_DEV0_EPF0_VF23_COMMAND__SPECIAL_CYCLE_EN_MASK
105600. BIF_CFG_DEV0_EPF0_VF23_COMMAND__SPECIAL_CYCLE_EN__SHIFT
105601. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
105602. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
105603. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
105604. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
105605. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
105606. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
105607. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
105608. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
105609. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
105610. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
105611. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
105612. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
105613. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
105614. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
105615. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
105616. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
105617. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
105618. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
105619. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
105620. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
105621. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
105622. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
105623. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__FRS_SUPPORTED_MASK
105624. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
105625. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
105626. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
105627. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__LTR_SUPPORTED_MASK
105628. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
105629. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
105630. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
105631. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
105632. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
105633. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__OBFF_SUPPORTED_MASK
105634. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
105635. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
105636. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
105637. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
105638. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
105639. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
105640. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
105641. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
105642. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
105643. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
105644. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
105645. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__EXTENDED_TAG_MASK
105646. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__EXTENDED_TAG__SHIFT
105647. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__FLR_CAPABLE_MASK
105648. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__FLR_CAPABLE__SHIFT
105649. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
105650. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
105651. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
105652. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
105653. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
105654. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
105655. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__PHANTOM_FUNC_MASK
105656. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__PHANTOM_FUNC__SHIFT
105657. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
105658. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
105659. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
105660. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
105661. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
105662. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
105663. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
105664. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
105665. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
105666. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
105667. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
105668. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
105669. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
105670. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
105671. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
105672. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
105673. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
105674. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
105675. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
105676. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
105677. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__LTR_EN_MASK
105678. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__LTR_EN__SHIFT
105679. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__OBFF_EN_MASK
105680. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__OBFF_EN__SHIFT
105681. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
105682. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
105683. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
105684. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
105685. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__CORR_ERR_EN_MASK
105686. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__CORR_ERR_EN__SHIFT
105687. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
105688. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
105689. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__FATAL_ERR_EN_MASK
105690. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
105691. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__INITIATE_FLR_MASK
105692. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__INITIATE_FLR__SHIFT
105693. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
105694. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
105695. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
105696. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
105697. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
105698. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
105699. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__NO_SNOOP_EN_MASK
105700. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
105701. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
105702. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
105703. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__RELAXED_ORD_EN_MASK
105704. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
105705. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__USR_REPORT_EN_MASK
105706. BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__USR_REPORT_EN__SHIFT
105707. BIF_CFG_DEV0_EPF0_VF23_DEVICE_ID__DEVICE_ID_MASK
105708. BIF_CFG_DEV0_EPF0_VF23_DEVICE_ID__DEVICE_ID__SHIFT
105709. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS2__RESERVED_MASK
105710. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS2__RESERVED__SHIFT
105711. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__AUX_PWR_MASK
105712. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__AUX_PWR__SHIFT
105713. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__CORR_ERR_MASK
105714. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__CORR_ERR__SHIFT
105715. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
105716. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
105717. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__FATAL_ERR_MASK
105718. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__FATAL_ERR__SHIFT
105719. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__NON_FATAL_ERR_MASK
105720. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
105721. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
105722. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
105723. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__USR_DETECTED_MASK
105724. BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__USR_DETECTED__SHIFT
105725. BIF_CFG_DEV0_EPF0_VF23_HEADER__DEVICE_TYPE_MASK
105726. BIF_CFG_DEV0_EPF0_VF23_HEADER__DEVICE_TYPE__SHIFT
105727. BIF_CFG_DEV0_EPF0_VF23_HEADER__HEADER_TYPE_MASK
105728. BIF_CFG_DEV0_EPF0_VF23_HEADER__HEADER_TYPE__SHIFT
105729. BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_LINE__INTERRUPT_LINE_MASK
105730. BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
105731. BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_PIN__INTERRUPT_PIN_MASK
105732. BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
105733. BIF_CFG_DEV0_EPF0_VF23_LATENCY__LATENCY_TIMER_MASK
105734. BIF_CFG_DEV0_EPF0_VF23_LATENCY__LATENCY_TIMER__SHIFT
105735. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
105736. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
105737. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
105738. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
105739. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
105740. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
105741. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
105742. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
105743. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
105744. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
105745. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
105746. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
105747. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
105748. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
105749. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
105750. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
105751. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
105752. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
105753. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
105754. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
105755. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__L0S_EXIT_LATENCY_MASK
105756. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
105757. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__L1_EXIT_LATENCY_MASK
105758. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__L1_EXIT_LATENCY__SHIFT
105759. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
105760. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
105761. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_SPEED_MASK
105762. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_SPEED__SHIFT
105763. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_WIDTH_MASK
105764. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_WIDTH__SHIFT
105765. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__PM_SUPPORT_MASK
105766. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__PM_SUPPORT__SHIFT
105767. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__PORT_NUMBER_MASK
105768. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__PORT_NUMBER__SHIFT
105769. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
105770. BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
105771. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
105772. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
105773. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__COMPLIANCE_SOS_MASK
105774. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
105775. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__ENTER_COMPLIANCE_MASK
105776. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
105777. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
105778. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
105779. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
105780. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
105781. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
105782. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
105783. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__TARGET_LINK_SPEED_MASK
105784. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
105785. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__XMIT_MARGIN_MASK
105786. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__XMIT_MARGIN__SHIFT
105787. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
105788. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
105789. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__COMMON_CLOCK_CFG_MASK
105790. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
105791. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
105792. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
105793. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__EXTENDED_SYNC_MASK
105794. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__EXTENDED_SYNC__SHIFT
105795. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
105796. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
105797. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
105798. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
105799. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
105800. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
105801. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_DIS_MASK
105802. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_DIS__SHIFT
105803. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__PM_CONTROL_MASK
105804. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__PM_CONTROL__SHIFT
105805. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__READ_CPL_BOUNDARY_MASK
105806. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
105807. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__RETRAIN_LINK_MASK
105808. BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__RETRAIN_LINK__SHIFT
105809. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
105810. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
105811. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
105812. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
105813. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
105814. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
105815. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
105816. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
105817. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
105818. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
105819. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
105820. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
105821. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
105822. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
105823. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
105824. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
105825. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
105826. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
105827. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
105828. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
105829. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
105830. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
105831. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__CURRENT_LINK_SPEED_MASK
105832. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
105833. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__DL_ACTIVE_MASK
105834. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__DL_ACTIVE__SHIFT
105835. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
105836. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
105837. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
105838. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
105839. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_TRAINING_MASK
105840. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_TRAINING__SHIFT
105841. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
105842. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
105843. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__SLOT_CLOCK_CFG_MASK
105844. BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
105845. BIF_CFG_DEV0_EPF0_VF23_MAX_LATENCY__MAX_LAT_MASK
105846. BIF_CFG_DEV0_EPF0_VF23_MAX_LATENCY__MAX_LAT__SHIFT
105847. BIF_CFG_DEV0_EPF0_VF23_MIN_GRANT__MIN_GNT_MASK
105848. BIF_CFG_DEV0_EPF0_VF23_MIN_GRANT__MIN_GNT__SHIFT
105849. BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST__CAP_ID_MASK
105850. BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST__CAP_ID__SHIFT
105851. BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST__NEXT_PTR_MASK
105852. BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST__NEXT_PTR__SHIFT
105853. BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_EN_MASK
105854. BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_EN__SHIFT
105855. BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
105856. BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
105857. BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
105858. BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
105859. BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA__MSIX_PBA_BIR_MASK
105860. BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA__MSIX_PBA_BIR__SHIFT
105861. BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA__MSIX_PBA_OFFSET_MASK
105862. BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
105863. BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE__MSIX_TABLE_BIR_MASK
105864. BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
105865. BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
105866. BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
105867. BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST__CAP_ID_MASK
105868. BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST__CAP_ID__SHIFT
105869. BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST__NEXT_PTR_MASK
105870. BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST__NEXT_PTR__SHIFT
105871. BIF_CFG_DEV0_EPF0_VF23_MSI_MASK_64__MSI_MASK_64_MASK
105872. BIF_CFG_DEV0_EPF0_VF23_MSI_MASK_64__MSI_MASK_64__SHIFT
105873. BIF_CFG_DEV0_EPF0_VF23_MSI_MASK__MSI_MASK_MASK
105874. BIF_CFG_DEV0_EPF0_VF23_MSI_MASK__MSI_MASK__SHIFT
105875. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
105876. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
105877. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
105878. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
105879. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_64BIT_MASK
105880. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_64BIT__SHIFT
105881. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_EN_MASK
105882. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_EN__SHIFT
105883. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
105884. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
105885. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
105886. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
105887. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
105888. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
105889. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA_64__MSI_DATA_64_MASK
105890. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
105891. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA__MSI_DATA_MASK
105892. BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA__MSI_DATA__SHIFT
105893. BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING_64__MSI_PENDING_64_MASK
105894. BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING_64__MSI_PENDING_64__SHIFT
105895. BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING__MSI_PENDING_MASK
105896. BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING__MSI_PENDING__SHIFT
105897. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
105898. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
105899. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
105900. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
105901. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
105902. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
105903. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
105904. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
105905. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
105906. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
105907. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
105908. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
105909. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
105910. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
105911. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
105912. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
105913. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
105914. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
105915. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
105916. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
105917. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
105918. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
105919. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
105920. BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
105921. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
105922. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
105923. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
105924. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
105925. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
105926. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
105927. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
105928. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
105929. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
105930. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
105931. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
105932. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
105933. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
105934. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
105935. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
105936. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
105937. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
105938. BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
105939. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
105940. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
105941. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
105942. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
105943. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
105944. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
105945. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL__ATC_ENABLE_MASK
105946. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
105947. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL__STU_MASK
105948. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL__STU__SHIFT
105949. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
105950. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
105951. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
105952. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
105953. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
105954. BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
105955. BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST__CAP_ID_MASK
105956. BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST__CAP_ID__SHIFT
105957. BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST__NEXT_PTR_MASK
105958. BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST__NEXT_PTR__SHIFT
105959. BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__DEVICE_TYPE_MASK
105960. BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__DEVICE_TYPE__SHIFT
105961. BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__INT_MESSAGE_NUM_MASK
105962. BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
105963. BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__SLOT_IMPLEMENTED_MASK
105964. BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
105965. BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__VERSION_MASK
105966. BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__VERSION__SHIFT
105967. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
105968. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
105969. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
105970. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
105971. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
105972. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
105973. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
105974. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
105975. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
105976. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
105977. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
105978. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
105979. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
105980. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
105981. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
105982. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
105983. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
105984. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
105985. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
105986. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
105987. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
105988. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
105989. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
105990. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
105991. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
105992. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
105993. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
105994. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
105995. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
105996. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
105997. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
105998. BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
105999. BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG0__TLP_HDR_MASK
106000. BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG0__TLP_HDR__SHIFT
106001. BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG1__TLP_HDR_MASK
106002. BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG1__TLP_HDR__SHIFT
106003. BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG2__TLP_HDR_MASK
106004. BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG2__TLP_HDR__SHIFT
106005. BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG3__TLP_HDR_MASK
106006. BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG3__TLP_HDR__SHIFT
106007. BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
106008. BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
106009. BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
106010. BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
106011. BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
106012. BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
106013. BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
106014. BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
106015. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
106016. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
106017. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
106018. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
106019. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
106020. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
106021. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
106022. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
106023. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
106024. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
106025. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
106026. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
106027. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
106028. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
106029. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
106030. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
106031. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
106032. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
106033. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
106034. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
106035. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
106036. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
106037. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
106038. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
106039. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
106040. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
106041. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
106042. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
106043. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
106044. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
106045. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
106046. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
106047. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
106048. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
106049. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
106050. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
106051. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
106052. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
106053. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
106054. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
106055. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
106056. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
106057. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
106058. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
106059. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
106060. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
106061. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
106062. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
106063. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
106064. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
106065. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
106066. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
106067. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
106068. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
106069. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
106070. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
106071. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
106072. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
106073. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
106074. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
106075. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
106076. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
106077. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
106078. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
106079. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
106080. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
106081. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
106082. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
106083. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
106084. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
106085. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
106086. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
106087. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
106088. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
106089. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
106090. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
106091. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
106092. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
106093. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
106094. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
106095. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
106096. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
106097. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
106098. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
106099. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
106100. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
106101. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
106102. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
106103. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
106104. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
106105. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
106106. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
106107. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
106108. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
106109. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
106110. BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
106111. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
106112. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
106113. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
106114. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
106115. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
106116. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
106117. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
106118. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
106119. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
106120. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
106121. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
106122. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
106123. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
106124. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
106125. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
106126. BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
106127. BIF_CFG_DEV0_EPF0_VF23_PROG_INTERFACE__PROG_INTERFACE_MASK
106128. BIF_CFG_DEV0_EPF0_VF23_PROG_INTERFACE__PROG_INTERFACE__SHIFT
106129. BIF_CFG_DEV0_EPF0_VF23_REVISION_ID__MAJOR_REV_ID_MASK
106130. BIF_CFG_DEV0_EPF0_VF23_REVISION_ID__MAJOR_REV_ID__SHIFT
106131. BIF_CFG_DEV0_EPF0_VF23_REVISION_ID__MINOR_REV_ID_MASK
106132. BIF_CFG_DEV0_EPF0_VF23_REVISION_ID__MINOR_REV_ID__SHIFT
106133. BIF_CFG_DEV0_EPF0_VF23_ROM_BASE_ADDR__BASE_ADDR_MASK
106134. BIF_CFG_DEV0_EPF0_VF23_ROM_BASE_ADDR__BASE_ADDR__SHIFT
106135. BIF_CFG_DEV0_EPF0_VF23_STATUS__CAP_LIST_MASK
106136. BIF_CFG_DEV0_EPF0_VF23_STATUS__CAP_LIST__SHIFT
106137. BIF_CFG_DEV0_EPF0_VF23_STATUS__DEVSEL_TIMING_MASK
106138. BIF_CFG_DEV0_EPF0_VF23_STATUS__DEVSEL_TIMING__SHIFT
106139. BIF_CFG_DEV0_EPF0_VF23_STATUS__FAST_BACK_CAPABLE_MASK
106140. BIF_CFG_DEV0_EPF0_VF23_STATUS__FAST_BACK_CAPABLE__SHIFT
106141. BIF_CFG_DEV0_EPF0_VF23_STATUS__IMMEDIATE_READINESS_MASK
106142. BIF_CFG_DEV0_EPF0_VF23_STATUS__IMMEDIATE_READINESS__SHIFT
106143. BIF_CFG_DEV0_EPF0_VF23_STATUS__INT_STATUS_MASK
106144. BIF_CFG_DEV0_EPF0_VF23_STATUS__INT_STATUS__SHIFT
106145. BIF_CFG_DEV0_EPF0_VF23_STATUS__MASTER_DATA_PARITY_ERROR_MASK
106146. BIF_CFG_DEV0_EPF0_VF23_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
106147. BIF_CFG_DEV0_EPF0_VF23_STATUS__PARITY_ERROR_DETECTED_MASK
106148. BIF_CFG_DEV0_EPF0_VF23_STATUS__PARITY_ERROR_DETECTED__SHIFT
106149. BIF_CFG_DEV0_EPF0_VF23_STATUS__PCI_66_CAP_MASK
106150. BIF_CFG_DEV0_EPF0_VF23_STATUS__PCI_66_CAP__SHIFT
106151. BIF_CFG_DEV0_EPF0_VF23_STATUS__RECEIVED_MASTER_ABORT_MASK
106152. BIF_CFG_DEV0_EPF0_VF23_STATUS__RECEIVED_MASTER_ABORT__SHIFT
106153. BIF_CFG_DEV0_EPF0_VF23_STATUS__RECEIVED_TARGET_ABORT_MASK
106154. BIF_CFG_DEV0_EPF0_VF23_STATUS__RECEIVED_TARGET_ABORT__SHIFT
106155. BIF_CFG_DEV0_EPF0_VF23_STATUS__SIGNALED_SYSTEM_ERROR_MASK
106156. BIF_CFG_DEV0_EPF0_VF23_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
106157. BIF_CFG_DEV0_EPF0_VF23_STATUS__SIGNAL_TARGET_ABORT_MASK
106158. BIF_CFG_DEV0_EPF0_VF23_STATUS__SIGNAL_TARGET_ABORT__SHIFT
106159. BIF_CFG_DEV0_EPF0_VF23_SUB_CLASS__SUB_CLASS_MASK
106160. BIF_CFG_DEV0_EPF0_VF23_SUB_CLASS__SUB_CLASS__SHIFT
106161. BIF_CFG_DEV0_EPF0_VF23_VENDOR_ID__VENDOR_ID_MASK
106162. BIF_CFG_DEV0_EPF0_VF23_VENDOR_ID__VENDOR_ID__SHIFT
106163. BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
106164. BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
106165. BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
106166. BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
106167. BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1__BASE_ADDR_MASK
106168. BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1__BASE_ADDR__SHIFT
106169. BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2__BASE_ADDR_MASK
106170. BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2__BASE_ADDR__SHIFT
106171. BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3__BASE_ADDR_MASK
106172. BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3__BASE_ADDR__SHIFT
106173. BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4__BASE_ADDR_MASK
106174. BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4__BASE_ADDR__SHIFT
106175. BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5__BASE_ADDR_MASK
106176. BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5__BASE_ADDR__SHIFT
106177. BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6__BASE_ADDR_MASK
106178. BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6__BASE_ADDR__SHIFT
106179. BIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS__BASE_CLASS_MASK
106180. BIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS__BASE_CLASS__SHIFT
106181. BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_CAP_MASK
106182. BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_CAP__SHIFT
106183. BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_COMP_MASK
106184. BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_COMP__SHIFT
106185. BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_STRT_MASK
106186. BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_STRT__SHIFT
106187. BIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
106188. BIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
106189. BIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR__CAP_PTR_MASK
106190. BIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR__CAP_PTR__SHIFT
106191. BIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
106192. BIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
106193. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__AD_STEPPING_MASK
106194. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__AD_STEPPING__SHIFT
106195. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__BUS_MASTER_EN_MASK
106196. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__BUS_MASTER_EN__SHIFT
106197. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__FAST_B2B_EN_MASK
106198. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__FAST_B2B_EN__SHIFT
106199. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__INT_DIS_MASK
106200. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__INT_DIS__SHIFT
106201. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__IO_ACCESS_EN_MASK
106202. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__IO_ACCESS_EN__SHIFT
106203. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__MEM_ACCESS_EN_MASK
106204. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__MEM_ACCESS_EN__SHIFT
106205. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
106206. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
106207. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__PAL_SNOOP_EN_MASK
106208. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__PAL_SNOOP_EN__SHIFT
106209. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
106210. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
106211. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__SERR_EN_MASK
106212. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__SERR_EN__SHIFT
106213. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__SPECIAL_CYCLE_EN_MASK
106214. BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
106215. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
106216. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
106217. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
106218. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
106219. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
106220. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
106221. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
106222. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
106223. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
106224. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
106225. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
106226. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
106227. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
106228. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
106229. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
106230. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
106231. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
106232. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
106233. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
106234. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
106235. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
106236. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
106237. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
106238. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
106239. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
106240. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
106241. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
106242. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
106243. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
106244. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
106245. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
106246. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
106247. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
106248. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
106249. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
106250. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
106251. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
106252. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
106253. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
106254. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
106255. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
106256. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
106257. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
106258. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
106259. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__EXTENDED_TAG_MASK
106260. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
106261. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__FLR_CAPABLE_MASK
106262. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
106263. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
106264. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
106265. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
106266. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
106267. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
106268. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
106269. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__PHANTOM_FUNC_MASK
106270. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
106271. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
106272. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
106273. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
106274. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
106275. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
106276. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
106277. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
106278. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
106279. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
106280. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
106281. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
106282. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
106283. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
106284. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
106285. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
106286. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
106287. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
106288. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
106289. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
106290. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
106291. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__LTR_EN_MASK
106292. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__LTR_EN__SHIFT
106293. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__OBFF_EN_MASK
106294. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__OBFF_EN__SHIFT
106295. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
106296. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
106297. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
106298. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
106299. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__CORR_ERR_EN_MASK
106300. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
106301. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
106302. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
106303. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
106304. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
106305. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__INITIATE_FLR_MASK
106306. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
106307. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
106308. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
106309. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
106310. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
106311. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
106312. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
106313. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
106314. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
106315. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
106316. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
106317. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
106318. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
106319. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__USR_REPORT_EN_MASK
106320. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
106321. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID__DEVICE_ID_MASK
106322. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID__DEVICE_ID__SHIFT
106323. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2__RESERVED_MASK
106324. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2__RESERVED__SHIFT
106325. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__AUX_PWR_MASK
106326. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__AUX_PWR__SHIFT
106327. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__CORR_ERR_MASK
106328. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__CORR_ERR__SHIFT
106329. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
106330. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
106331. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__FATAL_ERR_MASK
106332. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__FATAL_ERR__SHIFT
106333. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
106334. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
106335. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
106336. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
106337. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__USR_DETECTED_MASK
106338. BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__USR_DETECTED__SHIFT
106339. BIF_CFG_DEV0_EPF0_VF24_0_HEADER__DEVICE_TYPE_MASK
106340. BIF_CFG_DEV0_EPF0_VF24_0_HEADER__DEVICE_TYPE__SHIFT
106341. BIF_CFG_DEV0_EPF0_VF24_0_HEADER__HEADER_TYPE_MASK
106342. BIF_CFG_DEV0_EPF0_VF24_0_HEADER__HEADER_TYPE__SHIFT
106343. BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
106344. BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
106345. BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
106346. BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
106347. BIF_CFG_DEV0_EPF0_VF24_0_LATENCY__LATENCY_TIMER_MASK
106348. BIF_CFG_DEV0_EPF0_VF24_0_LATENCY__LATENCY_TIMER__SHIFT
106349. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
106350. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
106351. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
106352. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
106353. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
106354. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
106355. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
106356. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
106357. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
106358. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
106359. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
106360. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
106361. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
106362. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
106363. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
106364. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
106365. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
106366. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
106367. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
106368. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
106369. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
106370. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
106371. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__L1_EXIT_LATENCY_MASK
106372. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
106373. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
106374. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
106375. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_SPEED_MASK
106376. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_SPEED__SHIFT
106377. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_WIDTH_MASK
106378. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_WIDTH__SHIFT
106379. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__PM_SUPPORT_MASK
106380. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__PM_SUPPORT__SHIFT
106381. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__PORT_NUMBER_MASK
106382. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__PORT_NUMBER__SHIFT
106383. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
106384. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
106385. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
106386. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
106387. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
106388. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
106389. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
106390. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
106391. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
106392. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
106393. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
106394. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
106395. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
106396. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
106397. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
106398. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
106399. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__XMIT_MARGIN_MASK
106400. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
106401. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
106402. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
106403. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
106404. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
106405. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
106406. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
106407. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__EXTENDED_SYNC_MASK
106408. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
106409. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
106410. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
106411. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
106412. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
106413. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
106414. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
106415. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_DIS_MASK
106416. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_DIS__SHIFT
106417. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__PM_CONTROL_MASK
106418. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__PM_CONTROL__SHIFT
106419. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
106420. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
106421. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__RETRAIN_LINK_MASK
106422. BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__RETRAIN_LINK__SHIFT
106423. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
106424. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
106425. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
106426. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
106427. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
106428. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
106429. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
106430. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
106431. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
106432. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
106433. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
106434. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
106435. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
106436. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
106437. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
106438. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
106439. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
106440. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
106441. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
106442. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
106443. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
106444. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
106445. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
106446. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
106447. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__DL_ACTIVE_MASK
106448. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__DL_ACTIVE__SHIFT
106449. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
106450. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
106451. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
106452. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
106453. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_TRAINING_MASK
106454. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_TRAINING__SHIFT
106455. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
106456. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
106457. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
106458. BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
106459. BIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY__MAX_LAT_MASK
106460. BIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY__MAX_LAT__SHIFT
106461. BIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT__MIN_GNT_MASK
106462. BIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT__MIN_GNT__SHIFT
106463. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST__CAP_ID_MASK
106464. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST__CAP_ID__SHIFT
106465. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST__NEXT_PTR_MASK
106466. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
106467. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_EN_MASK
106468. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
106469. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
106470. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
106471. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
106472. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
106473. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA__MSIX_PBA_BIR_MASK
106474. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
106475. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
106476. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
106477. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
106478. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
106479. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
106480. BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
106481. BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST__CAP_ID_MASK
106482. BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST__CAP_ID__SHIFT
106483. BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST__NEXT_PTR_MASK
106484. BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
106485. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64__MSI_MASK_64_MASK
106486. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64__MSI_MASK_64__SHIFT
106487. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK__MSI_MASK_MASK
106488. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK__MSI_MASK__SHIFT
106489. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
106490. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
106491. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
106492. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
106493. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_64BIT_MASK
106494. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
106495. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_EN_MASK
106496. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_EN__SHIFT
106497. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
106498. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
106499. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
106500. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
106501. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
106502. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
106503. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
106504. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
106505. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA__MSI_DATA_MASK
106506. BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA__MSI_DATA__SHIFT
106507. BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64__MSI_PENDING_64_MASK
106508. BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
106509. BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING__MSI_PENDING_MASK
106510. BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING__MSI_PENDING__SHIFT
106511. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
106512. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
106513. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
106514. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
106515. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
106516. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
106517. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
106518. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
106519. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
106520. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
106521. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
106522. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
106523. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
106524. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
106525. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
106526. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
106527. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
106528. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
106529. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
106530. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
106531. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
106532. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
106533. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
106534. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
106535. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
106536. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
106537. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
106538. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
106539. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
106540. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
106541. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
106542. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
106543. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
106544. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
106545. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
106546. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
106547. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
106548. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
106549. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
106550. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
106551. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
106552. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
106553. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
106554. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
106555. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
106556. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
106557. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
106558. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
106559. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
106560. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
106561. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL__STU_MASK
106562. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL__STU__SHIFT
106563. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
106564. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
106565. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
106566. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
106567. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
106568. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
106569. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST__CAP_ID_MASK
106570. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST__CAP_ID__SHIFT
106571. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST__NEXT_PTR_MASK
106572. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
106573. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__DEVICE_TYPE_MASK
106574. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__DEVICE_TYPE__SHIFT
106575. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
106576. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
106577. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
106578. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
106579. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__VERSION_MASK
106580. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__VERSION__SHIFT
106581. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
106582. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
106583. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
106584. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
106585. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
106586. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
106587. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
106588. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
106589. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
106590. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
106591. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
106592. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
106593. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
106594. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
106595. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
106596. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
106597. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
106598. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
106599. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
106600. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
106601. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
106602. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
106603. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
106604. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
106605. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
106606. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
106607. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
106608. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
106609. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
106610. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
106611. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
106612. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
106613. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0__TLP_HDR_MASK
106614. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
106615. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1__TLP_HDR_MASK
106616. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
106617. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2__TLP_HDR_MASK
106618. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
106619. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3__TLP_HDR_MASK
106620. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
106621. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
106622. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
106623. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
106624. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
106625. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
106626. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
106627. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
106628. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
106629. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
106630. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
106631. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
106632. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
106633. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
106634. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
106635. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
106636. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
106637. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
106638. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
106639. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
106640. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
106641. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
106642. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
106643. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
106644. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
106645. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
106646. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
106647. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
106648. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
106649. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
106650. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
106651. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
106652. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
106653. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
106654. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
106655. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
106656. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
106657. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
106658. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
106659. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
106660. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
106661. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
106662. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
106663. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
106664. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
106665. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
106666. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
106667. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
106668. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
106669. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
106670. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
106671. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
106672. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
106673. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
106674. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
106675. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
106676. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
106677. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
106678. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
106679. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
106680. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
106681. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
106682. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
106683. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
106684. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
106685. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
106686. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
106687. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
106688. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
106689. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
106690. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
106691. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
106692. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
106693. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
106694. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
106695. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
106696. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
106697. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
106698. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
106699. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
106700. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
106701. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
106702. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
106703. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
106704. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
106705. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
106706. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
106707. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
106708. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
106709. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
106710. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
106711. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
106712. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
106713. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
106714. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
106715. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
106716. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
106717. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
106718. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
106719. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
106720. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
106721. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
106722. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
106723. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
106724. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
106725. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
106726. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
106727. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
106728. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
106729. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
106730. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
106731. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
106732. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
106733. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
106734. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
106735. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
106736. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
106737. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
106738. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
106739. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
106740. BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
106741. BIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE__PROG_INTERFACE_MASK
106742. BIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
106743. BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID__MAJOR_REV_ID_MASK
106744. BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID__MAJOR_REV_ID__SHIFT
106745. BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID__MINOR_REV_ID_MASK
106746. BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID__MINOR_REV_ID__SHIFT
106747. BIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR__BASE_ADDR_MASK
106748. BIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
106749. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__CAP_LIST_MASK
106750. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__CAP_LIST__SHIFT
106751. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__DEVSEL_TIMING_MASK
106752. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__DEVSEL_TIMING__SHIFT
106753. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__FAST_BACK_CAPABLE_MASK
106754. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__FAST_BACK_CAPABLE__SHIFT
106755. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__IMMEDIATE_READINESS_MASK
106756. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__IMMEDIATE_READINESS__SHIFT
106757. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__INT_STATUS_MASK
106758. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__INT_STATUS__SHIFT
106759. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
106760. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
106761. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__PARITY_ERROR_DETECTED_MASK
106762. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
106763. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__PCI_66_CAP_MASK
106764. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__PCI_66_CAP__SHIFT
106765. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__RECEIVED_MASTER_ABORT_MASK
106766. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
106767. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__RECEIVED_TARGET_ABORT_MASK
106768. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
106769. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
106770. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
106771. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__SIGNAL_TARGET_ABORT_MASK
106772. BIF_CFG_DEV0_EPF0_VF24_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
106773. BIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS__SUB_CLASS_MASK
106774. BIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS__SUB_CLASS__SHIFT
106775. BIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID__VENDOR_ID_MASK
106776. BIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID__VENDOR_ID__SHIFT
106777. BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
106778. BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
106779. BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
106780. BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
106781. BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1__BASE_ADDR_MASK
106782. BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1__BASE_ADDR__SHIFT
106783. BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2__BASE_ADDR_MASK
106784. BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2__BASE_ADDR__SHIFT
106785. BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3__BASE_ADDR_MASK
106786. BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3__BASE_ADDR__SHIFT
106787. BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4__BASE_ADDR_MASK
106788. BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4__BASE_ADDR__SHIFT
106789. BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5__BASE_ADDR_MASK
106790. BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5__BASE_ADDR__SHIFT
106791. BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6__BASE_ADDR_MASK
106792. BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6__BASE_ADDR__SHIFT
106793. BIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS__BASE_CLASS_MASK
106794. BIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS__BASE_CLASS__SHIFT
106795. BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_CAP_MASK
106796. BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_CAP__SHIFT
106797. BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_COMP_MASK
106798. BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_COMP__SHIFT
106799. BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_STRT_MASK
106800. BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_STRT__SHIFT
106801. BIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
106802. BIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
106803. BIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR__CAP_PTR_MASK
106804. BIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR__CAP_PTR__SHIFT
106805. BIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
106806. BIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
106807. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__AD_STEPPING_MASK
106808. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__AD_STEPPING__SHIFT
106809. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__BUS_MASTER_EN_MASK
106810. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__BUS_MASTER_EN__SHIFT
106811. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__FAST_B2B_EN_MASK
106812. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__FAST_B2B_EN__SHIFT
106813. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__INT_DIS_MASK
106814. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__INT_DIS__SHIFT
106815. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__IO_ACCESS_EN_MASK
106816. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__IO_ACCESS_EN__SHIFT
106817. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__MEM_ACCESS_EN_MASK
106818. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__MEM_ACCESS_EN__SHIFT
106819. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
106820. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
106821. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__PAL_SNOOP_EN_MASK
106822. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__PAL_SNOOP_EN__SHIFT
106823. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
106824. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
106825. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__SERR_EN_MASK
106826. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__SERR_EN__SHIFT
106827. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__SPECIAL_CYCLE_EN_MASK
106828. BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
106829. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
106830. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
106831. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
106832. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
106833. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
106834. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
106835. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
106836. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
106837. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
106838. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
106839. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
106840. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
106841. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
106842. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
106843. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
106844. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
106845. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
106846. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
106847. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
106848. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
106849. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
106850. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
106851. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
106852. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
106853. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
106854. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
106855. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
106856. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
106857. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
106858. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
106859. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
106860. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
106861. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
106862. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
106863. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
106864. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
106865. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
106866. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
106867. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
106868. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
106869. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
106870. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
106871. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
106872. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
106873. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__EXTENDED_TAG_MASK
106874. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
106875. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__FLR_CAPABLE_MASK
106876. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
106877. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
106878. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
106879. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
106880. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
106881. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
106882. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
106883. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__PHANTOM_FUNC_MASK
106884. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
106885. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
106886. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
106887. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
106888. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
106889. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
106890. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
106891. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
106892. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
106893. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
106894. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
106895. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
106896. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
106897. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
106898. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
106899. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
106900. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
106901. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
106902. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
106903. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
106904. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
106905. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__LTR_EN_MASK
106906. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__LTR_EN__SHIFT
106907. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__OBFF_EN_MASK
106908. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__OBFF_EN__SHIFT
106909. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
106910. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
106911. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
106912. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
106913. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__CORR_ERR_EN_MASK
106914. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
106915. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
106916. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
106917. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
106918. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
106919. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__INITIATE_FLR_MASK
106920. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
106921. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
106922. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
106923. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
106924. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
106925. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
106926. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
106927. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
106928. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
106929. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
106930. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
106931. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
106932. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
106933. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__USR_REPORT_EN_MASK
106934. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
106935. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID__DEVICE_ID_MASK
106936. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID__DEVICE_ID__SHIFT
106937. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2__RESERVED_MASK
106938. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2__RESERVED__SHIFT
106939. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__AUX_PWR_MASK
106940. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__AUX_PWR__SHIFT
106941. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__CORR_ERR_MASK
106942. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__CORR_ERR__SHIFT
106943. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
106944. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
106945. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__FATAL_ERR_MASK
106946. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__FATAL_ERR__SHIFT
106947. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
106948. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
106949. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
106950. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
106951. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__USR_DETECTED_MASK
106952. BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__USR_DETECTED__SHIFT
106953. BIF_CFG_DEV0_EPF0_VF24_1_HEADER__DEVICE_TYPE_MASK
106954. BIF_CFG_DEV0_EPF0_VF24_1_HEADER__DEVICE_TYPE__SHIFT
106955. BIF_CFG_DEV0_EPF0_VF24_1_HEADER__HEADER_TYPE_MASK
106956. BIF_CFG_DEV0_EPF0_VF24_1_HEADER__HEADER_TYPE__SHIFT
106957. BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
106958. BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
106959. BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
106960. BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
106961. BIF_CFG_DEV0_EPF0_VF24_1_LATENCY__LATENCY_TIMER_MASK
106962. BIF_CFG_DEV0_EPF0_VF24_1_LATENCY__LATENCY_TIMER__SHIFT
106963. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
106964. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
106965. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
106966. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
106967. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
106968. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
106969. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
106970. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
106971. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
106972. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
106973. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
106974. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
106975. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
106976. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
106977. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
106978. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
106979. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
106980. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
106981. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
106982. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
106983. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
106984. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
106985. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__L1_EXIT_LATENCY_MASK
106986. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
106987. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
106988. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
106989. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_SPEED_MASK
106990. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_SPEED__SHIFT
106991. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_WIDTH_MASK
106992. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_WIDTH__SHIFT
106993. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__PM_SUPPORT_MASK
106994. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__PM_SUPPORT__SHIFT
106995. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__PORT_NUMBER_MASK
106996. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__PORT_NUMBER__SHIFT
106997. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
106998. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
106999. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
107000. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
107001. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
107002. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
107003. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
107004. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
107005. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
107006. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
107007. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
107008. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
107009. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
107010. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
107011. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
107012. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
107013. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__XMIT_MARGIN_MASK
107014. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
107015. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
107016. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
107017. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
107018. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
107019. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
107020. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
107021. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__EXTENDED_SYNC_MASK
107022. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
107023. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
107024. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
107025. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
107026. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
107027. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
107028. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
107029. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_DIS_MASK
107030. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_DIS__SHIFT
107031. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__PM_CONTROL_MASK
107032. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__PM_CONTROL__SHIFT
107033. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
107034. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
107035. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__RETRAIN_LINK_MASK
107036. BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__RETRAIN_LINK__SHIFT
107037. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
107038. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
107039. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
107040. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
107041. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
107042. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
107043. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
107044. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
107045. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
107046. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
107047. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
107048. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
107049. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
107050. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
107051. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
107052. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
107053. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
107054. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
107055. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
107056. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
107057. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
107058. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
107059. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
107060. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
107061. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__DL_ACTIVE_MASK
107062. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__DL_ACTIVE__SHIFT
107063. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
107064. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
107065. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
107066. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
107067. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_TRAINING_MASK
107068. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_TRAINING__SHIFT
107069. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
107070. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
107071. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
107072. BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
107073. BIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY__MAX_LAT_MASK
107074. BIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY__MAX_LAT__SHIFT
107075. BIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT__MIN_GNT_MASK
107076. BIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT__MIN_GNT__SHIFT
107077. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST__CAP_ID_MASK
107078. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST__CAP_ID__SHIFT
107079. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST__NEXT_PTR_MASK
107080. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
107081. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_EN_MASK
107082. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
107083. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
107084. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
107085. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
107086. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
107087. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA__MSIX_PBA_BIR_MASK
107088. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
107089. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
107090. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
107091. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
107092. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
107093. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
107094. BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
107095. BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST__CAP_ID_MASK
107096. BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST__CAP_ID__SHIFT
107097. BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST__NEXT_PTR_MASK
107098. BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
107099. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64__MSI_MASK_64_MASK
107100. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64__MSI_MASK_64__SHIFT
107101. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK__MSI_MASK_MASK
107102. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK__MSI_MASK__SHIFT
107103. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
107104. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
107105. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
107106. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
107107. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_64BIT_MASK
107108. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
107109. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_EN_MASK
107110. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_EN__SHIFT
107111. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
107112. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
107113. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
107114. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
107115. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
107116. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
107117. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
107118. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
107119. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA__MSI_DATA_MASK
107120. BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA__MSI_DATA__SHIFT
107121. BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64__MSI_PENDING_64_MASK
107122. BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
107123. BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING__MSI_PENDING_MASK
107124. BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING__MSI_PENDING__SHIFT
107125. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
107126. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
107127. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
107128. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
107129. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
107130. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
107131. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
107132. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
107133. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
107134. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
107135. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
107136. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
107137. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
107138. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
107139. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
107140. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
107141. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
107142. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
107143. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
107144. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
107145. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
107146. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
107147. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
107148. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
107149. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
107150. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
107151. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
107152. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
107153. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
107154. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
107155. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
107156. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
107157. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
107158. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
107159. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
107160. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
107161. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
107162. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
107163. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
107164. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
107165. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
107166. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
107167. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
107168. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
107169. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
107170. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
107171. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
107172. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
107173. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
107174. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
107175. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL__STU_MASK
107176. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL__STU__SHIFT
107177. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
107178. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
107179. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
107180. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
107181. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
107182. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
107183. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST__CAP_ID_MASK
107184. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST__CAP_ID__SHIFT
107185. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST__NEXT_PTR_MASK
107186. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
107187. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__DEVICE_TYPE_MASK
107188. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__DEVICE_TYPE__SHIFT
107189. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
107190. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
107191. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
107192. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
107193. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__VERSION_MASK
107194. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__VERSION__SHIFT
107195. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
107196. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
107197. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
107198. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
107199. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
107200. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
107201. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
107202. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
107203. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
107204. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
107205. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
107206. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
107207. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
107208. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
107209. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
107210. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
107211. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
107212. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
107213. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
107214. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
107215. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
107216. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
107217. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
107218. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
107219. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
107220. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
107221. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
107222. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
107223. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
107224. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
107225. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
107226. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
107227. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0__TLP_HDR_MASK
107228. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
107229. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1__TLP_HDR_MASK
107230. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
107231. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2__TLP_HDR_MASK
107232. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
107233. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3__TLP_HDR_MASK
107234. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
107235. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
107236. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
107237. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
107238. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
107239. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
107240. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
107241. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
107242. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
107243. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
107244. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
107245. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
107246. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
107247. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
107248. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
107249. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
107250. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
107251. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
107252. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
107253. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
107254. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
107255. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
107256. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
107257. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
107258. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
107259. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
107260. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
107261. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
107262. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
107263. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
107264. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
107265. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
107266. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
107267. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
107268. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
107269. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
107270. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
107271. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
107272. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
107273. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
107274. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
107275. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
107276. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
107277. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
107278. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
107279. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
107280. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
107281. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
107282. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
107283. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
107284. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
107285. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
107286. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
107287. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
107288. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
107289. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
107290. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
107291. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
107292. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
107293. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
107294. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
107295. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
107296. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
107297. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
107298. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
107299. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
107300. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
107301. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
107302. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
107303. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
107304. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
107305. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
107306. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
107307. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
107308. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
107309. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
107310. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
107311. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
107312. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
107313. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
107314. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
107315. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
107316. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
107317. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
107318. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
107319. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
107320. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
107321. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
107322. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
107323. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
107324. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
107325. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
107326. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
107327. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
107328. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
107329. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
107330. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
107331. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
107332. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
107333. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
107334. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
107335. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
107336. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
107337. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
107338. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
107339. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
107340. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
107341. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
107342. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
107343. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
107344. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
107345. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
107346. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
107347. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
107348. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
107349. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
107350. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
107351. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
107352. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
107353. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
107354. BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
107355. BIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE__PROG_INTERFACE_MASK
107356. BIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
107357. BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID__MAJOR_REV_ID_MASK
107358. BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID__MAJOR_REV_ID__SHIFT
107359. BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID__MINOR_REV_ID_MASK
107360. BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID__MINOR_REV_ID__SHIFT
107361. BIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR__BASE_ADDR_MASK
107362. BIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
107363. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__CAP_LIST_MASK
107364. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__CAP_LIST__SHIFT
107365. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__DEVSEL_TIMING_MASK
107366. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__DEVSEL_TIMING__SHIFT
107367. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__FAST_BACK_CAPABLE_MASK
107368. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__FAST_BACK_CAPABLE__SHIFT
107369. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__IMMEDIATE_READINESS_MASK
107370. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__IMMEDIATE_READINESS__SHIFT
107371. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__INT_STATUS_MASK
107372. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__INT_STATUS__SHIFT
107373. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
107374. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
107375. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__PARITY_ERROR_DETECTED_MASK
107376. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
107377. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__PCI_66_CAP_MASK
107378. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__PCI_66_CAP__SHIFT
107379. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__RECEIVED_MASTER_ABORT_MASK
107380. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
107381. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__RECEIVED_TARGET_ABORT_MASK
107382. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
107383. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
107384. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
107385. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__SIGNAL_TARGET_ABORT_MASK
107386. BIF_CFG_DEV0_EPF0_VF24_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
107387. BIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS__SUB_CLASS_MASK
107388. BIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS__SUB_CLASS__SHIFT
107389. BIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID__VENDOR_ID_MASK
107390. BIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID__VENDOR_ID__SHIFT
107391. BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID__SUBSYSTEM_ID_MASK
107392. BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
107393. BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
107394. BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
107395. BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_1__BASE_ADDR_MASK
107396. BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_1__BASE_ADDR__SHIFT
107397. BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_2__BASE_ADDR_MASK
107398. BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_2__BASE_ADDR__SHIFT
107399. BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_3__BASE_ADDR_MASK
107400. BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_3__BASE_ADDR__SHIFT
107401. BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_4__BASE_ADDR_MASK
107402. BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_4__BASE_ADDR__SHIFT
107403. BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_5__BASE_ADDR_MASK
107404. BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_5__BASE_ADDR__SHIFT
107405. BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_6__BASE_ADDR_MASK
107406. BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_6__BASE_ADDR__SHIFT
107407. BIF_CFG_DEV0_EPF0_VF24_BASE_CLASS__BASE_CLASS_MASK
107408. BIF_CFG_DEV0_EPF0_VF24_BASE_CLASS__BASE_CLASS__SHIFT
107409. BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_CAP_MASK
107410. BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_CAP__SHIFT
107411. BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_COMP_MASK
107412. BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_COMP__SHIFT
107413. BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_STRT_MASK
107414. BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_STRT__SHIFT
107415. BIF_CFG_DEV0_EPF0_VF24_CACHE_LINE__CACHE_LINE_SIZE_MASK
107416. BIF_CFG_DEV0_EPF0_VF24_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
107417. BIF_CFG_DEV0_EPF0_VF24_CAP_PTR__CAP_PTR_MASK
107418. BIF_CFG_DEV0_EPF0_VF24_CAP_PTR__CAP_PTR__SHIFT
107419. BIF_CFG_DEV0_EPF0_VF24_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
107420. BIF_CFG_DEV0_EPF0_VF24_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
107421. BIF_CFG_DEV0_EPF0_VF24_COMMAND__AD_STEPPING_MASK
107422. BIF_CFG_DEV0_EPF0_VF24_COMMAND__AD_STEPPING__SHIFT
107423. BIF_CFG_DEV0_EPF0_VF24_COMMAND__BUS_MASTER_EN_MASK
107424. BIF_CFG_DEV0_EPF0_VF24_COMMAND__BUS_MASTER_EN__SHIFT
107425. BIF_CFG_DEV0_EPF0_VF24_COMMAND__FAST_B2B_EN_MASK
107426. BIF_CFG_DEV0_EPF0_VF24_COMMAND__FAST_B2B_EN__SHIFT
107427. BIF_CFG_DEV0_EPF0_VF24_COMMAND__INT_DIS_MASK
107428. BIF_CFG_DEV0_EPF0_VF24_COMMAND__INT_DIS__SHIFT
107429. BIF_CFG_DEV0_EPF0_VF24_COMMAND__IO_ACCESS_EN_MASK
107430. BIF_CFG_DEV0_EPF0_VF24_COMMAND__IO_ACCESS_EN__SHIFT
107431. BIF_CFG_DEV0_EPF0_VF24_COMMAND__MEM_ACCESS_EN_MASK
107432. BIF_CFG_DEV0_EPF0_VF24_COMMAND__MEM_ACCESS_EN__SHIFT
107433. BIF_CFG_DEV0_EPF0_VF24_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
107434. BIF_CFG_DEV0_EPF0_VF24_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
107435. BIF_CFG_DEV0_EPF0_VF24_COMMAND__PAL_SNOOP_EN_MASK
107436. BIF_CFG_DEV0_EPF0_VF24_COMMAND__PAL_SNOOP_EN__SHIFT
107437. BIF_CFG_DEV0_EPF0_VF24_COMMAND__PARITY_ERROR_RESPONSE_MASK
107438. BIF_CFG_DEV0_EPF0_VF24_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
107439. BIF_CFG_DEV0_EPF0_VF24_COMMAND__SERR_EN_MASK
107440. BIF_CFG_DEV0_EPF0_VF24_COMMAND__SERR_EN__SHIFT
107441. BIF_CFG_DEV0_EPF0_VF24_COMMAND__SPECIAL_CYCLE_EN_MASK
107442. BIF_CFG_DEV0_EPF0_VF24_COMMAND__SPECIAL_CYCLE_EN__SHIFT
107443. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
107444. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
107445. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
107446. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
107447. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
107448. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
107449. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
107450. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
107451. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
107452. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
107453. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
107454. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
107455. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
107456. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
107457. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
107458. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
107459. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
107460. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
107461. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
107462. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
107463. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
107464. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
107465. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__FRS_SUPPORTED_MASK
107466. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
107467. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
107468. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
107469. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__LTR_SUPPORTED_MASK
107470. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
107471. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
107472. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
107473. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
107474. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
107475. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__OBFF_SUPPORTED_MASK
107476. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
107477. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
107478. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
107479. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
107480. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
107481. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
107482. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
107483. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
107484. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
107485. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
107486. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
107487. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__EXTENDED_TAG_MASK
107488. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__EXTENDED_TAG__SHIFT
107489. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__FLR_CAPABLE_MASK
107490. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__FLR_CAPABLE__SHIFT
107491. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
107492. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
107493. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
107494. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
107495. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
107496. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
107497. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__PHANTOM_FUNC_MASK
107498. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__PHANTOM_FUNC__SHIFT
107499. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
107500. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
107501. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
107502. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
107503. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
107504. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
107505. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
107506. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
107507. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
107508. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
107509. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
107510. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
107511. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
107512. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
107513. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
107514. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
107515. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
107516. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
107517. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
107518. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
107519. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__LTR_EN_MASK
107520. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__LTR_EN__SHIFT
107521. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__OBFF_EN_MASK
107522. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__OBFF_EN__SHIFT
107523. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
107524. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
107525. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
107526. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
107527. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__CORR_ERR_EN_MASK
107528. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__CORR_ERR_EN__SHIFT
107529. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
107530. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
107531. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__FATAL_ERR_EN_MASK
107532. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
107533. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__INITIATE_FLR_MASK
107534. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__INITIATE_FLR__SHIFT
107535. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
107536. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
107537. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
107538. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
107539. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
107540. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
107541. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__NO_SNOOP_EN_MASK
107542. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
107543. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
107544. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
107545. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__RELAXED_ORD_EN_MASK
107546. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
107547. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__USR_REPORT_EN_MASK
107548. BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__USR_REPORT_EN__SHIFT
107549. BIF_CFG_DEV0_EPF0_VF24_DEVICE_ID__DEVICE_ID_MASK
107550. BIF_CFG_DEV0_EPF0_VF24_DEVICE_ID__DEVICE_ID__SHIFT
107551. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS2__RESERVED_MASK
107552. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS2__RESERVED__SHIFT
107553. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__AUX_PWR_MASK
107554. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__AUX_PWR__SHIFT
107555. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__CORR_ERR_MASK
107556. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__CORR_ERR__SHIFT
107557. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
107558. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
107559. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__FATAL_ERR_MASK
107560. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__FATAL_ERR__SHIFT
107561. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__NON_FATAL_ERR_MASK
107562. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
107563. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
107564. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
107565. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__USR_DETECTED_MASK
107566. BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__USR_DETECTED__SHIFT
107567. BIF_CFG_DEV0_EPF0_VF24_HEADER__DEVICE_TYPE_MASK
107568. BIF_CFG_DEV0_EPF0_VF24_HEADER__DEVICE_TYPE__SHIFT
107569. BIF_CFG_DEV0_EPF0_VF24_HEADER__HEADER_TYPE_MASK
107570. BIF_CFG_DEV0_EPF0_VF24_HEADER__HEADER_TYPE__SHIFT
107571. BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_LINE__INTERRUPT_LINE_MASK
107572. BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
107573. BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_PIN__INTERRUPT_PIN_MASK
107574. BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
107575. BIF_CFG_DEV0_EPF0_VF24_LATENCY__LATENCY_TIMER_MASK
107576. BIF_CFG_DEV0_EPF0_VF24_LATENCY__LATENCY_TIMER__SHIFT
107577. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
107578. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
107579. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
107580. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
107581. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
107582. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
107583. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
107584. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
107585. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
107586. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
107587. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
107588. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
107589. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
107590. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
107591. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
107592. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
107593. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
107594. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
107595. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
107596. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
107597. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__L0S_EXIT_LATENCY_MASK
107598. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
107599. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__L1_EXIT_LATENCY_MASK
107600. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__L1_EXIT_LATENCY__SHIFT
107601. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
107602. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
107603. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_SPEED_MASK
107604. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_SPEED__SHIFT
107605. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_WIDTH_MASK
107606. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_WIDTH__SHIFT
107607. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__PM_SUPPORT_MASK
107608. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__PM_SUPPORT__SHIFT
107609. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__PORT_NUMBER_MASK
107610. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__PORT_NUMBER__SHIFT
107611. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
107612. BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
107613. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
107614. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
107615. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__COMPLIANCE_SOS_MASK
107616. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
107617. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__ENTER_COMPLIANCE_MASK
107618. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
107619. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
107620. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
107621. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
107622. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
107623. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
107624. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
107625. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__TARGET_LINK_SPEED_MASK
107626. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
107627. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__XMIT_MARGIN_MASK
107628. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__XMIT_MARGIN__SHIFT
107629. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
107630. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
107631. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__COMMON_CLOCK_CFG_MASK
107632. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
107633. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
107634. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
107635. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__EXTENDED_SYNC_MASK
107636. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__EXTENDED_SYNC__SHIFT
107637. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
107638. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
107639. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
107640. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
107641. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
107642. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
107643. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_DIS_MASK
107644. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_DIS__SHIFT
107645. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__PM_CONTROL_MASK
107646. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__PM_CONTROL__SHIFT
107647. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__READ_CPL_BOUNDARY_MASK
107648. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
107649. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__RETRAIN_LINK_MASK
107650. BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__RETRAIN_LINK__SHIFT
107651. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
107652. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
107653. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
107654. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
107655. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
107656. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
107657. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
107658. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
107659. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
107660. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
107661. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
107662. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
107663. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
107664. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
107665. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
107666. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
107667. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
107668. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
107669. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
107670. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
107671. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
107672. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
107673. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__CURRENT_LINK_SPEED_MASK
107674. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
107675. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__DL_ACTIVE_MASK
107676. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__DL_ACTIVE__SHIFT
107677. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
107678. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
107679. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
107680. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
107681. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_TRAINING_MASK
107682. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_TRAINING__SHIFT
107683. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
107684. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
107685. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__SLOT_CLOCK_CFG_MASK
107686. BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
107687. BIF_CFG_DEV0_EPF0_VF24_MAX_LATENCY__MAX_LAT_MASK
107688. BIF_CFG_DEV0_EPF0_VF24_MAX_LATENCY__MAX_LAT__SHIFT
107689. BIF_CFG_DEV0_EPF0_VF24_MIN_GRANT__MIN_GNT_MASK
107690. BIF_CFG_DEV0_EPF0_VF24_MIN_GRANT__MIN_GNT__SHIFT
107691. BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST__CAP_ID_MASK
107692. BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST__CAP_ID__SHIFT
107693. BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST__NEXT_PTR_MASK
107694. BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST__NEXT_PTR__SHIFT
107695. BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_EN_MASK
107696. BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_EN__SHIFT
107697. BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
107698. BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
107699. BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
107700. BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
107701. BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA__MSIX_PBA_BIR_MASK
107702. BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA__MSIX_PBA_BIR__SHIFT
107703. BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA__MSIX_PBA_OFFSET_MASK
107704. BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
107705. BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE__MSIX_TABLE_BIR_MASK
107706. BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
107707. BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
107708. BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
107709. BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST__CAP_ID_MASK
107710. BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST__CAP_ID__SHIFT
107711. BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST__NEXT_PTR_MASK
107712. BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST__NEXT_PTR__SHIFT
107713. BIF_CFG_DEV0_EPF0_VF24_MSI_MASK_64__MSI_MASK_64_MASK
107714. BIF_CFG_DEV0_EPF0_VF24_MSI_MASK_64__MSI_MASK_64__SHIFT
107715. BIF_CFG_DEV0_EPF0_VF24_MSI_MASK__MSI_MASK_MASK
107716. BIF_CFG_DEV0_EPF0_VF24_MSI_MASK__MSI_MASK__SHIFT
107717. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
107718. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
107719. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
107720. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
107721. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_64BIT_MASK
107722. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_64BIT__SHIFT
107723. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_EN_MASK
107724. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_EN__SHIFT
107725. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
107726. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
107727. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
107728. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
107729. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
107730. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
107731. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA_64__MSI_DATA_64_MASK
107732. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
107733. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA__MSI_DATA_MASK
107734. BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA__MSI_DATA__SHIFT
107735. BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING_64__MSI_PENDING_64_MASK
107736. BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING_64__MSI_PENDING_64__SHIFT
107737. BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING__MSI_PENDING_MASK
107738. BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING__MSI_PENDING__SHIFT
107739. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
107740. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
107741. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
107742. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
107743. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
107744. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
107745. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
107746. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
107747. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
107748. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
107749. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
107750. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
107751. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
107752. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
107753. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
107754. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
107755. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
107756. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
107757. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
107758. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
107759. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
107760. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
107761. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
107762. BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
107763. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
107764. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
107765. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
107766. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
107767. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
107768. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
107769. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
107770. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
107771. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
107772. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
107773. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
107774. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
107775. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
107776. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
107777. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
107778. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
107779. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
107780. BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
107781. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
107782. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
107783. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
107784. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
107785. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
107786. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
107787. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL__ATC_ENABLE_MASK
107788. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
107789. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL__STU_MASK
107790. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL__STU__SHIFT
107791. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
107792. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
107793. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
107794. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
107795. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
107796. BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
107797. BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST__CAP_ID_MASK
107798. BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST__CAP_ID__SHIFT
107799. BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST__NEXT_PTR_MASK
107800. BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST__NEXT_PTR__SHIFT
107801. BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__DEVICE_TYPE_MASK
107802. BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__DEVICE_TYPE__SHIFT
107803. BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__INT_MESSAGE_NUM_MASK
107804. BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
107805. BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__SLOT_IMPLEMENTED_MASK
107806. BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
107807. BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__VERSION_MASK
107808. BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__VERSION__SHIFT
107809. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
107810. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
107811. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
107812. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
107813. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
107814. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
107815. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
107816. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
107817. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
107818. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
107819. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
107820. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
107821. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
107822. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
107823. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
107824. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
107825. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
107826. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
107827. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
107828. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
107829. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
107830. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
107831. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
107832. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
107833. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
107834. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
107835. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
107836. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
107837. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
107838. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
107839. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
107840. BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
107841. BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG0__TLP_HDR_MASK
107842. BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG0__TLP_HDR__SHIFT
107843. BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG1__TLP_HDR_MASK
107844. BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG1__TLP_HDR__SHIFT
107845. BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG2__TLP_HDR_MASK
107846. BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG2__TLP_HDR__SHIFT
107847. BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG3__TLP_HDR_MASK
107848. BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG3__TLP_HDR__SHIFT
107849. BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
107850. BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
107851. BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
107852. BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
107853. BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
107854. BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
107855. BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
107856. BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
107857. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
107858. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
107859. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
107860. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
107861. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
107862. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
107863. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
107864. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
107865. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
107866. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
107867. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
107868. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
107869. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
107870. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
107871. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
107872. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
107873. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
107874. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
107875. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
107876. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
107877. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
107878. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
107879. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
107880. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
107881. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
107882. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
107883. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
107884. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
107885. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
107886. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
107887. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
107888. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
107889. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
107890. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
107891. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
107892. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
107893. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
107894. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
107895. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
107896. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
107897. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
107898. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
107899. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
107900. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
107901. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
107902. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
107903. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
107904. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
107905. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
107906. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
107907. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
107908. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
107909. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
107910. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
107911. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
107912. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
107913. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
107914. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
107915. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
107916. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
107917. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
107918. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
107919. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
107920. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
107921. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
107922. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
107923. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
107924. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
107925. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
107926. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
107927. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
107928. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
107929. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
107930. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
107931. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
107932. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
107933. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
107934. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
107935. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
107936. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
107937. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
107938. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
107939. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
107940. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
107941. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
107942. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
107943. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
107944. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
107945. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
107946. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
107947. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
107948. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
107949. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
107950. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
107951. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
107952. BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
107953. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
107954. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
107955. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
107956. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
107957. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
107958. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
107959. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
107960. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
107961. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
107962. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
107963. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
107964. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
107965. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
107966. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
107967. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
107968. BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
107969. BIF_CFG_DEV0_EPF0_VF24_PROG_INTERFACE__PROG_INTERFACE_MASK
107970. BIF_CFG_DEV0_EPF0_VF24_PROG_INTERFACE__PROG_INTERFACE__SHIFT
107971. BIF_CFG_DEV0_EPF0_VF24_REVISION_ID__MAJOR_REV_ID_MASK
107972. BIF_CFG_DEV0_EPF0_VF24_REVISION_ID__MAJOR_REV_ID__SHIFT
107973. BIF_CFG_DEV0_EPF0_VF24_REVISION_ID__MINOR_REV_ID_MASK
107974. BIF_CFG_DEV0_EPF0_VF24_REVISION_ID__MINOR_REV_ID__SHIFT
107975. BIF_CFG_DEV0_EPF0_VF24_ROM_BASE_ADDR__BASE_ADDR_MASK
107976. BIF_CFG_DEV0_EPF0_VF24_ROM_BASE_ADDR__BASE_ADDR__SHIFT
107977. BIF_CFG_DEV0_EPF0_VF24_STATUS__CAP_LIST_MASK
107978. BIF_CFG_DEV0_EPF0_VF24_STATUS__CAP_LIST__SHIFT
107979. BIF_CFG_DEV0_EPF0_VF24_STATUS__DEVSEL_TIMING_MASK
107980. BIF_CFG_DEV0_EPF0_VF24_STATUS__DEVSEL_TIMING__SHIFT
107981. BIF_CFG_DEV0_EPF0_VF24_STATUS__FAST_BACK_CAPABLE_MASK
107982. BIF_CFG_DEV0_EPF0_VF24_STATUS__FAST_BACK_CAPABLE__SHIFT
107983. BIF_CFG_DEV0_EPF0_VF24_STATUS__IMMEDIATE_READINESS_MASK
107984. BIF_CFG_DEV0_EPF0_VF24_STATUS__IMMEDIATE_READINESS__SHIFT
107985. BIF_CFG_DEV0_EPF0_VF24_STATUS__INT_STATUS_MASK
107986. BIF_CFG_DEV0_EPF0_VF24_STATUS__INT_STATUS__SHIFT
107987. BIF_CFG_DEV0_EPF0_VF24_STATUS__MASTER_DATA_PARITY_ERROR_MASK
107988. BIF_CFG_DEV0_EPF0_VF24_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
107989. BIF_CFG_DEV0_EPF0_VF24_STATUS__PARITY_ERROR_DETECTED_MASK
107990. BIF_CFG_DEV0_EPF0_VF24_STATUS__PARITY_ERROR_DETECTED__SHIFT
107991. BIF_CFG_DEV0_EPF0_VF24_STATUS__PCI_66_CAP_MASK
107992. BIF_CFG_DEV0_EPF0_VF24_STATUS__PCI_66_CAP__SHIFT
107993. BIF_CFG_DEV0_EPF0_VF24_STATUS__RECEIVED_MASTER_ABORT_MASK
107994. BIF_CFG_DEV0_EPF0_VF24_STATUS__RECEIVED_MASTER_ABORT__SHIFT
107995. BIF_CFG_DEV0_EPF0_VF24_STATUS__RECEIVED_TARGET_ABORT_MASK
107996. BIF_CFG_DEV0_EPF0_VF24_STATUS__RECEIVED_TARGET_ABORT__SHIFT
107997. BIF_CFG_DEV0_EPF0_VF24_STATUS__SIGNALED_SYSTEM_ERROR_MASK
107998. BIF_CFG_DEV0_EPF0_VF24_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
107999. BIF_CFG_DEV0_EPF0_VF24_STATUS__SIGNAL_TARGET_ABORT_MASK
108000. BIF_CFG_DEV0_EPF0_VF24_STATUS__SIGNAL_TARGET_ABORT__SHIFT
108001. BIF_CFG_DEV0_EPF0_VF24_SUB_CLASS__SUB_CLASS_MASK
108002. BIF_CFG_DEV0_EPF0_VF24_SUB_CLASS__SUB_CLASS__SHIFT
108003. BIF_CFG_DEV0_EPF0_VF24_VENDOR_ID__VENDOR_ID_MASK
108004. BIF_CFG_DEV0_EPF0_VF24_VENDOR_ID__VENDOR_ID__SHIFT
108005. BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
108006. BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
108007. BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
108008. BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
108009. BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1__BASE_ADDR_MASK
108010. BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1__BASE_ADDR__SHIFT
108011. BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2__BASE_ADDR_MASK
108012. BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2__BASE_ADDR__SHIFT
108013. BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3__BASE_ADDR_MASK
108014. BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3__BASE_ADDR__SHIFT
108015. BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4__BASE_ADDR_MASK
108016. BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4__BASE_ADDR__SHIFT
108017. BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5__BASE_ADDR_MASK
108018. BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5__BASE_ADDR__SHIFT
108019. BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6__BASE_ADDR_MASK
108020. BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6__BASE_ADDR__SHIFT
108021. BIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS__BASE_CLASS_MASK
108022. BIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS__BASE_CLASS__SHIFT
108023. BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_CAP_MASK
108024. BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_CAP__SHIFT
108025. BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_COMP_MASK
108026. BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_COMP__SHIFT
108027. BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_STRT_MASK
108028. BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_STRT__SHIFT
108029. BIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
108030. BIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
108031. BIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR__CAP_PTR_MASK
108032. BIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR__CAP_PTR__SHIFT
108033. BIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
108034. BIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
108035. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__AD_STEPPING_MASK
108036. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__AD_STEPPING__SHIFT
108037. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__BUS_MASTER_EN_MASK
108038. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__BUS_MASTER_EN__SHIFT
108039. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__FAST_B2B_EN_MASK
108040. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__FAST_B2B_EN__SHIFT
108041. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__INT_DIS_MASK
108042. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__INT_DIS__SHIFT
108043. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__IO_ACCESS_EN_MASK
108044. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__IO_ACCESS_EN__SHIFT
108045. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__MEM_ACCESS_EN_MASK
108046. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__MEM_ACCESS_EN__SHIFT
108047. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
108048. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
108049. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__PAL_SNOOP_EN_MASK
108050. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__PAL_SNOOP_EN__SHIFT
108051. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
108052. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
108053. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__SERR_EN_MASK
108054. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__SERR_EN__SHIFT
108055. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__SPECIAL_CYCLE_EN_MASK
108056. BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
108057. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
108058. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
108059. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
108060. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
108061. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
108062. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
108063. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
108064. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
108065. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
108066. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
108067. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
108068. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
108069. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
108070. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
108071. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
108072. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
108073. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
108074. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
108075. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
108076. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
108077. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
108078. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
108079. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
108080. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
108081. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
108082. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
108083. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
108084. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
108085. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
108086. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
108087. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
108088. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
108089. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
108090. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
108091. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
108092. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
108093. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
108094. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
108095. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
108096. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
108097. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
108098. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
108099. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
108100. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
108101. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__EXTENDED_TAG_MASK
108102. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
108103. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__FLR_CAPABLE_MASK
108104. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
108105. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
108106. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
108107. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
108108. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
108109. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
108110. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
108111. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__PHANTOM_FUNC_MASK
108112. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
108113. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
108114. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
108115. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
108116. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
108117. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
108118. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
108119. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
108120. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
108121. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
108122. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
108123. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
108124. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
108125. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
108126. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
108127. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
108128. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
108129. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
108130. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
108131. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
108132. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
108133. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__LTR_EN_MASK
108134. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__LTR_EN__SHIFT
108135. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__OBFF_EN_MASK
108136. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__OBFF_EN__SHIFT
108137. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
108138. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
108139. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
108140. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
108141. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__CORR_ERR_EN_MASK
108142. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
108143. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
108144. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
108145. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
108146. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
108147. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__INITIATE_FLR_MASK
108148. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
108149. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
108150. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
108151. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
108152. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
108153. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
108154. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
108155. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
108156. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
108157. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
108158. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
108159. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
108160. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
108161. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__USR_REPORT_EN_MASK
108162. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
108163. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID__DEVICE_ID_MASK
108164. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID__DEVICE_ID__SHIFT
108165. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2__RESERVED_MASK
108166. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2__RESERVED__SHIFT
108167. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__AUX_PWR_MASK
108168. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__AUX_PWR__SHIFT
108169. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__CORR_ERR_MASK
108170. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__CORR_ERR__SHIFT
108171. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
108172. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
108173. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__FATAL_ERR_MASK
108174. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__FATAL_ERR__SHIFT
108175. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
108176. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
108177. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
108178. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
108179. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__USR_DETECTED_MASK
108180. BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__USR_DETECTED__SHIFT
108181. BIF_CFG_DEV0_EPF0_VF25_0_HEADER__DEVICE_TYPE_MASK
108182. BIF_CFG_DEV0_EPF0_VF25_0_HEADER__DEVICE_TYPE__SHIFT
108183. BIF_CFG_DEV0_EPF0_VF25_0_HEADER__HEADER_TYPE_MASK
108184. BIF_CFG_DEV0_EPF0_VF25_0_HEADER__HEADER_TYPE__SHIFT
108185. BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
108186. BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
108187. BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
108188. BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
108189. BIF_CFG_DEV0_EPF0_VF25_0_LATENCY__LATENCY_TIMER_MASK
108190. BIF_CFG_DEV0_EPF0_VF25_0_LATENCY__LATENCY_TIMER__SHIFT
108191. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
108192. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
108193. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
108194. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
108195. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
108196. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
108197. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
108198. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
108199. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
108200. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
108201. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
108202. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
108203. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
108204. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
108205. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
108206. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
108207. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
108208. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
108209. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
108210. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
108211. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
108212. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
108213. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__L1_EXIT_LATENCY_MASK
108214. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
108215. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
108216. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
108217. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_SPEED_MASK
108218. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_SPEED__SHIFT
108219. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_WIDTH_MASK
108220. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_WIDTH__SHIFT
108221. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__PM_SUPPORT_MASK
108222. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__PM_SUPPORT__SHIFT
108223. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__PORT_NUMBER_MASK
108224. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__PORT_NUMBER__SHIFT
108225. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
108226. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
108227. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
108228. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
108229. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
108230. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
108231. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
108232. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
108233. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
108234. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
108235. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
108236. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
108237. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
108238. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
108239. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
108240. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
108241. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__XMIT_MARGIN_MASK
108242. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
108243. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
108244. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
108245. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
108246. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
108247. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
108248. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
108249. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__EXTENDED_SYNC_MASK
108250. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
108251. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
108252. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
108253. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
108254. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
108255. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
108256. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
108257. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_DIS_MASK
108258. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_DIS__SHIFT
108259. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__PM_CONTROL_MASK
108260. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__PM_CONTROL__SHIFT
108261. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
108262. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
108263. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__RETRAIN_LINK_MASK
108264. BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__RETRAIN_LINK__SHIFT
108265. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
108266. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
108267. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
108268. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
108269. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
108270. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
108271. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
108272. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
108273. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
108274. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
108275. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
108276. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
108277. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
108278. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
108279. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
108280. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
108281. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
108282. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
108283. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
108284. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
108285. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
108286. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
108287. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
108288. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
108289. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__DL_ACTIVE_MASK
108290. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__DL_ACTIVE__SHIFT
108291. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
108292. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
108293. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
108294. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
108295. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_TRAINING_MASK
108296. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_TRAINING__SHIFT
108297. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
108298. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
108299. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
108300. BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
108301. BIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY__MAX_LAT_MASK
108302. BIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY__MAX_LAT__SHIFT
108303. BIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT__MIN_GNT_MASK
108304. BIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT__MIN_GNT__SHIFT
108305. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST__CAP_ID_MASK
108306. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST__CAP_ID__SHIFT
108307. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST__NEXT_PTR_MASK
108308. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
108309. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_EN_MASK
108310. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
108311. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
108312. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
108313. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
108314. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
108315. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA__MSIX_PBA_BIR_MASK
108316. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
108317. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
108318. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
108319. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
108320. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
108321. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
108322. BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
108323. BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST__CAP_ID_MASK
108324. BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST__CAP_ID__SHIFT
108325. BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST__NEXT_PTR_MASK
108326. BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
108327. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64__MSI_MASK_64_MASK
108328. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64__MSI_MASK_64__SHIFT
108329. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK__MSI_MASK_MASK
108330. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK__MSI_MASK__SHIFT
108331. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
108332. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
108333. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
108334. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
108335. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_64BIT_MASK
108336. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
108337. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_EN_MASK
108338. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_EN__SHIFT
108339. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
108340. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
108341. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
108342. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
108343. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
108344. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
108345. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
108346. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
108347. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA__MSI_DATA_MASK
108348. BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA__MSI_DATA__SHIFT
108349. BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64__MSI_PENDING_64_MASK
108350. BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
108351. BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING__MSI_PENDING_MASK
108352. BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING__MSI_PENDING__SHIFT
108353. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
108354. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
108355. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
108356. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
108357. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
108358. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
108359. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
108360. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
108361. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
108362. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
108363. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
108364. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
108365. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
108366. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
108367. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
108368. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
108369. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
108370. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
108371. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
108372. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
108373. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
108374. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
108375. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
108376. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
108377. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
108378. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
108379. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
108380. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
108381. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
108382. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
108383. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
108384. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
108385. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
108386. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
108387. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
108388. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
108389. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
108390. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
108391. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
108392. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
108393. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
108394. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
108395. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
108396. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
108397. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
108398. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
108399. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
108400. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
108401. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
108402. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
108403. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL__STU_MASK
108404. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL__STU__SHIFT
108405. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
108406. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
108407. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
108408. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
108409. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
108410. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
108411. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST__CAP_ID_MASK
108412. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST__CAP_ID__SHIFT
108413. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST__NEXT_PTR_MASK
108414. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
108415. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__DEVICE_TYPE_MASK
108416. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__DEVICE_TYPE__SHIFT
108417. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
108418. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
108419. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
108420. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
108421. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__VERSION_MASK
108422. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__VERSION__SHIFT
108423. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
108424. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
108425. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
108426. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
108427. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
108428. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
108429. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
108430. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
108431. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
108432. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
108433. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
108434. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
108435. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
108436. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
108437. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
108438. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
108439. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
108440. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
108441. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
108442. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
108443. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
108444. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
108445. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
108446. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
108447. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
108448. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
108449. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
108450. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
108451. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
108452. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
108453. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
108454. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
108455. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0__TLP_HDR_MASK
108456. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
108457. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1__TLP_HDR_MASK
108458. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
108459. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2__TLP_HDR_MASK
108460. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
108461. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3__TLP_HDR_MASK
108462. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
108463. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
108464. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
108465. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
108466. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
108467. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
108468. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
108469. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
108470. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
108471. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
108472. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
108473. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
108474. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
108475. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
108476. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
108477. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
108478. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
108479. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
108480. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
108481. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
108482. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
108483. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
108484. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
108485. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
108486. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
108487. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
108488. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
108489. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
108490. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
108491. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
108492. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
108493. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
108494. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
108495. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
108496. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
108497. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
108498. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
108499. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
108500. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
108501. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
108502. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
108503. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
108504. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
108505. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
108506. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
108507. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
108508. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
108509. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
108510. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
108511. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
108512. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
108513. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
108514. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
108515. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
108516. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
108517. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
108518. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
108519. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
108520. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
108521. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
108522. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
108523. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
108524. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
108525. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
108526. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
108527. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
108528. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
108529. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
108530. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
108531. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
108532. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
108533. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
108534. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
108535. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
108536. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
108537. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
108538. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
108539. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
108540. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
108541. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
108542. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
108543. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
108544. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
108545. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
108546. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
108547. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
108548. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
108549. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
108550. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
108551. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
108552. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
108553. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
108554. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
108555. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
108556. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
108557. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
108558. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
108559. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
108560. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
108561. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
108562. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
108563. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
108564. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
108565. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
108566. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
108567. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
108568. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
108569. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
108570. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
108571. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
108572. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
108573. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
108574. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
108575. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
108576. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
108577. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
108578. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
108579. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
108580. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
108581. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
108582. BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
108583. BIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE__PROG_INTERFACE_MASK
108584. BIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
108585. BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID__MAJOR_REV_ID_MASK
108586. BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID__MAJOR_REV_ID__SHIFT
108587. BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID__MINOR_REV_ID_MASK
108588. BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID__MINOR_REV_ID__SHIFT
108589. BIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR__BASE_ADDR_MASK
108590. BIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
108591. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__CAP_LIST_MASK
108592. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__CAP_LIST__SHIFT
108593. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__DEVSEL_TIMING_MASK
108594. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__DEVSEL_TIMING__SHIFT
108595. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__FAST_BACK_CAPABLE_MASK
108596. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__FAST_BACK_CAPABLE__SHIFT
108597. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__IMMEDIATE_READINESS_MASK
108598. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__IMMEDIATE_READINESS__SHIFT
108599. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__INT_STATUS_MASK
108600. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__INT_STATUS__SHIFT
108601. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
108602. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
108603. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__PARITY_ERROR_DETECTED_MASK
108604. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
108605. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__PCI_66_CAP_MASK
108606. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__PCI_66_CAP__SHIFT
108607. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__RECEIVED_MASTER_ABORT_MASK
108608. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
108609. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__RECEIVED_TARGET_ABORT_MASK
108610. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
108611. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
108612. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
108613. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__SIGNAL_TARGET_ABORT_MASK
108614. BIF_CFG_DEV0_EPF0_VF25_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
108615. BIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS__SUB_CLASS_MASK
108616. BIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS__SUB_CLASS__SHIFT
108617. BIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID__VENDOR_ID_MASK
108618. BIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID__VENDOR_ID__SHIFT
108619. BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
108620. BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
108621. BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
108622. BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
108623. BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1__BASE_ADDR_MASK
108624. BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1__BASE_ADDR__SHIFT
108625. BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2__BASE_ADDR_MASK
108626. BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2__BASE_ADDR__SHIFT
108627. BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3__BASE_ADDR_MASK
108628. BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3__BASE_ADDR__SHIFT
108629. BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4__BASE_ADDR_MASK
108630. BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4__BASE_ADDR__SHIFT
108631. BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5__BASE_ADDR_MASK
108632. BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5__BASE_ADDR__SHIFT
108633. BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6__BASE_ADDR_MASK
108634. BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6__BASE_ADDR__SHIFT
108635. BIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS__BASE_CLASS_MASK
108636. BIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS__BASE_CLASS__SHIFT
108637. BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_CAP_MASK
108638. BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_CAP__SHIFT
108639. BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_COMP_MASK
108640. BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_COMP__SHIFT
108641. BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_STRT_MASK
108642. BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_STRT__SHIFT
108643. BIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
108644. BIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
108645. BIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR__CAP_PTR_MASK
108646. BIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR__CAP_PTR__SHIFT
108647. BIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
108648. BIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
108649. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__AD_STEPPING_MASK
108650. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__AD_STEPPING__SHIFT
108651. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__BUS_MASTER_EN_MASK
108652. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__BUS_MASTER_EN__SHIFT
108653. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__FAST_B2B_EN_MASK
108654. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__FAST_B2B_EN__SHIFT
108655. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__INT_DIS_MASK
108656. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__INT_DIS__SHIFT
108657. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__IO_ACCESS_EN_MASK
108658. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__IO_ACCESS_EN__SHIFT
108659. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__MEM_ACCESS_EN_MASK
108660. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__MEM_ACCESS_EN__SHIFT
108661. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
108662. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
108663. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__PAL_SNOOP_EN_MASK
108664. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__PAL_SNOOP_EN__SHIFT
108665. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
108666. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
108667. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__SERR_EN_MASK
108668. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__SERR_EN__SHIFT
108669. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__SPECIAL_CYCLE_EN_MASK
108670. BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
108671. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
108672. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
108673. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
108674. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
108675. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
108676. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
108677. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
108678. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
108679. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
108680. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
108681. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
108682. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
108683. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
108684. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
108685. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
108686. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
108687. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
108688. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
108689. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
108690. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
108691. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
108692. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
108693. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
108694. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
108695. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
108696. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
108697. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
108698. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
108699. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
108700. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
108701. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
108702. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
108703. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
108704. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
108705. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
108706. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
108707. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
108708. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
108709. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
108710. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
108711. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
108712. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
108713. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
108714. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
108715. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__EXTENDED_TAG_MASK
108716. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
108717. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__FLR_CAPABLE_MASK
108718. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
108719. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
108720. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
108721. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
108722. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
108723. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
108724. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
108725. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__PHANTOM_FUNC_MASK
108726. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
108727. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
108728. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
108729. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
108730. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
108731. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
108732. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
108733. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
108734. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
108735. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
108736. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
108737. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
108738. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
108739. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
108740. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
108741. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
108742. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
108743. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
108744. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
108745. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
108746. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
108747. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__LTR_EN_MASK
108748. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__LTR_EN__SHIFT
108749. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__OBFF_EN_MASK
108750. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__OBFF_EN__SHIFT
108751. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
108752. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
108753. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
108754. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
108755. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__CORR_ERR_EN_MASK
108756. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
108757. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
108758. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
108759. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
108760. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
108761. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__INITIATE_FLR_MASK
108762. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
108763. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
108764. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
108765. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
108766. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
108767. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
108768. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
108769. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
108770. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
108771. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
108772. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
108773. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
108774. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
108775. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__USR_REPORT_EN_MASK
108776. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
108777. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID__DEVICE_ID_MASK
108778. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID__DEVICE_ID__SHIFT
108779. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2__RESERVED_MASK
108780. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2__RESERVED__SHIFT
108781. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__AUX_PWR_MASK
108782. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__AUX_PWR__SHIFT
108783. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__CORR_ERR_MASK
108784. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__CORR_ERR__SHIFT
108785. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
108786. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
108787. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__FATAL_ERR_MASK
108788. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__FATAL_ERR__SHIFT
108789. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
108790. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
108791. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
108792. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
108793. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__USR_DETECTED_MASK
108794. BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__USR_DETECTED__SHIFT
108795. BIF_CFG_DEV0_EPF0_VF25_1_HEADER__DEVICE_TYPE_MASK
108796. BIF_CFG_DEV0_EPF0_VF25_1_HEADER__DEVICE_TYPE__SHIFT
108797. BIF_CFG_DEV0_EPF0_VF25_1_HEADER__HEADER_TYPE_MASK
108798. BIF_CFG_DEV0_EPF0_VF25_1_HEADER__HEADER_TYPE__SHIFT
108799. BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
108800. BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
108801. BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
108802. BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
108803. BIF_CFG_DEV0_EPF0_VF25_1_LATENCY__LATENCY_TIMER_MASK
108804. BIF_CFG_DEV0_EPF0_VF25_1_LATENCY__LATENCY_TIMER__SHIFT
108805. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
108806. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
108807. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
108808. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
108809. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
108810. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
108811. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
108812. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
108813. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
108814. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
108815. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
108816. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
108817. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
108818. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
108819. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
108820. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
108821. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
108822. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
108823. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
108824. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
108825. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
108826. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
108827. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__L1_EXIT_LATENCY_MASK
108828. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
108829. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
108830. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
108831. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_SPEED_MASK
108832. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_SPEED__SHIFT
108833. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_WIDTH_MASK
108834. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_WIDTH__SHIFT
108835. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__PM_SUPPORT_MASK
108836. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__PM_SUPPORT__SHIFT
108837. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__PORT_NUMBER_MASK
108838. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__PORT_NUMBER__SHIFT
108839. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
108840. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
108841. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
108842. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
108843. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
108844. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
108845. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
108846. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
108847. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
108848. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
108849. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
108850. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
108851. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
108852. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
108853. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
108854. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
108855. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__XMIT_MARGIN_MASK
108856. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
108857. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
108858. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
108859. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
108860. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
108861. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
108862. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
108863. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__EXTENDED_SYNC_MASK
108864. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
108865. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
108866. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
108867. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
108868. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
108869. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
108870. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
108871. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_DIS_MASK
108872. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_DIS__SHIFT
108873. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__PM_CONTROL_MASK
108874. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__PM_CONTROL__SHIFT
108875. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
108876. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
108877. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__RETRAIN_LINK_MASK
108878. BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__RETRAIN_LINK__SHIFT
108879. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
108880. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
108881. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
108882. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
108883. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
108884. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
108885. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
108886. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
108887. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
108888. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
108889. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
108890. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
108891. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
108892. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
108893. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
108894. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
108895. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
108896. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
108897. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
108898. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
108899. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
108900. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
108901. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
108902. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
108903. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__DL_ACTIVE_MASK
108904. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__DL_ACTIVE__SHIFT
108905. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
108906. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
108907. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
108908. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
108909. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_TRAINING_MASK
108910. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_TRAINING__SHIFT
108911. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
108912. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
108913. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
108914. BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
108915. BIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY__MAX_LAT_MASK
108916. BIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY__MAX_LAT__SHIFT
108917. BIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT__MIN_GNT_MASK
108918. BIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT__MIN_GNT__SHIFT
108919. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST__CAP_ID_MASK
108920. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST__CAP_ID__SHIFT
108921. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST__NEXT_PTR_MASK
108922. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
108923. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_EN_MASK
108924. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
108925. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
108926. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
108927. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
108928. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
108929. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA__MSIX_PBA_BIR_MASK
108930. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
108931. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
108932. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
108933. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
108934. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
108935. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
108936. BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
108937. BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST__CAP_ID_MASK
108938. BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST__CAP_ID__SHIFT
108939. BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST__NEXT_PTR_MASK
108940. BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
108941. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64__MSI_MASK_64_MASK
108942. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64__MSI_MASK_64__SHIFT
108943. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK__MSI_MASK_MASK
108944. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK__MSI_MASK__SHIFT
108945. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
108946. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
108947. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
108948. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
108949. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_64BIT_MASK
108950. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
108951. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_EN_MASK
108952. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_EN__SHIFT
108953. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
108954. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
108955. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
108956. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
108957. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
108958. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
108959. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
108960. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
108961. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA__MSI_DATA_MASK
108962. BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA__MSI_DATA__SHIFT
108963. BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64__MSI_PENDING_64_MASK
108964. BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
108965. BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING__MSI_PENDING_MASK
108966. BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING__MSI_PENDING__SHIFT
108967. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
108968. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
108969. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
108970. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
108971. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
108972. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
108973. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
108974. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
108975. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
108976. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
108977. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
108978. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
108979. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
108980. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
108981. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
108982. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
108983. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
108984. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
108985. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
108986. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
108987. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
108988. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
108989. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
108990. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
108991. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
108992. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
108993. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
108994. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
108995. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
108996. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
108997. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
108998. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
108999. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
109000. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
109001. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
109002. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
109003. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
109004. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
109005. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
109006. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
109007. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
109008. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
109009. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
109010. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
109011. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
109012. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
109013. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
109014. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
109015. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
109016. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
109017. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL__STU_MASK
109018. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL__STU__SHIFT
109019. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
109020. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
109021. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
109022. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
109023. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
109024. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
109025. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST__CAP_ID_MASK
109026. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST__CAP_ID__SHIFT
109027. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST__NEXT_PTR_MASK
109028. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
109029. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__DEVICE_TYPE_MASK
109030. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__DEVICE_TYPE__SHIFT
109031. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
109032. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
109033. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
109034. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
109035. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__VERSION_MASK
109036. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__VERSION__SHIFT
109037. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
109038. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
109039. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
109040. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
109041. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
109042. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
109043. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
109044. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
109045. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
109046. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
109047. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
109048. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
109049. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
109050. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
109051. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
109052. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
109053. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
109054. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
109055. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
109056. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
109057. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
109058. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
109059. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
109060. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
109061. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
109062. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
109063. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
109064. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
109065. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
109066. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
109067. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
109068. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
109069. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0__TLP_HDR_MASK
109070. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
109071. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1__TLP_HDR_MASK
109072. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
109073. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2__TLP_HDR_MASK
109074. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
109075. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3__TLP_HDR_MASK
109076. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
109077. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
109078. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
109079. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
109080. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
109081. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
109082. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
109083. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
109084. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
109085. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
109086. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
109087. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
109088. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
109089. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
109090. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
109091. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
109092. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
109093. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
109094. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
109095. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
109096. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
109097. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
109098. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
109099. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
109100. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
109101. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
109102. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
109103. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
109104. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
109105. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
109106. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
109107. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
109108. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
109109. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
109110. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
109111. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
109112. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
109113. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
109114. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
109115. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
109116. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
109117. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
109118. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
109119. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
109120. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
109121. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
109122. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
109123. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
109124. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
109125. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
109126. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
109127. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
109128. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
109129. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
109130. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
109131. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
109132. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
109133. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
109134. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
109135. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
109136. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
109137. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
109138. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
109139. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
109140. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
109141. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
109142. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
109143. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
109144. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
109145. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
109146. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
109147. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
109148. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
109149. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
109150. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
109151. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
109152. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
109153. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
109154. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
109155. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
109156. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
109157. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
109158. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
109159. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
109160. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
109161. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
109162. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
109163. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
109164. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
109165. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
109166. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
109167. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
109168. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
109169. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
109170. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
109171. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
109172. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
109173. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
109174. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
109175. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
109176. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
109177. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
109178. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
109179. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
109180. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
109181. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
109182. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
109183. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
109184. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
109185. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
109186. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
109187. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
109188. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
109189. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
109190. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
109191. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
109192. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
109193. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
109194. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
109195. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
109196. BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
109197. BIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE__PROG_INTERFACE_MASK
109198. BIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
109199. BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID__MAJOR_REV_ID_MASK
109200. BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID__MAJOR_REV_ID__SHIFT
109201. BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID__MINOR_REV_ID_MASK
109202. BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID__MINOR_REV_ID__SHIFT
109203. BIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR__BASE_ADDR_MASK
109204. BIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
109205. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__CAP_LIST_MASK
109206. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__CAP_LIST__SHIFT
109207. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__DEVSEL_TIMING_MASK
109208. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__DEVSEL_TIMING__SHIFT
109209. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__FAST_BACK_CAPABLE_MASK
109210. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__FAST_BACK_CAPABLE__SHIFT
109211. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__IMMEDIATE_READINESS_MASK
109212. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__IMMEDIATE_READINESS__SHIFT
109213. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__INT_STATUS_MASK
109214. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__INT_STATUS__SHIFT
109215. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
109216. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
109217. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__PARITY_ERROR_DETECTED_MASK
109218. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
109219. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__PCI_66_CAP_MASK
109220. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__PCI_66_CAP__SHIFT
109221. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__RECEIVED_MASTER_ABORT_MASK
109222. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
109223. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__RECEIVED_TARGET_ABORT_MASK
109224. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
109225. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
109226. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
109227. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__SIGNAL_TARGET_ABORT_MASK
109228. BIF_CFG_DEV0_EPF0_VF25_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
109229. BIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS__SUB_CLASS_MASK
109230. BIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS__SUB_CLASS__SHIFT
109231. BIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID__VENDOR_ID_MASK
109232. BIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID__VENDOR_ID__SHIFT
109233. BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID__SUBSYSTEM_ID_MASK
109234. BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
109235. BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
109236. BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
109237. BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_1__BASE_ADDR_MASK
109238. BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_1__BASE_ADDR__SHIFT
109239. BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_2__BASE_ADDR_MASK
109240. BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_2__BASE_ADDR__SHIFT
109241. BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_3__BASE_ADDR_MASK
109242. BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_3__BASE_ADDR__SHIFT
109243. BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_4__BASE_ADDR_MASK
109244. BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_4__BASE_ADDR__SHIFT
109245. BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_5__BASE_ADDR_MASK
109246. BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_5__BASE_ADDR__SHIFT
109247. BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_6__BASE_ADDR_MASK
109248. BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_6__BASE_ADDR__SHIFT
109249. BIF_CFG_DEV0_EPF0_VF25_BASE_CLASS__BASE_CLASS_MASK
109250. BIF_CFG_DEV0_EPF0_VF25_BASE_CLASS__BASE_CLASS__SHIFT
109251. BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_CAP_MASK
109252. BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_CAP__SHIFT
109253. BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_COMP_MASK
109254. BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_COMP__SHIFT
109255. BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_STRT_MASK
109256. BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_STRT__SHIFT
109257. BIF_CFG_DEV0_EPF0_VF25_CACHE_LINE__CACHE_LINE_SIZE_MASK
109258. BIF_CFG_DEV0_EPF0_VF25_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
109259. BIF_CFG_DEV0_EPF0_VF25_CAP_PTR__CAP_PTR_MASK
109260. BIF_CFG_DEV0_EPF0_VF25_CAP_PTR__CAP_PTR__SHIFT
109261. BIF_CFG_DEV0_EPF0_VF25_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
109262. BIF_CFG_DEV0_EPF0_VF25_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
109263. BIF_CFG_DEV0_EPF0_VF25_COMMAND__AD_STEPPING_MASK
109264. BIF_CFG_DEV0_EPF0_VF25_COMMAND__AD_STEPPING__SHIFT
109265. BIF_CFG_DEV0_EPF0_VF25_COMMAND__BUS_MASTER_EN_MASK
109266. BIF_CFG_DEV0_EPF0_VF25_COMMAND__BUS_MASTER_EN__SHIFT
109267. BIF_CFG_DEV0_EPF0_VF25_COMMAND__FAST_B2B_EN_MASK
109268. BIF_CFG_DEV0_EPF0_VF25_COMMAND__FAST_B2B_EN__SHIFT
109269. BIF_CFG_DEV0_EPF0_VF25_COMMAND__INT_DIS_MASK
109270. BIF_CFG_DEV0_EPF0_VF25_COMMAND__INT_DIS__SHIFT
109271. BIF_CFG_DEV0_EPF0_VF25_COMMAND__IO_ACCESS_EN_MASK
109272. BIF_CFG_DEV0_EPF0_VF25_COMMAND__IO_ACCESS_EN__SHIFT
109273. BIF_CFG_DEV0_EPF0_VF25_COMMAND__MEM_ACCESS_EN_MASK
109274. BIF_CFG_DEV0_EPF0_VF25_COMMAND__MEM_ACCESS_EN__SHIFT
109275. BIF_CFG_DEV0_EPF0_VF25_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
109276. BIF_CFG_DEV0_EPF0_VF25_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
109277. BIF_CFG_DEV0_EPF0_VF25_COMMAND__PAL_SNOOP_EN_MASK
109278. BIF_CFG_DEV0_EPF0_VF25_COMMAND__PAL_SNOOP_EN__SHIFT
109279. BIF_CFG_DEV0_EPF0_VF25_COMMAND__PARITY_ERROR_RESPONSE_MASK
109280. BIF_CFG_DEV0_EPF0_VF25_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
109281. BIF_CFG_DEV0_EPF0_VF25_COMMAND__SERR_EN_MASK
109282. BIF_CFG_DEV0_EPF0_VF25_COMMAND__SERR_EN__SHIFT
109283. BIF_CFG_DEV0_EPF0_VF25_COMMAND__SPECIAL_CYCLE_EN_MASK
109284. BIF_CFG_DEV0_EPF0_VF25_COMMAND__SPECIAL_CYCLE_EN__SHIFT
109285. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
109286. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
109287. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
109288. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
109289. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
109290. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
109291. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
109292. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
109293. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
109294. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
109295. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
109296. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
109297. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
109298. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
109299. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
109300. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
109301. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
109302. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
109303. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
109304. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
109305. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
109306. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
109307. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__FRS_SUPPORTED_MASK
109308. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
109309. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
109310. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
109311. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__LTR_SUPPORTED_MASK
109312. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
109313. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
109314. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
109315. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
109316. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
109317. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__OBFF_SUPPORTED_MASK
109318. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
109319. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
109320. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
109321. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
109322. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
109323. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
109324. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
109325. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
109326. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
109327. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
109328. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
109329. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__EXTENDED_TAG_MASK
109330. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__EXTENDED_TAG__SHIFT
109331. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__FLR_CAPABLE_MASK
109332. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__FLR_CAPABLE__SHIFT
109333. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
109334. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
109335. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
109336. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
109337. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
109338. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
109339. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__PHANTOM_FUNC_MASK
109340. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__PHANTOM_FUNC__SHIFT
109341. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
109342. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
109343. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
109344. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
109345. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
109346. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
109347. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
109348. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
109349. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
109350. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
109351. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
109352. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
109353. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
109354. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
109355. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
109356. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
109357. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
109358. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
109359. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
109360. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
109361. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__LTR_EN_MASK
109362. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__LTR_EN__SHIFT
109363. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__OBFF_EN_MASK
109364. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__OBFF_EN__SHIFT
109365. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
109366. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
109367. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
109368. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
109369. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__CORR_ERR_EN_MASK
109370. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__CORR_ERR_EN__SHIFT
109371. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
109372. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
109373. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__FATAL_ERR_EN_MASK
109374. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
109375. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__INITIATE_FLR_MASK
109376. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__INITIATE_FLR__SHIFT
109377. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
109378. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
109379. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
109380. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
109381. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
109382. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
109383. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__NO_SNOOP_EN_MASK
109384. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
109385. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
109386. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
109387. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__RELAXED_ORD_EN_MASK
109388. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
109389. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__USR_REPORT_EN_MASK
109390. BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__USR_REPORT_EN__SHIFT
109391. BIF_CFG_DEV0_EPF0_VF25_DEVICE_ID__DEVICE_ID_MASK
109392. BIF_CFG_DEV0_EPF0_VF25_DEVICE_ID__DEVICE_ID__SHIFT
109393. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS2__RESERVED_MASK
109394. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS2__RESERVED__SHIFT
109395. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__AUX_PWR_MASK
109396. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__AUX_PWR__SHIFT
109397. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__CORR_ERR_MASK
109398. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__CORR_ERR__SHIFT
109399. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
109400. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
109401. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__FATAL_ERR_MASK
109402. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__FATAL_ERR__SHIFT
109403. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__NON_FATAL_ERR_MASK
109404. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
109405. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
109406. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
109407. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__USR_DETECTED_MASK
109408. BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__USR_DETECTED__SHIFT
109409. BIF_CFG_DEV0_EPF0_VF25_HEADER__DEVICE_TYPE_MASK
109410. BIF_CFG_DEV0_EPF0_VF25_HEADER__DEVICE_TYPE__SHIFT
109411. BIF_CFG_DEV0_EPF0_VF25_HEADER__HEADER_TYPE_MASK
109412. BIF_CFG_DEV0_EPF0_VF25_HEADER__HEADER_TYPE__SHIFT
109413. BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_LINE__INTERRUPT_LINE_MASK
109414. BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
109415. BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_PIN__INTERRUPT_PIN_MASK
109416. BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
109417. BIF_CFG_DEV0_EPF0_VF25_LATENCY__LATENCY_TIMER_MASK
109418. BIF_CFG_DEV0_EPF0_VF25_LATENCY__LATENCY_TIMER__SHIFT
109419. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
109420. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
109421. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
109422. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
109423. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
109424. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
109425. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
109426. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
109427. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
109428. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
109429. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
109430. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
109431. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
109432. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
109433. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
109434. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
109435. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
109436. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
109437. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
109438. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
109439. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__L0S_EXIT_LATENCY_MASK
109440. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
109441. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__L1_EXIT_LATENCY_MASK
109442. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__L1_EXIT_LATENCY__SHIFT
109443. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
109444. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
109445. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_SPEED_MASK
109446. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_SPEED__SHIFT
109447. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_WIDTH_MASK
109448. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_WIDTH__SHIFT
109449. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__PM_SUPPORT_MASK
109450. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__PM_SUPPORT__SHIFT
109451. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__PORT_NUMBER_MASK
109452. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__PORT_NUMBER__SHIFT
109453. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
109454. BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
109455. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
109456. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
109457. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__COMPLIANCE_SOS_MASK
109458. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
109459. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__ENTER_COMPLIANCE_MASK
109460. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
109461. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
109462. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
109463. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
109464. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
109465. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
109466. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
109467. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__TARGET_LINK_SPEED_MASK
109468. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
109469. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__XMIT_MARGIN_MASK
109470. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__XMIT_MARGIN__SHIFT
109471. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
109472. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
109473. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__COMMON_CLOCK_CFG_MASK
109474. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
109475. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
109476. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
109477. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__EXTENDED_SYNC_MASK
109478. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__EXTENDED_SYNC__SHIFT
109479. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
109480. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
109481. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
109482. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
109483. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
109484. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
109485. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_DIS_MASK
109486. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_DIS__SHIFT
109487. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__PM_CONTROL_MASK
109488. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__PM_CONTROL__SHIFT
109489. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__READ_CPL_BOUNDARY_MASK
109490. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
109491. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__RETRAIN_LINK_MASK
109492. BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__RETRAIN_LINK__SHIFT
109493. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
109494. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
109495. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
109496. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
109497. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
109498. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
109499. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
109500. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
109501. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
109502. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
109503. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
109504. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
109505. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
109506. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
109507. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
109508. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
109509. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
109510. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
109511. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
109512. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
109513. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
109514. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
109515. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__CURRENT_LINK_SPEED_MASK
109516. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
109517. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__DL_ACTIVE_MASK
109518. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__DL_ACTIVE__SHIFT
109519. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
109520. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
109521. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
109522. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
109523. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_TRAINING_MASK
109524. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_TRAINING__SHIFT
109525. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
109526. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
109527. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__SLOT_CLOCK_CFG_MASK
109528. BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
109529. BIF_CFG_DEV0_EPF0_VF25_MAX_LATENCY__MAX_LAT_MASK
109530. BIF_CFG_DEV0_EPF0_VF25_MAX_LATENCY__MAX_LAT__SHIFT
109531. BIF_CFG_DEV0_EPF0_VF25_MIN_GRANT__MIN_GNT_MASK
109532. BIF_CFG_DEV0_EPF0_VF25_MIN_GRANT__MIN_GNT__SHIFT
109533. BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST__CAP_ID_MASK
109534. BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST__CAP_ID__SHIFT
109535. BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST__NEXT_PTR_MASK
109536. BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST__NEXT_PTR__SHIFT
109537. BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_EN_MASK
109538. BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_EN__SHIFT
109539. BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
109540. BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
109541. BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
109542. BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
109543. BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA__MSIX_PBA_BIR_MASK
109544. BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA__MSIX_PBA_BIR__SHIFT
109545. BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA__MSIX_PBA_OFFSET_MASK
109546. BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
109547. BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE__MSIX_TABLE_BIR_MASK
109548. BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
109549. BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
109550. BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
109551. BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST__CAP_ID_MASK
109552. BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST__CAP_ID__SHIFT
109553. BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST__NEXT_PTR_MASK
109554. BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST__NEXT_PTR__SHIFT
109555. BIF_CFG_DEV0_EPF0_VF25_MSI_MASK_64__MSI_MASK_64_MASK
109556. BIF_CFG_DEV0_EPF0_VF25_MSI_MASK_64__MSI_MASK_64__SHIFT
109557. BIF_CFG_DEV0_EPF0_VF25_MSI_MASK__MSI_MASK_MASK
109558. BIF_CFG_DEV0_EPF0_VF25_MSI_MASK__MSI_MASK__SHIFT
109559. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
109560. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
109561. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
109562. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
109563. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_64BIT_MASK
109564. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_64BIT__SHIFT
109565. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_EN_MASK
109566. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_EN__SHIFT
109567. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
109568. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
109569. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
109570. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
109571. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
109572. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
109573. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA_64__MSI_DATA_64_MASK
109574. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
109575. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA__MSI_DATA_MASK
109576. BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA__MSI_DATA__SHIFT
109577. BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING_64__MSI_PENDING_64_MASK
109578. BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING_64__MSI_PENDING_64__SHIFT
109579. BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING__MSI_PENDING_MASK
109580. BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING__MSI_PENDING__SHIFT
109581. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
109582. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
109583. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
109584. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
109585. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
109586. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
109587. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
109588. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
109589. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
109590. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
109591. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
109592. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
109593. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
109594. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
109595. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
109596. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
109597. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
109598. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
109599. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
109600. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
109601. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
109602. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
109603. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
109604. BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
109605. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
109606. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
109607. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
109608. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
109609. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
109610. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
109611. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
109612. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
109613. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
109614. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
109615. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
109616. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
109617. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
109618. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
109619. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
109620. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
109621. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
109622. BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
109623. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
109624. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
109625. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
109626. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
109627. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
109628. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
109629. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL__ATC_ENABLE_MASK
109630. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
109631. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL__STU_MASK
109632. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL__STU__SHIFT
109633. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
109634. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
109635. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
109636. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
109637. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
109638. BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
109639. BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST__CAP_ID_MASK
109640. BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST__CAP_ID__SHIFT
109641. BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST__NEXT_PTR_MASK
109642. BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST__NEXT_PTR__SHIFT
109643. BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__DEVICE_TYPE_MASK
109644. BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__DEVICE_TYPE__SHIFT
109645. BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__INT_MESSAGE_NUM_MASK
109646. BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
109647. BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__SLOT_IMPLEMENTED_MASK
109648. BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
109649. BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__VERSION_MASK
109650. BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__VERSION__SHIFT
109651. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
109652. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
109653. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
109654. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
109655. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
109656. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
109657. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
109658. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
109659. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
109660. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
109661. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
109662. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
109663. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
109664. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
109665. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
109666. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
109667. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
109668. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
109669. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
109670. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
109671. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
109672. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
109673. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
109674. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
109675. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
109676. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
109677. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
109678. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
109679. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
109680. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
109681. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
109682. BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
109683. BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG0__TLP_HDR_MASK
109684. BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG0__TLP_HDR__SHIFT
109685. BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG1__TLP_HDR_MASK
109686. BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG1__TLP_HDR__SHIFT
109687. BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG2__TLP_HDR_MASK
109688. BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG2__TLP_HDR__SHIFT
109689. BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG3__TLP_HDR_MASK
109690. BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG3__TLP_HDR__SHIFT
109691. BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
109692. BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
109693. BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
109694. BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
109695. BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
109696. BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
109697. BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
109698. BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
109699. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
109700. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
109701. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
109702. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
109703. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
109704. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
109705. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
109706. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
109707. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
109708. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
109709. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
109710. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
109711. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
109712. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
109713. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
109714. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
109715. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
109716. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
109717. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
109718. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
109719. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
109720. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
109721. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
109722. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
109723. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
109724. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
109725. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
109726. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
109727. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
109728. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
109729. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
109730. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
109731. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
109732. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
109733. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
109734. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
109735. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
109736. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
109737. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
109738. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
109739. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
109740. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
109741. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
109742. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
109743. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
109744. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
109745. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
109746. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
109747. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
109748. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
109749. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
109750. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
109751. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
109752. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
109753. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
109754. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
109755. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
109756. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
109757. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
109758. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
109759. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
109760. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
109761. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
109762. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
109763. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
109764. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
109765. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
109766. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
109767. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
109768. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
109769. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
109770. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
109771. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
109772. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
109773. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
109774. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
109775. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
109776. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
109777. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
109778. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
109779. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
109780. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
109781. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
109782. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
109783. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
109784. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
109785. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
109786. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
109787. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
109788. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
109789. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
109790. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
109791. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
109792. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
109793. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
109794. BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
109795. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
109796. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
109797. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
109798. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
109799. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
109800. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
109801. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
109802. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
109803. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
109804. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
109805. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
109806. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
109807. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
109808. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
109809. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
109810. BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
109811. BIF_CFG_DEV0_EPF0_VF25_PROG_INTERFACE__PROG_INTERFACE_MASK
109812. BIF_CFG_DEV0_EPF0_VF25_PROG_INTERFACE__PROG_INTERFACE__SHIFT
109813. BIF_CFG_DEV0_EPF0_VF25_REVISION_ID__MAJOR_REV_ID_MASK
109814. BIF_CFG_DEV0_EPF0_VF25_REVISION_ID__MAJOR_REV_ID__SHIFT
109815. BIF_CFG_DEV0_EPF0_VF25_REVISION_ID__MINOR_REV_ID_MASK
109816. BIF_CFG_DEV0_EPF0_VF25_REVISION_ID__MINOR_REV_ID__SHIFT
109817. BIF_CFG_DEV0_EPF0_VF25_ROM_BASE_ADDR__BASE_ADDR_MASK
109818. BIF_CFG_DEV0_EPF0_VF25_ROM_BASE_ADDR__BASE_ADDR__SHIFT
109819. BIF_CFG_DEV0_EPF0_VF25_STATUS__CAP_LIST_MASK
109820. BIF_CFG_DEV0_EPF0_VF25_STATUS__CAP_LIST__SHIFT
109821. BIF_CFG_DEV0_EPF0_VF25_STATUS__DEVSEL_TIMING_MASK
109822. BIF_CFG_DEV0_EPF0_VF25_STATUS__DEVSEL_TIMING__SHIFT
109823. BIF_CFG_DEV0_EPF0_VF25_STATUS__FAST_BACK_CAPABLE_MASK
109824. BIF_CFG_DEV0_EPF0_VF25_STATUS__FAST_BACK_CAPABLE__SHIFT
109825. BIF_CFG_DEV0_EPF0_VF25_STATUS__IMMEDIATE_READINESS_MASK
109826. BIF_CFG_DEV0_EPF0_VF25_STATUS__IMMEDIATE_READINESS__SHIFT
109827. BIF_CFG_DEV0_EPF0_VF25_STATUS__INT_STATUS_MASK
109828. BIF_CFG_DEV0_EPF0_VF25_STATUS__INT_STATUS__SHIFT
109829. BIF_CFG_DEV0_EPF0_VF25_STATUS__MASTER_DATA_PARITY_ERROR_MASK
109830. BIF_CFG_DEV0_EPF0_VF25_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
109831. BIF_CFG_DEV0_EPF0_VF25_STATUS__PARITY_ERROR_DETECTED_MASK
109832. BIF_CFG_DEV0_EPF0_VF25_STATUS__PARITY_ERROR_DETECTED__SHIFT
109833. BIF_CFG_DEV0_EPF0_VF25_STATUS__PCI_66_CAP_MASK
109834. BIF_CFG_DEV0_EPF0_VF25_STATUS__PCI_66_CAP__SHIFT
109835. BIF_CFG_DEV0_EPF0_VF25_STATUS__RECEIVED_MASTER_ABORT_MASK
109836. BIF_CFG_DEV0_EPF0_VF25_STATUS__RECEIVED_MASTER_ABORT__SHIFT
109837. BIF_CFG_DEV0_EPF0_VF25_STATUS__RECEIVED_TARGET_ABORT_MASK
109838. BIF_CFG_DEV0_EPF0_VF25_STATUS__RECEIVED_TARGET_ABORT__SHIFT
109839. BIF_CFG_DEV0_EPF0_VF25_STATUS__SIGNALED_SYSTEM_ERROR_MASK
109840. BIF_CFG_DEV0_EPF0_VF25_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
109841. BIF_CFG_DEV0_EPF0_VF25_STATUS__SIGNAL_TARGET_ABORT_MASK
109842. BIF_CFG_DEV0_EPF0_VF25_STATUS__SIGNAL_TARGET_ABORT__SHIFT
109843. BIF_CFG_DEV0_EPF0_VF25_SUB_CLASS__SUB_CLASS_MASK
109844. BIF_CFG_DEV0_EPF0_VF25_SUB_CLASS__SUB_CLASS__SHIFT
109845. BIF_CFG_DEV0_EPF0_VF25_VENDOR_ID__VENDOR_ID_MASK
109846. BIF_CFG_DEV0_EPF0_VF25_VENDOR_ID__VENDOR_ID__SHIFT
109847. BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
109848. BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
109849. BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
109850. BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
109851. BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1__BASE_ADDR_MASK
109852. BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1__BASE_ADDR__SHIFT
109853. BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2__BASE_ADDR_MASK
109854. BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2__BASE_ADDR__SHIFT
109855. BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3__BASE_ADDR_MASK
109856. BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3__BASE_ADDR__SHIFT
109857. BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4__BASE_ADDR_MASK
109858. BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4__BASE_ADDR__SHIFT
109859. BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5__BASE_ADDR_MASK
109860. BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5__BASE_ADDR__SHIFT
109861. BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6__BASE_ADDR_MASK
109862. BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6__BASE_ADDR__SHIFT
109863. BIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS__BASE_CLASS_MASK
109864. BIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS__BASE_CLASS__SHIFT
109865. BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_CAP_MASK
109866. BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_CAP__SHIFT
109867. BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_COMP_MASK
109868. BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_COMP__SHIFT
109869. BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_STRT_MASK
109870. BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_STRT__SHIFT
109871. BIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
109872. BIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
109873. BIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR__CAP_PTR_MASK
109874. BIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR__CAP_PTR__SHIFT
109875. BIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
109876. BIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
109877. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__AD_STEPPING_MASK
109878. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__AD_STEPPING__SHIFT
109879. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__BUS_MASTER_EN_MASK
109880. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__BUS_MASTER_EN__SHIFT
109881. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__FAST_B2B_EN_MASK
109882. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__FAST_B2B_EN__SHIFT
109883. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__INT_DIS_MASK
109884. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__INT_DIS__SHIFT
109885. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__IO_ACCESS_EN_MASK
109886. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__IO_ACCESS_EN__SHIFT
109887. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__MEM_ACCESS_EN_MASK
109888. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__MEM_ACCESS_EN__SHIFT
109889. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
109890. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
109891. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__PAL_SNOOP_EN_MASK
109892. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__PAL_SNOOP_EN__SHIFT
109893. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
109894. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
109895. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__SERR_EN_MASK
109896. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__SERR_EN__SHIFT
109897. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__SPECIAL_CYCLE_EN_MASK
109898. BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
109899. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
109900. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
109901. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
109902. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
109903. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
109904. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
109905. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
109906. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
109907. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
109908. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
109909. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
109910. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
109911. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
109912. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
109913. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
109914. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
109915. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
109916. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
109917. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
109918. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
109919. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
109920. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
109921. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
109922. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
109923. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
109924. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
109925. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
109926. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
109927. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
109928. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
109929. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
109930. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
109931. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
109932. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
109933. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
109934. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
109935. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
109936. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
109937. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
109938. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
109939. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
109940. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
109941. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
109942. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
109943. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__EXTENDED_TAG_MASK
109944. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
109945. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__FLR_CAPABLE_MASK
109946. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
109947. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
109948. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
109949. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
109950. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
109951. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
109952. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
109953. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__PHANTOM_FUNC_MASK
109954. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
109955. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
109956. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
109957. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
109958. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
109959. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
109960. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
109961. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
109962. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
109963. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
109964. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
109965. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
109966. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
109967. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
109968. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
109969. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
109970. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
109971. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
109972. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
109973. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
109974. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
109975. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__LTR_EN_MASK
109976. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__LTR_EN__SHIFT
109977. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__OBFF_EN_MASK
109978. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__OBFF_EN__SHIFT
109979. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
109980. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
109981. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
109982. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
109983. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__CORR_ERR_EN_MASK
109984. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
109985. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
109986. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
109987. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
109988. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
109989. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__INITIATE_FLR_MASK
109990. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
109991. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
109992. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
109993. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
109994. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
109995. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
109996. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
109997. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
109998. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
109999. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
110000. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
110001. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
110002. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
110003. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__USR_REPORT_EN_MASK
110004. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
110005. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID__DEVICE_ID_MASK
110006. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID__DEVICE_ID__SHIFT
110007. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2__RESERVED_MASK
110008. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2__RESERVED__SHIFT
110009. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__AUX_PWR_MASK
110010. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__AUX_PWR__SHIFT
110011. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__CORR_ERR_MASK
110012. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__CORR_ERR__SHIFT
110013. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
110014. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
110015. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__FATAL_ERR_MASK
110016. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__FATAL_ERR__SHIFT
110017. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
110018. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
110019. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
110020. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
110021. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__USR_DETECTED_MASK
110022. BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__USR_DETECTED__SHIFT
110023. BIF_CFG_DEV0_EPF0_VF26_0_HEADER__DEVICE_TYPE_MASK
110024. BIF_CFG_DEV0_EPF0_VF26_0_HEADER__DEVICE_TYPE__SHIFT
110025. BIF_CFG_DEV0_EPF0_VF26_0_HEADER__HEADER_TYPE_MASK
110026. BIF_CFG_DEV0_EPF0_VF26_0_HEADER__HEADER_TYPE__SHIFT
110027. BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
110028. BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
110029. BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
110030. BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
110031. BIF_CFG_DEV0_EPF0_VF26_0_LATENCY__LATENCY_TIMER_MASK
110032. BIF_CFG_DEV0_EPF0_VF26_0_LATENCY__LATENCY_TIMER__SHIFT
110033. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
110034. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
110035. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
110036. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
110037. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
110038. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
110039. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
110040. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
110041. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
110042. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
110043. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
110044. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
110045. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
110046. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
110047. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
110048. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
110049. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
110050. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
110051. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
110052. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
110053. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
110054. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
110055. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__L1_EXIT_LATENCY_MASK
110056. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
110057. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
110058. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
110059. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_SPEED_MASK
110060. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_SPEED__SHIFT
110061. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_WIDTH_MASK
110062. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_WIDTH__SHIFT
110063. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__PM_SUPPORT_MASK
110064. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__PM_SUPPORT__SHIFT
110065. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__PORT_NUMBER_MASK
110066. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__PORT_NUMBER__SHIFT
110067. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
110068. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
110069. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
110070. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
110071. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
110072. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
110073. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
110074. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
110075. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
110076. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
110077. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
110078. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
110079. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
110080. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
110081. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
110082. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
110083. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__XMIT_MARGIN_MASK
110084. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
110085. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
110086. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
110087. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
110088. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
110089. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
110090. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
110091. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__EXTENDED_SYNC_MASK
110092. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
110093. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
110094. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
110095. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
110096. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
110097. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
110098. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
110099. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_DIS_MASK
110100. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_DIS__SHIFT
110101. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__PM_CONTROL_MASK
110102. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__PM_CONTROL__SHIFT
110103. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
110104. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
110105. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__RETRAIN_LINK_MASK
110106. BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__RETRAIN_LINK__SHIFT
110107. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
110108. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
110109. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
110110. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
110111. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
110112. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
110113. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
110114. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
110115. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
110116. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
110117. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
110118. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
110119. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
110120. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
110121. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
110122. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
110123. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
110124. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
110125. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
110126. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
110127. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
110128. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
110129. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
110130. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
110131. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__DL_ACTIVE_MASK
110132. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__DL_ACTIVE__SHIFT
110133. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
110134. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
110135. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
110136. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
110137. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_TRAINING_MASK
110138. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_TRAINING__SHIFT
110139. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
110140. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
110141. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
110142. BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
110143. BIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY__MAX_LAT_MASK
110144. BIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY__MAX_LAT__SHIFT
110145. BIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT__MIN_GNT_MASK
110146. BIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT__MIN_GNT__SHIFT
110147. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST__CAP_ID_MASK
110148. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST__CAP_ID__SHIFT
110149. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST__NEXT_PTR_MASK
110150. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
110151. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_EN_MASK
110152. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
110153. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
110154. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
110155. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
110156. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
110157. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA__MSIX_PBA_BIR_MASK
110158. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
110159. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
110160. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
110161. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
110162. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
110163. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
110164. BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
110165. BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST__CAP_ID_MASK
110166. BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST__CAP_ID__SHIFT
110167. BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST__NEXT_PTR_MASK
110168. BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
110169. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64__MSI_MASK_64_MASK
110170. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64__MSI_MASK_64__SHIFT
110171. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK__MSI_MASK_MASK
110172. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK__MSI_MASK__SHIFT
110173. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
110174. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
110175. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
110176. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
110177. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_64BIT_MASK
110178. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
110179. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_EN_MASK
110180. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_EN__SHIFT
110181. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
110182. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
110183. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
110184. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
110185. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
110186. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
110187. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
110188. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
110189. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA__MSI_DATA_MASK
110190. BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA__MSI_DATA__SHIFT
110191. BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64__MSI_PENDING_64_MASK
110192. BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
110193. BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING__MSI_PENDING_MASK
110194. BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING__MSI_PENDING__SHIFT
110195. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
110196. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
110197. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
110198. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
110199. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
110200. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
110201. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
110202. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
110203. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
110204. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
110205. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
110206. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
110207. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
110208. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
110209. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
110210. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
110211. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
110212. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
110213. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
110214. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
110215. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
110216. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
110217. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
110218. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
110219. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
110220. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
110221. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
110222. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
110223. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
110224. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
110225. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
110226. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
110227. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
110228. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
110229. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
110230. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
110231. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
110232. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
110233. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
110234. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
110235. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
110236. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
110237. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
110238. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
110239. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
110240. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
110241. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
110242. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
110243. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
110244. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
110245. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL__STU_MASK
110246. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL__STU__SHIFT
110247. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
110248. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
110249. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
110250. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
110251. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
110252. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
110253. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST__CAP_ID_MASK
110254. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST__CAP_ID__SHIFT
110255. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST__NEXT_PTR_MASK
110256. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
110257. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__DEVICE_TYPE_MASK
110258. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__DEVICE_TYPE__SHIFT
110259. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
110260. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
110261. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
110262. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
110263. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__VERSION_MASK
110264. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__VERSION__SHIFT
110265. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
110266. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
110267. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
110268. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
110269. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
110270. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
110271. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
110272. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
110273. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
110274. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
110275. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
110276. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
110277. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
110278. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
110279. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
110280. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
110281. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
110282. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
110283. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
110284. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
110285. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
110286. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
110287. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
110288. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
110289. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
110290. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
110291. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
110292. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
110293. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
110294. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
110295. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
110296. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
110297. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0__TLP_HDR_MASK
110298. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
110299. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1__TLP_HDR_MASK
110300. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
110301. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2__TLP_HDR_MASK
110302. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
110303. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3__TLP_HDR_MASK
110304. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
110305. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
110306. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
110307. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
110308. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
110309. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
110310. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
110311. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
110312. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
110313. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
110314. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
110315. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
110316. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
110317. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
110318. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
110319. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
110320. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
110321. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
110322. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
110323. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
110324. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
110325. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
110326. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
110327. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
110328. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
110329. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
110330. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
110331. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
110332. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
110333. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
110334. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
110335. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
110336. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
110337. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
110338. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
110339. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
110340. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
110341. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
110342. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
110343. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
110344. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
110345. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
110346. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
110347. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
110348. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
110349. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
110350. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
110351. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
110352. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
110353. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
110354. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
110355. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
110356. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
110357. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
110358. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
110359. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
110360. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
110361. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
110362. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
110363. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
110364. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
110365. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
110366. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
110367. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
110368. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
110369. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
110370. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
110371. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
110372. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
110373. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
110374. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
110375. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
110376. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
110377. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
110378. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
110379. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
110380. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
110381. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
110382. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
110383. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
110384. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
110385. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
110386. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
110387. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
110388. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
110389. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
110390. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
110391. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
110392. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
110393. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
110394. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
110395. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
110396. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
110397. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
110398. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
110399. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
110400. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
110401. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
110402. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
110403. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
110404. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
110405. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
110406. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
110407. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
110408. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
110409. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
110410. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
110411. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
110412. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
110413. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
110414. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
110415. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
110416. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
110417. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
110418. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
110419. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
110420. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
110421. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
110422. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
110423. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
110424. BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
110425. BIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE__PROG_INTERFACE_MASK
110426. BIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
110427. BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID__MAJOR_REV_ID_MASK
110428. BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID__MAJOR_REV_ID__SHIFT
110429. BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID__MINOR_REV_ID_MASK
110430. BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID__MINOR_REV_ID__SHIFT
110431. BIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR__BASE_ADDR_MASK
110432. BIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
110433. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__CAP_LIST_MASK
110434. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__CAP_LIST__SHIFT
110435. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__DEVSEL_TIMING_MASK
110436. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__DEVSEL_TIMING__SHIFT
110437. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__FAST_BACK_CAPABLE_MASK
110438. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__FAST_BACK_CAPABLE__SHIFT
110439. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__IMMEDIATE_READINESS_MASK
110440. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__IMMEDIATE_READINESS__SHIFT
110441. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__INT_STATUS_MASK
110442. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__INT_STATUS__SHIFT
110443. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
110444. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
110445. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__PARITY_ERROR_DETECTED_MASK
110446. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
110447. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__PCI_66_CAP_MASK
110448. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__PCI_66_CAP__SHIFT
110449. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__RECEIVED_MASTER_ABORT_MASK
110450. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
110451. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__RECEIVED_TARGET_ABORT_MASK
110452. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
110453. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
110454. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
110455. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__SIGNAL_TARGET_ABORT_MASK
110456. BIF_CFG_DEV0_EPF0_VF26_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
110457. BIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS__SUB_CLASS_MASK
110458. BIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS__SUB_CLASS__SHIFT
110459. BIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID__VENDOR_ID_MASK
110460. BIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID__VENDOR_ID__SHIFT
110461. BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
110462. BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
110463. BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
110464. BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
110465. BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1__BASE_ADDR_MASK
110466. BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1__BASE_ADDR__SHIFT
110467. BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2__BASE_ADDR_MASK
110468. BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2__BASE_ADDR__SHIFT
110469. BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3__BASE_ADDR_MASK
110470. BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3__BASE_ADDR__SHIFT
110471. BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4__BASE_ADDR_MASK
110472. BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4__BASE_ADDR__SHIFT
110473. BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5__BASE_ADDR_MASK
110474. BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5__BASE_ADDR__SHIFT
110475. BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6__BASE_ADDR_MASK
110476. BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6__BASE_ADDR__SHIFT
110477. BIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS__BASE_CLASS_MASK
110478. BIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS__BASE_CLASS__SHIFT
110479. BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_CAP_MASK
110480. BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_CAP__SHIFT
110481. BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_COMP_MASK
110482. BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_COMP__SHIFT
110483. BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_STRT_MASK
110484. BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_STRT__SHIFT
110485. BIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
110486. BIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
110487. BIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR__CAP_PTR_MASK
110488. BIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR__CAP_PTR__SHIFT
110489. BIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
110490. BIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
110491. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__AD_STEPPING_MASK
110492. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__AD_STEPPING__SHIFT
110493. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__BUS_MASTER_EN_MASK
110494. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__BUS_MASTER_EN__SHIFT
110495. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__FAST_B2B_EN_MASK
110496. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__FAST_B2B_EN__SHIFT
110497. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__INT_DIS_MASK
110498. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__INT_DIS__SHIFT
110499. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__IO_ACCESS_EN_MASK
110500. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__IO_ACCESS_EN__SHIFT
110501. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__MEM_ACCESS_EN_MASK
110502. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__MEM_ACCESS_EN__SHIFT
110503. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
110504. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
110505. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__PAL_SNOOP_EN_MASK
110506. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__PAL_SNOOP_EN__SHIFT
110507. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
110508. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
110509. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__SERR_EN_MASK
110510. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__SERR_EN__SHIFT
110511. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__SPECIAL_CYCLE_EN_MASK
110512. BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
110513. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
110514. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
110515. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
110516. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
110517. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
110518. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
110519. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
110520. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
110521. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
110522. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
110523. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
110524. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
110525. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
110526. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
110527. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
110528. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
110529. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
110530. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
110531. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
110532. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
110533. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
110534. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
110535. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
110536. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
110537. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
110538. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
110539. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
110540. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
110541. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
110542. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
110543. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
110544. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
110545. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
110546. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
110547. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
110548. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
110549. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
110550. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
110551. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
110552. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
110553. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
110554. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
110555. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
110556. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
110557. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__EXTENDED_TAG_MASK
110558. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
110559. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__FLR_CAPABLE_MASK
110560. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
110561. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
110562. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
110563. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
110564. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
110565. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
110566. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
110567. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__PHANTOM_FUNC_MASK
110568. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
110569. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
110570. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
110571. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
110572. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
110573. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
110574. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
110575. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
110576. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
110577. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
110578. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
110579. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
110580. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
110581. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
110582. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
110583. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
110584. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
110585. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
110586. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
110587. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
110588. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
110589. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__LTR_EN_MASK
110590. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__LTR_EN__SHIFT
110591. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__OBFF_EN_MASK
110592. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__OBFF_EN__SHIFT
110593. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
110594. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
110595. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
110596. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
110597. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__CORR_ERR_EN_MASK
110598. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
110599. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
110600. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
110601. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
110602. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
110603. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__INITIATE_FLR_MASK
110604. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
110605. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
110606. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
110607. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
110608. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
110609. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
110610. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
110611. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
110612. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
110613. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
110614. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
110615. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
110616. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
110617. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__USR_REPORT_EN_MASK
110618. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
110619. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID__DEVICE_ID_MASK
110620. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID__DEVICE_ID__SHIFT
110621. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2__RESERVED_MASK
110622. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2__RESERVED__SHIFT
110623. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__AUX_PWR_MASK
110624. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__AUX_PWR__SHIFT
110625. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__CORR_ERR_MASK
110626. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__CORR_ERR__SHIFT
110627. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
110628. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
110629. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__FATAL_ERR_MASK
110630. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__FATAL_ERR__SHIFT
110631. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
110632. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
110633. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
110634. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
110635. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__USR_DETECTED_MASK
110636. BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__USR_DETECTED__SHIFT
110637. BIF_CFG_DEV0_EPF0_VF26_1_HEADER__DEVICE_TYPE_MASK
110638. BIF_CFG_DEV0_EPF0_VF26_1_HEADER__DEVICE_TYPE__SHIFT
110639. BIF_CFG_DEV0_EPF0_VF26_1_HEADER__HEADER_TYPE_MASK
110640. BIF_CFG_DEV0_EPF0_VF26_1_HEADER__HEADER_TYPE__SHIFT
110641. BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
110642. BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
110643. BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
110644. BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
110645. BIF_CFG_DEV0_EPF0_VF26_1_LATENCY__LATENCY_TIMER_MASK
110646. BIF_CFG_DEV0_EPF0_VF26_1_LATENCY__LATENCY_TIMER__SHIFT
110647. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
110648. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
110649. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
110650. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
110651. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
110652. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
110653. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
110654. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
110655. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
110656. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
110657. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
110658. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
110659. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
110660. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
110661. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
110662. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
110663. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
110664. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
110665. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
110666. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
110667. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
110668. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
110669. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__L1_EXIT_LATENCY_MASK
110670. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
110671. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
110672. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
110673. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_SPEED_MASK
110674. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_SPEED__SHIFT
110675. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_WIDTH_MASK
110676. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_WIDTH__SHIFT
110677. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__PM_SUPPORT_MASK
110678. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__PM_SUPPORT__SHIFT
110679. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__PORT_NUMBER_MASK
110680. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__PORT_NUMBER__SHIFT
110681. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
110682. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
110683. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
110684. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
110685. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
110686. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
110687. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
110688. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
110689. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
110690. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
110691. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
110692. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
110693. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
110694. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
110695. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
110696. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
110697. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__XMIT_MARGIN_MASK
110698. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
110699. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
110700. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
110701. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
110702. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
110703. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
110704. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
110705. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__EXTENDED_SYNC_MASK
110706. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
110707. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
110708. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
110709. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
110710. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
110711. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
110712. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
110713. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_DIS_MASK
110714. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_DIS__SHIFT
110715. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__PM_CONTROL_MASK
110716. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__PM_CONTROL__SHIFT
110717. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
110718. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
110719. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__RETRAIN_LINK_MASK
110720. BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__RETRAIN_LINK__SHIFT
110721. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
110722. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
110723. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
110724. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
110725. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
110726. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
110727. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
110728. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
110729. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
110730. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
110731. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
110732. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
110733. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
110734. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
110735. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
110736. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
110737. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
110738. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
110739. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
110740. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
110741. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
110742. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
110743. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
110744. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
110745. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__DL_ACTIVE_MASK
110746. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__DL_ACTIVE__SHIFT
110747. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
110748. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
110749. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
110750. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
110751. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_TRAINING_MASK
110752. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_TRAINING__SHIFT
110753. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
110754. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
110755. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
110756. BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
110757. BIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY__MAX_LAT_MASK
110758. BIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY__MAX_LAT__SHIFT
110759. BIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT__MIN_GNT_MASK
110760. BIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT__MIN_GNT__SHIFT
110761. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST__CAP_ID_MASK
110762. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST__CAP_ID__SHIFT
110763. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST__NEXT_PTR_MASK
110764. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
110765. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_EN_MASK
110766. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
110767. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
110768. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
110769. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
110770. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
110771. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA__MSIX_PBA_BIR_MASK
110772. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
110773. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
110774. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
110775. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
110776. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
110777. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
110778. BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
110779. BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST__CAP_ID_MASK
110780. BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST__CAP_ID__SHIFT
110781. BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST__NEXT_PTR_MASK
110782. BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
110783. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64__MSI_MASK_64_MASK
110784. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64__MSI_MASK_64__SHIFT
110785. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK__MSI_MASK_MASK
110786. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK__MSI_MASK__SHIFT
110787. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
110788. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
110789. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
110790. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
110791. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_64BIT_MASK
110792. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
110793. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_EN_MASK
110794. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_EN__SHIFT
110795. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
110796. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
110797. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
110798. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
110799. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
110800. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
110801. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
110802. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
110803. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA__MSI_DATA_MASK
110804. BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA__MSI_DATA__SHIFT
110805. BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64__MSI_PENDING_64_MASK
110806. BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
110807. BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING__MSI_PENDING_MASK
110808. BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING__MSI_PENDING__SHIFT
110809. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
110810. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
110811. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
110812. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
110813. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
110814. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
110815. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
110816. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
110817. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
110818. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
110819. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
110820. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
110821. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
110822. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
110823. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
110824. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
110825. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
110826. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
110827. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
110828. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
110829. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
110830. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
110831. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
110832. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
110833. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
110834. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
110835. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
110836. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
110837. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
110838. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
110839. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
110840. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
110841. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
110842. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
110843. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
110844. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
110845. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
110846. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
110847. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
110848. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
110849. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
110850. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
110851. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
110852. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
110853. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
110854. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
110855. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
110856. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
110857. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
110858. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
110859. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL__STU_MASK
110860. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL__STU__SHIFT
110861. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
110862. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
110863. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
110864. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
110865. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
110866. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
110867. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST__CAP_ID_MASK
110868. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST__CAP_ID__SHIFT
110869. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST__NEXT_PTR_MASK
110870. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
110871. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__DEVICE_TYPE_MASK
110872. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__DEVICE_TYPE__SHIFT
110873. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
110874. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
110875. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
110876. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
110877. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__VERSION_MASK
110878. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__VERSION__SHIFT
110879. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
110880. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
110881. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
110882. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
110883. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
110884. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
110885. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
110886. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
110887. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
110888. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
110889. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
110890. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
110891. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
110892. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
110893. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
110894. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
110895. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
110896. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
110897. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
110898. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
110899. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
110900. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
110901. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
110902. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
110903. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
110904. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
110905. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
110906. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
110907. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
110908. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
110909. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
110910. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
110911. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0__TLP_HDR_MASK
110912. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
110913. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1__TLP_HDR_MASK
110914. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
110915. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2__TLP_HDR_MASK
110916. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
110917. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3__TLP_HDR_MASK
110918. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
110919. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
110920. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
110921. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
110922. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
110923. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
110924. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
110925. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
110926. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
110927. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
110928. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
110929. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
110930. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
110931. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
110932. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
110933. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
110934. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
110935. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
110936. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
110937. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
110938. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
110939. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
110940. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
110941. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
110942. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
110943. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
110944. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
110945. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
110946. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
110947. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
110948. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
110949. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
110950. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
110951. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
110952. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
110953. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
110954. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
110955. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
110956. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
110957. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
110958. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
110959. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
110960. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
110961. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
110962. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
110963. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
110964. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
110965. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
110966. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
110967. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
110968. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
110969. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
110970. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
110971. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
110972. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
110973. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
110974. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
110975. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
110976. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
110977. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
110978. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
110979. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
110980. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
110981. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
110982. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
110983. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
110984. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
110985. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
110986. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
110987. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
110988. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
110989. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
110990. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
110991. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
110992. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
110993. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
110994. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
110995. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
110996. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
110997. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
110998. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
110999. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
111000. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
111001. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
111002. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
111003. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
111004. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
111005. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
111006. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
111007. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
111008. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
111009. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
111010. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
111011. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
111012. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
111013. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
111014. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
111015. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
111016. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
111017. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
111018. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
111019. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
111020. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
111021. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
111022. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
111023. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
111024. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
111025. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
111026. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
111027. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
111028. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
111029. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
111030. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
111031. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
111032. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
111033. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
111034. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
111035. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
111036. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
111037. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
111038. BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
111039. BIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE__PROG_INTERFACE_MASK
111040. BIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
111041. BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID__MAJOR_REV_ID_MASK
111042. BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID__MAJOR_REV_ID__SHIFT
111043. BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID__MINOR_REV_ID_MASK
111044. BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID__MINOR_REV_ID__SHIFT
111045. BIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR__BASE_ADDR_MASK
111046. BIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
111047. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__CAP_LIST_MASK
111048. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__CAP_LIST__SHIFT
111049. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__DEVSEL_TIMING_MASK
111050. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__DEVSEL_TIMING__SHIFT
111051. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__FAST_BACK_CAPABLE_MASK
111052. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__FAST_BACK_CAPABLE__SHIFT
111053. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__IMMEDIATE_READINESS_MASK
111054. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__IMMEDIATE_READINESS__SHIFT
111055. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__INT_STATUS_MASK
111056. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__INT_STATUS__SHIFT
111057. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
111058. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
111059. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__PARITY_ERROR_DETECTED_MASK
111060. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
111061. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__PCI_66_CAP_MASK
111062. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__PCI_66_CAP__SHIFT
111063. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__RECEIVED_MASTER_ABORT_MASK
111064. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
111065. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__RECEIVED_TARGET_ABORT_MASK
111066. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
111067. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
111068. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
111069. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__SIGNAL_TARGET_ABORT_MASK
111070. BIF_CFG_DEV0_EPF0_VF26_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
111071. BIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS__SUB_CLASS_MASK
111072. BIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS__SUB_CLASS__SHIFT
111073. BIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID__VENDOR_ID_MASK
111074. BIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID__VENDOR_ID__SHIFT
111075. BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID__SUBSYSTEM_ID_MASK
111076. BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
111077. BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
111078. BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
111079. BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_1__BASE_ADDR_MASK
111080. BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_1__BASE_ADDR__SHIFT
111081. BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_2__BASE_ADDR_MASK
111082. BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_2__BASE_ADDR__SHIFT
111083. BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_3__BASE_ADDR_MASK
111084. BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_3__BASE_ADDR__SHIFT
111085. BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_4__BASE_ADDR_MASK
111086. BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_4__BASE_ADDR__SHIFT
111087. BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_5__BASE_ADDR_MASK
111088. BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_5__BASE_ADDR__SHIFT
111089. BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_6__BASE_ADDR_MASK
111090. BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_6__BASE_ADDR__SHIFT
111091. BIF_CFG_DEV0_EPF0_VF26_BASE_CLASS__BASE_CLASS_MASK
111092. BIF_CFG_DEV0_EPF0_VF26_BASE_CLASS__BASE_CLASS__SHIFT
111093. BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_CAP_MASK
111094. BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_CAP__SHIFT
111095. BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_COMP_MASK
111096. BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_COMP__SHIFT
111097. BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_STRT_MASK
111098. BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_STRT__SHIFT
111099. BIF_CFG_DEV0_EPF0_VF26_CACHE_LINE__CACHE_LINE_SIZE_MASK
111100. BIF_CFG_DEV0_EPF0_VF26_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
111101. BIF_CFG_DEV0_EPF0_VF26_CAP_PTR__CAP_PTR_MASK
111102. BIF_CFG_DEV0_EPF0_VF26_CAP_PTR__CAP_PTR__SHIFT
111103. BIF_CFG_DEV0_EPF0_VF26_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
111104. BIF_CFG_DEV0_EPF0_VF26_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
111105. BIF_CFG_DEV0_EPF0_VF26_COMMAND__AD_STEPPING_MASK
111106. BIF_CFG_DEV0_EPF0_VF26_COMMAND__AD_STEPPING__SHIFT
111107. BIF_CFG_DEV0_EPF0_VF26_COMMAND__BUS_MASTER_EN_MASK
111108. BIF_CFG_DEV0_EPF0_VF26_COMMAND__BUS_MASTER_EN__SHIFT
111109. BIF_CFG_DEV0_EPF0_VF26_COMMAND__FAST_B2B_EN_MASK
111110. BIF_CFG_DEV0_EPF0_VF26_COMMAND__FAST_B2B_EN__SHIFT
111111. BIF_CFG_DEV0_EPF0_VF26_COMMAND__INT_DIS_MASK
111112. BIF_CFG_DEV0_EPF0_VF26_COMMAND__INT_DIS__SHIFT
111113. BIF_CFG_DEV0_EPF0_VF26_COMMAND__IO_ACCESS_EN_MASK
111114. BIF_CFG_DEV0_EPF0_VF26_COMMAND__IO_ACCESS_EN__SHIFT
111115. BIF_CFG_DEV0_EPF0_VF26_COMMAND__MEM_ACCESS_EN_MASK
111116. BIF_CFG_DEV0_EPF0_VF26_COMMAND__MEM_ACCESS_EN__SHIFT
111117. BIF_CFG_DEV0_EPF0_VF26_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
111118. BIF_CFG_DEV0_EPF0_VF26_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
111119. BIF_CFG_DEV0_EPF0_VF26_COMMAND__PAL_SNOOP_EN_MASK
111120. BIF_CFG_DEV0_EPF0_VF26_COMMAND__PAL_SNOOP_EN__SHIFT
111121. BIF_CFG_DEV0_EPF0_VF26_COMMAND__PARITY_ERROR_RESPONSE_MASK
111122. BIF_CFG_DEV0_EPF0_VF26_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
111123. BIF_CFG_DEV0_EPF0_VF26_COMMAND__SERR_EN_MASK
111124. BIF_CFG_DEV0_EPF0_VF26_COMMAND__SERR_EN__SHIFT
111125. BIF_CFG_DEV0_EPF0_VF26_COMMAND__SPECIAL_CYCLE_EN_MASK
111126. BIF_CFG_DEV0_EPF0_VF26_COMMAND__SPECIAL_CYCLE_EN__SHIFT
111127. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
111128. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
111129. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
111130. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
111131. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
111132. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
111133. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
111134. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
111135. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
111136. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
111137. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
111138. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
111139. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
111140. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
111141. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
111142. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
111143. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
111144. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
111145. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
111146. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
111147. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
111148. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
111149. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__FRS_SUPPORTED_MASK
111150. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
111151. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
111152. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
111153. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__LTR_SUPPORTED_MASK
111154. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
111155. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
111156. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
111157. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
111158. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
111159. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__OBFF_SUPPORTED_MASK
111160. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
111161. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
111162. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
111163. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
111164. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
111165. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
111166. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
111167. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
111168. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
111169. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
111170. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
111171. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__EXTENDED_TAG_MASK
111172. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__EXTENDED_TAG__SHIFT
111173. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__FLR_CAPABLE_MASK
111174. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__FLR_CAPABLE__SHIFT
111175. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
111176. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
111177. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
111178. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
111179. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
111180. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
111181. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__PHANTOM_FUNC_MASK
111182. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__PHANTOM_FUNC__SHIFT
111183. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
111184. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
111185. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
111186. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
111187. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
111188. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
111189. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
111190. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
111191. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
111192. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
111193. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
111194. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
111195. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
111196. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
111197. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
111198. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
111199. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
111200. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
111201. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
111202. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
111203. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__LTR_EN_MASK
111204. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__LTR_EN__SHIFT
111205. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__OBFF_EN_MASK
111206. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__OBFF_EN__SHIFT
111207. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
111208. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
111209. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
111210. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
111211. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__CORR_ERR_EN_MASK
111212. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__CORR_ERR_EN__SHIFT
111213. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
111214. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
111215. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__FATAL_ERR_EN_MASK
111216. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
111217. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__INITIATE_FLR_MASK
111218. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__INITIATE_FLR__SHIFT
111219. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
111220. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
111221. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
111222. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
111223. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
111224. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
111225. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__NO_SNOOP_EN_MASK
111226. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
111227. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
111228. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
111229. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__RELAXED_ORD_EN_MASK
111230. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
111231. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__USR_REPORT_EN_MASK
111232. BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__USR_REPORT_EN__SHIFT
111233. BIF_CFG_DEV0_EPF0_VF26_DEVICE_ID__DEVICE_ID_MASK
111234. BIF_CFG_DEV0_EPF0_VF26_DEVICE_ID__DEVICE_ID__SHIFT
111235. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS2__RESERVED_MASK
111236. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS2__RESERVED__SHIFT
111237. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__AUX_PWR_MASK
111238. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__AUX_PWR__SHIFT
111239. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__CORR_ERR_MASK
111240. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__CORR_ERR__SHIFT
111241. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
111242. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
111243. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__FATAL_ERR_MASK
111244. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__FATAL_ERR__SHIFT
111245. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__NON_FATAL_ERR_MASK
111246. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
111247. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
111248. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
111249. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__USR_DETECTED_MASK
111250. BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__USR_DETECTED__SHIFT
111251. BIF_CFG_DEV0_EPF0_VF26_HEADER__DEVICE_TYPE_MASK
111252. BIF_CFG_DEV0_EPF0_VF26_HEADER__DEVICE_TYPE__SHIFT
111253. BIF_CFG_DEV0_EPF0_VF26_HEADER__HEADER_TYPE_MASK
111254. BIF_CFG_DEV0_EPF0_VF26_HEADER__HEADER_TYPE__SHIFT
111255. BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_LINE__INTERRUPT_LINE_MASK
111256. BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
111257. BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_PIN__INTERRUPT_PIN_MASK
111258. BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
111259. BIF_CFG_DEV0_EPF0_VF26_LATENCY__LATENCY_TIMER_MASK
111260. BIF_CFG_DEV0_EPF0_VF26_LATENCY__LATENCY_TIMER__SHIFT
111261. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
111262. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
111263. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
111264. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
111265. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
111266. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
111267. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
111268. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
111269. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
111270. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
111271. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
111272. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
111273. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
111274. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
111275. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
111276. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
111277. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
111278. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
111279. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
111280. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
111281. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__L0S_EXIT_LATENCY_MASK
111282. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
111283. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__L1_EXIT_LATENCY_MASK
111284. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__L1_EXIT_LATENCY__SHIFT
111285. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
111286. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
111287. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_SPEED_MASK
111288. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_SPEED__SHIFT
111289. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_WIDTH_MASK
111290. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_WIDTH__SHIFT
111291. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__PM_SUPPORT_MASK
111292. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__PM_SUPPORT__SHIFT
111293. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__PORT_NUMBER_MASK
111294. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__PORT_NUMBER__SHIFT
111295. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
111296. BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
111297. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
111298. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
111299. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__COMPLIANCE_SOS_MASK
111300. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
111301. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__ENTER_COMPLIANCE_MASK
111302. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
111303. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
111304. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
111305. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
111306. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
111307. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
111308. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
111309. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__TARGET_LINK_SPEED_MASK
111310. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
111311. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__XMIT_MARGIN_MASK
111312. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__XMIT_MARGIN__SHIFT
111313. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
111314. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
111315. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__COMMON_CLOCK_CFG_MASK
111316. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
111317. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
111318. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
111319. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__EXTENDED_SYNC_MASK
111320. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__EXTENDED_SYNC__SHIFT
111321. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
111322. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
111323. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
111324. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
111325. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
111326. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
111327. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_DIS_MASK
111328. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_DIS__SHIFT
111329. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__PM_CONTROL_MASK
111330. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__PM_CONTROL__SHIFT
111331. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__READ_CPL_BOUNDARY_MASK
111332. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
111333. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__RETRAIN_LINK_MASK
111334. BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__RETRAIN_LINK__SHIFT
111335. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
111336. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
111337. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
111338. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
111339. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
111340. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
111341. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
111342. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
111343. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
111344. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
111345. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
111346. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
111347. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
111348. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
111349. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
111350. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
111351. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
111352. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
111353. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
111354. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
111355. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
111356. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
111357. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__CURRENT_LINK_SPEED_MASK
111358. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
111359. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__DL_ACTIVE_MASK
111360. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__DL_ACTIVE__SHIFT
111361. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
111362. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
111363. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
111364. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
111365. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_TRAINING_MASK
111366. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_TRAINING__SHIFT
111367. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
111368. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
111369. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__SLOT_CLOCK_CFG_MASK
111370. BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
111371. BIF_CFG_DEV0_EPF0_VF26_MAX_LATENCY__MAX_LAT_MASK
111372. BIF_CFG_DEV0_EPF0_VF26_MAX_LATENCY__MAX_LAT__SHIFT
111373. BIF_CFG_DEV0_EPF0_VF26_MIN_GRANT__MIN_GNT_MASK
111374. BIF_CFG_DEV0_EPF0_VF26_MIN_GRANT__MIN_GNT__SHIFT
111375. BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST__CAP_ID_MASK
111376. BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST__CAP_ID__SHIFT
111377. BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST__NEXT_PTR_MASK
111378. BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST__NEXT_PTR__SHIFT
111379. BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_EN_MASK
111380. BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_EN__SHIFT
111381. BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
111382. BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
111383. BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
111384. BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
111385. BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA__MSIX_PBA_BIR_MASK
111386. BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA__MSIX_PBA_BIR__SHIFT
111387. BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA__MSIX_PBA_OFFSET_MASK
111388. BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
111389. BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE__MSIX_TABLE_BIR_MASK
111390. BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
111391. BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
111392. BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
111393. BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST__CAP_ID_MASK
111394. BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST__CAP_ID__SHIFT
111395. BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST__NEXT_PTR_MASK
111396. BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST__NEXT_PTR__SHIFT
111397. BIF_CFG_DEV0_EPF0_VF26_MSI_MASK_64__MSI_MASK_64_MASK
111398. BIF_CFG_DEV0_EPF0_VF26_MSI_MASK_64__MSI_MASK_64__SHIFT
111399. BIF_CFG_DEV0_EPF0_VF26_MSI_MASK__MSI_MASK_MASK
111400. BIF_CFG_DEV0_EPF0_VF26_MSI_MASK__MSI_MASK__SHIFT
111401. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
111402. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
111403. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
111404. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
111405. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_64BIT_MASK
111406. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_64BIT__SHIFT
111407. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_EN_MASK
111408. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_EN__SHIFT
111409. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
111410. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
111411. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
111412. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
111413. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
111414. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
111415. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA_64__MSI_DATA_64_MASK
111416. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
111417. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA__MSI_DATA_MASK
111418. BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA__MSI_DATA__SHIFT
111419. BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING_64__MSI_PENDING_64_MASK
111420. BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING_64__MSI_PENDING_64__SHIFT
111421. BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING__MSI_PENDING_MASK
111422. BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING__MSI_PENDING__SHIFT
111423. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
111424. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
111425. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
111426. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
111427. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
111428. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
111429. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
111430. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
111431. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
111432. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
111433. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
111434. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
111435. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
111436. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
111437. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
111438. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
111439. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
111440. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
111441. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
111442. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
111443. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
111444. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
111445. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
111446. BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
111447. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
111448. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
111449. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
111450. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
111451. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
111452. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
111453. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
111454. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
111455. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
111456. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
111457. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
111458. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
111459. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
111460. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
111461. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
111462. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
111463. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
111464. BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
111465. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
111466. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
111467. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
111468. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
111469. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
111470. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
111471. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL__ATC_ENABLE_MASK
111472. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
111473. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL__STU_MASK
111474. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL__STU__SHIFT
111475. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
111476. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
111477. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
111478. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
111479. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
111480. BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
111481. BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST__CAP_ID_MASK
111482. BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST__CAP_ID__SHIFT
111483. BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST__NEXT_PTR_MASK
111484. BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST__NEXT_PTR__SHIFT
111485. BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__DEVICE_TYPE_MASK
111486. BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__DEVICE_TYPE__SHIFT
111487. BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__INT_MESSAGE_NUM_MASK
111488. BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
111489. BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__SLOT_IMPLEMENTED_MASK
111490. BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
111491. BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__VERSION_MASK
111492. BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__VERSION__SHIFT
111493. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
111494. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
111495. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
111496. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
111497. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
111498. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
111499. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
111500. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
111501. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
111502. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
111503. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
111504. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
111505. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
111506. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
111507. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
111508. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
111509. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
111510. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
111511. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
111512. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
111513. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
111514. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
111515. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
111516. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
111517. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
111518. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
111519. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
111520. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
111521. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
111522. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
111523. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
111524. BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
111525. BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG0__TLP_HDR_MASK
111526. BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG0__TLP_HDR__SHIFT
111527. BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG1__TLP_HDR_MASK
111528. BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG1__TLP_HDR__SHIFT
111529. BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG2__TLP_HDR_MASK
111530. BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG2__TLP_HDR__SHIFT
111531. BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG3__TLP_HDR_MASK
111532. BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG3__TLP_HDR__SHIFT
111533. BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
111534. BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
111535. BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
111536. BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
111537. BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
111538. BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
111539. BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
111540. BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
111541. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
111542. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
111543. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
111544. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
111545. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
111546. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
111547. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
111548. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
111549. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
111550. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
111551. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
111552. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
111553. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
111554. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
111555. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
111556. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
111557. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
111558. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
111559. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
111560. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
111561. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
111562. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
111563. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
111564. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
111565. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
111566. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
111567. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
111568. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
111569. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
111570. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
111571. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
111572. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
111573. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
111574. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
111575. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
111576. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
111577. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
111578. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
111579. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
111580. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
111581. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
111582. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
111583. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
111584. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
111585. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
111586. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
111587. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
111588. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
111589. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
111590. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
111591. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
111592. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
111593. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
111594. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
111595. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
111596. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
111597. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
111598. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
111599. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
111600. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
111601. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
111602. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
111603. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
111604. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
111605. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
111606. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
111607. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
111608. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
111609. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
111610. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
111611. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
111612. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
111613. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
111614. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
111615. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
111616. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
111617. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
111618. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
111619. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
111620. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
111621. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
111622. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
111623. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
111624. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
111625. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
111626. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
111627. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
111628. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
111629. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
111630. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
111631. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
111632. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
111633. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
111634. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
111635. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
111636. BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
111637. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
111638. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
111639. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
111640. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
111641. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
111642. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
111643. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
111644. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
111645. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
111646. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
111647. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
111648. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
111649. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
111650. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
111651. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
111652. BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
111653. BIF_CFG_DEV0_EPF0_VF26_PROG_INTERFACE__PROG_INTERFACE_MASK
111654. BIF_CFG_DEV0_EPF0_VF26_PROG_INTERFACE__PROG_INTERFACE__SHIFT
111655. BIF_CFG_DEV0_EPF0_VF26_REVISION_ID__MAJOR_REV_ID_MASK
111656. BIF_CFG_DEV0_EPF0_VF26_REVISION_ID__MAJOR_REV_ID__SHIFT
111657. BIF_CFG_DEV0_EPF0_VF26_REVISION_ID__MINOR_REV_ID_MASK
111658. BIF_CFG_DEV0_EPF0_VF26_REVISION_ID__MINOR_REV_ID__SHIFT
111659. BIF_CFG_DEV0_EPF0_VF26_ROM_BASE_ADDR__BASE_ADDR_MASK
111660. BIF_CFG_DEV0_EPF0_VF26_ROM_BASE_ADDR__BASE_ADDR__SHIFT
111661. BIF_CFG_DEV0_EPF0_VF26_STATUS__CAP_LIST_MASK
111662. BIF_CFG_DEV0_EPF0_VF26_STATUS__CAP_LIST__SHIFT
111663. BIF_CFG_DEV0_EPF0_VF26_STATUS__DEVSEL_TIMING_MASK
111664. BIF_CFG_DEV0_EPF0_VF26_STATUS__DEVSEL_TIMING__SHIFT
111665. BIF_CFG_DEV0_EPF0_VF26_STATUS__FAST_BACK_CAPABLE_MASK
111666. BIF_CFG_DEV0_EPF0_VF26_STATUS__FAST_BACK_CAPABLE__SHIFT
111667. BIF_CFG_DEV0_EPF0_VF26_STATUS__IMMEDIATE_READINESS_MASK
111668. BIF_CFG_DEV0_EPF0_VF26_STATUS__IMMEDIATE_READINESS__SHIFT
111669. BIF_CFG_DEV0_EPF0_VF26_STATUS__INT_STATUS_MASK
111670. BIF_CFG_DEV0_EPF0_VF26_STATUS__INT_STATUS__SHIFT
111671. BIF_CFG_DEV0_EPF0_VF26_STATUS__MASTER_DATA_PARITY_ERROR_MASK
111672. BIF_CFG_DEV0_EPF0_VF26_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
111673. BIF_CFG_DEV0_EPF0_VF26_STATUS__PARITY_ERROR_DETECTED_MASK
111674. BIF_CFG_DEV0_EPF0_VF26_STATUS__PARITY_ERROR_DETECTED__SHIFT
111675. BIF_CFG_DEV0_EPF0_VF26_STATUS__PCI_66_CAP_MASK
111676. BIF_CFG_DEV0_EPF0_VF26_STATUS__PCI_66_CAP__SHIFT
111677. BIF_CFG_DEV0_EPF0_VF26_STATUS__RECEIVED_MASTER_ABORT_MASK
111678. BIF_CFG_DEV0_EPF0_VF26_STATUS__RECEIVED_MASTER_ABORT__SHIFT
111679. BIF_CFG_DEV0_EPF0_VF26_STATUS__RECEIVED_TARGET_ABORT_MASK
111680. BIF_CFG_DEV0_EPF0_VF26_STATUS__RECEIVED_TARGET_ABORT__SHIFT
111681. BIF_CFG_DEV0_EPF0_VF26_STATUS__SIGNALED_SYSTEM_ERROR_MASK
111682. BIF_CFG_DEV0_EPF0_VF26_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
111683. BIF_CFG_DEV0_EPF0_VF26_STATUS__SIGNAL_TARGET_ABORT_MASK
111684. BIF_CFG_DEV0_EPF0_VF26_STATUS__SIGNAL_TARGET_ABORT__SHIFT
111685. BIF_CFG_DEV0_EPF0_VF26_SUB_CLASS__SUB_CLASS_MASK
111686. BIF_CFG_DEV0_EPF0_VF26_SUB_CLASS__SUB_CLASS__SHIFT
111687. BIF_CFG_DEV0_EPF0_VF26_VENDOR_ID__VENDOR_ID_MASK
111688. BIF_CFG_DEV0_EPF0_VF26_VENDOR_ID__VENDOR_ID__SHIFT
111689. BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
111690. BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
111691. BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
111692. BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
111693. BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1__BASE_ADDR_MASK
111694. BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1__BASE_ADDR__SHIFT
111695. BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2__BASE_ADDR_MASK
111696. BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2__BASE_ADDR__SHIFT
111697. BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3__BASE_ADDR_MASK
111698. BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3__BASE_ADDR__SHIFT
111699. BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4__BASE_ADDR_MASK
111700. BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4__BASE_ADDR__SHIFT
111701. BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5__BASE_ADDR_MASK
111702. BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5__BASE_ADDR__SHIFT
111703. BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6__BASE_ADDR_MASK
111704. BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6__BASE_ADDR__SHIFT
111705. BIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS__BASE_CLASS_MASK
111706. BIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS__BASE_CLASS__SHIFT
111707. BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_CAP_MASK
111708. BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_CAP__SHIFT
111709. BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_COMP_MASK
111710. BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_COMP__SHIFT
111711. BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_STRT_MASK
111712. BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_STRT__SHIFT
111713. BIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
111714. BIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
111715. BIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR__CAP_PTR_MASK
111716. BIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR__CAP_PTR__SHIFT
111717. BIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
111718. BIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
111719. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__AD_STEPPING_MASK
111720. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__AD_STEPPING__SHIFT
111721. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__BUS_MASTER_EN_MASK
111722. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__BUS_MASTER_EN__SHIFT
111723. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__FAST_B2B_EN_MASK
111724. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__FAST_B2B_EN__SHIFT
111725. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__INT_DIS_MASK
111726. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__INT_DIS__SHIFT
111727. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__IO_ACCESS_EN_MASK
111728. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__IO_ACCESS_EN__SHIFT
111729. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__MEM_ACCESS_EN_MASK
111730. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__MEM_ACCESS_EN__SHIFT
111731. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
111732. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
111733. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__PAL_SNOOP_EN_MASK
111734. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__PAL_SNOOP_EN__SHIFT
111735. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
111736. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
111737. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__SERR_EN_MASK
111738. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__SERR_EN__SHIFT
111739. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__SPECIAL_CYCLE_EN_MASK
111740. BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
111741. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
111742. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
111743. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
111744. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
111745. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
111746. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
111747. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
111748. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
111749. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
111750. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
111751. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
111752. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
111753. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
111754. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
111755. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
111756. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
111757. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
111758. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
111759. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
111760. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
111761. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
111762. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
111763. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
111764. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
111765. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
111766. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
111767. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
111768. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
111769. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
111770. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
111771. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
111772. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
111773. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
111774. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
111775. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
111776. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
111777. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
111778. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
111779. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
111780. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
111781. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
111782. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
111783. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
111784. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
111785. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__EXTENDED_TAG_MASK
111786. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
111787. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__FLR_CAPABLE_MASK
111788. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
111789. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
111790. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
111791. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
111792. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
111793. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
111794. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
111795. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__PHANTOM_FUNC_MASK
111796. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
111797. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
111798. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
111799. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
111800. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
111801. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
111802. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
111803. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
111804. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
111805. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
111806. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
111807. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
111808. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
111809. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
111810. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
111811. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
111812. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
111813. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
111814. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
111815. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
111816. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
111817. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__LTR_EN_MASK
111818. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__LTR_EN__SHIFT
111819. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__OBFF_EN_MASK
111820. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__OBFF_EN__SHIFT
111821. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
111822. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
111823. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
111824. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
111825. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__CORR_ERR_EN_MASK
111826. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
111827. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
111828. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
111829. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
111830. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
111831. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__INITIATE_FLR_MASK
111832. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
111833. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
111834. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
111835. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
111836. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
111837. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
111838. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
111839. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
111840. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
111841. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
111842. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
111843. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
111844. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
111845. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__USR_REPORT_EN_MASK
111846. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
111847. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID__DEVICE_ID_MASK
111848. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID__DEVICE_ID__SHIFT
111849. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2__RESERVED_MASK
111850. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2__RESERVED__SHIFT
111851. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__AUX_PWR_MASK
111852. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__AUX_PWR__SHIFT
111853. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__CORR_ERR_MASK
111854. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__CORR_ERR__SHIFT
111855. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
111856. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
111857. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__FATAL_ERR_MASK
111858. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__FATAL_ERR__SHIFT
111859. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
111860. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
111861. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
111862. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
111863. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__USR_DETECTED_MASK
111864. BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__USR_DETECTED__SHIFT
111865. BIF_CFG_DEV0_EPF0_VF27_0_HEADER__DEVICE_TYPE_MASK
111866. BIF_CFG_DEV0_EPF0_VF27_0_HEADER__DEVICE_TYPE__SHIFT
111867. BIF_CFG_DEV0_EPF0_VF27_0_HEADER__HEADER_TYPE_MASK
111868. BIF_CFG_DEV0_EPF0_VF27_0_HEADER__HEADER_TYPE__SHIFT
111869. BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
111870. BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
111871. BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
111872. BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
111873. BIF_CFG_DEV0_EPF0_VF27_0_LATENCY__LATENCY_TIMER_MASK
111874. BIF_CFG_DEV0_EPF0_VF27_0_LATENCY__LATENCY_TIMER__SHIFT
111875. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
111876. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
111877. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
111878. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
111879. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
111880. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
111881. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
111882. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
111883. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
111884. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
111885. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
111886. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
111887. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
111888. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
111889. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
111890. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
111891. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
111892. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
111893. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
111894. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
111895. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
111896. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
111897. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__L1_EXIT_LATENCY_MASK
111898. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
111899. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
111900. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
111901. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_SPEED_MASK
111902. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_SPEED__SHIFT
111903. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_WIDTH_MASK
111904. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_WIDTH__SHIFT
111905. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__PM_SUPPORT_MASK
111906. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__PM_SUPPORT__SHIFT
111907. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__PORT_NUMBER_MASK
111908. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__PORT_NUMBER__SHIFT
111909. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
111910. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
111911. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
111912. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
111913. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
111914. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
111915. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
111916. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
111917. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
111918. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
111919. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
111920. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
111921. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
111922. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
111923. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
111924. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
111925. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__XMIT_MARGIN_MASK
111926. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
111927. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
111928. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
111929. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
111930. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
111931. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
111932. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
111933. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__EXTENDED_SYNC_MASK
111934. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
111935. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
111936. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
111937. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
111938. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
111939. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
111940. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
111941. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_DIS_MASK
111942. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_DIS__SHIFT
111943. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__PM_CONTROL_MASK
111944. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__PM_CONTROL__SHIFT
111945. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
111946. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
111947. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__RETRAIN_LINK_MASK
111948. BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__RETRAIN_LINK__SHIFT
111949. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
111950. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
111951. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
111952. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
111953. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
111954. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
111955. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
111956. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
111957. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
111958. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
111959. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
111960. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
111961. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
111962. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
111963. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
111964. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
111965. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
111966. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
111967. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
111968. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
111969. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
111970. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
111971. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
111972. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
111973. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__DL_ACTIVE_MASK
111974. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__DL_ACTIVE__SHIFT
111975. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
111976. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
111977. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
111978. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
111979. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_TRAINING_MASK
111980. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_TRAINING__SHIFT
111981. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
111982. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
111983. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
111984. BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
111985. BIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY__MAX_LAT_MASK
111986. BIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY__MAX_LAT__SHIFT
111987. BIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT__MIN_GNT_MASK
111988. BIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT__MIN_GNT__SHIFT
111989. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST__CAP_ID_MASK
111990. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST__CAP_ID__SHIFT
111991. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST__NEXT_PTR_MASK
111992. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
111993. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_EN_MASK
111994. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
111995. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
111996. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
111997. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
111998. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
111999. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA__MSIX_PBA_BIR_MASK
112000. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
112001. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
112002. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
112003. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
112004. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
112005. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
112006. BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
112007. BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST__CAP_ID_MASK
112008. BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST__CAP_ID__SHIFT
112009. BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST__NEXT_PTR_MASK
112010. BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
112011. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64__MSI_MASK_64_MASK
112012. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64__MSI_MASK_64__SHIFT
112013. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK__MSI_MASK_MASK
112014. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK__MSI_MASK__SHIFT
112015. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
112016. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
112017. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
112018. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
112019. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_64BIT_MASK
112020. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
112021. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_EN_MASK
112022. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_EN__SHIFT
112023. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
112024. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
112025. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
112026. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
112027. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
112028. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
112029. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
112030. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
112031. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA__MSI_DATA_MASK
112032. BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA__MSI_DATA__SHIFT
112033. BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64__MSI_PENDING_64_MASK
112034. BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
112035. BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING__MSI_PENDING_MASK
112036. BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING__MSI_PENDING__SHIFT
112037. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
112038. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
112039. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
112040. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
112041. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
112042. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
112043. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
112044. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
112045. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
112046. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
112047. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
112048. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
112049. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
112050. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
112051. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
112052. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
112053. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
112054. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
112055. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
112056. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
112057. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
112058. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
112059. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
112060. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
112061. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
112062. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
112063. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
112064. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
112065. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
112066. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
112067. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
112068. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
112069. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
112070. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
112071. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
112072. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
112073. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
112074. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
112075. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
112076. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
112077. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
112078. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
112079. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
112080. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
112081. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
112082. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
112083. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
112084. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
112085. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
112086. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
112087. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL__STU_MASK
112088. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL__STU__SHIFT
112089. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
112090. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
112091. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
112092. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
112093. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
112094. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
112095. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST__CAP_ID_MASK
112096. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST__CAP_ID__SHIFT
112097. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST__NEXT_PTR_MASK
112098. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
112099. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__DEVICE_TYPE_MASK
112100. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__DEVICE_TYPE__SHIFT
112101. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
112102. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
112103. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
112104. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
112105. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__VERSION_MASK
112106. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__VERSION__SHIFT
112107. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
112108. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
112109. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
112110. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
112111. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
112112. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
112113. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
112114. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
112115. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
112116. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
112117. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
112118. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
112119. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
112120. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
112121. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
112122. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
112123. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
112124. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
112125. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
112126. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
112127. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
112128. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
112129. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
112130. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
112131. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
112132. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
112133. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
112134. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
112135. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
112136. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
112137. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
112138. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
112139. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0__TLP_HDR_MASK
112140. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
112141. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1__TLP_HDR_MASK
112142. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
112143. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2__TLP_HDR_MASK
112144. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
112145. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3__TLP_HDR_MASK
112146. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
112147. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
112148. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
112149. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
112150. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
112151. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
112152. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
112153. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
112154. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
112155. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
112156. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
112157. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
112158. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
112159. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
112160. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
112161. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
112162. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
112163. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
112164. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
112165. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
112166. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
112167. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
112168. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
112169. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
112170. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
112171. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
112172. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
112173. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
112174. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
112175. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
112176. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
112177. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
112178. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
112179. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
112180. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
112181. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
112182. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
112183. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
112184. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
112185. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
112186. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
112187. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
112188. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
112189. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
112190. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
112191. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
112192. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
112193. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
112194. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
112195. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
112196. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
112197. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
112198. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
112199. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
112200. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
112201. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
112202. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
112203. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
112204. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
112205. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
112206. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
112207. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
112208. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
112209. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
112210. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
112211. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
112212. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
112213. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
112214. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
112215. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
112216. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
112217. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
112218. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
112219. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
112220. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
112221. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
112222. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
112223. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
112224. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
112225. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
112226. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
112227. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
112228. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
112229. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
112230. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
112231. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
112232. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
112233. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
112234. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
112235. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
112236. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
112237. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
112238. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
112239. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
112240. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
112241. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
112242. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
112243. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
112244. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
112245. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
112246. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
112247. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
112248. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
112249. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
112250. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
112251. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
112252. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
112253. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
112254. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
112255. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
112256. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
112257. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
112258. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
112259. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
112260. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
112261. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
112262. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
112263. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
112264. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
112265. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
112266. BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
112267. BIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE__PROG_INTERFACE_MASK
112268. BIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
112269. BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID__MAJOR_REV_ID_MASK
112270. BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID__MAJOR_REV_ID__SHIFT
112271. BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID__MINOR_REV_ID_MASK
112272. BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID__MINOR_REV_ID__SHIFT
112273. BIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR__BASE_ADDR_MASK
112274. BIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
112275. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__CAP_LIST_MASK
112276. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__CAP_LIST__SHIFT
112277. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__DEVSEL_TIMING_MASK
112278. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__DEVSEL_TIMING__SHIFT
112279. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__FAST_BACK_CAPABLE_MASK
112280. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__FAST_BACK_CAPABLE__SHIFT
112281. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__IMMEDIATE_READINESS_MASK
112282. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__IMMEDIATE_READINESS__SHIFT
112283. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__INT_STATUS_MASK
112284. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__INT_STATUS__SHIFT
112285. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
112286. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
112287. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__PARITY_ERROR_DETECTED_MASK
112288. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
112289. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__PCI_66_CAP_MASK
112290. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__PCI_66_CAP__SHIFT
112291. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__RECEIVED_MASTER_ABORT_MASK
112292. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
112293. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__RECEIVED_TARGET_ABORT_MASK
112294. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
112295. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
112296. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
112297. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__SIGNAL_TARGET_ABORT_MASK
112298. BIF_CFG_DEV0_EPF0_VF27_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
112299. BIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS__SUB_CLASS_MASK
112300. BIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS__SUB_CLASS__SHIFT
112301. BIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID__VENDOR_ID_MASK
112302. BIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID__VENDOR_ID__SHIFT
112303. BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
112304. BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
112305. BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
112306. BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
112307. BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1__BASE_ADDR_MASK
112308. BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1__BASE_ADDR__SHIFT
112309. BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2__BASE_ADDR_MASK
112310. BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2__BASE_ADDR__SHIFT
112311. BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3__BASE_ADDR_MASK
112312. BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3__BASE_ADDR__SHIFT
112313. BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4__BASE_ADDR_MASK
112314. BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4__BASE_ADDR__SHIFT
112315. BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5__BASE_ADDR_MASK
112316. BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5__BASE_ADDR__SHIFT
112317. BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6__BASE_ADDR_MASK
112318. BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6__BASE_ADDR__SHIFT
112319. BIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS__BASE_CLASS_MASK
112320. BIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS__BASE_CLASS__SHIFT
112321. BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_CAP_MASK
112322. BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_CAP__SHIFT
112323. BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_COMP_MASK
112324. BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_COMP__SHIFT
112325. BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_STRT_MASK
112326. BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_STRT__SHIFT
112327. BIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
112328. BIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
112329. BIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR__CAP_PTR_MASK
112330. BIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR__CAP_PTR__SHIFT
112331. BIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
112332. BIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
112333. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__AD_STEPPING_MASK
112334. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__AD_STEPPING__SHIFT
112335. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__BUS_MASTER_EN_MASK
112336. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__BUS_MASTER_EN__SHIFT
112337. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__FAST_B2B_EN_MASK
112338. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__FAST_B2B_EN__SHIFT
112339. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__INT_DIS_MASK
112340. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__INT_DIS__SHIFT
112341. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__IO_ACCESS_EN_MASK
112342. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__IO_ACCESS_EN__SHIFT
112343. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__MEM_ACCESS_EN_MASK
112344. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__MEM_ACCESS_EN__SHIFT
112345. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
112346. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
112347. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__PAL_SNOOP_EN_MASK
112348. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__PAL_SNOOP_EN__SHIFT
112349. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
112350. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
112351. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__SERR_EN_MASK
112352. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__SERR_EN__SHIFT
112353. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__SPECIAL_CYCLE_EN_MASK
112354. BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
112355. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
112356. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
112357. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
112358. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
112359. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
112360. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
112361. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
112362. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
112363. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
112364. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
112365. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
112366. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
112367. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
112368. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
112369. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
112370. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
112371. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
112372. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
112373. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
112374. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
112375. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
112376. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
112377. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
112378. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
112379. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
112380. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
112381. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
112382. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
112383. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
112384. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
112385. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
112386. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
112387. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
112388. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
112389. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
112390. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
112391. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
112392. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
112393. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
112394. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
112395. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
112396. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
112397. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
112398. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
112399. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__EXTENDED_TAG_MASK
112400. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
112401. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__FLR_CAPABLE_MASK
112402. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
112403. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
112404. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
112405. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
112406. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
112407. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
112408. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
112409. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__PHANTOM_FUNC_MASK
112410. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
112411. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
112412. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
112413. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
112414. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
112415. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
112416. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
112417. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
112418. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
112419. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
112420. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
112421. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
112422. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
112423. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
112424. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
112425. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
112426. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
112427. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
112428. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
112429. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
112430. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
112431. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__LTR_EN_MASK
112432. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__LTR_EN__SHIFT
112433. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__OBFF_EN_MASK
112434. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__OBFF_EN__SHIFT
112435. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
112436. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
112437. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
112438. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
112439. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__CORR_ERR_EN_MASK
112440. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
112441. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
112442. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
112443. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
112444. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
112445. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__INITIATE_FLR_MASK
112446. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
112447. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
112448. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
112449. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
112450. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
112451. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
112452. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
112453. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
112454. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
112455. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
112456. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
112457. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
112458. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
112459. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__USR_REPORT_EN_MASK
112460. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
112461. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID__DEVICE_ID_MASK
112462. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID__DEVICE_ID__SHIFT
112463. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2__RESERVED_MASK
112464. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2__RESERVED__SHIFT
112465. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__AUX_PWR_MASK
112466. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__AUX_PWR__SHIFT
112467. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__CORR_ERR_MASK
112468. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__CORR_ERR__SHIFT
112469. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
112470. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
112471. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__FATAL_ERR_MASK
112472. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__FATAL_ERR__SHIFT
112473. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
112474. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
112475. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
112476. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
112477. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__USR_DETECTED_MASK
112478. BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__USR_DETECTED__SHIFT
112479. BIF_CFG_DEV0_EPF0_VF27_1_HEADER__DEVICE_TYPE_MASK
112480. BIF_CFG_DEV0_EPF0_VF27_1_HEADER__DEVICE_TYPE__SHIFT
112481. BIF_CFG_DEV0_EPF0_VF27_1_HEADER__HEADER_TYPE_MASK
112482. BIF_CFG_DEV0_EPF0_VF27_1_HEADER__HEADER_TYPE__SHIFT
112483. BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
112484. BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
112485. BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
112486. BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
112487. BIF_CFG_DEV0_EPF0_VF27_1_LATENCY__LATENCY_TIMER_MASK
112488. BIF_CFG_DEV0_EPF0_VF27_1_LATENCY__LATENCY_TIMER__SHIFT
112489. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
112490. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
112491. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
112492. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
112493. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
112494. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
112495. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
112496. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
112497. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
112498. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
112499. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
112500. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
112501. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
112502. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
112503. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
112504. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
112505. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
112506. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
112507. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
112508. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
112509. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
112510. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
112511. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__L1_EXIT_LATENCY_MASK
112512. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
112513. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
112514. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
112515. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_SPEED_MASK
112516. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_SPEED__SHIFT
112517. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_WIDTH_MASK
112518. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_WIDTH__SHIFT
112519. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__PM_SUPPORT_MASK
112520. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__PM_SUPPORT__SHIFT
112521. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__PORT_NUMBER_MASK
112522. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__PORT_NUMBER__SHIFT
112523. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
112524. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
112525. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
112526. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
112527. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
112528. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
112529. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
112530. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
112531. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
112532. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
112533. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
112534. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
112535. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
112536. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
112537. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
112538. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
112539. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__XMIT_MARGIN_MASK
112540. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
112541. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
112542. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
112543. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
112544. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
112545. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
112546. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
112547. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__EXTENDED_SYNC_MASK
112548. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
112549. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
112550. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
112551. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
112552. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
112553. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
112554. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
112555. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_DIS_MASK
112556. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_DIS__SHIFT
112557. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__PM_CONTROL_MASK
112558. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__PM_CONTROL__SHIFT
112559. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
112560. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
112561. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__RETRAIN_LINK_MASK
112562. BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__RETRAIN_LINK__SHIFT
112563. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
112564. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
112565. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
112566. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
112567. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
112568. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
112569. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
112570. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
112571. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
112572. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
112573. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
112574. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
112575. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
112576. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
112577. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
112578. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
112579. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
112580. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
112581. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
112582. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
112583. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
112584. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
112585. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
112586. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
112587. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__DL_ACTIVE_MASK
112588. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__DL_ACTIVE__SHIFT
112589. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
112590. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
112591. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
112592. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
112593. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_TRAINING_MASK
112594. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_TRAINING__SHIFT
112595. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
112596. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
112597. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
112598. BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
112599. BIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY__MAX_LAT_MASK
112600. BIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY__MAX_LAT__SHIFT
112601. BIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT__MIN_GNT_MASK
112602. BIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT__MIN_GNT__SHIFT
112603. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST__CAP_ID_MASK
112604. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST__CAP_ID__SHIFT
112605. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST__NEXT_PTR_MASK
112606. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
112607. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_EN_MASK
112608. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
112609. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
112610. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
112611. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
112612. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
112613. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA__MSIX_PBA_BIR_MASK
112614. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
112615. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
112616. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
112617. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
112618. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
112619. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
112620. BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
112621. BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST__CAP_ID_MASK
112622. BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST__CAP_ID__SHIFT
112623. BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST__NEXT_PTR_MASK
112624. BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
112625. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64__MSI_MASK_64_MASK
112626. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64__MSI_MASK_64__SHIFT
112627. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK__MSI_MASK_MASK
112628. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK__MSI_MASK__SHIFT
112629. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
112630. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
112631. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
112632. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
112633. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_64BIT_MASK
112634. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
112635. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_EN_MASK
112636. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_EN__SHIFT
112637. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
112638. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
112639. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
112640. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
112641. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
112642. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
112643. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
112644. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
112645. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA__MSI_DATA_MASK
112646. BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA__MSI_DATA__SHIFT
112647. BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64__MSI_PENDING_64_MASK
112648. BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
112649. BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING__MSI_PENDING_MASK
112650. BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING__MSI_PENDING__SHIFT
112651. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
112652. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
112653. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
112654. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
112655. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
112656. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
112657. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
112658. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
112659. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
112660. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
112661. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
112662. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
112663. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
112664. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
112665. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
112666. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
112667. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
112668. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
112669. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
112670. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
112671. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
112672. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
112673. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
112674. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
112675. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
112676. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
112677. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
112678. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
112679. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
112680. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
112681. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
112682. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
112683. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
112684. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
112685. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
112686. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
112687. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
112688. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
112689. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
112690. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
112691. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
112692. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
112693. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
112694. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
112695. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
112696. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
112697. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
112698. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
112699. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
112700. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
112701. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL__STU_MASK
112702. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL__STU__SHIFT
112703. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
112704. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
112705. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
112706. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
112707. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
112708. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
112709. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST__CAP_ID_MASK
112710. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST__CAP_ID__SHIFT
112711. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST__NEXT_PTR_MASK
112712. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
112713. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__DEVICE_TYPE_MASK
112714. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__DEVICE_TYPE__SHIFT
112715. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
112716. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
112717. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
112718. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
112719. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__VERSION_MASK
112720. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__VERSION__SHIFT
112721. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
112722. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
112723. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
112724. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
112725. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
112726. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
112727. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
112728. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
112729. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
112730. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
112731. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
112732. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
112733. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
112734. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
112735. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
112736. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
112737. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
112738. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
112739. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
112740. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
112741. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
112742. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
112743. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
112744. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
112745. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
112746. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
112747. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
112748. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
112749. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
112750. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
112751. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
112752. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
112753. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0__TLP_HDR_MASK
112754. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
112755. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1__TLP_HDR_MASK
112756. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
112757. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2__TLP_HDR_MASK
112758. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
112759. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3__TLP_HDR_MASK
112760. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
112761. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
112762. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
112763. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
112764. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
112765. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
112766. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
112767. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
112768. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
112769. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
112770. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
112771. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
112772. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
112773. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
112774. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
112775. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
112776. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
112777. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
112778. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
112779. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
112780. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
112781. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
112782. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
112783. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
112784. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
112785. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
112786. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
112787. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
112788. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
112789. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
112790. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
112791. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
112792. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
112793. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
112794. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
112795. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
112796. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
112797. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
112798. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
112799. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
112800. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
112801. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
112802. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
112803. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
112804. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
112805. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
112806. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
112807. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
112808. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
112809. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
112810. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
112811. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
112812. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
112813. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
112814. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
112815. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
112816. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
112817. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
112818. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
112819. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
112820. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
112821. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
112822. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
112823. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
112824. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
112825. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
112826. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
112827. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
112828. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
112829. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
112830. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
112831. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
112832. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
112833. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
112834. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
112835. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
112836. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
112837. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
112838. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
112839. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
112840. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
112841. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
112842. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
112843. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
112844. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
112845. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
112846. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
112847. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
112848. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
112849. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
112850. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
112851. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
112852. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
112853. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
112854. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
112855. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
112856. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
112857. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
112858. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
112859. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
112860. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
112861. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
112862. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
112863. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
112864. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
112865. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
112866. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
112867. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
112868. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
112869. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
112870. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
112871. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
112872. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
112873. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
112874. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
112875. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
112876. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
112877. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
112878. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
112879. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
112880. BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
112881. BIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE__PROG_INTERFACE_MASK
112882. BIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
112883. BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID__MAJOR_REV_ID_MASK
112884. BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID__MAJOR_REV_ID__SHIFT
112885. BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID__MINOR_REV_ID_MASK
112886. BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID__MINOR_REV_ID__SHIFT
112887. BIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR__BASE_ADDR_MASK
112888. BIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
112889. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__CAP_LIST_MASK
112890. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__CAP_LIST__SHIFT
112891. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__DEVSEL_TIMING_MASK
112892. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__DEVSEL_TIMING__SHIFT
112893. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__FAST_BACK_CAPABLE_MASK
112894. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__FAST_BACK_CAPABLE__SHIFT
112895. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__IMMEDIATE_READINESS_MASK
112896. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__IMMEDIATE_READINESS__SHIFT
112897. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__INT_STATUS_MASK
112898. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__INT_STATUS__SHIFT
112899. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
112900. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
112901. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__PARITY_ERROR_DETECTED_MASK
112902. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
112903. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__PCI_66_CAP_MASK
112904. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__PCI_66_CAP__SHIFT
112905. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__RECEIVED_MASTER_ABORT_MASK
112906. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
112907. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__RECEIVED_TARGET_ABORT_MASK
112908. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
112909. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
112910. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
112911. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__SIGNAL_TARGET_ABORT_MASK
112912. BIF_CFG_DEV0_EPF0_VF27_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
112913. BIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS__SUB_CLASS_MASK
112914. BIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS__SUB_CLASS__SHIFT
112915. BIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID__VENDOR_ID_MASK
112916. BIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID__VENDOR_ID__SHIFT
112917. BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID__SUBSYSTEM_ID_MASK
112918. BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
112919. BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
112920. BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
112921. BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_1__BASE_ADDR_MASK
112922. BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_1__BASE_ADDR__SHIFT
112923. BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_2__BASE_ADDR_MASK
112924. BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_2__BASE_ADDR__SHIFT
112925. BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_3__BASE_ADDR_MASK
112926. BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_3__BASE_ADDR__SHIFT
112927. BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_4__BASE_ADDR_MASK
112928. BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_4__BASE_ADDR__SHIFT
112929. BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_5__BASE_ADDR_MASK
112930. BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_5__BASE_ADDR__SHIFT
112931. BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_6__BASE_ADDR_MASK
112932. BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_6__BASE_ADDR__SHIFT
112933. BIF_CFG_DEV0_EPF0_VF27_BASE_CLASS__BASE_CLASS_MASK
112934. BIF_CFG_DEV0_EPF0_VF27_BASE_CLASS__BASE_CLASS__SHIFT
112935. BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_CAP_MASK
112936. BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_CAP__SHIFT
112937. BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_COMP_MASK
112938. BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_COMP__SHIFT
112939. BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_STRT_MASK
112940. BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_STRT__SHIFT
112941. BIF_CFG_DEV0_EPF0_VF27_CACHE_LINE__CACHE_LINE_SIZE_MASK
112942. BIF_CFG_DEV0_EPF0_VF27_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
112943. BIF_CFG_DEV0_EPF0_VF27_CAP_PTR__CAP_PTR_MASK
112944. BIF_CFG_DEV0_EPF0_VF27_CAP_PTR__CAP_PTR__SHIFT
112945. BIF_CFG_DEV0_EPF0_VF27_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
112946. BIF_CFG_DEV0_EPF0_VF27_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
112947. BIF_CFG_DEV0_EPF0_VF27_COMMAND__AD_STEPPING_MASK
112948. BIF_CFG_DEV0_EPF0_VF27_COMMAND__AD_STEPPING__SHIFT
112949. BIF_CFG_DEV0_EPF0_VF27_COMMAND__BUS_MASTER_EN_MASK
112950. BIF_CFG_DEV0_EPF0_VF27_COMMAND__BUS_MASTER_EN__SHIFT
112951. BIF_CFG_DEV0_EPF0_VF27_COMMAND__FAST_B2B_EN_MASK
112952. BIF_CFG_DEV0_EPF0_VF27_COMMAND__FAST_B2B_EN__SHIFT
112953. BIF_CFG_DEV0_EPF0_VF27_COMMAND__INT_DIS_MASK
112954. BIF_CFG_DEV0_EPF0_VF27_COMMAND__INT_DIS__SHIFT
112955. BIF_CFG_DEV0_EPF0_VF27_COMMAND__IO_ACCESS_EN_MASK
112956. BIF_CFG_DEV0_EPF0_VF27_COMMAND__IO_ACCESS_EN__SHIFT
112957. BIF_CFG_DEV0_EPF0_VF27_COMMAND__MEM_ACCESS_EN_MASK
112958. BIF_CFG_DEV0_EPF0_VF27_COMMAND__MEM_ACCESS_EN__SHIFT
112959. BIF_CFG_DEV0_EPF0_VF27_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
112960. BIF_CFG_DEV0_EPF0_VF27_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
112961. BIF_CFG_DEV0_EPF0_VF27_COMMAND__PAL_SNOOP_EN_MASK
112962. BIF_CFG_DEV0_EPF0_VF27_COMMAND__PAL_SNOOP_EN__SHIFT
112963. BIF_CFG_DEV0_EPF0_VF27_COMMAND__PARITY_ERROR_RESPONSE_MASK
112964. BIF_CFG_DEV0_EPF0_VF27_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
112965. BIF_CFG_DEV0_EPF0_VF27_COMMAND__SERR_EN_MASK
112966. BIF_CFG_DEV0_EPF0_VF27_COMMAND__SERR_EN__SHIFT
112967. BIF_CFG_DEV0_EPF0_VF27_COMMAND__SPECIAL_CYCLE_EN_MASK
112968. BIF_CFG_DEV0_EPF0_VF27_COMMAND__SPECIAL_CYCLE_EN__SHIFT
112969. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
112970. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
112971. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
112972. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
112973. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
112974. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
112975. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
112976. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
112977. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
112978. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
112979. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
112980. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
112981. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
112982. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
112983. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
112984. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
112985. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
112986. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
112987. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
112988. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
112989. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
112990. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
112991. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__FRS_SUPPORTED_MASK
112992. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
112993. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
112994. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
112995. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__LTR_SUPPORTED_MASK
112996. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
112997. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
112998. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
112999. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
113000. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
113001. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__OBFF_SUPPORTED_MASK
113002. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
113003. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
113004. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
113005. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
113006. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
113007. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
113008. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
113009. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
113010. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
113011. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
113012. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
113013. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__EXTENDED_TAG_MASK
113014. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__EXTENDED_TAG__SHIFT
113015. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__FLR_CAPABLE_MASK
113016. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__FLR_CAPABLE__SHIFT
113017. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
113018. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
113019. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
113020. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
113021. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
113022. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
113023. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__PHANTOM_FUNC_MASK
113024. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__PHANTOM_FUNC__SHIFT
113025. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
113026. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
113027. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
113028. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
113029. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
113030. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
113031. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
113032. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
113033. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
113034. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
113035. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
113036. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
113037. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
113038. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
113039. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
113040. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
113041. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
113042. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
113043. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
113044. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
113045. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__LTR_EN_MASK
113046. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__LTR_EN__SHIFT
113047. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__OBFF_EN_MASK
113048. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__OBFF_EN__SHIFT
113049. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
113050. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
113051. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
113052. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
113053. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__CORR_ERR_EN_MASK
113054. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__CORR_ERR_EN__SHIFT
113055. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
113056. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
113057. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__FATAL_ERR_EN_MASK
113058. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
113059. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__INITIATE_FLR_MASK
113060. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__INITIATE_FLR__SHIFT
113061. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
113062. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
113063. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
113064. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
113065. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
113066. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
113067. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__NO_SNOOP_EN_MASK
113068. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
113069. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
113070. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
113071. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__RELAXED_ORD_EN_MASK
113072. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
113073. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__USR_REPORT_EN_MASK
113074. BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__USR_REPORT_EN__SHIFT
113075. BIF_CFG_DEV0_EPF0_VF27_DEVICE_ID__DEVICE_ID_MASK
113076. BIF_CFG_DEV0_EPF0_VF27_DEVICE_ID__DEVICE_ID__SHIFT
113077. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS2__RESERVED_MASK
113078. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS2__RESERVED__SHIFT
113079. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__AUX_PWR_MASK
113080. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__AUX_PWR__SHIFT
113081. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__CORR_ERR_MASK
113082. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__CORR_ERR__SHIFT
113083. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
113084. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
113085. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__FATAL_ERR_MASK
113086. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__FATAL_ERR__SHIFT
113087. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__NON_FATAL_ERR_MASK
113088. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
113089. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
113090. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
113091. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__USR_DETECTED_MASK
113092. BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__USR_DETECTED__SHIFT
113093. BIF_CFG_DEV0_EPF0_VF27_HEADER__DEVICE_TYPE_MASK
113094. BIF_CFG_DEV0_EPF0_VF27_HEADER__DEVICE_TYPE__SHIFT
113095. BIF_CFG_DEV0_EPF0_VF27_HEADER__HEADER_TYPE_MASK
113096. BIF_CFG_DEV0_EPF0_VF27_HEADER__HEADER_TYPE__SHIFT
113097. BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_LINE__INTERRUPT_LINE_MASK
113098. BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
113099. BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_PIN__INTERRUPT_PIN_MASK
113100. BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
113101. BIF_CFG_DEV0_EPF0_VF27_LATENCY__LATENCY_TIMER_MASK
113102. BIF_CFG_DEV0_EPF0_VF27_LATENCY__LATENCY_TIMER__SHIFT
113103. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
113104. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
113105. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
113106. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
113107. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
113108. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
113109. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
113110. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
113111. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
113112. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
113113. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
113114. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
113115. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
113116. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
113117. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
113118. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
113119. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
113120. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
113121. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
113122. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
113123. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__L0S_EXIT_LATENCY_MASK
113124. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
113125. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__L1_EXIT_LATENCY_MASK
113126. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__L1_EXIT_LATENCY__SHIFT
113127. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
113128. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
113129. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_SPEED_MASK
113130. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_SPEED__SHIFT
113131. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_WIDTH_MASK
113132. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_WIDTH__SHIFT
113133. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__PM_SUPPORT_MASK
113134. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__PM_SUPPORT__SHIFT
113135. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__PORT_NUMBER_MASK
113136. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__PORT_NUMBER__SHIFT
113137. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
113138. BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
113139. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
113140. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
113141. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__COMPLIANCE_SOS_MASK
113142. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
113143. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__ENTER_COMPLIANCE_MASK
113144. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
113145. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
113146. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
113147. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
113148. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
113149. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
113150. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
113151. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__TARGET_LINK_SPEED_MASK
113152. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
113153. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__XMIT_MARGIN_MASK
113154. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__XMIT_MARGIN__SHIFT
113155. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
113156. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
113157. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__COMMON_CLOCK_CFG_MASK
113158. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
113159. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
113160. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
113161. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__EXTENDED_SYNC_MASK
113162. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__EXTENDED_SYNC__SHIFT
113163. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
113164. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
113165. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
113166. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
113167. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
113168. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
113169. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_DIS_MASK
113170. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_DIS__SHIFT
113171. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__PM_CONTROL_MASK
113172. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__PM_CONTROL__SHIFT
113173. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__READ_CPL_BOUNDARY_MASK
113174. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
113175. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__RETRAIN_LINK_MASK
113176. BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__RETRAIN_LINK__SHIFT
113177. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
113178. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
113179. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
113180. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
113181. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
113182. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
113183. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
113184. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
113185. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
113186. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
113187. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
113188. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
113189. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
113190. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
113191. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
113192. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
113193. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
113194. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
113195. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
113196. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
113197. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
113198. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
113199. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__CURRENT_LINK_SPEED_MASK
113200. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
113201. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__DL_ACTIVE_MASK
113202. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__DL_ACTIVE__SHIFT
113203. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
113204. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
113205. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
113206. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
113207. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_TRAINING_MASK
113208. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_TRAINING__SHIFT
113209. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
113210. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
113211. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__SLOT_CLOCK_CFG_MASK
113212. BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
113213. BIF_CFG_DEV0_EPF0_VF27_MAX_LATENCY__MAX_LAT_MASK
113214. BIF_CFG_DEV0_EPF0_VF27_MAX_LATENCY__MAX_LAT__SHIFT
113215. BIF_CFG_DEV0_EPF0_VF27_MIN_GRANT__MIN_GNT_MASK
113216. BIF_CFG_DEV0_EPF0_VF27_MIN_GRANT__MIN_GNT__SHIFT
113217. BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST__CAP_ID_MASK
113218. BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST__CAP_ID__SHIFT
113219. BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST__NEXT_PTR_MASK
113220. BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST__NEXT_PTR__SHIFT
113221. BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_EN_MASK
113222. BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_EN__SHIFT
113223. BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
113224. BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
113225. BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
113226. BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
113227. BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA__MSIX_PBA_BIR_MASK
113228. BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA__MSIX_PBA_BIR__SHIFT
113229. BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA__MSIX_PBA_OFFSET_MASK
113230. BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
113231. BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE__MSIX_TABLE_BIR_MASK
113232. BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
113233. BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
113234. BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
113235. BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST__CAP_ID_MASK
113236. BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST__CAP_ID__SHIFT
113237. BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST__NEXT_PTR_MASK
113238. BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST__NEXT_PTR__SHIFT
113239. BIF_CFG_DEV0_EPF0_VF27_MSI_MASK_64__MSI_MASK_64_MASK
113240. BIF_CFG_DEV0_EPF0_VF27_MSI_MASK_64__MSI_MASK_64__SHIFT
113241. BIF_CFG_DEV0_EPF0_VF27_MSI_MASK__MSI_MASK_MASK
113242. BIF_CFG_DEV0_EPF0_VF27_MSI_MASK__MSI_MASK__SHIFT
113243. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
113244. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
113245. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
113246. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
113247. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_64BIT_MASK
113248. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_64BIT__SHIFT
113249. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_EN_MASK
113250. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_EN__SHIFT
113251. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
113252. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
113253. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
113254. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
113255. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
113256. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
113257. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA_64__MSI_DATA_64_MASK
113258. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
113259. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA__MSI_DATA_MASK
113260. BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA__MSI_DATA__SHIFT
113261. BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING_64__MSI_PENDING_64_MASK
113262. BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING_64__MSI_PENDING_64__SHIFT
113263. BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING__MSI_PENDING_MASK
113264. BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING__MSI_PENDING__SHIFT
113265. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
113266. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
113267. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
113268. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
113269. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
113270. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
113271. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
113272. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
113273. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
113274. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
113275. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
113276. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
113277. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
113278. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
113279. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
113280. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
113281. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
113282. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
113283. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
113284. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
113285. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
113286. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
113287. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
113288. BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
113289. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
113290. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
113291. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
113292. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
113293. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
113294. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
113295. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
113296. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
113297. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
113298. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
113299. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
113300. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
113301. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
113302. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
113303. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
113304. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
113305. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
113306. BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
113307. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
113308. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
113309. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
113310. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
113311. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
113312. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
113313. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL__ATC_ENABLE_MASK
113314. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
113315. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL__STU_MASK
113316. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL__STU__SHIFT
113317. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
113318. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
113319. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
113320. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
113321. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
113322. BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
113323. BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST__CAP_ID_MASK
113324. BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST__CAP_ID__SHIFT
113325. BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST__NEXT_PTR_MASK
113326. BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST__NEXT_PTR__SHIFT
113327. BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__DEVICE_TYPE_MASK
113328. BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__DEVICE_TYPE__SHIFT
113329. BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__INT_MESSAGE_NUM_MASK
113330. BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
113331. BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__SLOT_IMPLEMENTED_MASK
113332. BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
113333. BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__VERSION_MASK
113334. BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__VERSION__SHIFT
113335. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
113336. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
113337. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
113338. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
113339. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
113340. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
113341. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
113342. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
113343. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
113344. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
113345. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
113346. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
113347. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
113348. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
113349. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
113350. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
113351. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
113352. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
113353. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
113354. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
113355. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
113356. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
113357. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
113358. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
113359. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
113360. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
113361. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
113362. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
113363. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
113364. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
113365. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
113366. BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
113367. BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG0__TLP_HDR_MASK
113368. BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG0__TLP_HDR__SHIFT
113369. BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG1__TLP_HDR_MASK
113370. BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG1__TLP_HDR__SHIFT
113371. BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG2__TLP_HDR_MASK
113372. BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG2__TLP_HDR__SHIFT
113373. BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG3__TLP_HDR_MASK
113374. BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG3__TLP_HDR__SHIFT
113375. BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
113376. BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
113377. BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
113378. BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
113379. BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
113380. BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
113381. BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
113382. BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
113383. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
113384. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
113385. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
113386. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
113387. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
113388. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
113389. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
113390. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
113391. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
113392. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
113393. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
113394. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
113395. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
113396. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
113397. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
113398. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
113399. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
113400. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
113401. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
113402. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
113403. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
113404. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
113405. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
113406. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
113407. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
113408. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
113409. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
113410. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
113411. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
113412. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
113413. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
113414. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
113415. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
113416. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
113417. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
113418. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
113419. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
113420. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
113421. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
113422. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
113423. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
113424. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
113425. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
113426. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
113427. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
113428. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
113429. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
113430. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
113431. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
113432. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
113433. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
113434. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
113435. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
113436. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
113437. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
113438. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
113439. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
113440. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
113441. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
113442. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
113443. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
113444. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
113445. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
113446. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
113447. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
113448. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
113449. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
113450. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
113451. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
113452. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
113453. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
113454. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
113455. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
113456. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
113457. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
113458. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
113459. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
113460. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
113461. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
113462. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
113463. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
113464. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
113465. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
113466. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
113467. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
113468. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
113469. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
113470. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
113471. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
113472. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
113473. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
113474. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
113475. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
113476. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
113477. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
113478. BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
113479. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
113480. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
113481. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
113482. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
113483. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
113484. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
113485. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
113486. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
113487. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
113488. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
113489. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
113490. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
113491. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
113492. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
113493. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
113494. BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
113495. BIF_CFG_DEV0_EPF0_VF27_PROG_INTERFACE__PROG_INTERFACE_MASK
113496. BIF_CFG_DEV0_EPF0_VF27_PROG_INTERFACE__PROG_INTERFACE__SHIFT
113497. BIF_CFG_DEV0_EPF0_VF27_REVISION_ID__MAJOR_REV_ID_MASK
113498. BIF_CFG_DEV0_EPF0_VF27_REVISION_ID__MAJOR_REV_ID__SHIFT
113499. BIF_CFG_DEV0_EPF0_VF27_REVISION_ID__MINOR_REV_ID_MASK
113500. BIF_CFG_DEV0_EPF0_VF27_REVISION_ID__MINOR_REV_ID__SHIFT
113501. BIF_CFG_DEV0_EPF0_VF27_ROM_BASE_ADDR__BASE_ADDR_MASK
113502. BIF_CFG_DEV0_EPF0_VF27_ROM_BASE_ADDR__BASE_ADDR__SHIFT
113503. BIF_CFG_DEV0_EPF0_VF27_STATUS__CAP_LIST_MASK
113504. BIF_CFG_DEV0_EPF0_VF27_STATUS__CAP_LIST__SHIFT
113505. BIF_CFG_DEV0_EPF0_VF27_STATUS__DEVSEL_TIMING_MASK
113506. BIF_CFG_DEV0_EPF0_VF27_STATUS__DEVSEL_TIMING__SHIFT
113507. BIF_CFG_DEV0_EPF0_VF27_STATUS__FAST_BACK_CAPABLE_MASK
113508. BIF_CFG_DEV0_EPF0_VF27_STATUS__FAST_BACK_CAPABLE__SHIFT
113509. BIF_CFG_DEV0_EPF0_VF27_STATUS__IMMEDIATE_READINESS_MASK
113510. BIF_CFG_DEV0_EPF0_VF27_STATUS__IMMEDIATE_READINESS__SHIFT
113511. BIF_CFG_DEV0_EPF0_VF27_STATUS__INT_STATUS_MASK
113512. BIF_CFG_DEV0_EPF0_VF27_STATUS__INT_STATUS__SHIFT
113513. BIF_CFG_DEV0_EPF0_VF27_STATUS__MASTER_DATA_PARITY_ERROR_MASK
113514. BIF_CFG_DEV0_EPF0_VF27_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
113515. BIF_CFG_DEV0_EPF0_VF27_STATUS__PARITY_ERROR_DETECTED_MASK
113516. BIF_CFG_DEV0_EPF0_VF27_STATUS__PARITY_ERROR_DETECTED__SHIFT
113517. BIF_CFG_DEV0_EPF0_VF27_STATUS__PCI_66_CAP_MASK
113518. BIF_CFG_DEV0_EPF0_VF27_STATUS__PCI_66_CAP__SHIFT
113519. BIF_CFG_DEV0_EPF0_VF27_STATUS__RECEIVED_MASTER_ABORT_MASK
113520. BIF_CFG_DEV0_EPF0_VF27_STATUS__RECEIVED_MASTER_ABORT__SHIFT
113521. BIF_CFG_DEV0_EPF0_VF27_STATUS__RECEIVED_TARGET_ABORT_MASK
113522. BIF_CFG_DEV0_EPF0_VF27_STATUS__RECEIVED_TARGET_ABORT__SHIFT
113523. BIF_CFG_DEV0_EPF0_VF27_STATUS__SIGNALED_SYSTEM_ERROR_MASK
113524. BIF_CFG_DEV0_EPF0_VF27_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
113525. BIF_CFG_DEV0_EPF0_VF27_STATUS__SIGNAL_TARGET_ABORT_MASK
113526. BIF_CFG_DEV0_EPF0_VF27_STATUS__SIGNAL_TARGET_ABORT__SHIFT
113527. BIF_CFG_DEV0_EPF0_VF27_SUB_CLASS__SUB_CLASS_MASK
113528. BIF_CFG_DEV0_EPF0_VF27_SUB_CLASS__SUB_CLASS__SHIFT
113529. BIF_CFG_DEV0_EPF0_VF27_VENDOR_ID__VENDOR_ID_MASK
113530. BIF_CFG_DEV0_EPF0_VF27_VENDOR_ID__VENDOR_ID__SHIFT
113531. BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
113532. BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
113533. BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
113534. BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
113535. BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1__BASE_ADDR_MASK
113536. BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1__BASE_ADDR__SHIFT
113537. BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2__BASE_ADDR_MASK
113538. BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2__BASE_ADDR__SHIFT
113539. BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3__BASE_ADDR_MASK
113540. BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3__BASE_ADDR__SHIFT
113541. BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4__BASE_ADDR_MASK
113542. BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4__BASE_ADDR__SHIFT
113543. BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5__BASE_ADDR_MASK
113544. BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5__BASE_ADDR__SHIFT
113545. BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6__BASE_ADDR_MASK
113546. BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6__BASE_ADDR__SHIFT
113547. BIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS__BASE_CLASS_MASK
113548. BIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS__BASE_CLASS__SHIFT
113549. BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_CAP_MASK
113550. BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_CAP__SHIFT
113551. BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_COMP_MASK
113552. BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_COMP__SHIFT
113553. BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_STRT_MASK
113554. BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_STRT__SHIFT
113555. BIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
113556. BIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
113557. BIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR__CAP_PTR_MASK
113558. BIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR__CAP_PTR__SHIFT
113559. BIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
113560. BIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
113561. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__AD_STEPPING_MASK
113562. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__AD_STEPPING__SHIFT
113563. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__BUS_MASTER_EN_MASK
113564. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__BUS_MASTER_EN__SHIFT
113565. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__FAST_B2B_EN_MASK
113566. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__FAST_B2B_EN__SHIFT
113567. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__INT_DIS_MASK
113568. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__INT_DIS__SHIFT
113569. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__IO_ACCESS_EN_MASK
113570. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__IO_ACCESS_EN__SHIFT
113571. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__MEM_ACCESS_EN_MASK
113572. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__MEM_ACCESS_EN__SHIFT
113573. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
113574. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
113575. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__PAL_SNOOP_EN_MASK
113576. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__PAL_SNOOP_EN__SHIFT
113577. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
113578. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
113579. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__SERR_EN_MASK
113580. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__SERR_EN__SHIFT
113581. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__SPECIAL_CYCLE_EN_MASK
113582. BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
113583. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
113584. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
113585. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
113586. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
113587. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
113588. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
113589. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
113590. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
113591. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
113592. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
113593. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
113594. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
113595. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
113596. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
113597. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
113598. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
113599. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
113600. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
113601. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
113602. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
113603. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
113604. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
113605. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
113606. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
113607. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
113608. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
113609. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
113610. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
113611. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
113612. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
113613. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
113614. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
113615. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
113616. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
113617. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
113618. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
113619. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
113620. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
113621. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
113622. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
113623. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
113624. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
113625. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
113626. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
113627. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__EXTENDED_TAG_MASK
113628. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
113629. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__FLR_CAPABLE_MASK
113630. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
113631. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
113632. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
113633. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
113634. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
113635. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
113636. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
113637. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__PHANTOM_FUNC_MASK
113638. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
113639. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
113640. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
113641. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
113642. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
113643. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
113644. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
113645. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
113646. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
113647. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
113648. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
113649. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
113650. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
113651. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
113652. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
113653. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
113654. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
113655. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
113656. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
113657. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
113658. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
113659. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__LTR_EN_MASK
113660. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__LTR_EN__SHIFT
113661. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__OBFF_EN_MASK
113662. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__OBFF_EN__SHIFT
113663. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
113664. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
113665. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
113666. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
113667. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__CORR_ERR_EN_MASK
113668. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
113669. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
113670. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
113671. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
113672. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
113673. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__INITIATE_FLR_MASK
113674. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
113675. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
113676. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
113677. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
113678. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
113679. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
113680. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
113681. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
113682. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
113683. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
113684. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
113685. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
113686. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
113687. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__USR_REPORT_EN_MASK
113688. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
113689. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID__DEVICE_ID_MASK
113690. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID__DEVICE_ID__SHIFT
113691. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2__RESERVED_MASK
113692. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2__RESERVED__SHIFT
113693. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__AUX_PWR_MASK
113694. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__AUX_PWR__SHIFT
113695. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__CORR_ERR_MASK
113696. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__CORR_ERR__SHIFT
113697. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
113698. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
113699. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__FATAL_ERR_MASK
113700. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__FATAL_ERR__SHIFT
113701. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
113702. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
113703. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
113704. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
113705. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__USR_DETECTED_MASK
113706. BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__USR_DETECTED__SHIFT
113707. BIF_CFG_DEV0_EPF0_VF28_0_HEADER__DEVICE_TYPE_MASK
113708. BIF_CFG_DEV0_EPF0_VF28_0_HEADER__DEVICE_TYPE__SHIFT
113709. BIF_CFG_DEV0_EPF0_VF28_0_HEADER__HEADER_TYPE_MASK
113710. BIF_CFG_DEV0_EPF0_VF28_0_HEADER__HEADER_TYPE__SHIFT
113711. BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
113712. BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
113713. BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
113714. BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
113715. BIF_CFG_DEV0_EPF0_VF28_0_LATENCY__LATENCY_TIMER_MASK
113716. BIF_CFG_DEV0_EPF0_VF28_0_LATENCY__LATENCY_TIMER__SHIFT
113717. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
113718. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
113719. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
113720. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
113721. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
113722. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
113723. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
113724. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
113725. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
113726. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
113727. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
113728. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
113729. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
113730. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
113731. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
113732. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
113733. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
113734. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
113735. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
113736. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
113737. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
113738. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
113739. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__L1_EXIT_LATENCY_MASK
113740. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
113741. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
113742. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
113743. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_SPEED_MASK
113744. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_SPEED__SHIFT
113745. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_WIDTH_MASK
113746. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_WIDTH__SHIFT
113747. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__PM_SUPPORT_MASK
113748. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__PM_SUPPORT__SHIFT
113749. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__PORT_NUMBER_MASK
113750. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__PORT_NUMBER__SHIFT
113751. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
113752. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
113753. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
113754. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
113755. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
113756. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
113757. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
113758. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
113759. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
113760. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
113761. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
113762. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
113763. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
113764. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
113765. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
113766. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
113767. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__XMIT_MARGIN_MASK
113768. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
113769. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
113770. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
113771. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
113772. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
113773. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
113774. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
113775. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__EXTENDED_SYNC_MASK
113776. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
113777. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
113778. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
113779. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
113780. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
113781. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
113782. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
113783. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_DIS_MASK
113784. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_DIS__SHIFT
113785. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__PM_CONTROL_MASK
113786. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__PM_CONTROL__SHIFT
113787. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
113788. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
113789. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__RETRAIN_LINK_MASK
113790. BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__RETRAIN_LINK__SHIFT
113791. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
113792. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
113793. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
113794. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
113795. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
113796. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
113797. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
113798. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
113799. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
113800. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
113801. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
113802. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
113803. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
113804. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
113805. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
113806. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
113807. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
113808. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
113809. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
113810. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
113811. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
113812. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
113813. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
113814. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
113815. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__DL_ACTIVE_MASK
113816. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__DL_ACTIVE__SHIFT
113817. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
113818. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
113819. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
113820. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
113821. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_TRAINING_MASK
113822. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_TRAINING__SHIFT
113823. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
113824. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
113825. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
113826. BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
113827. BIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY__MAX_LAT_MASK
113828. BIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY__MAX_LAT__SHIFT
113829. BIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT__MIN_GNT_MASK
113830. BIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT__MIN_GNT__SHIFT
113831. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST__CAP_ID_MASK
113832. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST__CAP_ID__SHIFT
113833. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST__NEXT_PTR_MASK
113834. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
113835. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_EN_MASK
113836. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
113837. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
113838. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
113839. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
113840. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
113841. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA__MSIX_PBA_BIR_MASK
113842. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
113843. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
113844. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
113845. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
113846. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
113847. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
113848. BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
113849. BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST__CAP_ID_MASK
113850. BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST__CAP_ID__SHIFT
113851. BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST__NEXT_PTR_MASK
113852. BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
113853. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64__MSI_MASK_64_MASK
113854. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64__MSI_MASK_64__SHIFT
113855. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK__MSI_MASK_MASK
113856. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK__MSI_MASK__SHIFT
113857. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
113858. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
113859. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
113860. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
113861. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_64BIT_MASK
113862. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
113863. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_EN_MASK
113864. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_EN__SHIFT
113865. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
113866. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
113867. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
113868. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
113869. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
113870. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
113871. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
113872. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
113873. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA__MSI_DATA_MASK
113874. BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA__MSI_DATA__SHIFT
113875. BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64__MSI_PENDING_64_MASK
113876. BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
113877. BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING__MSI_PENDING_MASK
113878. BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING__MSI_PENDING__SHIFT
113879. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
113880. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
113881. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
113882. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
113883. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
113884. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
113885. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
113886. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
113887. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
113888. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
113889. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
113890. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
113891. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
113892. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
113893. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
113894. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
113895. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
113896. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
113897. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
113898. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
113899. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
113900. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
113901. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
113902. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
113903. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
113904. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
113905. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
113906. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
113907. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
113908. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
113909. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
113910. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
113911. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
113912. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
113913. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
113914. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
113915. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
113916. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
113917. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
113918. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
113919. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
113920. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
113921. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
113922. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
113923. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
113924. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
113925. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
113926. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
113927. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
113928. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
113929. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL__STU_MASK
113930. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL__STU__SHIFT
113931. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
113932. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
113933. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
113934. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
113935. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
113936. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
113937. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST__CAP_ID_MASK
113938. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST__CAP_ID__SHIFT
113939. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST__NEXT_PTR_MASK
113940. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
113941. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__DEVICE_TYPE_MASK
113942. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__DEVICE_TYPE__SHIFT
113943. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
113944. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
113945. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
113946. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
113947. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__VERSION_MASK
113948. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__VERSION__SHIFT
113949. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
113950. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
113951. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
113952. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
113953. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
113954. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
113955. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
113956. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
113957. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
113958. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
113959. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
113960. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
113961. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
113962. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
113963. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
113964. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
113965. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
113966. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
113967. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
113968. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
113969. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
113970. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
113971. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
113972. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
113973. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
113974. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
113975. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
113976. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
113977. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
113978. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
113979. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
113980. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
113981. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0__TLP_HDR_MASK
113982. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
113983. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1__TLP_HDR_MASK
113984. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
113985. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2__TLP_HDR_MASK
113986. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
113987. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3__TLP_HDR_MASK
113988. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
113989. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
113990. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
113991. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
113992. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
113993. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
113994. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
113995. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
113996. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
113997. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
113998. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
113999. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
114000. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
114001. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
114002. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
114003. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
114004. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
114005. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
114006. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
114007. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
114008. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
114009. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
114010. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
114011. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
114012. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
114013. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
114014. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
114015. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
114016. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
114017. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
114018. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
114019. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
114020. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
114021. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
114022. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
114023. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
114024. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
114025. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
114026. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
114027. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
114028. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
114029. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
114030. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
114031. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
114032. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
114033. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
114034. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
114035. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
114036. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
114037. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
114038. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
114039. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
114040. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
114041. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
114042. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
114043. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
114044. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
114045. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
114046. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
114047. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
114048. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
114049. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
114050. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
114051. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
114052. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
114053. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
114054. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
114055. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
114056. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
114057. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
114058. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
114059. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
114060. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
114061. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
114062. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
114063. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
114064. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
114065. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
114066. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
114067. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
114068. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
114069. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
114070. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
114071. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
114072. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
114073. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
114074. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
114075. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
114076. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
114077. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
114078. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
114079. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
114080. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
114081. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
114082. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
114083. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
114084. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
114085. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
114086. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
114087. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
114088. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
114089. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
114090. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
114091. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
114092. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
114093. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
114094. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
114095. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
114096. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
114097. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
114098. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
114099. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
114100. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
114101. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
114102. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
114103. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
114104. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
114105. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
114106. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
114107. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
114108. BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
114109. BIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE__PROG_INTERFACE_MASK
114110. BIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
114111. BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID__MAJOR_REV_ID_MASK
114112. BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID__MAJOR_REV_ID__SHIFT
114113. BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID__MINOR_REV_ID_MASK
114114. BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID__MINOR_REV_ID__SHIFT
114115. BIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR__BASE_ADDR_MASK
114116. BIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
114117. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__CAP_LIST_MASK
114118. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__CAP_LIST__SHIFT
114119. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__DEVSEL_TIMING_MASK
114120. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__DEVSEL_TIMING__SHIFT
114121. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__FAST_BACK_CAPABLE_MASK
114122. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__FAST_BACK_CAPABLE__SHIFT
114123. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__IMMEDIATE_READINESS_MASK
114124. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__IMMEDIATE_READINESS__SHIFT
114125. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__INT_STATUS_MASK
114126. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__INT_STATUS__SHIFT
114127. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
114128. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
114129. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__PARITY_ERROR_DETECTED_MASK
114130. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
114131. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__PCI_66_CAP_MASK
114132. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__PCI_66_CAP__SHIFT
114133. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__RECEIVED_MASTER_ABORT_MASK
114134. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
114135. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__RECEIVED_TARGET_ABORT_MASK
114136. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
114137. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
114138. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
114139. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__SIGNAL_TARGET_ABORT_MASK
114140. BIF_CFG_DEV0_EPF0_VF28_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
114141. BIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS__SUB_CLASS_MASK
114142. BIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS__SUB_CLASS__SHIFT
114143. BIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID__VENDOR_ID_MASK
114144. BIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID__VENDOR_ID__SHIFT
114145. BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
114146. BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
114147. BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
114148. BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
114149. BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1__BASE_ADDR_MASK
114150. BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1__BASE_ADDR__SHIFT
114151. BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2__BASE_ADDR_MASK
114152. BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2__BASE_ADDR__SHIFT
114153. BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3__BASE_ADDR_MASK
114154. BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3__BASE_ADDR__SHIFT
114155. BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4__BASE_ADDR_MASK
114156. BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4__BASE_ADDR__SHIFT
114157. BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5__BASE_ADDR_MASK
114158. BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5__BASE_ADDR__SHIFT
114159. BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6__BASE_ADDR_MASK
114160. BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6__BASE_ADDR__SHIFT
114161. BIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS__BASE_CLASS_MASK
114162. BIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS__BASE_CLASS__SHIFT
114163. BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_CAP_MASK
114164. BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_CAP__SHIFT
114165. BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_COMP_MASK
114166. BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_COMP__SHIFT
114167. BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_STRT_MASK
114168. BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_STRT__SHIFT
114169. BIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
114170. BIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
114171. BIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR__CAP_PTR_MASK
114172. BIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR__CAP_PTR__SHIFT
114173. BIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
114174. BIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
114175. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__AD_STEPPING_MASK
114176. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__AD_STEPPING__SHIFT
114177. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__BUS_MASTER_EN_MASK
114178. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__BUS_MASTER_EN__SHIFT
114179. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__FAST_B2B_EN_MASK
114180. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__FAST_B2B_EN__SHIFT
114181. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__INT_DIS_MASK
114182. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__INT_DIS__SHIFT
114183. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__IO_ACCESS_EN_MASK
114184. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__IO_ACCESS_EN__SHIFT
114185. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__MEM_ACCESS_EN_MASK
114186. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__MEM_ACCESS_EN__SHIFT
114187. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
114188. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
114189. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__PAL_SNOOP_EN_MASK
114190. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__PAL_SNOOP_EN__SHIFT
114191. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
114192. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
114193. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__SERR_EN_MASK
114194. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__SERR_EN__SHIFT
114195. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__SPECIAL_CYCLE_EN_MASK
114196. BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
114197. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
114198. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
114199. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
114200. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
114201. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
114202. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
114203. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
114204. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
114205. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
114206. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
114207. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
114208. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
114209. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
114210. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
114211. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
114212. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
114213. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
114214. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
114215. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
114216. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
114217. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
114218. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
114219. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
114220. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
114221. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
114222. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
114223. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
114224. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
114225. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
114226. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
114227. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
114228. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
114229. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
114230. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
114231. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
114232. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
114233. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
114234. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
114235. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
114236. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
114237. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
114238. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
114239. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
114240. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
114241. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__EXTENDED_TAG_MASK
114242. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
114243. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__FLR_CAPABLE_MASK
114244. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
114245. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
114246. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
114247. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
114248. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
114249. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
114250. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
114251. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__PHANTOM_FUNC_MASK
114252. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
114253. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
114254. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
114255. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
114256. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
114257. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
114258. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
114259. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
114260. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
114261. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
114262. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
114263. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
114264. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
114265. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
114266. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
114267. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
114268. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
114269. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
114270. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
114271. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
114272. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
114273. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__LTR_EN_MASK
114274. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__LTR_EN__SHIFT
114275. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__OBFF_EN_MASK
114276. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__OBFF_EN__SHIFT
114277. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
114278. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
114279. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
114280. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
114281. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__CORR_ERR_EN_MASK
114282. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
114283. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
114284. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
114285. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
114286. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
114287. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__INITIATE_FLR_MASK
114288. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
114289. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
114290. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
114291. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
114292. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
114293. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
114294. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
114295. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
114296. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
114297. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
114298. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
114299. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
114300. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
114301. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__USR_REPORT_EN_MASK
114302. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
114303. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID__DEVICE_ID_MASK
114304. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID__DEVICE_ID__SHIFT
114305. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2__RESERVED_MASK
114306. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2__RESERVED__SHIFT
114307. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__AUX_PWR_MASK
114308. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__AUX_PWR__SHIFT
114309. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__CORR_ERR_MASK
114310. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__CORR_ERR__SHIFT
114311. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
114312. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
114313. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__FATAL_ERR_MASK
114314. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__FATAL_ERR__SHIFT
114315. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
114316. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
114317. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
114318. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
114319. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__USR_DETECTED_MASK
114320. BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__USR_DETECTED__SHIFT
114321. BIF_CFG_DEV0_EPF0_VF28_1_HEADER__DEVICE_TYPE_MASK
114322. BIF_CFG_DEV0_EPF0_VF28_1_HEADER__DEVICE_TYPE__SHIFT
114323. BIF_CFG_DEV0_EPF0_VF28_1_HEADER__HEADER_TYPE_MASK
114324. BIF_CFG_DEV0_EPF0_VF28_1_HEADER__HEADER_TYPE__SHIFT
114325. BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
114326. BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
114327. BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
114328. BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
114329. BIF_CFG_DEV0_EPF0_VF28_1_LATENCY__LATENCY_TIMER_MASK
114330. BIF_CFG_DEV0_EPF0_VF28_1_LATENCY__LATENCY_TIMER__SHIFT
114331. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
114332. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
114333. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
114334. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
114335. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
114336. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
114337. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
114338. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
114339. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
114340. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
114341. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
114342. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
114343. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
114344. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
114345. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
114346. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
114347. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
114348. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
114349. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
114350. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
114351. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
114352. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
114353. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__L1_EXIT_LATENCY_MASK
114354. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
114355. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
114356. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
114357. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_SPEED_MASK
114358. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_SPEED__SHIFT
114359. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_WIDTH_MASK
114360. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_WIDTH__SHIFT
114361. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__PM_SUPPORT_MASK
114362. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__PM_SUPPORT__SHIFT
114363. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__PORT_NUMBER_MASK
114364. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__PORT_NUMBER__SHIFT
114365. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
114366. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
114367. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
114368. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
114369. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
114370. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
114371. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
114372. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
114373. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
114374. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
114375. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
114376. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
114377. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
114378. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
114379. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
114380. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
114381. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__XMIT_MARGIN_MASK
114382. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
114383. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
114384. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
114385. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
114386. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
114387. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
114388. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
114389. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__EXTENDED_SYNC_MASK
114390. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
114391. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
114392. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
114393. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
114394. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
114395. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
114396. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
114397. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_DIS_MASK
114398. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_DIS__SHIFT
114399. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__PM_CONTROL_MASK
114400. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__PM_CONTROL__SHIFT
114401. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
114402. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
114403. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__RETRAIN_LINK_MASK
114404. BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__RETRAIN_LINK__SHIFT
114405. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
114406. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
114407. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
114408. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
114409. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
114410. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
114411. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
114412. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
114413. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
114414. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
114415. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
114416. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
114417. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
114418. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
114419. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
114420. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
114421. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
114422. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
114423. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
114424. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
114425. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
114426. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
114427. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
114428. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
114429. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__DL_ACTIVE_MASK
114430. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__DL_ACTIVE__SHIFT
114431. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
114432. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
114433. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
114434. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
114435. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_TRAINING_MASK
114436. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_TRAINING__SHIFT
114437. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
114438. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
114439. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
114440. BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
114441. BIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY__MAX_LAT_MASK
114442. BIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY__MAX_LAT__SHIFT
114443. BIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT__MIN_GNT_MASK
114444. BIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT__MIN_GNT__SHIFT
114445. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST__CAP_ID_MASK
114446. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST__CAP_ID__SHIFT
114447. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST__NEXT_PTR_MASK
114448. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
114449. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_EN_MASK
114450. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
114451. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
114452. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
114453. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
114454. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
114455. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA__MSIX_PBA_BIR_MASK
114456. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
114457. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
114458. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
114459. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
114460. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
114461. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
114462. BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
114463. BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST__CAP_ID_MASK
114464. BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST__CAP_ID__SHIFT
114465. BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST__NEXT_PTR_MASK
114466. BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
114467. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64__MSI_MASK_64_MASK
114468. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64__MSI_MASK_64__SHIFT
114469. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK__MSI_MASK_MASK
114470. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK__MSI_MASK__SHIFT
114471. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
114472. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
114473. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
114474. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
114475. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_64BIT_MASK
114476. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
114477. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_EN_MASK
114478. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_EN__SHIFT
114479. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
114480. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
114481. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
114482. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
114483. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
114484. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
114485. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
114486. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
114487. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA__MSI_DATA_MASK
114488. BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA__MSI_DATA__SHIFT
114489. BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64__MSI_PENDING_64_MASK
114490. BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
114491. BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING__MSI_PENDING_MASK
114492. BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING__MSI_PENDING__SHIFT
114493. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
114494. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
114495. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
114496. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
114497. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
114498. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
114499. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
114500. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
114501. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
114502. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
114503. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
114504. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
114505. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
114506. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
114507. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
114508. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
114509. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
114510. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
114511. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
114512. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
114513. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
114514. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
114515. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
114516. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
114517. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
114518. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
114519. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
114520. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
114521. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
114522. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
114523. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
114524. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
114525. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
114526. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
114527. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
114528. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
114529. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
114530. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
114531. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
114532. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
114533. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
114534. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
114535. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
114536. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
114537. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
114538. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
114539. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
114540. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
114541. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
114542. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
114543. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL__STU_MASK
114544. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL__STU__SHIFT
114545. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
114546. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
114547. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
114548. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
114549. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
114550. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
114551. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST__CAP_ID_MASK
114552. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST__CAP_ID__SHIFT
114553. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST__NEXT_PTR_MASK
114554. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
114555. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__DEVICE_TYPE_MASK
114556. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__DEVICE_TYPE__SHIFT
114557. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
114558. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
114559. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
114560. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
114561. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__VERSION_MASK
114562. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__VERSION__SHIFT
114563. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
114564. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
114565. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
114566. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
114567. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
114568. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
114569. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
114570. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
114571. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
114572. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
114573. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
114574. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
114575. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
114576. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
114577. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
114578. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
114579. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
114580. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
114581. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
114582. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
114583. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
114584. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
114585. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
114586. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
114587. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
114588. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
114589. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
114590. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
114591. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
114592. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
114593. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
114594. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
114595. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0__TLP_HDR_MASK
114596. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
114597. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1__TLP_HDR_MASK
114598. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
114599. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2__TLP_HDR_MASK
114600. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
114601. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3__TLP_HDR_MASK
114602. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
114603. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
114604. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
114605. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
114606. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
114607. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
114608. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
114609. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
114610. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
114611. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
114612. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
114613. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
114614. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
114615. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
114616. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
114617. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
114618. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
114619. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
114620. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
114621. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
114622. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
114623. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
114624. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
114625. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
114626. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
114627. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
114628. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
114629. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
114630. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
114631. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
114632. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
114633. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
114634. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
114635. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
114636. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
114637. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
114638. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
114639. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
114640. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
114641. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
114642. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
114643. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
114644. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
114645. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
114646. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
114647. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
114648. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
114649. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
114650. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
114651. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
114652. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
114653. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
114654. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
114655. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
114656. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
114657. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
114658. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
114659. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
114660. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
114661. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
114662. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
114663. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
114664. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
114665. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
114666. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
114667. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
114668. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
114669. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
114670. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
114671. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
114672. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
114673. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
114674. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
114675. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
114676. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
114677. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
114678. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
114679. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
114680. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
114681. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
114682. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
114683. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
114684. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
114685. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
114686. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
114687. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
114688. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
114689. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
114690. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
114691. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
114692. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
114693. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
114694. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
114695. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
114696. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
114697. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
114698. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
114699. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
114700. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
114701. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
114702. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
114703. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
114704. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
114705. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
114706. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
114707. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
114708. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
114709. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
114710. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
114711. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
114712. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
114713. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
114714. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
114715. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
114716. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
114717. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
114718. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
114719. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
114720. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
114721. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
114722. BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
114723. BIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE__PROG_INTERFACE_MASK
114724. BIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
114725. BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID__MAJOR_REV_ID_MASK
114726. BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID__MAJOR_REV_ID__SHIFT
114727. BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID__MINOR_REV_ID_MASK
114728. BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID__MINOR_REV_ID__SHIFT
114729. BIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR__BASE_ADDR_MASK
114730. BIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
114731. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__CAP_LIST_MASK
114732. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__CAP_LIST__SHIFT
114733. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__DEVSEL_TIMING_MASK
114734. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__DEVSEL_TIMING__SHIFT
114735. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__FAST_BACK_CAPABLE_MASK
114736. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__FAST_BACK_CAPABLE__SHIFT
114737. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__IMMEDIATE_READINESS_MASK
114738. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__IMMEDIATE_READINESS__SHIFT
114739. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__INT_STATUS_MASK
114740. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__INT_STATUS__SHIFT
114741. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
114742. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
114743. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__PARITY_ERROR_DETECTED_MASK
114744. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
114745. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__PCI_66_CAP_MASK
114746. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__PCI_66_CAP__SHIFT
114747. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__RECEIVED_MASTER_ABORT_MASK
114748. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
114749. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__RECEIVED_TARGET_ABORT_MASK
114750. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
114751. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
114752. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
114753. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__SIGNAL_TARGET_ABORT_MASK
114754. BIF_CFG_DEV0_EPF0_VF28_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
114755. BIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS__SUB_CLASS_MASK
114756. BIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS__SUB_CLASS__SHIFT
114757. BIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID__VENDOR_ID_MASK
114758. BIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID__VENDOR_ID__SHIFT
114759. BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID__SUBSYSTEM_ID_MASK
114760. BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
114761. BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
114762. BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
114763. BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_1__BASE_ADDR_MASK
114764. BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_1__BASE_ADDR__SHIFT
114765. BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_2__BASE_ADDR_MASK
114766. BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_2__BASE_ADDR__SHIFT
114767. BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_3__BASE_ADDR_MASK
114768. BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_3__BASE_ADDR__SHIFT
114769. BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_4__BASE_ADDR_MASK
114770. BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_4__BASE_ADDR__SHIFT
114771. BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_5__BASE_ADDR_MASK
114772. BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_5__BASE_ADDR__SHIFT
114773. BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_6__BASE_ADDR_MASK
114774. BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_6__BASE_ADDR__SHIFT
114775. BIF_CFG_DEV0_EPF0_VF28_BASE_CLASS__BASE_CLASS_MASK
114776. BIF_CFG_DEV0_EPF0_VF28_BASE_CLASS__BASE_CLASS__SHIFT
114777. BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_CAP_MASK
114778. BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_CAP__SHIFT
114779. BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_COMP_MASK
114780. BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_COMP__SHIFT
114781. BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_STRT_MASK
114782. BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_STRT__SHIFT
114783. BIF_CFG_DEV0_EPF0_VF28_CACHE_LINE__CACHE_LINE_SIZE_MASK
114784. BIF_CFG_DEV0_EPF0_VF28_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
114785. BIF_CFG_DEV0_EPF0_VF28_CAP_PTR__CAP_PTR_MASK
114786. BIF_CFG_DEV0_EPF0_VF28_CAP_PTR__CAP_PTR__SHIFT
114787. BIF_CFG_DEV0_EPF0_VF28_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
114788. BIF_CFG_DEV0_EPF0_VF28_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
114789. BIF_CFG_DEV0_EPF0_VF28_COMMAND__AD_STEPPING_MASK
114790. BIF_CFG_DEV0_EPF0_VF28_COMMAND__AD_STEPPING__SHIFT
114791. BIF_CFG_DEV0_EPF0_VF28_COMMAND__BUS_MASTER_EN_MASK
114792. BIF_CFG_DEV0_EPF0_VF28_COMMAND__BUS_MASTER_EN__SHIFT
114793. BIF_CFG_DEV0_EPF0_VF28_COMMAND__FAST_B2B_EN_MASK
114794. BIF_CFG_DEV0_EPF0_VF28_COMMAND__FAST_B2B_EN__SHIFT
114795. BIF_CFG_DEV0_EPF0_VF28_COMMAND__INT_DIS_MASK
114796. BIF_CFG_DEV0_EPF0_VF28_COMMAND__INT_DIS__SHIFT
114797. BIF_CFG_DEV0_EPF0_VF28_COMMAND__IO_ACCESS_EN_MASK
114798. BIF_CFG_DEV0_EPF0_VF28_COMMAND__IO_ACCESS_EN__SHIFT
114799. BIF_CFG_DEV0_EPF0_VF28_COMMAND__MEM_ACCESS_EN_MASK
114800. BIF_CFG_DEV0_EPF0_VF28_COMMAND__MEM_ACCESS_EN__SHIFT
114801. BIF_CFG_DEV0_EPF0_VF28_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
114802. BIF_CFG_DEV0_EPF0_VF28_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
114803. BIF_CFG_DEV0_EPF0_VF28_COMMAND__PAL_SNOOP_EN_MASK
114804. BIF_CFG_DEV0_EPF0_VF28_COMMAND__PAL_SNOOP_EN__SHIFT
114805. BIF_CFG_DEV0_EPF0_VF28_COMMAND__PARITY_ERROR_RESPONSE_MASK
114806. BIF_CFG_DEV0_EPF0_VF28_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
114807. BIF_CFG_DEV0_EPF0_VF28_COMMAND__SERR_EN_MASK
114808. BIF_CFG_DEV0_EPF0_VF28_COMMAND__SERR_EN__SHIFT
114809. BIF_CFG_DEV0_EPF0_VF28_COMMAND__SPECIAL_CYCLE_EN_MASK
114810. BIF_CFG_DEV0_EPF0_VF28_COMMAND__SPECIAL_CYCLE_EN__SHIFT
114811. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
114812. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
114813. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
114814. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
114815. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
114816. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
114817. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
114818. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
114819. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
114820. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
114821. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
114822. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
114823. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
114824. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
114825. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
114826. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
114827. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
114828. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
114829. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
114830. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
114831. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
114832. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
114833. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__FRS_SUPPORTED_MASK
114834. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
114835. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
114836. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
114837. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__LTR_SUPPORTED_MASK
114838. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
114839. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
114840. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
114841. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
114842. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
114843. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__OBFF_SUPPORTED_MASK
114844. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
114845. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
114846. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
114847. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
114848. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
114849. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
114850. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
114851. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
114852. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
114853. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
114854. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
114855. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__EXTENDED_TAG_MASK
114856. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__EXTENDED_TAG__SHIFT
114857. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__FLR_CAPABLE_MASK
114858. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__FLR_CAPABLE__SHIFT
114859. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
114860. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
114861. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
114862. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
114863. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
114864. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
114865. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__PHANTOM_FUNC_MASK
114866. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__PHANTOM_FUNC__SHIFT
114867. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
114868. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
114869. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
114870. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
114871. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
114872. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
114873. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
114874. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
114875. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
114876. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
114877. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
114878. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
114879. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
114880. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
114881. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
114882. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
114883. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
114884. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
114885. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
114886. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
114887. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__LTR_EN_MASK
114888. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__LTR_EN__SHIFT
114889. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__OBFF_EN_MASK
114890. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__OBFF_EN__SHIFT
114891. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
114892. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
114893. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
114894. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
114895. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__CORR_ERR_EN_MASK
114896. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__CORR_ERR_EN__SHIFT
114897. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
114898. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
114899. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__FATAL_ERR_EN_MASK
114900. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
114901. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__INITIATE_FLR_MASK
114902. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__INITIATE_FLR__SHIFT
114903. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
114904. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
114905. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
114906. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
114907. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
114908. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
114909. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__NO_SNOOP_EN_MASK
114910. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
114911. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
114912. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
114913. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__RELAXED_ORD_EN_MASK
114914. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
114915. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__USR_REPORT_EN_MASK
114916. BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__USR_REPORT_EN__SHIFT
114917. BIF_CFG_DEV0_EPF0_VF28_DEVICE_ID__DEVICE_ID_MASK
114918. BIF_CFG_DEV0_EPF0_VF28_DEVICE_ID__DEVICE_ID__SHIFT
114919. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS2__RESERVED_MASK
114920. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS2__RESERVED__SHIFT
114921. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__AUX_PWR_MASK
114922. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__AUX_PWR__SHIFT
114923. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__CORR_ERR_MASK
114924. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__CORR_ERR__SHIFT
114925. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
114926. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
114927. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__FATAL_ERR_MASK
114928. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__FATAL_ERR__SHIFT
114929. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__NON_FATAL_ERR_MASK
114930. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
114931. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
114932. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
114933. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__USR_DETECTED_MASK
114934. BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__USR_DETECTED__SHIFT
114935. BIF_CFG_DEV0_EPF0_VF28_HEADER__DEVICE_TYPE_MASK
114936. BIF_CFG_DEV0_EPF0_VF28_HEADER__DEVICE_TYPE__SHIFT
114937. BIF_CFG_DEV0_EPF0_VF28_HEADER__HEADER_TYPE_MASK
114938. BIF_CFG_DEV0_EPF0_VF28_HEADER__HEADER_TYPE__SHIFT
114939. BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_LINE__INTERRUPT_LINE_MASK
114940. BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
114941. BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_PIN__INTERRUPT_PIN_MASK
114942. BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
114943. BIF_CFG_DEV0_EPF0_VF28_LATENCY__LATENCY_TIMER_MASK
114944. BIF_CFG_DEV0_EPF0_VF28_LATENCY__LATENCY_TIMER__SHIFT
114945. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
114946. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
114947. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
114948. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
114949. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
114950. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
114951. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
114952. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
114953. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
114954. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
114955. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
114956. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
114957. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
114958. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
114959. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
114960. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
114961. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
114962. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
114963. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
114964. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
114965. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__L0S_EXIT_LATENCY_MASK
114966. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
114967. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__L1_EXIT_LATENCY_MASK
114968. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__L1_EXIT_LATENCY__SHIFT
114969. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
114970. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
114971. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_SPEED_MASK
114972. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_SPEED__SHIFT
114973. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_WIDTH_MASK
114974. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_WIDTH__SHIFT
114975. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__PM_SUPPORT_MASK
114976. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__PM_SUPPORT__SHIFT
114977. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__PORT_NUMBER_MASK
114978. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__PORT_NUMBER__SHIFT
114979. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
114980. BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
114981. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
114982. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
114983. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__COMPLIANCE_SOS_MASK
114984. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
114985. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__ENTER_COMPLIANCE_MASK
114986. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
114987. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
114988. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
114989. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
114990. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
114991. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
114992. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
114993. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__TARGET_LINK_SPEED_MASK
114994. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
114995. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__XMIT_MARGIN_MASK
114996. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__XMIT_MARGIN__SHIFT
114997. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
114998. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
114999. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__COMMON_CLOCK_CFG_MASK
115000. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
115001. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
115002. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
115003. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__EXTENDED_SYNC_MASK
115004. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__EXTENDED_SYNC__SHIFT
115005. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
115006. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
115007. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
115008. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
115009. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
115010. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
115011. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_DIS_MASK
115012. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_DIS__SHIFT
115013. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__PM_CONTROL_MASK
115014. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__PM_CONTROL__SHIFT
115015. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__READ_CPL_BOUNDARY_MASK
115016. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
115017. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__RETRAIN_LINK_MASK
115018. BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__RETRAIN_LINK__SHIFT
115019. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
115020. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
115021. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
115022. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
115023. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
115024. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
115025. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
115026. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
115027. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
115028. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
115029. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
115030. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
115031. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
115032. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
115033. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
115034. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
115035. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
115036. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
115037. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
115038. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
115039. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
115040. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
115041. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__CURRENT_LINK_SPEED_MASK
115042. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
115043. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__DL_ACTIVE_MASK
115044. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__DL_ACTIVE__SHIFT
115045. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
115046. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
115047. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
115048. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
115049. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_TRAINING_MASK
115050. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_TRAINING__SHIFT
115051. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
115052. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
115053. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__SLOT_CLOCK_CFG_MASK
115054. BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
115055. BIF_CFG_DEV0_EPF0_VF28_MAX_LATENCY__MAX_LAT_MASK
115056. BIF_CFG_DEV0_EPF0_VF28_MAX_LATENCY__MAX_LAT__SHIFT
115057. BIF_CFG_DEV0_EPF0_VF28_MIN_GRANT__MIN_GNT_MASK
115058. BIF_CFG_DEV0_EPF0_VF28_MIN_GRANT__MIN_GNT__SHIFT
115059. BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST__CAP_ID_MASK
115060. BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST__CAP_ID__SHIFT
115061. BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST__NEXT_PTR_MASK
115062. BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST__NEXT_PTR__SHIFT
115063. BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_EN_MASK
115064. BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_EN__SHIFT
115065. BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
115066. BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
115067. BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
115068. BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
115069. BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA__MSIX_PBA_BIR_MASK
115070. BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA__MSIX_PBA_BIR__SHIFT
115071. BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA__MSIX_PBA_OFFSET_MASK
115072. BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
115073. BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE__MSIX_TABLE_BIR_MASK
115074. BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
115075. BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
115076. BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
115077. BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST__CAP_ID_MASK
115078. BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST__CAP_ID__SHIFT
115079. BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST__NEXT_PTR_MASK
115080. BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST__NEXT_PTR__SHIFT
115081. BIF_CFG_DEV0_EPF0_VF28_MSI_MASK_64__MSI_MASK_64_MASK
115082. BIF_CFG_DEV0_EPF0_VF28_MSI_MASK_64__MSI_MASK_64__SHIFT
115083. BIF_CFG_DEV0_EPF0_VF28_MSI_MASK__MSI_MASK_MASK
115084. BIF_CFG_DEV0_EPF0_VF28_MSI_MASK__MSI_MASK__SHIFT
115085. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
115086. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
115087. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
115088. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
115089. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_64BIT_MASK
115090. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_64BIT__SHIFT
115091. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_EN_MASK
115092. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_EN__SHIFT
115093. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
115094. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
115095. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
115096. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
115097. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
115098. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
115099. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA_64__MSI_DATA_64_MASK
115100. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
115101. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA__MSI_DATA_MASK
115102. BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA__MSI_DATA__SHIFT
115103. BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING_64__MSI_PENDING_64_MASK
115104. BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING_64__MSI_PENDING_64__SHIFT
115105. BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING__MSI_PENDING_MASK
115106. BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING__MSI_PENDING__SHIFT
115107. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
115108. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
115109. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
115110. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
115111. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
115112. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
115113. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
115114. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
115115. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
115116. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
115117. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
115118. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
115119. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
115120. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
115121. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
115122. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
115123. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
115124. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
115125. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
115126. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
115127. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
115128. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
115129. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
115130. BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
115131. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
115132. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
115133. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
115134. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
115135. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
115136. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
115137. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
115138. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
115139. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
115140. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
115141. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
115142. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
115143. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
115144. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
115145. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
115146. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
115147. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
115148. BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
115149. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
115150. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
115151. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
115152. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
115153. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
115154. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
115155. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL__ATC_ENABLE_MASK
115156. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
115157. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL__STU_MASK
115158. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL__STU__SHIFT
115159. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
115160. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
115161. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
115162. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
115163. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
115164. BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
115165. BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST__CAP_ID_MASK
115166. BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST__CAP_ID__SHIFT
115167. BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST__NEXT_PTR_MASK
115168. BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST__NEXT_PTR__SHIFT
115169. BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__DEVICE_TYPE_MASK
115170. BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__DEVICE_TYPE__SHIFT
115171. BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__INT_MESSAGE_NUM_MASK
115172. BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
115173. BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__SLOT_IMPLEMENTED_MASK
115174. BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
115175. BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__VERSION_MASK
115176. BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__VERSION__SHIFT
115177. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
115178. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
115179. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
115180. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
115181. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
115182. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
115183. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
115184. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
115185. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
115186. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
115187. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
115188. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
115189. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
115190. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
115191. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
115192. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
115193. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
115194. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
115195. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
115196. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
115197. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
115198. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
115199. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
115200. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
115201. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
115202. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
115203. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
115204. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
115205. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
115206. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
115207. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
115208. BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
115209. BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG0__TLP_HDR_MASK
115210. BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG0__TLP_HDR__SHIFT
115211. BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG1__TLP_HDR_MASK
115212. BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG1__TLP_HDR__SHIFT
115213. BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG2__TLP_HDR_MASK
115214. BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG2__TLP_HDR__SHIFT
115215. BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG3__TLP_HDR_MASK
115216. BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG3__TLP_HDR__SHIFT
115217. BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
115218. BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
115219. BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
115220. BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
115221. BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
115222. BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
115223. BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
115224. BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
115225. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
115226. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
115227. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
115228. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
115229. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
115230. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
115231. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
115232. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
115233. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
115234. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
115235. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
115236. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
115237. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
115238. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
115239. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
115240. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
115241. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
115242. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
115243. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
115244. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
115245. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
115246. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
115247. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
115248. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
115249. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
115250. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
115251. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
115252. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
115253. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
115254. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
115255. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
115256. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
115257. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
115258. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
115259. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
115260. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
115261. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
115262. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
115263. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
115264. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
115265. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
115266. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
115267. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
115268. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
115269. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
115270. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
115271. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
115272. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
115273. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
115274. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
115275. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
115276. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
115277. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
115278. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
115279. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
115280. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
115281. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
115282. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
115283. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
115284. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
115285. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
115286. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
115287. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
115288. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
115289. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
115290. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
115291. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
115292. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
115293. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
115294. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
115295. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
115296. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
115297. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
115298. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
115299. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
115300. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
115301. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
115302. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
115303. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
115304. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
115305. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
115306. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
115307. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
115308. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
115309. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
115310. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
115311. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
115312. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
115313. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
115314. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
115315. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
115316. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
115317. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
115318. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
115319. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
115320. BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
115321. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
115322. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
115323. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
115324. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
115325. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
115326. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
115327. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
115328. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
115329. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
115330. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
115331. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
115332. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
115333. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
115334. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
115335. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
115336. BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
115337. BIF_CFG_DEV0_EPF0_VF28_PROG_INTERFACE__PROG_INTERFACE_MASK
115338. BIF_CFG_DEV0_EPF0_VF28_PROG_INTERFACE__PROG_INTERFACE__SHIFT
115339. BIF_CFG_DEV0_EPF0_VF28_REVISION_ID__MAJOR_REV_ID_MASK
115340. BIF_CFG_DEV0_EPF0_VF28_REVISION_ID__MAJOR_REV_ID__SHIFT
115341. BIF_CFG_DEV0_EPF0_VF28_REVISION_ID__MINOR_REV_ID_MASK
115342. BIF_CFG_DEV0_EPF0_VF28_REVISION_ID__MINOR_REV_ID__SHIFT
115343. BIF_CFG_DEV0_EPF0_VF28_ROM_BASE_ADDR__BASE_ADDR_MASK
115344. BIF_CFG_DEV0_EPF0_VF28_ROM_BASE_ADDR__BASE_ADDR__SHIFT
115345. BIF_CFG_DEV0_EPF0_VF28_STATUS__CAP_LIST_MASK
115346. BIF_CFG_DEV0_EPF0_VF28_STATUS__CAP_LIST__SHIFT
115347. BIF_CFG_DEV0_EPF0_VF28_STATUS__DEVSEL_TIMING_MASK
115348. BIF_CFG_DEV0_EPF0_VF28_STATUS__DEVSEL_TIMING__SHIFT
115349. BIF_CFG_DEV0_EPF0_VF28_STATUS__FAST_BACK_CAPABLE_MASK
115350. BIF_CFG_DEV0_EPF0_VF28_STATUS__FAST_BACK_CAPABLE__SHIFT
115351. BIF_CFG_DEV0_EPF0_VF28_STATUS__IMMEDIATE_READINESS_MASK
115352. BIF_CFG_DEV0_EPF0_VF28_STATUS__IMMEDIATE_READINESS__SHIFT
115353. BIF_CFG_DEV0_EPF0_VF28_STATUS__INT_STATUS_MASK
115354. BIF_CFG_DEV0_EPF0_VF28_STATUS__INT_STATUS__SHIFT
115355. BIF_CFG_DEV0_EPF0_VF28_STATUS__MASTER_DATA_PARITY_ERROR_MASK
115356. BIF_CFG_DEV0_EPF0_VF28_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
115357. BIF_CFG_DEV0_EPF0_VF28_STATUS__PARITY_ERROR_DETECTED_MASK
115358. BIF_CFG_DEV0_EPF0_VF28_STATUS__PARITY_ERROR_DETECTED__SHIFT
115359. BIF_CFG_DEV0_EPF0_VF28_STATUS__PCI_66_CAP_MASK
115360. BIF_CFG_DEV0_EPF0_VF28_STATUS__PCI_66_CAP__SHIFT
115361. BIF_CFG_DEV0_EPF0_VF28_STATUS__RECEIVED_MASTER_ABORT_MASK
115362. BIF_CFG_DEV0_EPF0_VF28_STATUS__RECEIVED_MASTER_ABORT__SHIFT
115363. BIF_CFG_DEV0_EPF0_VF28_STATUS__RECEIVED_TARGET_ABORT_MASK
115364. BIF_CFG_DEV0_EPF0_VF28_STATUS__RECEIVED_TARGET_ABORT__SHIFT
115365. BIF_CFG_DEV0_EPF0_VF28_STATUS__SIGNALED_SYSTEM_ERROR_MASK
115366. BIF_CFG_DEV0_EPF0_VF28_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
115367. BIF_CFG_DEV0_EPF0_VF28_STATUS__SIGNAL_TARGET_ABORT_MASK
115368. BIF_CFG_DEV0_EPF0_VF28_STATUS__SIGNAL_TARGET_ABORT__SHIFT
115369. BIF_CFG_DEV0_EPF0_VF28_SUB_CLASS__SUB_CLASS_MASK
115370. BIF_CFG_DEV0_EPF0_VF28_SUB_CLASS__SUB_CLASS__SHIFT
115371. BIF_CFG_DEV0_EPF0_VF28_VENDOR_ID__VENDOR_ID_MASK
115372. BIF_CFG_DEV0_EPF0_VF28_VENDOR_ID__VENDOR_ID__SHIFT
115373. BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
115374. BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
115375. BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
115376. BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
115377. BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1__BASE_ADDR_MASK
115378. BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1__BASE_ADDR__SHIFT
115379. BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2__BASE_ADDR_MASK
115380. BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2__BASE_ADDR__SHIFT
115381. BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3__BASE_ADDR_MASK
115382. BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3__BASE_ADDR__SHIFT
115383. BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4__BASE_ADDR_MASK
115384. BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4__BASE_ADDR__SHIFT
115385. BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5__BASE_ADDR_MASK
115386. BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5__BASE_ADDR__SHIFT
115387. BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6__BASE_ADDR_MASK
115388. BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6__BASE_ADDR__SHIFT
115389. BIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS__BASE_CLASS_MASK
115390. BIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS__BASE_CLASS__SHIFT
115391. BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_CAP_MASK
115392. BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_CAP__SHIFT
115393. BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_COMP_MASK
115394. BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_COMP__SHIFT
115395. BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_STRT_MASK
115396. BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_STRT__SHIFT
115397. BIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
115398. BIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
115399. BIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR__CAP_PTR_MASK
115400. BIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR__CAP_PTR__SHIFT
115401. BIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
115402. BIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
115403. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__AD_STEPPING_MASK
115404. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__AD_STEPPING__SHIFT
115405. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__BUS_MASTER_EN_MASK
115406. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__BUS_MASTER_EN__SHIFT
115407. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__FAST_B2B_EN_MASK
115408. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__FAST_B2B_EN__SHIFT
115409. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__INT_DIS_MASK
115410. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__INT_DIS__SHIFT
115411. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__IO_ACCESS_EN_MASK
115412. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__IO_ACCESS_EN__SHIFT
115413. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__MEM_ACCESS_EN_MASK
115414. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__MEM_ACCESS_EN__SHIFT
115415. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
115416. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
115417. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__PAL_SNOOP_EN_MASK
115418. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__PAL_SNOOP_EN__SHIFT
115419. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
115420. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
115421. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__SERR_EN_MASK
115422. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__SERR_EN__SHIFT
115423. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__SPECIAL_CYCLE_EN_MASK
115424. BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
115425. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
115426. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
115427. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
115428. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
115429. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
115430. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
115431. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
115432. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
115433. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
115434. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
115435. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
115436. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
115437. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
115438. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
115439. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
115440. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
115441. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
115442. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
115443. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
115444. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
115445. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
115446. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
115447. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
115448. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
115449. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
115450. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
115451. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
115452. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
115453. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
115454. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
115455. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
115456. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
115457. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
115458. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
115459. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
115460. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
115461. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
115462. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
115463. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
115464. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
115465. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
115466. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
115467. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
115468. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
115469. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__EXTENDED_TAG_MASK
115470. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
115471. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__FLR_CAPABLE_MASK
115472. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
115473. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
115474. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
115475. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
115476. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
115477. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
115478. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
115479. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__PHANTOM_FUNC_MASK
115480. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
115481. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
115482. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
115483. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
115484. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
115485. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
115486. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
115487. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
115488. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
115489. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
115490. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
115491. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
115492. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
115493. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
115494. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
115495. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
115496. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
115497. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
115498. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
115499. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
115500. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
115501. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__LTR_EN_MASK
115502. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__LTR_EN__SHIFT
115503. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__OBFF_EN_MASK
115504. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__OBFF_EN__SHIFT
115505. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
115506. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
115507. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
115508. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
115509. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__CORR_ERR_EN_MASK
115510. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
115511. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
115512. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
115513. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
115514. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
115515. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__INITIATE_FLR_MASK
115516. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
115517. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
115518. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
115519. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
115520. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
115521. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
115522. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
115523. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
115524. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
115525. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
115526. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
115527. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
115528. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
115529. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__USR_REPORT_EN_MASK
115530. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
115531. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID__DEVICE_ID_MASK
115532. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID__DEVICE_ID__SHIFT
115533. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2__RESERVED_MASK
115534. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2__RESERVED__SHIFT
115535. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__AUX_PWR_MASK
115536. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__AUX_PWR__SHIFT
115537. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__CORR_ERR_MASK
115538. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__CORR_ERR__SHIFT
115539. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
115540. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
115541. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__FATAL_ERR_MASK
115542. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__FATAL_ERR__SHIFT
115543. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
115544. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
115545. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
115546. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
115547. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__USR_DETECTED_MASK
115548. BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__USR_DETECTED__SHIFT
115549. BIF_CFG_DEV0_EPF0_VF29_0_HEADER__DEVICE_TYPE_MASK
115550. BIF_CFG_DEV0_EPF0_VF29_0_HEADER__DEVICE_TYPE__SHIFT
115551. BIF_CFG_DEV0_EPF0_VF29_0_HEADER__HEADER_TYPE_MASK
115552. BIF_CFG_DEV0_EPF0_VF29_0_HEADER__HEADER_TYPE__SHIFT
115553. BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
115554. BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
115555. BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
115556. BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
115557. BIF_CFG_DEV0_EPF0_VF29_0_LATENCY__LATENCY_TIMER_MASK
115558. BIF_CFG_DEV0_EPF0_VF29_0_LATENCY__LATENCY_TIMER__SHIFT
115559. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
115560. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
115561. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
115562. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
115563. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
115564. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
115565. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
115566. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
115567. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
115568. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
115569. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
115570. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
115571. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
115572. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
115573. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
115574. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
115575. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
115576. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
115577. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
115578. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
115579. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
115580. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
115581. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__L1_EXIT_LATENCY_MASK
115582. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
115583. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
115584. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
115585. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_SPEED_MASK
115586. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_SPEED__SHIFT
115587. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_WIDTH_MASK
115588. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_WIDTH__SHIFT
115589. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__PM_SUPPORT_MASK
115590. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__PM_SUPPORT__SHIFT
115591. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__PORT_NUMBER_MASK
115592. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__PORT_NUMBER__SHIFT
115593. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
115594. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
115595. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
115596. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
115597. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
115598. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
115599. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
115600. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
115601. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
115602. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
115603. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
115604. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
115605. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
115606. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
115607. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
115608. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
115609. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__XMIT_MARGIN_MASK
115610. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
115611. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
115612. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
115613. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
115614. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
115615. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
115616. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
115617. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__EXTENDED_SYNC_MASK
115618. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
115619. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
115620. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
115621. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
115622. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
115623. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
115624. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
115625. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_DIS_MASK
115626. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_DIS__SHIFT
115627. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__PM_CONTROL_MASK
115628. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__PM_CONTROL__SHIFT
115629. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
115630. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
115631. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__RETRAIN_LINK_MASK
115632. BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__RETRAIN_LINK__SHIFT
115633. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
115634. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
115635. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
115636. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
115637. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
115638. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
115639. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
115640. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
115641. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
115642. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
115643. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
115644. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
115645. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
115646. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
115647. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
115648. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
115649. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
115650. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
115651. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
115652. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
115653. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
115654. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
115655. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
115656. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
115657. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__DL_ACTIVE_MASK
115658. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__DL_ACTIVE__SHIFT
115659. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
115660. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
115661. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
115662. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
115663. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_TRAINING_MASK
115664. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_TRAINING__SHIFT
115665. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
115666. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
115667. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
115668. BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
115669. BIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY__MAX_LAT_MASK
115670. BIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY__MAX_LAT__SHIFT
115671. BIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT__MIN_GNT_MASK
115672. BIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT__MIN_GNT__SHIFT
115673. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST__CAP_ID_MASK
115674. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST__CAP_ID__SHIFT
115675. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST__NEXT_PTR_MASK
115676. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
115677. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_EN_MASK
115678. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
115679. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
115680. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
115681. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
115682. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
115683. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA__MSIX_PBA_BIR_MASK
115684. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
115685. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
115686. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
115687. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
115688. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
115689. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
115690. BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
115691. BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST__CAP_ID_MASK
115692. BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST__CAP_ID__SHIFT
115693. BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST__NEXT_PTR_MASK
115694. BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
115695. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64__MSI_MASK_64_MASK
115696. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64__MSI_MASK_64__SHIFT
115697. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK__MSI_MASK_MASK
115698. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK__MSI_MASK__SHIFT
115699. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
115700. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
115701. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
115702. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
115703. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_64BIT_MASK
115704. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
115705. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_EN_MASK
115706. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_EN__SHIFT
115707. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
115708. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
115709. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
115710. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
115711. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
115712. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
115713. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
115714. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
115715. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA__MSI_DATA_MASK
115716. BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA__MSI_DATA__SHIFT
115717. BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64__MSI_PENDING_64_MASK
115718. BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
115719. BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING__MSI_PENDING_MASK
115720. BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING__MSI_PENDING__SHIFT
115721. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
115722. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
115723. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
115724. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
115725. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
115726. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
115727. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
115728. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
115729. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
115730. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
115731. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
115732. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
115733. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
115734. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
115735. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
115736. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
115737. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
115738. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
115739. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
115740. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
115741. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
115742. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
115743. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
115744. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
115745. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
115746. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
115747. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
115748. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
115749. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
115750. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
115751. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
115752. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
115753. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
115754. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
115755. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
115756. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
115757. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
115758. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
115759. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
115760. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
115761. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
115762. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
115763. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
115764. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
115765. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
115766. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
115767. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
115768. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
115769. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
115770. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
115771. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL__STU_MASK
115772. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL__STU__SHIFT
115773. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
115774. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
115775. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
115776. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
115777. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
115778. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
115779. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST__CAP_ID_MASK
115780. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST__CAP_ID__SHIFT
115781. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST__NEXT_PTR_MASK
115782. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
115783. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__DEVICE_TYPE_MASK
115784. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__DEVICE_TYPE__SHIFT
115785. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
115786. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
115787. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
115788. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
115789. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__VERSION_MASK
115790. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__VERSION__SHIFT
115791. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
115792. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
115793. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
115794. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
115795. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
115796. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
115797. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
115798. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
115799. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
115800. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
115801. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
115802. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
115803. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
115804. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
115805. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
115806. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
115807. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
115808. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
115809. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
115810. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
115811. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
115812. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
115813. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
115814. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
115815. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
115816. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
115817. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
115818. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
115819. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
115820. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
115821. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
115822. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
115823. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0__TLP_HDR_MASK
115824. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
115825. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1__TLP_HDR_MASK
115826. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
115827. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2__TLP_HDR_MASK
115828. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
115829. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3__TLP_HDR_MASK
115830. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
115831. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
115832. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
115833. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
115834. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
115835. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
115836. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
115837. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
115838. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
115839. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
115840. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
115841. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
115842. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
115843. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
115844. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
115845. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
115846. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
115847. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
115848. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
115849. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
115850. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
115851. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
115852. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
115853. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
115854. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
115855. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
115856. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
115857. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
115858. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
115859. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
115860. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
115861. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
115862. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
115863. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
115864. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
115865. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
115866. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
115867. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
115868. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
115869. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
115870. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
115871. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
115872. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
115873. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
115874. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
115875. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
115876. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
115877. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
115878. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
115879. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
115880. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
115881. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
115882. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
115883. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
115884. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
115885. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
115886. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
115887. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
115888. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
115889. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
115890. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
115891. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
115892. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
115893. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
115894. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
115895. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
115896. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
115897. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
115898. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
115899. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
115900. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
115901. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
115902. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
115903. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
115904. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
115905. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
115906. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
115907. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
115908. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
115909. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
115910. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
115911. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
115912. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
115913. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
115914. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
115915. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
115916. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
115917. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
115918. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
115919. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
115920. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
115921. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
115922. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
115923. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
115924. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
115925. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
115926. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
115927. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
115928. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
115929. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
115930. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
115931. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
115932. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
115933. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
115934. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
115935. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
115936. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
115937. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
115938. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
115939. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
115940. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
115941. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
115942. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
115943. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
115944. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
115945. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
115946. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
115947. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
115948. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
115949. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
115950. BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
115951. BIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE__PROG_INTERFACE_MASK
115952. BIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
115953. BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID__MAJOR_REV_ID_MASK
115954. BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID__MAJOR_REV_ID__SHIFT
115955. BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID__MINOR_REV_ID_MASK
115956. BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID__MINOR_REV_ID__SHIFT
115957. BIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR__BASE_ADDR_MASK
115958. BIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
115959. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__CAP_LIST_MASK
115960. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__CAP_LIST__SHIFT
115961. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__DEVSEL_TIMING_MASK
115962. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__DEVSEL_TIMING__SHIFT
115963. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__FAST_BACK_CAPABLE_MASK
115964. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__FAST_BACK_CAPABLE__SHIFT
115965. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__IMMEDIATE_READINESS_MASK
115966. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__IMMEDIATE_READINESS__SHIFT
115967. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__INT_STATUS_MASK
115968. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__INT_STATUS__SHIFT
115969. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
115970. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
115971. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__PARITY_ERROR_DETECTED_MASK
115972. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
115973. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__PCI_66_CAP_MASK
115974. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__PCI_66_CAP__SHIFT
115975. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__RECEIVED_MASTER_ABORT_MASK
115976. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
115977. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__RECEIVED_TARGET_ABORT_MASK
115978. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
115979. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
115980. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
115981. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__SIGNAL_TARGET_ABORT_MASK
115982. BIF_CFG_DEV0_EPF0_VF29_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
115983. BIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS__SUB_CLASS_MASK
115984. BIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS__SUB_CLASS__SHIFT
115985. BIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID__VENDOR_ID_MASK
115986. BIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID__VENDOR_ID__SHIFT
115987. BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
115988. BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
115989. BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
115990. BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
115991. BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1__BASE_ADDR_MASK
115992. BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1__BASE_ADDR__SHIFT
115993. BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2__BASE_ADDR_MASK
115994. BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2__BASE_ADDR__SHIFT
115995. BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3__BASE_ADDR_MASK
115996. BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3__BASE_ADDR__SHIFT
115997. BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4__BASE_ADDR_MASK
115998. BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4__BASE_ADDR__SHIFT
115999. BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5__BASE_ADDR_MASK
116000. BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5__BASE_ADDR__SHIFT
116001. BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6__BASE_ADDR_MASK
116002. BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6__BASE_ADDR__SHIFT
116003. BIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS__BASE_CLASS_MASK
116004. BIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS__BASE_CLASS__SHIFT
116005. BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_CAP_MASK
116006. BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_CAP__SHIFT
116007. BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_COMP_MASK
116008. BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_COMP__SHIFT
116009. BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_STRT_MASK
116010. BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_STRT__SHIFT
116011. BIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
116012. BIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
116013. BIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR__CAP_PTR_MASK
116014. BIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR__CAP_PTR__SHIFT
116015. BIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
116016. BIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
116017. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__AD_STEPPING_MASK
116018. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__AD_STEPPING__SHIFT
116019. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__BUS_MASTER_EN_MASK
116020. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__BUS_MASTER_EN__SHIFT
116021. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__FAST_B2B_EN_MASK
116022. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__FAST_B2B_EN__SHIFT
116023. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__INT_DIS_MASK
116024. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__INT_DIS__SHIFT
116025. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__IO_ACCESS_EN_MASK
116026. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__IO_ACCESS_EN__SHIFT
116027. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__MEM_ACCESS_EN_MASK
116028. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__MEM_ACCESS_EN__SHIFT
116029. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
116030. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
116031. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__PAL_SNOOP_EN_MASK
116032. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__PAL_SNOOP_EN__SHIFT
116033. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
116034. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
116035. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__SERR_EN_MASK
116036. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__SERR_EN__SHIFT
116037. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__SPECIAL_CYCLE_EN_MASK
116038. BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
116039. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
116040. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
116041. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
116042. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
116043. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
116044. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
116045. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
116046. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
116047. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
116048. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
116049. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
116050. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
116051. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
116052. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
116053. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
116054. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
116055. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
116056. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
116057. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
116058. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
116059. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
116060. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
116061. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
116062. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
116063. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
116064. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
116065. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
116066. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
116067. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
116068. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
116069. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
116070. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
116071. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
116072. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
116073. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
116074. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
116075. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
116076. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
116077. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
116078. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
116079. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
116080. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
116081. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
116082. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
116083. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__EXTENDED_TAG_MASK
116084. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
116085. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__FLR_CAPABLE_MASK
116086. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
116087. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
116088. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
116089. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
116090. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
116091. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
116092. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
116093. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__PHANTOM_FUNC_MASK
116094. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
116095. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
116096. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
116097. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
116098. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
116099. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
116100. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
116101. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
116102. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
116103. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
116104. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
116105. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
116106. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
116107. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
116108. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
116109. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
116110. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
116111. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
116112. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
116113. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
116114. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
116115. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__LTR_EN_MASK
116116. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__LTR_EN__SHIFT
116117. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__OBFF_EN_MASK
116118. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__OBFF_EN__SHIFT
116119. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
116120. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
116121. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
116122. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
116123. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__CORR_ERR_EN_MASK
116124. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
116125. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
116126. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
116127. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
116128. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
116129. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__INITIATE_FLR_MASK
116130. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
116131. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
116132. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
116133. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
116134. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
116135. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
116136. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
116137. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
116138. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
116139. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
116140. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
116141. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
116142. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
116143. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__USR_REPORT_EN_MASK
116144. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
116145. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID__DEVICE_ID_MASK
116146. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID__DEVICE_ID__SHIFT
116147. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2__RESERVED_MASK
116148. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2__RESERVED__SHIFT
116149. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__AUX_PWR_MASK
116150. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__AUX_PWR__SHIFT
116151. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__CORR_ERR_MASK
116152. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__CORR_ERR__SHIFT
116153. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
116154. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
116155. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__FATAL_ERR_MASK
116156. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__FATAL_ERR__SHIFT
116157. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
116158. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
116159. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
116160. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
116161. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__USR_DETECTED_MASK
116162. BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__USR_DETECTED__SHIFT
116163. BIF_CFG_DEV0_EPF0_VF29_1_HEADER__DEVICE_TYPE_MASK
116164. BIF_CFG_DEV0_EPF0_VF29_1_HEADER__DEVICE_TYPE__SHIFT
116165. BIF_CFG_DEV0_EPF0_VF29_1_HEADER__HEADER_TYPE_MASK
116166. BIF_CFG_DEV0_EPF0_VF29_1_HEADER__HEADER_TYPE__SHIFT
116167. BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
116168. BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
116169. BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
116170. BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
116171. BIF_CFG_DEV0_EPF0_VF29_1_LATENCY__LATENCY_TIMER_MASK
116172. BIF_CFG_DEV0_EPF0_VF29_1_LATENCY__LATENCY_TIMER__SHIFT
116173. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
116174. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
116175. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
116176. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
116177. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
116178. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
116179. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
116180. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
116181. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
116182. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
116183. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
116184. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
116185. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
116186. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
116187. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
116188. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
116189. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
116190. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
116191. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
116192. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
116193. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
116194. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
116195. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__L1_EXIT_LATENCY_MASK
116196. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
116197. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
116198. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
116199. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_SPEED_MASK
116200. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_SPEED__SHIFT
116201. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_WIDTH_MASK
116202. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_WIDTH__SHIFT
116203. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__PM_SUPPORT_MASK
116204. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__PM_SUPPORT__SHIFT
116205. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__PORT_NUMBER_MASK
116206. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__PORT_NUMBER__SHIFT
116207. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
116208. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
116209. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
116210. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
116211. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
116212. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
116213. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
116214. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
116215. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
116216. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
116217. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
116218. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
116219. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
116220. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
116221. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
116222. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
116223. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__XMIT_MARGIN_MASK
116224. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
116225. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
116226. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
116227. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
116228. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
116229. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
116230. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
116231. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__EXTENDED_SYNC_MASK
116232. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
116233. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
116234. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
116235. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
116236. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
116237. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
116238. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
116239. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_DIS_MASK
116240. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_DIS__SHIFT
116241. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__PM_CONTROL_MASK
116242. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__PM_CONTROL__SHIFT
116243. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
116244. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
116245. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__RETRAIN_LINK_MASK
116246. BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__RETRAIN_LINK__SHIFT
116247. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
116248. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
116249. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
116250. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
116251. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
116252. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
116253. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
116254. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
116255. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
116256. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
116257. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
116258. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
116259. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
116260. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
116261. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
116262. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
116263. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
116264. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
116265. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
116266. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
116267. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
116268. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
116269. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
116270. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
116271. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__DL_ACTIVE_MASK
116272. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__DL_ACTIVE__SHIFT
116273. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
116274. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
116275. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
116276. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
116277. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_TRAINING_MASK
116278. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_TRAINING__SHIFT
116279. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
116280. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
116281. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
116282. BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
116283. BIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY__MAX_LAT_MASK
116284. BIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY__MAX_LAT__SHIFT
116285. BIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT__MIN_GNT_MASK
116286. BIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT__MIN_GNT__SHIFT
116287. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST__CAP_ID_MASK
116288. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST__CAP_ID__SHIFT
116289. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST__NEXT_PTR_MASK
116290. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
116291. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_EN_MASK
116292. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
116293. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
116294. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
116295. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
116296. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
116297. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA__MSIX_PBA_BIR_MASK
116298. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
116299. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
116300. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
116301. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
116302. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
116303. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
116304. BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
116305. BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST__CAP_ID_MASK
116306. BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST__CAP_ID__SHIFT
116307. BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST__NEXT_PTR_MASK
116308. BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
116309. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64__MSI_MASK_64_MASK
116310. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64__MSI_MASK_64__SHIFT
116311. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK__MSI_MASK_MASK
116312. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK__MSI_MASK__SHIFT
116313. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
116314. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
116315. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
116316. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
116317. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_64BIT_MASK
116318. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
116319. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_EN_MASK
116320. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_EN__SHIFT
116321. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
116322. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
116323. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
116324. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
116325. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
116326. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
116327. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
116328. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
116329. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA__MSI_DATA_MASK
116330. BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA__MSI_DATA__SHIFT
116331. BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64__MSI_PENDING_64_MASK
116332. BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
116333. BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING__MSI_PENDING_MASK
116334. BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING__MSI_PENDING__SHIFT
116335. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
116336. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
116337. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
116338. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
116339. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
116340. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
116341. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
116342. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
116343. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
116344. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
116345. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
116346. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
116347. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
116348. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
116349. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
116350. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
116351. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
116352. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
116353. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
116354. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
116355. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
116356. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
116357. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
116358. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
116359. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
116360. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
116361. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
116362. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
116363. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
116364. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
116365. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
116366. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
116367. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
116368. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
116369. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
116370. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
116371. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
116372. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
116373. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
116374. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
116375. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
116376. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
116377. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
116378. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
116379. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
116380. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
116381. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
116382. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
116383. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
116384. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
116385. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL__STU_MASK
116386. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL__STU__SHIFT
116387. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
116388. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
116389. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
116390. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
116391. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
116392. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
116393. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST__CAP_ID_MASK
116394. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST__CAP_ID__SHIFT
116395. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST__NEXT_PTR_MASK
116396. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
116397. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__DEVICE_TYPE_MASK
116398. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__DEVICE_TYPE__SHIFT
116399. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
116400. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
116401. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
116402. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
116403. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__VERSION_MASK
116404. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__VERSION__SHIFT
116405. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
116406. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
116407. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
116408. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
116409. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
116410. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
116411. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
116412. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
116413. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
116414. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
116415. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
116416. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
116417. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
116418. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
116419. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
116420. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
116421. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
116422. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
116423. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
116424. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
116425. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
116426. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
116427. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
116428. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
116429. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
116430. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
116431. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
116432. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
116433. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
116434. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
116435. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
116436. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
116437. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0__TLP_HDR_MASK
116438. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
116439. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1__TLP_HDR_MASK
116440. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
116441. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2__TLP_HDR_MASK
116442. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
116443. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3__TLP_HDR_MASK
116444. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
116445. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
116446. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
116447. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
116448. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
116449. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
116450. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
116451. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
116452. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
116453. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
116454. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
116455. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
116456. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
116457. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
116458. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
116459. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
116460. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
116461. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
116462. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
116463. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
116464. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
116465. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
116466. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
116467. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
116468. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
116469. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
116470. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
116471. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
116472. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
116473. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
116474. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
116475. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
116476. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
116477. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
116478. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
116479. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
116480. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
116481. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
116482. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
116483. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
116484. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
116485. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
116486. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
116487. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
116488. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
116489. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
116490. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
116491. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
116492. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
116493. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
116494. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
116495. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
116496. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
116497. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
116498. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
116499. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
116500. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
116501. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
116502. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
116503. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
116504. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
116505. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
116506. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
116507. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
116508. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
116509. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
116510. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
116511. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
116512. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
116513. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
116514. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
116515. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
116516. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
116517. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
116518. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
116519. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
116520. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
116521. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
116522. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
116523. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
116524. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
116525. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
116526. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
116527. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
116528. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
116529. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
116530. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
116531. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
116532. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
116533. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
116534. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
116535. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
116536. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
116537. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
116538. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
116539. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
116540. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
116541. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
116542. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
116543. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
116544. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
116545. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
116546. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
116547. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
116548. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
116549. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
116550. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
116551. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
116552. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
116553. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
116554. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
116555. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
116556. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
116557. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
116558. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
116559. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
116560. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
116561. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
116562. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
116563. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
116564. BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
116565. BIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE__PROG_INTERFACE_MASK
116566. BIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
116567. BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID__MAJOR_REV_ID_MASK
116568. BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID__MAJOR_REV_ID__SHIFT
116569. BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID__MINOR_REV_ID_MASK
116570. BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID__MINOR_REV_ID__SHIFT
116571. BIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR__BASE_ADDR_MASK
116572. BIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
116573. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__CAP_LIST_MASK
116574. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__CAP_LIST__SHIFT
116575. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__DEVSEL_TIMING_MASK
116576. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__DEVSEL_TIMING__SHIFT
116577. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__FAST_BACK_CAPABLE_MASK
116578. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__FAST_BACK_CAPABLE__SHIFT
116579. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__IMMEDIATE_READINESS_MASK
116580. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__IMMEDIATE_READINESS__SHIFT
116581. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__INT_STATUS_MASK
116582. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__INT_STATUS__SHIFT
116583. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
116584. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
116585. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__PARITY_ERROR_DETECTED_MASK
116586. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
116587. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__PCI_66_CAP_MASK
116588. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__PCI_66_CAP__SHIFT
116589. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__RECEIVED_MASTER_ABORT_MASK
116590. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
116591. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__RECEIVED_TARGET_ABORT_MASK
116592. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
116593. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
116594. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
116595. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__SIGNAL_TARGET_ABORT_MASK
116596. BIF_CFG_DEV0_EPF0_VF29_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
116597. BIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS__SUB_CLASS_MASK
116598. BIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS__SUB_CLASS__SHIFT
116599. BIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID__VENDOR_ID_MASK
116600. BIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID__VENDOR_ID__SHIFT
116601. BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID__SUBSYSTEM_ID_MASK
116602. BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
116603. BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
116604. BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
116605. BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_1__BASE_ADDR_MASK
116606. BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_1__BASE_ADDR__SHIFT
116607. BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_2__BASE_ADDR_MASK
116608. BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_2__BASE_ADDR__SHIFT
116609. BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_3__BASE_ADDR_MASK
116610. BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_3__BASE_ADDR__SHIFT
116611. BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_4__BASE_ADDR_MASK
116612. BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_4__BASE_ADDR__SHIFT
116613. BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_5__BASE_ADDR_MASK
116614. BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_5__BASE_ADDR__SHIFT
116615. BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_6__BASE_ADDR_MASK
116616. BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_6__BASE_ADDR__SHIFT
116617. BIF_CFG_DEV0_EPF0_VF29_BASE_CLASS__BASE_CLASS_MASK
116618. BIF_CFG_DEV0_EPF0_VF29_BASE_CLASS__BASE_CLASS__SHIFT
116619. BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_CAP_MASK
116620. BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_CAP__SHIFT
116621. BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_COMP_MASK
116622. BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_COMP__SHIFT
116623. BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_STRT_MASK
116624. BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_STRT__SHIFT
116625. BIF_CFG_DEV0_EPF0_VF29_CACHE_LINE__CACHE_LINE_SIZE_MASK
116626. BIF_CFG_DEV0_EPF0_VF29_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
116627. BIF_CFG_DEV0_EPF0_VF29_CAP_PTR__CAP_PTR_MASK
116628. BIF_CFG_DEV0_EPF0_VF29_CAP_PTR__CAP_PTR__SHIFT
116629. BIF_CFG_DEV0_EPF0_VF29_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
116630. BIF_CFG_DEV0_EPF0_VF29_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
116631. BIF_CFG_DEV0_EPF0_VF29_COMMAND__AD_STEPPING_MASK
116632. BIF_CFG_DEV0_EPF0_VF29_COMMAND__AD_STEPPING__SHIFT
116633. BIF_CFG_DEV0_EPF0_VF29_COMMAND__BUS_MASTER_EN_MASK
116634. BIF_CFG_DEV0_EPF0_VF29_COMMAND__BUS_MASTER_EN__SHIFT
116635. BIF_CFG_DEV0_EPF0_VF29_COMMAND__FAST_B2B_EN_MASK
116636. BIF_CFG_DEV0_EPF0_VF29_COMMAND__FAST_B2B_EN__SHIFT
116637. BIF_CFG_DEV0_EPF0_VF29_COMMAND__INT_DIS_MASK
116638. BIF_CFG_DEV0_EPF0_VF29_COMMAND__INT_DIS__SHIFT
116639. BIF_CFG_DEV0_EPF0_VF29_COMMAND__IO_ACCESS_EN_MASK
116640. BIF_CFG_DEV0_EPF0_VF29_COMMAND__IO_ACCESS_EN__SHIFT
116641. BIF_CFG_DEV0_EPF0_VF29_COMMAND__MEM_ACCESS_EN_MASK
116642. BIF_CFG_DEV0_EPF0_VF29_COMMAND__MEM_ACCESS_EN__SHIFT
116643. BIF_CFG_DEV0_EPF0_VF29_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
116644. BIF_CFG_DEV0_EPF0_VF29_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
116645. BIF_CFG_DEV0_EPF0_VF29_COMMAND__PAL_SNOOP_EN_MASK
116646. BIF_CFG_DEV0_EPF0_VF29_COMMAND__PAL_SNOOP_EN__SHIFT
116647. BIF_CFG_DEV0_EPF0_VF29_COMMAND__PARITY_ERROR_RESPONSE_MASK
116648. BIF_CFG_DEV0_EPF0_VF29_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
116649. BIF_CFG_DEV0_EPF0_VF29_COMMAND__SERR_EN_MASK
116650. BIF_CFG_DEV0_EPF0_VF29_COMMAND__SERR_EN__SHIFT
116651. BIF_CFG_DEV0_EPF0_VF29_COMMAND__SPECIAL_CYCLE_EN_MASK
116652. BIF_CFG_DEV0_EPF0_VF29_COMMAND__SPECIAL_CYCLE_EN__SHIFT
116653. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
116654. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
116655. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
116656. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
116657. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
116658. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
116659. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
116660. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
116661. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
116662. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
116663. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
116664. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
116665. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
116666. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
116667. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
116668. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
116669. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
116670. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
116671. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
116672. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
116673. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
116674. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
116675. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__FRS_SUPPORTED_MASK
116676. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
116677. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
116678. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
116679. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__LTR_SUPPORTED_MASK
116680. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
116681. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
116682. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
116683. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
116684. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
116685. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__OBFF_SUPPORTED_MASK
116686. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
116687. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
116688. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
116689. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
116690. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
116691. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
116692. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
116693. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
116694. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
116695. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
116696. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
116697. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__EXTENDED_TAG_MASK
116698. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__EXTENDED_TAG__SHIFT
116699. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__FLR_CAPABLE_MASK
116700. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__FLR_CAPABLE__SHIFT
116701. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
116702. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
116703. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
116704. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
116705. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
116706. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
116707. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__PHANTOM_FUNC_MASK
116708. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__PHANTOM_FUNC__SHIFT
116709. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
116710. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
116711. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
116712. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
116713. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
116714. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
116715. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
116716. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
116717. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
116718. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
116719. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
116720. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
116721. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
116722. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
116723. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
116724. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
116725. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
116726. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
116727. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
116728. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
116729. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__LTR_EN_MASK
116730. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__LTR_EN__SHIFT
116731. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__OBFF_EN_MASK
116732. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__OBFF_EN__SHIFT
116733. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
116734. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
116735. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
116736. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
116737. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__CORR_ERR_EN_MASK
116738. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__CORR_ERR_EN__SHIFT
116739. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
116740. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
116741. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__FATAL_ERR_EN_MASK
116742. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
116743. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__INITIATE_FLR_MASK
116744. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__INITIATE_FLR__SHIFT
116745. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
116746. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
116747. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
116748. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
116749. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
116750. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
116751. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__NO_SNOOP_EN_MASK
116752. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
116753. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
116754. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
116755. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__RELAXED_ORD_EN_MASK
116756. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
116757. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__USR_REPORT_EN_MASK
116758. BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__USR_REPORT_EN__SHIFT
116759. BIF_CFG_DEV0_EPF0_VF29_DEVICE_ID__DEVICE_ID_MASK
116760. BIF_CFG_DEV0_EPF0_VF29_DEVICE_ID__DEVICE_ID__SHIFT
116761. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS2__RESERVED_MASK
116762. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS2__RESERVED__SHIFT
116763. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__AUX_PWR_MASK
116764. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__AUX_PWR__SHIFT
116765. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__CORR_ERR_MASK
116766. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__CORR_ERR__SHIFT
116767. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
116768. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
116769. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__FATAL_ERR_MASK
116770. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__FATAL_ERR__SHIFT
116771. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__NON_FATAL_ERR_MASK
116772. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
116773. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
116774. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
116775. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__USR_DETECTED_MASK
116776. BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__USR_DETECTED__SHIFT
116777. BIF_CFG_DEV0_EPF0_VF29_HEADER__DEVICE_TYPE_MASK
116778. BIF_CFG_DEV0_EPF0_VF29_HEADER__DEVICE_TYPE__SHIFT
116779. BIF_CFG_DEV0_EPF0_VF29_HEADER__HEADER_TYPE_MASK
116780. BIF_CFG_DEV0_EPF0_VF29_HEADER__HEADER_TYPE__SHIFT
116781. BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_LINE__INTERRUPT_LINE_MASK
116782. BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
116783. BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_PIN__INTERRUPT_PIN_MASK
116784. BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
116785. BIF_CFG_DEV0_EPF0_VF29_LATENCY__LATENCY_TIMER_MASK
116786. BIF_CFG_DEV0_EPF0_VF29_LATENCY__LATENCY_TIMER__SHIFT
116787. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
116788. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
116789. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
116790. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
116791. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
116792. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
116793. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
116794. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
116795. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
116796. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
116797. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
116798. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
116799. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
116800. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
116801. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
116802. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
116803. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
116804. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
116805. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
116806. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
116807. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__L0S_EXIT_LATENCY_MASK
116808. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
116809. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__L1_EXIT_LATENCY_MASK
116810. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__L1_EXIT_LATENCY__SHIFT
116811. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
116812. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
116813. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_SPEED_MASK
116814. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_SPEED__SHIFT
116815. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_WIDTH_MASK
116816. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_WIDTH__SHIFT
116817. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__PM_SUPPORT_MASK
116818. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__PM_SUPPORT__SHIFT
116819. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__PORT_NUMBER_MASK
116820. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__PORT_NUMBER__SHIFT
116821. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
116822. BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
116823. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
116824. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
116825. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__COMPLIANCE_SOS_MASK
116826. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
116827. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__ENTER_COMPLIANCE_MASK
116828. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
116829. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
116830. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
116831. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
116832. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
116833. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
116834. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
116835. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__TARGET_LINK_SPEED_MASK
116836. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
116837. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__XMIT_MARGIN_MASK
116838. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__XMIT_MARGIN__SHIFT
116839. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
116840. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
116841. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__COMMON_CLOCK_CFG_MASK
116842. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
116843. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
116844. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
116845. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__EXTENDED_SYNC_MASK
116846. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__EXTENDED_SYNC__SHIFT
116847. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
116848. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
116849. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
116850. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
116851. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
116852. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
116853. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_DIS_MASK
116854. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_DIS__SHIFT
116855. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__PM_CONTROL_MASK
116856. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__PM_CONTROL__SHIFT
116857. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__READ_CPL_BOUNDARY_MASK
116858. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
116859. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__RETRAIN_LINK_MASK
116860. BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__RETRAIN_LINK__SHIFT
116861. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
116862. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
116863. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
116864. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
116865. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
116866. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
116867. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
116868. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
116869. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
116870. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
116871. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
116872. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
116873. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
116874. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
116875. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
116876. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
116877. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
116878. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
116879. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
116880. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
116881. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
116882. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
116883. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__CURRENT_LINK_SPEED_MASK
116884. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
116885. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__DL_ACTIVE_MASK
116886. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__DL_ACTIVE__SHIFT
116887. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
116888. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
116889. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
116890. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
116891. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_TRAINING_MASK
116892. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_TRAINING__SHIFT
116893. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
116894. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
116895. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__SLOT_CLOCK_CFG_MASK
116896. BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
116897. BIF_CFG_DEV0_EPF0_VF29_MAX_LATENCY__MAX_LAT_MASK
116898. BIF_CFG_DEV0_EPF0_VF29_MAX_LATENCY__MAX_LAT__SHIFT
116899. BIF_CFG_DEV0_EPF0_VF29_MIN_GRANT__MIN_GNT_MASK
116900. BIF_CFG_DEV0_EPF0_VF29_MIN_GRANT__MIN_GNT__SHIFT
116901. BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST__CAP_ID_MASK
116902. BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST__CAP_ID__SHIFT
116903. BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST__NEXT_PTR_MASK
116904. BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST__NEXT_PTR__SHIFT
116905. BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_EN_MASK
116906. BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_EN__SHIFT
116907. BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
116908. BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
116909. BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
116910. BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
116911. BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA__MSIX_PBA_BIR_MASK
116912. BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA__MSIX_PBA_BIR__SHIFT
116913. BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA__MSIX_PBA_OFFSET_MASK
116914. BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
116915. BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE__MSIX_TABLE_BIR_MASK
116916. BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
116917. BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
116918. BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
116919. BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST__CAP_ID_MASK
116920. BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST__CAP_ID__SHIFT
116921. BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST__NEXT_PTR_MASK
116922. BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST__NEXT_PTR__SHIFT
116923. BIF_CFG_DEV0_EPF0_VF29_MSI_MASK_64__MSI_MASK_64_MASK
116924. BIF_CFG_DEV0_EPF0_VF29_MSI_MASK_64__MSI_MASK_64__SHIFT
116925. BIF_CFG_DEV0_EPF0_VF29_MSI_MASK__MSI_MASK_MASK
116926. BIF_CFG_DEV0_EPF0_VF29_MSI_MASK__MSI_MASK__SHIFT
116927. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
116928. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
116929. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
116930. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
116931. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_64BIT_MASK
116932. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_64BIT__SHIFT
116933. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_EN_MASK
116934. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_EN__SHIFT
116935. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
116936. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
116937. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
116938. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
116939. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
116940. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
116941. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA_64__MSI_DATA_64_MASK
116942. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
116943. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA__MSI_DATA_MASK
116944. BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA__MSI_DATA__SHIFT
116945. BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING_64__MSI_PENDING_64_MASK
116946. BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING_64__MSI_PENDING_64__SHIFT
116947. BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING__MSI_PENDING_MASK
116948. BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING__MSI_PENDING__SHIFT
116949. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
116950. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
116951. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
116952. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
116953. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
116954. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
116955. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
116956. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
116957. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
116958. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
116959. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
116960. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
116961. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
116962. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
116963. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
116964. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
116965. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
116966. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
116967. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
116968. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
116969. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
116970. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
116971. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
116972. BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
116973. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
116974. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
116975. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
116976. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
116977. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
116978. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
116979. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
116980. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
116981. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
116982. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
116983. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
116984. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
116985. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
116986. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
116987. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
116988. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
116989. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
116990. BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
116991. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
116992. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
116993. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
116994. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
116995. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
116996. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
116997. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL__ATC_ENABLE_MASK
116998. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
116999. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL__STU_MASK
117000. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL__STU__SHIFT
117001. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
117002. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
117003. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
117004. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
117005. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
117006. BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
117007. BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST__CAP_ID_MASK
117008. BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST__CAP_ID__SHIFT
117009. BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST__NEXT_PTR_MASK
117010. BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST__NEXT_PTR__SHIFT
117011. BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__DEVICE_TYPE_MASK
117012. BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__DEVICE_TYPE__SHIFT
117013. BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__INT_MESSAGE_NUM_MASK
117014. BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
117015. BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__SLOT_IMPLEMENTED_MASK
117016. BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
117017. BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__VERSION_MASK
117018. BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__VERSION__SHIFT
117019. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
117020. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
117021. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
117022. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
117023. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
117024. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
117025. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
117026. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
117027. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
117028. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
117029. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
117030. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
117031. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
117032. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
117033. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
117034. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
117035. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
117036. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
117037. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
117038. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
117039. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
117040. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
117041. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
117042. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
117043. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
117044. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
117045. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
117046. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
117047. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
117048. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
117049. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
117050. BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
117051. BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG0__TLP_HDR_MASK
117052. BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG0__TLP_HDR__SHIFT
117053. BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG1__TLP_HDR_MASK
117054. BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG1__TLP_HDR__SHIFT
117055. BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG2__TLP_HDR_MASK
117056. BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG2__TLP_HDR__SHIFT
117057. BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG3__TLP_HDR_MASK
117058. BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG3__TLP_HDR__SHIFT
117059. BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
117060. BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
117061. BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
117062. BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
117063. BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
117064. BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
117065. BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
117066. BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
117067. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
117068. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
117069. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
117070. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
117071. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
117072. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
117073. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
117074. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
117075. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
117076. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
117077. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
117078. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
117079. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
117080. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
117081. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
117082. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
117083. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
117084. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
117085. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
117086. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
117087. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
117088. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
117089. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
117090. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
117091. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
117092. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
117093. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
117094. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
117095. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
117096. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
117097. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
117098. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
117099. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
117100. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
117101. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
117102. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
117103. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
117104. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
117105. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
117106. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
117107. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
117108. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
117109. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
117110. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
117111. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
117112. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
117113. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
117114. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
117115. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
117116. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
117117. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
117118. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
117119. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
117120. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
117121. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
117122. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
117123. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
117124. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
117125. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
117126. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
117127. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
117128. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
117129. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
117130. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
117131. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
117132. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
117133. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
117134. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
117135. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
117136. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
117137. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
117138. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
117139. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
117140. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
117141. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
117142. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
117143. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
117144. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
117145. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
117146. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
117147. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
117148. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
117149. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
117150. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
117151. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
117152. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
117153. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
117154. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
117155. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
117156. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
117157. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
117158. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
117159. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
117160. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
117161. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
117162. BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
117163. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
117164. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
117165. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
117166. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
117167. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
117168. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
117169. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
117170. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
117171. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
117172. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
117173. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
117174. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
117175. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
117176. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
117177. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
117178. BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
117179. BIF_CFG_DEV0_EPF0_VF29_PROG_INTERFACE__PROG_INTERFACE_MASK
117180. BIF_CFG_DEV0_EPF0_VF29_PROG_INTERFACE__PROG_INTERFACE__SHIFT
117181. BIF_CFG_DEV0_EPF0_VF29_REVISION_ID__MAJOR_REV_ID_MASK
117182. BIF_CFG_DEV0_EPF0_VF29_REVISION_ID__MAJOR_REV_ID__SHIFT
117183. BIF_CFG_DEV0_EPF0_VF29_REVISION_ID__MINOR_REV_ID_MASK
117184. BIF_CFG_DEV0_EPF0_VF29_REVISION_ID__MINOR_REV_ID__SHIFT
117185. BIF_CFG_DEV0_EPF0_VF29_ROM_BASE_ADDR__BASE_ADDR_MASK
117186. BIF_CFG_DEV0_EPF0_VF29_ROM_BASE_ADDR__BASE_ADDR__SHIFT
117187. BIF_CFG_DEV0_EPF0_VF29_STATUS__CAP_LIST_MASK
117188. BIF_CFG_DEV0_EPF0_VF29_STATUS__CAP_LIST__SHIFT
117189. BIF_CFG_DEV0_EPF0_VF29_STATUS__DEVSEL_TIMING_MASK
117190. BIF_CFG_DEV0_EPF0_VF29_STATUS__DEVSEL_TIMING__SHIFT
117191. BIF_CFG_DEV0_EPF0_VF29_STATUS__FAST_BACK_CAPABLE_MASK
117192. BIF_CFG_DEV0_EPF0_VF29_STATUS__FAST_BACK_CAPABLE__SHIFT
117193. BIF_CFG_DEV0_EPF0_VF29_STATUS__IMMEDIATE_READINESS_MASK
117194. BIF_CFG_DEV0_EPF0_VF29_STATUS__IMMEDIATE_READINESS__SHIFT
117195. BIF_CFG_DEV0_EPF0_VF29_STATUS__INT_STATUS_MASK
117196. BIF_CFG_DEV0_EPF0_VF29_STATUS__INT_STATUS__SHIFT
117197. BIF_CFG_DEV0_EPF0_VF29_STATUS__MASTER_DATA_PARITY_ERROR_MASK
117198. BIF_CFG_DEV0_EPF0_VF29_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
117199. BIF_CFG_DEV0_EPF0_VF29_STATUS__PARITY_ERROR_DETECTED_MASK
117200. BIF_CFG_DEV0_EPF0_VF29_STATUS__PARITY_ERROR_DETECTED__SHIFT
117201. BIF_CFG_DEV0_EPF0_VF29_STATUS__PCI_66_CAP_MASK
117202. BIF_CFG_DEV0_EPF0_VF29_STATUS__PCI_66_CAP__SHIFT
117203. BIF_CFG_DEV0_EPF0_VF29_STATUS__RECEIVED_MASTER_ABORT_MASK
117204. BIF_CFG_DEV0_EPF0_VF29_STATUS__RECEIVED_MASTER_ABORT__SHIFT
117205. BIF_CFG_DEV0_EPF0_VF29_STATUS__RECEIVED_TARGET_ABORT_MASK
117206. BIF_CFG_DEV0_EPF0_VF29_STATUS__RECEIVED_TARGET_ABORT__SHIFT
117207. BIF_CFG_DEV0_EPF0_VF29_STATUS__SIGNALED_SYSTEM_ERROR_MASK
117208. BIF_CFG_DEV0_EPF0_VF29_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
117209. BIF_CFG_DEV0_EPF0_VF29_STATUS__SIGNAL_TARGET_ABORT_MASK
117210. BIF_CFG_DEV0_EPF0_VF29_STATUS__SIGNAL_TARGET_ABORT__SHIFT
117211. BIF_CFG_DEV0_EPF0_VF29_SUB_CLASS__SUB_CLASS_MASK
117212. BIF_CFG_DEV0_EPF0_VF29_SUB_CLASS__SUB_CLASS__SHIFT
117213. BIF_CFG_DEV0_EPF0_VF29_VENDOR_ID__VENDOR_ID_MASK
117214. BIF_CFG_DEV0_EPF0_VF29_VENDOR_ID__VENDOR_ID__SHIFT
117215. BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
117216. BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
117217. BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
117218. BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
117219. BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR_MASK
117220. BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT
117221. BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR_MASK
117222. BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT
117223. BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR_MASK
117224. BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT
117225. BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR_MASK
117226. BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT
117227. BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR_MASK
117228. BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT
117229. BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR_MASK
117230. BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT
117231. BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS_MASK
117232. BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS__SHIFT
117233. BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP_MASK
117234. BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP__SHIFT
117235. BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP_MASK
117236. BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP__SHIFT
117237. BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT_MASK
117238. BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT__SHIFT
117239. BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
117240. BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
117241. BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR_MASK
117242. BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR__SHIFT
117243. BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
117244. BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
117245. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING_MASK
117246. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING__SHIFT
117247. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN_MASK
117248. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN__SHIFT
117249. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN_MASK
117250. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN__SHIFT
117251. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS_MASK
117252. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS__SHIFT
117253. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN_MASK
117254. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN__SHIFT
117255. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN_MASK
117256. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN__SHIFT
117257. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
117258. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
117259. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN_MASK
117260. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN__SHIFT
117261. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
117262. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
117263. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN_MASK
117264. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN__SHIFT
117265. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK
117266. BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
117267. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
117268. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
117269. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
117270. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
117271. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
117272. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
117273. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
117274. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
117275. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
117276. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
117277. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
117278. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
117279. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
117280. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
117281. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
117282. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
117283. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
117284. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
117285. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
117286. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
117287. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
117288. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
117289. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
117290. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
117291. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
117292. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
117293. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
117294. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
117295. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
117296. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
117297. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
117298. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
117299. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
117300. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
117301. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
117302. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
117303. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
117304. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
117305. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
117306. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
117307. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
117308. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
117309. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
117310. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
117311. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG_MASK
117312. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
117313. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE_MASK
117314. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
117315. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
117316. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
117317. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
117318. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
117319. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
117320. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
117321. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK
117322. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
117323. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
117324. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
117325. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
117326. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
117327. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
117328. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
117329. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
117330. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
117331. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
117332. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
117333. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
117334. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
117335. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
117336. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
117337. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
117338. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
117339. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
117340. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
117341. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
117342. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
117343. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN_MASK
117344. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN__SHIFT
117345. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN_MASK
117346. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT
117347. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
117348. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
117349. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
117350. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
117351. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK
117352. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
117353. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
117354. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
117355. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
117356. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
117357. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR_MASK
117358. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
117359. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
117360. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
117361. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
117362. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
117363. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
117364. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
117365. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
117366. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
117367. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
117368. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
117369. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
117370. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
117371. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK
117372. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
117373. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID_MASK
117374. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID__SHIFT
117375. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED_MASK
117376. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED__SHIFT
117377. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR_MASK
117378. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR__SHIFT
117379. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR_MASK
117380. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR__SHIFT
117381. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
117382. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
117383. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR_MASK
117384. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT
117385. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
117386. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
117387. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
117388. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
117389. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED_MASK
117390. BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT
117391. BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE_MASK
117392. BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE__SHIFT
117393. BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE_MASK
117394. BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE__SHIFT
117395. BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
117396. BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
117397. BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
117398. BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
117399. BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER_MASK
117400. BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER__SHIFT
117401. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
117402. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
117403. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
117404. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
117405. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
117406. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
117407. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
117408. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
117409. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RESERVED_MASK
117410. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RESERVED__SHIFT
117411. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
117412. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
117413. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
117414. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
117415. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
117416. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
117417. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
117418. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
117419. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
117420. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
117421. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
117422. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
117423. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
117424. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
117425. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK
117426. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
117427. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
117428. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
117429. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED_MASK
117430. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED__SHIFT
117431. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH_MASK
117432. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH__SHIFT
117433. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT_MASK
117434. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT__SHIFT
117435. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER_MASK
117436. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER__SHIFT
117437. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
117438. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
117439. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
117440. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
117441. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
117442. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
117443. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
117444. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
117445. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
117446. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
117447. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
117448. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
117449. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
117450. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
117451. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
117452. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
117453. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN_MASK
117454. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
117455. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
117456. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
117457. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
117458. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
117459. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
117460. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
117461. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC_MASK
117462. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
117463. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
117464. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
117465. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
117466. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
117467. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
117468. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
117469. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS_MASK
117470. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS__SHIFT
117471. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL_MASK
117472. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL__SHIFT
117473. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
117474. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
117475. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK_MASK
117476. BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT
117477. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
117478. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
117479. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
117480. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
117481. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
117482. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
117483. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
117484. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
117485. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
117486. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
117487. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
117488. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
117489. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
117490. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
117491. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
117492. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
117493. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
117494. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
117495. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
117496. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
117497. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
117498. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
117499. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
117500. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
117501. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
117502. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
117503. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
117504. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
117505. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
117506. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
117507. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
117508. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
117509. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
117510. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
117511. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE_MASK
117512. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE__SHIFT
117513. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
117514. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
117515. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
117516. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
117517. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING_MASK
117518. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING__SHIFT
117519. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
117520. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
117521. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
117522. BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
117523. BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY__MAX_LAT_MASK
117524. BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY__MAX_LAT__SHIFT
117525. BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT__MIN_GNT_MASK
117526. BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT__MIN_GNT__SHIFT
117527. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID_MASK
117528. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT
117529. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK
117530. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
117531. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK
117532. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
117533. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
117534. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
117535. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
117536. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
117537. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK
117538. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
117539. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
117540. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
117541. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
117542. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
117543. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
117544. BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
117545. BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID_MASK
117546. BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID__SHIFT
117547. BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR_MASK
117548. BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
117549. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64_MASK
117550. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT
117551. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK_MASK
117552. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK__SHIFT
117553. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
117554. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
117555. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
117556. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
117557. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK
117558. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
117559. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN_MASK
117560. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT
117561. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
117562. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
117563. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
117564. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
117565. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
117566. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
117567. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
117568. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
117569. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA_MASK
117570. BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT
117571. BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK
117572. BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
117573. BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING_MASK
117574. BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING__SHIFT
117575. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
117576. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
117577. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
117578. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
117579. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
117580. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
117581. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
117582. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
117583. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
117584. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
117585. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
117586. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
117587. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
117588. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
117589. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
117590. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
117591. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
117592. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
117593. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
117594. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
117595. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
117596. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
117597. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
117598. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
117599. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
117600. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
117601. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
117602. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
117603. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
117604. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
117605. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
117606. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
117607. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
117608. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
117609. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
117610. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
117611. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
117612. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
117613. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
117614. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
117615. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
117616. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
117617. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
117618. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
117619. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
117620. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
117621. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
117622. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
117623. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
117624. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
117625. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__STU_MASK
117626. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__STU__SHIFT
117627. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
117628. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
117629. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
117630. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
117631. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
117632. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
117633. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID_MASK
117634. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT
117635. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK
117636. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
117637. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE_MASK
117638. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT
117639. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
117640. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
117641. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
117642. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
117643. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION_MASK
117644. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION__SHIFT
117645. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
117646. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
117647. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
117648. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
117649. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
117650. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
117651. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
117652. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
117653. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
117654. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
117655. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
117656. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
117657. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
117658. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
117659. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
117660. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
117661. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
117662. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
117663. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
117664. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
117665. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
117666. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
117667. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
117668. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
117669. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
117670. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
117671. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
117672. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
117673. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
117674. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
117675. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
117676. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
117677. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK
117678. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
117679. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK
117680. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
117681. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK
117682. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
117683. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK
117684. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
117685. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
117686. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
117687. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
117688. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
117689. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
117690. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
117691. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
117692. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
117693. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
117694. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
117695. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
117696. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
117697. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
117698. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
117699. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
117700. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
117701. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
117702. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
117703. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
117704. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
117705. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
117706. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
117707. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
117708. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
117709. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
117710. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
117711. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
117712. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
117713. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
117714. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
117715. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
117716. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
117717. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
117718. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
117719. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
117720. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
117721. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
117722. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
117723. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
117724. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
117725. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
117726. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
117727. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
117728. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
117729. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
117730. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
117731. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
117732. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
117733. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
117734. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
117735. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
117736. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
117737. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
117738. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
117739. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
117740. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
117741. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
117742. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
117743. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
117744. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
117745. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
117746. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
117747. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
117748. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
117749. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
117750. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
117751. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
117752. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
117753. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
117754. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
117755. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
117756. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
117757. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
117758. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
117759. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
117760. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
117761. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
117762. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
117763. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
117764. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
117765. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
117766. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
117767. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
117768. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
117769. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
117770. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
117771. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
117772. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
117773. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
117774. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
117775. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
117776. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
117777. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
117778. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
117779. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
117780. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
117781. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
117782. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
117783. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
117784. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
117785. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
117786. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
117787. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
117788. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
117789. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
117790. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
117791. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
117792. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
117793. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
117794. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
117795. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
117796. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
117797. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
117798. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
117799. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
117800. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
117801. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
117802. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
117803. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
117804. BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
117805. BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK
117806. BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
117807. BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID_MASK
117808. BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT
117809. BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID_MASK
117810. BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID__SHIFT
117811. BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK
117812. BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
117813. BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2__RESERVED_MASK
117814. BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2__RESERVED__SHIFT
117815. BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2__RESERVED_MASK
117816. BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2__RESERVED__SHIFT
117817. BIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2__RESERVED_MASK
117818. BIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2__RESERVED__SHIFT
117819. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST_MASK
117820. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST__SHIFT
117821. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING_MASK
117822. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING__SHIFT
117823. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE_MASK
117824. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT
117825. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__IMMEDIATE_READINESS_MASK
117826. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__IMMEDIATE_READINESS__SHIFT
117827. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS_MASK
117828. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS__SHIFT
117829. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
117830. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
117831. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED_MASK
117832. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
117833. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_CAP_MASK
117834. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_CAP__SHIFT
117835. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_EN_MASK
117836. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_EN__SHIFT
117837. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK
117838. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
117839. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK
117840. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
117841. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
117842. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
117843. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK
117844. BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
117845. BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS_MASK
117846. BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS__SHIFT
117847. BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID_MASK
117848. BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID__SHIFT
117849. BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
117850. BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
117851. BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
117852. BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
117853. BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR_MASK
117854. BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT
117855. BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR_MASK
117856. BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT
117857. BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR_MASK
117858. BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT
117859. BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR_MASK
117860. BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT
117861. BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR_MASK
117862. BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT
117863. BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR_MASK
117864. BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT
117865. BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS_MASK
117866. BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS__SHIFT
117867. BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP_MASK
117868. BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP__SHIFT
117869. BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP_MASK
117870. BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP__SHIFT
117871. BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT_MASK
117872. BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT__SHIFT
117873. BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
117874. BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
117875. BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR_MASK
117876. BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR__SHIFT
117877. BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
117878. BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
117879. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING_MASK
117880. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING__SHIFT
117881. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN_MASK
117882. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN__SHIFT
117883. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN_MASK
117884. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN__SHIFT
117885. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS_MASK
117886. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS__SHIFT
117887. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN_MASK
117888. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN__SHIFT
117889. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN_MASK
117890. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN__SHIFT
117891. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
117892. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
117893. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN_MASK
117894. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN__SHIFT
117895. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
117896. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
117897. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN_MASK
117898. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN__SHIFT
117899. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK
117900. BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
117901. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
117902. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
117903. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
117904. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
117905. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
117906. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
117907. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
117908. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
117909. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
117910. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
117911. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
117912. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
117913. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
117914. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
117915. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
117916. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
117917. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
117918. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
117919. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
117920. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
117921. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
117922. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
117923. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
117924. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
117925. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
117926. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
117927. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
117928. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
117929. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
117930. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
117931. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
117932. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
117933. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
117934. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
117935. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
117936. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
117937. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
117938. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
117939. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
117940. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
117941. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
117942. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
117943. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
117944. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
117945. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG_MASK
117946. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
117947. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE_MASK
117948. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
117949. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
117950. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
117951. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
117952. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
117953. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
117954. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
117955. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK
117956. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
117957. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
117958. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
117959. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
117960. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
117961. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
117962. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
117963. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
117964. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
117965. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
117966. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
117967. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
117968. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
117969. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
117970. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
117971. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
117972. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
117973. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
117974. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
117975. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
117976. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
117977. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN_MASK
117978. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN__SHIFT
117979. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN_MASK
117980. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT
117981. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
117982. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
117983. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
117984. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
117985. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK
117986. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
117987. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
117988. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
117989. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
117990. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
117991. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR_MASK
117992. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
117993. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
117994. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
117995. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
117996. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
117997. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
117998. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
117999. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
118000. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
118001. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
118002. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
118003. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
118004. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
118005. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK
118006. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
118007. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID_MASK
118008. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID__SHIFT
118009. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED_MASK
118010. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED__SHIFT
118011. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR_MASK
118012. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR__SHIFT
118013. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR_MASK
118014. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR__SHIFT
118015. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
118016. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
118017. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR_MASK
118018. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT
118019. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
118020. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
118021. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
118022. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
118023. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED_MASK
118024. BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT
118025. BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE_MASK
118026. BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE__SHIFT
118027. BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE_MASK
118028. BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE__SHIFT
118029. BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
118030. BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
118031. BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
118032. BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
118033. BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER_MASK
118034. BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER__SHIFT
118035. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
118036. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
118037. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
118038. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
118039. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
118040. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
118041. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
118042. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
118043. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RESERVED_MASK
118044. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RESERVED__SHIFT
118045. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
118046. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
118047. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
118048. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
118049. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
118050. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
118051. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
118052. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
118053. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
118054. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
118055. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
118056. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
118057. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
118058. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
118059. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK
118060. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
118061. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
118062. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
118063. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED_MASK
118064. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED__SHIFT
118065. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH_MASK
118066. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH__SHIFT
118067. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT_MASK
118068. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT__SHIFT
118069. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER_MASK
118070. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER__SHIFT
118071. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
118072. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
118073. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
118074. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
118075. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
118076. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
118077. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
118078. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
118079. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
118080. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
118081. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
118082. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
118083. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
118084. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
118085. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
118086. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
118087. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN_MASK
118088. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
118089. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
118090. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
118091. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
118092. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
118093. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
118094. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
118095. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC_MASK
118096. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
118097. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
118098. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
118099. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
118100. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
118101. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
118102. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
118103. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS_MASK
118104. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS__SHIFT
118105. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL_MASK
118106. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL__SHIFT
118107. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
118108. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
118109. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK_MASK
118110. BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT
118111. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
118112. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
118113. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
118114. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
118115. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
118116. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
118117. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
118118. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
118119. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
118120. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
118121. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
118122. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
118123. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
118124. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
118125. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
118126. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
118127. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
118128. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
118129. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
118130. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
118131. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
118132. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
118133. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
118134. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
118135. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
118136. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
118137. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
118138. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
118139. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
118140. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
118141. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
118142. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
118143. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
118144. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
118145. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE_MASK
118146. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE__SHIFT
118147. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
118148. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
118149. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
118150. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
118151. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING_MASK
118152. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING__SHIFT
118153. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
118154. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
118155. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
118156. BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
118157. BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY__MAX_LAT_MASK
118158. BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY__MAX_LAT__SHIFT
118159. BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT__MIN_GNT_MASK
118160. BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT__MIN_GNT__SHIFT
118161. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID_MASK
118162. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT
118163. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK
118164. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
118165. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK
118166. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
118167. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
118168. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
118169. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
118170. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
118171. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK
118172. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
118173. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
118174. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
118175. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
118176. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
118177. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
118178. BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
118179. BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID_MASK
118180. BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID__SHIFT
118181. BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR_MASK
118182. BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
118183. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64_MASK
118184. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT
118185. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK_MASK
118186. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK__SHIFT
118187. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
118188. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
118189. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
118190. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
118191. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK
118192. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
118193. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN_MASK
118194. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT
118195. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
118196. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
118197. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
118198. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
118199. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
118200. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
118201. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
118202. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
118203. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA_MASK
118204. BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT
118205. BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK
118206. BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
118207. BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING_MASK
118208. BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING__SHIFT
118209. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
118210. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
118211. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
118212. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
118213. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
118214. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
118215. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
118216. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
118217. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
118218. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
118219. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
118220. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
118221. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
118222. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
118223. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
118224. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
118225. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
118226. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
118227. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
118228. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
118229. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
118230. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
118231. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
118232. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
118233. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
118234. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
118235. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
118236. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
118237. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
118238. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
118239. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
118240. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
118241. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
118242. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
118243. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
118244. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
118245. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
118246. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
118247. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
118248. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
118249. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
118250. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
118251. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
118252. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
118253. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
118254. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
118255. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
118256. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
118257. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
118258. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
118259. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__STU_MASK
118260. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__STU__SHIFT
118261. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
118262. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
118263. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
118264. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
118265. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
118266. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
118267. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID_MASK
118268. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT
118269. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK
118270. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
118271. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE_MASK
118272. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT
118273. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
118274. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
118275. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
118276. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
118277. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION_MASK
118278. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION__SHIFT
118279. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
118280. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
118281. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
118282. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
118283. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
118284. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
118285. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
118286. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
118287. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
118288. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
118289. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
118290. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
118291. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
118292. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
118293. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
118294. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
118295. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
118296. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
118297. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
118298. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
118299. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
118300. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
118301. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
118302. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
118303. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
118304. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
118305. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
118306. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
118307. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
118308. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
118309. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
118310. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
118311. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK
118312. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
118313. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK
118314. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
118315. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK
118316. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
118317. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK
118318. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
118319. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
118320. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
118321. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
118322. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
118323. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
118324. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
118325. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
118326. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
118327. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
118328. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
118329. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
118330. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
118331. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
118332. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
118333. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
118334. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
118335. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
118336. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
118337. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
118338. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
118339. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
118340. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
118341. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
118342. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
118343. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
118344. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
118345. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
118346. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
118347. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
118348. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
118349. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
118350. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
118351. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
118352. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
118353. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
118354. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
118355. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
118356. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
118357. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
118358. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
118359. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
118360. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
118361. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
118362. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
118363. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
118364. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
118365. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
118366. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
118367. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
118368. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
118369. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
118370. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
118371. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
118372. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
118373. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
118374. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
118375. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
118376. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
118377. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
118378. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
118379. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
118380. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
118381. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
118382. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
118383. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
118384. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
118385. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
118386. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
118387. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
118388. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
118389. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
118390. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
118391. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
118392. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
118393. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
118394. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
118395. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
118396. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
118397. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
118398. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
118399. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
118400. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
118401. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
118402. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
118403. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
118404. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
118405. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
118406. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
118407. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
118408. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
118409. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
118410. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
118411. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
118412. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
118413. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
118414. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
118415. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
118416. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
118417. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
118418. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
118419. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
118420. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
118421. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
118422. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
118423. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
118424. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
118425. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
118426. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
118427. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
118428. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
118429. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
118430. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
118431. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
118432. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
118433. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
118434. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
118435. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
118436. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
118437. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
118438. BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
118439. BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK
118440. BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
118441. BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID_MASK
118442. BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT
118443. BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID_MASK
118444. BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID__SHIFT
118445. BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK
118446. BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
118447. BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CAP2__RESERVED_MASK
118448. BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CAP2__RESERVED__SHIFT
118449. BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CNTL2__RESERVED_MASK
118450. BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CNTL2__RESERVED__SHIFT
118451. BIF_CFG_DEV0_EPF0_VF2_1_SLOT_STATUS2__RESERVED_MASK
118452. BIF_CFG_DEV0_EPF0_VF2_1_SLOT_STATUS2__RESERVED__SHIFT
118453. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST_MASK
118454. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST__SHIFT
118455. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING_MASK
118456. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING__SHIFT
118457. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE_MASK
118458. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT
118459. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__IMMEDIATE_READINESS_MASK
118460. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__IMMEDIATE_READINESS__SHIFT
118461. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS_MASK
118462. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS__SHIFT
118463. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
118464. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
118465. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED_MASK
118466. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
118467. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_CAP_MASK
118468. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_CAP__SHIFT
118469. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_EN_MASK
118470. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_EN__SHIFT
118471. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK
118472. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
118473. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK
118474. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
118475. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
118476. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
118477. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK
118478. BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
118479. BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS_MASK
118480. BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS__SHIFT
118481. BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID_MASK
118482. BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID__SHIFT
118483. BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK
118484. BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
118485. BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
118486. BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
118487. BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK
118488. BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT
118489. BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK
118490. BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT
118491. BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK
118492. BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT
118493. BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK
118494. BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT
118495. BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK
118496. BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT
118497. BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK
118498. BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT
118499. BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK
118500. BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT
118501. BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK
118502. BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT
118503. BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK
118504. BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT
118505. BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK
118506. BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT
118507. BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK
118508. BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
118509. BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK
118510. BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT
118511. BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
118512. BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
118513. BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK
118514. BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT
118515. BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK
118516. BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT
118517. BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK
118518. BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT
118519. BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK
118520. BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT
118521. BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK
118522. BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT
118523. BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK
118524. BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT
118525. BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
118526. BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
118527. BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK
118528. BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT
118529. BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK
118530. BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
118531. BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK
118532. BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT
118533. BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK
118534. BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
118535. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
118536. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
118537. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
118538. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
118539. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
118540. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
118541. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
118542. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
118543. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
118544. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
118545. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
118546. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
118547. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
118548. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
118549. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
118550. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
118551. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
118552. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
118553. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
118554. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
118555. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
118556. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
118557. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK
118558. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
118559. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
118560. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
118561. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK
118562. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
118563. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
118564. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
118565. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
118566. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
118567. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
118568. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
118569. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
118570. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
118571. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
118572. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
118573. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
118574. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
118575. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
118576. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
118577. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
118578. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
118579. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK
118580. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT
118581. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK
118582. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT
118583. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
118584. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
118585. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
118586. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
118587. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
118588. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
118589. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK
118590. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
118591. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
118592. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
118593. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
118594. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
118595. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
118596. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
118597. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
118598. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
118599. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
118600. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
118601. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
118602. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
118603. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
118604. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
118605. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
118606. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
118607. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
118608. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
118609. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
118610. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
118611. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK
118612. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT
118613. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK
118614. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT
118615. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
118616. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
118617. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
118618. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
118619. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK
118620. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
118621. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
118622. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
118623. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK
118624. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
118625. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK
118626. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT
118627. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
118628. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
118629. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
118630. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
118631. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
118632. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
118633. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK
118634. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
118635. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
118636. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
118637. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
118638. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
118639. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK
118640. BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
118641. BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK
118642. BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT
118643. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK
118644. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT
118645. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK
118646. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT
118647. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK
118648. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT
118649. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
118650. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
118651. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK
118652. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT
118653. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK
118654. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
118655. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
118656. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
118657. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK
118658. BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT
118659. BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE_MASK
118660. BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE__SHIFT
118661. BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE_MASK
118662. BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE__SHIFT
118663. BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
118664. BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
118665. BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
118666. BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
118667. BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK
118668. BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT
118669. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
118670. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
118671. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
118672. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
118673. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
118674. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
118675. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
118676. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
118677. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
118678. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
118679. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
118680. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
118681. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
118682. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
118683. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
118684. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
118685. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
118686. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
118687. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
118688. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
118689. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK
118690. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
118691. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK
118692. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
118693. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
118694. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
118695. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK
118696. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT
118697. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK
118698. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT
118699. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK
118700. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT
118701. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK
118702. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT
118703. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
118704. BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
118705. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
118706. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
118707. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK
118708. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
118709. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
118710. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
118711. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
118712. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
118713. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
118714. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
118715. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
118716. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
118717. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
118718. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
118719. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK
118720. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT
118721. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
118722. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
118723. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
118724. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
118725. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
118726. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
118727. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK
118728. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT
118729. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
118730. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
118731. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
118732. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
118733. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
118734. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
118735. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK
118736. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT
118737. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK
118738. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT
118739. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
118740. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
118741. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK
118742. BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT
118743. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
118744. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
118745. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
118746. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
118747. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
118748. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
118749. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
118750. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
118751. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
118752. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
118753. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
118754. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
118755. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
118756. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
118757. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
118758. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
118759. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
118760. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
118761. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
118762. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
118763. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
118764. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
118765. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
118766. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
118767. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK
118768. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT
118769. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
118770. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
118771. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
118772. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
118773. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK
118774. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT
118775. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
118776. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
118777. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
118778. BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
118779. BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK
118780. BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT
118781. BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK
118782. BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT
118783. BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK
118784. BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT
118785. BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK
118786. BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT
118787. BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK
118788. BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT
118789. BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
118790. BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
118791. BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
118792. BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
118793. BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK
118794. BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT
118795. BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK
118796. BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
118797. BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK
118798. BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
118799. BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
118800. BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
118801. BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK
118802. BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT
118803. BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK
118804. BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT
118805. BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK
118806. BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT
118807. BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK
118808. BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT
118809. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
118810. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
118811. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
118812. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
118813. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK
118814. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
118815. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK
118816. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT
118817. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
118818. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
118819. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
118820. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
118821. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
118822. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
118823. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
118824. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
118825. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK
118826. BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT
118827. BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK
118828. BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT
118829. BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK
118830. BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT
118831. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
118832. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
118833. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
118834. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
118835. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
118836. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
118837. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
118838. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
118839. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
118840. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
118841. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
118842. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
118843. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
118844. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
118845. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
118846. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
118847. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
118848. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
118849. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
118850. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
118851. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
118852. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
118853. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
118854. BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
118855. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
118856. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
118857. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
118858. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
118859. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
118860. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
118861. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
118862. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
118863. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
118864. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
118865. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
118866. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
118867. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
118868. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
118869. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
118870. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
118871. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
118872. BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
118873. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
118874. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
118875. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
118876. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
118877. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
118878. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
118879. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE_MASK
118880. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
118881. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU_MASK
118882. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU__SHIFT
118883. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
118884. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
118885. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
118886. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
118887. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
118888. BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
118889. BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK
118890. BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT
118891. BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK
118892. BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
118893. BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK
118894. BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT
118895. BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK
118896. BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
118897. BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
118898. BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
118899. BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK
118900. BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT
118901. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
118902. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
118903. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
118904. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
118905. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
118906. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
118907. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
118908. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
118909. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
118910. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
118911. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
118912. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
118913. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
118914. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
118915. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
118916. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
118917. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
118918. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
118919. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
118920. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
118921. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
118922. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
118923. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
118924. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
118925. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
118926. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
118927. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
118928. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
118929. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
118930. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
118931. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
118932. BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
118933. BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK
118934. BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
118935. BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK
118936. BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
118937. BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK
118938. BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
118939. BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK
118940. BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
118941. BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
118942. BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
118943. BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
118944. BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
118945. BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
118946. BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
118947. BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
118948. BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
118949. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
118950. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
118951. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
118952. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
118953. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
118954. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
118955. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
118956. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
118957. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
118958. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
118959. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
118960. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
118961. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
118962. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
118963. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
118964. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
118965. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
118966. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
118967. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
118968. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
118969. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
118970. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
118971. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
118972. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
118973. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
118974. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
118975. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
118976. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
118977. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
118978. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
118979. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
118980. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
118981. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
118982. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
118983. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
118984. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
118985. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
118986. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
118987. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
118988. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
118989. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
118990. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
118991. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
118992. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
118993. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
118994. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
118995. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
118996. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
118997. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
118998. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
118999. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
119000. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
119001. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
119002. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
119003. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
119004. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
119005. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
119006. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
119007. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
119008. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
119009. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
119010. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
119011. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
119012. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
119013. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
119014. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
119015. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
119016. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
119017. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
119018. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
119019. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
119020. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
119021. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
119022. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
119023. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
119024. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
119025. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
119026. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
119027. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
119028. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
119029. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
119030. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
119031. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
119032. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
119033. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
119034. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
119035. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
119036. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
119037. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
119038. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
119039. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
119040. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
119041. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
119042. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
119043. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
119044. BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
119045. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
119046. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
119047. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
119048. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
119049. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
119050. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
119051. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
119052. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
119053. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
119054. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
119055. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
119056. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
119057. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
119058. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
119059. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
119060. BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
119061. BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK
119062. BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
119063. BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK
119064. BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT
119065. BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK
119066. BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT
119067. BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK
119068. BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT
119069. BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK
119070. BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT
119071. BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK
119072. BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT
119073. BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK
119074. BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT
119075. BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK
119076. BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT
119077. BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK
119078. BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT
119079. BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
119080. BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
119081. BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK
119082. BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT
119083. BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK
119084. BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT
119085. BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK
119086. BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
119087. BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK
119088. BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
119089. BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
119090. BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
119091. BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK
119092. BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
119093. BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK
119094. BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT
119095. BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK
119096. BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT
119097. BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
119098. BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
119099. BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
119100. BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
119101. BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1__BASE_ADDR_MASK
119102. BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1__BASE_ADDR__SHIFT
119103. BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2__BASE_ADDR_MASK
119104. BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2__BASE_ADDR__SHIFT
119105. BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3__BASE_ADDR_MASK
119106. BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3__BASE_ADDR__SHIFT
119107. BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4__BASE_ADDR_MASK
119108. BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4__BASE_ADDR__SHIFT
119109. BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5__BASE_ADDR_MASK
119110. BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5__BASE_ADDR__SHIFT
119111. BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6__BASE_ADDR_MASK
119112. BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6__BASE_ADDR__SHIFT
119113. BIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS__BASE_CLASS_MASK
119114. BIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS__BASE_CLASS__SHIFT
119115. BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_CAP_MASK
119116. BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_CAP__SHIFT
119117. BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_COMP_MASK
119118. BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_COMP__SHIFT
119119. BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_STRT_MASK
119120. BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_STRT__SHIFT
119121. BIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
119122. BIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
119123. BIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR__CAP_PTR_MASK
119124. BIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR__CAP_PTR__SHIFT
119125. BIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
119126. BIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
119127. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__AD_STEPPING_MASK
119128. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__AD_STEPPING__SHIFT
119129. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__BUS_MASTER_EN_MASK
119130. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__BUS_MASTER_EN__SHIFT
119131. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__FAST_B2B_EN_MASK
119132. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__FAST_B2B_EN__SHIFT
119133. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__INT_DIS_MASK
119134. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__INT_DIS__SHIFT
119135. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__IO_ACCESS_EN_MASK
119136. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__IO_ACCESS_EN__SHIFT
119137. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__MEM_ACCESS_EN_MASK
119138. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__MEM_ACCESS_EN__SHIFT
119139. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
119140. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
119141. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__PAL_SNOOP_EN_MASK
119142. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__PAL_SNOOP_EN__SHIFT
119143. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
119144. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
119145. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__SERR_EN_MASK
119146. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__SERR_EN__SHIFT
119147. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__SPECIAL_CYCLE_EN_MASK
119148. BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
119149. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
119150. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
119151. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
119152. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
119153. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
119154. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
119155. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
119156. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
119157. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
119158. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
119159. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
119160. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
119161. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
119162. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
119163. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
119164. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
119165. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
119166. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
119167. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
119168. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
119169. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
119170. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
119171. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
119172. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
119173. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
119174. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
119175. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
119176. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
119177. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
119178. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
119179. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
119180. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
119181. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
119182. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
119183. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
119184. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
119185. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
119186. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
119187. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
119188. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
119189. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
119190. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
119191. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
119192. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
119193. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__EXTENDED_TAG_MASK
119194. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
119195. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__FLR_CAPABLE_MASK
119196. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
119197. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
119198. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
119199. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
119200. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
119201. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
119202. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
119203. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__PHANTOM_FUNC_MASK
119204. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
119205. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
119206. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
119207. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
119208. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
119209. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
119210. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
119211. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
119212. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
119213. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
119214. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
119215. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
119216. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
119217. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
119218. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
119219. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
119220. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
119221. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
119222. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
119223. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
119224. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
119225. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__LTR_EN_MASK
119226. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__LTR_EN__SHIFT
119227. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__OBFF_EN_MASK
119228. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__OBFF_EN__SHIFT
119229. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
119230. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
119231. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
119232. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
119233. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__CORR_ERR_EN_MASK
119234. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
119235. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
119236. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
119237. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
119238. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
119239. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__INITIATE_FLR_MASK
119240. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
119241. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
119242. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
119243. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
119244. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
119245. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
119246. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
119247. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
119248. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
119249. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
119250. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
119251. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
119252. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
119253. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__USR_REPORT_EN_MASK
119254. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
119255. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID__DEVICE_ID_MASK
119256. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID__DEVICE_ID__SHIFT
119257. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2__RESERVED_MASK
119258. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2__RESERVED__SHIFT
119259. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__AUX_PWR_MASK
119260. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__AUX_PWR__SHIFT
119261. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__CORR_ERR_MASK
119262. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__CORR_ERR__SHIFT
119263. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
119264. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
119265. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__FATAL_ERR_MASK
119266. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__FATAL_ERR__SHIFT
119267. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
119268. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
119269. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
119270. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
119271. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__USR_DETECTED_MASK
119272. BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__USR_DETECTED__SHIFT
119273. BIF_CFG_DEV0_EPF0_VF30_0_HEADER__DEVICE_TYPE_MASK
119274. BIF_CFG_DEV0_EPF0_VF30_0_HEADER__DEVICE_TYPE__SHIFT
119275. BIF_CFG_DEV0_EPF0_VF30_0_HEADER__HEADER_TYPE_MASK
119276. BIF_CFG_DEV0_EPF0_VF30_0_HEADER__HEADER_TYPE__SHIFT
119277. BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
119278. BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
119279. BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
119280. BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
119281. BIF_CFG_DEV0_EPF0_VF30_0_LATENCY__LATENCY_TIMER_MASK
119282. BIF_CFG_DEV0_EPF0_VF30_0_LATENCY__LATENCY_TIMER__SHIFT
119283. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
119284. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
119285. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
119286. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
119287. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
119288. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
119289. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
119290. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
119291. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
119292. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
119293. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
119294. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
119295. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
119296. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
119297. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
119298. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
119299. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
119300. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
119301. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
119302. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
119303. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
119304. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
119305. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__L1_EXIT_LATENCY_MASK
119306. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
119307. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
119308. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
119309. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_SPEED_MASK
119310. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_SPEED__SHIFT
119311. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_WIDTH_MASK
119312. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_WIDTH__SHIFT
119313. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__PM_SUPPORT_MASK
119314. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__PM_SUPPORT__SHIFT
119315. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__PORT_NUMBER_MASK
119316. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__PORT_NUMBER__SHIFT
119317. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
119318. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
119319. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
119320. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
119321. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
119322. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
119323. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
119324. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
119325. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
119326. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
119327. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
119328. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
119329. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
119330. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
119331. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
119332. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
119333. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__XMIT_MARGIN_MASK
119334. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
119335. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
119336. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
119337. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
119338. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
119339. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
119340. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
119341. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__EXTENDED_SYNC_MASK
119342. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
119343. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
119344. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
119345. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
119346. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
119347. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
119348. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
119349. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_DIS_MASK
119350. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_DIS__SHIFT
119351. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__PM_CONTROL_MASK
119352. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__PM_CONTROL__SHIFT
119353. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
119354. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
119355. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__RETRAIN_LINK_MASK
119356. BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__RETRAIN_LINK__SHIFT
119357. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
119358. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
119359. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
119360. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
119361. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
119362. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
119363. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
119364. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
119365. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
119366. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
119367. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
119368. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
119369. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
119370. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
119371. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
119372. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
119373. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
119374. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
119375. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
119376. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
119377. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
119378. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
119379. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
119380. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
119381. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__DL_ACTIVE_MASK
119382. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__DL_ACTIVE__SHIFT
119383. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
119384. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
119385. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
119386. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
119387. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_TRAINING_MASK
119388. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_TRAINING__SHIFT
119389. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
119390. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
119391. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
119392. BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
119393. BIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY__MAX_LAT_MASK
119394. BIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY__MAX_LAT__SHIFT
119395. BIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT__MIN_GNT_MASK
119396. BIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT__MIN_GNT__SHIFT
119397. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST__CAP_ID_MASK
119398. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST__CAP_ID__SHIFT
119399. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST__NEXT_PTR_MASK
119400. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
119401. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_EN_MASK
119402. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
119403. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
119404. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
119405. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
119406. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
119407. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA__MSIX_PBA_BIR_MASK
119408. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
119409. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
119410. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
119411. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
119412. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
119413. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
119414. BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
119415. BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST__CAP_ID_MASK
119416. BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST__CAP_ID__SHIFT
119417. BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST__NEXT_PTR_MASK
119418. BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
119419. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64__MSI_MASK_64_MASK
119420. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64__MSI_MASK_64__SHIFT
119421. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK__MSI_MASK_MASK
119422. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK__MSI_MASK__SHIFT
119423. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
119424. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
119425. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
119426. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
119427. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_64BIT_MASK
119428. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
119429. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_EN_MASK
119430. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_EN__SHIFT
119431. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
119432. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
119433. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
119434. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
119435. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
119436. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
119437. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
119438. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
119439. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA__MSI_DATA_MASK
119440. BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA__MSI_DATA__SHIFT
119441. BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64__MSI_PENDING_64_MASK
119442. BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
119443. BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING__MSI_PENDING_MASK
119444. BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING__MSI_PENDING__SHIFT
119445. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
119446. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
119447. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
119448. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
119449. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
119450. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
119451. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
119452. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
119453. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
119454. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
119455. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
119456. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
119457. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
119458. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
119459. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
119460. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
119461. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
119462. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
119463. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
119464. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
119465. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
119466. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
119467. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
119468. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
119469. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
119470. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
119471. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
119472. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
119473. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
119474. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
119475. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
119476. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
119477. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
119478. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
119479. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
119480. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
119481. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
119482. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
119483. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
119484. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
119485. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
119486. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
119487. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
119488. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
119489. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
119490. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
119491. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
119492. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
119493. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
119494. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
119495. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL__STU_MASK
119496. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL__STU__SHIFT
119497. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
119498. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
119499. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
119500. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
119501. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
119502. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
119503. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST__CAP_ID_MASK
119504. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST__CAP_ID__SHIFT
119505. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST__NEXT_PTR_MASK
119506. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
119507. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__DEVICE_TYPE_MASK
119508. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__DEVICE_TYPE__SHIFT
119509. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
119510. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
119511. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
119512. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
119513. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__VERSION_MASK
119514. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__VERSION__SHIFT
119515. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
119516. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
119517. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
119518. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
119519. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
119520. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
119521. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
119522. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
119523. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
119524. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
119525. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
119526. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
119527. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
119528. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
119529. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
119530. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
119531. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
119532. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
119533. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
119534. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
119535. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
119536. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
119537. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
119538. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
119539. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
119540. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
119541. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
119542. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
119543. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
119544. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
119545. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
119546. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
119547. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0__TLP_HDR_MASK
119548. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
119549. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1__TLP_HDR_MASK
119550. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
119551. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2__TLP_HDR_MASK
119552. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
119553. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3__TLP_HDR_MASK
119554. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
119555. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
119556. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
119557. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
119558. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
119559. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
119560. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
119561. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
119562. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
119563. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
119564. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
119565. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
119566. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
119567. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
119568. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
119569. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
119570. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
119571. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
119572. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
119573. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
119574. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
119575. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
119576. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
119577. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
119578. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
119579. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
119580. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
119581. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
119582. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
119583. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
119584. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
119585. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
119586. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
119587. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
119588. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
119589. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
119590. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
119591. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
119592. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
119593. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
119594. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
119595. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
119596. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
119597. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
119598. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
119599. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
119600. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
119601. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
119602. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
119603. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
119604. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
119605. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
119606. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
119607. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
119608. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
119609. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
119610. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
119611. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
119612. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
119613. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
119614. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
119615. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
119616. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
119617. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
119618. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
119619. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
119620. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
119621. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
119622. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
119623. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
119624. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
119625. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
119626. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
119627. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
119628. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
119629. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
119630. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
119631. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
119632. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
119633. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
119634. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
119635. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
119636. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
119637. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
119638. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
119639. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
119640. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
119641. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
119642. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
119643. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
119644. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
119645. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
119646. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
119647. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
119648. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
119649. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
119650. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
119651. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
119652. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
119653. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
119654. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
119655. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
119656. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
119657. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
119658. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
119659. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
119660. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
119661. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
119662. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
119663. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
119664. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
119665. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
119666. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
119667. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
119668. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
119669. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
119670. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
119671. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
119672. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
119673. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
119674. BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
119675. BIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE__PROG_INTERFACE_MASK
119676. BIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
119677. BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID__MAJOR_REV_ID_MASK
119678. BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID__MAJOR_REV_ID__SHIFT
119679. BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID__MINOR_REV_ID_MASK
119680. BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID__MINOR_REV_ID__SHIFT
119681. BIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR__BASE_ADDR_MASK
119682. BIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
119683. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__CAP_LIST_MASK
119684. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__CAP_LIST__SHIFT
119685. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__DEVSEL_TIMING_MASK
119686. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__DEVSEL_TIMING__SHIFT
119687. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__FAST_BACK_CAPABLE_MASK
119688. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__FAST_BACK_CAPABLE__SHIFT
119689. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__IMMEDIATE_READINESS_MASK
119690. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__IMMEDIATE_READINESS__SHIFT
119691. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__INT_STATUS_MASK
119692. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__INT_STATUS__SHIFT
119693. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
119694. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
119695. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__PARITY_ERROR_DETECTED_MASK
119696. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
119697. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__PCI_66_CAP_MASK
119698. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__PCI_66_CAP__SHIFT
119699. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__RECEIVED_MASTER_ABORT_MASK
119700. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
119701. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__RECEIVED_TARGET_ABORT_MASK
119702. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
119703. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
119704. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
119705. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__SIGNAL_TARGET_ABORT_MASK
119706. BIF_CFG_DEV0_EPF0_VF30_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
119707. BIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS__SUB_CLASS_MASK
119708. BIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS__SUB_CLASS__SHIFT
119709. BIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID__VENDOR_ID_MASK
119710. BIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID__VENDOR_ID__SHIFT
119711. BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
119712. BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
119713. BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
119714. BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
119715. BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1__BASE_ADDR_MASK
119716. BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1__BASE_ADDR__SHIFT
119717. BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2__BASE_ADDR_MASK
119718. BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2__BASE_ADDR__SHIFT
119719. BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3__BASE_ADDR_MASK
119720. BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3__BASE_ADDR__SHIFT
119721. BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4__BASE_ADDR_MASK
119722. BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4__BASE_ADDR__SHIFT
119723. BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5__BASE_ADDR_MASK
119724. BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5__BASE_ADDR__SHIFT
119725. BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6__BASE_ADDR_MASK
119726. BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6__BASE_ADDR__SHIFT
119727. BIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS__BASE_CLASS_MASK
119728. BIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS__BASE_CLASS__SHIFT
119729. BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_CAP_MASK
119730. BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_CAP__SHIFT
119731. BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_COMP_MASK
119732. BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_COMP__SHIFT
119733. BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_STRT_MASK
119734. BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_STRT__SHIFT
119735. BIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
119736. BIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
119737. BIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR__CAP_PTR_MASK
119738. BIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR__CAP_PTR__SHIFT
119739. BIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
119740. BIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
119741. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__AD_STEPPING_MASK
119742. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__AD_STEPPING__SHIFT
119743. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__BUS_MASTER_EN_MASK
119744. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__BUS_MASTER_EN__SHIFT
119745. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__FAST_B2B_EN_MASK
119746. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__FAST_B2B_EN__SHIFT
119747. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__INT_DIS_MASK
119748. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__INT_DIS__SHIFT
119749. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__IO_ACCESS_EN_MASK
119750. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__IO_ACCESS_EN__SHIFT
119751. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__MEM_ACCESS_EN_MASK
119752. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__MEM_ACCESS_EN__SHIFT
119753. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
119754. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
119755. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__PAL_SNOOP_EN_MASK
119756. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__PAL_SNOOP_EN__SHIFT
119757. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
119758. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
119759. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__SERR_EN_MASK
119760. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__SERR_EN__SHIFT
119761. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__SPECIAL_CYCLE_EN_MASK
119762. BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
119763. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
119764. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
119765. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
119766. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
119767. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
119768. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
119769. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
119770. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
119771. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
119772. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
119773. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
119774. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
119775. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
119776. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
119777. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
119778. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
119779. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
119780. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
119781. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
119782. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
119783. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
119784. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
119785. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
119786. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
119787. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
119788. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
119789. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
119790. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
119791. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
119792. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
119793. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
119794. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
119795. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
119796. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
119797. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
119798. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
119799. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
119800. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
119801. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
119802. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
119803. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
119804. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
119805. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
119806. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
119807. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__EXTENDED_TAG_MASK
119808. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
119809. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__FLR_CAPABLE_MASK
119810. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
119811. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
119812. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
119813. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
119814. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
119815. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
119816. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
119817. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__PHANTOM_FUNC_MASK
119818. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
119819. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
119820. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
119821. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
119822. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
119823. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
119824. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
119825. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
119826. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
119827. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
119828. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
119829. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
119830. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
119831. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
119832. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
119833. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
119834. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
119835. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
119836. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
119837. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
119838. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
119839. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__LTR_EN_MASK
119840. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__LTR_EN__SHIFT
119841. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__OBFF_EN_MASK
119842. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__OBFF_EN__SHIFT
119843. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
119844. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
119845. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
119846. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
119847. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__CORR_ERR_EN_MASK
119848. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
119849. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
119850. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
119851. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
119852. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
119853. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__INITIATE_FLR_MASK
119854. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
119855. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
119856. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
119857. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
119858. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
119859. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
119860. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
119861. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
119862. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
119863. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
119864. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
119865. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
119866. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
119867. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__USR_REPORT_EN_MASK
119868. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
119869. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID__DEVICE_ID_MASK
119870. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID__DEVICE_ID__SHIFT
119871. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2__RESERVED_MASK
119872. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2__RESERVED__SHIFT
119873. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__AUX_PWR_MASK
119874. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__AUX_PWR__SHIFT
119875. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__CORR_ERR_MASK
119876. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__CORR_ERR__SHIFT
119877. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
119878. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
119879. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__FATAL_ERR_MASK
119880. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__FATAL_ERR__SHIFT
119881. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
119882. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
119883. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
119884. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
119885. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__USR_DETECTED_MASK
119886. BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__USR_DETECTED__SHIFT
119887. BIF_CFG_DEV0_EPF0_VF30_1_HEADER__DEVICE_TYPE_MASK
119888. BIF_CFG_DEV0_EPF0_VF30_1_HEADER__DEVICE_TYPE__SHIFT
119889. BIF_CFG_DEV0_EPF0_VF30_1_HEADER__HEADER_TYPE_MASK
119890. BIF_CFG_DEV0_EPF0_VF30_1_HEADER__HEADER_TYPE__SHIFT
119891. BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
119892. BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
119893. BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
119894. BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
119895. BIF_CFG_DEV0_EPF0_VF30_1_LATENCY__LATENCY_TIMER_MASK
119896. BIF_CFG_DEV0_EPF0_VF30_1_LATENCY__LATENCY_TIMER__SHIFT
119897. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
119898. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
119899. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
119900. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
119901. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
119902. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
119903. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
119904. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
119905. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
119906. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
119907. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
119908. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
119909. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
119910. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
119911. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
119912. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
119913. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
119914. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
119915. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
119916. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
119917. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
119918. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
119919. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__L1_EXIT_LATENCY_MASK
119920. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
119921. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
119922. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
119923. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_SPEED_MASK
119924. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_SPEED__SHIFT
119925. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_WIDTH_MASK
119926. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_WIDTH__SHIFT
119927. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__PM_SUPPORT_MASK
119928. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__PM_SUPPORT__SHIFT
119929. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__PORT_NUMBER_MASK
119930. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__PORT_NUMBER__SHIFT
119931. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
119932. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
119933. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
119934. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
119935. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
119936. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
119937. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
119938. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
119939. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
119940. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
119941. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
119942. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
119943. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
119944. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
119945. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
119946. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
119947. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__XMIT_MARGIN_MASK
119948. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
119949. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
119950. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
119951. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
119952. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
119953. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
119954. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
119955. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__EXTENDED_SYNC_MASK
119956. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
119957. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
119958. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
119959. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
119960. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
119961. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
119962. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
119963. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_DIS_MASK
119964. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_DIS__SHIFT
119965. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__PM_CONTROL_MASK
119966. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__PM_CONTROL__SHIFT
119967. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
119968. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
119969. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__RETRAIN_LINK_MASK
119970. BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__RETRAIN_LINK__SHIFT
119971. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
119972. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
119973. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
119974. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
119975. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
119976. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
119977. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
119978. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
119979. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
119980. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
119981. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
119982. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
119983. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
119984. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
119985. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
119986. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
119987. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
119988. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
119989. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
119990. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
119991. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
119992. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
119993. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
119994. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
119995. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__DL_ACTIVE_MASK
119996. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__DL_ACTIVE__SHIFT
119997. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
119998. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
119999. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
120000. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
120001. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_TRAINING_MASK
120002. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_TRAINING__SHIFT
120003. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
120004. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
120005. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
120006. BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
120007. BIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY__MAX_LAT_MASK
120008. BIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY__MAX_LAT__SHIFT
120009. BIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT__MIN_GNT_MASK
120010. BIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT__MIN_GNT__SHIFT
120011. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST__CAP_ID_MASK
120012. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST__CAP_ID__SHIFT
120013. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST__NEXT_PTR_MASK
120014. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
120015. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_EN_MASK
120016. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
120017. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
120018. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
120019. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
120020. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
120021. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA__MSIX_PBA_BIR_MASK
120022. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
120023. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
120024. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
120025. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
120026. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
120027. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
120028. BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
120029. BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST__CAP_ID_MASK
120030. BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST__CAP_ID__SHIFT
120031. BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST__NEXT_PTR_MASK
120032. BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
120033. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64__MSI_MASK_64_MASK
120034. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64__MSI_MASK_64__SHIFT
120035. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK__MSI_MASK_MASK
120036. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK__MSI_MASK__SHIFT
120037. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
120038. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
120039. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
120040. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
120041. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_64BIT_MASK
120042. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
120043. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_EN_MASK
120044. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_EN__SHIFT
120045. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
120046. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
120047. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
120048. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
120049. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
120050. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
120051. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
120052. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
120053. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA__MSI_DATA_MASK
120054. BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA__MSI_DATA__SHIFT
120055. BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64__MSI_PENDING_64_MASK
120056. BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
120057. BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING__MSI_PENDING_MASK
120058. BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING__MSI_PENDING__SHIFT
120059. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
120060. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
120061. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
120062. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
120063. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
120064. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
120065. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
120066. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
120067. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
120068. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
120069. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
120070. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
120071. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
120072. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
120073. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
120074. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
120075. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
120076. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
120077. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
120078. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
120079. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
120080. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
120081. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
120082. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
120083. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
120084. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
120085. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
120086. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
120087. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
120088. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
120089. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
120090. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
120091. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
120092. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
120093. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
120094. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
120095. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
120096. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
120097. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
120098. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
120099. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
120100. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
120101. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
120102. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
120103. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
120104. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
120105. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
120106. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
120107. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
120108. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
120109. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL__STU_MASK
120110. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL__STU__SHIFT
120111. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
120112. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
120113. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
120114. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
120115. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
120116. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
120117. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST__CAP_ID_MASK
120118. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST__CAP_ID__SHIFT
120119. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST__NEXT_PTR_MASK
120120. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
120121. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__DEVICE_TYPE_MASK
120122. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__DEVICE_TYPE__SHIFT
120123. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
120124. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
120125. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
120126. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
120127. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__VERSION_MASK
120128. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__VERSION__SHIFT
120129. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
120130. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
120131. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
120132. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
120133. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
120134. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
120135. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
120136. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
120137. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
120138. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
120139. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
120140. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
120141. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
120142. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
120143. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
120144. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
120145. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
120146. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
120147. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
120148. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
120149. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
120150. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
120151. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
120152. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
120153. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
120154. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
120155. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
120156. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
120157. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
120158. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
120159. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
120160. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
120161. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0__TLP_HDR_MASK
120162. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
120163. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1__TLP_HDR_MASK
120164. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
120165. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2__TLP_HDR_MASK
120166. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
120167. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3__TLP_HDR_MASK
120168. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
120169. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
120170. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
120171. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
120172. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
120173. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
120174. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
120175. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
120176. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
120177. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
120178. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
120179. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
120180. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
120181. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
120182. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
120183. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
120184. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
120185. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
120186. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
120187. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
120188. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
120189. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
120190. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
120191. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
120192. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
120193. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
120194. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
120195. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
120196. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
120197. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
120198. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
120199. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
120200. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
120201. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
120202. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
120203. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
120204. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
120205. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
120206. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
120207. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
120208. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
120209. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
120210. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
120211. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
120212. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
120213. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
120214. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
120215. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
120216. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
120217. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
120218. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
120219. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
120220. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
120221. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
120222. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
120223. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
120224. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
120225. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
120226. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
120227. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
120228. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
120229. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
120230. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
120231. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
120232. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
120233. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
120234. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
120235. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
120236. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
120237. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
120238. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
120239. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
120240. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
120241. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
120242. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
120243. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
120244. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
120245. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
120246. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
120247. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
120248. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
120249. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
120250. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
120251. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
120252. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
120253. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
120254. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
120255. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
120256. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
120257. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
120258. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
120259. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
120260. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
120261. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
120262. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
120263. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
120264. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
120265. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
120266. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
120267. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
120268. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
120269. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
120270. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
120271. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
120272. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
120273. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
120274. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
120275. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
120276. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
120277. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
120278. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
120279. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
120280. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
120281. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
120282. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
120283. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
120284. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
120285. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
120286. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
120287. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
120288. BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
120289. BIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE__PROG_INTERFACE_MASK
120290. BIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
120291. BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID__MAJOR_REV_ID_MASK
120292. BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID__MAJOR_REV_ID__SHIFT
120293. BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID__MINOR_REV_ID_MASK
120294. BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID__MINOR_REV_ID__SHIFT
120295. BIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR__BASE_ADDR_MASK
120296. BIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
120297. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__CAP_LIST_MASK
120298. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__CAP_LIST__SHIFT
120299. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__DEVSEL_TIMING_MASK
120300. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__DEVSEL_TIMING__SHIFT
120301. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__FAST_BACK_CAPABLE_MASK
120302. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__FAST_BACK_CAPABLE__SHIFT
120303. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__IMMEDIATE_READINESS_MASK
120304. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__IMMEDIATE_READINESS__SHIFT
120305. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__INT_STATUS_MASK
120306. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__INT_STATUS__SHIFT
120307. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
120308. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
120309. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__PARITY_ERROR_DETECTED_MASK
120310. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
120311. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__PCI_66_CAP_MASK
120312. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__PCI_66_CAP__SHIFT
120313. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__RECEIVED_MASTER_ABORT_MASK
120314. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
120315. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__RECEIVED_TARGET_ABORT_MASK
120316. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
120317. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
120318. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
120319. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__SIGNAL_TARGET_ABORT_MASK
120320. BIF_CFG_DEV0_EPF0_VF30_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
120321. BIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS__SUB_CLASS_MASK
120322. BIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS__SUB_CLASS__SHIFT
120323. BIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID__VENDOR_ID_MASK
120324. BIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID__VENDOR_ID__SHIFT
120325. BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID__SUBSYSTEM_ID_MASK
120326. BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
120327. BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
120328. BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
120329. BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_1__BASE_ADDR_MASK
120330. BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_1__BASE_ADDR__SHIFT
120331. BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_2__BASE_ADDR_MASK
120332. BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_2__BASE_ADDR__SHIFT
120333. BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_3__BASE_ADDR_MASK
120334. BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_3__BASE_ADDR__SHIFT
120335. BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_4__BASE_ADDR_MASK
120336. BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_4__BASE_ADDR__SHIFT
120337. BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_5__BASE_ADDR_MASK
120338. BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_5__BASE_ADDR__SHIFT
120339. BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_6__BASE_ADDR_MASK
120340. BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_6__BASE_ADDR__SHIFT
120341. BIF_CFG_DEV0_EPF0_VF30_BASE_CLASS__BASE_CLASS_MASK
120342. BIF_CFG_DEV0_EPF0_VF30_BASE_CLASS__BASE_CLASS__SHIFT
120343. BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_CAP_MASK
120344. BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_CAP__SHIFT
120345. BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_COMP_MASK
120346. BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_COMP__SHIFT
120347. BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_STRT_MASK
120348. BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_STRT__SHIFT
120349. BIF_CFG_DEV0_EPF0_VF30_CACHE_LINE__CACHE_LINE_SIZE_MASK
120350. BIF_CFG_DEV0_EPF0_VF30_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
120351. BIF_CFG_DEV0_EPF0_VF30_CAP_PTR__CAP_PTR_MASK
120352. BIF_CFG_DEV0_EPF0_VF30_CAP_PTR__CAP_PTR__SHIFT
120353. BIF_CFG_DEV0_EPF0_VF30_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
120354. BIF_CFG_DEV0_EPF0_VF30_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
120355. BIF_CFG_DEV0_EPF0_VF30_COMMAND__AD_STEPPING_MASK
120356. BIF_CFG_DEV0_EPF0_VF30_COMMAND__AD_STEPPING__SHIFT
120357. BIF_CFG_DEV0_EPF0_VF30_COMMAND__BUS_MASTER_EN_MASK
120358. BIF_CFG_DEV0_EPF0_VF30_COMMAND__BUS_MASTER_EN__SHIFT
120359. BIF_CFG_DEV0_EPF0_VF30_COMMAND__FAST_B2B_EN_MASK
120360. BIF_CFG_DEV0_EPF0_VF30_COMMAND__FAST_B2B_EN__SHIFT
120361. BIF_CFG_DEV0_EPF0_VF30_COMMAND__INT_DIS_MASK
120362. BIF_CFG_DEV0_EPF0_VF30_COMMAND__INT_DIS__SHIFT
120363. BIF_CFG_DEV0_EPF0_VF30_COMMAND__IO_ACCESS_EN_MASK
120364. BIF_CFG_DEV0_EPF0_VF30_COMMAND__IO_ACCESS_EN__SHIFT
120365. BIF_CFG_DEV0_EPF0_VF30_COMMAND__MEM_ACCESS_EN_MASK
120366. BIF_CFG_DEV0_EPF0_VF30_COMMAND__MEM_ACCESS_EN__SHIFT
120367. BIF_CFG_DEV0_EPF0_VF30_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
120368. BIF_CFG_DEV0_EPF0_VF30_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
120369. BIF_CFG_DEV0_EPF0_VF30_COMMAND__PAL_SNOOP_EN_MASK
120370. BIF_CFG_DEV0_EPF0_VF30_COMMAND__PAL_SNOOP_EN__SHIFT
120371. BIF_CFG_DEV0_EPF0_VF30_COMMAND__PARITY_ERROR_RESPONSE_MASK
120372. BIF_CFG_DEV0_EPF0_VF30_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
120373. BIF_CFG_DEV0_EPF0_VF30_COMMAND__SERR_EN_MASK
120374. BIF_CFG_DEV0_EPF0_VF30_COMMAND__SERR_EN__SHIFT
120375. BIF_CFG_DEV0_EPF0_VF30_COMMAND__SPECIAL_CYCLE_EN_MASK
120376. BIF_CFG_DEV0_EPF0_VF30_COMMAND__SPECIAL_CYCLE_EN__SHIFT
120377. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
120378. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
120379. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
120380. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
120381. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
120382. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
120383. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
120384. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
120385. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
120386. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
120387. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
120388. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
120389. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
120390. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
120391. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
120392. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
120393. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
120394. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
120395. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
120396. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
120397. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
120398. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
120399. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__FRS_SUPPORTED_MASK
120400. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
120401. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
120402. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
120403. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__LTR_SUPPORTED_MASK
120404. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
120405. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
120406. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
120407. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
120408. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
120409. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__OBFF_SUPPORTED_MASK
120410. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
120411. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
120412. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
120413. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
120414. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
120415. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
120416. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
120417. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
120418. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
120419. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
120420. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
120421. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__EXTENDED_TAG_MASK
120422. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__EXTENDED_TAG__SHIFT
120423. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__FLR_CAPABLE_MASK
120424. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__FLR_CAPABLE__SHIFT
120425. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
120426. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
120427. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
120428. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
120429. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
120430. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
120431. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__PHANTOM_FUNC_MASK
120432. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__PHANTOM_FUNC__SHIFT
120433. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
120434. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
120435. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
120436. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
120437. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
120438. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
120439. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
120440. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
120441. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
120442. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
120443. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
120444. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
120445. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
120446. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
120447. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
120448. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
120449. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
120450. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
120451. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
120452. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
120453. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__LTR_EN_MASK
120454. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__LTR_EN__SHIFT
120455. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__OBFF_EN_MASK
120456. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__OBFF_EN__SHIFT
120457. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
120458. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
120459. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
120460. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
120461. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__CORR_ERR_EN_MASK
120462. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__CORR_ERR_EN__SHIFT
120463. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
120464. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
120465. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__FATAL_ERR_EN_MASK
120466. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
120467. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__INITIATE_FLR_MASK
120468. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__INITIATE_FLR__SHIFT
120469. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
120470. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
120471. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
120472. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
120473. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
120474. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
120475. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__NO_SNOOP_EN_MASK
120476. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
120477. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
120478. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
120479. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__RELAXED_ORD_EN_MASK
120480. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
120481. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__USR_REPORT_EN_MASK
120482. BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__USR_REPORT_EN__SHIFT
120483. BIF_CFG_DEV0_EPF0_VF30_DEVICE_ID__DEVICE_ID_MASK
120484. BIF_CFG_DEV0_EPF0_VF30_DEVICE_ID__DEVICE_ID__SHIFT
120485. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS2__RESERVED_MASK
120486. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS2__RESERVED__SHIFT
120487. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__AUX_PWR_MASK
120488. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__AUX_PWR__SHIFT
120489. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__CORR_ERR_MASK
120490. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__CORR_ERR__SHIFT
120491. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
120492. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
120493. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__FATAL_ERR_MASK
120494. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__FATAL_ERR__SHIFT
120495. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__NON_FATAL_ERR_MASK
120496. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
120497. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
120498. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
120499. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__USR_DETECTED_MASK
120500. BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__USR_DETECTED__SHIFT
120501. BIF_CFG_DEV0_EPF0_VF30_HEADER__DEVICE_TYPE_MASK
120502. BIF_CFG_DEV0_EPF0_VF30_HEADER__DEVICE_TYPE__SHIFT
120503. BIF_CFG_DEV0_EPF0_VF30_HEADER__HEADER_TYPE_MASK
120504. BIF_CFG_DEV0_EPF0_VF30_HEADER__HEADER_TYPE__SHIFT
120505. BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_LINE__INTERRUPT_LINE_MASK
120506. BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
120507. BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_PIN__INTERRUPT_PIN_MASK
120508. BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
120509. BIF_CFG_DEV0_EPF0_VF30_LATENCY__LATENCY_TIMER_MASK
120510. BIF_CFG_DEV0_EPF0_VF30_LATENCY__LATENCY_TIMER__SHIFT
120511. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
120512. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
120513. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
120514. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
120515. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
120516. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
120517. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
120518. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
120519. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
120520. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
120521. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
120522. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
120523. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
120524. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
120525. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
120526. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
120527. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
120528. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
120529. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
120530. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
120531. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__L0S_EXIT_LATENCY_MASK
120532. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
120533. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__L1_EXIT_LATENCY_MASK
120534. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__L1_EXIT_LATENCY__SHIFT
120535. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
120536. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
120537. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_SPEED_MASK
120538. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_SPEED__SHIFT
120539. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_WIDTH_MASK
120540. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_WIDTH__SHIFT
120541. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__PM_SUPPORT_MASK
120542. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__PM_SUPPORT__SHIFT
120543. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__PORT_NUMBER_MASK
120544. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__PORT_NUMBER__SHIFT
120545. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
120546. BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
120547. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
120548. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
120549. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__COMPLIANCE_SOS_MASK
120550. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
120551. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__ENTER_COMPLIANCE_MASK
120552. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
120553. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
120554. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
120555. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
120556. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
120557. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
120558. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
120559. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__TARGET_LINK_SPEED_MASK
120560. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
120561. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__XMIT_MARGIN_MASK
120562. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__XMIT_MARGIN__SHIFT
120563. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
120564. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
120565. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__COMMON_CLOCK_CFG_MASK
120566. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
120567. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
120568. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
120569. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__EXTENDED_SYNC_MASK
120570. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__EXTENDED_SYNC__SHIFT
120571. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
120572. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
120573. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
120574. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
120575. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
120576. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
120577. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_DIS_MASK
120578. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_DIS__SHIFT
120579. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__PM_CONTROL_MASK
120580. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__PM_CONTROL__SHIFT
120581. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__READ_CPL_BOUNDARY_MASK
120582. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
120583. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__RETRAIN_LINK_MASK
120584. BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__RETRAIN_LINK__SHIFT
120585. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
120586. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
120587. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
120588. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
120589. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
120590. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
120591. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
120592. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
120593. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
120594. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
120595. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
120596. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
120597. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
120598. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
120599. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
120600. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
120601. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
120602. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
120603. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
120604. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
120605. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
120606. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
120607. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__CURRENT_LINK_SPEED_MASK
120608. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
120609. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__DL_ACTIVE_MASK
120610. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__DL_ACTIVE__SHIFT
120611. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
120612. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
120613. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
120614. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
120615. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_TRAINING_MASK
120616. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_TRAINING__SHIFT
120617. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
120618. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
120619. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__SLOT_CLOCK_CFG_MASK
120620. BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
120621. BIF_CFG_DEV0_EPF0_VF30_MAX_LATENCY__MAX_LAT_MASK
120622. BIF_CFG_DEV0_EPF0_VF30_MAX_LATENCY__MAX_LAT__SHIFT
120623. BIF_CFG_DEV0_EPF0_VF30_MIN_GRANT__MIN_GNT_MASK
120624. BIF_CFG_DEV0_EPF0_VF30_MIN_GRANT__MIN_GNT__SHIFT
120625. BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST__CAP_ID_MASK
120626. BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST__CAP_ID__SHIFT
120627. BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST__NEXT_PTR_MASK
120628. BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST__NEXT_PTR__SHIFT
120629. BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_EN_MASK
120630. BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_EN__SHIFT
120631. BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
120632. BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
120633. BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
120634. BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
120635. BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA__MSIX_PBA_BIR_MASK
120636. BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA__MSIX_PBA_BIR__SHIFT
120637. BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA__MSIX_PBA_OFFSET_MASK
120638. BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
120639. BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE__MSIX_TABLE_BIR_MASK
120640. BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
120641. BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
120642. BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
120643. BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST__CAP_ID_MASK
120644. BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST__CAP_ID__SHIFT
120645. BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST__NEXT_PTR_MASK
120646. BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST__NEXT_PTR__SHIFT
120647. BIF_CFG_DEV0_EPF0_VF30_MSI_MASK_64__MSI_MASK_64_MASK
120648. BIF_CFG_DEV0_EPF0_VF30_MSI_MASK_64__MSI_MASK_64__SHIFT
120649. BIF_CFG_DEV0_EPF0_VF30_MSI_MASK__MSI_MASK_MASK
120650. BIF_CFG_DEV0_EPF0_VF30_MSI_MASK__MSI_MASK__SHIFT
120651. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
120652. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
120653. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
120654. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
120655. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_64BIT_MASK
120656. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_64BIT__SHIFT
120657. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_EN_MASK
120658. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_EN__SHIFT
120659. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
120660. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
120661. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
120662. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
120663. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
120664. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
120665. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA_64__MSI_DATA_64_MASK
120666. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
120667. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA__MSI_DATA_MASK
120668. BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA__MSI_DATA__SHIFT
120669. BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING_64__MSI_PENDING_64_MASK
120670. BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING_64__MSI_PENDING_64__SHIFT
120671. BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING__MSI_PENDING_MASK
120672. BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING__MSI_PENDING__SHIFT
120673. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
120674. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
120675. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
120676. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
120677. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
120678. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
120679. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
120680. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
120681. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
120682. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
120683. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
120684. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
120685. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
120686. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
120687. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
120688. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
120689. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
120690. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
120691. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
120692. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
120693. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
120694. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
120695. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
120696. BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
120697. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
120698. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
120699. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
120700. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
120701. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
120702. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
120703. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
120704. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
120705. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
120706. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
120707. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
120708. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
120709. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
120710. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
120711. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
120712. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
120713. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
120714. BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
120715. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
120716. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
120717. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
120718. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
120719. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
120720. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
120721. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL__ATC_ENABLE_MASK
120722. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
120723. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL__STU_MASK
120724. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL__STU__SHIFT
120725. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
120726. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
120727. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
120728. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
120729. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
120730. BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
120731. BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST__CAP_ID_MASK
120732. BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST__CAP_ID__SHIFT
120733. BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST__NEXT_PTR_MASK
120734. BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST__NEXT_PTR__SHIFT
120735. BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__DEVICE_TYPE_MASK
120736. BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__DEVICE_TYPE__SHIFT
120737. BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__INT_MESSAGE_NUM_MASK
120738. BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
120739. BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__SLOT_IMPLEMENTED_MASK
120740. BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
120741. BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__VERSION_MASK
120742. BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__VERSION__SHIFT
120743. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
120744. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
120745. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
120746. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
120747. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
120748. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
120749. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
120750. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
120751. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
120752. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
120753. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
120754. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
120755. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
120756. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
120757. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
120758. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
120759. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
120760. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
120761. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
120762. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
120763. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
120764. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
120765. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
120766. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
120767. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
120768. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
120769. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
120770. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
120771. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
120772. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
120773. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
120774. BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
120775. BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG0__TLP_HDR_MASK
120776. BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG0__TLP_HDR__SHIFT
120777. BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG1__TLP_HDR_MASK
120778. BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG1__TLP_HDR__SHIFT
120779. BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG2__TLP_HDR_MASK
120780. BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG2__TLP_HDR__SHIFT
120781. BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG3__TLP_HDR_MASK
120782. BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG3__TLP_HDR__SHIFT
120783. BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
120784. BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
120785. BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
120786. BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
120787. BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
120788. BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
120789. BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
120790. BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
120791. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
120792. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
120793. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
120794. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
120795. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
120796. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
120797. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
120798. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
120799. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
120800. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
120801. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
120802. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
120803. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
120804. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
120805. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
120806. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
120807. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
120808. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
120809. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
120810. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
120811. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
120812. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
120813. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
120814. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
120815. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
120816. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
120817. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
120818. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
120819. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
120820. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
120821. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
120822. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
120823. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
120824. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
120825. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
120826. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
120827. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
120828. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
120829. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
120830. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
120831. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
120832. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
120833. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
120834. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
120835. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
120836. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
120837. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
120838. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
120839. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
120840. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
120841. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
120842. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
120843. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
120844. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
120845. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
120846. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
120847. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
120848. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
120849. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
120850. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
120851. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
120852. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
120853. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
120854. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
120855. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
120856. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
120857. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
120858. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
120859. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
120860. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
120861. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
120862. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
120863. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
120864. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
120865. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
120866. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
120867. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
120868. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
120869. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
120870. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
120871. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
120872. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
120873. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
120874. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
120875. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
120876. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
120877. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
120878. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
120879. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
120880. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
120881. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
120882. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
120883. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
120884. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
120885. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
120886. BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
120887. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
120888. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
120889. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
120890. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
120891. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
120892. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
120893. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
120894. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
120895. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
120896. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
120897. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
120898. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
120899. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
120900. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
120901. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
120902. BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
120903. BIF_CFG_DEV0_EPF0_VF30_PROG_INTERFACE__PROG_INTERFACE_MASK
120904. BIF_CFG_DEV0_EPF0_VF30_PROG_INTERFACE__PROG_INTERFACE__SHIFT
120905. BIF_CFG_DEV0_EPF0_VF30_REVISION_ID__MAJOR_REV_ID_MASK
120906. BIF_CFG_DEV0_EPF0_VF30_REVISION_ID__MAJOR_REV_ID__SHIFT
120907. BIF_CFG_DEV0_EPF0_VF30_REVISION_ID__MINOR_REV_ID_MASK
120908. BIF_CFG_DEV0_EPF0_VF30_REVISION_ID__MINOR_REV_ID__SHIFT
120909. BIF_CFG_DEV0_EPF0_VF30_ROM_BASE_ADDR__BASE_ADDR_MASK
120910. BIF_CFG_DEV0_EPF0_VF30_ROM_BASE_ADDR__BASE_ADDR__SHIFT
120911. BIF_CFG_DEV0_EPF0_VF30_STATUS__CAP_LIST_MASK
120912. BIF_CFG_DEV0_EPF0_VF30_STATUS__CAP_LIST__SHIFT
120913. BIF_CFG_DEV0_EPF0_VF30_STATUS__DEVSEL_TIMING_MASK
120914. BIF_CFG_DEV0_EPF0_VF30_STATUS__DEVSEL_TIMING__SHIFT
120915. BIF_CFG_DEV0_EPF0_VF30_STATUS__FAST_BACK_CAPABLE_MASK
120916. BIF_CFG_DEV0_EPF0_VF30_STATUS__FAST_BACK_CAPABLE__SHIFT
120917. BIF_CFG_DEV0_EPF0_VF30_STATUS__IMMEDIATE_READINESS_MASK
120918. BIF_CFG_DEV0_EPF0_VF30_STATUS__IMMEDIATE_READINESS__SHIFT
120919. BIF_CFG_DEV0_EPF0_VF30_STATUS__INT_STATUS_MASK
120920. BIF_CFG_DEV0_EPF0_VF30_STATUS__INT_STATUS__SHIFT
120921. BIF_CFG_DEV0_EPF0_VF30_STATUS__MASTER_DATA_PARITY_ERROR_MASK
120922. BIF_CFG_DEV0_EPF0_VF30_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
120923. BIF_CFG_DEV0_EPF0_VF30_STATUS__PARITY_ERROR_DETECTED_MASK
120924. BIF_CFG_DEV0_EPF0_VF30_STATUS__PARITY_ERROR_DETECTED__SHIFT
120925. BIF_CFG_DEV0_EPF0_VF30_STATUS__PCI_66_CAP_MASK
120926. BIF_CFG_DEV0_EPF0_VF30_STATUS__PCI_66_CAP__SHIFT
120927. BIF_CFG_DEV0_EPF0_VF30_STATUS__RECEIVED_MASTER_ABORT_MASK
120928. BIF_CFG_DEV0_EPF0_VF30_STATUS__RECEIVED_MASTER_ABORT__SHIFT
120929. BIF_CFG_DEV0_EPF0_VF30_STATUS__RECEIVED_TARGET_ABORT_MASK
120930. BIF_CFG_DEV0_EPF0_VF30_STATUS__RECEIVED_TARGET_ABORT__SHIFT
120931. BIF_CFG_DEV0_EPF0_VF30_STATUS__SIGNALED_SYSTEM_ERROR_MASK
120932. BIF_CFG_DEV0_EPF0_VF30_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
120933. BIF_CFG_DEV0_EPF0_VF30_STATUS__SIGNAL_TARGET_ABORT_MASK
120934. BIF_CFG_DEV0_EPF0_VF30_STATUS__SIGNAL_TARGET_ABORT__SHIFT
120935. BIF_CFG_DEV0_EPF0_VF30_SUB_CLASS__SUB_CLASS_MASK
120936. BIF_CFG_DEV0_EPF0_VF30_SUB_CLASS__SUB_CLASS__SHIFT
120937. BIF_CFG_DEV0_EPF0_VF30_VENDOR_ID__VENDOR_ID_MASK
120938. BIF_CFG_DEV0_EPF0_VF30_VENDOR_ID__VENDOR_ID__SHIFT
120939. BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
120940. BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
120941. BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
120942. BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
120943. BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR_MASK
120944. BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT
120945. BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR_MASK
120946. BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT
120947. BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR_MASK
120948. BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT
120949. BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR_MASK
120950. BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT
120951. BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR_MASK
120952. BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT
120953. BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR_MASK
120954. BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT
120955. BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS_MASK
120956. BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS__SHIFT
120957. BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP_MASK
120958. BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP__SHIFT
120959. BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP_MASK
120960. BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP__SHIFT
120961. BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT_MASK
120962. BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT__SHIFT
120963. BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
120964. BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
120965. BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR_MASK
120966. BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR__SHIFT
120967. BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
120968. BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
120969. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING_MASK
120970. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING__SHIFT
120971. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN_MASK
120972. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN__SHIFT
120973. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN_MASK
120974. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN__SHIFT
120975. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS_MASK
120976. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS__SHIFT
120977. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN_MASK
120978. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN__SHIFT
120979. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN_MASK
120980. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN__SHIFT
120981. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
120982. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
120983. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN_MASK
120984. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN__SHIFT
120985. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
120986. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
120987. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN_MASK
120988. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN__SHIFT
120989. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK
120990. BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
120991. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
120992. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
120993. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
120994. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
120995. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
120996. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
120997. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
120998. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
120999. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
121000. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
121001. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
121002. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
121003. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
121004. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
121005. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
121006. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
121007. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
121008. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
121009. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
121010. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
121011. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
121012. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
121013. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
121014. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
121015. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
121016. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
121017. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
121018. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
121019. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
121020. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
121021. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
121022. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
121023. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
121024. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
121025. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
121026. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
121027. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
121028. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
121029. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
121030. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
121031. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
121032. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
121033. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
121034. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
121035. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG_MASK
121036. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
121037. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE_MASK
121038. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
121039. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
121040. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
121041. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
121042. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
121043. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
121044. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
121045. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK
121046. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
121047. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
121048. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
121049. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
121050. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
121051. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
121052. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
121053. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
121054. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
121055. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
121056. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
121057. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
121058. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
121059. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
121060. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
121061. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
121062. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
121063. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
121064. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
121065. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
121066. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
121067. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN_MASK
121068. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN__SHIFT
121069. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN_MASK
121070. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT
121071. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
121072. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
121073. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
121074. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
121075. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK
121076. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
121077. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
121078. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
121079. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
121080. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
121081. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR_MASK
121082. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
121083. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
121084. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
121085. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
121086. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
121087. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
121088. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
121089. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
121090. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
121091. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
121092. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
121093. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
121094. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
121095. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK
121096. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
121097. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID_MASK
121098. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID__SHIFT
121099. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED_MASK
121100. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED__SHIFT
121101. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR_MASK
121102. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR__SHIFT
121103. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR_MASK
121104. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR__SHIFT
121105. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
121106. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
121107. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR_MASK
121108. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT
121109. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
121110. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
121111. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
121112. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
121113. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED_MASK
121114. BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT
121115. BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE_MASK
121116. BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE__SHIFT
121117. BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE_MASK
121118. BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE__SHIFT
121119. BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
121120. BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
121121. BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
121122. BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
121123. BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER_MASK
121124. BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER__SHIFT
121125. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
121126. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
121127. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
121128. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
121129. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
121130. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
121131. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
121132. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
121133. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RESERVED_MASK
121134. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RESERVED__SHIFT
121135. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
121136. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
121137. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
121138. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
121139. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
121140. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
121141. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
121142. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
121143. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
121144. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
121145. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
121146. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
121147. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
121148. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
121149. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK
121150. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
121151. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
121152. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
121153. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED_MASK
121154. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED__SHIFT
121155. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH_MASK
121156. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH__SHIFT
121157. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT_MASK
121158. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT__SHIFT
121159. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER_MASK
121160. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER__SHIFT
121161. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
121162. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
121163. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
121164. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
121165. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
121166. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
121167. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
121168. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
121169. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
121170. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
121171. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
121172. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
121173. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
121174. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
121175. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
121176. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
121177. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN_MASK
121178. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
121179. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
121180. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
121181. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
121182. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
121183. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
121184. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
121185. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC_MASK
121186. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
121187. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
121188. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
121189. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
121190. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
121191. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
121192. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
121193. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS_MASK
121194. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS__SHIFT
121195. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL_MASK
121196. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL__SHIFT
121197. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
121198. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
121199. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK_MASK
121200. BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT
121201. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
121202. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
121203. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
121204. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
121205. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
121206. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
121207. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
121208. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
121209. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
121210. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
121211. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
121212. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
121213. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
121214. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
121215. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
121216. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
121217. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
121218. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
121219. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
121220. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
121221. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
121222. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
121223. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
121224. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
121225. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
121226. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
121227. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
121228. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
121229. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
121230. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
121231. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
121232. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
121233. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
121234. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
121235. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE_MASK
121236. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE__SHIFT
121237. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
121238. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
121239. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
121240. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
121241. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING_MASK
121242. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING__SHIFT
121243. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
121244. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
121245. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
121246. BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
121247. BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY__MAX_LAT_MASK
121248. BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY__MAX_LAT__SHIFT
121249. BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT__MIN_GNT_MASK
121250. BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT__MIN_GNT__SHIFT
121251. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID_MASK
121252. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT
121253. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK
121254. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
121255. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK
121256. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
121257. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
121258. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
121259. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
121260. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
121261. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK
121262. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
121263. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
121264. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
121265. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
121266. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
121267. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
121268. BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
121269. BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID_MASK
121270. BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID__SHIFT
121271. BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR_MASK
121272. BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
121273. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64_MASK
121274. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT
121275. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK_MASK
121276. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK__SHIFT
121277. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
121278. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
121279. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
121280. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
121281. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK
121282. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
121283. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN_MASK
121284. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT
121285. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
121286. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
121287. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
121288. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
121289. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
121290. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
121291. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
121292. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
121293. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA_MASK
121294. BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT
121295. BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK
121296. BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
121297. BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING_MASK
121298. BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING__SHIFT
121299. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
121300. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
121301. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
121302. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
121303. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
121304. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
121305. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
121306. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
121307. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
121308. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
121309. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
121310. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
121311. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
121312. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
121313. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
121314. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
121315. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
121316. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
121317. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
121318. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
121319. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
121320. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
121321. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
121322. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
121323. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
121324. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
121325. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
121326. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
121327. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
121328. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
121329. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
121330. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
121331. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
121332. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
121333. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
121334. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
121335. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
121336. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
121337. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
121338. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
121339. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
121340. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
121341. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
121342. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
121343. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
121344. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
121345. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
121346. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
121347. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
121348. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
121349. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__STU_MASK
121350. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__STU__SHIFT
121351. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
121352. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
121353. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
121354. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
121355. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
121356. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
121357. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID_MASK
121358. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT
121359. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK
121360. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
121361. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE_MASK
121362. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT
121363. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
121364. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
121365. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
121366. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
121367. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION_MASK
121368. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION__SHIFT
121369. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
121370. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
121371. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
121372. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
121373. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
121374. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
121375. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
121376. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
121377. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
121378. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
121379. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
121380. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
121381. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
121382. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
121383. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
121384. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
121385. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
121386. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
121387. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
121388. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
121389. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
121390. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
121391. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
121392. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
121393. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
121394. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
121395. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
121396. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
121397. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
121398. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
121399. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
121400. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
121401. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK
121402. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
121403. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK
121404. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
121405. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK
121406. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
121407. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK
121408. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
121409. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
121410. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
121411. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
121412. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
121413. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
121414. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
121415. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
121416. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
121417. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
121418. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
121419. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
121420. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
121421. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
121422. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
121423. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
121424. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
121425. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
121426. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
121427. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
121428. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
121429. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
121430. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
121431. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
121432. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
121433. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
121434. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
121435. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
121436. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
121437. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
121438. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
121439. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
121440. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
121441. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
121442. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
121443. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
121444. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
121445. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
121446. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
121447. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
121448. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
121449. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
121450. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
121451. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
121452. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
121453. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
121454. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
121455. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
121456. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
121457. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
121458. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
121459. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
121460. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
121461. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
121462. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
121463. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
121464. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
121465. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
121466. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
121467. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
121468. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
121469. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
121470. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
121471. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
121472. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
121473. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
121474. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
121475. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
121476. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
121477. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
121478. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
121479. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
121480. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
121481. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
121482. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
121483. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
121484. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
121485. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
121486. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
121487. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
121488. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
121489. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
121490. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
121491. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
121492. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
121493. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
121494. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
121495. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
121496. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
121497. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
121498. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
121499. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
121500. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
121501. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
121502. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
121503. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
121504. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
121505. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
121506. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
121507. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
121508. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
121509. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
121510. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
121511. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
121512. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
121513. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
121514. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
121515. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
121516. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
121517. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
121518. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
121519. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
121520. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
121521. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
121522. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
121523. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
121524. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
121525. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
121526. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
121527. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
121528. BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
121529. BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK
121530. BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
121531. BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID_MASK
121532. BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT
121533. BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID_MASK
121534. BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID__SHIFT
121535. BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK
121536. BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
121537. BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2__RESERVED_MASK
121538. BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2__RESERVED__SHIFT
121539. BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2__RESERVED_MASK
121540. BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2__RESERVED__SHIFT
121541. BIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2__RESERVED_MASK
121542. BIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2__RESERVED__SHIFT
121543. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST_MASK
121544. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST__SHIFT
121545. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING_MASK
121546. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING__SHIFT
121547. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE_MASK
121548. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT
121549. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__IMMEDIATE_READINESS_MASK
121550. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__IMMEDIATE_READINESS__SHIFT
121551. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS_MASK
121552. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS__SHIFT
121553. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
121554. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
121555. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED_MASK
121556. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
121557. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_CAP_MASK
121558. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_CAP__SHIFT
121559. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_EN_MASK
121560. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_EN__SHIFT
121561. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK
121562. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
121563. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK
121564. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
121565. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
121566. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
121567. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK
121568. BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
121569. BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS_MASK
121570. BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS__SHIFT
121571. BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID_MASK
121572. BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID__SHIFT
121573. BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
121574. BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
121575. BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
121576. BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
121577. BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR_MASK
121578. BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT
121579. BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR_MASK
121580. BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT
121581. BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR_MASK
121582. BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT
121583. BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR_MASK
121584. BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT
121585. BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR_MASK
121586. BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT
121587. BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR_MASK
121588. BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT
121589. BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS_MASK
121590. BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS__SHIFT
121591. BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP_MASK
121592. BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP__SHIFT
121593. BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP_MASK
121594. BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP__SHIFT
121595. BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT_MASK
121596. BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT__SHIFT
121597. BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
121598. BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
121599. BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR_MASK
121600. BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR__SHIFT
121601. BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
121602. BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
121603. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING_MASK
121604. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING__SHIFT
121605. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN_MASK
121606. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN__SHIFT
121607. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN_MASK
121608. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN__SHIFT
121609. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS_MASK
121610. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS__SHIFT
121611. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN_MASK
121612. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN__SHIFT
121613. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN_MASK
121614. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN__SHIFT
121615. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
121616. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
121617. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN_MASK
121618. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN__SHIFT
121619. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
121620. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
121621. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN_MASK
121622. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN__SHIFT
121623. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK
121624. BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
121625. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
121626. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
121627. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
121628. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
121629. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
121630. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
121631. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
121632. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
121633. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
121634. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
121635. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
121636. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
121637. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
121638. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
121639. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
121640. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
121641. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
121642. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
121643. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
121644. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
121645. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
121646. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
121647. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
121648. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
121649. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
121650. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
121651. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
121652. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
121653. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
121654. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
121655. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
121656. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
121657. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
121658. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
121659. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
121660. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
121661. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
121662. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
121663. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
121664. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
121665. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
121666. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
121667. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
121668. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
121669. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG_MASK
121670. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
121671. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE_MASK
121672. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
121673. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
121674. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
121675. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
121676. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
121677. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
121678. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
121679. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK
121680. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
121681. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
121682. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
121683. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
121684. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
121685. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
121686. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
121687. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
121688. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
121689. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
121690. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
121691. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
121692. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
121693. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
121694. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
121695. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
121696. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
121697. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
121698. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
121699. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
121700. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
121701. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN_MASK
121702. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN__SHIFT
121703. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN_MASK
121704. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT
121705. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
121706. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
121707. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
121708. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
121709. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK
121710. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
121711. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
121712. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
121713. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
121714. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
121715. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR_MASK
121716. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
121717. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
121718. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
121719. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
121720. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
121721. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
121722. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
121723. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
121724. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
121725. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
121726. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
121727. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
121728. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
121729. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK
121730. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
121731. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID_MASK
121732. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID__SHIFT
121733. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED_MASK
121734. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED__SHIFT
121735. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR_MASK
121736. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR__SHIFT
121737. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR_MASK
121738. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR__SHIFT
121739. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
121740. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
121741. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR_MASK
121742. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT
121743. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
121744. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
121745. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
121746. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
121747. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED_MASK
121748. BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT
121749. BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE_MASK
121750. BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE__SHIFT
121751. BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE_MASK
121752. BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE__SHIFT
121753. BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
121754. BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
121755. BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
121756. BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
121757. BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER_MASK
121758. BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER__SHIFT
121759. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
121760. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
121761. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
121762. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
121763. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
121764. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
121765. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
121766. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
121767. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RESERVED_MASK
121768. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RESERVED__SHIFT
121769. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
121770. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
121771. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
121772. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
121773. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
121774. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
121775. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
121776. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
121777. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
121778. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
121779. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
121780. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
121781. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
121782. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
121783. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK
121784. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
121785. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
121786. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
121787. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED_MASK
121788. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED__SHIFT
121789. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH_MASK
121790. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH__SHIFT
121791. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT_MASK
121792. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT__SHIFT
121793. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER_MASK
121794. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER__SHIFT
121795. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
121796. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
121797. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
121798. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
121799. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
121800. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
121801. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
121802. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
121803. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
121804. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
121805. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
121806. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
121807. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
121808. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
121809. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
121810. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
121811. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN_MASK
121812. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
121813. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
121814. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
121815. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
121816. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
121817. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
121818. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
121819. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC_MASK
121820. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
121821. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
121822. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
121823. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
121824. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
121825. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
121826. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
121827. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS_MASK
121828. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS__SHIFT
121829. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL_MASK
121830. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL__SHIFT
121831. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
121832. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
121833. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK_MASK
121834. BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT
121835. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
121836. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
121837. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
121838. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
121839. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
121840. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
121841. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
121842. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
121843. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
121844. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
121845. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
121846. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
121847. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
121848. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
121849. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
121850. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
121851. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
121852. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
121853. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
121854. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
121855. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
121856. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
121857. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
121858. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
121859. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
121860. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
121861. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
121862. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
121863. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
121864. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
121865. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
121866. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
121867. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
121868. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
121869. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE_MASK
121870. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE__SHIFT
121871. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
121872. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
121873. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
121874. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
121875. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING_MASK
121876. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING__SHIFT
121877. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
121878. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
121879. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
121880. BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
121881. BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY__MAX_LAT_MASK
121882. BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY__MAX_LAT__SHIFT
121883. BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT__MIN_GNT_MASK
121884. BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT__MIN_GNT__SHIFT
121885. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID_MASK
121886. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT
121887. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK
121888. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
121889. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK
121890. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
121891. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
121892. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
121893. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
121894. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
121895. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK
121896. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
121897. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
121898. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
121899. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
121900. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
121901. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
121902. BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
121903. BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID_MASK
121904. BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID__SHIFT
121905. BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR_MASK
121906. BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
121907. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64_MASK
121908. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT
121909. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK_MASK
121910. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK__SHIFT
121911. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
121912. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
121913. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
121914. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
121915. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK
121916. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
121917. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN_MASK
121918. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT
121919. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
121920. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
121921. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
121922. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
121923. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
121924. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
121925. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
121926. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
121927. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA_MASK
121928. BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT
121929. BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK
121930. BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
121931. BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING_MASK
121932. BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING__SHIFT
121933. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
121934. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
121935. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
121936. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
121937. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
121938. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
121939. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
121940. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
121941. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
121942. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
121943. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
121944. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
121945. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
121946. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
121947. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
121948. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
121949. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
121950. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
121951. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
121952. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
121953. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
121954. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
121955. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
121956. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
121957. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
121958. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
121959. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
121960. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
121961. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
121962. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
121963. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
121964. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
121965. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
121966. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
121967. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
121968. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
121969. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
121970. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
121971. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
121972. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
121973. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
121974. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
121975. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
121976. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
121977. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
121978. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
121979. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
121980. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
121981. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
121982. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
121983. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__STU_MASK
121984. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__STU__SHIFT
121985. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
121986. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
121987. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
121988. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
121989. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
121990. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
121991. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID_MASK
121992. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT
121993. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK
121994. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
121995. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE_MASK
121996. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT
121997. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
121998. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
121999. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
122000. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
122001. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION_MASK
122002. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION__SHIFT
122003. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
122004. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
122005. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
122006. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
122007. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
122008. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
122009. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
122010. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
122011. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
122012. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
122013. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
122014. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
122015. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
122016. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
122017. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
122018. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
122019. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
122020. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
122021. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
122022. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
122023. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
122024. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
122025. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
122026. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
122027. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
122028. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
122029. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
122030. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
122031. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
122032. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
122033. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
122034. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
122035. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK
122036. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
122037. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK
122038. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
122039. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK
122040. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
122041. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK
122042. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
122043. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
122044. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
122045. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
122046. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
122047. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
122048. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
122049. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
122050. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
122051. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
122052. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
122053. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
122054. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
122055. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
122056. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
122057. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
122058. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
122059. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
122060. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
122061. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
122062. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
122063. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
122064. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
122065. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
122066. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
122067. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
122068. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
122069. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
122070. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
122071. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
122072. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
122073. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
122074. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
122075. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
122076. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
122077. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
122078. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
122079. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
122080. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
122081. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
122082. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
122083. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
122084. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
122085. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
122086. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
122087. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
122088. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
122089. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
122090. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
122091. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
122092. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
122093. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
122094. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
122095. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
122096. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
122097. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
122098. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
122099. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
122100. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
122101. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
122102. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
122103. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
122104. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
122105. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
122106. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
122107. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
122108. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
122109. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
122110. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
122111. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
122112. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
122113. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
122114. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
122115. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
122116. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
122117. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
122118. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
122119. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
122120. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
122121. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
122122. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
122123. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
122124. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
122125. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
122126. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
122127. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
122128. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
122129. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
122130. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
122131. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
122132. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
122133. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
122134. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
122135. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
122136. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
122137. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
122138. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
122139. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
122140. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
122141. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
122142. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
122143. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
122144. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
122145. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
122146. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
122147. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
122148. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
122149. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
122150. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
122151. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
122152. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
122153. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
122154. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
122155. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
122156. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
122157. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
122158. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
122159. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
122160. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
122161. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
122162. BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
122163. BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK
122164. BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
122165. BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID_MASK
122166. BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT
122167. BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID_MASK
122168. BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID__SHIFT
122169. BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK
122170. BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
122171. BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CAP2__RESERVED_MASK
122172. BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CAP2__RESERVED__SHIFT
122173. BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CNTL2__RESERVED_MASK
122174. BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CNTL2__RESERVED__SHIFT
122175. BIF_CFG_DEV0_EPF0_VF3_1_SLOT_STATUS2__RESERVED_MASK
122176. BIF_CFG_DEV0_EPF0_VF3_1_SLOT_STATUS2__RESERVED__SHIFT
122177. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST_MASK
122178. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST__SHIFT
122179. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING_MASK
122180. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING__SHIFT
122181. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE_MASK
122182. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT
122183. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__IMMEDIATE_READINESS_MASK
122184. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__IMMEDIATE_READINESS__SHIFT
122185. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS_MASK
122186. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS__SHIFT
122187. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
122188. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
122189. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED_MASK
122190. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
122191. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_CAP_MASK
122192. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_CAP__SHIFT
122193. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_EN_MASK
122194. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_EN__SHIFT
122195. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK
122196. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
122197. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK
122198. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
122199. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
122200. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
122201. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK
122202. BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
122203. BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS_MASK
122204. BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS__SHIFT
122205. BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID_MASK
122206. BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID__SHIFT
122207. BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK
122208. BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
122209. BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
122210. BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
122211. BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK
122212. BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT
122213. BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK
122214. BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT
122215. BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK
122216. BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT
122217. BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK
122218. BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT
122219. BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK
122220. BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT
122221. BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK
122222. BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT
122223. BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK
122224. BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT
122225. BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK
122226. BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT
122227. BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK
122228. BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT
122229. BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK
122230. BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT
122231. BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK
122232. BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
122233. BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK
122234. BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT
122235. BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
122236. BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
122237. BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK
122238. BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT
122239. BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK
122240. BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT
122241. BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK
122242. BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT
122243. BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK
122244. BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT
122245. BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK
122246. BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT
122247. BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK
122248. BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT
122249. BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
122250. BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
122251. BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK
122252. BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT
122253. BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK
122254. BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
122255. BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK
122256. BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT
122257. BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK
122258. BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT
122259. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
122260. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
122261. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
122262. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
122263. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
122264. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
122265. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
122266. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
122267. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
122268. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
122269. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
122270. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
122271. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
122272. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
122273. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
122274. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
122275. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
122276. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
122277. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
122278. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
122279. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
122280. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
122281. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK
122282. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
122283. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
122284. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
122285. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK
122286. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
122287. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
122288. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
122289. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
122290. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
122291. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK
122292. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
122293. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
122294. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
122295. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
122296. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
122297. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
122298. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
122299. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
122300. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
122301. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
122302. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
122303. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK
122304. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT
122305. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK
122306. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT
122307. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
122308. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
122309. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
122310. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
122311. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
122312. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
122313. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK
122314. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT
122315. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
122316. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
122317. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
122318. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
122319. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
122320. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
122321. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
122322. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
122323. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
122324. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
122325. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
122326. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
122327. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
122328. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
122329. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
122330. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
122331. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
122332. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
122333. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
122334. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
122335. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK
122336. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT
122337. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK
122338. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT
122339. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
122340. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
122341. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
122342. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
122343. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK
122344. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT
122345. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
122346. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
122347. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK
122348. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
122349. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK
122350. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT
122351. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
122352. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
122353. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
122354. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
122355. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
122356. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
122357. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK
122358. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
122359. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
122360. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
122361. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK
122362. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
122363. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK
122364. BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT
122365. BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK
122366. BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT
122367. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK
122368. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT
122369. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK
122370. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT
122371. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK
122372. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT
122373. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
122374. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
122375. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK
122376. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT
122377. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK
122378. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
122379. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
122380. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
122381. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK
122382. BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT
122383. BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE_MASK
122384. BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE__SHIFT
122385. BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE_MASK
122386. BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE__SHIFT
122387. BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK
122388. BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
122389. BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK
122390. BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
122391. BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK
122392. BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT
122393. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
122394. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
122395. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
122396. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
122397. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
122398. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
122399. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
122400. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
122401. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
122402. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
122403. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
122404. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
122405. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
122406. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
122407. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
122408. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
122409. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
122410. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
122411. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
122412. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
122413. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK
122414. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
122415. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK
122416. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT
122417. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
122418. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
122419. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK
122420. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT
122421. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK
122422. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT
122423. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK
122424. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT
122425. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK
122426. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT
122427. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
122428. BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
122429. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
122430. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
122431. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK
122432. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
122433. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK
122434. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
122435. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
122436. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
122437. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
122438. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
122439. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
122440. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
122441. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK
122442. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
122443. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK
122444. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT
122445. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
122446. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
122447. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK
122448. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
122449. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
122450. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
122451. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK
122452. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT
122453. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
122454. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
122455. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
122456. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
122457. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
122458. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
122459. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK
122460. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT
122461. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK
122462. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT
122463. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK
122464. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
122465. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK
122466. BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT
122467. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
122468. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
122469. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
122470. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
122471. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
122472. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
122473. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
122474. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
122475. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
122476. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
122477. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
122478. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
122479. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
122480. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
122481. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
122482. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
122483. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
122484. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
122485. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
122486. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
122487. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
122488. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
122489. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK
122490. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
122491. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK
122492. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT
122493. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
122494. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
122495. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
122496. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
122497. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK
122498. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT
122499. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
122500. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
122501. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK
122502. BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
122503. BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK
122504. BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT
122505. BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK
122506. BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT
122507. BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK
122508. BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT
122509. BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK
122510. BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT
122511. BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK
122512. BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT
122513. BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
122514. BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
122515. BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
122516. BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
122517. BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK
122518. BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT
122519. BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK
122520. BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
122521. BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK
122522. BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
122523. BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
122524. BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
122525. BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK
122526. BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT
122527. BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK
122528. BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT
122529. BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK
122530. BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT
122531. BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK
122532. BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT
122533. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
122534. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
122535. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
122536. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
122537. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK
122538. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT
122539. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK
122540. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT
122541. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
122542. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
122543. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
122544. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
122545. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
122546. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
122547. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK
122548. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
122549. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK
122550. BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT
122551. BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK
122552. BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT
122553. BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK
122554. BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT
122555. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
122556. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
122557. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
122558. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
122559. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
122560. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
122561. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
122562. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
122563. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
122564. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
122565. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
122566. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
122567. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
122568. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
122569. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
122570. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
122571. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
122572. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
122573. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
122574. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
122575. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
122576. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
122577. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
122578. BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
122579. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
122580. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
122581. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
122582. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
122583. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
122584. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
122585. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
122586. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
122587. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
122588. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
122589. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
122590. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
122591. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
122592. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
122593. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
122594. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
122595. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
122596. BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
122597. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
122598. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
122599. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
122600. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
122601. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
122602. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
122603. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE_MASK
122604. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
122605. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU_MASK
122606. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU__SHIFT
122607. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
122608. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
122609. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
122610. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
122611. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
122612. BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
122613. BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK
122614. BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT
122615. BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK
122616. BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT
122617. BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK
122618. BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT
122619. BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK
122620. BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
122621. BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK
122622. BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
122623. BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK
122624. BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT
122625. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
122626. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
122627. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
122628. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
122629. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
122630. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
122631. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
122632. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
122633. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
122634. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
122635. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
122636. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
122637. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
122638. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
122639. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
122640. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
122641. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
122642. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
122643. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
122644. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
122645. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
122646. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
122647. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
122648. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
122649. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
122650. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
122651. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
122652. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
122653. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
122654. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
122655. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
122656. BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
122657. BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK
122658. BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT
122659. BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK
122660. BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT
122661. BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK
122662. BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT
122663. BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK
122664. BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT
122665. BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
122666. BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
122667. BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
122668. BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
122669. BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
122670. BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
122671. BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
122672. BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
122673. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
122674. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
122675. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
122676. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
122677. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
122678. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
122679. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
122680. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
122681. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
122682. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
122683. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
122684. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
122685. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
122686. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
122687. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
122688. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
122689. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
122690. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
122691. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
122692. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
122693. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
122694. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
122695. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
122696. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
122697. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
122698. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
122699. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
122700. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
122701. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
122702. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
122703. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
122704. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
122705. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
122706. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
122707. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
122708. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
122709. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
122710. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
122711. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
122712. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
122713. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
122714. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
122715. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
122716. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
122717. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
122718. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
122719. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
122720. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
122721. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
122722. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
122723. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
122724. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
122725. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
122726. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
122727. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
122728. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
122729. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
122730. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
122731. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
122732. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
122733. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
122734. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
122735. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
122736. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
122737. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
122738. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
122739. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
122740. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
122741. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
122742. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
122743. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
122744. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
122745. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
122746. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
122747. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
122748. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
122749. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
122750. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
122751. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
122752. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
122753. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
122754. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
122755. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
122756. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
122757. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
122758. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
122759. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
122760. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
122761. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
122762. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
122763. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
122764. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
122765. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
122766. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
122767. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
122768. BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
122769. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
122770. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
122771. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
122772. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
122773. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
122774. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
122775. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
122776. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
122777. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
122778. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
122779. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
122780. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
122781. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
122782. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
122783. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
122784. BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
122785. BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK
122786. BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT
122787. BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK
122788. BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT
122789. BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK
122790. BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT
122791. BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK
122792. BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT
122793. BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK
122794. BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT
122795. BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK
122796. BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT
122797. BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK
122798. BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT
122799. BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK
122800. BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT
122801. BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK
122802. BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT
122803. BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK
122804. BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
122805. BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK
122806. BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT
122807. BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK
122808. BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT
122809. BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK
122810. BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT
122811. BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK
122812. BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT
122813. BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK
122814. BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
122815. BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK
122816. BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT
122817. BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK
122818. BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT
122819. BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK
122820. BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT
122821. BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
122822. BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
122823. BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
122824. BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
122825. BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR_MASK
122826. BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT
122827. BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR_MASK
122828. BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT
122829. BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR_MASK
122830. BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT
122831. BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR_MASK
122832. BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT
122833. BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR_MASK
122834. BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT
122835. BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR_MASK
122836. BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT
122837. BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS_MASK
122838. BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS__SHIFT
122839. BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP_MASK
122840. BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP__SHIFT
122841. BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP_MASK
122842. BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP__SHIFT
122843. BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT_MASK
122844. BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT__SHIFT
122845. BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
122846. BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
122847. BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR_MASK
122848. BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR__SHIFT
122849. BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
122850. BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
122851. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING_MASK
122852. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING__SHIFT
122853. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN_MASK
122854. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN__SHIFT
122855. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN_MASK
122856. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN__SHIFT
122857. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS_MASK
122858. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS__SHIFT
122859. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN_MASK
122860. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN__SHIFT
122861. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN_MASK
122862. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN__SHIFT
122863. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
122864. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
122865. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN_MASK
122866. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN__SHIFT
122867. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
122868. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
122869. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN_MASK
122870. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN__SHIFT
122871. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK
122872. BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
122873. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
122874. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
122875. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
122876. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
122877. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
122878. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
122879. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
122880. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
122881. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
122882. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
122883. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
122884. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
122885. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
122886. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
122887. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
122888. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
122889. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
122890. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
122891. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
122892. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
122893. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
122894. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
122895. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
122896. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
122897. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
122898. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
122899. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
122900. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
122901. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
122902. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
122903. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
122904. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
122905. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
122906. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
122907. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
122908. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
122909. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
122910. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
122911. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
122912. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
122913. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
122914. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
122915. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
122916. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
122917. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG_MASK
122918. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
122919. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE_MASK
122920. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
122921. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
122922. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
122923. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
122924. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
122925. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
122926. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
122927. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK
122928. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
122929. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
122930. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
122931. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
122932. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
122933. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
122934. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
122935. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
122936. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
122937. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
122938. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
122939. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
122940. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
122941. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
122942. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
122943. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
122944. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
122945. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
122946. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
122947. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
122948. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
122949. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN_MASK
122950. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN__SHIFT
122951. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN_MASK
122952. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT
122953. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
122954. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
122955. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
122956. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
122957. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK
122958. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
122959. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
122960. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
122961. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
122962. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
122963. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR_MASK
122964. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
122965. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
122966. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
122967. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
122968. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
122969. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
122970. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
122971. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
122972. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
122973. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
122974. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
122975. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
122976. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
122977. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK
122978. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
122979. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID_MASK
122980. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID__SHIFT
122981. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED_MASK
122982. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED__SHIFT
122983. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR_MASK
122984. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR__SHIFT
122985. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR_MASK
122986. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR__SHIFT
122987. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
122988. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
122989. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR_MASK
122990. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT
122991. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
122992. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
122993. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
122994. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
122995. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED_MASK
122996. BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT
122997. BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE_MASK
122998. BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE__SHIFT
122999. BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE_MASK
123000. BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE__SHIFT
123001. BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
123002. BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
123003. BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
123004. BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
123005. BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER_MASK
123006. BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER__SHIFT
123007. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
123008. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
123009. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
123010. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
123011. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
123012. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
123013. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
123014. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
123015. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RESERVED_MASK
123016. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RESERVED__SHIFT
123017. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
123018. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
123019. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
123020. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
123021. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
123022. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
123023. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
123024. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
123025. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
123026. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
123027. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
123028. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
123029. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
123030. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
123031. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK
123032. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
123033. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
123034. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
123035. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED_MASK
123036. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED__SHIFT
123037. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH_MASK
123038. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH__SHIFT
123039. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT_MASK
123040. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT__SHIFT
123041. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER_MASK
123042. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER__SHIFT
123043. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
123044. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
123045. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
123046. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
123047. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
123048. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
123049. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
123050. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
123051. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
123052. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
123053. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
123054. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
123055. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
123056. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
123057. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
123058. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
123059. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN_MASK
123060. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
123061. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
123062. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
123063. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
123064. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
123065. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
123066. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
123067. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC_MASK
123068. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
123069. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
123070. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
123071. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
123072. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
123073. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
123074. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
123075. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS_MASK
123076. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS__SHIFT
123077. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL_MASK
123078. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL__SHIFT
123079. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
123080. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
123081. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK_MASK
123082. BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT
123083. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
123084. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
123085. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
123086. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
123087. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
123088. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
123089. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
123090. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
123091. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
123092. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
123093. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
123094. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
123095. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
123096. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
123097. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
123098. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
123099. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
123100. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
123101. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
123102. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
123103. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
123104. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
123105. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
123106. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
123107. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
123108. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
123109. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
123110. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
123111. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
123112. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
123113. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
123114. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
123115. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
123116. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
123117. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE_MASK
123118. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE__SHIFT
123119. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
123120. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
123121. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
123122. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
123123. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING_MASK
123124. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING__SHIFT
123125. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
123126. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
123127. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
123128. BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
123129. BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY__MAX_LAT_MASK
123130. BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY__MAX_LAT__SHIFT
123131. BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT__MIN_GNT_MASK
123132. BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT__MIN_GNT__SHIFT
123133. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID_MASK
123134. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT
123135. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK
123136. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
123137. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK
123138. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
123139. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
123140. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
123141. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
123142. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
123143. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK
123144. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
123145. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
123146. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
123147. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
123148. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
123149. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
123150. BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
123151. BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID_MASK
123152. BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID__SHIFT
123153. BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR_MASK
123154. BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
123155. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64_MASK
123156. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT
123157. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK_MASK
123158. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK__SHIFT
123159. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
123160. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
123161. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
123162. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
123163. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK
123164. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
123165. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN_MASK
123166. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT
123167. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
123168. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
123169. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
123170. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
123171. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
123172. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
123173. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
123174. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
123175. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA_MASK
123176. BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT
123177. BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK
123178. BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
123179. BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING_MASK
123180. BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING__SHIFT
123181. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
123182. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
123183. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
123184. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
123185. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
123186. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
123187. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
123188. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
123189. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
123190. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
123191. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
123192. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
123193. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
123194. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
123195. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
123196. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
123197. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
123198. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
123199. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
123200. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
123201. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
123202. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
123203. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
123204. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
123205. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
123206. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
123207. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
123208. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
123209. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
123210. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
123211. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
123212. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
123213. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
123214. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
123215. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
123216. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
123217. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
123218. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
123219. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
123220. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
123221. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
123222. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
123223. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
123224. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
123225. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
123226. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
123227. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
123228. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
123229. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
123230. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
123231. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__STU_MASK
123232. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__STU__SHIFT
123233. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
123234. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
123235. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
123236. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
123237. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
123238. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
123239. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID_MASK
123240. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT
123241. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK
123242. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
123243. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE_MASK
123244. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT
123245. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
123246. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
123247. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
123248. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
123249. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION_MASK
123250. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION__SHIFT
123251. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
123252. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
123253. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
123254. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
123255. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
123256. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
123257. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
123258. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
123259. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
123260. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
123261. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
123262. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
123263. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
123264. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
123265. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
123266. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
123267. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
123268. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
123269. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
123270. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
123271. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
123272. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
123273. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
123274. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
123275. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
123276. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
123277. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
123278. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
123279. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
123280. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
123281. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
123282. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
123283. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK
123284. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
123285. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK
123286. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
123287. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK
123288. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
123289. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK
123290. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
123291. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
123292. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
123293. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
123294. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
123295. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
123296. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
123297. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
123298. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
123299. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
123300. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
123301. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
123302. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
123303. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
123304. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
123305. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
123306. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
123307. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
123308. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
123309. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
123310. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
123311. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
123312. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
123313. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
123314. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
123315. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
123316. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
123317. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
123318. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
123319. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
123320. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
123321. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
123322. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
123323. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
123324. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
123325. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
123326. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
123327. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
123328. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
123329. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
123330. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
123331. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
123332. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
123333. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
123334. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
123335. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
123336. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
123337. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
123338. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
123339. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
123340. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
123341. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
123342. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
123343. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
123344. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
123345. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
123346. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
123347. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
123348. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
123349. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
123350. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
123351. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
123352. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
123353. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
123354. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
123355. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
123356. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
123357. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
123358. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
123359. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
123360. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
123361. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
123362. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
123363. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
123364. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
123365. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
123366. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
123367. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
123368. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
123369. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
123370. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
123371. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
123372. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
123373. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
123374. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
123375. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
123376. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
123377. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
123378. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
123379. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
123380. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
123381. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
123382. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
123383. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
123384. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
123385. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
123386. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
123387. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
123388. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
123389. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
123390. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
123391. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
123392. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
123393. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
123394. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
123395. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
123396. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
123397. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
123398. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
123399. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
123400. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
123401. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
123402. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
123403. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
123404. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
123405. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
123406. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
123407. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
123408. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
123409. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
123410. BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
123411. BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK
123412. BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
123413. BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID_MASK
123414. BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT
123415. BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID_MASK
123416. BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID__SHIFT
123417. BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK
123418. BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
123419. BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2__RESERVED_MASK
123420. BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2__RESERVED__SHIFT
123421. BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2__RESERVED_MASK
123422. BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2__RESERVED__SHIFT
123423. BIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2__RESERVED_MASK
123424. BIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2__RESERVED__SHIFT
123425. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST_MASK
123426. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST__SHIFT
123427. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING_MASK
123428. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING__SHIFT
123429. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE_MASK
123430. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT
123431. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__IMMEDIATE_READINESS_MASK
123432. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__IMMEDIATE_READINESS__SHIFT
123433. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS_MASK
123434. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS__SHIFT
123435. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
123436. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
123437. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED_MASK
123438. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
123439. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_CAP_MASK
123440. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_CAP__SHIFT
123441. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_EN_MASK
123442. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_EN__SHIFT
123443. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK
123444. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
123445. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK
123446. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
123447. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
123448. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
123449. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK
123450. BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
123451. BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS_MASK
123452. BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS__SHIFT
123453. BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID_MASK
123454. BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID__SHIFT
123455. BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
123456. BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
123457. BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
123458. BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
123459. BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR_MASK
123460. BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT
123461. BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR_MASK
123462. BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT
123463. BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR_MASK
123464. BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT
123465. BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR_MASK
123466. BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT
123467. BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR_MASK
123468. BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT
123469. BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR_MASK
123470. BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT
123471. BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS_MASK
123472. BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS__SHIFT
123473. BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP_MASK
123474. BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP__SHIFT
123475. BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP_MASK
123476. BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP__SHIFT
123477. BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT_MASK
123478. BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT__SHIFT
123479. BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
123480. BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
123481. BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR_MASK
123482. BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR__SHIFT
123483. BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
123484. BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
123485. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING_MASK
123486. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING__SHIFT
123487. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN_MASK
123488. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN__SHIFT
123489. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN_MASK
123490. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN__SHIFT
123491. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS_MASK
123492. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS__SHIFT
123493. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN_MASK
123494. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN__SHIFT
123495. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN_MASK
123496. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN__SHIFT
123497. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
123498. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
123499. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN_MASK
123500. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN__SHIFT
123501. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
123502. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
123503. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN_MASK
123504. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN__SHIFT
123505. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK
123506. BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
123507. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
123508. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
123509. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
123510. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
123511. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
123512. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
123513. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
123514. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
123515. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
123516. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
123517. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
123518. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
123519. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
123520. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
123521. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
123522. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
123523. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
123524. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
123525. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
123526. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
123527. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
123528. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
123529. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
123530. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
123531. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
123532. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
123533. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
123534. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
123535. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
123536. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
123537. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
123538. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
123539. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
123540. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
123541. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
123542. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
123543. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
123544. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
123545. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
123546. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
123547. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
123548. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
123549. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
123550. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
123551. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG_MASK
123552. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
123553. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE_MASK
123554. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
123555. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
123556. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
123557. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
123558. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
123559. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
123560. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
123561. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK
123562. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
123563. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
123564. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
123565. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
123566. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
123567. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
123568. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
123569. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
123570. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
123571. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
123572. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
123573. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
123574. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
123575. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
123576. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
123577. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
123578. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
123579. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
123580. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
123581. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
123582. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
123583. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN_MASK
123584. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN__SHIFT
123585. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN_MASK
123586. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT
123587. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
123588. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
123589. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
123590. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
123591. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK
123592. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
123593. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
123594. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
123595. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
123596. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
123597. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR_MASK
123598. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
123599. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
123600. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
123601. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
123602. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
123603. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
123604. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
123605. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
123606. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
123607. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
123608. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
123609. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
123610. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
123611. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK
123612. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
123613. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID_MASK
123614. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID__SHIFT
123615. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED_MASK
123616. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED__SHIFT
123617. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR_MASK
123618. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR__SHIFT
123619. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR_MASK
123620. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR__SHIFT
123621. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
123622. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
123623. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR_MASK
123624. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT
123625. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
123626. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
123627. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
123628. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
123629. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED_MASK
123630. BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT
123631. BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE_MASK
123632. BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE__SHIFT
123633. BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE_MASK
123634. BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE__SHIFT
123635. BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
123636. BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
123637. BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
123638. BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
123639. BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER_MASK
123640. BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER__SHIFT
123641. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
123642. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
123643. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
123644. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
123645. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
123646. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
123647. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
123648. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
123649. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RESERVED_MASK
123650. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RESERVED__SHIFT
123651. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
123652. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
123653. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
123654. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
123655. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
123656. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
123657. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
123658. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
123659. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
123660. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
123661. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
123662. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
123663. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
123664. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
123665. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK
123666. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
123667. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
123668. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
123669. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED_MASK
123670. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED__SHIFT
123671. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH_MASK
123672. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH__SHIFT
123673. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT_MASK
123674. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT__SHIFT
123675. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER_MASK
123676. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER__SHIFT
123677. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
123678. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
123679. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
123680. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
123681. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
123682. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
123683. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
123684. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
123685. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
123686. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
123687. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
123688. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
123689. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
123690. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
123691. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
123692. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
123693. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN_MASK
123694. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
123695. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
123696. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
123697. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
123698. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
123699. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
123700. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
123701. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC_MASK
123702. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
123703. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
123704. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
123705. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
123706. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
123707. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
123708. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
123709. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS_MASK
123710. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS__SHIFT
123711. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL_MASK
123712. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL__SHIFT
123713. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
123714. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
123715. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK_MASK
123716. BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT
123717. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
123718. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
123719. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
123720. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
123721. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
123722. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
123723. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
123724. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
123725. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
123726. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
123727. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
123728. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
123729. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
123730. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
123731. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
123732. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
123733. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
123734. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
123735. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
123736. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
123737. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
123738. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
123739. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
123740. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
123741. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
123742. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
123743. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
123744. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
123745. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
123746. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
123747. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
123748. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
123749. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
123750. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
123751. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE_MASK
123752. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE__SHIFT
123753. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
123754. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
123755. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
123756. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
123757. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING_MASK
123758. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING__SHIFT
123759. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
123760. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
123761. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
123762. BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
123763. BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY__MAX_LAT_MASK
123764. BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY__MAX_LAT__SHIFT
123765. BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT__MIN_GNT_MASK
123766. BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT__MIN_GNT__SHIFT
123767. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID_MASK
123768. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT
123769. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK
123770. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
123771. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK
123772. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
123773. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
123774. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
123775. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
123776. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
123777. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK
123778. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
123779. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
123780. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
123781. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
123782. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
123783. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
123784. BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
123785. BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID_MASK
123786. BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID__SHIFT
123787. BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR_MASK
123788. BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
123789. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64_MASK
123790. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT
123791. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK_MASK
123792. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK__SHIFT
123793. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
123794. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
123795. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
123796. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
123797. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK
123798. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
123799. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN_MASK
123800. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT
123801. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
123802. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
123803. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
123804. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
123805. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
123806. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
123807. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
123808. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
123809. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA_MASK
123810. BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT
123811. BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK
123812. BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
123813. BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING_MASK
123814. BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING__SHIFT
123815. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
123816. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
123817. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
123818. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
123819. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
123820. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
123821. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
123822. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
123823. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
123824. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
123825. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
123826. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
123827. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
123828. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
123829. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
123830. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
123831. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
123832. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
123833. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
123834. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
123835. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
123836. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
123837. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
123838. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
123839. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
123840. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
123841. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
123842. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
123843. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
123844. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
123845. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
123846. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
123847. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
123848. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
123849. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
123850. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
123851. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
123852. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
123853. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
123854. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
123855. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
123856. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
123857. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
123858. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
123859. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
123860. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
123861. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
123862. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
123863. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
123864. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
123865. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__STU_MASK
123866. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__STU__SHIFT
123867. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
123868. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
123869. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
123870. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
123871. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
123872. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
123873. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID_MASK
123874. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT
123875. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK
123876. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
123877. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE_MASK
123878. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT
123879. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
123880. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
123881. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
123882. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
123883. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION_MASK
123884. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION__SHIFT
123885. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
123886. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
123887. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
123888. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
123889. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
123890. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
123891. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
123892. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
123893. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
123894. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
123895. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
123896. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
123897. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
123898. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
123899. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
123900. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
123901. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
123902. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
123903. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
123904. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
123905. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
123906. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
123907. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
123908. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
123909. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
123910. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
123911. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
123912. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
123913. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
123914. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
123915. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
123916. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
123917. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK
123918. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
123919. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK
123920. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
123921. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK
123922. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
123923. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK
123924. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
123925. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
123926. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
123927. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
123928. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
123929. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
123930. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
123931. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
123932. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
123933. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
123934. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
123935. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
123936. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
123937. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
123938. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
123939. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
123940. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
123941. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
123942. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
123943. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
123944. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
123945. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
123946. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
123947. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
123948. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
123949. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
123950. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
123951. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
123952. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
123953. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
123954. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
123955. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
123956. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
123957. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
123958. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
123959. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
123960. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
123961. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
123962. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
123963. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
123964. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
123965. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
123966. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
123967. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
123968. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
123969. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
123970. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
123971. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
123972. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
123973. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
123974. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
123975. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
123976. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
123977. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
123978. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
123979. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
123980. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
123981. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
123982. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
123983. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
123984. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
123985. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
123986. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
123987. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
123988. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
123989. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
123990. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
123991. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
123992. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
123993. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
123994. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
123995. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
123996. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
123997. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
123998. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
123999. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
124000. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
124001. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
124002. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
124003. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
124004. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
124005. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
124006. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
124007. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
124008. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
124009. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
124010. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
124011. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
124012. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
124013. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
124014. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
124015. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
124016. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
124017. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
124018. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
124019. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
124020. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
124021. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
124022. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
124023. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
124024. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
124025. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
124026. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
124027. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
124028. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
124029. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
124030. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
124031. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
124032. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
124033. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
124034. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
124035. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
124036. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
124037. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
124038. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
124039. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
124040. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
124041. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
124042. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
124043. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
124044. BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
124045. BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK
124046. BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
124047. BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID_MASK
124048. BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT
124049. BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID_MASK
124050. BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID__SHIFT
124051. BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK
124052. BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
124053. BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CAP2__RESERVED_MASK
124054. BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CAP2__RESERVED__SHIFT
124055. BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CNTL2__RESERVED_MASK
124056. BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CNTL2__RESERVED__SHIFT
124057. BIF_CFG_DEV0_EPF0_VF4_1_SLOT_STATUS2__RESERVED_MASK
124058. BIF_CFG_DEV0_EPF0_VF4_1_SLOT_STATUS2__RESERVED__SHIFT
124059. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST_MASK
124060. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST__SHIFT
124061. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING_MASK
124062. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING__SHIFT
124063. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE_MASK
124064. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT
124065. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__IMMEDIATE_READINESS_MASK
124066. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__IMMEDIATE_READINESS__SHIFT
124067. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS_MASK
124068. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS__SHIFT
124069. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
124070. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
124071. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED_MASK
124072. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
124073. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_CAP_MASK
124074. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_CAP__SHIFT
124075. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_EN_MASK
124076. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_EN__SHIFT
124077. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK
124078. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
124079. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK
124080. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
124081. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
124082. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
124083. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK
124084. BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
124085. BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS_MASK
124086. BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS__SHIFT
124087. BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID_MASK
124088. BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID__SHIFT
124089. BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK
124090. BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
124091. BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
124092. BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
124093. BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK
124094. BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT
124095. BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK
124096. BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT
124097. BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK
124098. BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT
124099. BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK
124100. BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT
124101. BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK
124102. BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT
124103. BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK
124104. BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT
124105. BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK
124106. BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT
124107. BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK
124108. BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT
124109. BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK
124110. BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT
124111. BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK
124112. BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT
124113. BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK
124114. BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
124115. BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK
124116. BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT
124117. BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
124118. BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
124119. BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK
124120. BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT
124121. BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK
124122. BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT
124123. BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK
124124. BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT
124125. BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK
124126. BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT
124127. BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK
124128. BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT
124129. BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK
124130. BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT
124131. BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
124132. BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
124133. BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK
124134. BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT
124135. BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK
124136. BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
124137. BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK
124138. BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT
124139. BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK
124140. BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT
124141. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
124142. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
124143. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
124144. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
124145. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
124146. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
124147. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
124148. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
124149. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
124150. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
124151. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
124152. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
124153. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
124154. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
124155. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
124156. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
124157. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
124158. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
124159. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
124160. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
124161. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
124162. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
124163. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK
124164. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
124165. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
124166. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
124167. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK
124168. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
124169. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
124170. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
124171. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
124172. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
124173. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK
124174. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
124175. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
124176. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
124177. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
124178. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
124179. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
124180. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
124181. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
124182. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
124183. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
124184. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
124185. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK
124186. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT
124187. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK
124188. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT
124189. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
124190. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
124191. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
124192. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
124193. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
124194. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
124195. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK
124196. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT
124197. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
124198. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
124199. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
124200. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
124201. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
124202. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
124203. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
124204. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
124205. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
124206. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
124207. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
124208. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
124209. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
124210. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
124211. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
124212. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
124213. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
124214. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
124215. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
124216. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
124217. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK
124218. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT
124219. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK
124220. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT
124221. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
124222. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
124223. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
124224. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
124225. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK
124226. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT
124227. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
124228. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
124229. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK
124230. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
124231. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK
124232. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT
124233. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
124234. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
124235. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
124236. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
124237. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
124238. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
124239. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK
124240. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
124241. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
124242. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
124243. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK
124244. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
124245. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK
124246. BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT
124247. BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK
124248. BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT
124249. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK
124250. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT
124251. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK
124252. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT
124253. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK
124254. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT
124255. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
124256. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
124257. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK
124258. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT
124259. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK
124260. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
124261. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
124262. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
124263. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK
124264. BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT
124265. BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE_MASK
124266. BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE__SHIFT
124267. BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE_MASK
124268. BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE__SHIFT
124269. BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK
124270. BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
124271. BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK
124272. BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
124273. BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK
124274. BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT
124275. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
124276. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
124277. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
124278. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
124279. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
124280. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
124281. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
124282. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
124283. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
124284. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
124285. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
124286. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
124287. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
124288. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
124289. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
124290. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
124291. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
124292. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
124293. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
124294. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
124295. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK
124296. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
124297. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK
124298. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT
124299. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
124300. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
124301. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK
124302. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT
124303. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK
124304. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT
124305. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK
124306. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT
124307. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK
124308. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT
124309. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
124310. BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
124311. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
124312. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
124313. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK
124314. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
124315. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK
124316. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
124317. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
124318. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
124319. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
124320. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
124321. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
124322. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
124323. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK
124324. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
124325. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK
124326. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT
124327. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
124328. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
124329. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK
124330. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
124331. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
124332. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
124333. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK
124334. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT
124335. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
124336. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
124337. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
124338. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
124339. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
124340. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
124341. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK
124342. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT
124343. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK
124344. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT
124345. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK
124346. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
124347. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK
124348. BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT
124349. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
124350. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
124351. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
124352. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
124353. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
124354. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
124355. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
124356. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
124357. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
124358. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
124359. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
124360. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
124361. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
124362. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
124363. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
124364. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
124365. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
124366. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
124367. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
124368. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
124369. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
124370. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
124371. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK
124372. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
124373. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK
124374. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT
124375. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
124376. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
124377. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
124378. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
124379. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK
124380. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT
124381. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
124382. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
124383. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK
124384. BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
124385. BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK
124386. BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT
124387. BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK
124388. BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT
124389. BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK
124390. BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT
124391. BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK
124392. BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT
124393. BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK
124394. BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT
124395. BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
124396. BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
124397. BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
124398. BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
124399. BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK
124400. BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT
124401. BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK
124402. BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
124403. BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK
124404. BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
124405. BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
124406. BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
124407. BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK
124408. BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT
124409. BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK
124410. BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT
124411. BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK
124412. BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT
124413. BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK
124414. BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT
124415. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
124416. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
124417. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
124418. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
124419. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK
124420. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT
124421. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK
124422. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT
124423. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
124424. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
124425. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
124426. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
124427. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
124428. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
124429. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK
124430. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
124431. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK
124432. BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT
124433. BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK
124434. BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT
124435. BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK
124436. BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT
124437. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
124438. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
124439. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
124440. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
124441. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
124442. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
124443. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
124444. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
124445. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
124446. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
124447. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
124448. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
124449. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
124450. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
124451. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
124452. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
124453. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
124454. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
124455. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
124456. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
124457. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
124458. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
124459. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
124460. BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
124461. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
124462. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
124463. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
124464. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
124465. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
124466. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
124467. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
124468. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
124469. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
124470. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
124471. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
124472. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
124473. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
124474. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
124475. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
124476. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
124477. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
124478. BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
124479. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
124480. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
124481. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
124482. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
124483. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
124484. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
124485. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE_MASK
124486. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
124487. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU_MASK
124488. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU__SHIFT
124489. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
124490. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
124491. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
124492. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
124493. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
124494. BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
124495. BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK
124496. BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT
124497. BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK
124498. BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT
124499. BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK
124500. BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT
124501. BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK
124502. BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
124503. BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK
124504. BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
124505. BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK
124506. BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT
124507. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
124508. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
124509. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
124510. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
124511. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
124512. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
124513. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
124514. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
124515. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
124516. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
124517. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
124518. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
124519. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
124520. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
124521. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
124522. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
124523. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
124524. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
124525. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
124526. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
124527. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
124528. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
124529. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
124530. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
124531. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
124532. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
124533. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
124534. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
124535. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
124536. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
124537. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
124538. BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
124539. BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK
124540. BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT
124541. BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK
124542. BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT
124543. BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK
124544. BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT
124545. BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK
124546. BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT
124547. BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
124548. BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
124549. BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
124550. BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
124551. BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
124552. BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
124553. BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
124554. BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
124555. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
124556. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
124557. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
124558. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
124559. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
124560. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
124561. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
124562. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
124563. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
124564. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
124565. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
124566. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
124567. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
124568. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
124569. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
124570. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
124571. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
124572. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
124573. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
124574. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
124575. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
124576. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
124577. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
124578. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
124579. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
124580. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
124581. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
124582. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
124583. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
124584. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
124585. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
124586. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
124587. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
124588. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
124589. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
124590. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
124591. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
124592. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
124593. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
124594. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
124595. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
124596. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
124597. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
124598. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
124599. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
124600. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
124601. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
124602. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
124603. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
124604. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
124605. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
124606. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
124607. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
124608. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
124609. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
124610. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
124611. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
124612. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
124613. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
124614. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
124615. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
124616. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
124617. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
124618. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
124619. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
124620. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
124621. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
124622. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
124623. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
124624. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
124625. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
124626. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
124627. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
124628. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
124629. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
124630. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
124631. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
124632. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
124633. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
124634. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
124635. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
124636. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
124637. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
124638. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
124639. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
124640. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
124641. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
124642. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
124643. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
124644. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
124645. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
124646. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
124647. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
124648. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
124649. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
124650. BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
124651. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
124652. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
124653. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
124654. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
124655. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
124656. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
124657. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
124658. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
124659. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
124660. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
124661. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
124662. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
124663. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
124664. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
124665. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
124666. BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
124667. BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK
124668. BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT
124669. BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK
124670. BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT
124671. BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK
124672. BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT
124673. BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK
124674. BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT
124675. BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK
124676. BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT
124677. BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK
124678. BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT
124679. BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK
124680. BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT
124681. BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK
124682. BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT
124683. BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK
124684. BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT
124685. BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK
124686. BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
124687. BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK
124688. BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT
124689. BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK
124690. BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT
124691. BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK
124692. BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT
124693. BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK
124694. BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT
124695. BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK
124696. BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
124697. BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK
124698. BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT
124699. BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK
124700. BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT
124701. BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK
124702. BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT
124703. BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
124704. BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
124705. BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
124706. BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
124707. BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR_MASK
124708. BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT
124709. BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR_MASK
124710. BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT
124711. BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR_MASK
124712. BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT
124713. BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR_MASK
124714. BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT
124715. BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR_MASK
124716. BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT
124717. BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR_MASK
124718. BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT
124719. BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS_MASK
124720. BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS__SHIFT
124721. BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP_MASK
124722. BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP__SHIFT
124723. BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP_MASK
124724. BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP__SHIFT
124725. BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT_MASK
124726. BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT__SHIFT
124727. BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
124728. BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
124729. BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR_MASK
124730. BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR__SHIFT
124731. BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
124732. BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
124733. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING_MASK
124734. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING__SHIFT
124735. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN_MASK
124736. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN__SHIFT
124737. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN_MASK
124738. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN__SHIFT
124739. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS_MASK
124740. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS__SHIFT
124741. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN_MASK
124742. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN__SHIFT
124743. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN_MASK
124744. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN__SHIFT
124745. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
124746. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
124747. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN_MASK
124748. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN__SHIFT
124749. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
124750. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
124751. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN_MASK
124752. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN__SHIFT
124753. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK
124754. BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
124755. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
124756. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
124757. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
124758. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
124759. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
124760. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
124761. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
124762. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
124763. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
124764. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
124765. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
124766. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
124767. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
124768. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
124769. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
124770. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
124771. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
124772. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
124773. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
124774. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
124775. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
124776. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
124777. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
124778. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
124779. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
124780. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
124781. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
124782. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
124783. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
124784. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
124785. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
124786. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
124787. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
124788. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
124789. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
124790. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
124791. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
124792. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
124793. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
124794. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
124795. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
124796. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
124797. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
124798. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
124799. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG_MASK
124800. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
124801. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE_MASK
124802. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
124803. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
124804. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
124805. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
124806. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
124807. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
124808. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
124809. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK
124810. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
124811. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
124812. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
124813. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
124814. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
124815. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
124816. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
124817. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
124818. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
124819. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
124820. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
124821. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
124822. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
124823. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
124824. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
124825. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
124826. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
124827. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
124828. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
124829. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
124830. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
124831. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN_MASK
124832. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN__SHIFT
124833. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN_MASK
124834. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT
124835. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
124836. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
124837. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
124838. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
124839. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK
124840. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
124841. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
124842. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
124843. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
124844. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
124845. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR_MASK
124846. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
124847. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
124848. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
124849. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
124850. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
124851. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
124852. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
124853. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
124854. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
124855. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
124856. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
124857. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
124858. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
124859. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK
124860. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
124861. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID_MASK
124862. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID__SHIFT
124863. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED_MASK
124864. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED__SHIFT
124865. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR_MASK
124866. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR__SHIFT
124867. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR_MASK
124868. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR__SHIFT
124869. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
124870. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
124871. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR_MASK
124872. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT
124873. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
124874. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
124875. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
124876. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
124877. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED_MASK
124878. BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT
124879. BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE_MASK
124880. BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE__SHIFT
124881. BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE_MASK
124882. BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE__SHIFT
124883. BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
124884. BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
124885. BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
124886. BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
124887. BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER_MASK
124888. BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER__SHIFT
124889. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
124890. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
124891. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
124892. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
124893. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
124894. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
124895. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
124896. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
124897. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RESERVED_MASK
124898. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RESERVED__SHIFT
124899. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
124900. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
124901. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
124902. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
124903. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
124904. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
124905. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
124906. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
124907. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
124908. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
124909. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
124910. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
124911. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
124912. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
124913. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK
124914. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
124915. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
124916. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
124917. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED_MASK
124918. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED__SHIFT
124919. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH_MASK
124920. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH__SHIFT
124921. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT_MASK
124922. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT__SHIFT
124923. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER_MASK
124924. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER__SHIFT
124925. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
124926. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
124927. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
124928. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
124929. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
124930. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
124931. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
124932. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
124933. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
124934. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
124935. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
124936. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
124937. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
124938. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
124939. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
124940. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
124941. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN_MASK
124942. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
124943. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
124944. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
124945. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
124946. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
124947. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
124948. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
124949. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC_MASK
124950. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
124951. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
124952. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
124953. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
124954. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
124955. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
124956. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
124957. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS_MASK
124958. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS__SHIFT
124959. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL_MASK
124960. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL__SHIFT
124961. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
124962. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
124963. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK_MASK
124964. BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT
124965. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
124966. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
124967. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
124968. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
124969. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
124970. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
124971. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
124972. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
124973. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
124974. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
124975. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
124976. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
124977. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
124978. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
124979. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
124980. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
124981. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
124982. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
124983. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
124984. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
124985. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
124986. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
124987. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
124988. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
124989. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
124990. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
124991. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
124992. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
124993. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
124994. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
124995. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
124996. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
124997. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
124998. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
124999. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE_MASK
125000. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE__SHIFT
125001. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
125002. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
125003. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
125004. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
125005. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING_MASK
125006. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING__SHIFT
125007. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
125008. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
125009. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
125010. BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
125011. BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY__MAX_LAT_MASK
125012. BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY__MAX_LAT__SHIFT
125013. BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT__MIN_GNT_MASK
125014. BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT__MIN_GNT__SHIFT
125015. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID_MASK
125016. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT
125017. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK
125018. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
125019. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK
125020. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
125021. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
125022. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
125023. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
125024. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
125025. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK
125026. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
125027. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
125028. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
125029. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
125030. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
125031. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
125032. BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
125033. BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID_MASK
125034. BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID__SHIFT
125035. BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR_MASK
125036. BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
125037. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64_MASK
125038. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT
125039. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK_MASK
125040. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK__SHIFT
125041. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
125042. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
125043. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
125044. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
125045. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK
125046. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
125047. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN_MASK
125048. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT
125049. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
125050. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
125051. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
125052. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
125053. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
125054. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
125055. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
125056. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
125057. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA_MASK
125058. BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT
125059. BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK
125060. BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
125061. BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING_MASK
125062. BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING__SHIFT
125063. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
125064. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
125065. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
125066. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
125067. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
125068. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
125069. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
125070. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
125071. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
125072. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
125073. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
125074. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
125075. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
125076. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
125077. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
125078. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
125079. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
125080. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
125081. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
125082. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
125083. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
125084. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
125085. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
125086. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
125087. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
125088. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
125089. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
125090. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
125091. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
125092. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
125093. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
125094. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
125095. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
125096. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
125097. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
125098. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
125099. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
125100. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
125101. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
125102. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
125103. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
125104. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
125105. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
125106. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
125107. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
125108. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
125109. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
125110. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
125111. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
125112. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
125113. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__STU_MASK
125114. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__STU__SHIFT
125115. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
125116. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
125117. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
125118. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
125119. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
125120. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
125121. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID_MASK
125122. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT
125123. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK
125124. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
125125. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE_MASK
125126. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT
125127. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
125128. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
125129. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
125130. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
125131. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION_MASK
125132. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION__SHIFT
125133. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
125134. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
125135. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
125136. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
125137. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
125138. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
125139. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
125140. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
125141. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
125142. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
125143. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
125144. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
125145. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
125146. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
125147. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
125148. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
125149. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
125150. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
125151. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
125152. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
125153. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
125154. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
125155. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
125156. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
125157. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
125158. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
125159. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
125160. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
125161. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
125162. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
125163. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
125164. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
125165. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK
125166. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
125167. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK
125168. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
125169. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK
125170. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
125171. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK
125172. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
125173. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
125174. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
125175. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
125176. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
125177. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
125178. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
125179. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
125180. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
125181. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
125182. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
125183. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
125184. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
125185. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
125186. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
125187. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
125188. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
125189. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
125190. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
125191. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
125192. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
125193. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
125194. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
125195. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
125196. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
125197. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
125198. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
125199. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
125200. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
125201. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
125202. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
125203. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
125204. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
125205. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
125206. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
125207. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
125208. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
125209. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
125210. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
125211. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
125212. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
125213. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
125214. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
125215. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
125216. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
125217. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
125218. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
125219. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
125220. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
125221. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
125222. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
125223. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
125224. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
125225. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
125226. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
125227. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
125228. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
125229. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
125230. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
125231. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
125232. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
125233. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
125234. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
125235. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
125236. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
125237. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
125238. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
125239. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
125240. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
125241. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
125242. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
125243. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
125244. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
125245. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
125246. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
125247. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
125248. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
125249. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
125250. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
125251. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
125252. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
125253. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
125254. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
125255. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
125256. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
125257. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
125258. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
125259. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
125260. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
125261. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
125262. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
125263. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
125264. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
125265. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
125266. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
125267. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
125268. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
125269. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
125270. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
125271. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
125272. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
125273. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
125274. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
125275. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
125276. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
125277. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
125278. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
125279. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
125280. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
125281. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
125282. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
125283. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
125284. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
125285. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
125286. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
125287. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
125288. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
125289. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
125290. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
125291. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
125292. BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
125293. BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK
125294. BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
125295. BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID_MASK
125296. BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT
125297. BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID_MASK
125298. BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID__SHIFT
125299. BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK
125300. BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
125301. BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2__RESERVED_MASK
125302. BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2__RESERVED__SHIFT
125303. BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2__RESERVED_MASK
125304. BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2__RESERVED__SHIFT
125305. BIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2__RESERVED_MASK
125306. BIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2__RESERVED__SHIFT
125307. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST_MASK
125308. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST__SHIFT
125309. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING_MASK
125310. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING__SHIFT
125311. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE_MASK
125312. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT
125313. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__IMMEDIATE_READINESS_MASK
125314. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__IMMEDIATE_READINESS__SHIFT
125315. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS_MASK
125316. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS__SHIFT
125317. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
125318. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
125319. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED_MASK
125320. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
125321. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_CAP_MASK
125322. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_CAP__SHIFT
125323. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_EN_MASK
125324. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_EN__SHIFT
125325. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK
125326. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
125327. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK
125328. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
125329. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
125330. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
125331. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK
125332. BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
125333. BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS_MASK
125334. BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS__SHIFT
125335. BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID_MASK
125336. BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID__SHIFT
125337. BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
125338. BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
125339. BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
125340. BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
125341. BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR_MASK
125342. BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT
125343. BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR_MASK
125344. BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT
125345. BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR_MASK
125346. BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT
125347. BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR_MASK
125348. BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT
125349. BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR_MASK
125350. BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT
125351. BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR_MASK
125352. BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT
125353. BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS_MASK
125354. BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS__SHIFT
125355. BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP_MASK
125356. BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP__SHIFT
125357. BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP_MASK
125358. BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP__SHIFT
125359. BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT_MASK
125360. BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT__SHIFT
125361. BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
125362. BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
125363. BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR_MASK
125364. BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR__SHIFT
125365. BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
125366. BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
125367. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING_MASK
125368. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING__SHIFT
125369. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN_MASK
125370. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN__SHIFT
125371. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN_MASK
125372. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN__SHIFT
125373. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS_MASK
125374. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS__SHIFT
125375. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN_MASK
125376. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN__SHIFT
125377. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN_MASK
125378. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN__SHIFT
125379. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
125380. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
125381. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN_MASK
125382. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN__SHIFT
125383. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
125384. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
125385. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN_MASK
125386. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN__SHIFT
125387. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK
125388. BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
125389. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
125390. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
125391. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
125392. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
125393. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
125394. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
125395. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
125396. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
125397. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
125398. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
125399. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
125400. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
125401. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
125402. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
125403. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
125404. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
125405. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
125406. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
125407. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
125408. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
125409. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
125410. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
125411. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
125412. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
125413. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
125414. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
125415. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
125416. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
125417. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
125418. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
125419. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
125420. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
125421. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
125422. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
125423. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
125424. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
125425. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
125426. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
125427. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
125428. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
125429. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
125430. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
125431. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
125432. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
125433. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG_MASK
125434. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
125435. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE_MASK
125436. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
125437. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
125438. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
125439. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
125440. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
125441. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
125442. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
125443. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK
125444. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
125445. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
125446. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
125447. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
125448. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
125449. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
125450. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
125451. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
125452. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
125453. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
125454. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
125455. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
125456. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
125457. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
125458. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
125459. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
125460. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
125461. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
125462. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
125463. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
125464. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
125465. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN_MASK
125466. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN__SHIFT
125467. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN_MASK
125468. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT
125469. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
125470. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
125471. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
125472. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
125473. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK
125474. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
125475. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
125476. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
125477. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
125478. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
125479. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR_MASK
125480. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
125481. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
125482. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
125483. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
125484. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
125485. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
125486. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
125487. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
125488. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
125489. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
125490. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
125491. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
125492. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
125493. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK
125494. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
125495. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID_MASK
125496. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID__SHIFT
125497. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED_MASK
125498. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED__SHIFT
125499. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR_MASK
125500. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR__SHIFT
125501. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR_MASK
125502. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR__SHIFT
125503. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
125504. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
125505. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR_MASK
125506. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT
125507. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
125508. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
125509. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
125510. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
125511. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED_MASK
125512. BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT
125513. BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE_MASK
125514. BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE__SHIFT
125515. BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE_MASK
125516. BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE__SHIFT
125517. BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
125518. BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
125519. BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
125520. BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
125521. BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER_MASK
125522. BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER__SHIFT
125523. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
125524. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
125525. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
125526. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
125527. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
125528. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
125529. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
125530. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
125531. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RESERVED_MASK
125532. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RESERVED__SHIFT
125533. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
125534. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
125535. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
125536. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
125537. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
125538. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
125539. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
125540. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
125541. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
125542. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
125543. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
125544. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
125545. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
125546. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
125547. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK
125548. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
125549. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
125550. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
125551. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED_MASK
125552. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED__SHIFT
125553. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH_MASK
125554. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH__SHIFT
125555. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT_MASK
125556. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT__SHIFT
125557. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER_MASK
125558. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER__SHIFT
125559. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
125560. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
125561. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
125562. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
125563. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
125564. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
125565. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
125566. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
125567. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
125568. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
125569. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
125570. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
125571. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
125572. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
125573. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
125574. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
125575. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN_MASK
125576. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
125577. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
125578. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
125579. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
125580. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
125581. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
125582. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
125583. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC_MASK
125584. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
125585. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
125586. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
125587. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
125588. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
125589. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
125590. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
125591. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS_MASK
125592. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS__SHIFT
125593. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL_MASK
125594. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL__SHIFT
125595. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
125596. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
125597. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK_MASK
125598. BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT
125599. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
125600. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
125601. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
125602. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
125603. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
125604. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
125605. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
125606. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
125607. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
125608. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
125609. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
125610. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
125611. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
125612. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
125613. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
125614. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
125615. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
125616. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
125617. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
125618. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
125619. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
125620. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
125621. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
125622. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
125623. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
125624. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
125625. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
125626. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
125627. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
125628. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
125629. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
125630. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
125631. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
125632. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
125633. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE_MASK
125634. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE__SHIFT
125635. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
125636. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
125637. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
125638. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
125639. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING_MASK
125640. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING__SHIFT
125641. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
125642. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
125643. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
125644. BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
125645. BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY__MAX_LAT_MASK
125646. BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY__MAX_LAT__SHIFT
125647. BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT__MIN_GNT_MASK
125648. BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT__MIN_GNT__SHIFT
125649. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID_MASK
125650. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT
125651. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK
125652. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
125653. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK
125654. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
125655. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
125656. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
125657. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
125658. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
125659. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK
125660. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
125661. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
125662. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
125663. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
125664. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
125665. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
125666. BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
125667. BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID_MASK
125668. BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID__SHIFT
125669. BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR_MASK
125670. BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
125671. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64_MASK
125672. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT
125673. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK_MASK
125674. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK__SHIFT
125675. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
125676. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
125677. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
125678. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
125679. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK
125680. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
125681. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN_MASK
125682. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT
125683. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
125684. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
125685. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
125686. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
125687. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
125688. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
125689. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
125690. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
125691. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA_MASK
125692. BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT
125693. BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK
125694. BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
125695. BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING_MASK
125696. BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING__SHIFT
125697. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
125698. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
125699. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
125700. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
125701. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
125702. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
125703. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
125704. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
125705. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
125706. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
125707. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
125708. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
125709. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
125710. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
125711. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
125712. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
125713. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
125714. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
125715. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
125716. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
125717. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
125718. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
125719. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
125720. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
125721. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
125722. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
125723. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
125724. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
125725. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
125726. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
125727. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
125728. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
125729. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
125730. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
125731. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
125732. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
125733. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
125734. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
125735. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
125736. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
125737. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
125738. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
125739. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
125740. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
125741. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
125742. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
125743. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
125744. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
125745. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
125746. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
125747. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__STU_MASK
125748. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__STU__SHIFT
125749. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
125750. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
125751. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
125752. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
125753. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
125754. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
125755. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID_MASK
125756. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT
125757. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK
125758. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
125759. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE_MASK
125760. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT
125761. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
125762. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
125763. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
125764. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
125765. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION_MASK
125766. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION__SHIFT
125767. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
125768. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
125769. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
125770. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
125771. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
125772. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
125773. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
125774. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
125775. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
125776. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
125777. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
125778. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
125779. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
125780. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
125781. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
125782. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
125783. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
125784. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
125785. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
125786. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
125787. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
125788. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
125789. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
125790. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
125791. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
125792. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
125793. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
125794. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
125795. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
125796. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
125797. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
125798. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
125799. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK
125800. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
125801. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK
125802. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
125803. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK
125804. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
125805. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK
125806. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
125807. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
125808. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
125809. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
125810. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
125811. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
125812. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
125813. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
125814. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
125815. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
125816. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
125817. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
125818. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
125819. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
125820. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
125821. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
125822. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
125823. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
125824. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
125825. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
125826. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
125827. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
125828. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
125829. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
125830. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
125831. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
125832. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
125833. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
125834. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
125835. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
125836. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
125837. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
125838. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
125839. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
125840. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
125841. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
125842. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
125843. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
125844. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
125845. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
125846. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
125847. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
125848. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
125849. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
125850. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
125851. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
125852. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
125853. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
125854. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
125855. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
125856. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
125857. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
125858. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
125859. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
125860. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
125861. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
125862. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
125863. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
125864. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
125865. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
125866. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
125867. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
125868. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
125869. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
125870. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
125871. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
125872. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
125873. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
125874. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
125875. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
125876. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
125877. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
125878. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
125879. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
125880. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
125881. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
125882. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
125883. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
125884. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
125885. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
125886. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
125887. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
125888. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
125889. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
125890. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
125891. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
125892. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
125893. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
125894. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
125895. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
125896. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
125897. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
125898. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
125899. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
125900. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
125901. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
125902. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
125903. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
125904. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
125905. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
125906. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
125907. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
125908. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
125909. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
125910. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
125911. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
125912. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
125913. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
125914. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
125915. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
125916. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
125917. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
125918. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
125919. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
125920. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
125921. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
125922. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
125923. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
125924. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
125925. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
125926. BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
125927. BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK
125928. BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
125929. BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID_MASK
125930. BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT
125931. BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID_MASK
125932. BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID__SHIFT
125933. BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK
125934. BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
125935. BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CAP2__RESERVED_MASK
125936. BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CAP2__RESERVED__SHIFT
125937. BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CNTL2__RESERVED_MASK
125938. BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CNTL2__RESERVED__SHIFT
125939. BIF_CFG_DEV0_EPF0_VF5_1_SLOT_STATUS2__RESERVED_MASK
125940. BIF_CFG_DEV0_EPF0_VF5_1_SLOT_STATUS2__RESERVED__SHIFT
125941. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST_MASK
125942. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST__SHIFT
125943. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING_MASK
125944. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING__SHIFT
125945. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE_MASK
125946. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT
125947. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__IMMEDIATE_READINESS_MASK
125948. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__IMMEDIATE_READINESS__SHIFT
125949. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS_MASK
125950. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS__SHIFT
125951. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
125952. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
125953. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED_MASK
125954. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
125955. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_CAP_MASK
125956. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_CAP__SHIFT
125957. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_EN_MASK
125958. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_EN__SHIFT
125959. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK
125960. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
125961. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK
125962. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
125963. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
125964. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
125965. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK
125966. BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
125967. BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS_MASK
125968. BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS__SHIFT
125969. BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID_MASK
125970. BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID__SHIFT
125971. BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK
125972. BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
125973. BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
125974. BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
125975. BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK
125976. BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT
125977. BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK
125978. BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT
125979. BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK
125980. BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT
125981. BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK
125982. BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT
125983. BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK
125984. BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT
125985. BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK
125986. BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT
125987. BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK
125988. BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT
125989. BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK
125990. BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT
125991. BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK
125992. BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT
125993. BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK
125994. BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT
125995. BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK
125996. BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
125997. BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK
125998. BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT
125999. BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
126000. BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
126001. BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK
126002. BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT
126003. BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK
126004. BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT
126005. BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK
126006. BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT
126007. BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK
126008. BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT
126009. BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK
126010. BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT
126011. BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK
126012. BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT
126013. BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
126014. BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
126015. BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK
126016. BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT
126017. BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK
126018. BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
126019. BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK
126020. BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT
126021. BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK
126022. BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT
126023. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
126024. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
126025. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
126026. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
126027. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
126028. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
126029. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
126030. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
126031. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
126032. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
126033. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
126034. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
126035. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
126036. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
126037. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
126038. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
126039. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
126040. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
126041. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
126042. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
126043. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
126044. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
126045. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK
126046. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
126047. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
126048. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
126049. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK
126050. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
126051. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
126052. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
126053. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
126054. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
126055. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK
126056. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
126057. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
126058. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
126059. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
126060. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
126061. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
126062. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
126063. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
126064. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
126065. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
126066. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
126067. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK
126068. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT
126069. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK
126070. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT
126071. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
126072. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
126073. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
126074. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
126075. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
126076. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
126077. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK
126078. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT
126079. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
126080. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
126081. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
126082. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
126083. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
126084. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
126085. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
126086. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
126087. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
126088. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
126089. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
126090. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
126091. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
126092. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
126093. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
126094. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
126095. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
126096. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
126097. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
126098. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
126099. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK
126100. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT
126101. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK
126102. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT
126103. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
126104. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
126105. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
126106. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
126107. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK
126108. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT
126109. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
126110. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
126111. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK
126112. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
126113. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK
126114. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT
126115. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
126116. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
126117. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
126118. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
126119. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
126120. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
126121. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK
126122. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
126123. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
126124. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
126125. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK
126126. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
126127. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK
126128. BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT
126129. BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK
126130. BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT
126131. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK
126132. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT
126133. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK
126134. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT
126135. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK
126136. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT
126137. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
126138. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
126139. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK
126140. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT
126141. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK
126142. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
126143. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
126144. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
126145. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK
126146. BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT
126147. BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE_MASK
126148. BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE__SHIFT
126149. BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE_MASK
126150. BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE__SHIFT
126151. BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK
126152. BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
126153. BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK
126154. BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
126155. BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK
126156. BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT
126157. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
126158. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
126159. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
126160. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
126161. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
126162. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
126163. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
126164. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
126165. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
126166. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
126167. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
126168. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
126169. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
126170. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
126171. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
126172. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
126173. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
126174. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
126175. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
126176. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
126177. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK
126178. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
126179. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK
126180. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT
126181. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
126182. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
126183. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK
126184. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT
126185. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK
126186. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT
126187. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK
126188. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT
126189. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK
126190. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT
126191. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
126192. BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
126193. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
126194. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
126195. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK
126196. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
126197. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK
126198. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
126199. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
126200. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
126201. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
126202. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
126203. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
126204. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
126205. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK
126206. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
126207. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK
126208. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT
126209. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
126210. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
126211. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK
126212. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
126213. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
126214. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
126215. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK
126216. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT
126217. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
126218. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
126219. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
126220. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
126221. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
126222. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
126223. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK
126224. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT
126225. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK
126226. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT
126227. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK
126228. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
126229. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK
126230. BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT
126231. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
126232. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
126233. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
126234. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
126235. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
126236. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
126237. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
126238. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
126239. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
126240. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
126241. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
126242. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
126243. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
126244. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
126245. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
126246. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
126247. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
126248. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
126249. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
126250. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
126251. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
126252. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
126253. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK
126254. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
126255. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK
126256. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT
126257. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
126258. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
126259. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
126260. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
126261. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK
126262. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT
126263. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
126264. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
126265. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK
126266. BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
126267. BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK
126268. BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT
126269. BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK
126270. BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT
126271. BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK
126272. BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT
126273. BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK
126274. BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT
126275. BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK
126276. BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT
126277. BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
126278. BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
126279. BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
126280. BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
126281. BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK
126282. BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT
126283. BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK
126284. BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
126285. BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK
126286. BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
126287. BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
126288. BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
126289. BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK
126290. BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT
126291. BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK
126292. BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT
126293. BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK
126294. BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT
126295. BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK
126296. BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT
126297. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
126298. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
126299. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
126300. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
126301. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK
126302. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT
126303. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK
126304. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT
126305. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
126306. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
126307. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
126308. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
126309. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
126310. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
126311. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK
126312. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
126313. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK
126314. BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT
126315. BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK
126316. BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT
126317. BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK
126318. BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT
126319. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
126320. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
126321. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
126322. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
126323. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
126324. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
126325. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
126326. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
126327. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
126328. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
126329. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
126330. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
126331. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
126332. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
126333. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
126334. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
126335. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
126336. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
126337. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
126338. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
126339. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
126340. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
126341. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
126342. BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
126343. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
126344. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
126345. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
126346. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
126347. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
126348. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
126349. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
126350. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
126351. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
126352. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
126353. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
126354. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
126355. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
126356. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
126357. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
126358. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
126359. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
126360. BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
126361. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
126362. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
126363. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
126364. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
126365. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
126366. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
126367. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE_MASK
126368. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
126369. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU_MASK
126370. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU__SHIFT
126371. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
126372. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
126373. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
126374. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
126375. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
126376. BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
126377. BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK
126378. BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT
126379. BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK
126380. BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT
126381. BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK
126382. BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT
126383. BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK
126384. BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
126385. BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK
126386. BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
126387. BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK
126388. BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT
126389. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
126390. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
126391. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
126392. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
126393. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
126394. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
126395. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
126396. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
126397. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
126398. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
126399. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
126400. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
126401. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
126402. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
126403. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
126404. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
126405. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
126406. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
126407. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
126408. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
126409. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
126410. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
126411. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
126412. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
126413. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
126414. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
126415. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
126416. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
126417. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
126418. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
126419. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
126420. BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
126421. BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK
126422. BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT
126423. BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK
126424. BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT
126425. BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK
126426. BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT
126427. BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK
126428. BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT
126429. BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
126430. BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
126431. BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
126432. BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
126433. BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
126434. BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
126435. BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
126436. BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
126437. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
126438. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
126439. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
126440. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
126441. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
126442. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
126443. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
126444. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
126445. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
126446. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
126447. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
126448. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
126449. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
126450. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
126451. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
126452. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
126453. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
126454. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
126455. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
126456. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
126457. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
126458. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
126459. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
126460. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
126461. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
126462. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
126463. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
126464. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
126465. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
126466. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
126467. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
126468. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
126469. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
126470. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
126471. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
126472. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
126473. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
126474. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
126475. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
126476. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
126477. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
126478. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
126479. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
126480. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
126481. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
126482. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
126483. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
126484. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
126485. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
126486. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
126487. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
126488. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
126489. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
126490. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
126491. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
126492. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
126493. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
126494. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
126495. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
126496. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
126497. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
126498. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
126499. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
126500. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
126501. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
126502. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
126503. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
126504. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
126505. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
126506. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
126507. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
126508. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
126509. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
126510. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
126511. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
126512. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
126513. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
126514. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
126515. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
126516. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
126517. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
126518. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
126519. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
126520. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
126521. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
126522. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
126523. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
126524. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
126525. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
126526. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
126527. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
126528. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
126529. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
126530. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
126531. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
126532. BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
126533. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
126534. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
126535. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
126536. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
126537. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
126538. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
126539. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
126540. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
126541. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
126542. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
126543. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
126544. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
126545. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
126546. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
126547. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
126548. BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
126549. BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK
126550. BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT
126551. BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK
126552. BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT
126553. BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK
126554. BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT
126555. BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK
126556. BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT
126557. BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK
126558. BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT
126559. BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK
126560. BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT
126561. BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK
126562. BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT
126563. BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK
126564. BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT
126565. BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK
126566. BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT
126567. BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK
126568. BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
126569. BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK
126570. BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT
126571. BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK
126572. BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT
126573. BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK
126574. BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT
126575. BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK
126576. BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT
126577. BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK
126578. BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
126579. BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK
126580. BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT
126581. BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK
126582. BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT
126583. BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK
126584. BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT
126585. BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
126586. BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
126587. BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
126588. BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
126589. BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR_MASK
126590. BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT
126591. BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR_MASK
126592. BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT
126593. BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR_MASK
126594. BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT
126595. BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR_MASK
126596. BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT
126597. BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR_MASK
126598. BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT
126599. BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR_MASK
126600. BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT
126601. BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS_MASK
126602. BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS__SHIFT
126603. BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP_MASK
126604. BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP__SHIFT
126605. BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP_MASK
126606. BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP__SHIFT
126607. BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT_MASK
126608. BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT__SHIFT
126609. BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
126610. BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
126611. BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR_MASK
126612. BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR__SHIFT
126613. BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
126614. BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
126615. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING_MASK
126616. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING__SHIFT
126617. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN_MASK
126618. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN__SHIFT
126619. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN_MASK
126620. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN__SHIFT
126621. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS_MASK
126622. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS__SHIFT
126623. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN_MASK
126624. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN__SHIFT
126625. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN_MASK
126626. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN__SHIFT
126627. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
126628. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
126629. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN_MASK
126630. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN__SHIFT
126631. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
126632. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
126633. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN_MASK
126634. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN__SHIFT
126635. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK
126636. BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
126637. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
126638. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
126639. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
126640. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
126641. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
126642. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
126643. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
126644. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
126645. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
126646. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
126647. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
126648. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
126649. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
126650. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
126651. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
126652. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
126653. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
126654. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
126655. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
126656. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
126657. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
126658. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
126659. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
126660. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
126661. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
126662. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
126663. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
126664. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
126665. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
126666. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
126667. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
126668. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
126669. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
126670. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
126671. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
126672. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
126673. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
126674. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
126675. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
126676. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
126677. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
126678. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
126679. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
126680. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
126681. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG_MASK
126682. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
126683. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE_MASK
126684. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
126685. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
126686. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
126687. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
126688. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
126689. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
126690. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
126691. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK
126692. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
126693. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
126694. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
126695. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
126696. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
126697. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
126698. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
126699. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
126700. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
126701. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
126702. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
126703. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
126704. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
126705. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
126706. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
126707. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
126708. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
126709. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
126710. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
126711. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
126712. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
126713. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN_MASK
126714. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN__SHIFT
126715. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN_MASK
126716. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT
126717. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
126718. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
126719. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
126720. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
126721. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK
126722. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
126723. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
126724. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
126725. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
126726. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
126727. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR_MASK
126728. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
126729. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
126730. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
126731. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
126732. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
126733. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
126734. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
126735. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
126736. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
126737. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
126738. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
126739. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
126740. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
126741. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK
126742. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
126743. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID_MASK
126744. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID__SHIFT
126745. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED_MASK
126746. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED__SHIFT
126747. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR_MASK
126748. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR__SHIFT
126749. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR_MASK
126750. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR__SHIFT
126751. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
126752. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
126753. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR_MASK
126754. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT
126755. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
126756. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
126757. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
126758. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
126759. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED_MASK
126760. BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT
126761. BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE_MASK
126762. BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE__SHIFT
126763. BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE_MASK
126764. BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE__SHIFT
126765. BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
126766. BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
126767. BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
126768. BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
126769. BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER_MASK
126770. BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER__SHIFT
126771. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
126772. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
126773. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
126774. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
126775. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
126776. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
126777. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
126778. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
126779. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RESERVED_MASK
126780. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RESERVED__SHIFT
126781. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
126782. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
126783. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
126784. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
126785. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
126786. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
126787. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
126788. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
126789. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
126790. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
126791. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
126792. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
126793. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
126794. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
126795. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK
126796. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
126797. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
126798. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
126799. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED_MASK
126800. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED__SHIFT
126801. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH_MASK
126802. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH__SHIFT
126803. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT_MASK
126804. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT__SHIFT
126805. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER_MASK
126806. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER__SHIFT
126807. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
126808. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
126809. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
126810. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
126811. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
126812. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
126813. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
126814. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
126815. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
126816. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
126817. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
126818. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
126819. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
126820. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
126821. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
126822. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
126823. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN_MASK
126824. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
126825. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
126826. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
126827. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
126828. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
126829. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
126830. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
126831. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC_MASK
126832. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
126833. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
126834. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
126835. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
126836. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
126837. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
126838. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
126839. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS_MASK
126840. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS__SHIFT
126841. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL_MASK
126842. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL__SHIFT
126843. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
126844. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
126845. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK_MASK
126846. BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT
126847. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
126848. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
126849. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
126850. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
126851. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
126852. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
126853. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
126854. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
126855. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
126856. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
126857. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
126858. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
126859. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
126860. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
126861. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
126862. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
126863. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
126864. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
126865. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
126866. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
126867. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
126868. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
126869. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
126870. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
126871. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
126872. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
126873. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
126874. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
126875. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
126876. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
126877. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
126878. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
126879. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
126880. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
126881. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE_MASK
126882. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE__SHIFT
126883. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
126884. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
126885. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
126886. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
126887. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING_MASK
126888. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING__SHIFT
126889. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
126890. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
126891. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
126892. BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
126893. BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY__MAX_LAT_MASK
126894. BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY__MAX_LAT__SHIFT
126895. BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT__MIN_GNT_MASK
126896. BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT__MIN_GNT__SHIFT
126897. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID_MASK
126898. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT
126899. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK
126900. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
126901. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK
126902. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
126903. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
126904. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
126905. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
126906. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
126907. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK
126908. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
126909. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
126910. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
126911. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
126912. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
126913. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
126914. BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
126915. BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID_MASK
126916. BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID__SHIFT
126917. BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR_MASK
126918. BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
126919. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64_MASK
126920. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT
126921. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK_MASK
126922. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK__SHIFT
126923. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
126924. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
126925. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
126926. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
126927. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK
126928. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
126929. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN_MASK
126930. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT
126931. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
126932. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
126933. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
126934. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
126935. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
126936. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
126937. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
126938. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
126939. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA_MASK
126940. BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT
126941. BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK
126942. BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
126943. BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING_MASK
126944. BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING__SHIFT
126945. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
126946. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
126947. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
126948. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
126949. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
126950. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
126951. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
126952. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
126953. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
126954. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
126955. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
126956. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
126957. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
126958. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
126959. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
126960. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
126961. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
126962. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
126963. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
126964. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
126965. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
126966. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
126967. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
126968. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
126969. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
126970. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
126971. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
126972. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
126973. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
126974. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
126975. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
126976. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
126977. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
126978. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
126979. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
126980. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
126981. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
126982. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
126983. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
126984. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
126985. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
126986. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
126987. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
126988. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
126989. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
126990. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
126991. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
126992. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
126993. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
126994. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
126995. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__STU_MASK
126996. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__STU__SHIFT
126997. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
126998. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
126999. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
127000. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
127001. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
127002. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
127003. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID_MASK
127004. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT
127005. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK
127006. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
127007. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE_MASK
127008. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT
127009. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
127010. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
127011. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
127012. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
127013. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION_MASK
127014. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION__SHIFT
127015. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
127016. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
127017. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
127018. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
127019. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
127020. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
127021. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
127022. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
127023. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
127024. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
127025. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
127026. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
127027. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
127028. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
127029. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
127030. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
127031. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
127032. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
127033. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
127034. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
127035. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
127036. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
127037. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
127038. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
127039. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
127040. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
127041. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
127042. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
127043. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
127044. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
127045. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
127046. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
127047. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK
127048. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
127049. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK
127050. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
127051. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK
127052. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
127053. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK
127054. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
127055. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
127056. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
127057. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
127058. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
127059. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
127060. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
127061. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
127062. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
127063. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
127064. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
127065. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
127066. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
127067. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
127068. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
127069. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
127070. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
127071. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
127072. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
127073. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
127074. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
127075. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
127076. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
127077. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
127078. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
127079. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
127080. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
127081. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
127082. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
127083. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
127084. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
127085. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
127086. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
127087. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
127088. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
127089. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
127090. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
127091. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
127092. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
127093. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
127094. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
127095. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
127096. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
127097. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
127098. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
127099. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
127100. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
127101. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
127102. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
127103. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
127104. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
127105. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
127106. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
127107. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
127108. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
127109. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
127110. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
127111. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
127112. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
127113. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
127114. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
127115. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
127116. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
127117. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
127118. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
127119. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
127120. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
127121. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
127122. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
127123. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
127124. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
127125. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
127126. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
127127. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
127128. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
127129. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
127130. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
127131. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
127132. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
127133. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
127134. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
127135. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
127136. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
127137. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
127138. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
127139. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
127140. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
127141. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
127142. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
127143. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
127144. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
127145. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
127146. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
127147. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
127148. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
127149. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
127150. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
127151. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
127152. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
127153. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
127154. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
127155. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
127156. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
127157. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
127158. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
127159. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
127160. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
127161. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
127162. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
127163. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
127164. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
127165. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
127166. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
127167. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
127168. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
127169. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
127170. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
127171. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
127172. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
127173. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
127174. BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
127175. BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK
127176. BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
127177. BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID_MASK
127178. BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT
127179. BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID_MASK
127180. BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID__SHIFT
127181. BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK
127182. BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
127183. BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2__RESERVED_MASK
127184. BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2__RESERVED__SHIFT
127185. BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2__RESERVED_MASK
127186. BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2__RESERVED__SHIFT
127187. BIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2__RESERVED_MASK
127188. BIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2__RESERVED__SHIFT
127189. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST_MASK
127190. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST__SHIFT
127191. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING_MASK
127192. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING__SHIFT
127193. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE_MASK
127194. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT
127195. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__IMMEDIATE_READINESS_MASK
127196. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__IMMEDIATE_READINESS__SHIFT
127197. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS_MASK
127198. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS__SHIFT
127199. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
127200. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
127201. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED_MASK
127202. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
127203. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_CAP_MASK
127204. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_CAP__SHIFT
127205. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_EN_MASK
127206. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_EN__SHIFT
127207. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK
127208. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
127209. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK
127210. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
127211. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
127212. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
127213. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK
127214. BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
127215. BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS_MASK
127216. BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS__SHIFT
127217. BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID_MASK
127218. BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID__SHIFT
127219. BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
127220. BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
127221. BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
127222. BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
127223. BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR_MASK
127224. BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT
127225. BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR_MASK
127226. BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT
127227. BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR_MASK
127228. BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT
127229. BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR_MASK
127230. BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT
127231. BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR_MASK
127232. BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT
127233. BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR_MASK
127234. BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT
127235. BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS_MASK
127236. BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS__SHIFT
127237. BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP_MASK
127238. BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP__SHIFT
127239. BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP_MASK
127240. BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP__SHIFT
127241. BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT_MASK
127242. BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT__SHIFT
127243. BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
127244. BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
127245. BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR_MASK
127246. BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR__SHIFT
127247. BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
127248. BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
127249. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING_MASK
127250. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING__SHIFT
127251. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN_MASK
127252. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN__SHIFT
127253. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN_MASK
127254. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN__SHIFT
127255. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS_MASK
127256. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS__SHIFT
127257. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN_MASK
127258. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN__SHIFT
127259. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN_MASK
127260. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN__SHIFT
127261. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
127262. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
127263. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN_MASK
127264. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN__SHIFT
127265. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
127266. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
127267. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN_MASK
127268. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN__SHIFT
127269. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK
127270. BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
127271. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
127272. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
127273. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
127274. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
127275. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
127276. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
127277. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
127278. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
127279. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
127280. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
127281. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
127282. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
127283. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
127284. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
127285. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
127286. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
127287. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
127288. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
127289. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
127290. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
127291. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
127292. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
127293. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
127294. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
127295. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
127296. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
127297. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
127298. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
127299. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
127300. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
127301. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
127302. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
127303. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
127304. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
127305. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
127306. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
127307. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
127308. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
127309. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
127310. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
127311. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
127312. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
127313. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
127314. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
127315. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG_MASK
127316. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
127317. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE_MASK
127318. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
127319. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
127320. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
127321. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
127322. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
127323. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
127324. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
127325. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK
127326. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
127327. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
127328. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
127329. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
127330. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
127331. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
127332. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
127333. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
127334. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
127335. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
127336. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
127337. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
127338. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
127339. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
127340. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
127341. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
127342. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
127343. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
127344. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
127345. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
127346. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
127347. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN_MASK
127348. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN__SHIFT
127349. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN_MASK
127350. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT
127351. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
127352. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
127353. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
127354. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
127355. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK
127356. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
127357. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
127358. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
127359. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
127360. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
127361. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR_MASK
127362. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
127363. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
127364. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
127365. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
127366. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
127367. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
127368. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
127369. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
127370. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
127371. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
127372. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
127373. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
127374. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
127375. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK
127376. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
127377. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID_MASK
127378. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID__SHIFT
127379. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED_MASK
127380. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED__SHIFT
127381. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR_MASK
127382. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR__SHIFT
127383. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR_MASK
127384. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR__SHIFT
127385. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
127386. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
127387. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR_MASK
127388. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT
127389. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
127390. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
127391. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
127392. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
127393. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED_MASK
127394. BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT
127395. BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE_MASK
127396. BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE__SHIFT
127397. BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE_MASK
127398. BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE__SHIFT
127399. BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
127400. BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
127401. BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
127402. BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
127403. BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER_MASK
127404. BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER__SHIFT
127405. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
127406. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
127407. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
127408. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
127409. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
127410. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
127411. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
127412. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
127413. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RESERVED_MASK
127414. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RESERVED__SHIFT
127415. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
127416. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
127417. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
127418. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
127419. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
127420. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
127421. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
127422. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
127423. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
127424. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
127425. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
127426. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
127427. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
127428. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
127429. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK
127430. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
127431. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
127432. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
127433. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED_MASK
127434. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED__SHIFT
127435. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH_MASK
127436. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH__SHIFT
127437. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT_MASK
127438. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT__SHIFT
127439. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER_MASK
127440. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER__SHIFT
127441. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
127442. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
127443. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
127444. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
127445. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
127446. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
127447. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
127448. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
127449. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
127450. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
127451. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
127452. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
127453. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
127454. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
127455. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
127456. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
127457. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN_MASK
127458. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
127459. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
127460. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
127461. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
127462. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
127463. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
127464. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
127465. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC_MASK
127466. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
127467. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
127468. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
127469. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
127470. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
127471. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
127472. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
127473. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS_MASK
127474. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS__SHIFT
127475. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL_MASK
127476. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL__SHIFT
127477. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
127478. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
127479. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK_MASK
127480. BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT
127481. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
127482. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
127483. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
127484. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
127485. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
127486. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
127487. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
127488. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
127489. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
127490. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
127491. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
127492. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
127493. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
127494. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
127495. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
127496. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
127497. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
127498. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
127499. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
127500. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
127501. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
127502. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
127503. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
127504. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
127505. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
127506. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
127507. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
127508. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
127509. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
127510. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
127511. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
127512. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
127513. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
127514. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
127515. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE_MASK
127516. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE__SHIFT
127517. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
127518. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
127519. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
127520. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
127521. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING_MASK
127522. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING__SHIFT
127523. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
127524. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
127525. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
127526. BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
127527. BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY__MAX_LAT_MASK
127528. BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY__MAX_LAT__SHIFT
127529. BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT__MIN_GNT_MASK
127530. BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT__MIN_GNT__SHIFT
127531. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID_MASK
127532. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT
127533. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK
127534. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
127535. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK
127536. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
127537. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
127538. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
127539. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
127540. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
127541. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK
127542. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
127543. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
127544. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
127545. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
127546. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
127547. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
127548. BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
127549. BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID_MASK
127550. BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID__SHIFT
127551. BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR_MASK
127552. BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
127553. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64_MASK
127554. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT
127555. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK_MASK
127556. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK__SHIFT
127557. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
127558. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
127559. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
127560. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
127561. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK
127562. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
127563. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN_MASK
127564. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT
127565. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
127566. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
127567. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
127568. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
127569. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
127570. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
127571. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
127572. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
127573. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA_MASK
127574. BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT
127575. BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK
127576. BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
127577. BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING_MASK
127578. BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING__SHIFT
127579. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
127580. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
127581. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
127582. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
127583. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
127584. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
127585. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
127586. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
127587. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
127588. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
127589. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
127590. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
127591. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
127592. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
127593. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
127594. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
127595. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
127596. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
127597. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
127598. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
127599. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
127600. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
127601. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
127602. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
127603. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
127604. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
127605. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
127606. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
127607. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
127608. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
127609. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
127610. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
127611. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
127612. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
127613. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
127614. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
127615. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
127616. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
127617. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
127618. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
127619. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
127620. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
127621. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
127622. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
127623. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
127624. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
127625. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
127626. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
127627. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
127628. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
127629. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__STU_MASK
127630. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__STU__SHIFT
127631. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
127632. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
127633. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
127634. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
127635. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
127636. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
127637. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID_MASK
127638. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT
127639. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK
127640. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
127641. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE_MASK
127642. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT
127643. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
127644. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
127645. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
127646. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
127647. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION_MASK
127648. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION__SHIFT
127649. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
127650. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
127651. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
127652. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
127653. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
127654. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
127655. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
127656. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
127657. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
127658. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
127659. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
127660. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
127661. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
127662. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
127663. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
127664. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
127665. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
127666. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
127667. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
127668. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
127669. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
127670. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
127671. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
127672. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
127673. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
127674. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
127675. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
127676. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
127677. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
127678. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
127679. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
127680. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
127681. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK
127682. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
127683. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK
127684. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
127685. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK
127686. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
127687. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK
127688. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
127689. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
127690. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
127691. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
127692. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
127693. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
127694. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
127695. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
127696. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
127697. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
127698. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
127699. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
127700. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
127701. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
127702. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
127703. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
127704. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
127705. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
127706. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
127707. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
127708. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
127709. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
127710. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
127711. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
127712. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
127713. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
127714. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
127715. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
127716. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
127717. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
127718. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
127719. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
127720. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
127721. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
127722. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
127723. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
127724. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
127725. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
127726. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
127727. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
127728. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
127729. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
127730. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
127731. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
127732. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
127733. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
127734. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
127735. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
127736. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
127737. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
127738. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
127739. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
127740. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
127741. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
127742. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
127743. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
127744. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
127745. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
127746. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
127747. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
127748. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
127749. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
127750. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
127751. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
127752. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
127753. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
127754. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
127755. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
127756. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
127757. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
127758. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
127759. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
127760. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
127761. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
127762. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
127763. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
127764. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
127765. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
127766. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
127767. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
127768. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
127769. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
127770. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
127771. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
127772. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
127773. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
127774. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
127775. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
127776. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
127777. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
127778. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
127779. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
127780. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
127781. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
127782. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
127783. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
127784. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
127785. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
127786. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
127787. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
127788. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
127789. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
127790. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
127791. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
127792. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
127793. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
127794. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
127795. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
127796. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
127797. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
127798. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
127799. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
127800. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
127801. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
127802. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
127803. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
127804. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
127805. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
127806. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
127807. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
127808. BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
127809. BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK
127810. BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
127811. BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID_MASK
127812. BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT
127813. BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID_MASK
127814. BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID__SHIFT
127815. BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK
127816. BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
127817. BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CAP2__RESERVED_MASK
127818. BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CAP2__RESERVED__SHIFT
127819. BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CNTL2__RESERVED_MASK
127820. BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CNTL2__RESERVED__SHIFT
127821. BIF_CFG_DEV0_EPF0_VF6_1_SLOT_STATUS2__RESERVED_MASK
127822. BIF_CFG_DEV0_EPF0_VF6_1_SLOT_STATUS2__RESERVED__SHIFT
127823. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST_MASK
127824. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST__SHIFT
127825. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING_MASK
127826. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING__SHIFT
127827. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE_MASK
127828. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT
127829. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__IMMEDIATE_READINESS_MASK
127830. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__IMMEDIATE_READINESS__SHIFT
127831. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS_MASK
127832. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS__SHIFT
127833. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
127834. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
127835. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED_MASK
127836. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
127837. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_CAP_MASK
127838. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_CAP__SHIFT
127839. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_EN_MASK
127840. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_EN__SHIFT
127841. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK
127842. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
127843. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK
127844. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
127845. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
127846. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
127847. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK
127848. BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
127849. BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS_MASK
127850. BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS__SHIFT
127851. BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID_MASK
127852. BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID__SHIFT
127853. BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK
127854. BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
127855. BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
127856. BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
127857. BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK
127858. BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT
127859. BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK
127860. BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT
127861. BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK
127862. BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT
127863. BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK
127864. BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT
127865. BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK
127866. BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT
127867. BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK
127868. BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT
127869. BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK
127870. BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT
127871. BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK
127872. BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT
127873. BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK
127874. BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT
127875. BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK
127876. BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT
127877. BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK
127878. BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
127879. BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK
127880. BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT
127881. BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
127882. BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
127883. BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK
127884. BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT
127885. BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK
127886. BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT
127887. BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK
127888. BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT
127889. BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK
127890. BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT
127891. BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK
127892. BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT
127893. BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK
127894. BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT
127895. BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
127896. BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
127897. BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK
127898. BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT
127899. BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK
127900. BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
127901. BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK
127902. BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT
127903. BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK
127904. BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT
127905. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
127906. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
127907. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
127908. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
127909. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
127910. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
127911. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
127912. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
127913. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
127914. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
127915. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
127916. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
127917. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
127918. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
127919. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
127920. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
127921. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
127922. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
127923. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
127924. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
127925. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
127926. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
127927. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK
127928. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
127929. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
127930. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
127931. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK
127932. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
127933. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
127934. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
127935. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
127936. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
127937. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK
127938. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
127939. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
127940. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
127941. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
127942. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
127943. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
127944. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
127945. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
127946. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
127947. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
127948. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
127949. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK
127950. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT
127951. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK
127952. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT
127953. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
127954. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
127955. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
127956. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
127957. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
127958. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
127959. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK
127960. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT
127961. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
127962. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
127963. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
127964. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
127965. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
127966. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
127967. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
127968. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
127969. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
127970. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
127971. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
127972. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
127973. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
127974. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
127975. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
127976. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
127977. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
127978. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
127979. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
127980. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
127981. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK
127982. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT
127983. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK
127984. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT
127985. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
127986. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
127987. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
127988. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
127989. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK
127990. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT
127991. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
127992. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
127993. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK
127994. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
127995. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK
127996. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT
127997. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
127998. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
127999. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
128000. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
128001. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
128002. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
128003. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK
128004. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
128005. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
128006. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
128007. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK
128008. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
128009. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK
128010. BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT
128011. BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK
128012. BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT
128013. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK
128014. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT
128015. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK
128016. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT
128017. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK
128018. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT
128019. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
128020. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
128021. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK
128022. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT
128023. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK
128024. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
128025. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
128026. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
128027. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK
128028. BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT
128029. BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE_MASK
128030. BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE__SHIFT
128031. BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE_MASK
128032. BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE__SHIFT
128033. BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK
128034. BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
128035. BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK
128036. BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
128037. BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK
128038. BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT
128039. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
128040. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
128041. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
128042. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
128043. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
128044. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
128045. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
128046. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
128047. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
128048. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
128049. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
128050. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
128051. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
128052. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
128053. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
128054. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
128055. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
128056. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
128057. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
128058. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
128059. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK
128060. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
128061. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK
128062. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT
128063. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
128064. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
128065. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK
128066. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT
128067. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK
128068. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT
128069. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK
128070. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT
128071. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK
128072. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT
128073. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
128074. BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
128075. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
128076. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
128077. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK
128078. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
128079. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK
128080. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
128081. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
128082. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
128083. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
128084. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
128085. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
128086. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
128087. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK
128088. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
128089. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK
128090. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT
128091. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
128092. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
128093. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK
128094. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
128095. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
128096. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
128097. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK
128098. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT
128099. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
128100. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
128101. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
128102. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
128103. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
128104. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
128105. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK
128106. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT
128107. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK
128108. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT
128109. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK
128110. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
128111. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK
128112. BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT
128113. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
128114. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
128115. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
128116. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
128117. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
128118. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
128119. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
128120. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
128121. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
128122. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
128123. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
128124. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
128125. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
128126. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
128127. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
128128. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
128129. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
128130. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
128131. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
128132. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
128133. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
128134. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
128135. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK
128136. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
128137. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK
128138. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT
128139. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
128140. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
128141. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
128142. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
128143. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK
128144. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT
128145. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
128146. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
128147. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK
128148. BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
128149. BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK
128150. BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT
128151. BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK
128152. BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT
128153. BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK
128154. BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT
128155. BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK
128156. BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT
128157. BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK
128158. BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT
128159. BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
128160. BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
128161. BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
128162. BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
128163. BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK
128164. BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT
128165. BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK
128166. BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
128167. BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK
128168. BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
128169. BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
128170. BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
128171. BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK
128172. BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT
128173. BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK
128174. BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT
128175. BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK
128176. BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT
128177. BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK
128178. BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT
128179. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
128180. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
128181. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
128182. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
128183. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK
128184. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT
128185. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK
128186. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT
128187. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
128188. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
128189. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
128190. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
128191. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
128192. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
128193. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK
128194. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
128195. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK
128196. BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT
128197. BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK
128198. BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT
128199. BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK
128200. BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT
128201. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
128202. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
128203. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
128204. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
128205. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
128206. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
128207. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
128208. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
128209. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
128210. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
128211. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
128212. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
128213. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
128214. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
128215. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
128216. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
128217. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
128218. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
128219. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
128220. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
128221. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
128222. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
128223. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
128224. BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
128225. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
128226. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
128227. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
128228. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
128229. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
128230. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
128231. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
128232. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
128233. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
128234. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
128235. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
128236. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
128237. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
128238. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
128239. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
128240. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
128241. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
128242. BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
128243. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
128244. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
128245. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
128246. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
128247. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
128248. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
128249. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE_MASK
128250. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
128251. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU_MASK
128252. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU__SHIFT
128253. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
128254. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
128255. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
128256. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
128257. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
128258. BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
128259. BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK
128260. BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT
128261. BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK
128262. BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT
128263. BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK
128264. BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT
128265. BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK
128266. BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
128267. BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK
128268. BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
128269. BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK
128270. BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT
128271. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
128272. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
128273. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
128274. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
128275. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
128276. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
128277. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
128278. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
128279. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
128280. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
128281. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
128282. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
128283. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
128284. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
128285. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
128286. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
128287. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
128288. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
128289. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
128290. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
128291. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
128292. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
128293. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
128294. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
128295. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
128296. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
128297. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
128298. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
128299. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
128300. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
128301. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
128302. BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
128303. BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK
128304. BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT
128305. BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK
128306. BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT
128307. BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK
128308. BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT
128309. BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK
128310. BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT
128311. BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
128312. BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
128313. BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
128314. BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
128315. BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
128316. BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
128317. BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
128318. BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
128319. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
128320. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
128321. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
128322. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
128323. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
128324. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
128325. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
128326. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
128327. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
128328. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
128329. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
128330. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
128331. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
128332. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
128333. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
128334. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
128335. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
128336. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
128337. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
128338. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
128339. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
128340. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
128341. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
128342. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
128343. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
128344. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
128345. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
128346. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
128347. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
128348. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
128349. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
128350. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
128351. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
128352. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
128353. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
128354. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
128355. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
128356. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
128357. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
128358. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
128359. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
128360. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
128361. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
128362. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
128363. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
128364. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
128365. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
128366. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
128367. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
128368. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
128369. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
128370. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
128371. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
128372. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
128373. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
128374. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
128375. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
128376. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
128377. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
128378. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
128379. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
128380. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
128381. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
128382. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
128383. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
128384. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
128385. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
128386. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
128387. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
128388. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
128389. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
128390. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
128391. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
128392. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
128393. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
128394. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
128395. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
128396. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
128397. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
128398. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
128399. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
128400. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
128401. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
128402. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
128403. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
128404. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
128405. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
128406. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
128407. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
128408. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
128409. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
128410. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
128411. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
128412. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
128413. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
128414. BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
128415. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
128416. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
128417. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
128418. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
128419. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
128420. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
128421. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
128422. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
128423. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
128424. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
128425. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
128426. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
128427. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
128428. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
128429. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
128430. BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
128431. BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK
128432. BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT
128433. BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK
128434. BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT
128435. BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK
128436. BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT
128437. BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK
128438. BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT
128439. BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK
128440. BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT
128441. BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK
128442. BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT
128443. BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK
128444. BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT
128445. BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK
128446. BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT
128447. BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK
128448. BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT
128449. BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK
128450. BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
128451. BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK
128452. BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT
128453. BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK
128454. BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT
128455. BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK
128456. BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT
128457. BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK
128458. BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT
128459. BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK
128460. BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
128461. BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK
128462. BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT
128463. BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK
128464. BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT
128465. BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK
128466. BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT
128467. BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
128468. BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
128469. BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
128470. BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
128471. BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR_MASK
128472. BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT
128473. BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR_MASK
128474. BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT
128475. BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR_MASK
128476. BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT
128477. BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR_MASK
128478. BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT
128479. BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR_MASK
128480. BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT
128481. BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR_MASK
128482. BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT
128483. BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS_MASK
128484. BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS__SHIFT
128485. BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP_MASK
128486. BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP__SHIFT
128487. BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP_MASK
128488. BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP__SHIFT
128489. BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT_MASK
128490. BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT__SHIFT
128491. BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
128492. BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
128493. BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR_MASK
128494. BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR__SHIFT
128495. BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
128496. BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
128497. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING_MASK
128498. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING__SHIFT
128499. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN_MASK
128500. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN__SHIFT
128501. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN_MASK
128502. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN__SHIFT
128503. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS_MASK
128504. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS__SHIFT
128505. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN_MASK
128506. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN__SHIFT
128507. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN_MASK
128508. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN__SHIFT
128509. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
128510. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
128511. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN_MASK
128512. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN__SHIFT
128513. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
128514. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
128515. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN_MASK
128516. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN__SHIFT
128517. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK
128518. BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
128519. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
128520. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
128521. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
128522. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
128523. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
128524. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
128525. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
128526. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
128527. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
128528. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
128529. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
128530. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
128531. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
128532. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
128533. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
128534. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
128535. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
128536. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
128537. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
128538. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
128539. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
128540. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
128541. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
128542. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
128543. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
128544. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
128545. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
128546. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
128547. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
128548. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
128549. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
128550. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
128551. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
128552. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
128553. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
128554. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
128555. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
128556. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
128557. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
128558. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
128559. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
128560. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
128561. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
128562. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
128563. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG_MASK
128564. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
128565. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE_MASK
128566. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
128567. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
128568. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
128569. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
128570. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
128571. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
128572. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
128573. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK
128574. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
128575. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
128576. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
128577. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
128578. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
128579. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
128580. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
128581. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
128582. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
128583. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
128584. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
128585. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
128586. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
128587. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
128588. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
128589. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
128590. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
128591. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
128592. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
128593. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
128594. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
128595. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN_MASK
128596. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN__SHIFT
128597. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN_MASK
128598. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT
128599. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
128600. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
128601. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
128602. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
128603. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK
128604. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
128605. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
128606. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
128607. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
128608. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
128609. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR_MASK
128610. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
128611. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
128612. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
128613. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
128614. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
128615. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
128616. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
128617. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
128618. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
128619. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
128620. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
128621. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
128622. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
128623. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK
128624. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
128625. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID_MASK
128626. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID__SHIFT
128627. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED_MASK
128628. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED__SHIFT
128629. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR_MASK
128630. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR__SHIFT
128631. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR_MASK
128632. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR__SHIFT
128633. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
128634. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
128635. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR_MASK
128636. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT
128637. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
128638. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
128639. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
128640. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
128641. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED_MASK
128642. BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT
128643. BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE_MASK
128644. BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE__SHIFT
128645. BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE_MASK
128646. BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE__SHIFT
128647. BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
128648. BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
128649. BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
128650. BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
128651. BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER_MASK
128652. BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER__SHIFT
128653. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
128654. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
128655. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
128656. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
128657. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
128658. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
128659. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
128660. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
128661. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RESERVED_MASK
128662. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RESERVED__SHIFT
128663. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
128664. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
128665. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
128666. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
128667. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
128668. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
128669. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
128670. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
128671. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
128672. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
128673. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
128674. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
128675. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
128676. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
128677. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK
128678. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
128679. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
128680. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
128681. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED_MASK
128682. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED__SHIFT
128683. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH_MASK
128684. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH__SHIFT
128685. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT_MASK
128686. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT__SHIFT
128687. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER_MASK
128688. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER__SHIFT
128689. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
128690. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
128691. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
128692. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
128693. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
128694. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
128695. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
128696. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
128697. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
128698. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
128699. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
128700. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
128701. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
128702. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
128703. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
128704. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
128705. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN_MASK
128706. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
128707. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
128708. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
128709. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
128710. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
128711. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
128712. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
128713. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC_MASK
128714. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
128715. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
128716. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
128717. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
128718. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
128719. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
128720. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
128721. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS_MASK
128722. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS__SHIFT
128723. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL_MASK
128724. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL__SHIFT
128725. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
128726. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
128727. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK_MASK
128728. BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT
128729. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
128730. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
128731. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
128732. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
128733. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
128734. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
128735. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
128736. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
128737. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
128738. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
128739. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
128740. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
128741. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
128742. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
128743. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
128744. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
128745. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
128746. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
128747. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
128748. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
128749. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
128750. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
128751. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
128752. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
128753. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
128754. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
128755. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
128756. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
128757. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
128758. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
128759. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
128760. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
128761. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
128762. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
128763. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE_MASK
128764. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE__SHIFT
128765. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
128766. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
128767. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
128768. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
128769. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING_MASK
128770. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING__SHIFT
128771. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
128772. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
128773. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
128774. BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
128775. BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY__MAX_LAT_MASK
128776. BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY__MAX_LAT__SHIFT
128777. BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT__MIN_GNT_MASK
128778. BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT__MIN_GNT__SHIFT
128779. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID_MASK
128780. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT
128781. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK
128782. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
128783. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK
128784. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
128785. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
128786. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
128787. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
128788. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
128789. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK
128790. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
128791. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
128792. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
128793. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
128794. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
128795. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
128796. BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
128797. BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID_MASK
128798. BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID__SHIFT
128799. BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR_MASK
128800. BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
128801. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64_MASK
128802. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT
128803. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK_MASK
128804. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK__SHIFT
128805. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
128806. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
128807. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
128808. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
128809. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK
128810. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
128811. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN_MASK
128812. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT
128813. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
128814. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
128815. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
128816. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
128817. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
128818. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
128819. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
128820. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
128821. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA_MASK
128822. BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT
128823. BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK
128824. BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
128825. BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING_MASK
128826. BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING__SHIFT
128827. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
128828. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
128829. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
128830. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
128831. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
128832. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
128833. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
128834. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
128835. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
128836. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
128837. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
128838. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
128839. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
128840. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
128841. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
128842. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
128843. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
128844. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
128845. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
128846. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
128847. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
128848. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
128849. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
128850. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
128851. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
128852. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
128853. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
128854. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
128855. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
128856. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
128857. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
128858. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
128859. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
128860. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
128861. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
128862. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
128863. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
128864. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
128865. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
128866. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
128867. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
128868. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
128869. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
128870. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
128871. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
128872. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
128873. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
128874. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
128875. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
128876. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
128877. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__STU_MASK
128878. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__STU__SHIFT
128879. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
128880. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
128881. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
128882. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
128883. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
128884. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
128885. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID_MASK
128886. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT
128887. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK
128888. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
128889. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE_MASK
128890. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT
128891. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
128892. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
128893. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
128894. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
128895. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION_MASK
128896. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION__SHIFT
128897. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
128898. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
128899. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
128900. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
128901. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
128902. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
128903. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
128904. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
128905. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
128906. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
128907. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
128908. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
128909. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
128910. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
128911. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
128912. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
128913. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
128914. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
128915. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
128916. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
128917. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
128918. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
128919. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
128920. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
128921. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
128922. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
128923. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
128924. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
128925. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
128926. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
128927. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
128928. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
128929. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK
128930. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
128931. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK
128932. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
128933. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK
128934. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
128935. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK
128936. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
128937. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
128938. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
128939. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
128940. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
128941. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
128942. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
128943. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
128944. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
128945. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
128946. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
128947. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
128948. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
128949. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
128950. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
128951. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
128952. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
128953. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
128954. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
128955. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
128956. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
128957. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
128958. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
128959. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
128960. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
128961. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
128962. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
128963. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
128964. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
128965. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
128966. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
128967. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
128968. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
128969. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
128970. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
128971. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
128972. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
128973. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
128974. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
128975. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
128976. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
128977. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
128978. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
128979. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
128980. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
128981. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
128982. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
128983. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
128984. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
128985. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
128986. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
128987. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
128988. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
128989. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
128990. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
128991. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
128992. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
128993. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
128994. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
128995. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
128996. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
128997. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
128998. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
128999. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
129000. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
129001. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
129002. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
129003. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
129004. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
129005. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
129006. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
129007. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
129008. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
129009. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
129010. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
129011. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
129012. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
129013. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
129014. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
129015. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
129016. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
129017. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
129018. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
129019. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
129020. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
129021. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
129022. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
129023. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
129024. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
129025. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
129026. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
129027. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
129028. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
129029. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
129030. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
129031. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
129032. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
129033. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
129034. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
129035. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
129036. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
129037. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
129038. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
129039. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
129040. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
129041. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
129042. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
129043. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
129044. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
129045. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
129046. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
129047. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
129048. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
129049. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
129050. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
129051. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
129052. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
129053. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
129054. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
129055. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
129056. BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
129057. BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK
129058. BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
129059. BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID_MASK
129060. BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT
129061. BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID_MASK
129062. BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID__SHIFT
129063. BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK
129064. BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
129065. BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2__RESERVED_MASK
129066. BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2__RESERVED__SHIFT
129067. BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2__RESERVED_MASK
129068. BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2__RESERVED__SHIFT
129069. BIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2__RESERVED_MASK
129070. BIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2__RESERVED__SHIFT
129071. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST_MASK
129072. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST__SHIFT
129073. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING_MASK
129074. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING__SHIFT
129075. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE_MASK
129076. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT
129077. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__IMMEDIATE_READINESS_MASK
129078. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__IMMEDIATE_READINESS__SHIFT
129079. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS_MASK
129080. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS__SHIFT
129081. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
129082. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
129083. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED_MASK
129084. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
129085. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_CAP_MASK
129086. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_CAP__SHIFT
129087. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_EN_MASK
129088. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_EN__SHIFT
129089. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK
129090. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
129091. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK
129092. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
129093. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
129094. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
129095. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK
129096. BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
129097. BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS_MASK
129098. BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS__SHIFT
129099. BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID_MASK
129100. BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID__SHIFT
129101. BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
129102. BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
129103. BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
129104. BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
129105. BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR_MASK
129106. BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT
129107. BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR_MASK
129108. BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT
129109. BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR_MASK
129110. BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT
129111. BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR_MASK
129112. BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT
129113. BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR_MASK
129114. BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT
129115. BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR_MASK
129116. BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT
129117. BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS_MASK
129118. BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS__SHIFT
129119. BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP_MASK
129120. BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP__SHIFT
129121. BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP_MASK
129122. BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP__SHIFT
129123. BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT_MASK
129124. BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT__SHIFT
129125. BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
129126. BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
129127. BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR_MASK
129128. BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR__SHIFT
129129. BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
129130. BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
129131. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING_MASK
129132. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING__SHIFT
129133. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN_MASK
129134. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN__SHIFT
129135. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN_MASK
129136. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN__SHIFT
129137. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS_MASK
129138. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS__SHIFT
129139. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN_MASK
129140. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN__SHIFT
129141. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN_MASK
129142. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN__SHIFT
129143. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
129144. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
129145. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN_MASK
129146. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN__SHIFT
129147. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
129148. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
129149. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN_MASK
129150. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN__SHIFT
129151. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK
129152. BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
129153. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
129154. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
129155. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
129156. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
129157. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
129158. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
129159. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
129160. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
129161. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
129162. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
129163. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
129164. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
129165. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
129166. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
129167. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
129168. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
129169. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
129170. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
129171. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
129172. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
129173. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
129174. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
129175. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
129176. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
129177. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
129178. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
129179. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
129180. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
129181. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
129182. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
129183. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
129184. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
129185. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
129186. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
129187. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
129188. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
129189. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
129190. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
129191. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
129192. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
129193. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
129194. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
129195. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
129196. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
129197. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG_MASK
129198. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
129199. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE_MASK
129200. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
129201. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
129202. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
129203. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
129204. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
129205. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
129206. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
129207. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK
129208. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
129209. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
129210. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
129211. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
129212. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
129213. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
129214. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
129215. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
129216. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
129217. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
129218. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
129219. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
129220. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
129221. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
129222. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
129223. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
129224. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
129225. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
129226. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
129227. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
129228. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
129229. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN_MASK
129230. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN__SHIFT
129231. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN_MASK
129232. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT
129233. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
129234. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
129235. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
129236. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
129237. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK
129238. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
129239. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
129240. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
129241. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
129242. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
129243. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR_MASK
129244. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
129245. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
129246. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
129247. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
129248. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
129249. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
129250. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
129251. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
129252. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
129253. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
129254. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
129255. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
129256. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
129257. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK
129258. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
129259. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID_MASK
129260. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID__SHIFT
129261. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED_MASK
129262. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED__SHIFT
129263. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR_MASK
129264. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR__SHIFT
129265. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR_MASK
129266. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR__SHIFT
129267. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
129268. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
129269. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR_MASK
129270. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT
129271. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
129272. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
129273. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
129274. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
129275. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED_MASK
129276. BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT
129277. BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE_MASK
129278. BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE__SHIFT
129279. BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE_MASK
129280. BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE__SHIFT
129281. BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
129282. BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
129283. BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
129284. BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
129285. BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER_MASK
129286. BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER__SHIFT
129287. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
129288. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
129289. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
129290. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
129291. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
129292. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
129293. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
129294. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
129295. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RESERVED_MASK
129296. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RESERVED__SHIFT
129297. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
129298. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
129299. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
129300. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
129301. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
129302. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
129303. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
129304. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
129305. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
129306. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
129307. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
129308. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
129309. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
129310. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
129311. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK
129312. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
129313. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
129314. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
129315. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED_MASK
129316. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED__SHIFT
129317. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH_MASK
129318. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH__SHIFT
129319. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT_MASK
129320. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT__SHIFT
129321. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER_MASK
129322. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER__SHIFT
129323. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
129324. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
129325. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
129326. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
129327. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
129328. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
129329. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
129330. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
129331. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
129332. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
129333. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
129334. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
129335. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
129336. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
129337. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
129338. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
129339. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN_MASK
129340. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
129341. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
129342. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
129343. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
129344. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
129345. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
129346. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
129347. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC_MASK
129348. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
129349. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
129350. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
129351. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
129352. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
129353. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
129354. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
129355. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS_MASK
129356. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS__SHIFT
129357. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL_MASK
129358. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL__SHIFT
129359. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
129360. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
129361. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK_MASK
129362. BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT
129363. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
129364. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
129365. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
129366. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
129367. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
129368. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
129369. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
129370. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
129371. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
129372. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
129373. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
129374. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
129375. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
129376. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
129377. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
129378. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
129379. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
129380. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
129381. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
129382. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
129383. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
129384. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
129385. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
129386. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
129387. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
129388. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
129389. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
129390. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
129391. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
129392. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
129393. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
129394. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
129395. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
129396. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
129397. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE_MASK
129398. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE__SHIFT
129399. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
129400. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
129401. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
129402. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
129403. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING_MASK
129404. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING__SHIFT
129405. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
129406. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
129407. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
129408. BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
129409. BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY__MAX_LAT_MASK
129410. BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY__MAX_LAT__SHIFT
129411. BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT__MIN_GNT_MASK
129412. BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT__MIN_GNT__SHIFT
129413. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID_MASK
129414. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT
129415. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK
129416. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
129417. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK
129418. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
129419. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
129420. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
129421. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
129422. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
129423. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK
129424. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
129425. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
129426. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
129427. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
129428. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
129429. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
129430. BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
129431. BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID_MASK
129432. BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID__SHIFT
129433. BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR_MASK
129434. BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
129435. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64_MASK
129436. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT
129437. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK_MASK
129438. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK__SHIFT
129439. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
129440. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
129441. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
129442. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
129443. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK
129444. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
129445. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN_MASK
129446. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT
129447. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
129448. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
129449. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
129450. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
129451. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
129452. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
129453. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
129454. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
129455. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA_MASK
129456. BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT
129457. BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK
129458. BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
129459. BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING_MASK
129460. BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING__SHIFT
129461. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
129462. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
129463. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
129464. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
129465. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
129466. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
129467. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
129468. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
129469. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
129470. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
129471. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
129472. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
129473. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
129474. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
129475. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
129476. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
129477. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
129478. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
129479. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
129480. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
129481. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
129482. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
129483. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
129484. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
129485. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
129486. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
129487. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
129488. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
129489. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
129490. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
129491. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
129492. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
129493. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
129494. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
129495. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
129496. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
129497. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
129498. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
129499. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
129500. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
129501. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
129502. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
129503. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
129504. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
129505. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
129506. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
129507. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
129508. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
129509. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
129510. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
129511. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__STU_MASK
129512. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__STU__SHIFT
129513. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
129514. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
129515. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
129516. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
129517. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
129518. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
129519. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID_MASK
129520. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT
129521. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK
129522. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
129523. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE_MASK
129524. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT
129525. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
129526. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
129527. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
129528. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
129529. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION_MASK
129530. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION__SHIFT
129531. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
129532. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
129533. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
129534. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
129535. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
129536. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
129537. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
129538. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
129539. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
129540. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
129541. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
129542. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
129543. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
129544. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
129545. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
129546. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
129547. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
129548. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
129549. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
129550. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
129551. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
129552. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
129553. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
129554. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
129555. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
129556. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
129557. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
129558. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
129559. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
129560. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
129561. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
129562. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
129563. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK
129564. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
129565. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK
129566. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
129567. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK
129568. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
129569. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK
129570. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
129571. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
129572. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
129573. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
129574. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
129575. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
129576. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
129577. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
129578. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
129579. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
129580. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
129581. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
129582. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
129583. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
129584. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
129585. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
129586. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
129587. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
129588. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
129589. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
129590. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
129591. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
129592. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
129593. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
129594. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
129595. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
129596. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
129597. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
129598. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
129599. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
129600. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
129601. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
129602. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
129603. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
129604. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
129605. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
129606. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
129607. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
129608. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
129609. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
129610. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
129611. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
129612. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
129613. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
129614. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
129615. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
129616. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
129617. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
129618. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
129619. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
129620. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
129621. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
129622. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
129623. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
129624. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
129625. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
129626. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
129627. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
129628. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
129629. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
129630. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
129631. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
129632. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
129633. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
129634. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
129635. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
129636. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
129637. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
129638. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
129639. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
129640. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
129641. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
129642. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
129643. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
129644. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
129645. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
129646. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
129647. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
129648. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
129649. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
129650. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
129651. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
129652. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
129653. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
129654. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
129655. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
129656. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
129657. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
129658. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
129659. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
129660. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
129661. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
129662. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
129663. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
129664. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
129665. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
129666. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
129667. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
129668. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
129669. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
129670. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
129671. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
129672. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
129673. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
129674. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
129675. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
129676. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
129677. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
129678. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
129679. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
129680. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
129681. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
129682. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
129683. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
129684. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
129685. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
129686. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
129687. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
129688. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
129689. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
129690. BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
129691. BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK
129692. BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
129693. BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID_MASK
129694. BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT
129695. BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID_MASK
129696. BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID__SHIFT
129697. BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK
129698. BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
129699. BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CAP2__RESERVED_MASK
129700. BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CAP2__RESERVED__SHIFT
129701. BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CNTL2__RESERVED_MASK
129702. BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CNTL2__RESERVED__SHIFT
129703. BIF_CFG_DEV0_EPF0_VF7_1_SLOT_STATUS2__RESERVED_MASK
129704. BIF_CFG_DEV0_EPF0_VF7_1_SLOT_STATUS2__RESERVED__SHIFT
129705. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST_MASK
129706. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST__SHIFT
129707. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING_MASK
129708. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING__SHIFT
129709. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE_MASK
129710. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT
129711. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__IMMEDIATE_READINESS_MASK
129712. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__IMMEDIATE_READINESS__SHIFT
129713. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS_MASK
129714. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS__SHIFT
129715. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
129716. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
129717. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED_MASK
129718. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
129719. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_CAP_MASK
129720. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_CAP__SHIFT
129721. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_EN_MASK
129722. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_EN__SHIFT
129723. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK
129724. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
129725. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK
129726. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
129727. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
129728. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
129729. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK
129730. BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
129731. BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS_MASK
129732. BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS__SHIFT
129733. BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID_MASK
129734. BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID__SHIFT
129735. BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK
129736. BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
129737. BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
129738. BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
129739. BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK
129740. BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT
129741. BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK
129742. BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT
129743. BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK
129744. BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT
129745. BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK
129746. BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT
129747. BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK
129748. BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT
129749. BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK
129750. BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT
129751. BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK
129752. BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT
129753. BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK
129754. BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT
129755. BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK
129756. BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT
129757. BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK
129758. BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT
129759. BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK
129760. BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
129761. BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK
129762. BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT
129763. BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
129764. BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
129765. BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK
129766. BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT
129767. BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK
129768. BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT
129769. BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK
129770. BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT
129771. BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK
129772. BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT
129773. BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK
129774. BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT
129775. BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK
129776. BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT
129777. BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
129778. BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
129779. BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK
129780. BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT
129781. BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK
129782. BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
129783. BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK
129784. BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT
129785. BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK
129786. BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT
129787. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
129788. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
129789. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
129790. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
129791. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
129792. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
129793. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
129794. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
129795. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
129796. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
129797. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
129798. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
129799. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
129800. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
129801. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
129802. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
129803. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
129804. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
129805. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
129806. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
129807. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
129808. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
129809. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK
129810. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
129811. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
129812. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
129813. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK
129814. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
129815. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
129816. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
129817. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
129818. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
129819. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK
129820. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
129821. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
129822. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
129823. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
129824. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
129825. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
129826. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
129827. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
129828. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
129829. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
129830. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
129831. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK
129832. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT
129833. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK
129834. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT
129835. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
129836. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
129837. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
129838. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
129839. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
129840. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
129841. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK
129842. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT
129843. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
129844. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
129845. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
129846. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
129847. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
129848. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
129849. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
129850. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
129851. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
129852. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
129853. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
129854. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
129855. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
129856. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
129857. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
129858. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
129859. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
129860. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
129861. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
129862. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
129863. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK
129864. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT
129865. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK
129866. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT
129867. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
129868. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
129869. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
129870. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
129871. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK
129872. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT
129873. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
129874. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
129875. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK
129876. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
129877. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK
129878. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT
129879. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
129880. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
129881. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
129882. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
129883. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
129884. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
129885. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK
129886. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
129887. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
129888. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
129889. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK
129890. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
129891. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK
129892. BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT
129893. BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK
129894. BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT
129895. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK
129896. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT
129897. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK
129898. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT
129899. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK
129900. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT
129901. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
129902. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
129903. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK
129904. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT
129905. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK
129906. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
129907. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
129908. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
129909. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK
129910. BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT
129911. BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE_MASK
129912. BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE__SHIFT
129913. BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE_MASK
129914. BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE__SHIFT
129915. BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK
129916. BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
129917. BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK
129918. BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
129919. BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK
129920. BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT
129921. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
129922. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
129923. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
129924. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
129925. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
129926. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
129927. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
129928. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
129929. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
129930. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
129931. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
129932. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
129933. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
129934. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
129935. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
129936. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
129937. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
129938. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
129939. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
129940. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
129941. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK
129942. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
129943. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK
129944. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT
129945. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
129946. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
129947. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK
129948. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT
129949. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK
129950. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT
129951. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK
129952. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT
129953. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK
129954. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT
129955. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
129956. BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
129957. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
129958. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
129959. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK
129960. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
129961. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK
129962. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
129963. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
129964. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
129965. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
129966. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
129967. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
129968. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
129969. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK
129970. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
129971. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK
129972. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT
129973. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
129974. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
129975. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK
129976. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
129977. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
129978. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
129979. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK
129980. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT
129981. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
129982. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
129983. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
129984. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
129985. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
129986. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
129987. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK
129988. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT
129989. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK
129990. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT
129991. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK
129992. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
129993. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK
129994. BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT
129995. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
129996. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
129997. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
129998. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
129999. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
130000. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
130001. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
130002. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
130003. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
130004. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
130005. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
130006. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
130007. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
130008. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
130009. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
130010. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
130011. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
130012. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
130013. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
130014. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
130015. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
130016. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
130017. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK
130018. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
130019. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK
130020. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT
130021. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
130022. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
130023. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
130024. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
130025. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK
130026. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT
130027. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
130028. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
130029. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK
130030. BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
130031. BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK
130032. BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT
130033. BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK
130034. BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT
130035. BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK
130036. BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT
130037. BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK
130038. BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT
130039. BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK
130040. BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT
130041. BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
130042. BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
130043. BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
130044. BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
130045. BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK
130046. BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT
130047. BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK
130048. BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
130049. BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK
130050. BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
130051. BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
130052. BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
130053. BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK
130054. BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT
130055. BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK
130056. BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT
130057. BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK
130058. BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT
130059. BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK
130060. BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT
130061. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
130062. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
130063. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
130064. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
130065. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK
130066. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT
130067. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK
130068. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT
130069. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
130070. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
130071. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
130072. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
130073. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
130074. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
130075. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK
130076. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
130077. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK
130078. BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT
130079. BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK
130080. BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT
130081. BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK
130082. BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT
130083. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
130084. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
130085. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
130086. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
130087. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
130088. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
130089. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
130090. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
130091. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
130092. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
130093. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
130094. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
130095. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
130096. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
130097. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
130098. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
130099. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
130100. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
130101. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
130102. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
130103. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
130104. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
130105. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
130106. BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
130107. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
130108. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
130109. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
130110. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
130111. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
130112. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
130113. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
130114. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
130115. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
130116. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
130117. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
130118. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
130119. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
130120. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
130121. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
130122. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
130123. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
130124. BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
130125. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
130126. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
130127. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
130128. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
130129. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
130130. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
130131. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE_MASK
130132. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
130133. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU_MASK
130134. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU__SHIFT
130135. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
130136. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
130137. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
130138. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
130139. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
130140. BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
130141. BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK
130142. BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT
130143. BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK
130144. BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT
130145. BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK
130146. BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT
130147. BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK
130148. BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
130149. BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK
130150. BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
130151. BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK
130152. BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT
130153. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
130154. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
130155. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
130156. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
130157. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
130158. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
130159. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
130160. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
130161. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
130162. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
130163. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
130164. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
130165. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
130166. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
130167. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
130168. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
130169. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
130170. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
130171. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
130172. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
130173. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
130174. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
130175. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
130176. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
130177. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
130178. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
130179. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
130180. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
130181. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
130182. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
130183. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
130184. BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
130185. BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK
130186. BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT
130187. BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK
130188. BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT
130189. BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK
130190. BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT
130191. BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK
130192. BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT
130193. BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
130194. BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
130195. BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
130196. BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
130197. BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
130198. BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
130199. BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
130200. BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
130201. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
130202. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
130203. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
130204. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
130205. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
130206. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
130207. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
130208. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
130209. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
130210. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
130211. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
130212. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
130213. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
130214. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
130215. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
130216. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
130217. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
130218. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
130219. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
130220. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
130221. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
130222. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
130223. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
130224. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
130225. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
130226. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
130227. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
130228. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
130229. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
130230. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
130231. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
130232. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
130233. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
130234. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
130235. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
130236. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
130237. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
130238. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
130239. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
130240. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
130241. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
130242. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
130243. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
130244. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
130245. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
130246. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
130247. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
130248. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
130249. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
130250. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
130251. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
130252. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
130253. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
130254. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
130255. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
130256. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
130257. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
130258. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
130259. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
130260. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
130261. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
130262. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
130263. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
130264. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
130265. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
130266. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
130267. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
130268. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
130269. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
130270. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
130271. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
130272. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
130273. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
130274. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
130275. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
130276. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
130277. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
130278. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
130279. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
130280. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
130281. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
130282. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
130283. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
130284. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
130285. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
130286. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
130287. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
130288. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
130289. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
130290. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
130291. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
130292. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
130293. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
130294. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
130295. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
130296. BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
130297. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
130298. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
130299. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
130300. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
130301. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
130302. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
130303. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
130304. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
130305. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
130306. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
130307. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
130308. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
130309. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
130310. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
130311. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
130312. BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
130313. BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK
130314. BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT
130315. BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK
130316. BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT
130317. BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK
130318. BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT
130319. BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK
130320. BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT
130321. BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK
130322. BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT
130323. BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK
130324. BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT
130325. BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK
130326. BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT
130327. BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK
130328. BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT
130329. BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK
130330. BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT
130331. BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK
130332. BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
130333. BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK
130334. BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT
130335. BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK
130336. BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT
130337. BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK
130338. BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT
130339. BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK
130340. BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT
130341. BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK
130342. BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
130343. BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK
130344. BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT
130345. BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK
130346. BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT
130347. BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK
130348. BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT
130349. BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
130350. BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
130351. BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
130352. BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
130353. BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR_MASK
130354. BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR__SHIFT
130355. BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR_MASK
130356. BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR__SHIFT
130357. BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR_MASK
130358. BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR__SHIFT
130359. BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR_MASK
130360. BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR__SHIFT
130361. BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR_MASK
130362. BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR__SHIFT
130363. BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR_MASK
130364. BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR__SHIFT
130365. BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS_MASK
130366. BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS__SHIFT
130367. BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP_MASK
130368. BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP__SHIFT
130369. BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP_MASK
130370. BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP__SHIFT
130371. BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT_MASK
130372. BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT__SHIFT
130373. BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
130374. BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
130375. BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR_MASK
130376. BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR__SHIFT
130377. BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
130378. BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
130379. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING_MASK
130380. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING__SHIFT
130381. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN_MASK
130382. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN__SHIFT
130383. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN_MASK
130384. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN__SHIFT
130385. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS_MASK
130386. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS__SHIFT
130387. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN_MASK
130388. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN__SHIFT
130389. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN_MASK
130390. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN__SHIFT
130391. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
130392. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
130393. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN_MASK
130394. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN__SHIFT
130395. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
130396. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
130397. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN_MASK
130398. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN__SHIFT
130399. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN_MASK
130400. BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
130401. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
130402. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
130403. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
130404. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
130405. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
130406. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
130407. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
130408. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
130409. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
130410. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
130411. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
130412. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
130413. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
130414. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
130415. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
130416. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
130417. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
130418. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
130419. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
130420. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
130421. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
130422. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
130423. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
130424. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
130425. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
130426. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
130427. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
130428. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
130429. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
130430. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
130431. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
130432. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
130433. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
130434. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
130435. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
130436. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
130437. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
130438. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
130439. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
130440. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
130441. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
130442. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
130443. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
130444. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
130445. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG_MASK
130446. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
130447. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE_MASK
130448. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
130449. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
130450. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
130451. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
130452. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
130453. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
130454. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
130455. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC_MASK
130456. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
130457. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
130458. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
130459. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
130460. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
130461. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
130462. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
130463. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
130464. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
130465. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
130466. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
130467. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
130468. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
130469. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
130470. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
130471. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
130472. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
130473. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
130474. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
130475. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
130476. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
130477. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN_MASK
130478. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN__SHIFT
130479. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN_MASK
130480. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN__SHIFT
130481. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
130482. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
130483. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
130484. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
130485. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN_MASK
130486. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
130487. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
130488. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
130489. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
130490. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
130491. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR_MASK
130492. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
130493. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
130494. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
130495. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
130496. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
130497. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
130498. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
130499. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
130500. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
130501. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
130502. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
130503. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
130504. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
130505. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN_MASK
130506. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
130507. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID_MASK
130508. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID__SHIFT
130509. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED_MASK
130510. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED__SHIFT
130511. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR_MASK
130512. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR__SHIFT
130513. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR_MASK
130514. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR__SHIFT
130515. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
130516. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
130517. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR_MASK
130518. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR__SHIFT
130519. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
130520. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
130521. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
130522. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
130523. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED_MASK
130524. BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED__SHIFT
130525. BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE_MASK
130526. BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE__SHIFT
130527. BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE_MASK
130528. BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE__SHIFT
130529. BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
130530. BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
130531. BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
130532. BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
130533. BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER_MASK
130534. BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER__SHIFT
130535. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
130536. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
130537. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
130538. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
130539. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
130540. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
130541. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
130542. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
130543. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RESERVED_MASK
130544. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RESERVED__SHIFT
130545. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
130546. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
130547. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
130548. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
130549. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
130550. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
130551. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
130552. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
130553. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
130554. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
130555. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
130556. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
130557. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
130558. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
130559. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY_MASK
130560. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
130561. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
130562. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
130563. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED_MASK
130564. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED__SHIFT
130565. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH_MASK
130566. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH__SHIFT
130567. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT_MASK
130568. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT__SHIFT
130569. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER_MASK
130570. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER__SHIFT
130571. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
130572. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
130573. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
130574. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
130575. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
130576. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
130577. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
130578. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
130579. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
130580. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
130581. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
130582. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
130583. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
130584. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
130585. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
130586. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
130587. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN_MASK
130588. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
130589. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
130590. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
130591. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
130592. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
130593. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
130594. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
130595. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC_MASK
130596. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
130597. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
130598. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
130599. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
130600. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
130601. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
130602. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
130603. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS_MASK
130604. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS__SHIFT
130605. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL_MASK
130606. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL__SHIFT
130607. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
130608. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
130609. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK_MASK
130610. BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK__SHIFT
130611. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
130612. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
130613. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
130614. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
130615. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
130616. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
130617. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
130618. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
130619. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
130620. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
130621. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
130622. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
130623. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
130624. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
130625. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
130626. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
130627. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
130628. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
130629. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
130630. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
130631. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
130632. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
130633. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
130634. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
130635. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
130636. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
130637. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
130638. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
130639. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
130640. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
130641. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
130642. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
130643. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
130644. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
130645. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE_MASK
130646. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE__SHIFT
130647. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
130648. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
130649. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
130650. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
130651. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING_MASK
130652. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING__SHIFT
130653. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
130654. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
130655. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
130656. BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
130657. BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY__MAX_LAT_MASK
130658. BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY__MAX_LAT__SHIFT
130659. BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT__MIN_GNT_MASK
130660. BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT__MIN_GNT__SHIFT
130661. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID_MASK
130662. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID__SHIFT
130663. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR_MASK
130664. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
130665. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN_MASK
130666. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
130667. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
130668. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
130669. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
130670. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
130671. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR_MASK
130672. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
130673. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
130674. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
130675. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
130676. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
130677. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
130678. BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
130679. BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID_MASK
130680. BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID__SHIFT
130681. BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR_MASK
130682. BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
130683. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64_MASK
130684. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64__SHIFT
130685. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK_MASK
130686. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK__SHIFT
130687. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
130688. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
130689. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
130690. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
130691. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT_MASK
130692. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
130693. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN_MASK
130694. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN__SHIFT
130695. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
130696. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
130697. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
130698. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
130699. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
130700. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
130701. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
130702. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
130703. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA_MASK
130704. BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA__SHIFT
130705. BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64_MASK
130706. BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
130707. BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING_MASK
130708. BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING__SHIFT
130709. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
130710. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
130711. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
130712. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
130713. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
130714. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
130715. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
130716. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
130717. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
130718. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
130719. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
130720. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
130721. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
130722. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
130723. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
130724. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
130725. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
130726. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
130727. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
130728. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
130729. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
130730. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
130731. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
130732. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
130733. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
130734. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
130735. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
130736. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
130737. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
130738. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
130739. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
130740. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
130741. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
130742. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
130743. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
130744. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
130745. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
130746. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
130747. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
130748. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
130749. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
130750. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
130751. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
130752. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
130753. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
130754. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
130755. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
130756. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
130757. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
130758. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
130759. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__STU_MASK
130760. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__STU__SHIFT
130761. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
130762. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
130763. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
130764. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
130765. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
130766. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
130767. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID_MASK
130768. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID__SHIFT
130769. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR_MASK
130770. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
130771. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE_MASK
130772. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE__SHIFT
130773. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
130774. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
130775. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
130776. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
130777. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION_MASK
130778. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION__SHIFT
130779. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
130780. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
130781. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
130782. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
130783. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
130784. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
130785. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
130786. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
130787. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
130788. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
130789. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
130790. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
130791. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
130792. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
130793. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
130794. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
130795. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
130796. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
130797. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
130798. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
130799. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
130800. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
130801. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
130802. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
130803. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
130804. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
130805. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
130806. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
130807. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
130808. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
130809. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
130810. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
130811. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR_MASK
130812. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
130813. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR_MASK
130814. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
130815. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR_MASK
130816. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
130817. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR_MASK
130818. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
130819. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
130820. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
130821. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
130822. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
130823. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
130824. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
130825. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
130826. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
130827. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
130828. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
130829. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
130830. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
130831. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
130832. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
130833. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
130834. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
130835. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
130836. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
130837. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
130838. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
130839. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
130840. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
130841. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
130842. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
130843. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
130844. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
130845. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
130846. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
130847. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
130848. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
130849. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
130850. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
130851. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
130852. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
130853. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
130854. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
130855. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
130856. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
130857. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
130858. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
130859. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
130860. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
130861. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
130862. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
130863. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
130864. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
130865. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
130866. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
130867. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
130868. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
130869. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
130870. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
130871. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
130872. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
130873. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
130874. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
130875. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
130876. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
130877. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
130878. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
130879. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
130880. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
130881. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
130882. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
130883. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
130884. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
130885. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
130886. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
130887. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
130888. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
130889. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
130890. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
130891. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
130892. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
130893. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
130894. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
130895. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
130896. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
130897. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
130898. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
130899. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
130900. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
130901. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
130902. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
130903. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
130904. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
130905. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
130906. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
130907. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
130908. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
130909. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
130910. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
130911. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
130912. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
130913. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
130914. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
130915. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
130916. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
130917. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
130918. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
130919. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
130920. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
130921. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
130922. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
130923. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
130924. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
130925. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
130926. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
130927. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
130928. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
130929. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
130930. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
130931. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
130932. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
130933. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
130934. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
130935. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
130936. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
130937. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
130938. BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
130939. BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE_MASK
130940. BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
130941. BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID_MASK
130942. BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID__SHIFT
130943. BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID_MASK
130944. BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID__SHIFT
130945. BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR_MASK
130946. BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
130947. BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2__RESERVED_MASK
130948. BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2__RESERVED__SHIFT
130949. BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2__RESERVED_MASK
130950. BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2__RESERVED__SHIFT
130951. BIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2__RESERVED_MASK
130952. BIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2__RESERVED__SHIFT
130953. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST_MASK
130954. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST__SHIFT
130955. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING_MASK
130956. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING__SHIFT
130957. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE_MASK
130958. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE__SHIFT
130959. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__IMMEDIATE_READINESS_MASK
130960. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__IMMEDIATE_READINESS__SHIFT
130961. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS_MASK
130962. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS__SHIFT
130963. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
130964. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
130965. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED_MASK
130966. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
130967. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_CAP_MASK
130968. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_CAP__SHIFT
130969. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_EN_MASK
130970. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_EN__SHIFT
130971. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT_MASK
130972. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
130973. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT_MASK
130974. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
130975. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
130976. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
130977. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT_MASK
130978. BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
130979. BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS_MASK
130980. BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS__SHIFT
130981. BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID_MASK
130982. BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID__SHIFT
130983. BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
130984. BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
130985. BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
130986. BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
130987. BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR_MASK
130988. BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR__SHIFT
130989. BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR_MASK
130990. BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR__SHIFT
130991. BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR_MASK
130992. BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR__SHIFT
130993. BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR_MASK
130994. BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR__SHIFT
130995. BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR_MASK
130996. BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR__SHIFT
130997. BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR_MASK
130998. BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR__SHIFT
130999. BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS_MASK
131000. BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS__SHIFT
131001. BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP_MASK
131002. BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP__SHIFT
131003. BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP_MASK
131004. BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP__SHIFT
131005. BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT_MASK
131006. BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT__SHIFT
131007. BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
131008. BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
131009. BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR_MASK
131010. BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR__SHIFT
131011. BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
131012. BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
131013. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING_MASK
131014. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING__SHIFT
131015. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN_MASK
131016. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN__SHIFT
131017. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN_MASK
131018. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN__SHIFT
131019. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS_MASK
131020. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS__SHIFT
131021. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN_MASK
131022. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN__SHIFT
131023. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN_MASK
131024. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN__SHIFT
131025. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
131026. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
131027. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN_MASK
131028. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN__SHIFT
131029. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
131030. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
131031. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN_MASK
131032. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN__SHIFT
131033. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN_MASK
131034. BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
131035. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
131036. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
131037. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
131038. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
131039. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
131040. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
131041. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
131042. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
131043. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
131044. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
131045. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
131046. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
131047. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
131048. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
131049. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
131050. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
131051. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
131052. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
131053. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
131054. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
131055. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
131056. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
131057. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
131058. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
131059. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
131060. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
131061. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
131062. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
131063. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
131064. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
131065. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
131066. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
131067. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
131068. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
131069. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
131070. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
131071. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
131072. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
131073. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
131074. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
131075. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
131076. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
131077. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
131078. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
131079. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG_MASK
131080. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
131081. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE_MASK
131082. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
131083. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
131084. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
131085. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
131086. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
131087. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
131088. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
131089. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC_MASK
131090. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
131091. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
131092. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
131093. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
131094. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
131095. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
131096. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
131097. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
131098. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
131099. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
131100. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
131101. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
131102. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
131103. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
131104. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
131105. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
131106. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
131107. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
131108. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
131109. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
131110. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
131111. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN_MASK
131112. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN__SHIFT
131113. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN_MASK
131114. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN__SHIFT
131115. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
131116. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
131117. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
131118. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
131119. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN_MASK
131120. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
131121. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
131122. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
131123. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
131124. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
131125. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR_MASK
131126. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
131127. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
131128. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
131129. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
131130. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
131131. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
131132. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
131133. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
131134. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
131135. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
131136. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
131137. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
131138. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
131139. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN_MASK
131140. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
131141. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID_MASK
131142. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID__SHIFT
131143. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED_MASK
131144. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED__SHIFT
131145. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR_MASK
131146. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR__SHIFT
131147. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR_MASK
131148. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR__SHIFT
131149. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
131150. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
131151. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR_MASK
131152. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR__SHIFT
131153. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
131154. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
131155. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
131156. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
131157. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED_MASK
131158. BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED__SHIFT
131159. BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE_MASK
131160. BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE__SHIFT
131161. BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE_MASK
131162. BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE__SHIFT
131163. BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
131164. BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
131165. BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
131166. BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
131167. BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER_MASK
131168. BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER__SHIFT
131169. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
131170. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
131171. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
131172. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
131173. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
131174. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
131175. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
131176. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
131177. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RESERVED_MASK
131178. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RESERVED__SHIFT
131179. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
131180. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
131181. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
131182. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
131183. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
131184. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
131185. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
131186. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
131187. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
131188. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
131189. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
131190. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
131191. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
131192. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
131193. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY_MASK
131194. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
131195. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
131196. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
131197. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED_MASK
131198. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED__SHIFT
131199. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH_MASK
131200. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH__SHIFT
131201. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT_MASK
131202. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT__SHIFT
131203. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER_MASK
131204. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER__SHIFT
131205. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
131206. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
131207. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
131208. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
131209. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
131210. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
131211. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
131212. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
131213. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
131214. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
131215. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
131216. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
131217. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
131218. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
131219. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
131220. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
131221. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN_MASK
131222. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
131223. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
131224. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
131225. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
131226. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
131227. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
131228. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
131229. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC_MASK
131230. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
131231. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
131232. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
131233. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
131234. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
131235. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
131236. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
131237. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS_MASK
131238. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS__SHIFT
131239. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL_MASK
131240. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL__SHIFT
131241. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
131242. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
131243. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK_MASK
131244. BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK__SHIFT
131245. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
131246. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
131247. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
131248. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
131249. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
131250. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
131251. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
131252. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
131253. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
131254. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
131255. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
131256. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
131257. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
131258. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
131259. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
131260. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
131261. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
131262. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
131263. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
131264. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
131265. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
131266. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
131267. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
131268. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
131269. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
131270. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
131271. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
131272. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
131273. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
131274. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
131275. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
131276. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
131277. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
131278. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
131279. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE_MASK
131280. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE__SHIFT
131281. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
131282. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
131283. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
131284. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
131285. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING_MASK
131286. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING__SHIFT
131287. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
131288. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
131289. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
131290. BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
131291. BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY__MAX_LAT_MASK
131292. BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY__MAX_LAT__SHIFT
131293. BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT__MIN_GNT_MASK
131294. BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT__MIN_GNT__SHIFT
131295. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID_MASK
131296. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID__SHIFT
131297. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR_MASK
131298. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
131299. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN_MASK
131300. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
131301. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
131302. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
131303. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
131304. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
131305. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR_MASK
131306. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
131307. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
131308. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
131309. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
131310. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
131311. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
131312. BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
131313. BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID_MASK
131314. BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID__SHIFT
131315. BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR_MASK
131316. BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
131317. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64_MASK
131318. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64__SHIFT
131319. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK_MASK
131320. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK__SHIFT
131321. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
131322. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
131323. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
131324. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
131325. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT_MASK
131326. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
131327. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN_MASK
131328. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN__SHIFT
131329. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
131330. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
131331. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
131332. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
131333. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
131334. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
131335. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
131336. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
131337. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA_MASK
131338. BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA__SHIFT
131339. BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64_MASK
131340. BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
131341. BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING_MASK
131342. BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING__SHIFT
131343. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
131344. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
131345. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
131346. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
131347. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
131348. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
131349. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
131350. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
131351. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
131352. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
131353. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
131354. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
131355. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
131356. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
131357. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
131358. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
131359. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
131360. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
131361. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
131362. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
131363. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
131364. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
131365. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
131366. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
131367. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
131368. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
131369. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
131370. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
131371. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
131372. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
131373. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
131374. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
131375. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
131376. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
131377. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
131378. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
131379. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
131380. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
131381. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
131382. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
131383. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
131384. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
131385. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
131386. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
131387. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
131388. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
131389. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
131390. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
131391. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
131392. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
131393. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__STU_MASK
131394. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__STU__SHIFT
131395. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
131396. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
131397. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
131398. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
131399. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
131400. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
131401. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID_MASK
131402. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID__SHIFT
131403. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR_MASK
131404. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
131405. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE_MASK
131406. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE__SHIFT
131407. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
131408. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
131409. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
131410. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
131411. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION_MASK
131412. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION__SHIFT
131413. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
131414. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
131415. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
131416. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
131417. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
131418. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
131419. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
131420. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
131421. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
131422. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
131423. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
131424. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
131425. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
131426. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
131427. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
131428. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
131429. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
131430. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
131431. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
131432. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
131433. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
131434. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
131435. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
131436. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
131437. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
131438. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
131439. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
131440. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
131441. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
131442. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
131443. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
131444. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
131445. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR_MASK
131446. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
131447. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR_MASK
131448. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
131449. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR_MASK
131450. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
131451. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR_MASK
131452. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
131453. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
131454. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
131455. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
131456. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
131457. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
131458. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
131459. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
131460. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
131461. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
131462. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
131463. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
131464. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
131465. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
131466. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
131467. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
131468. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
131469. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
131470. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
131471. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
131472. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
131473. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
131474. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
131475. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
131476. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
131477. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
131478. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
131479. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
131480. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
131481. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
131482. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
131483. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
131484. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
131485. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
131486. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
131487. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
131488. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
131489. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
131490. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
131491. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
131492. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
131493. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
131494. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
131495. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
131496. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
131497. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
131498. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
131499. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
131500. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
131501. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
131502. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
131503. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
131504. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
131505. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
131506. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
131507. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
131508. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
131509. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
131510. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
131511. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
131512. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
131513. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
131514. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
131515. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
131516. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
131517. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
131518. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
131519. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
131520. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
131521. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
131522. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
131523. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
131524. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
131525. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
131526. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
131527. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
131528. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
131529. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
131530. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
131531. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
131532. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
131533. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
131534. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
131535. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
131536. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
131537. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
131538. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
131539. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
131540. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
131541. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
131542. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
131543. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
131544. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
131545. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
131546. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
131547. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
131548. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
131549. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
131550. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
131551. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
131552. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
131553. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
131554. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
131555. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
131556. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
131557. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
131558. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
131559. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
131560. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
131561. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
131562. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
131563. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
131564. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
131565. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
131566. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
131567. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
131568. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
131569. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
131570. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
131571. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
131572. BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
131573. BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE_MASK
131574. BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
131575. BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID_MASK
131576. BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID__SHIFT
131577. BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID_MASK
131578. BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID__SHIFT
131579. BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR_MASK
131580. BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
131581. BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CAP2__RESERVED_MASK
131582. BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CAP2__RESERVED__SHIFT
131583. BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CNTL2__RESERVED_MASK
131584. BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CNTL2__RESERVED__SHIFT
131585. BIF_CFG_DEV0_EPF0_VF8_1_SLOT_STATUS2__RESERVED_MASK
131586. BIF_CFG_DEV0_EPF0_VF8_1_SLOT_STATUS2__RESERVED__SHIFT
131587. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST_MASK
131588. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST__SHIFT
131589. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING_MASK
131590. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING__SHIFT
131591. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE_MASK
131592. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE__SHIFT
131593. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__IMMEDIATE_READINESS_MASK
131594. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__IMMEDIATE_READINESS__SHIFT
131595. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS_MASK
131596. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS__SHIFT
131597. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
131598. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
131599. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED_MASK
131600. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
131601. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_CAP_MASK
131602. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_CAP__SHIFT
131603. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_EN_MASK
131604. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_EN__SHIFT
131605. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT_MASK
131606. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
131607. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT_MASK
131608. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
131609. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
131610. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
131611. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT_MASK
131612. BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
131613. BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS_MASK
131614. BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS__SHIFT
131615. BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID_MASK
131616. BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID__SHIFT
131617. BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_ID_MASK
131618. BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
131619. BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
131620. BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
131621. BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1__BASE_ADDR_MASK
131622. BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1__BASE_ADDR__SHIFT
131623. BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2__BASE_ADDR_MASK
131624. BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2__BASE_ADDR__SHIFT
131625. BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3__BASE_ADDR_MASK
131626. BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3__BASE_ADDR__SHIFT
131627. BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4__BASE_ADDR_MASK
131628. BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4__BASE_ADDR__SHIFT
131629. BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5__BASE_ADDR_MASK
131630. BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5__BASE_ADDR__SHIFT
131631. BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6__BASE_ADDR_MASK
131632. BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6__BASE_ADDR__SHIFT
131633. BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS__BASE_CLASS_MASK
131634. BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS__BASE_CLASS__SHIFT
131635. BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_CAP_MASK
131636. BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_CAP__SHIFT
131637. BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_COMP_MASK
131638. BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_COMP__SHIFT
131639. BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_STRT_MASK
131640. BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_STRT__SHIFT
131641. BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE__CACHE_LINE_SIZE_MASK
131642. BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
131643. BIF_CFG_DEV0_EPF0_VF8_CAP_PTR__CAP_PTR_MASK
131644. BIF_CFG_DEV0_EPF0_VF8_CAP_PTR__CAP_PTR__SHIFT
131645. BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
131646. BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
131647. BIF_CFG_DEV0_EPF0_VF8_COMMAND__AD_STEPPING_MASK
131648. BIF_CFG_DEV0_EPF0_VF8_COMMAND__AD_STEPPING__SHIFT
131649. BIF_CFG_DEV0_EPF0_VF8_COMMAND__BUS_MASTER_EN_MASK
131650. BIF_CFG_DEV0_EPF0_VF8_COMMAND__BUS_MASTER_EN__SHIFT
131651. BIF_CFG_DEV0_EPF0_VF8_COMMAND__FAST_B2B_EN_MASK
131652. BIF_CFG_DEV0_EPF0_VF8_COMMAND__FAST_B2B_EN__SHIFT
131653. BIF_CFG_DEV0_EPF0_VF8_COMMAND__INT_DIS_MASK
131654. BIF_CFG_DEV0_EPF0_VF8_COMMAND__INT_DIS__SHIFT
131655. BIF_CFG_DEV0_EPF0_VF8_COMMAND__IO_ACCESS_EN_MASK
131656. BIF_CFG_DEV0_EPF0_VF8_COMMAND__IO_ACCESS_EN__SHIFT
131657. BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_ACCESS_EN_MASK
131658. BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_ACCESS_EN__SHIFT
131659. BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
131660. BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
131661. BIF_CFG_DEV0_EPF0_VF8_COMMAND__PAL_SNOOP_EN_MASK
131662. BIF_CFG_DEV0_EPF0_VF8_COMMAND__PAL_SNOOP_EN__SHIFT
131663. BIF_CFG_DEV0_EPF0_VF8_COMMAND__PARITY_ERROR_RESPONSE_MASK
131664. BIF_CFG_DEV0_EPF0_VF8_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
131665. BIF_CFG_DEV0_EPF0_VF8_COMMAND__SERR_EN_MASK
131666. BIF_CFG_DEV0_EPF0_VF8_COMMAND__SERR_EN__SHIFT
131667. BIF_CFG_DEV0_EPF0_VF8_COMMAND__SPECIAL_CYCLE_EN_MASK
131668. BIF_CFG_DEV0_EPF0_VF8_COMMAND__SPECIAL_CYCLE_EN__SHIFT
131669. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
131670. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
131671. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
131672. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
131673. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
131674. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
131675. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
131676. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
131677. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
131678. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
131679. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
131680. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
131681. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
131682. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
131683. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
131684. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
131685. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
131686. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
131687. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
131688. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
131689. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
131690. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
131691. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__FRS_SUPPORTED_MASK
131692. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
131693. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
131694. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
131695. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LTR_SUPPORTED_MASK
131696. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
131697. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
131698. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
131699. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
131700. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
131701. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__OBFF_SUPPORTED_MASK
131702. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
131703. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
131704. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
131705. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
131706. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
131707. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
131708. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
131709. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
131710. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
131711. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
131712. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
131713. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__EXTENDED_TAG_MASK
131714. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__EXTENDED_TAG__SHIFT
131715. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__FLR_CAPABLE_MASK
131716. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__FLR_CAPABLE__SHIFT
131717. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
131718. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
131719. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
131720. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
131721. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
131722. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
131723. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__PHANTOM_FUNC_MASK
131724. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__PHANTOM_FUNC__SHIFT
131725. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
131726. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
131727. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
131728. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
131729. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
131730. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
131731. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
131732. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
131733. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
131734. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
131735. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
131736. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
131737. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
131738. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
131739. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
131740. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
131741. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
131742. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
131743. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
131744. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
131745. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__LTR_EN_MASK
131746. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__LTR_EN__SHIFT
131747. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__OBFF_EN_MASK
131748. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__OBFF_EN__SHIFT
131749. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
131750. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
131751. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
131752. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
131753. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__CORR_ERR_EN_MASK
131754. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__CORR_ERR_EN__SHIFT
131755. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
131756. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
131757. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__FATAL_ERR_EN_MASK
131758. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
131759. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__INITIATE_FLR_MASK
131760. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__INITIATE_FLR__SHIFT
131761. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
131762. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
131763. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
131764. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
131765. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
131766. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
131767. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NO_SNOOP_EN_MASK
131768. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
131769. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
131770. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
131771. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__RELAXED_ORD_EN_MASK
131772. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
131773. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__USR_REPORT_EN_MASK
131774. BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__USR_REPORT_EN__SHIFT
131775. BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID__DEVICE_ID_MASK
131776. BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID__DEVICE_ID__SHIFT
131777. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2__RESERVED_MASK
131778. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2__RESERVED__SHIFT
131779. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__AUX_PWR_MASK
131780. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__AUX_PWR__SHIFT
131781. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__CORR_ERR_MASK
131782. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__CORR_ERR__SHIFT
131783. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
131784. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
131785. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__FATAL_ERR_MASK
131786. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__FATAL_ERR__SHIFT
131787. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__NON_FATAL_ERR_MASK
131788. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
131789. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
131790. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
131791. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__USR_DETECTED_MASK
131792. BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__USR_DETECTED__SHIFT
131793. BIF_CFG_DEV0_EPF0_VF8_HEADER__DEVICE_TYPE_MASK
131794. BIF_CFG_DEV0_EPF0_VF8_HEADER__DEVICE_TYPE__SHIFT
131795. BIF_CFG_DEV0_EPF0_VF8_HEADER__HEADER_TYPE_MASK
131796. BIF_CFG_DEV0_EPF0_VF8_HEADER__HEADER_TYPE__SHIFT
131797. BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE__INTERRUPT_LINE_MASK
131798. BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
131799. BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN__INTERRUPT_PIN_MASK
131800. BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
131801. BIF_CFG_DEV0_EPF0_VF8_LATENCY__LATENCY_TIMER_MASK
131802. BIF_CFG_DEV0_EPF0_VF8_LATENCY__LATENCY_TIMER__SHIFT
131803. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
131804. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
131805. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
131806. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
131807. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
131808. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
131809. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
131810. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
131811. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
131812. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
131813. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
131814. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
131815. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
131816. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
131817. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
131818. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
131819. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
131820. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
131821. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
131822. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
131823. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L0S_EXIT_LATENCY_MASK
131824. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
131825. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L1_EXIT_LATENCY_MASK
131826. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L1_EXIT_LATENCY__SHIFT
131827. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
131828. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
131829. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_SPEED_MASK
131830. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_SPEED__SHIFT
131831. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_WIDTH_MASK
131832. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_WIDTH__SHIFT
131833. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PM_SUPPORT_MASK
131834. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PM_SUPPORT__SHIFT
131835. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PORT_NUMBER_MASK
131836. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PORT_NUMBER__SHIFT
131837. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
131838. BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
131839. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
131840. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
131841. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_SOS_MASK
131842. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
131843. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_COMPLIANCE_MASK
131844. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
131845. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
131846. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
131847. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
131848. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
131849. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
131850. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
131851. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__TARGET_LINK_SPEED_MASK
131852. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
131853. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__XMIT_MARGIN_MASK
131854. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__XMIT_MARGIN__SHIFT
131855. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
131856. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
131857. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__COMMON_CLOCK_CFG_MASK
131858. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
131859. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
131860. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
131861. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__EXTENDED_SYNC_MASK
131862. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__EXTENDED_SYNC__SHIFT
131863. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
131864. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
131865. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
131866. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
131867. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
131868. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
131869. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_DIS_MASK
131870. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_DIS__SHIFT
131871. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PM_CONTROL_MASK
131872. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PM_CONTROL__SHIFT
131873. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__READ_CPL_BOUNDARY_MASK
131874. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
131875. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__RETRAIN_LINK_MASK
131876. BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__RETRAIN_LINK__SHIFT
131877. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
131878. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
131879. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
131880. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
131881. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
131882. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
131883. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
131884. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
131885. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
131886. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
131887. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
131888. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
131889. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
131890. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
131891. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
131892. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
131893. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
131894. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
131895. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
131896. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
131897. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
131898. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
131899. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__CURRENT_LINK_SPEED_MASK
131900. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
131901. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__DL_ACTIVE_MASK
131902. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__DL_ACTIVE__SHIFT
131903. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
131904. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
131905. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
131906. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
131907. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_TRAINING_MASK
131908. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_TRAINING__SHIFT
131909. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
131910. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
131911. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__SLOT_CLOCK_CFG_MASK
131912. BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
131913. BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY__MAX_LAT_MASK
131914. BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY__MAX_LAT__SHIFT
131915. BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT__MIN_GNT_MASK
131916. BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT__MIN_GNT__SHIFT
131917. BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__CAP_ID_MASK
131918. BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__CAP_ID__SHIFT
131919. BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__NEXT_PTR_MASK
131920. BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__NEXT_PTR__SHIFT
131921. BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_EN_MASK
131922. BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_EN__SHIFT
131923. BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
131924. BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
131925. BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
131926. BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
131927. BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_BIR_MASK
131928. BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_BIR__SHIFT
131929. BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_OFFSET_MASK
131930. BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
131931. BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_BIR_MASK
131932. BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
131933. BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
131934. BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
131935. BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__CAP_ID_MASK
131936. BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__CAP_ID__SHIFT
131937. BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__NEXT_PTR_MASK
131938. BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__NEXT_PTR__SHIFT
131939. BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64__MSI_MASK_64_MASK
131940. BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64__MSI_MASK_64__SHIFT
131941. BIF_CFG_DEV0_EPF0_VF8_MSI_MASK__MSI_MASK_MASK
131942. BIF_CFG_DEV0_EPF0_VF8_MSI_MASK__MSI_MASK__SHIFT
131943. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
131944. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
131945. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
131946. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
131947. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_64BIT_MASK
131948. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_64BIT__SHIFT
131949. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EN_MASK
131950. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EN__SHIFT
131951. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
131952. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
131953. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
131954. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
131955. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
131956. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
131957. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64__MSI_DATA_64_MASK
131958. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
131959. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA__MSI_DATA_MASK
131960. BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA__MSI_DATA__SHIFT
131961. BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64__MSI_PENDING_64_MASK
131962. BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64__MSI_PENDING_64__SHIFT
131963. BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING__MSI_PENDING_MASK
131964. BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING__MSI_PENDING__SHIFT
131965. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
131966. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
131967. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
131968. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
131969. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
131970. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
131971. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
131972. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
131973. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
131974. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
131975. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
131976. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
131977. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
131978. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
131979. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
131980. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
131981. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
131982. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
131983. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
131984. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
131985. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
131986. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
131987. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
131988. BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
131989. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
131990. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
131991. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
131992. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
131993. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
131994. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
131995. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
131996. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
131997. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
131998. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
131999. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
132000. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
132001. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
132002. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
132003. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
132004. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
132005. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
132006. BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
132007. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
132008. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
132009. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
132010. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
132011. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
132012. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
132013. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL__ATC_ENABLE_MASK
132014. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
132015. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL__STU_MASK
132016. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL__STU__SHIFT
132017. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
132018. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
132019. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
132020. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
132021. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
132022. BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
132023. BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__CAP_ID_MASK
132024. BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__CAP_ID__SHIFT
132025. BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__NEXT_PTR_MASK
132026. BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__NEXT_PTR__SHIFT
132027. BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__DEVICE_TYPE_MASK
132028. BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__DEVICE_TYPE__SHIFT
132029. BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__INT_MESSAGE_NUM_MASK
132030. BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
132031. BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__SLOT_IMPLEMENTED_MASK
132032. BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
132033. BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__VERSION_MASK
132034. BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__VERSION__SHIFT
132035. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
132036. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
132037. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
132038. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
132039. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
132040. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
132041. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
132042. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
132043. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
132044. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
132045. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
132046. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
132047. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
132048. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
132049. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
132050. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
132051. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
132052. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
132053. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
132054. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
132055. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
132056. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
132057. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
132058. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
132059. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
132060. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
132061. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
132062. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
132063. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
132064. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
132065. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
132066. BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
132067. BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0__TLP_HDR_MASK
132068. BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0__TLP_HDR__SHIFT
132069. BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1__TLP_HDR_MASK
132070. BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1__TLP_HDR__SHIFT
132071. BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2__TLP_HDR_MASK
132072. BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2__TLP_HDR__SHIFT
132073. BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3__TLP_HDR_MASK
132074. BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3__TLP_HDR__SHIFT
132075. BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
132076. BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
132077. BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
132078. BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
132079. BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
132080. BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
132081. BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
132082. BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
132083. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
132084. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
132085. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
132086. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
132087. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
132088. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
132089. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
132090. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
132091. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
132092. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
132093. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
132094. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
132095. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
132096. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
132097. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
132098. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
132099. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
132100. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
132101. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
132102. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
132103. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
132104. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
132105. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
132106. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
132107. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
132108. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
132109. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
132110. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
132111. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
132112. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
132113. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
132114. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
132115. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
132116. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
132117. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
132118. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
132119. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
132120. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
132121. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
132122. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
132123. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
132124. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
132125. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
132126. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
132127. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
132128. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
132129. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
132130. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
132131. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
132132. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
132133. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
132134. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
132135. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
132136. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
132137. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
132138. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
132139. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
132140. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
132141. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
132142. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
132143. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
132144. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
132145. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
132146. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
132147. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
132148. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
132149. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
132150. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
132151. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
132152. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
132153. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
132154. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
132155. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
132156. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
132157. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
132158. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
132159. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
132160. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
132161. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
132162. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
132163. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
132164. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
132165. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
132166. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
132167. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
132168. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
132169. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
132170. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
132171. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
132172. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
132173. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
132174. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
132175. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
132176. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
132177. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
132178. BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
132179. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
132180. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
132181. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
132182. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
132183. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
132184. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
132185. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
132186. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
132187. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
132188. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
132189. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
132190. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
132191. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
132192. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
132193. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
132194. BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
132195. BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE__PROG_INTERFACE_MASK
132196. BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE__PROG_INTERFACE__SHIFT
132197. BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MAJOR_REV_ID_MASK
132198. BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MAJOR_REV_ID__SHIFT
132199. BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MINOR_REV_ID_MASK
132200. BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MINOR_REV_ID__SHIFT
132201. BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__BASE_ADDR_MASK
132202. BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__BASE_ADDR__SHIFT
132203. BIF_CFG_DEV0_EPF0_VF8_STATUS__CAP_LIST_MASK
132204. BIF_CFG_DEV0_EPF0_VF8_STATUS__CAP_LIST__SHIFT
132205. BIF_CFG_DEV0_EPF0_VF8_STATUS__DEVSEL_TIMING_MASK
132206. BIF_CFG_DEV0_EPF0_VF8_STATUS__DEVSEL_TIMING__SHIFT
132207. BIF_CFG_DEV0_EPF0_VF8_STATUS__FAST_BACK_CAPABLE_MASK
132208. BIF_CFG_DEV0_EPF0_VF8_STATUS__FAST_BACK_CAPABLE__SHIFT
132209. BIF_CFG_DEV0_EPF0_VF8_STATUS__IMMEDIATE_READINESS_MASK
132210. BIF_CFG_DEV0_EPF0_VF8_STATUS__IMMEDIATE_READINESS__SHIFT
132211. BIF_CFG_DEV0_EPF0_VF8_STATUS__INT_STATUS_MASK
132212. BIF_CFG_DEV0_EPF0_VF8_STATUS__INT_STATUS__SHIFT
132213. BIF_CFG_DEV0_EPF0_VF8_STATUS__MASTER_DATA_PARITY_ERROR_MASK
132214. BIF_CFG_DEV0_EPF0_VF8_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
132215. BIF_CFG_DEV0_EPF0_VF8_STATUS__PARITY_ERROR_DETECTED_MASK
132216. BIF_CFG_DEV0_EPF0_VF8_STATUS__PARITY_ERROR_DETECTED__SHIFT
132217. BIF_CFG_DEV0_EPF0_VF8_STATUS__PCI_66_CAP_MASK
132218. BIF_CFG_DEV0_EPF0_VF8_STATUS__PCI_66_CAP__SHIFT
132219. BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_MASTER_ABORT_MASK
132220. BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_MASTER_ABORT__SHIFT
132221. BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_TARGET_ABORT_MASK
132222. BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_TARGET_ABORT__SHIFT
132223. BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNALED_SYSTEM_ERROR_MASK
132224. BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
132225. BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNAL_TARGET_ABORT_MASK
132226. BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNAL_TARGET_ABORT__SHIFT
132227. BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS__SUB_CLASS_MASK
132228. BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS__SUB_CLASS__SHIFT
132229. BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID__VENDOR_ID_MASK
132230. BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID__VENDOR_ID__SHIFT
132231. BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
132232. BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
132233. BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
132234. BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
132235. BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR_MASK
132236. BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR__SHIFT
132237. BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR_MASK
132238. BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR__SHIFT
132239. BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR_MASK
132240. BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR__SHIFT
132241. BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR_MASK
132242. BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR__SHIFT
132243. BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR_MASK
132244. BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR__SHIFT
132245. BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR_MASK
132246. BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR__SHIFT
132247. BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS_MASK
132248. BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS__SHIFT
132249. BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP_MASK
132250. BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP__SHIFT
132251. BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP_MASK
132252. BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP__SHIFT
132253. BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT_MASK
132254. BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT__SHIFT
132255. BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
132256. BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
132257. BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR_MASK
132258. BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR__SHIFT
132259. BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
132260. BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
132261. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING_MASK
132262. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING__SHIFT
132263. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN_MASK
132264. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN__SHIFT
132265. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN_MASK
132266. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN__SHIFT
132267. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS_MASK
132268. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS__SHIFT
132269. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN_MASK
132270. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN__SHIFT
132271. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN_MASK
132272. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN__SHIFT
132273. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
132274. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
132275. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN_MASK
132276. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN__SHIFT
132277. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
132278. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
132279. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN_MASK
132280. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN__SHIFT
132281. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN_MASK
132282. BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
132283. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
132284. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
132285. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
132286. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
132287. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
132288. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
132289. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
132290. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
132291. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
132292. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
132293. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
132294. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
132295. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
132296. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
132297. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
132298. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
132299. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
132300. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
132301. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
132302. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
132303. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
132304. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
132305. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
132306. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
132307. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
132308. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
132309. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
132310. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
132311. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
132312. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
132313. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
132314. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
132315. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
132316. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
132317. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
132318. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
132319. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
132320. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
132321. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
132322. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
132323. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
132324. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
132325. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
132326. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
132327. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG_MASK
132328. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
132329. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE_MASK
132330. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
132331. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
132332. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
132333. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
132334. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
132335. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
132336. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
132337. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC_MASK
132338. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
132339. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
132340. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
132341. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
132342. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
132343. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
132344. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
132345. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
132346. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
132347. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
132348. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
132349. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
132350. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
132351. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
132352. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
132353. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
132354. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
132355. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
132356. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
132357. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
132358. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
132359. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN_MASK
132360. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN__SHIFT
132361. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN_MASK
132362. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN__SHIFT
132363. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
132364. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
132365. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
132366. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
132367. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN_MASK
132368. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
132369. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
132370. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
132371. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
132372. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
132373. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR_MASK
132374. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
132375. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
132376. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
132377. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
132378. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
132379. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
132380. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
132381. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
132382. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
132383. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
132384. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
132385. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
132386. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
132387. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN_MASK
132388. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
132389. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID_MASK
132390. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID__SHIFT
132391. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED_MASK
132392. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED__SHIFT
132393. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR_MASK
132394. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR__SHIFT
132395. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR_MASK
132396. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR__SHIFT
132397. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
132398. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
132399. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR_MASK
132400. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR__SHIFT
132401. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
132402. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
132403. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
132404. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
132405. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED_MASK
132406. BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED__SHIFT
132407. BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE_MASK
132408. BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE__SHIFT
132409. BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE_MASK
132410. BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE__SHIFT
132411. BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
132412. BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
132413. BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
132414. BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
132415. BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER_MASK
132416. BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER__SHIFT
132417. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
132418. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
132419. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
132420. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
132421. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
132422. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
132423. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
132424. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
132425. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RESERVED_MASK
132426. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RESERVED__SHIFT
132427. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
132428. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
132429. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
132430. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
132431. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
132432. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
132433. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
132434. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
132435. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
132436. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
132437. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
132438. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
132439. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
132440. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
132441. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY_MASK
132442. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
132443. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
132444. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
132445. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED_MASK
132446. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED__SHIFT
132447. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH_MASK
132448. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH__SHIFT
132449. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT_MASK
132450. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT__SHIFT
132451. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER_MASK
132452. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER__SHIFT
132453. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
132454. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
132455. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
132456. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
132457. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
132458. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
132459. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
132460. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
132461. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
132462. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
132463. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
132464. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
132465. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
132466. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
132467. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
132468. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
132469. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN_MASK
132470. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
132471. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
132472. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
132473. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
132474. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
132475. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
132476. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
132477. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC_MASK
132478. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
132479. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
132480. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
132481. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
132482. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
132483. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
132484. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
132485. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS_MASK
132486. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS__SHIFT
132487. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL_MASK
132488. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL__SHIFT
132489. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
132490. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
132491. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK_MASK
132492. BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK__SHIFT
132493. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
132494. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
132495. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
132496. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
132497. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
132498. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
132499. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
132500. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
132501. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
132502. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
132503. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
132504. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
132505. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
132506. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
132507. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
132508. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
132509. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
132510. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
132511. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
132512. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
132513. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
132514. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
132515. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
132516. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
132517. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
132518. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
132519. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
132520. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
132521. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
132522. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
132523. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
132524. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
132525. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
132526. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
132527. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE_MASK
132528. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE__SHIFT
132529. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
132530. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
132531. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
132532. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
132533. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING_MASK
132534. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING__SHIFT
132535. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
132536. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
132537. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
132538. BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
132539. BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY__MAX_LAT_MASK
132540. BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY__MAX_LAT__SHIFT
132541. BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT__MIN_GNT_MASK
132542. BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT__MIN_GNT__SHIFT
132543. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID_MASK
132544. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID__SHIFT
132545. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR_MASK
132546. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
132547. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN_MASK
132548. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
132549. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
132550. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
132551. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
132552. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
132553. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR_MASK
132554. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
132555. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
132556. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
132557. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
132558. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
132559. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
132560. BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
132561. BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID_MASK
132562. BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID__SHIFT
132563. BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR_MASK
132564. BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
132565. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64_MASK
132566. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64__SHIFT
132567. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK_MASK
132568. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK__SHIFT
132569. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
132570. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
132571. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
132572. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
132573. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT_MASK
132574. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
132575. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN_MASK
132576. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN__SHIFT
132577. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
132578. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
132579. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
132580. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
132581. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
132582. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
132583. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
132584. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
132585. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA_MASK
132586. BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA__SHIFT
132587. BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64_MASK
132588. BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
132589. BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING_MASK
132590. BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING__SHIFT
132591. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
132592. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
132593. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
132594. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
132595. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
132596. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
132597. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
132598. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
132599. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
132600. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
132601. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
132602. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
132603. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
132604. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
132605. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
132606. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
132607. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
132608. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
132609. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
132610. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
132611. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
132612. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
132613. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
132614. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
132615. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
132616. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
132617. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
132618. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
132619. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
132620. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
132621. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
132622. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
132623. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
132624. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
132625. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
132626. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
132627. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
132628. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
132629. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
132630. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
132631. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
132632. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
132633. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
132634. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
132635. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
132636. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
132637. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
132638. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
132639. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
132640. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
132641. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__STU_MASK
132642. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__STU__SHIFT
132643. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
132644. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
132645. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
132646. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
132647. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
132648. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
132649. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID_MASK
132650. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID__SHIFT
132651. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR_MASK
132652. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
132653. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE_MASK
132654. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE__SHIFT
132655. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
132656. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
132657. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
132658. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
132659. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION_MASK
132660. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION__SHIFT
132661. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
132662. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
132663. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
132664. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
132665. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
132666. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
132667. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
132668. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
132669. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
132670. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
132671. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
132672. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
132673. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
132674. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
132675. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
132676. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
132677. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
132678. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
132679. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
132680. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
132681. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
132682. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
132683. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
132684. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
132685. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
132686. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
132687. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
132688. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
132689. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
132690. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
132691. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
132692. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
132693. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR_MASK
132694. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
132695. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR_MASK
132696. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
132697. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR_MASK
132698. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
132699. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR_MASK
132700. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
132701. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
132702. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
132703. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
132704. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
132705. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
132706. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
132707. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
132708. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
132709. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
132710. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
132711. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
132712. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
132713. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
132714. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
132715. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
132716. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
132717. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
132718. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
132719. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
132720. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
132721. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
132722. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
132723. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
132724. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
132725. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
132726. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
132727. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
132728. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
132729. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
132730. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
132731. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
132732. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
132733. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
132734. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
132735. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
132736. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
132737. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
132738. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
132739. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
132740. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
132741. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
132742. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
132743. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
132744. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
132745. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
132746. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
132747. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
132748. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
132749. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
132750. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
132751. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
132752. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
132753. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
132754. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
132755. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
132756. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
132757. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
132758. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
132759. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
132760. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
132761. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
132762. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
132763. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
132764. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
132765. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
132766. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
132767. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
132768. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
132769. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
132770. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
132771. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
132772. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
132773. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
132774. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
132775. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
132776. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
132777. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
132778. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
132779. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
132780. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
132781. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
132782. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
132783. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
132784. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
132785. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
132786. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
132787. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
132788. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
132789. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
132790. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
132791. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
132792. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
132793. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
132794. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
132795. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
132796. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
132797. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
132798. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
132799. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
132800. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
132801. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
132802. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
132803. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
132804. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
132805. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
132806. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
132807. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
132808. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
132809. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
132810. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
132811. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
132812. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
132813. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
132814. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
132815. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
132816. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
132817. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
132818. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
132819. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
132820. BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
132821. BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE_MASK
132822. BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
132823. BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID_MASK
132824. BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID__SHIFT
132825. BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID_MASK
132826. BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID__SHIFT
132827. BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR_MASK
132828. BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
132829. BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2__RESERVED_MASK
132830. BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2__RESERVED__SHIFT
132831. BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2__RESERVED_MASK
132832. BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2__RESERVED__SHIFT
132833. BIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2__RESERVED_MASK
132834. BIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2__RESERVED__SHIFT
132835. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST_MASK
132836. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST__SHIFT
132837. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING_MASK
132838. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING__SHIFT
132839. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE_MASK
132840. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE__SHIFT
132841. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__IMMEDIATE_READINESS_MASK
132842. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__IMMEDIATE_READINESS__SHIFT
132843. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS_MASK
132844. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS__SHIFT
132845. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
132846. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
132847. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED_MASK
132848. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
132849. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_CAP_MASK
132850. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_CAP__SHIFT
132851. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_EN_MASK
132852. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_EN__SHIFT
132853. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT_MASK
132854. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
132855. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT_MASK
132856. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
132857. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
132858. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
132859. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT_MASK
132860. BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
132861. BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS_MASK
132862. BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS__SHIFT
132863. BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID_MASK
132864. BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID__SHIFT
132865. BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
132866. BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
132867. BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
132868. BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
132869. BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR_MASK
132870. BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR__SHIFT
132871. BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR_MASK
132872. BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR__SHIFT
132873. BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR_MASK
132874. BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR__SHIFT
132875. BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR_MASK
132876. BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR__SHIFT
132877. BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR_MASK
132878. BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR__SHIFT
132879. BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR_MASK
132880. BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR__SHIFT
132881. BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS_MASK
132882. BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS__SHIFT
132883. BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP_MASK
132884. BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP__SHIFT
132885. BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP_MASK
132886. BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP__SHIFT
132887. BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT_MASK
132888. BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT__SHIFT
132889. BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
132890. BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
132891. BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR_MASK
132892. BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR__SHIFT
132893. BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
132894. BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
132895. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING_MASK
132896. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING__SHIFT
132897. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN_MASK
132898. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN__SHIFT
132899. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN_MASK
132900. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN__SHIFT
132901. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS_MASK
132902. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS__SHIFT
132903. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN_MASK
132904. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN__SHIFT
132905. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN_MASK
132906. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN__SHIFT
132907. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
132908. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
132909. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN_MASK
132910. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN__SHIFT
132911. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
132912. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
132913. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN_MASK
132914. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN__SHIFT
132915. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN_MASK
132916. BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
132917. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
132918. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
132919. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
132920. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
132921. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
132922. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
132923. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
132924. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
132925. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
132926. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
132927. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
132928. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
132929. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
132930. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
132931. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
132932. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
132933. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
132934. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
132935. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
132936. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
132937. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
132938. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
132939. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
132940. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
132941. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
132942. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
132943. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
132944. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
132945. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
132946. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
132947. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
132948. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
132949. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
132950. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
132951. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
132952. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
132953. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
132954. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
132955. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
132956. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
132957. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
132958. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
132959. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
132960. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
132961. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG_MASK
132962. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
132963. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE_MASK
132964. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
132965. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
132966. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
132967. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
132968. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
132969. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
132970. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
132971. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC_MASK
132972. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
132973. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
132974. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
132975. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
132976. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
132977. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
132978. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
132979. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
132980. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
132981. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
132982. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
132983. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
132984. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
132985. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
132986. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
132987. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
132988. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
132989. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
132990. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
132991. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
132992. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
132993. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN_MASK
132994. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN__SHIFT
132995. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN_MASK
132996. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN__SHIFT
132997. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
132998. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
132999. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
133000. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
133001. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN_MASK
133002. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
133003. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
133004. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
133005. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
133006. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
133007. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR_MASK
133008. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
133009. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
133010. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
133011. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
133012. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
133013. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
133014. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
133015. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
133016. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
133017. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
133018. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
133019. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
133020. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
133021. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN_MASK
133022. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
133023. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID_MASK
133024. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID__SHIFT
133025. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED_MASK
133026. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED__SHIFT
133027. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR_MASK
133028. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR__SHIFT
133029. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR_MASK
133030. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR__SHIFT
133031. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
133032. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
133033. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR_MASK
133034. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR__SHIFT
133035. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
133036. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
133037. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
133038. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
133039. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED_MASK
133040. BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED__SHIFT
133041. BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE_MASK
133042. BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE__SHIFT
133043. BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE_MASK
133044. BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE__SHIFT
133045. BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
133046. BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
133047. BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
133048. BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
133049. BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER_MASK
133050. BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER__SHIFT
133051. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
133052. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
133053. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
133054. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
133055. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
133056. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
133057. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
133058. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
133059. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RESERVED_MASK
133060. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RESERVED__SHIFT
133061. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
133062. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
133063. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
133064. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
133065. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
133066. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
133067. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
133068. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
133069. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
133070. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
133071. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
133072. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
133073. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
133074. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
133075. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY_MASK
133076. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
133077. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
133078. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
133079. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED_MASK
133080. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED__SHIFT
133081. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH_MASK
133082. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH__SHIFT
133083. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT_MASK
133084. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT__SHIFT
133085. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER_MASK
133086. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER__SHIFT
133087. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
133088. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
133089. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
133090. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
133091. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
133092. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
133093. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
133094. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
133095. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
133096. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
133097. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
133098. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
133099. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
133100. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
133101. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
133102. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
133103. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN_MASK
133104. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
133105. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
133106. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
133107. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
133108. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
133109. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
133110. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
133111. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC_MASK
133112. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
133113. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
133114. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
133115. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
133116. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
133117. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
133118. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
133119. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS_MASK
133120. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS__SHIFT
133121. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL_MASK
133122. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL__SHIFT
133123. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
133124. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
133125. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK_MASK
133126. BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK__SHIFT
133127. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
133128. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
133129. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
133130. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
133131. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
133132. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
133133. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
133134. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
133135. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
133136. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
133137. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
133138. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
133139. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
133140. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
133141. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
133142. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
133143. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
133144. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
133145. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
133146. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
133147. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
133148. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
133149. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
133150. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
133151. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
133152. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
133153. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
133154. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
133155. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
133156. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
133157. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
133158. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
133159. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
133160. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
133161. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE_MASK
133162. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE__SHIFT
133163. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
133164. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
133165. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
133166. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
133167. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING_MASK
133168. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING__SHIFT
133169. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
133170. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
133171. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
133172. BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
133173. BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY__MAX_LAT_MASK
133174. BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY__MAX_LAT__SHIFT
133175. BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT__MIN_GNT_MASK
133176. BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT__MIN_GNT__SHIFT
133177. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID_MASK
133178. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID__SHIFT
133179. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR_MASK
133180. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
133181. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN_MASK
133182. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
133183. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
133184. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
133185. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
133186. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
133187. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR_MASK
133188. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
133189. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
133190. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
133191. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
133192. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
133193. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
133194. BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
133195. BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID_MASK
133196. BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID__SHIFT
133197. BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR_MASK
133198. BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
133199. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64_MASK
133200. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64__SHIFT
133201. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK_MASK
133202. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK__SHIFT
133203. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
133204. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
133205. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
133206. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
133207. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT_MASK
133208. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
133209. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN_MASK
133210. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN__SHIFT
133211. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
133212. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
133213. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
133214. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
133215. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
133216. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
133217. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
133218. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
133219. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA_MASK
133220. BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA__SHIFT
133221. BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64_MASK
133222. BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
133223. BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING_MASK
133224. BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING__SHIFT
133225. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
133226. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
133227. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
133228. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
133229. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
133230. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
133231. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
133232. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
133233. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
133234. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
133235. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
133236. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
133237. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
133238. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
133239. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
133240. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
133241. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
133242. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
133243. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
133244. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
133245. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
133246. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
133247. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
133248. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
133249. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
133250. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
133251. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
133252. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
133253. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
133254. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
133255. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
133256. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
133257. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
133258. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
133259. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
133260. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
133261. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
133262. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
133263. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
133264. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
133265. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
133266. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
133267. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
133268. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
133269. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
133270. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
133271. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
133272. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
133273. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
133274. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
133275. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__STU_MASK
133276. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__STU__SHIFT
133277. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
133278. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
133279. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
133280. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
133281. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
133282. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
133283. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID_MASK
133284. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID__SHIFT
133285. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR_MASK
133286. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
133287. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE_MASK
133288. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE__SHIFT
133289. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
133290. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
133291. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
133292. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
133293. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION_MASK
133294. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION__SHIFT
133295. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
133296. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
133297. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
133298. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
133299. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
133300. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
133301. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
133302. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
133303. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
133304. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
133305. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
133306. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
133307. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
133308. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
133309. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
133310. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
133311. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
133312. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
133313. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
133314. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
133315. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
133316. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
133317. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
133318. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
133319. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
133320. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
133321. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
133322. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
133323. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
133324. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
133325. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
133326. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
133327. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR_MASK
133328. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
133329. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR_MASK
133330. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
133331. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR_MASK
133332. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
133333. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR_MASK
133334. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
133335. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
133336. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
133337. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
133338. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
133339. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
133340. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
133341. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
133342. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
133343. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
133344. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
133345. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
133346. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
133347. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
133348. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
133349. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
133350. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
133351. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
133352. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
133353. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
133354. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
133355. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
133356. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
133357. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
133358. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
133359. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
133360. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
133361. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
133362. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
133363. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
133364. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
133365. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
133366. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
133367. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
133368. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
133369. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
133370. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
133371. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
133372. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
133373. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
133374. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
133375. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
133376. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
133377. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
133378. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
133379. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
133380. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
133381. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
133382. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
133383. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
133384. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
133385. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
133386. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
133387. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
133388. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
133389. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
133390. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
133391. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
133392. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
133393. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
133394. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
133395. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
133396. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
133397. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
133398. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
133399. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
133400. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
133401. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
133402. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
133403. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
133404. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
133405. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
133406. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
133407. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
133408. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
133409. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
133410. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
133411. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
133412. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
133413. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
133414. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
133415. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
133416. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
133417. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
133418. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
133419. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
133420. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
133421. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
133422. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
133423. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
133424. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
133425. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
133426. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
133427. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
133428. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
133429. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
133430. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
133431. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
133432. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
133433. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
133434. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
133435. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
133436. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
133437. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
133438. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
133439. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
133440. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
133441. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
133442. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
133443. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
133444. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
133445. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
133446. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
133447. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
133448. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
133449. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
133450. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
133451. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
133452. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
133453. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
133454. BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
133455. BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE_MASK
133456. BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
133457. BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID_MASK
133458. BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID__SHIFT
133459. BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID_MASK
133460. BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID__SHIFT
133461. BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR_MASK
133462. BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
133463. BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CAP2__RESERVED_MASK
133464. BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CAP2__RESERVED__SHIFT
133465. BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CNTL2__RESERVED_MASK
133466. BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CNTL2__RESERVED__SHIFT
133467. BIF_CFG_DEV0_EPF0_VF9_1_SLOT_STATUS2__RESERVED_MASK
133468. BIF_CFG_DEV0_EPF0_VF9_1_SLOT_STATUS2__RESERVED__SHIFT
133469. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST_MASK
133470. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST__SHIFT
133471. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING_MASK
133472. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING__SHIFT
133473. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE_MASK
133474. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE__SHIFT
133475. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__IMMEDIATE_READINESS_MASK
133476. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__IMMEDIATE_READINESS__SHIFT
133477. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS_MASK
133478. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS__SHIFT
133479. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
133480. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
133481. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED_MASK
133482. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
133483. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_CAP_MASK
133484. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_CAP__SHIFT
133485. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_EN_MASK
133486. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_EN__SHIFT
133487. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT_MASK
133488. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
133489. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT_MASK
133490. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
133491. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
133492. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
133493. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT_MASK
133494. BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
133495. BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS_MASK
133496. BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS__SHIFT
133497. BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID_MASK
133498. BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID__SHIFT
133499. BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_ID_MASK
133500. BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
133501. BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
133502. BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
133503. BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1__BASE_ADDR_MASK
133504. BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1__BASE_ADDR__SHIFT
133505. BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2__BASE_ADDR_MASK
133506. BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2__BASE_ADDR__SHIFT
133507. BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3__BASE_ADDR_MASK
133508. BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3__BASE_ADDR__SHIFT
133509. BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4__BASE_ADDR_MASK
133510. BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4__BASE_ADDR__SHIFT
133511. BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5__BASE_ADDR_MASK
133512. BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5__BASE_ADDR__SHIFT
133513. BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6__BASE_ADDR_MASK
133514. BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6__BASE_ADDR__SHIFT
133515. BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS__BASE_CLASS_MASK
133516. BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS__BASE_CLASS__SHIFT
133517. BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_CAP_MASK
133518. BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_CAP__SHIFT
133519. BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_COMP_MASK
133520. BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_COMP__SHIFT
133521. BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_STRT_MASK
133522. BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_STRT__SHIFT
133523. BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE__CACHE_LINE_SIZE_MASK
133524. BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
133525. BIF_CFG_DEV0_EPF0_VF9_CAP_PTR__CAP_PTR_MASK
133526. BIF_CFG_DEV0_EPF0_VF9_CAP_PTR__CAP_PTR__SHIFT
133527. BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
133528. BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
133529. BIF_CFG_DEV0_EPF0_VF9_COMMAND__AD_STEPPING_MASK
133530. BIF_CFG_DEV0_EPF0_VF9_COMMAND__AD_STEPPING__SHIFT
133531. BIF_CFG_DEV0_EPF0_VF9_COMMAND__BUS_MASTER_EN_MASK
133532. BIF_CFG_DEV0_EPF0_VF9_COMMAND__BUS_MASTER_EN__SHIFT
133533. BIF_CFG_DEV0_EPF0_VF9_COMMAND__FAST_B2B_EN_MASK
133534. BIF_CFG_DEV0_EPF0_VF9_COMMAND__FAST_B2B_EN__SHIFT
133535. BIF_CFG_DEV0_EPF0_VF9_COMMAND__INT_DIS_MASK
133536. BIF_CFG_DEV0_EPF0_VF9_COMMAND__INT_DIS__SHIFT
133537. BIF_CFG_DEV0_EPF0_VF9_COMMAND__IO_ACCESS_EN_MASK
133538. BIF_CFG_DEV0_EPF0_VF9_COMMAND__IO_ACCESS_EN__SHIFT
133539. BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_ACCESS_EN_MASK
133540. BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_ACCESS_EN__SHIFT
133541. BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
133542. BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
133543. BIF_CFG_DEV0_EPF0_VF9_COMMAND__PAL_SNOOP_EN_MASK
133544. BIF_CFG_DEV0_EPF0_VF9_COMMAND__PAL_SNOOP_EN__SHIFT
133545. BIF_CFG_DEV0_EPF0_VF9_COMMAND__PARITY_ERROR_RESPONSE_MASK
133546. BIF_CFG_DEV0_EPF0_VF9_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
133547. BIF_CFG_DEV0_EPF0_VF9_COMMAND__SERR_EN_MASK
133548. BIF_CFG_DEV0_EPF0_VF9_COMMAND__SERR_EN__SHIFT
133549. BIF_CFG_DEV0_EPF0_VF9_COMMAND__SPECIAL_CYCLE_EN_MASK
133550. BIF_CFG_DEV0_EPF0_VF9_COMMAND__SPECIAL_CYCLE_EN__SHIFT
133551. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
133552. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
133553. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
133554. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
133555. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
133556. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
133557. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
133558. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
133559. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
133560. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
133561. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
133562. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
133563. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
133564. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
133565. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
133566. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
133567. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
133568. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
133569. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
133570. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
133571. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
133572. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
133573. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__FRS_SUPPORTED_MASK
133574. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
133575. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
133576. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
133577. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LTR_SUPPORTED_MASK
133578. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
133579. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
133580. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
133581. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
133582. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
133583. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__OBFF_SUPPORTED_MASK
133584. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
133585. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
133586. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
133587. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
133588. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
133589. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
133590. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
133591. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
133592. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
133593. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
133594. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
133595. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__EXTENDED_TAG_MASK
133596. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__EXTENDED_TAG__SHIFT
133597. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__FLR_CAPABLE_MASK
133598. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__FLR_CAPABLE__SHIFT
133599. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
133600. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
133601. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
133602. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
133603. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
133604. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
133605. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__PHANTOM_FUNC_MASK
133606. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__PHANTOM_FUNC__SHIFT
133607. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
133608. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
133609. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
133610. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
133611. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
133612. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
133613. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
133614. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
133615. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
133616. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
133617. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
133618. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
133619. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
133620. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
133621. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
133622. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
133623. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
133624. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
133625. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
133626. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
133627. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__LTR_EN_MASK
133628. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__LTR_EN__SHIFT
133629. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__OBFF_EN_MASK
133630. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__OBFF_EN__SHIFT
133631. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
133632. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
133633. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
133634. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
133635. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__CORR_ERR_EN_MASK
133636. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__CORR_ERR_EN__SHIFT
133637. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
133638. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
133639. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__FATAL_ERR_EN_MASK
133640. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
133641. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__INITIATE_FLR_MASK
133642. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__INITIATE_FLR__SHIFT
133643. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
133644. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
133645. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
133646. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
133647. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
133648. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
133649. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NO_SNOOP_EN_MASK
133650. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
133651. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
133652. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
133653. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__RELAXED_ORD_EN_MASK
133654. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
133655. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__USR_REPORT_EN_MASK
133656. BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__USR_REPORT_EN__SHIFT
133657. BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID__DEVICE_ID_MASK
133658. BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID__DEVICE_ID__SHIFT
133659. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2__RESERVED_MASK
133660. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2__RESERVED__SHIFT
133661. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__AUX_PWR_MASK
133662. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__AUX_PWR__SHIFT
133663. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__CORR_ERR_MASK
133664. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__CORR_ERR__SHIFT
133665. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
133666. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
133667. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__FATAL_ERR_MASK
133668. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__FATAL_ERR__SHIFT
133669. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__NON_FATAL_ERR_MASK
133670. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
133671. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
133672. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
133673. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__USR_DETECTED_MASK
133674. BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__USR_DETECTED__SHIFT
133675. BIF_CFG_DEV0_EPF0_VF9_HEADER__DEVICE_TYPE_MASK
133676. BIF_CFG_DEV0_EPF0_VF9_HEADER__DEVICE_TYPE__SHIFT
133677. BIF_CFG_DEV0_EPF0_VF9_HEADER__HEADER_TYPE_MASK
133678. BIF_CFG_DEV0_EPF0_VF9_HEADER__HEADER_TYPE__SHIFT
133679. BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE__INTERRUPT_LINE_MASK
133680. BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
133681. BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN__INTERRUPT_PIN_MASK
133682. BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
133683. BIF_CFG_DEV0_EPF0_VF9_LATENCY__LATENCY_TIMER_MASK
133684. BIF_CFG_DEV0_EPF0_VF9_LATENCY__LATENCY_TIMER__SHIFT
133685. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
133686. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
133687. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
133688. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
133689. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
133690. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
133691. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
133692. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
133693. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
133694. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
133695. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
133696. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
133697. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
133698. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
133699. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
133700. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
133701. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
133702. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
133703. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
133704. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
133705. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L0S_EXIT_LATENCY_MASK
133706. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
133707. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L1_EXIT_LATENCY_MASK
133708. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L1_EXIT_LATENCY__SHIFT
133709. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
133710. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
133711. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_SPEED_MASK
133712. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_SPEED__SHIFT
133713. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_WIDTH_MASK
133714. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_WIDTH__SHIFT
133715. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PM_SUPPORT_MASK
133716. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PM_SUPPORT__SHIFT
133717. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PORT_NUMBER_MASK
133718. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PORT_NUMBER__SHIFT
133719. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
133720. BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
133721. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
133722. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
133723. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_SOS_MASK
133724. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
133725. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_COMPLIANCE_MASK
133726. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
133727. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
133728. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
133729. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
133730. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
133731. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
133732. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
133733. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__TARGET_LINK_SPEED_MASK
133734. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
133735. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__XMIT_MARGIN_MASK
133736. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__XMIT_MARGIN__SHIFT
133737. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
133738. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
133739. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__COMMON_CLOCK_CFG_MASK
133740. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
133741. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
133742. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
133743. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__EXTENDED_SYNC_MASK
133744. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__EXTENDED_SYNC__SHIFT
133745. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
133746. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
133747. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
133748. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
133749. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
133750. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
133751. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_DIS_MASK
133752. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_DIS__SHIFT
133753. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PM_CONTROL_MASK
133754. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PM_CONTROL__SHIFT
133755. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__READ_CPL_BOUNDARY_MASK
133756. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
133757. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__RETRAIN_LINK_MASK
133758. BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__RETRAIN_LINK__SHIFT
133759. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
133760. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
133761. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
133762. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
133763. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
133764. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
133765. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
133766. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
133767. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
133768. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
133769. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
133770. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
133771. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
133772. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
133773. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
133774. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
133775. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
133776. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
133777. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
133778. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
133779. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
133780. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
133781. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__CURRENT_LINK_SPEED_MASK
133782. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
133783. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__DL_ACTIVE_MASK
133784. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__DL_ACTIVE__SHIFT
133785. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
133786. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
133787. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
133788. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
133789. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_TRAINING_MASK
133790. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_TRAINING__SHIFT
133791. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
133792. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
133793. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__SLOT_CLOCK_CFG_MASK
133794. BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
133795. BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY__MAX_LAT_MASK
133796. BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY__MAX_LAT__SHIFT
133797. BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT__MIN_GNT_MASK
133798. BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT__MIN_GNT__SHIFT
133799. BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__CAP_ID_MASK
133800. BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__CAP_ID__SHIFT
133801. BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__NEXT_PTR_MASK
133802. BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__NEXT_PTR__SHIFT
133803. BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_EN_MASK
133804. BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_EN__SHIFT
133805. BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
133806. BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
133807. BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
133808. BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
133809. BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_BIR_MASK
133810. BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_BIR__SHIFT
133811. BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_OFFSET_MASK
133812. BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
133813. BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_BIR_MASK
133814. BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
133815. BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
133816. BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
133817. BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__CAP_ID_MASK
133818. BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__CAP_ID__SHIFT
133819. BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__NEXT_PTR_MASK
133820. BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__NEXT_PTR__SHIFT
133821. BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64__MSI_MASK_64_MASK
133822. BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64__MSI_MASK_64__SHIFT
133823. BIF_CFG_DEV0_EPF0_VF9_MSI_MASK__MSI_MASK_MASK
133824. BIF_CFG_DEV0_EPF0_VF9_MSI_MASK__MSI_MASK__SHIFT
133825. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
133826. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
133827. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
133828. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
133829. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_64BIT_MASK
133830. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_64BIT__SHIFT
133831. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EN_MASK
133832. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EN__SHIFT
133833. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
133834. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
133835. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
133836. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
133837. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
133838. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
133839. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64__MSI_DATA_64_MASK
133840. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
133841. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA__MSI_DATA_MASK
133842. BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA__MSI_DATA__SHIFT
133843. BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64__MSI_PENDING_64_MASK
133844. BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64__MSI_PENDING_64__SHIFT
133845. BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING__MSI_PENDING_MASK
133846. BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING__MSI_PENDING__SHIFT
133847. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
133848. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
133849. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
133850. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
133851. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
133852. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
133853. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
133854. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
133855. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
133856. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
133857. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
133858. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
133859. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
133860. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
133861. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
133862. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
133863. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
133864. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
133865. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
133866. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
133867. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
133868. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
133869. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
133870. BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
133871. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
133872. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
133873. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
133874. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
133875. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
133876. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
133877. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
133878. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
133879. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
133880. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
133881. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
133882. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
133883. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
133884. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
133885. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
133886. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
133887. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
133888. BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
133889. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
133890. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
133891. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
133892. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
133893. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
133894. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
133895. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL__ATC_ENABLE_MASK
133896. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
133897. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL__STU_MASK
133898. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL__STU__SHIFT
133899. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
133900. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
133901. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
133902. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
133903. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
133904. BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
133905. BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__CAP_ID_MASK
133906. BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__CAP_ID__SHIFT
133907. BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__NEXT_PTR_MASK
133908. BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__NEXT_PTR__SHIFT
133909. BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__DEVICE_TYPE_MASK
133910. BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__DEVICE_TYPE__SHIFT
133911. BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__INT_MESSAGE_NUM_MASK
133912. BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
133913. BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__SLOT_IMPLEMENTED_MASK
133914. BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
133915. BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__VERSION_MASK
133916. BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__VERSION__SHIFT
133917. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
133918. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
133919. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
133920. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
133921. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
133922. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
133923. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
133924. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
133925. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
133926. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
133927. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
133928. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
133929. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
133930. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
133931. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
133932. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
133933. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
133934. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
133935. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
133936. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
133937. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
133938. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
133939. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
133940. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
133941. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
133942. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
133943. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
133944. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
133945. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
133946. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
133947. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
133948. BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
133949. BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0__TLP_HDR_MASK
133950. BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0__TLP_HDR__SHIFT
133951. BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1__TLP_HDR_MASK
133952. BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1__TLP_HDR__SHIFT
133953. BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2__TLP_HDR_MASK
133954. BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2__TLP_HDR__SHIFT
133955. BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3__TLP_HDR_MASK
133956. BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3__TLP_HDR__SHIFT
133957. BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
133958. BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
133959. BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
133960. BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
133961. BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
133962. BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
133963. BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
133964. BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
133965. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
133966. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
133967. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
133968. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
133969. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
133970. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
133971. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
133972. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
133973. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
133974. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
133975. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
133976. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
133977. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
133978. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
133979. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
133980. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
133981. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
133982. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
133983. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
133984. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
133985. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
133986. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
133987. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
133988. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
133989. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
133990. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
133991. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
133992. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
133993. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
133994. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
133995. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
133996. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
133997. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
133998. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
133999. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
134000. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
134001. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
134002. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
134003. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
134004. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
134005. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
134006. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
134007. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
134008. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
134009. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
134010. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
134011. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
134012. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
134013. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
134014. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
134015. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
134016. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
134017. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
134018. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
134019. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
134020. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
134021. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
134022. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
134023. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
134024. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
134025. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
134026. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
134027. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
134028. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
134029. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
134030. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
134031. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
134032. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
134033. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
134034. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
134035. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
134036. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
134037. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
134038. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
134039. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
134040. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
134041. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
134042. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
134043. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
134044. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
134045. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
134046. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
134047. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
134048. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
134049. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
134050. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
134051. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
134052. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
134053. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
134054. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
134055. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
134056. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
134057. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
134058. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
134059. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
134060. BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
134061. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
134062. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
134063. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
134064. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
134065. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
134066. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
134067. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
134068. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
134069. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
134070. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
134071. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
134072. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
134073. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
134074. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
134075. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
134076. BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
134077. BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE__PROG_INTERFACE_MASK
134078. BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE__PROG_INTERFACE__SHIFT
134079. BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MAJOR_REV_ID_MASK
134080. BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MAJOR_REV_ID__SHIFT
134081. BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MINOR_REV_ID_MASK
134082. BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MINOR_REV_ID__SHIFT
134083. BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__BASE_ADDR_MASK
134084. BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__BASE_ADDR__SHIFT
134085. BIF_CFG_DEV0_EPF0_VF9_STATUS__CAP_LIST_MASK
134086. BIF_CFG_DEV0_EPF0_VF9_STATUS__CAP_LIST__SHIFT
134087. BIF_CFG_DEV0_EPF0_VF9_STATUS__DEVSEL_TIMING_MASK
134088. BIF_CFG_DEV0_EPF0_VF9_STATUS__DEVSEL_TIMING__SHIFT
134089. BIF_CFG_DEV0_EPF0_VF9_STATUS__FAST_BACK_CAPABLE_MASK
134090. BIF_CFG_DEV0_EPF0_VF9_STATUS__FAST_BACK_CAPABLE__SHIFT
134091. BIF_CFG_DEV0_EPF0_VF9_STATUS__IMMEDIATE_READINESS_MASK
134092. BIF_CFG_DEV0_EPF0_VF9_STATUS__IMMEDIATE_READINESS__SHIFT
134093. BIF_CFG_DEV0_EPF0_VF9_STATUS__INT_STATUS_MASK
134094. BIF_CFG_DEV0_EPF0_VF9_STATUS__INT_STATUS__SHIFT
134095. BIF_CFG_DEV0_EPF0_VF9_STATUS__MASTER_DATA_PARITY_ERROR_MASK
134096. BIF_CFG_DEV0_EPF0_VF9_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
134097. BIF_CFG_DEV0_EPF0_VF9_STATUS__PARITY_ERROR_DETECTED_MASK
134098. BIF_CFG_DEV0_EPF0_VF9_STATUS__PARITY_ERROR_DETECTED__SHIFT
134099. BIF_CFG_DEV0_EPF0_VF9_STATUS__PCI_66_CAP_MASK
134100. BIF_CFG_DEV0_EPF0_VF9_STATUS__PCI_66_CAP__SHIFT
134101. BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_MASTER_ABORT_MASK
134102. BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_MASTER_ABORT__SHIFT
134103. BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_TARGET_ABORT_MASK
134104. BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_TARGET_ABORT__SHIFT
134105. BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNALED_SYSTEM_ERROR_MASK
134106. BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
134107. BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNAL_TARGET_ABORT_MASK
134108. BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNAL_TARGET_ABORT__SHIFT
134109. BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS__SUB_CLASS_MASK
134110. BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS__SUB_CLASS__SHIFT
134111. BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID__VENDOR_ID_MASK
134112. BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID__VENDOR_ID__SHIFT
134113. BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
134114. BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
134115. BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
134116. BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
134117. BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
134118. BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
134119. BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
134120. BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
134121. BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK
134122. BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT
134123. BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK
134124. BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT
134125. BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK
134126. BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT
134127. BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK
134128. BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT
134129. BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK
134130. BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT
134131. BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK
134132. BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT
134133. BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK
134134. BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT
134135. BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK
134136. BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT
134137. BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK
134138. BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT
134139. BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK
134140. BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT
134141. BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
134142. BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
134143. BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK
134144. BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT
134145. BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
134146. BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
134147. BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK
134148. BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT
134149. BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK
134150. BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT
134151. BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK
134152. BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT
134153. BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK
134154. BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT
134155. BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK
134156. BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT
134157. BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK
134158. BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT
134159. BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
134160. BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
134161. BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK
134162. BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT
134163. BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
134164. BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
134165. BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK
134166. BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT
134167. BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK
134168. BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
134169. BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK
134170. BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT
134171. BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK
134172. BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT
134173. BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK
134174. BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK
134175. BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT
134176. BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT
134177. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
134178. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
134179. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
134180. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
134181. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
134182. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
134183. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
134184. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
134185. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
134186. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
134187. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
134188. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
134189. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
134190. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
134191. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
134192. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
134193. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
134194. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
134195. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
134196. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
134197. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
134198. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
134199. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
134200. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
134201. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
134202. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
134203. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
134204. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
134205. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
134206. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
134207. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
134208. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
134209. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
134210. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
134211. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
134212. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
134213. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
134214. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
134215. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
134216. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
134217. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
134218. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
134219. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
134220. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
134221. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK
134222. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
134223. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK
134224. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
134225. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
134226. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
134227. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
134228. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
134229. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
134230. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
134231. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK
134232. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
134233. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
134234. BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
134235. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
134236. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
134237. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
134238. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
134239. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
134240. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
134241. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
134242. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
134243. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
134244. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
134245. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
134246. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
134247. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
134248. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
134249. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
134250. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
134251. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
134252. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
134253. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK
134254. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT
134255. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK
134256. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT
134257. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
134258. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
134259. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
134260. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
134261. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK
134262. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
134263. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
134264. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
134265. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
134266. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
134267. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK
134268. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
134269. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
134270. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
134271. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
134272. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
134273. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
134274. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
134275. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
134276. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
134277. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
134278. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
134279. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
134280. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
134281. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK
134282. BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
134283. BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK
134284. BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT
134285. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK
134286. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT
134287. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK
134288. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT
134289. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK
134290. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT
134291. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
134292. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
134293. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK
134294. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT
134295. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
134296. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
134297. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
134298. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
134299. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK
134300. BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT
134301. BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK
134302. BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT
134303. BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK
134304. BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT
134305. BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
134306. BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
134307. BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
134308. BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
134309. BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK
134310. BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT
134311. BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK
134312. BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT
134313. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK
134314. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT
134315. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK
134316. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT
134317. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK
134318. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT
134319. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK
134320. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT
134321. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK
134322. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT
134323. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK
134324. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT
134325. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK
134326. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT
134327. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK
134328. BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT
134329. BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK
134330. BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT
134331. BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK
134332. BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT
134333. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK
134334. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT
134335. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK
134336. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT
134337. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK
134338. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT
134339. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK
134340. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT
134341. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK
134342. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT
134343. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK
134344. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT
134345. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK
134346. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT
134347. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK
134348. BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT
134349. BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK
134350. BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT
134351. BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK
134352. BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT
134353. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK
134354. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT
134355. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK
134356. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT
134357. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK
134358. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT
134359. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK
134360. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT
134361. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK
134362. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT
134363. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK
134364. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT
134365. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK
134366. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT
134367. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK
134368. BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT
134369. BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK
134370. BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT
134371. BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK
134372. BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT
134373. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK
134374. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT
134375. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK
134376. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT
134377. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK
134378. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT
134379. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK
134380. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT
134381. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK
134382. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT
134383. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK
134384. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT
134385. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK
134386. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT
134387. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK
134388. BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT
134389. BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK
134390. BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT
134391. BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK
134392. BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT
134393. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK
134394. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT
134395. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK
134396. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT
134397. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK
134398. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT
134399. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK
134400. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT
134401. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK
134402. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT
134403. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK
134404. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT
134405. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK
134406. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT
134407. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK
134408. BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT
134409. BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK
134410. BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT
134411. BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK
134412. BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT
134413. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK
134414. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT
134415. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK
134416. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT
134417. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK
134418. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT
134419. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK
134420. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT
134421. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK
134422. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT
134423. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK
134424. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT
134425. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK
134426. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT
134427. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK
134428. BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT
134429. BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK
134430. BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT
134431. BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK
134432. BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT
134433. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK
134434. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT
134435. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK
134436. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT
134437. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK
134438. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT
134439. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK
134440. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT
134441. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK
134442. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT
134443. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK
134444. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT
134445. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK
134446. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT
134447. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK
134448. BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT
134449. BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK
134450. BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT
134451. BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK
134452. BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT
134453. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK
134454. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT
134455. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK
134456. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT
134457. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK
134458. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT
134459. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK
134460. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT
134461. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK
134462. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT
134463. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK
134464. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT
134465. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK
134466. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT
134467. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK
134468. BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT
134469. BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK
134470. BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT
134471. BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK
134472. BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT
134473. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK
134474. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT
134475. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK
134476. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT
134477. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK
134478. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT
134479. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK
134480. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT
134481. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK
134482. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT
134483. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK
134484. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT
134485. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK
134486. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT
134487. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK
134488. BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT
134489. BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK
134490. BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT
134491. BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK
134492. BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT
134493. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK
134494. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT
134495. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK
134496. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT
134497. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK
134498. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT
134499. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK
134500. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT
134501. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK
134502. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT
134503. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK
134504. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT
134505. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK
134506. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT
134507. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK
134508. BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT
134509. BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK
134510. BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT
134511. BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK
134512. BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT
134513. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK
134514. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT
134515. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK
134516. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT
134517. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK
134518. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT
134519. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK
134520. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT
134521. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK
134522. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT
134523. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK
134524. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT
134525. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK
134526. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT
134527. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK
134528. BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT
134529. BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK
134530. BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT
134531. BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK
134532. BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT
134533. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK
134534. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT
134535. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK
134536. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT
134537. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK
134538. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT
134539. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK
134540. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT
134541. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK
134542. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT
134543. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK
134544. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT
134545. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK
134546. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT
134547. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK
134548. BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT
134549. BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK
134550. BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT
134551. BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK
134552. BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT
134553. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK
134554. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT
134555. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK
134556. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT
134557. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK
134558. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT
134559. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK
134560. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT
134561. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK
134562. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT
134563. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK
134564. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT
134565. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK
134566. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT
134567. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK
134568. BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT
134569. BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK
134570. BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT
134571. BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK
134572. BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT
134573. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK
134574. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT
134575. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK
134576. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT
134577. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK
134578. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT
134579. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK
134580. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT
134581. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK
134582. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT
134583. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK
134584. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT
134585. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK
134586. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT
134587. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK
134588. BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT
134589. BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK
134590. BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT
134591. BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK
134592. BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT
134593. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK
134594. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT
134595. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK
134596. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT
134597. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK
134598. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT
134599. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK
134600. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT
134601. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK
134602. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT
134603. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK
134604. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT
134605. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK
134606. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT
134607. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK
134608. BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT
134609. BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK
134610. BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT
134611. BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK
134612. BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT
134613. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK
134614. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT
134615. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK
134616. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT
134617. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK
134618. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT
134619. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK
134620. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT
134621. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK
134622. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT
134623. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK
134624. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT
134625. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK
134626. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT
134627. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK
134628. BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT
134629. BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK
134630. BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT
134631. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
134632. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
134633. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
134634. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
134635. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
134636. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
134637. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
134638. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
134639. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RESERVED_MASK
134640. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RESERVED__SHIFT
134641. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
134642. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
134643. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
134644. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
134645. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
134646. BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
134647. BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED_MASK
134648. BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED__SHIFT
134649. BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
134650. BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
134651. BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
134652. BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
134653. BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
134654. BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
134655. BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
134656. BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
134657. BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK
134658. BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
134659. BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
134660. BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
134661. BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK
134662. BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT
134663. BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK
134664. BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT
134665. BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK
134666. BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT
134667. BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK
134668. BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT
134669. BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
134670. BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
134671. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
134672. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
134673. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
134674. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
134675. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
134676. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
134677. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
134678. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
134679. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
134680. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
134681. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
134682. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
134683. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
134684. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
134685. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK
134686. BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
134687. BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED_MASK
134688. BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED__SHIFT
134689. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
134690. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
134691. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
134692. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
134693. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
134694. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
134695. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK
134696. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
134697. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
134698. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
134699. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
134700. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
134701. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
134702. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
134703. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK
134704. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT
134705. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK
134706. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT
134707. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
134708. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
134709. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK
134710. BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT
134711. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
134712. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
134713. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
134714. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
134715. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
134716. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
134717. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
134718. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
134719. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
134720. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
134721. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
134722. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
134723. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
134724. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
134725. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
134726. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
134727. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
134728. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
134729. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
134730. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
134731. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
134732. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
134733. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
134734. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
134735. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
134736. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
134737. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
134738. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
134739. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
134740. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
134741. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
134742. BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
134743. BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK
134744. BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT
134745. BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK
134746. BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT
134747. BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK
134748. BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT
134749. BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK
134750. BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT
134751. BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK
134752. BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT
134753. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
134754. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
134755. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK
134756. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT
134757. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
134758. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
134759. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
134760. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
134761. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK
134762. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT
134763. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
134764. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
134765. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
134766. BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
134767. BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK
134768. BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT
134769. BIF_CFG_DEV0_EPF1_0_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
134770. BIF_CFG_DEV0_EPF1_0_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
134771. BIF_CFG_DEV0_EPF1_0_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
134772. BIF_CFG_DEV0_EPF1_0_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
134773. BIF_CFG_DEV0_EPF1_0_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
134774. BIF_CFG_DEV0_EPF1_0_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
134775. BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK
134776. BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT
134777. BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK
134778. BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT
134779. BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK
134780. BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT
134781. BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK
134782. BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT
134783. BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK
134784. BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT
134785. BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK
134786. BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT
134787. BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK
134788. BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
134789. BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK
134790. BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
134791. BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
134792. BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
134793. BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
134794. BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
134795. BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK
134796. BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
134797. BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
134798. BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
134799. BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
134800. BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
134801. BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
134802. BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
134803. BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK
134804. BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT
134805. BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK
134806. BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
134807. BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK
134808. BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT
134809. BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK
134810. BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT
134811. BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
134812. BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
134813. BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
134814. BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
134815. BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK
134816. BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
134817. BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK
134818. BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT
134819. BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
134820. BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
134821. BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
134822. BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
134823. BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
134824. BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
134825. BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
134826. BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
134827. BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK
134828. BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT
134829. BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK
134830. BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
134831. BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK
134832. BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT
134833. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
134834. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
134835. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
134836. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
134837. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
134838. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
134839. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
134840. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
134841. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
134842. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
134843. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
134844. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
134845. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
134846. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
134847. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
134848. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
134849. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
134850. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
134851. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
134852. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
134853. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
134854. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
134855. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
134856. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
134857. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
134858. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
134859. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
134860. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
134861. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
134862. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
134863. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
134864. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
134865. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
134866. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
134867. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
134868. BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
134869. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
134870. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
134871. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
134872. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
134873. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
134874. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
134875. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
134876. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
134877. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
134878. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
134879. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
134880. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
134881. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
134882. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
134883. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
134884. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
134885. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
134886. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
134887. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
134888. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
134889. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
134890. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
134891. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
134892. BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
134893. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
134894. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
134895. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
134896. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
134897. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
134898. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
134899. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
134900. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
134901. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
134902. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
134903. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
134904. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
134905. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
134906. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
134907. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
134908. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
134909. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
134910. BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
134911. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
134912. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
134913. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
134914. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
134915. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
134916. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
134917. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK
134918. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
134919. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU_MASK
134920. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU__SHIFT
134921. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
134922. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
134923. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
134924. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
134925. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
134926. BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
134927. BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
134928. BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
134929. BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK
134930. BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
134931. BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK
134932. BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
134933. BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
134934. BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
134935. BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
134936. BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
134937. BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK
134938. BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
134939. BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK
134940. BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
134941. BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
134942. BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
134943. BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
134944. BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
134945. BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK
134946. BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
134947. BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK
134948. BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
134949. BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
134950. BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
134951. BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
134952. BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
134953. BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK
134954. BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
134955. BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK
134956. BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
134957. BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
134958. BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
134959. BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
134960. BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
134961. BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK
134962. BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
134963. BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK
134964. BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
134965. BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
134966. BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
134967. BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
134968. BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
134969. BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK
134970. BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
134971. BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK
134972. BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
134973. BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
134974. BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
134975. BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
134976. BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
134977. BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
134978. BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
134979. BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
134980. BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
134981. BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK
134982. BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT
134983. BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK
134984. BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
134985. BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK
134986. BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT
134987. BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
134988. BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
134989. BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
134990. BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
134991. BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK
134992. BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT
134993. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
134994. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
134995. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
134996. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
134997. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
134998. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
134999. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
135000. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
135001. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
135002. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
135003. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
135004. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
135005. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
135006. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
135007. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
135008. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
135009. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
135010. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
135011. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
135012. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
135013. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
135014. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
135015. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
135016. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
135017. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
135018. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
135019. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
135020. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
135021. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
135022. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
135023. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
135024. BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
135025. BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
135026. BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
135027. BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
135028. BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
135029. BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
135030. BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
135031. BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
135032. BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
135033. BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
135034. BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
135035. BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK
135036. BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT
135037. BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK
135038. BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT
135039. BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK
135040. BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT
135041. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
135042. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
135043. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
135044. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
135045. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
135046. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
135047. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
135048. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
135049. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
135050. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
135051. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
135052. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
135053. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
135054. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
135055. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
135056. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
135057. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
135058. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
135059. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
135060. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
135061. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
135062. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
135063. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
135064. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
135065. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
135066. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
135067. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
135068. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
135069. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
135070. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
135071. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
135072. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
135073. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
135074. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
135075. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
135076. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
135077. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
135078. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
135079. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
135080. BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
135081. BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK
135082. BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
135083. BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK
135084. BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
135085. BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK
135086. BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
135087. BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK
135088. BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
135089. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135090. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135091. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135092. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135093. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
135094. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
135095. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135096. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135097. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135098. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135099. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135100. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135101. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135102. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135103. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
135104. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
135105. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135106. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135107. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135108. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135109. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135110. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135111. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135112. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135113. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
135114. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
135115. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135116. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135117. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135118. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135119. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135120. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135121. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135122. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135123. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
135124. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
135125. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135126. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135127. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135128. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135129. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135130. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135131. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135132. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135133. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
135134. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
135135. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135136. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135137. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135138. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135139. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135140. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135141. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135142. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135143. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
135144. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
135145. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135146. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135147. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135148. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135149. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135150. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135151. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135152. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135153. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
135154. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
135155. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135156. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135157. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135158. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135159. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135160. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135161. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135162. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135163. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
135164. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
135165. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135166. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135167. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135168. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135169. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135170. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135171. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135172. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135173. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
135174. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
135175. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135176. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135177. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135178. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135179. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135180. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135181. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135182. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135183. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
135184. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
135185. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135186. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135187. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135188. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135189. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135190. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135191. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135192. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135193. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
135194. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
135195. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135196. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135197. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135198. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135199. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135200. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135201. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135202. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135203. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
135204. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
135205. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135206. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135207. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135208. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135209. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135210. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135211. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135212. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135213. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
135214. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
135215. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135216. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135217. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135218. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135219. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135220. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135221. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135222. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135223. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
135224. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
135225. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135226. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135227. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135228. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135229. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135230. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135231. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135232. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135233. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
135234. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
135235. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135236. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135237. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135238. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135239. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
135240. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
135241. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
135242. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
135243. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
135244. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
135245. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
135246. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
135247. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
135248. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
135249. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
135250. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
135251. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
135252. BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
135253. BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
135254. BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
135255. BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
135256. BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
135257. BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
135258. BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
135259. BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__RESERVED_MASK
135260. BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__RESERVED__SHIFT
135261. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
135262. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
135263. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
135264. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
135265. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
135266. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
135267. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
135268. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
135269. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
135270. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
135271. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
135272. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
135273. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
135274. BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
135275. BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
135276. BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
135277. BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
135278. BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
135279. BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
135280. BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
135281. BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
135282. BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
135283. BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
135284. BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
135285. BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
135286. BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
135287. BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
135288. BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
135289. BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
135290. BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
135291. BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
135292. BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
135293. BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
135294. BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
135295. BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
135296. BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
135297. BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK
135298. BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
135299. BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK
135300. BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT
135301. BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK
135302. BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT
135303. BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
135304. BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
135305. BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
135306. BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
135307. BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
135308. BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
135309. BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
135310. BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
135311. BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
135312. BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
135313. BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
135314. BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
135315. BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK
135316. BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT
135317. BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK
135318. BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT
135319. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK
135320. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT
135321. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK
135322. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT
135323. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK
135324. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT
135325. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK
135326. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT
135327. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK
135328. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT
135329. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK
135330. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT
135331. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK
135332. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT
135333. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK
135334. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT
135335. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK
135336. BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT
135337. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
135338. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
135339. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
135340. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
135341. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
135342. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
135343. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK
135344. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
135345. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
135346. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
135347. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
135348. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
135349. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
135350. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
135351. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
135352. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
135353. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
135354. BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
135355. BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
135356. BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
135357. BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
135358. BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
135359. BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
135360. BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
135361. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
135362. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
135363. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
135364. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
135365. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
135366. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
135367. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
135368. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
135369. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
135370. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
135371. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
135372. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
135373. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
135374. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
135375. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
135376. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
135377. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
135378. BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
135379. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
135380. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
135381. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
135382. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
135383. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
135384. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
135385. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
135386. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
135387. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
135388. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
135389. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
135390. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
135391. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
135392. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
135393. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK
135394. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
135395. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
135396. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
135397. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
135398. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
135399. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
135400. BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
135401. BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
135402. BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
135403. BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
135404. BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
135405. BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
135406. BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
135407. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK
135408. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT
135409. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK
135410. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT
135411. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK
135412. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT
135413. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
135414. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
135415. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK
135416. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT
135417. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK
135418. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT
135419. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK
135420. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT
135421. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK
135422. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT
135423. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK
135424. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT
135425. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK
135426. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
135427. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK
135428. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT
135429. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK
135430. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT
135431. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK
135432. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT
135433. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK
135434. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT
135435. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK
135436. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT
135437. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK
135438. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT
135439. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK
135440. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT
135441. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK
135442. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT
135443. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK
135444. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT
135445. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK
135446. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT
135447. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK
135448. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT
135449. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK
135450. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT
135451. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK
135452. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT
135453. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK
135454. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT
135455. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK
135456. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT
135457. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK
135458. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT
135459. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK
135460. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT
135461. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK
135462. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT
135463. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK
135464. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT
135465. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK
135466. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT
135467. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK
135468. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT
135469. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK
135470. BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT
135471. BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
135472. BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
135473. BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
135474. BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
135475. BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
135476. BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
135477. BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
135478. BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
135479. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
135480. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
135481. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
135482. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
135483. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
135484. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
135485. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
135486. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
135487. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
135488. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
135489. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
135490. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
135491. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
135492. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
135493. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
135494. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
135495. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
135496. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
135497. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
135498. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
135499. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
135500. BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
135501. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
135502. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
135503. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
135504. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
135505. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
135506. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
135507. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
135508. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
135509. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
135510. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
135511. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
135512. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
135513. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
135514. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
135515. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
135516. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
135517. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
135518. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
135519. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
135520. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
135521. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
135522. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
135523. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
135524. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
135525. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
135526. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
135527. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
135528. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
135529. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
135530. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
135531. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
135532. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
135533. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
135534. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
135535. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
135536. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
135537. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
135538. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
135539. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
135540. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
135541. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
135542. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
135543. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
135544. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
135545. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
135546. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
135547. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
135548. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
135549. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
135550. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
135551. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
135552. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
135553. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
135554. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
135555. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
135556. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
135557. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
135558. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
135559. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
135560. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
135561. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
135562. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
135563. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
135564. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
135565. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
135566. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
135567. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
135568. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
135569. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
135570. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
135571. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
135572. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
135573. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
135574. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
135575. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
135576. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
135577. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
135578. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
135579. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
135580. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
135581. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
135582. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
135583. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
135584. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
135585. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
135586. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
135587. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
135588. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
135589. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
135590. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
135591. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
135592. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
135593. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
135594. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
135595. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
135596. BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
135597. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
135598. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
135599. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
135600. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
135601. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
135602. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
135603. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
135604. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
135605. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
135606. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
135607. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
135608. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
135609. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
135610. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
135611. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
135612. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
135613. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
135614. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
135615. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
135616. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
135617. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
135618. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
135619. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
135620. BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
135621. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
135622. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
135623. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
135624. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
135625. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
135626. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
135627. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
135628. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
135629. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
135630. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
135631. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
135632. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
135633. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
135634. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
135635. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
135636. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
135637. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
135638. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
135639. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
135640. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
135641. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
135642. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
135643. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
135644. BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
135645. BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
135646. BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
135647. BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
135648. BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
135649. BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
135650. BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
135651. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
135652. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
135653. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
135654. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
135655. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK
135656. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT
135657. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK
135658. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT
135659. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK
135660. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT
135661. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
135662. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
135663. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
135664. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
135665. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
135666. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
135667. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK
135668. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT
135669. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK
135670. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT
135671. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK
135672. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT
135673. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK
135674. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT
135675. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK
135676. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT
135677. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK
135678. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT
135679. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK
135680. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT
135681. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK
135682. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT
135683. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK
135684. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT
135685. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK
135686. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT
135687. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK
135688. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT
135689. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK
135690. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT
135691. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK
135692. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT
135693. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK
135694. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT
135695. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK
135696. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT
135697. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK
135698. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT
135699. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK
135700. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT
135701. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK
135702. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT
135703. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK
135704. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT
135705. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK
135706. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT
135707. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK
135708. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT
135709. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK
135710. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT
135711. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK
135712. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT
135713. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK
135714. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT
135715. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK
135716. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT
135717. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK
135718. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT
135719. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK
135720. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT
135721. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK
135722. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT
135723. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK
135724. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT
135725. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK
135726. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT
135727. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK
135728. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT
135729. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK
135730. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT
135731. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK
135732. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT
135733. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK
135734. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT
135735. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK
135736. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT
135737. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK
135738. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT
135739. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK
135740. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT
135741. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK
135742. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT
135743. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK
135744. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT
135745. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK
135746. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT
135747. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK
135748. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT
135749. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK
135750. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT
135751. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK
135752. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT
135753. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK
135754. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT
135755. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK
135756. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT
135757. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK
135758. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT
135759. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK
135760. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT
135761. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK
135762. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT
135763. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK
135764. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT
135765. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK
135766. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT
135767. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK
135768. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT
135769. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK
135770. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT
135771. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK
135772. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT
135773. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK
135774. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT
135775. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK
135776. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT
135777. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK
135778. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT
135779. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK
135780. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT
135781. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK
135782. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT
135783. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK
135784. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT
135785. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK
135786. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT
135787. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK
135788. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT
135789. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK
135790. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT
135791. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK
135792. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT
135793. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK
135794. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT
135795. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK
135796. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT
135797. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK
135798. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT
135799. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK
135800. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT
135801. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK
135802. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT
135803. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK
135804. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT
135805. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK
135806. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT
135807. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK
135808. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT
135809. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK
135810. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT
135811. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK
135812. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT
135813. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK
135814. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT
135815. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK
135816. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT
135817. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK
135818. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT
135819. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK
135820. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT
135821. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK
135822. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT
135823. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK
135824. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT
135825. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK
135826. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT
135827. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK
135828. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT
135829. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK
135830. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT
135831. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK
135832. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT
135833. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK
135834. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT
135835. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK
135836. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT
135837. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK
135838. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT
135839. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK
135840. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT
135841. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK
135842. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT
135843. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK
135844. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT
135845. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK
135846. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT
135847. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK
135848. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT
135849. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK
135850. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT
135851. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK
135852. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT
135853. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK
135854. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT
135855. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK
135856. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT
135857. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK
135858. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT
135859. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK
135860. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT
135861. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK
135862. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT
135863. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK
135864. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT
135865. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK
135866. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT
135867. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK
135868. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT
135869. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK
135870. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
135871. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK
135872. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
135873. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK
135874. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT
135875. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK
135876. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT
135877. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK
135878. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT
135879. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK
135880. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT
135881. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK
135882. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
135883. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK
135884. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
135885. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK
135886. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT
135887. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK
135888. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT
135889. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK
135890. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
135891. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK
135892. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
135893. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK
135894. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT
135895. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK
135896. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT
135897. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK
135898. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
135899. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK
135900. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
135901. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK
135902. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT
135903. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK
135904. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT
135905. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK
135906. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT
135907. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK
135908. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT
135909. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK
135910. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT
135911. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK
135912. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT
135913. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK
135914. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT
135915. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK
135916. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT
135917. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK
135918. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT
135919. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK
135920. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT
135921. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK
135922. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT
135923. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK
135924. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT
135925. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK
135926. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT
135927. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK
135928. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT
135929. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK
135930. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT
135931. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK
135932. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT
135933. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK
135934. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT
135935. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK
135936. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT
135937. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK
135938. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT
135939. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK
135940. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT
135941. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK
135942. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT
135943. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK
135944. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT
135945. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK
135946. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT
135947. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK
135948. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT
135949. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK
135950. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT
135951. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK
135952. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT
135953. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK
135954. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT
135955. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK
135956. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT
135957. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK
135958. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT
135959. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK
135960. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT
135961. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK
135962. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT
135963. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK
135964. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT
135965. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK
135966. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT
135967. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK
135968. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT
135969. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK
135970. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT
135971. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK
135972. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT
135973. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK
135974. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT
135975. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK
135976. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT
135977. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK
135978. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT
135979. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK
135980. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT
135981. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK
135982. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT
135983. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK
135984. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT
135985. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK
135986. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT
135987. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK
135988. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT
135989. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK
135990. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT
135991. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK
135992. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT
135993. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK
135994. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT
135995. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK
135996. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT
135997. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK
135998. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT
135999. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK
136000. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT
136001. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK
136002. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT
136003. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK
136004. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT
136005. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK
136006. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT
136007. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK
136008. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT
136009. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK
136010. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT
136011. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK
136012. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT
136013. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK
136014. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT
136015. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK
136016. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT
136017. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK
136018. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT
136019. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK
136020. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT
136021. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK
136022. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT
136023. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK
136024. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT
136025. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK
136026. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT
136027. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK
136028. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT
136029. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK
136030. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT
136031. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK
136032. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT
136033. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK
136034. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT
136035. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK
136036. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT
136037. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK
136038. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT
136039. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK
136040. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT
136041. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK
136042. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT
136043. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK
136044. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT
136045. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK
136046. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT
136047. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK
136048. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT
136049. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK
136050. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT
136051. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK
136052. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT
136053. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK
136054. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT
136055. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK
136056. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT
136057. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK
136058. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT
136059. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK
136060. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT
136061. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK
136062. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT
136063. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK
136064. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT
136065. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK
136066. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT
136067. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK
136068. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT
136069. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK
136070. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT
136071. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK
136072. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT
136073. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK
136074. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT
136075. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK
136076. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT
136077. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK
136078. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT
136079. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK
136080. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT
136081. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK
136082. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT
136083. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK
136084. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT
136085. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK
136086. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT
136087. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK
136088. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT
136089. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK
136090. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT
136091. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK
136092. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT
136093. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK
136094. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT
136095. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK
136096. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT
136097. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK
136098. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT
136099. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK
136100. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT
136101. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK
136102. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT
136103. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK
136104. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT
136105. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK
136106. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT
136107. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK
136108. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT
136109. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK
136110. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT
136111. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
136112. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
136113. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
136114. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
136115. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
136116. BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
136117. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK
136118. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
136119. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK
136120. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT
136121. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK
136122. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT
136123. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK
136124. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT
136125. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK
136126. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
136127. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK
136128. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT
136129. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK
136130. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT
136131. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK
136132. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT
136133. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK
136134. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
136135. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK
136136. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT
136137. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK
136138. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT
136139. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK
136140. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT
136141. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK
136142. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
136143. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK
136144. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT
136145. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK
136146. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT
136147. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK
136148. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT
136149. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK
136150. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
136151. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK
136152. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT
136153. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK
136154. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT
136155. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK
136156. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT
136157. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK
136158. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
136159. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK
136160. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT
136161. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK
136162. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT
136163. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK
136164. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT
136165. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK
136166. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
136167. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK
136168. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
136169. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
136170. BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
136171. BIF_CFG_DEV0_EPF1_0_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
136172. BIF_CFG_DEV0_EPF1_0_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
136173. BIF_CFG_DEV0_EPF1_0_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
136174. BIF_CFG_DEV0_EPF1_0_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
136175. BIF_CFG_DEV0_EPF1_0_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
136176. BIF_CFG_DEV0_EPF1_0_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
136177. BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK
136178. BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT
136179. BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK
136180. BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
136181. BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK
136182. BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT
136183. BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK
136184. BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT
136185. BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK
136186. BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT
136187. BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
136188. BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
136189. BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
136190. BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
136191. BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK
136192. BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT
136193. BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK
136194. BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT
136195. BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK
136196. BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT
136197. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
136198. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
136199. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
136200. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
136201. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
136202. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
136203. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
136204. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
136205. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
136206. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
136207. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK
136208. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT
136209. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK
136210. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
136211. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK
136212. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
136213. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK
136214. BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
136215. BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK
136216. BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
136217. BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK
136218. BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT
136219. BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK
136220. BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT
136221. BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK
136222. BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
136223. BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK
136224. BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT
136225. BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK
136226. BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT
136227. BIF_CFG_DEV0_EPF1_0_SLOT_CAP2__RESERVED_MASK
136228. BIF_CFG_DEV0_EPF1_0_SLOT_CAP2__RESERVED__SHIFT
136229. BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2__RESERVED_MASK
136230. BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2__RESERVED__SHIFT
136231. BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2__RESERVED_MASK
136232. BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2__RESERVED__SHIFT
136233. BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK
136234. BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT
136235. BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK
136236. BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT
136237. BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK
136238. BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT
136239. BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK
136240. BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT
136241. BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK
136242. BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT
136243. BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
136244. BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
136245. BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK
136246. BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
136247. BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK
136248. BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT
136249. BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN_MASK
136250. BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN__SHIFT
136251. BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK
136252. BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
136253. BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK
136254. BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
136255. BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
136256. BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
136257. BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK
136258. BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
136259. BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK
136260. BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT
136261. BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK
136262. BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT
136263. BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK
136264. BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT
136265. BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK
136266. BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
136267. BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK
136268. BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT
136269. BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
136270. BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
136271. BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
136272. BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
136273. BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
136274. BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
136275. BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
136276. BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
136277. BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK
136278. BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT
136279. BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK
136280. BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT
136281. BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK
136282. BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT
136283. BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK
136284. BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT
136285. BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK
136286. BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT
136287. BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK
136288. BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT
136289. BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS_MASK
136290. BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT
136291. BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP_MASK
136292. BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP__SHIFT
136293. BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP_MASK
136294. BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP__SHIFT
136295. BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT_MASK
136296. BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT__SHIFT
136297. BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
136298. BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
136299. BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR_MASK
136300. BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR__SHIFT
136301. BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
136302. BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
136303. BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING_MASK
136304. BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING__SHIFT
136305. BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN_MASK
136306. BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT
136307. BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN_MASK
136308. BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT
136309. BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS_MASK
136310. BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS__SHIFT
136311. BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN_MASK
136312. BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT
136313. BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK
136314. BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT
136315. BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
136316. BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
136317. BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK
136318. BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT
136319. BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
136320. BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
136321. BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN_MASK
136322. BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT
136323. BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK
136324. BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
136325. BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK
136326. BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT
136327. BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK
136328. BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT
136329. BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK
136330. BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK
136331. BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT
136332. BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT
136333. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
136334. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
136335. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
136336. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
136337. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
136338. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
136339. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
136340. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
136341. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
136342. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
136343. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
136344. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
136345. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
136346. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
136347. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
136348. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
136349. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
136350. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
136351. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
136352. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
136353. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
136354. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
136355. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
136356. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
136357. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
136358. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
136359. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
136360. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
136361. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
136362. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
136363. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
136364. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
136365. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
136366. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
136367. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
136368. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
136369. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
136370. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
136371. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
136372. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
136373. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
136374. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
136375. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
136376. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
136377. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK
136378. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
136379. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK
136380. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
136381. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
136382. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
136383. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
136384. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
136385. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
136386. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
136387. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK
136388. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
136389. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
136390. BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
136391. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
136392. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
136393. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
136394. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
136395. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
136396. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
136397. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
136398. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
136399. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
136400. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
136401. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
136402. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
136403. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
136404. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
136405. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
136406. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
136407. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
136408. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
136409. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK
136410. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT
136411. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK
136412. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT
136413. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
136414. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
136415. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
136416. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
136417. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK
136418. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
136419. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
136420. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
136421. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
136422. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
136423. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK
136424. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
136425. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
136426. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
136427. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
136428. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
136429. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
136430. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
136431. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
136432. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
136433. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
136434. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
136435. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
136436. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
136437. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK
136438. BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
136439. BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID_MASK
136440. BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT
136441. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED_MASK
136442. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT
136443. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK
136444. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT
136445. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK
136446. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT
136447. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
136448. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
136449. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK
136450. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT
136451. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
136452. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
136453. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
136454. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
136455. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK
136456. BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT
136457. BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE_MASK
136458. BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE__SHIFT
136459. BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE_MASK
136460. BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE__SHIFT
136461. BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
136462. BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
136463. BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
136464. BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
136465. BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK
136466. BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT
136467. BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK
136468. BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT
136469. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK
136470. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT
136471. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK
136472. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT
136473. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK
136474. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT
136475. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK
136476. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT
136477. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK
136478. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT
136479. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK
136480. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT
136481. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK
136482. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT
136483. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK
136484. BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT
136485. BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK
136486. BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT
136487. BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK
136488. BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT
136489. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK
136490. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT
136491. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK
136492. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT
136493. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK
136494. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT
136495. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK
136496. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT
136497. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK
136498. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT
136499. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK
136500. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT
136501. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK
136502. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT
136503. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK
136504. BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT
136505. BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK
136506. BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT
136507. BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK
136508. BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT
136509. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK
136510. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT
136511. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK
136512. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT
136513. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK
136514. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT
136515. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK
136516. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT
136517. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK
136518. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT
136519. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK
136520. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT
136521. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK
136522. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT
136523. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK
136524. BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT
136525. BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK
136526. BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT
136527. BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK
136528. BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT
136529. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK
136530. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT
136531. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK
136532. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT
136533. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK
136534. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT
136535. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK
136536. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT
136537. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK
136538. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT
136539. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK
136540. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT
136541. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK
136542. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT
136543. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK
136544. BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT
136545. BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK
136546. BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT
136547. BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK
136548. BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT
136549. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK
136550. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT
136551. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK
136552. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT
136553. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK
136554. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT
136555. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK
136556. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT
136557. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK
136558. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT
136559. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK
136560. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT
136561. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK
136562. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT
136563. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK
136564. BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT
136565. BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK
136566. BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT
136567. BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK
136568. BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT
136569. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK
136570. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT
136571. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK
136572. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT
136573. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK
136574. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT
136575. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK
136576. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT
136577. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK
136578. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT
136579. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK
136580. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT
136581. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK
136582. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT
136583. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK
136584. BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT
136585. BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK
136586. BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT
136587. BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK
136588. BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT
136589. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK
136590. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT
136591. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK
136592. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT
136593. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK
136594. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT
136595. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK
136596. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT
136597. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK
136598. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT
136599. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK
136600. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT
136601. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK
136602. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT
136603. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK
136604. BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT
136605. BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK
136606. BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT
136607. BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK
136608. BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT
136609. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK
136610. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT
136611. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK
136612. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT
136613. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK
136614. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT
136615. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK
136616. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT
136617. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK
136618. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT
136619. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK
136620. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT
136621. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK
136622. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT
136623. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK
136624. BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT
136625. BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK
136626. BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT
136627. BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK
136628. BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT
136629. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK
136630. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT
136631. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK
136632. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT
136633. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK
136634. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT
136635. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK
136636. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT
136637. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK
136638. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT
136639. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK
136640. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT
136641. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK
136642. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT
136643. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK
136644. BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT
136645. BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK
136646. BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT
136647. BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK
136648. BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT
136649. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK
136650. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT
136651. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK
136652. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT
136653. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK
136654. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT
136655. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK
136656. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT
136657. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK
136658. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT
136659. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK
136660. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT
136661. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK
136662. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT
136663. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK
136664. BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT
136665. BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK
136666. BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT
136667. BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK
136668. BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT
136669. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK
136670. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT
136671. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK
136672. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT
136673. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK
136674. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT
136675. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK
136676. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT
136677. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK
136678. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT
136679. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK
136680. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT
136681. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK
136682. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT
136683. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK
136684. BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT
136685. BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK
136686. BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT
136687. BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK
136688. BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT
136689. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK
136690. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT
136691. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK
136692. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT
136693. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK
136694. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT
136695. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK
136696. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT
136697. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK
136698. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT
136699. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK
136700. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT
136701. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK
136702. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT
136703. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK
136704. BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT
136705. BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK
136706. BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT
136707. BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK
136708. BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT
136709. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK
136710. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT
136711. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK
136712. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT
136713. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK
136714. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT
136715. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK
136716. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT
136717. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK
136718. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT
136719. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK
136720. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT
136721. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK
136722. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT
136723. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK
136724. BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT
136725. BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK
136726. BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT
136727. BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK
136728. BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT
136729. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK
136730. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT
136731. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK
136732. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT
136733. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK
136734. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT
136735. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK
136736. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT
136737. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK
136738. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT
136739. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK
136740. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT
136741. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK
136742. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT
136743. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK
136744. BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT
136745. BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK
136746. BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT
136747. BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK
136748. BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT
136749. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK
136750. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT
136751. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK
136752. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT
136753. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK
136754. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT
136755. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK
136756. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT
136757. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK
136758. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT
136759. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK
136760. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT
136761. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK
136762. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT
136763. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK
136764. BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT
136765. BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK
136766. BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT
136767. BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK
136768. BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT
136769. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK
136770. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT
136771. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK
136772. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT
136773. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK
136774. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT
136775. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK
136776. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT
136777. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK
136778. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT
136779. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK
136780. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT
136781. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK
136782. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT
136783. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK
136784. BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT
136785. BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER_MASK
136786. BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT
136787. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
136788. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
136789. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
136790. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
136791. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
136792. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
136793. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
136794. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
136795. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RESERVED_MASK
136796. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RESERVED__SHIFT
136797. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
136798. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
136799. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
136800. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
136801. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
136802. BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
136803. BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT__RESERVED_MASK
136804. BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT__RESERVED__SHIFT
136805. BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
136806. BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
136807. BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
136808. BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
136809. BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
136810. BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
136811. BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
136812. BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
136813. BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK
136814. BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
136815. BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
136816. BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
136817. BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED_MASK
136818. BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT
136819. BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH_MASK
136820. BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT
136821. BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT_MASK
136822. BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT
136823. BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER_MASK
136824. BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT
136825. BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
136826. BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
136827. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
136828. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
136829. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
136830. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
136831. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
136832. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
136833. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
136834. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
136835. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
136836. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
136837. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
136838. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
136839. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
136840. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
136841. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK
136842. BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
136843. BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT__RESERVED_MASK
136844. BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT__RESERVED__SHIFT
136845. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
136846. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
136847. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
136848. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
136849. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
136850. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
136851. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK
136852. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
136853. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
136854. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
136855. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
136856. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
136857. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
136858. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
136859. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS_MASK
136860. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT
136861. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL_MASK
136862. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT
136863. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
136864. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
136865. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK
136866. BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT
136867. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
136868. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
136869. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
136870. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
136871. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
136872. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
136873. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
136874. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
136875. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
136876. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
136877. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
136878. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
136879. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
136880. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
136881. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
136882. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
136883. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
136884. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
136885. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
136886. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
136887. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
136888. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
136889. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
136890. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
136891. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
136892. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
136893. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
136894. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
136895. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
136896. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
136897. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
136898. BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
136899. BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK
136900. BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT
136901. BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK
136902. BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT
136903. BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK
136904. BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT
136905. BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK
136906. BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT
136907. BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK
136908. BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT
136909. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
136910. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
136911. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK
136912. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT
136913. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
136914. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
136915. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
136916. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
136917. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK
136918. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT
136919. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
136920. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
136921. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
136922. BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
136923. BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK
136924. BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT
136925. BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK
136926. BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT
136927. BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK
136928. BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT
136929. BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK
136930. BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT
136931. BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT_MASK
136932. BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT
136933. BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT_MASK
136934. BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT
136935. BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK
136936. BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT
136937. BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK
136938. BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
136939. BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK
136940. BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
136941. BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
136942. BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
136943. BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
136944. BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
136945. BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK
136946. BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
136947. BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
136948. BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
136949. BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
136950. BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
136951. BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
136952. BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
136953. BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK
136954. BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT
136955. BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK
136956. BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
136957. BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK
136958. BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT
136959. BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK_MASK
136960. BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK__SHIFT
136961. BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
136962. BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
136963. BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
136964. BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
136965. BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK
136966. BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
136967. BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK
136968. BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT
136969. BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
136970. BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
136971. BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
136972. BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
136973. BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
136974. BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
136975. BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
136976. BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
136977. BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK
136978. BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT
136979. BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK
136980. BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
136981. BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING_MASK
136982. BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT
136983. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
136984. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
136985. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
136986. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
136987. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
136988. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
136989. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
136990. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
136991. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
136992. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
136993. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
136994. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
136995. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
136996. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
136997. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
136998. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
136999. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
137000. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
137001. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
137002. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
137003. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
137004. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
137005. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
137006. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
137007. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
137008. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
137009. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
137010. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
137011. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
137012. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
137013. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
137014. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
137015. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
137016. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
137017. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
137018. BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
137019. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
137020. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
137021. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
137022. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
137023. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
137024. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
137025. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
137026. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
137027. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
137028. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
137029. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
137030. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
137031. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
137032. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
137033. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
137034. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
137035. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
137036. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
137037. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
137038. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
137039. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
137040. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
137041. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
137042. BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
137043. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
137044. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
137045. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
137046. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
137047. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
137048. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
137049. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
137050. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
137051. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
137052. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
137053. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
137054. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
137055. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
137056. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
137057. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
137058. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
137059. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
137060. BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
137061. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
137062. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
137063. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
137064. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
137065. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
137066. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
137067. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
137068. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
137069. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU_MASK
137070. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU__SHIFT
137071. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
137072. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
137073. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
137074. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
137075. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
137076. BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
137077. BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
137078. BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
137079. BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK
137080. BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
137081. BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK
137082. BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
137083. BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
137084. BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
137085. BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
137086. BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
137087. BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK
137088. BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
137089. BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK
137090. BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
137091. BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
137092. BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
137093. BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
137094. BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
137095. BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK
137096. BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
137097. BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK
137098. BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
137099. BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
137100. BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
137101. BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
137102. BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
137103. BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK
137104. BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
137105. BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK
137106. BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
137107. BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
137108. BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
137109. BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
137110. BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
137111. BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK
137112. BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
137113. BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK
137114. BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
137115. BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
137116. BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
137117. BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
137118. BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
137119. BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK
137120. BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
137121. BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK
137122. BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
137123. BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
137124. BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
137125. BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
137126. BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
137127. BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
137128. BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
137129. BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
137130. BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
137131. BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK
137132. BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT
137133. BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK
137134. BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
137135. BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK
137136. BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT
137137. BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
137138. BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
137139. BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
137140. BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
137141. BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION_MASK
137142. BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION__SHIFT
137143. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
137144. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
137145. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
137146. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
137147. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
137148. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
137149. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
137150. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
137151. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
137152. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
137153. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
137154. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
137155. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
137156. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
137157. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
137158. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
137159. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
137160. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
137161. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
137162. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
137163. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
137164. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
137165. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
137166. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
137167. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
137168. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
137169. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
137170. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
137171. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
137172. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
137173. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
137174. BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
137175. BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
137176. BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
137177. BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
137178. BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
137179. BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
137180. BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
137181. BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
137182. BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
137183. BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
137184. BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
137185. BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK
137186. BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT
137187. BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK
137188. BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT
137189. BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK
137190. BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT
137191. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
137192. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
137193. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
137194. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
137195. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
137196. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
137197. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
137198. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
137199. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
137200. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
137201. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
137202. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
137203. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
137204. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
137205. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
137206. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
137207. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
137208. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
137209. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
137210. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
137211. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
137212. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
137213. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
137214. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
137215. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
137216. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
137217. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
137218. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
137219. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
137220. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
137221. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
137222. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
137223. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
137224. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
137225. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
137226. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
137227. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
137228. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
137229. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
137230. BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
137231. BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK
137232. BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
137233. BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK
137234. BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
137235. BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK
137236. BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
137237. BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK
137238. BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
137239. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137240. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137241. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137242. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137243. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
137244. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
137245. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137246. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137247. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137248. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137249. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137250. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137251. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137252. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137253. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
137254. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
137255. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137256. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137257. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137258. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137259. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137260. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137261. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137262. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137263. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
137264. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
137265. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137266. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137267. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137268. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137269. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137270. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137271. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137272. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137273. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
137274. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
137275. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137276. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137277. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137278. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137279. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137280. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137281. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137282. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137283. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
137284. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
137285. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137286. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137287. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137288. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137289. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137290. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137291. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137292. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137293. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
137294. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
137295. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137296. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137297. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137298. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137299. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137300. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137301. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137302. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137303. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
137304. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
137305. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137306. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137307. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137308. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137309. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137310. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137311. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137312. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137313. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
137314. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
137315. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137316. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137317. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137318. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137319. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137320. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137321. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137322. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137323. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
137324. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
137325. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137326. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137327. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137328. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137329. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137330. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137331. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137332. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137333. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
137334. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
137335. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137336. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137337. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137338. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137339. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137340. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137341. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137342. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137343. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
137344. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
137345. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137346. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137347. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137348. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137349. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137350. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137351. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137352. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137353. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
137354. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
137355. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137356. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137357. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137358. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137359. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137360. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137361. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137362. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137363. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
137364. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
137365. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137366. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137367. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137368. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137369. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137370. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137371. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137372. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137373. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
137374. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
137375. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137376. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137377. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137378. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137379. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137380. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137381. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137382. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137383. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
137384. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
137385. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137386. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137387. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137388. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137389. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
137390. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
137391. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
137392. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
137393. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
137394. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
137395. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
137396. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
137397. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
137398. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
137399. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
137400. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
137401. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
137402. BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
137403. BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
137404. BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
137405. BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
137406. BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
137407. BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
137408. BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
137409. BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__RESERVED_MASK
137410. BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__RESERVED__SHIFT
137411. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
137412. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
137413. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
137414. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
137415. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
137416. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
137417. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
137418. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
137419. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
137420. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
137421. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
137422. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
137423. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
137424. BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
137425. BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
137426. BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
137427. BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
137428. BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
137429. BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
137430. BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
137431. BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
137432. BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
137433. BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
137434. BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
137435. BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
137436. BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
137437. BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
137438. BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
137439. BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
137440. BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
137441. BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
137442. BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
137443. BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
137444. BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
137445. BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
137446. BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
137447. BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK
137448. BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
137449. BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK
137450. BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT
137451. BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE_MASK
137452. BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT
137453. BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
137454. BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
137455. BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
137456. BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
137457. BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
137458. BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
137459. BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
137460. BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
137461. BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
137462. BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
137463. BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
137464. BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
137465. BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK
137466. BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT
137467. BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK
137468. BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT
137469. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK
137470. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT
137471. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK
137472. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT
137473. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK
137474. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT
137475. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK
137476. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT
137477. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK
137478. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT
137479. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK
137480. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT
137481. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK
137482. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT
137483. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK
137484. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT
137485. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK
137486. BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT
137487. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
137488. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
137489. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
137490. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
137491. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
137492. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
137493. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK
137494. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
137495. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
137496. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
137497. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
137498. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
137499. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
137500. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
137501. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
137502. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
137503. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
137504. BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
137505. BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
137506. BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
137507. BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
137508. BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
137509. BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
137510. BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
137511. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
137512. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
137513. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
137514. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
137515. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
137516. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
137517. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
137518. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
137519. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
137520. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
137521. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
137522. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
137523. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
137524. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
137525. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
137526. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
137527. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
137528. BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
137529. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
137530. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
137531. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
137532. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
137533. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
137534. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
137535. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
137536. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
137537. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
137538. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
137539. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
137540. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
137541. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
137542. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
137543. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK
137544. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
137545. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
137546. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
137547. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
137548. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
137549. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
137550. BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
137551. BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
137552. BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
137553. BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
137554. BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
137555. BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
137556. BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
137557. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK
137558. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT
137559. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK
137560. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT
137561. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK
137562. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT
137563. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
137564. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
137565. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK
137566. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT
137567. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK
137568. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT
137569. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK
137570. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT
137571. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK
137572. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT
137573. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK
137574. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT
137575. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK
137576. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
137577. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK
137578. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT
137579. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK
137580. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT
137581. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK
137582. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT
137583. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK
137584. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT
137585. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK
137586. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT
137587. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK
137588. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT
137589. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK
137590. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT
137591. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK
137592. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT
137593. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK
137594. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT
137595. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK
137596. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT
137597. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK
137598. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT
137599. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK
137600. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT
137601. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK
137602. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT
137603. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK
137604. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT
137605. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK
137606. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT
137607. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK
137608. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT
137609. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK
137610. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT
137611. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK
137612. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT
137613. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK
137614. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT
137615. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK
137616. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT
137617. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK
137618. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT
137619. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK
137620. BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT
137621. BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
137622. BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
137623. BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
137624. BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
137625. BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
137626. BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
137627. BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
137628. BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
137629. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
137630. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
137631. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
137632. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
137633. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
137634. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
137635. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
137636. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
137637. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
137638. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
137639. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
137640. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
137641. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
137642. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
137643. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
137644. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
137645. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
137646. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
137647. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
137648. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
137649. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
137650. BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
137651. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
137652. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
137653. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
137654. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
137655. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
137656. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
137657. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
137658. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
137659. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
137660. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
137661. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
137662. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
137663. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
137664. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
137665. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
137666. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
137667. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
137668. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
137669. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
137670. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
137671. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
137672. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
137673. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
137674. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
137675. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
137676. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
137677. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
137678. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
137679. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
137680. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
137681. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
137682. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
137683. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
137684. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
137685. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
137686. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
137687. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
137688. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
137689. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
137690. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
137691. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
137692. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
137693. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
137694. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
137695. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
137696. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
137697. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
137698. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
137699. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
137700. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
137701. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
137702. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
137703. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
137704. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
137705. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
137706. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
137707. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
137708. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
137709. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
137710. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
137711. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
137712. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
137713. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
137714. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
137715. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
137716. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
137717. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
137718. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
137719. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
137720. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
137721. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
137722. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
137723. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
137724. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
137725. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
137726. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
137727. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
137728. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
137729. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
137730. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
137731. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
137732. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
137733. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
137734. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
137735. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
137736. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
137737. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
137738. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
137739. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
137740. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
137741. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
137742. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
137743. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
137744. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
137745. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
137746. BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
137747. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
137748. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
137749. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
137750. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
137751. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
137752. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
137753. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
137754. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
137755. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
137756. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
137757. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
137758. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
137759. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
137760. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
137761. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
137762. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
137763. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
137764. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
137765. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
137766. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
137767. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
137768. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
137769. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
137770. BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
137771. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
137772. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
137773. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
137774. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
137775. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
137776. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
137777. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
137778. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
137779. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
137780. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
137781. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
137782. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
137783. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
137784. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
137785. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
137786. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
137787. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
137788. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
137789. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
137790. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
137791. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
137792. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
137793. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
137794. BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
137795. BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
137796. BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
137797. BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
137798. BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
137799. BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
137800. BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
137801. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
137802. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
137803. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
137804. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
137805. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK
137806. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT
137807. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK
137808. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT
137809. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK
137810. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT
137811. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
137812. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
137813. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
137814. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
137815. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
137816. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
137817. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK
137818. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT
137819. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK
137820. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT
137821. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK
137822. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT
137823. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK
137824. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT
137825. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK
137826. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT
137827. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK
137828. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT
137829. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK
137830. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT
137831. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK
137832. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT
137833. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK
137834. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT
137835. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK
137836. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT
137837. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK
137838. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT
137839. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK
137840. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT
137841. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK
137842. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT
137843. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK
137844. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT
137845. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK
137846. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT
137847. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK
137848. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT
137849. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK
137850. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT
137851. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK
137852. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT
137853. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK
137854. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT
137855. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK
137856. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT
137857. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK
137858. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT
137859. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK
137860. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT
137861. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK
137862. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT
137863. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK
137864. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT
137865. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK
137866. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT
137867. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK
137868. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT
137869. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK
137870. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT
137871. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK
137872. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT
137873. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK
137874. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT
137875. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK
137876. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT
137877. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK
137878. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT
137879. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK
137880. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT
137881. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK
137882. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT
137883. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK
137884. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT
137885. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK
137886. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT
137887. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK
137888. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT
137889. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK
137890. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT
137891. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK
137892. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT
137893. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK
137894. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT
137895. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK
137896. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT
137897. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK
137898. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT
137899. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK
137900. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT
137901. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK
137902. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT
137903. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK
137904. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT
137905. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK
137906. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT
137907. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK
137908. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT
137909. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK
137910. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT
137911. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK
137912. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT
137913. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK
137914. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT
137915. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK
137916. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT
137917. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK
137918. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT
137919. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK
137920. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT
137921. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK
137922. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT
137923. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK
137924. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT
137925. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK
137926. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT
137927. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK
137928. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT
137929. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK
137930. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT
137931. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK
137932. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT
137933. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK
137934. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT
137935. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK
137936. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT
137937. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK
137938. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT
137939. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK
137940. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT
137941. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK
137942. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT
137943. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK
137944. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT
137945. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK
137946. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT
137947. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK
137948. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT
137949. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK
137950. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT
137951. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK
137952. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT
137953. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK
137954. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT
137955. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK
137956. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT
137957. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK
137958. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT
137959. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK
137960. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT
137961. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK
137962. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT
137963. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK
137964. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT
137965. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK
137966. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT
137967. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK
137968. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT
137969. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK
137970. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT
137971. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK
137972. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT
137973. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK
137974. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT
137975. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK
137976. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT
137977. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK
137978. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT
137979. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK
137980. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT
137981. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK
137982. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT
137983. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK
137984. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT
137985. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK
137986. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT
137987. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK
137988. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT
137989. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK
137990. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT
137991. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK
137992. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT
137993. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK
137994. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT
137995. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK
137996. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT
137997. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK
137998. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT
137999. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK
138000. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT
138001. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK
138002. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT
138003. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK
138004. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT
138005. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK
138006. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT
138007. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK
138008. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT
138009. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK
138010. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT
138011. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK
138012. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT
138013. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK
138014. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT
138015. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK
138016. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT
138017. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK
138018. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT
138019. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK
138020. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
138021. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK
138022. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
138023. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK
138024. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT
138025. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK
138026. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT
138027. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK
138028. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT
138029. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK
138030. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT
138031. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK
138032. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
138033. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK
138034. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
138035. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK
138036. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT
138037. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK
138038. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT
138039. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK
138040. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
138041. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK
138042. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
138043. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK
138044. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT
138045. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK
138046. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT
138047. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK
138048. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
138049. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK
138050. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
138051. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK
138052. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT
138053. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK
138054. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT
138055. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK
138056. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT
138057. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK
138058. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT
138059. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK
138060. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT
138061. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK
138062. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT
138063. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK
138064. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT
138065. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK
138066. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT
138067. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK
138068. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT
138069. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK
138070. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT
138071. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK
138072. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT
138073. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK
138074. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT
138075. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK
138076. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT
138077. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK
138078. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT
138079. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK
138080. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT
138081. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK
138082. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT
138083. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK
138084. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT
138085. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK
138086. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT
138087. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK
138088. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT
138089. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK
138090. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT
138091. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK
138092. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT
138093. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK
138094. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT
138095. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK
138096. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT
138097. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK
138098. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT
138099. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK
138100. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT
138101. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK
138102. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT
138103. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK
138104. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT
138105. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK
138106. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT
138107. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK
138108. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT
138109. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK
138110. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT
138111. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK
138112. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT
138113. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK
138114. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT
138115. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK
138116. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT
138117. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK
138118. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT
138119. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK
138120. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT
138121. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK
138122. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT
138123. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK
138124. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT
138125. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK
138126. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT
138127. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK
138128. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT
138129. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK
138130. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT
138131. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK
138132. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT
138133. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK
138134. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT
138135. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK
138136. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT
138137. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK
138138. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT
138139. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK
138140. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT
138141. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK
138142. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT
138143. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK
138144. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT
138145. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK
138146. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT
138147. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK
138148. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT
138149. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK
138150. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT
138151. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK
138152. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT
138153. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK
138154. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT
138155. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK
138156. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT
138157. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK
138158. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT
138159. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK
138160. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT
138161. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK
138162. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT
138163. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK
138164. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT
138165. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK
138166. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT
138167. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK
138168. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT
138169. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK
138170. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT
138171. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK
138172. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT
138173. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK
138174. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT
138175. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK
138176. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT
138177. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK
138178. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT
138179. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK
138180. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT
138181. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK
138182. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT
138183. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK
138184. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT
138185. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK
138186. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT
138187. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK
138188. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT
138189. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK
138190. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT
138191. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK
138192. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT
138193. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK
138194. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT
138195. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK
138196. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT
138197. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK
138198. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT
138199. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK
138200. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT
138201. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK
138202. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT
138203. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK
138204. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT
138205. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK
138206. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT
138207. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK
138208. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT
138209. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK
138210. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT
138211. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK
138212. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT
138213. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK
138214. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT
138215. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK
138216. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT
138217. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK
138218. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT
138219. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK
138220. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT
138221. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK
138222. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT
138223. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK
138224. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT
138225. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK
138226. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT
138227. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK
138228. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT
138229. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK
138230. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT
138231. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK
138232. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT
138233. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK
138234. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT
138235. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK
138236. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT
138237. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK
138238. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT
138239. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK
138240. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT
138241. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK
138242. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT
138243. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK
138244. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT
138245. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK
138246. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT
138247. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK
138248. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT
138249. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK
138250. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT
138251. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK
138252. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT
138253. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK
138254. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT
138255. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK
138256. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT
138257. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK
138258. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT
138259. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK
138260. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT
138261. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
138262. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
138263. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
138264. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
138265. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
138266. BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
138267. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK
138268. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
138269. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK
138270. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT
138271. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK
138272. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT
138273. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK
138274. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT
138275. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK
138276. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
138277. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK
138278. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT
138279. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK
138280. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT
138281. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK
138282. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT
138283. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK
138284. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
138285. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK
138286. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT
138287. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK
138288. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT
138289. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK
138290. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT
138291. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK
138292. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
138293. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK
138294. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT
138295. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK
138296. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT
138297. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK
138298. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT
138299. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK
138300. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
138301. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK
138302. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT
138303. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK
138304. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT
138305. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK
138306. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT
138307. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK
138308. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
138309. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK
138310. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT
138311. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK
138312. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT
138313. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK
138314. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT
138315. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK
138316. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
138317. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK
138318. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
138319. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
138320. BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
138321. BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK
138322. BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT
138323. BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK
138324. BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
138325. BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT_MASK
138326. BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT
138327. BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT_MASK
138328. BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT
138329. BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT_MASK
138330. BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT
138331. BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
138332. BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
138333. BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
138334. BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
138335. BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK_MASK
138336. BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT
138337. BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT_MASK
138338. BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT
138339. BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION_MASK
138340. BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION__SHIFT
138341. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
138342. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
138343. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
138344. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
138345. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
138346. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
138347. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
138348. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
138349. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
138350. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
138351. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK
138352. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT
138353. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK
138354. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
138355. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK
138356. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
138357. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK
138358. BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
138359. BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK
138360. BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
138361. BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK
138362. BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT
138363. BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK
138364. BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT
138365. BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK
138366. BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
138367. BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK
138368. BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT
138369. BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK
138370. BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT
138371. BIF_CFG_DEV0_EPF1_1_SLOT_CAP2__RESERVED_MASK
138372. BIF_CFG_DEV0_EPF1_1_SLOT_CAP2__RESERVED__SHIFT
138373. BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2__RESERVED_MASK
138374. BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2__RESERVED__SHIFT
138375. BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2__RESERVED_MASK
138376. BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2__RESERVED__SHIFT
138377. BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST_MASK
138378. BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST__SHIFT
138379. BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING_MASK
138380. BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT
138381. BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK
138382. BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT
138383. BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS_MASK
138384. BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS__SHIFT
138385. BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS_MASK
138386. BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS__SHIFT
138387. BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
138388. BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
138389. BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK
138390. BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
138391. BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP_MASK
138392. BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP__SHIFT
138393. BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_EN_MASK
138394. BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_EN__SHIFT
138395. BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK
138396. BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
138397. BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK
138398. BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
138399. BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
138400. BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
138401. BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK
138402. BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
138403. BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS_MASK
138404. BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT
138405. BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK
138406. BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT
138407. BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK
138408. BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT
138409. BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK
138410. BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
138411. BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID_MASK
138412. BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT
138413. BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
138414. BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
138415. BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
138416. BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
138417. BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID_MASK
138418. BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
138419. BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
138420. BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
138421. BIF_CFG_DEV0_EPF1_2_BASE_ADDR_1__BASE_ADDR_MASK
138422. BIF_CFG_DEV0_EPF1_2_BASE_ADDR_1__BASE_ADDR__SHIFT
138423. BIF_CFG_DEV0_EPF1_2_BASE_ADDR_2__BASE_ADDR_MASK
138424. BIF_CFG_DEV0_EPF1_2_BASE_ADDR_2__BASE_ADDR__SHIFT
138425. BIF_CFG_DEV0_EPF1_2_BASE_ADDR_3__BASE_ADDR_MASK
138426. BIF_CFG_DEV0_EPF1_2_BASE_ADDR_3__BASE_ADDR__SHIFT
138427. BIF_CFG_DEV0_EPF1_2_BASE_ADDR_4__BASE_ADDR_MASK
138428. BIF_CFG_DEV0_EPF1_2_BASE_ADDR_4__BASE_ADDR__SHIFT
138429. BIF_CFG_DEV0_EPF1_2_BASE_ADDR_5__BASE_ADDR_MASK
138430. BIF_CFG_DEV0_EPF1_2_BASE_ADDR_5__BASE_ADDR__SHIFT
138431. BIF_CFG_DEV0_EPF1_2_BASE_ADDR_6__BASE_ADDR_MASK
138432. BIF_CFG_DEV0_EPF1_2_BASE_ADDR_6__BASE_ADDR__SHIFT
138433. BIF_CFG_DEV0_EPF1_2_BASE_CLASS__BASE_CLASS_MASK
138434. BIF_CFG_DEV0_EPF1_2_BASE_CLASS__BASE_CLASS__SHIFT
138435. BIF_CFG_DEV0_EPF1_2_BIST__BIST_CAP_MASK
138436. BIF_CFG_DEV0_EPF1_2_BIST__BIST_CAP__SHIFT
138437. BIF_CFG_DEV0_EPF1_2_BIST__BIST_COMP_MASK
138438. BIF_CFG_DEV0_EPF1_2_BIST__BIST_COMP__SHIFT
138439. BIF_CFG_DEV0_EPF1_2_BIST__BIST_STRT_MASK
138440. BIF_CFG_DEV0_EPF1_2_BIST__BIST_STRT__SHIFT
138441. BIF_CFG_DEV0_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
138442. BIF_CFG_DEV0_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
138443. BIF_CFG_DEV0_EPF1_2_CAP_PTR__CAP_PTR_MASK
138444. BIF_CFG_DEV0_EPF1_2_CAP_PTR__CAP_PTR__SHIFT
138445. BIF_CFG_DEV0_EPF1_2_COMMAND__AD_STEPPING_MASK
138446. BIF_CFG_DEV0_EPF1_2_COMMAND__AD_STEPPING__SHIFT
138447. BIF_CFG_DEV0_EPF1_2_COMMAND__BUS_MASTER_EN_MASK
138448. BIF_CFG_DEV0_EPF1_2_COMMAND__BUS_MASTER_EN__SHIFT
138449. BIF_CFG_DEV0_EPF1_2_COMMAND__FAST_B2B_EN_MASK
138450. BIF_CFG_DEV0_EPF1_2_COMMAND__FAST_B2B_EN__SHIFT
138451. BIF_CFG_DEV0_EPF1_2_COMMAND__INT_DIS_MASK
138452. BIF_CFG_DEV0_EPF1_2_COMMAND__INT_DIS__SHIFT
138453. BIF_CFG_DEV0_EPF1_2_COMMAND__IO_ACCESS_EN_MASK
138454. BIF_CFG_DEV0_EPF1_2_COMMAND__IO_ACCESS_EN__SHIFT
138455. BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_ACCESS_EN_MASK
138456. BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_ACCESS_EN__SHIFT
138457. BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
138458. BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
138459. BIF_CFG_DEV0_EPF1_2_COMMAND__PAL_SNOOP_EN_MASK
138460. BIF_CFG_DEV0_EPF1_2_COMMAND__PAL_SNOOP_EN__SHIFT
138461. BIF_CFG_DEV0_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
138462. BIF_CFG_DEV0_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
138463. BIF_CFG_DEV0_EPF1_2_COMMAND__SERR_EN_MASK
138464. BIF_CFG_DEV0_EPF1_2_COMMAND__SERR_EN__SHIFT
138465. BIF_CFG_DEV0_EPF1_2_COMMAND__SPECIAL_CYCLE_EN_MASK
138466. BIF_CFG_DEV0_EPF1_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
138467. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
138468. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
138469. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
138470. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
138471. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
138472. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
138473. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
138474. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
138475. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
138476. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
138477. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
138478. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
138479. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
138480. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
138481. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
138482. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
138483. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
138484. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
138485. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
138486. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
138487. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
138488. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
138489. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
138490. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
138491. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
138492. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
138493. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
138494. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
138495. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
138496. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
138497. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
138498. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
138499. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__EXTENDED_TAG_MASK
138500. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
138501. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__FLR_CAPABLE_MASK
138502. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
138503. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
138504. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
138505. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
138506. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
138507. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
138508. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
138509. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__PHANTOM_FUNC_MASK
138510. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
138511. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
138512. BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
138513. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
138514. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
138515. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
138516. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
138517. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
138518. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
138519. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
138520. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
138521. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
138522. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
138523. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
138524. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
138525. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
138526. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
138527. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
138528. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
138529. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__LTR_EN_MASK
138530. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__LTR_EN__SHIFT
138531. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__OBFF_EN_MASK
138532. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__OBFF_EN__SHIFT
138533. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
138534. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
138535. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__CORR_ERR_EN_MASK
138536. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
138537. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
138538. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
138539. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
138540. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
138541. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__INITIATE_FLR_MASK
138542. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__INITIATE_FLR__SHIFT
138543. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
138544. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
138545. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
138546. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
138547. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
138548. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
138549. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
138550. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
138551. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
138552. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
138553. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
138554. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
138555. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__USR_REPORT_EN_MASK
138556. BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
138557. BIF_CFG_DEV0_EPF1_2_DEVICE_ID__DEVICE_ID_MASK
138558. BIF_CFG_DEV0_EPF1_2_DEVICE_ID__DEVICE_ID__SHIFT
138559. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS2__RESERVED_MASK
138560. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS2__RESERVED__SHIFT
138561. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__AUX_PWR_MASK
138562. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__AUX_PWR__SHIFT
138563. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__CORR_ERR_MASK
138564. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__CORR_ERR__SHIFT
138565. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__FATAL_ERR_MASK
138566. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__FATAL_ERR__SHIFT
138567. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
138568. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
138569. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
138570. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
138571. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__USR_DETECTED_MASK
138572. BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__USR_DETECTED__SHIFT
138573. BIF_CFG_DEV0_EPF1_2_HEADER__DEVICE_TYPE_MASK
138574. BIF_CFG_DEV0_EPF1_2_HEADER__DEVICE_TYPE__SHIFT
138575. BIF_CFG_DEV0_EPF1_2_HEADER__HEADER_TYPE_MASK
138576. BIF_CFG_DEV0_EPF1_2_HEADER__HEADER_TYPE__SHIFT
138577. BIF_CFG_DEV0_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
138578. BIF_CFG_DEV0_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
138579. BIF_CFG_DEV0_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
138580. BIF_CFG_DEV0_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
138581. BIF_CFG_DEV0_EPF1_2_LATENCY__LATENCY_TIMER_MASK
138582. BIF_CFG_DEV0_EPF1_2_LATENCY__LATENCY_TIMER__SHIFT
138583. BIF_CFG_DEV0_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
138584. BIF_CFG_DEV0_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
138585. BIF_CFG_DEV0_EPF1_2_LINK_CAP2__RESERVED_MASK
138586. BIF_CFG_DEV0_EPF1_2_LINK_CAP2__RESERVED__SHIFT
138587. BIF_CFG_DEV0_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
138588. BIF_CFG_DEV0_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
138589. BIF_CFG_DEV0_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
138590. BIF_CFG_DEV0_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
138591. BIF_CFG_DEV0_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
138592. BIF_CFG_DEV0_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
138593. BIF_CFG_DEV0_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
138594. BIF_CFG_DEV0_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
138595. BIF_CFG_DEV0_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
138596. BIF_CFG_DEV0_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
138597. BIF_CFG_DEV0_EPF1_2_LINK_CAP__L1_EXIT_LATENCY_MASK
138598. BIF_CFG_DEV0_EPF1_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
138599. BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
138600. BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
138601. BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_SPEED_MASK
138602. BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_SPEED__SHIFT
138603. BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_WIDTH_MASK
138604. BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_WIDTH__SHIFT
138605. BIF_CFG_DEV0_EPF1_2_LINK_CAP__PM_SUPPORT_MASK
138606. BIF_CFG_DEV0_EPF1_2_LINK_CAP__PM_SUPPORT__SHIFT
138607. BIF_CFG_DEV0_EPF1_2_LINK_CAP__PORT_NUMBER_MASK
138608. BIF_CFG_DEV0_EPF1_2_LINK_CAP__PORT_NUMBER__SHIFT
138609. BIF_CFG_DEV0_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
138610. BIF_CFG_DEV0_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
138611. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
138612. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
138613. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
138614. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
138615. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
138616. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
138617. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
138618. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
138619. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
138620. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
138621. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
138622. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
138623. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
138624. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
138625. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__XMIT_MARGIN_MASK
138626. BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
138627. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
138628. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
138629. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
138630. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
138631. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__EXTENDED_SYNC_MASK
138632. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
138633. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
138634. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
138635. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
138636. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
138637. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
138638. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
138639. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_DIS_MASK
138640. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_DIS__SHIFT
138641. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__PM_CONTROL_MASK
138642. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__PM_CONTROL__SHIFT
138643. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
138644. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
138645. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__RETRAIN_LINK_MASK
138646. BIF_CFG_DEV0_EPF1_2_LINK_CNTL__RETRAIN_LINK__SHIFT
138647. BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
138648. BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
138649. BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
138650. BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
138651. BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
138652. BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
138653. BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
138654. BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
138655. BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
138656. BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
138657. BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
138658. BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
138659. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
138660. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
138661. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__DL_ACTIVE_MASK
138662. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__DL_ACTIVE__SHIFT
138663. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
138664. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
138665. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
138666. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
138667. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_TRAINING_MASK
138668. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_TRAINING__SHIFT
138669. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
138670. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
138671. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
138672. BIF_CFG_DEV0_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
138673. BIF_CFG_DEV0_EPF1_2_MAX_LATENCY__MAX_LAT_MASK
138674. BIF_CFG_DEV0_EPF1_2_MAX_LATENCY__MAX_LAT__SHIFT
138675. BIF_CFG_DEV0_EPF1_2_MIN_GRANT__MIN_GNT_MASK
138676. BIF_CFG_DEV0_EPF1_2_MIN_GRANT__MIN_GNT__SHIFT
138677. BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__CAP_ID_MASK
138678. BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__CAP_ID__SHIFT
138679. BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__NEXT_PTR_MASK
138680. BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT
138681. BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_EN_MASK
138682. BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT
138683. BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
138684. BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
138685. BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
138686. BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
138687. BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_BIR_MASK
138688. BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT
138689. BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK
138690. BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
138691. BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK
138692. BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
138693. BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
138694. BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
138695. BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__CAP_ID_MASK
138696. BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__CAP_ID__SHIFT
138697. BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__NEXT_PTR_MASK
138698. BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
138699. BIF_CFG_DEV0_EPF1_2_MSI_MASK_64__MSI_MASK_64_MASK
138700. BIF_CFG_DEV0_EPF1_2_MSI_MASK_64__MSI_MASK_64__SHIFT
138701. BIF_CFG_DEV0_EPF1_2_MSI_MASK__MSI_MASK_MASK
138702. BIF_CFG_DEV0_EPF1_2_MSI_MASK__MSI_MASK__SHIFT
138703. BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
138704. BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
138705. BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
138706. BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
138707. BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_64BIT_MASK
138708. BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
138709. BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_EN_MASK
138710. BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_EN__SHIFT
138711. BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
138712. BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
138713. BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
138714. BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
138715. BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
138716. BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
138717. BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
138718. BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
138719. BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA__MSI_DATA_MASK
138720. BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA__MSI_DATA__SHIFT
138721. BIF_CFG_DEV0_EPF1_2_MSI_PENDING_64__MSI_PENDING_64_MASK
138722. BIF_CFG_DEV0_EPF1_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT
138723. BIF_CFG_DEV0_EPF1_2_MSI_PENDING__MSI_PENDING_MASK
138724. BIF_CFG_DEV0_EPF1_2_MSI_PENDING__MSI_PENDING__SHIFT
138725. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
138726. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
138727. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
138728. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
138729. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
138730. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
138731. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
138732. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
138733. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
138734. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
138735. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
138736. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
138737. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
138738. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
138739. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
138740. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
138741. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
138742. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
138743. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
138744. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
138745. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
138746. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
138747. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
138748. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
138749. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
138750. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
138751. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
138752. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
138753. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
138754. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
138755. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
138756. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
138757. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
138758. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
138759. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
138760. BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
138761. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
138762. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
138763. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
138764. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
138765. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
138766. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
138767. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
138768. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
138769. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
138770. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
138771. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
138772. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
138773. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
138774. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
138775. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
138776. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
138777. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
138778. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
138779. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
138780. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
138781. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
138782. BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
138783. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
138784. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
138785. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
138786. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
138787. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
138788. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
138789. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
138790. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
138791. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
138792. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
138793. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
138794. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
138795. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
138796. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
138797. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
138798. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
138799. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
138800. BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
138801. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
138802. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
138803. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
138804. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
138805. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
138806. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
138807. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__ATC_ENABLE_MASK
138808. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
138809. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__STU_MASK
138810. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__STU__SHIFT
138811. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
138812. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
138813. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
138814. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
138815. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
138816. BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
138817. BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
138818. BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
138819. BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK
138820. BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
138821. BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK
138822. BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
138823. BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
138824. BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
138825. BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
138826. BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
138827. BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK
138828. BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
138829. BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK
138830. BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
138831. BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
138832. BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
138833. BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
138834. BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
138835. BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK
138836. BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
138837. BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK
138838. BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
138839. BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
138840. BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
138841. BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
138842. BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
138843. BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK
138844. BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
138845. BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK
138846. BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
138847. BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
138848. BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
138849. BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
138850. BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
138851. BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK
138852. BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
138853. BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK
138854. BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
138855. BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
138856. BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
138857. BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
138858. BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
138859. BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK
138860. BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
138861. BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK
138862. BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
138863. BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
138864. BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
138865. BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
138866. BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
138867. BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
138868. BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
138869. BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
138870. BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
138871. BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__CAP_ID_MASK
138872. BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__CAP_ID__SHIFT
138873. BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__NEXT_PTR_MASK
138874. BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
138875. BIF_CFG_DEV0_EPF1_2_PCIE_CAP__DEVICE_TYPE_MASK
138876. BIF_CFG_DEV0_EPF1_2_PCIE_CAP__DEVICE_TYPE__SHIFT
138877. BIF_CFG_DEV0_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
138878. BIF_CFG_DEV0_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
138879. BIF_CFG_DEV0_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
138880. BIF_CFG_DEV0_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
138881. BIF_CFG_DEV0_EPF1_2_PCIE_CAP__VERSION_MASK
138882. BIF_CFG_DEV0_EPF1_2_PCIE_CAP__VERSION__SHIFT
138883. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
138884. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
138885. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
138886. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
138887. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
138888. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
138889. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
138890. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
138891. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
138892. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
138893. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
138894. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
138895. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
138896. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
138897. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
138898. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
138899. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
138900. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
138901. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
138902. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
138903. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
138904. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
138905. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
138906. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
138907. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
138908. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
138909. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
138910. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
138911. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
138912. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
138913. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
138914. BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
138915. BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
138916. BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
138917. BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
138918. BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
138919. BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
138920. BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
138921. BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
138922. BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
138923. BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
138924. BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
138925. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
138926. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
138927. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
138928. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
138929. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
138930. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
138931. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
138932. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
138933. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
138934. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
138935. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
138936. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
138937. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
138938. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
138939. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
138940. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
138941. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
138942. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
138943. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
138944. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
138945. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
138946. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
138947. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
138948. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
138949. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
138950. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
138951. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
138952. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
138953. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
138954. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
138955. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
138956. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
138957. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
138958. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
138959. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
138960. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
138961. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
138962. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
138963. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
138964. BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
138965. BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG0__TLP_HDR_MASK
138966. BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
138967. BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG1__TLP_HDR_MASK
138968. BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
138969. BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG2__TLP_HDR_MASK
138970. BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
138971. BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG3__TLP_HDR_MASK
138972. BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
138973. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
138974. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
138975. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
138976. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
138977. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
138978. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
138979. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
138980. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
138981. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
138982. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
138983. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
138984. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
138985. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
138986. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
138987. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
138988. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
138989. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
138990. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
138991. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
138992. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
138993. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
138994. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
138995. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
138996. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
138997. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
138998. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
138999. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139000. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139001. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139002. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139003. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
139004. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
139005. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
139006. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
139007. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
139008. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
139009. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139010. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139011. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139012. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139013. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
139014. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
139015. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
139016. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
139017. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
139018. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
139019. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139020. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139021. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139022. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139023. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
139024. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
139025. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
139026. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
139027. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
139028. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
139029. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139030. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139031. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139032. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139033. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
139034. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
139035. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
139036. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
139037. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
139038. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
139039. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139040. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139041. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139042. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139043. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
139044. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
139045. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
139046. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
139047. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
139048. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
139049. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139050. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139051. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139052. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139053. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
139054. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
139055. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
139056. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
139057. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
139058. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
139059. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139060. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139061. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139062. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139063. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
139064. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
139065. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
139066. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
139067. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
139068. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
139069. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139070. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139071. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139072. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139073. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
139074. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
139075. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
139076. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
139077. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
139078. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
139079. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139080. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139081. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139082. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139083. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
139084. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
139085. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
139086. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
139087. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
139088. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
139089. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139090. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139091. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139092. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139093. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
139094. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
139095. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
139096. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
139097. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
139098. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
139099. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139100. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139101. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139102. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139103. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
139104. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
139105. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
139106. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
139107. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
139108. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
139109. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139110. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139111. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139112. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139113. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
139114. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
139115. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
139116. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
139117. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
139118. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
139119. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139120. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139121. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139122. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139123. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
139124. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
139125. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
139126. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
139127. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
139128. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
139129. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
139130. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
139131. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
139132. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
139133. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
139134. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
139135. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
139136. BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
139137. BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
139138. BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
139139. BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
139140. BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
139141. BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__RESERVED_MASK
139142. BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__RESERVED__SHIFT
139143. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
139144. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
139145. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
139146. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
139147. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
139148. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
139149. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
139150. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
139151. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
139152. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
139153. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
139154. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
139155. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
139156. BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
139157. BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
139158. BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
139159. BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
139160. BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
139161. BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
139162. BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
139163. BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
139164. BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
139165. BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
139166. BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
139167. BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
139168. BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
139169. BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
139170. BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
139171. BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
139172. BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
139173. BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK
139174. BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
139175. BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK
139176. BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT
139177. BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_ENABLE_MASK
139178. BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT
139179. BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
139180. BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
139181. BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
139182. BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
139183. BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
139184. BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
139185. BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
139186. BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
139187. BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
139188. BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
139189. BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
139190. BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
139191. BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK
139192. BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT
139193. BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK
139194. BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT
139195. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK
139196. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT
139197. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK
139198. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT
139199. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK
139200. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT
139201. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK
139202. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT
139203. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK
139204. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT
139205. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK
139206. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT
139207. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK
139208. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT
139209. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__STOPPED_MASK
139210. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT
139211. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK
139212. BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT
139213. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
139214. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
139215. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
139216. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
139217. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
139218. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
139219. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_ENABLE_MASK
139220. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
139221. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
139222. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
139223. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
139224. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
139225. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
139226. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
139227. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
139228. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
139229. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
139230. BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
139231. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
139232. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
139233. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
139234. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
139235. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
139236. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
139237. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
139238. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
139239. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
139240. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
139241. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
139242. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
139243. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
139244. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
139245. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
139246. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
139247. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
139248. BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
139249. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
139250. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
139251. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
139252. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
139253. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
139254. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
139255. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
139256. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
139257. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
139258. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
139259. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
139260. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
139261. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
139262. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
139263. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK
139264. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
139265. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
139266. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
139267. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
139268. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
139269. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
139270. BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
139271. BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
139272. BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
139273. BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
139274. BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
139275. BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
139276. BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
139277. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK
139278. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT
139279. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK
139280. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT
139281. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK
139282. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT
139283. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK
139284. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT
139285. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK
139286. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT
139287. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK
139288. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT
139289. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK
139290. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT
139291. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK
139292. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT
139293. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK
139294. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT
139295. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK
139296. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT
139297. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK
139298. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT
139299. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK
139300. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT
139301. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK
139302. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT
139303. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK
139304. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT
139305. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK
139306. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT
139307. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK
139308. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT
139309. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK
139310. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT
139311. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK
139312. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT
139313. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK
139314. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT
139315. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK
139316. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT
139317. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK
139318. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT
139319. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK
139320. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT
139321. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK
139322. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT
139323. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK
139324. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT
139325. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK
139326. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT
139327. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK
139328. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT
139329. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK
139330. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT
139331. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK
139332. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT
139333. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK
139334. BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT
139335. BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
139336. BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
139337. BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
139338. BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
139339. BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
139340. BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
139341. BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
139342. BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
139343. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
139344. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
139345. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
139346. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
139347. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
139348. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
139349. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
139350. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
139351. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
139352. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
139353. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
139354. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
139355. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
139356. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
139357. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
139358. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
139359. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
139360. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
139361. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
139362. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
139363. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
139364. BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
139365. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
139366. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
139367. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
139368. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
139369. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
139370. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
139371. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
139372. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
139373. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
139374. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
139375. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
139376. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
139377. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
139378. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
139379. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
139380. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
139381. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
139382. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
139383. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
139384. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
139385. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
139386. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
139387. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
139388. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
139389. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
139390. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
139391. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
139392. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
139393. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
139394. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
139395. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
139396. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
139397. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
139398. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
139399. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
139400. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
139401. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
139402. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
139403. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
139404. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
139405. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
139406. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
139407. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
139408. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
139409. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
139410. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
139411. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
139412. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
139413. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
139414. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
139415. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
139416. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
139417. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
139418. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
139419. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
139420. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
139421. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
139422. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
139423. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
139424. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
139425. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
139426. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
139427. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
139428. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
139429. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
139430. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
139431. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
139432. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
139433. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
139434. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
139435. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
139436. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
139437. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
139438. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
139439. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
139440. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
139441. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
139442. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
139443. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
139444. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
139445. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
139446. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
139447. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
139448. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
139449. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
139450. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
139451. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
139452. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
139453. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
139454. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
139455. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
139456. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
139457. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
139458. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
139459. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
139460. BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
139461. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
139462. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
139463. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
139464. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
139465. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
139466. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
139467. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
139468. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
139469. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
139470. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
139471. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
139472. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
139473. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
139474. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
139475. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
139476. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
139477. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
139478. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
139479. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
139480. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
139481. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
139482. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
139483. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
139484. BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
139485. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
139486. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
139487. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
139488. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
139489. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
139490. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
139491. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
139492. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
139493. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
139494. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
139495. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
139496. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
139497. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
139498. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
139499. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
139500. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
139501. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
139502. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
139503. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
139504. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
139505. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
139506. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
139507. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
139508. BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
139509. BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
139510. BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
139511. BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
139512. BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
139513. BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
139514. BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
139515. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
139516. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
139517. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
139518. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
139519. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK
139520. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT
139521. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK
139522. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT
139523. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK
139524. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT
139525. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
139526. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
139527. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
139528. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
139529. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
139530. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
139531. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK
139532. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT
139533. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK
139534. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT
139535. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK
139536. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT
139537. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK
139538. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT
139539. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK
139540. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT
139541. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK
139542. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT
139543. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK
139544. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT
139545. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK
139546. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT
139547. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK
139548. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT
139549. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK
139550. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT
139551. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK
139552. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT
139553. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK
139554. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT
139555. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK
139556. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT
139557. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK
139558. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT
139559. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK
139560. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT
139561. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK
139562. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT
139563. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK
139564. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT
139565. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK
139566. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT
139567. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK
139568. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT
139569. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK
139570. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT
139571. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK
139572. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT
139573. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK
139574. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT
139575. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK
139576. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT
139577. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK
139578. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT
139579. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK
139580. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT
139581. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK
139582. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT
139583. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK
139584. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT
139585. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK
139586. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT
139587. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK
139588. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT
139589. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK
139590. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT
139591. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK
139592. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT
139593. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK
139594. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT
139595. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK
139596. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT
139597. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK
139598. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT
139599. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK
139600. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT
139601. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK
139602. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT
139603. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK
139604. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT
139605. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK
139606. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT
139607. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK
139608. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT
139609. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK
139610. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT
139611. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK
139612. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT
139613. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK
139614. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT
139615. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK
139616. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT
139617. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK
139618. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT
139619. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK
139620. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT
139621. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK
139622. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT
139623. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK
139624. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT
139625. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK
139626. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT
139627. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK
139628. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT
139629. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK
139630. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT
139631. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK
139632. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT
139633. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK
139634. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT
139635. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK
139636. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT
139637. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK
139638. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT
139639. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK
139640. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT
139641. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK
139642. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT
139643. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK
139644. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT
139645. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK
139646. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT
139647. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK
139648. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT
139649. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK
139650. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT
139651. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK
139652. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT
139653. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK
139654. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT
139655. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK
139656. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT
139657. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK
139658. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT
139659. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK
139660. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT
139661. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK
139662. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT
139663. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK
139664. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT
139665. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK
139666. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
139667. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK
139668. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
139669. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK
139670. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT
139671. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK
139672. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT
139673. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK
139674. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT
139675. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK
139676. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT
139677. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK
139678. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
139679. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK
139680. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
139681. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK
139682. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT
139683. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK
139684. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT
139685. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK
139686. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
139687. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK
139688. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
139689. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK
139690. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT
139691. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK
139692. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT
139693. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK
139694. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT
139695. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK
139696. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT
139697. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK
139698. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT
139699. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK
139700. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT
139701. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK
139702. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT
139703. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK
139704. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT
139705. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK
139706. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT
139707. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK
139708. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT
139709. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK
139710. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT
139711. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK
139712. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT
139713. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK
139714. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT
139715. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK
139716. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT
139717. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK
139718. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT
139719. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK
139720. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT
139721. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK
139722. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT
139723. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK
139724. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT
139725. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK
139726. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT
139727. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK
139728. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT
139729. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK
139730. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT
139731. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK
139732. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT
139733. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK
139734. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT
139735. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK
139736. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT
139737. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK
139738. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT
139739. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK
139740. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT
139741. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK
139742. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT
139743. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK
139744. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT
139745. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK
139746. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT
139747. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK
139748. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT
139749. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK
139750. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT
139751. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK
139752. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT
139753. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK
139754. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT
139755. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK
139756. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT
139757. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK
139758. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT
139759. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK
139760. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT
139761. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK
139762. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT
139763. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK
139764. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT
139765. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK
139766. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT
139767. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK
139768. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT
139769. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK
139770. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT
139771. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK
139772. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT
139773. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK
139774. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT
139775. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK
139776. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT
139777. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK
139778. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT
139779. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK
139780. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT
139781. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK
139782. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT
139783. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK
139784. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT
139785. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK
139786. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT
139787. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK
139788. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT
139789. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK
139790. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT
139791. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK
139792. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT
139793. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK
139794. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT
139795. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK
139796. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT
139797. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK
139798. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT
139799. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK
139800. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT
139801. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK
139802. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT
139803. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK
139804. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT
139805. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK
139806. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT
139807. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK
139808. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT
139809. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK
139810. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT
139811. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
139812. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
139813. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
139814. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
139815. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
139816. BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
139817. BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__CAP_ID_MASK
139818. BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__CAP_ID__SHIFT
139819. BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__NEXT_PTR_MASK
139820. BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
139821. BIF_CFG_DEV0_EPF1_2_PMI_CAP__AUX_CURRENT_MASK
139822. BIF_CFG_DEV0_EPF1_2_PMI_CAP__AUX_CURRENT__SHIFT
139823. BIF_CFG_DEV0_EPF1_2_PMI_CAP__D1_SUPPORT_MASK
139824. BIF_CFG_DEV0_EPF1_2_PMI_CAP__D1_SUPPORT__SHIFT
139825. BIF_CFG_DEV0_EPF1_2_PMI_CAP__D2_SUPPORT_MASK
139826. BIF_CFG_DEV0_EPF1_2_PMI_CAP__D2_SUPPORT__SHIFT
139827. BIF_CFG_DEV0_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
139828. BIF_CFG_DEV0_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
139829. BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_CLOCK_MASK
139830. BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_CLOCK__SHIFT
139831. BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_SUPPORT_MASK
139832. BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_SUPPORT__SHIFT
139833. BIF_CFG_DEV0_EPF1_2_PMI_CAP__VERSION_MASK
139834. BIF_CFG_DEV0_EPF1_2_PMI_CAP__VERSION__SHIFT
139835. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
139836. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
139837. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
139838. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
139839. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
139840. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
139841. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
139842. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
139843. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
139844. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
139845. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_EN_MASK
139846. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_EN__SHIFT
139847. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_STATUS_MASK
139848. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
139849. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PMI_DATA_MASK
139850. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
139851. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__POWER_STATE_MASK
139852. BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
139853. BIF_CFG_DEV0_EPF1_2_PROG_INTERFACE__PROG_INTERFACE_MASK
139854. BIF_CFG_DEV0_EPF1_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
139855. BIF_CFG_DEV0_EPF1_2_REVISION_ID__MAJOR_REV_ID_MASK
139856. BIF_CFG_DEV0_EPF1_2_REVISION_ID__MAJOR_REV_ID__SHIFT
139857. BIF_CFG_DEV0_EPF1_2_REVISION_ID__MINOR_REV_ID_MASK
139858. BIF_CFG_DEV0_EPF1_2_REVISION_ID__MINOR_REV_ID__SHIFT
139859. BIF_CFG_DEV0_EPF1_2_ROM_BASE_ADDR__BASE_ADDR_MASK
139860. BIF_CFG_DEV0_EPF1_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT
139861. BIF_CFG_DEV0_EPF1_2_SLOT_CAP2__RESERVED_MASK
139862. BIF_CFG_DEV0_EPF1_2_SLOT_CAP2__RESERVED__SHIFT
139863. BIF_CFG_DEV0_EPF1_2_SLOT_CNTL2__RESERVED_MASK
139864. BIF_CFG_DEV0_EPF1_2_SLOT_CNTL2__RESERVED__SHIFT
139865. BIF_CFG_DEV0_EPF1_2_SLOT_STATUS2__RESERVED_MASK
139866. BIF_CFG_DEV0_EPF1_2_SLOT_STATUS2__RESERVED__SHIFT
139867. BIF_CFG_DEV0_EPF1_2_STATUS__CAP_LIST_MASK
139868. BIF_CFG_DEV0_EPF1_2_STATUS__CAP_LIST__SHIFT
139869. BIF_CFG_DEV0_EPF1_2_STATUS__DEVSEL_TIMING_MASK
139870. BIF_CFG_DEV0_EPF1_2_STATUS__DEVSEL_TIMING__SHIFT
139871. BIF_CFG_DEV0_EPF1_2_STATUS__FAST_BACK_CAPABLE_MASK
139872. BIF_CFG_DEV0_EPF1_2_STATUS__FAST_BACK_CAPABLE__SHIFT
139873. BIF_CFG_DEV0_EPF1_2_STATUS__INT_STATUS_MASK
139874. BIF_CFG_DEV0_EPF1_2_STATUS__INT_STATUS__SHIFT
139875. BIF_CFG_DEV0_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
139876. BIF_CFG_DEV0_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
139877. BIF_CFG_DEV0_EPF1_2_STATUS__PARITY_ERROR_DETECTED_MASK
139878. BIF_CFG_DEV0_EPF1_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
139879. BIF_CFG_DEV0_EPF1_2_STATUS__PCI_66_EN_MASK
139880. BIF_CFG_DEV0_EPF1_2_STATUS__PCI_66_EN__SHIFT
139881. BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_MASTER_ABORT_MASK
139882. BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
139883. BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_TARGET_ABORT_MASK
139884. BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
139885. BIF_CFG_DEV0_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
139886. BIF_CFG_DEV0_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
139887. BIF_CFG_DEV0_EPF1_2_STATUS__SIGNAL_TARGET_ABORT_MASK
139888. BIF_CFG_DEV0_EPF1_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
139889. BIF_CFG_DEV0_EPF1_2_SUB_CLASS__SUB_CLASS_MASK
139890. BIF_CFG_DEV0_EPF1_2_SUB_CLASS__SUB_CLASS__SHIFT
139891. BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__CAP_ID_MASK
139892. BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__CAP_ID__SHIFT
139893. BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__LENGTH_MASK
139894. BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__LENGTH__SHIFT
139895. BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR_MASK
139896. BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
139897. BIF_CFG_DEV0_EPF1_2_VENDOR_ID__VENDOR_ID_MASK
139898. BIF_CFG_DEV0_EPF1_2_VENDOR_ID__VENDOR_ID__SHIFT
139899. BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
139900. BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
139901. BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
139902. BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
139903. BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK
139904. BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
139905. BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
139906. BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
139907. BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK
139908. BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT
139909. BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK
139910. BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT
139911. BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK
139912. BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT
139913. BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK
139914. BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT
139915. BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK
139916. BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT
139917. BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK
139918. BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT
139919. BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK
139920. BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT
139921. BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK
139922. BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT
139923. BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK
139924. BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT
139925. BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK
139926. BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT
139927. BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK
139928. BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
139929. BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK
139930. BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT
139931. BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
139932. BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
139933. BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK
139934. BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT
139935. BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK
139936. BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT
139937. BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK
139938. BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT
139939. BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK
139940. BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT
139941. BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK
139942. BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT
139943. BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK
139944. BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT
139945. BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
139946. BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
139947. BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK
139948. BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT
139949. BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK
139950. BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
139951. BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK
139952. BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT
139953. BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK
139954. BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
139955. BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK
139956. BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT
139957. BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK
139958. BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT
139959. BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK
139960. BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK
139961. BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT
139962. BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT
139963. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
139964. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
139965. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
139966. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
139967. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
139968. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
139969. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
139970. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
139971. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
139972. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
139973. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
139974. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
139975. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
139976. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
139977. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
139978. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
139979. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
139980. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
139981. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
139982. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
139983. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
139984. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
139985. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK
139986. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
139987. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
139988. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
139989. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK
139990. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
139991. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
139992. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
139993. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
139994. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
139995. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
139996. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
139997. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
139998. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
139999. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
140000. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
140001. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
140002. BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
140003. BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
140004. BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
140005. BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
140006. BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
140007. BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK
140008. BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT
140009. BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK
140010. BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT
140011. BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
140012. BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
140013. BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
140014. BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
140015. BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
140016. BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
140017. BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK
140018. BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
140019. BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
140020. BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
140021. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
140022. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
140023. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
140024. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
140025. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
140026. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
140027. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
140028. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
140029. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
140030. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
140031. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
140032. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
140033. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
140034. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
140035. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
140036. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
140037. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
140038. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
140039. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK
140040. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT
140041. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK
140042. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT
140043. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
140044. BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
140045. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
140046. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
140047. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK
140048. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
140049. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
140050. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
140051. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK
140052. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
140053. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK
140054. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT
140055. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
140056. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
140057. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
140058. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
140059. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
140060. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
140061. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK
140062. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
140063. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
140064. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
140065. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
140066. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
140067. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK
140068. BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
140069. BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK
140070. BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT
140071. BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK
140072. BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT
140073. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK
140074. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT
140075. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK
140076. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT
140077. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
140078. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
140079. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK
140080. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT
140081. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK
140082. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
140083. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
140084. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
140085. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK
140086. BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT
140087. BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK
140088. BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT
140089. BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK
140090. BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT
140091. BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
140092. BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
140093. BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
140094. BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
140095. BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK
140096. BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT
140097. BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK
140098. BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT
140099. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK
140100. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT
140101. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK
140102. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT
140103. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK
140104. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT
140105. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK
140106. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT
140107. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK
140108. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT
140109. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK
140110. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT
140111. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK
140112. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT
140113. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK
140114. BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT
140115. BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK
140116. BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT
140117. BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK
140118. BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT
140119. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK
140120. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT
140121. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK
140122. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT
140123. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK
140124. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT
140125. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK
140126. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT
140127. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK
140128. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT
140129. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK
140130. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT
140131. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK
140132. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT
140133. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK
140134. BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT
140135. BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK
140136. BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT
140137. BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK
140138. BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT
140139. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK
140140. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT
140141. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK
140142. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT
140143. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK
140144. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT
140145. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK
140146. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT
140147. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK
140148. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT
140149. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK
140150. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT
140151. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK
140152. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT
140153. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK
140154. BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT
140155. BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK
140156. BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT
140157. BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK
140158. BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT
140159. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK
140160. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT
140161. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK
140162. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT
140163. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK
140164. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT
140165. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK
140166. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT
140167. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK
140168. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT
140169. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK
140170. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT
140171. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK
140172. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT
140173. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK
140174. BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT
140175. BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK
140176. BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT
140177. BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK
140178. BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT
140179. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK
140180. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT
140181. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK
140182. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT
140183. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK
140184. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT
140185. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK
140186. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT
140187. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK
140188. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT
140189. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK
140190. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT
140191. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK
140192. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT
140193. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK
140194. BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT
140195. BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK
140196. BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT
140197. BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK
140198. BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT
140199. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK
140200. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT
140201. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK
140202. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT
140203. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK
140204. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT
140205. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK
140206. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT
140207. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK
140208. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT
140209. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK
140210. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT
140211. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK
140212. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT
140213. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK
140214. BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT
140215. BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK
140216. BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT
140217. BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK
140218. BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT
140219. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK
140220. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT
140221. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK
140222. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT
140223. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK
140224. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT
140225. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK
140226. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT
140227. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK
140228. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT
140229. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK
140230. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT
140231. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK
140232. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT
140233. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK
140234. BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT
140235. BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK
140236. BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT
140237. BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK
140238. BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT
140239. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK
140240. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT
140241. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK
140242. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT
140243. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK
140244. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT
140245. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK
140246. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT
140247. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK
140248. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT
140249. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK
140250. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT
140251. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK
140252. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT
140253. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK
140254. BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT
140255. BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK
140256. BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT
140257. BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK
140258. BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT
140259. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK
140260. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT
140261. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK
140262. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT
140263. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK
140264. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT
140265. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK
140266. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT
140267. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK
140268. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT
140269. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK
140270. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT
140271. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK
140272. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT
140273. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK
140274. BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT
140275. BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK
140276. BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT
140277. BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK
140278. BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT
140279. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK
140280. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT
140281. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK
140282. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT
140283. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK
140284. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT
140285. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK
140286. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT
140287. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK
140288. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT
140289. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK
140290. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT
140291. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK
140292. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT
140293. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK
140294. BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT
140295. BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK
140296. BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT
140297. BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK
140298. BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT
140299. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK
140300. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT
140301. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK
140302. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT
140303. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK
140304. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT
140305. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK
140306. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT
140307. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK
140308. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT
140309. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK
140310. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT
140311. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK
140312. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT
140313. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK
140314. BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT
140315. BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK
140316. BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT
140317. BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK
140318. BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT
140319. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK
140320. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT
140321. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK
140322. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT
140323. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK
140324. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT
140325. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK
140326. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT
140327. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK
140328. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT
140329. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK
140330. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT
140331. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK
140332. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT
140333. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK
140334. BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT
140335. BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK
140336. BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT
140337. BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK
140338. BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT
140339. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK
140340. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT
140341. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK
140342. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT
140343. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK
140344. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT
140345. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK
140346. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT
140347. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK
140348. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT
140349. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK
140350. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT
140351. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK
140352. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT
140353. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK
140354. BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT
140355. BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK
140356. BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT
140357. BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK
140358. BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT
140359. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK
140360. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT
140361. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK
140362. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT
140363. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK
140364. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT
140365. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK
140366. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT
140367. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK
140368. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT
140369. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK
140370. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT
140371. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK
140372. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT
140373. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK
140374. BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT
140375. BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK
140376. BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT
140377. BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK
140378. BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT
140379. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK
140380. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT
140381. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK
140382. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT
140383. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK
140384. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT
140385. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK
140386. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT
140387. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK
140388. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT
140389. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK
140390. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT
140391. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK
140392. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT
140393. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK
140394. BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT
140395. BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK
140396. BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT
140397. BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK
140398. BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT
140399. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK
140400. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT
140401. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK
140402. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT
140403. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK
140404. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT
140405. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK
140406. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT
140407. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK
140408. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT
140409. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK
140410. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT
140411. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK
140412. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT
140413. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK
140414. BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT
140415. BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK
140416. BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT
140417. BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
140418. BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
140419. BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
140420. BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
140421. BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
140422. BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
140423. BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
140424. BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
140425. BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
140426. BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
140427. BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
140428. BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
140429. BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
140430. BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
140431. BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED_MASK
140432. BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED__SHIFT
140433. BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
140434. BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
140435. BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
140436. BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
140437. BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
140438. BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
140439. BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK
140440. BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
140441. BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK
140442. BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
140443. BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
140444. BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
140445. BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK
140446. BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT
140447. BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK
140448. BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT
140449. BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK
140450. BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT
140451. BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK
140452. BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT
140453. BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
140454. BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
140455. BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
140456. BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
140457. BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK
140458. BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
140459. BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
140460. BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
140461. BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
140462. BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
140463. BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
140464. BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
140465. BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
140466. BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
140467. BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
140468. BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
140469. BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK
140470. BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT
140471. BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED_MASK
140472. BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED__SHIFT
140473. BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
140474. BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
140475. BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
140476. BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
140477. BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
140478. BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
140479. BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK
140480. BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT
140481. BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
140482. BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
140483. BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
140484. BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
140485. BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
140486. BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
140487. BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK
140488. BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT
140489. BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK
140490. BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT
140491. BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
140492. BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
140493. BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK
140494. BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT
140495. BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
140496. BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
140497. BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
140498. BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
140499. BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
140500. BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
140501. BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
140502. BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
140503. BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
140504. BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
140505. BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
140506. BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
140507. BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
140508. BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
140509. BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
140510. BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
140511. BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
140512. BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
140513. BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
140514. BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
140515. BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
140516. BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
140517. BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK
140518. BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT
140519. BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK
140520. BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT
140521. BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK
140522. BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT
140523. BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK
140524. BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT
140525. BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK
140526. BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT
140527. BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
140528. BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
140529. BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK
140530. BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT
140531. BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
140532. BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
140533. BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
140534. BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
140535. BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK
140536. BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT
140537. BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
140538. BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
140539. BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
140540. BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
140541. BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK
140542. BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT
140543. BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK
140544. BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT
140545. BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY_MASK
140546. BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT
140547. BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK
140548. BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT
140549. BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK
140550. BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT
140551. BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK
140552. BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT
140553. BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK
140554. BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT
140555. BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK
140556. BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
140557. BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK
140558. BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
140559. BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
140560. BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
140561. BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
140562. BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
140563. BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK
140564. BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
140565. BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
140566. BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
140567. BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
140568. BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
140569. BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
140570. BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
140571. BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK
140572. BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT
140573. BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK
140574. BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT
140575. BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK
140576. BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT
140577. BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK
140578. BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT
140579. BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
140580. BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
140581. BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
140582. BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
140583. BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK
140584. BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
140585. BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK
140586. BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT
140587. BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
140588. BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
140589. BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
140590. BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
140591. BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
140592. BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
140593. BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
140594. BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
140595. BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK
140596. BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT
140597. BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK
140598. BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
140599. BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK
140600. BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT
140601. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
140602. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
140603. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
140604. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
140605. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
140606. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
140607. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
140608. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
140609. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
140610. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
140611. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
140612. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
140613. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
140614. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
140615. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
140616. BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
140617. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
140618. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
140619. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
140620. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
140621. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
140622. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
140623. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
140624. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
140625. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
140626. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
140627. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
140628. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
140629. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
140630. BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
140631. BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
140632. BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
140633. BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
140634. BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
140635. BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
140636. BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
140637. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
140638. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
140639. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
140640. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
140641. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
140642. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
140643. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
140644. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
140645. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
140646. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
140647. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
140648. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
140649. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
140650. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
140651. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
140652. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
140653. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
140654. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
140655. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
140656. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
140657. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
140658. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
140659. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
140660. BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
140661. BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
140662. BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
140663. BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
140664. BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
140665. BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
140666. BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
140667. BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
140668. BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
140669. BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
140670. BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
140671. BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
140672. BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
140673. BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
140674. BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
140675. BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
140676. BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
140677. BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
140678. BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
140679. BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
140680. BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
140681. BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
140682. BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
140683. BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
140684. BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
140685. BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK
140686. BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
140687. BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU_MASK
140688. BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU__SHIFT
140689. BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
140690. BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
140691. BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
140692. BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
140693. BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
140694. BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
140695. BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
140696. BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
140697. BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK
140698. BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
140699. BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK
140700. BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
140701. BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
140702. BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
140703. BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
140704. BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
140705. BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK
140706. BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
140707. BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK
140708. BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
140709. BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
140710. BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
140711. BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
140712. BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
140713. BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK
140714. BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
140715. BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK
140716. BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
140717. BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
140718. BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
140719. BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
140720. BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
140721. BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK
140722. BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
140723. BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK
140724. BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
140725. BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
140726. BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
140727. BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
140728. BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
140729. BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK
140730. BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
140731. BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK
140732. BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
140733. BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
140734. BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
140735. BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
140736. BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
140737. BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK
140738. BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
140739. BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK
140740. BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
140741. BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
140742. BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
140743. BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
140744. BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
140745. BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
140746. BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
140747. BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
140748. BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
140749. BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK
140750. BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT
140751. BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK
140752. BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
140753. BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK
140754. BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT
140755. BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK
140756. BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
140757. BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
140758. BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
140759. BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK
140760. BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT
140761. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
140762. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
140763. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
140764. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
140765. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
140766. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
140767. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
140768. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
140769. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
140770. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
140771. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
140772. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
140773. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
140774. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
140775. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
140776. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
140777. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
140778. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
140779. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
140780. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
140781. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
140782. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
140783. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
140784. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
140785. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
140786. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
140787. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
140788. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
140789. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
140790. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
140791. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
140792. BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
140793. BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
140794. BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
140795. BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
140796. BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
140797. BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
140798. BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
140799. BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
140800. BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
140801. BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
140802. BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
140803. BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK
140804. BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT
140805. BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK
140806. BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT
140807. BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK
140808. BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT
140809. BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
140810. BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
140811. BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
140812. BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
140813. BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
140814. BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
140815. BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
140816. BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
140817. BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
140818. BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
140819. BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
140820. BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
140821. BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
140822. BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
140823. BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
140824. BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
140825. BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
140826. BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
140827. BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
140828. BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
140829. BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
140830. BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
140831. BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
140832. BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
140833. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
140834. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
140835. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
140836. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
140837. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
140838. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
140839. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
140840. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
140841. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
140842. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
140843. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
140844. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
140845. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
140846. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
140847. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
140848. BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
140849. BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK
140850. BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
140851. BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK
140852. BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
140853. BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK
140854. BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
140855. BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK
140856. BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
140857. BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140858. BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140859. BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140860. BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140861. BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
140862. BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
140863. BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140864. BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140865. BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140866. BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140867. BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140868. BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140869. BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140870. BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140871. BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
140872. BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
140873. BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140874. BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140875. BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140876. BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140877. BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140878. BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140879. BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140880. BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140881. BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
140882. BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
140883. BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140884. BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140885. BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140886. BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140887. BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140888. BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140889. BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140890. BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140891. BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
140892. BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
140893. BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140894. BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140895. BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140896. BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140897. BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140898. BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140899. BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140900. BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140901. BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
140902. BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
140903. BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140904. BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140905. BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140906. BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140907. BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140908. BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140909. BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140910. BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140911. BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
140912. BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
140913. BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140914. BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140915. BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140916. BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140917. BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140918. BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140919. BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140920. BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140921. BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
140922. BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
140923. BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140924. BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140925. BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140926. BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140927. BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140928. BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140929. BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140930. BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140931. BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
140932. BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
140933. BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140934. BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140935. BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140936. BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140937. BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140938. BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140939. BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140940. BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140941. BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
140942. BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
140943. BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140944. BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140945. BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140946. BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140947. BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140948. BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140949. BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140950. BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140951. BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
140952. BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
140953. BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140954. BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140955. BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140956. BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140957. BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140958. BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140959. BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140960. BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140961. BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
140962. BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
140963. BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140964. BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140965. BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140966. BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140967. BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140968. BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140969. BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140970. BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140971. BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
140972. BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
140973. BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140974. BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140975. BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140976. BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140977. BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140978. BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140979. BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140980. BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140981. BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
140982. BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
140983. BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140984. BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140985. BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140986. BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140987. BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140988. BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140989. BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
140990. BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
140991. BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
140992. BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
140993. BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
140994. BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
140995. BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
140996. BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
140997. BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
140998. BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
140999. BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
141000. BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
141001. BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
141002. BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
141003. BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
141004. BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
141005. BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
141006. BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
141007. BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
141008. BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
141009. BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
141010. BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
141011. BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
141012. BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
141013. BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
141014. BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
141015. BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
141016. BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
141017. BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
141018. BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
141019. BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
141020. BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
141021. BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
141022. BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
141023. BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
141024. BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
141025. BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
141026. BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
141027. BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
141028. BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
141029. BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
141030. BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
141031. BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
141032. BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
141033. BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
141034. BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
141035. BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
141036. BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
141037. BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
141038. BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
141039. BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
141040. BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
141041. BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
141042. BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
141043. BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
141044. BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
141045. BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
141046. BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
141047. BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
141048. BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
141049. BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
141050. BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
141051. BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
141052. BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
141053. BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
141054. BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
141055. BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
141056. BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
141057. BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
141058. BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
141059. BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
141060. BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
141061. BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
141062. BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
141063. BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP_MASK
141064. BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
141065. BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK
141066. BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT
141067. BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE_MASK
141068. BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE__SHIFT
141069. BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
141070. BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
141071. BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
141072. BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
141073. BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
141074. BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
141075. BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
141076. BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
141077. BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
141078. BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
141079. BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
141080. BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
141081. BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK
141082. BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT
141083. BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK
141084. BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT
141085. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK
141086. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT
141087. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK
141088. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT
141089. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK
141090. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT
141091. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK
141092. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT
141093. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK
141094. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT
141095. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK
141096. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT
141097. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK
141098. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT
141099. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK
141100. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT
141101. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK
141102. BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT
141103. BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
141104. BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
141105. BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
141106. BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
141107. BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
141108. BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
141109. BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK
141110. BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
141111. BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
141112. BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
141113. BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
141114. BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
141115. BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
141116. BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
141117. BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
141118. BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
141119. BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
141120. BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
141121. BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
141122. BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
141123. BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
141124. BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
141125. BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
141126. BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
141127. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
141128. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
141129. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
141130. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
141131. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
141132. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
141133. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
141134. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
141135. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
141136. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
141137. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
141138. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
141139. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
141140. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
141141. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
141142. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
141143. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
141144. BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
141145. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
141146. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
141147. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
141148. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
141149. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
141150. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
141151. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
141152. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
141153. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
141154. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
141155. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
141156. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
141157. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
141158. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
141159. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK
141160. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
141161. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
141162. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
141163. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
141164. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
141165. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
141166. BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
141167. BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
141168. BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
141169. BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
141170. BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
141171. BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
141172. BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
141173. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK
141174. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT
141175. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK
141176. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT
141177. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK
141178. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT
141179. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
141180. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
141181. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK
141182. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT
141183. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK
141184. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT
141185. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK
141186. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT
141187. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK
141188. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT
141189. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK
141190. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT
141191. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK
141192. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
141193. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK
141194. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT
141195. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK
141196. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT
141197. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK
141198. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT
141199. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK
141200. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT
141201. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK
141202. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT
141203. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK
141204. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT
141205. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK
141206. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT
141207. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK
141208. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT
141209. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK
141210. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT
141211. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK
141212. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT
141213. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK
141214. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT
141215. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK
141216. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT
141217. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK
141218. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT
141219. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK
141220. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT
141221. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK
141222. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT
141223. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK
141224. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT
141225. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK
141226. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT
141227. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK
141228. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT
141229. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK
141230. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT
141231. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK
141232. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT
141233. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK
141234. BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT
141235. BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
141236. BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
141237. BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
141238. BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
141239. BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
141240. BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
141241. BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
141242. BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
141243. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
141244. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
141245. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
141246. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
141247. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
141248. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
141249. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
141250. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
141251. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
141252. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
141253. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
141254. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
141255. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
141256. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
141257. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
141258. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
141259. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
141260. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
141261. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
141262. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
141263. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
141264. BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
141265. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
141266. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
141267. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
141268. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
141269. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
141270. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
141271. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
141272. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
141273. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
141274. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
141275. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
141276. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
141277. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
141278. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
141279. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
141280. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
141281. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
141282. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
141283. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
141284. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
141285. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
141286. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
141287. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
141288. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
141289. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
141290. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
141291. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
141292. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
141293. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
141294. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
141295. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
141296. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
141297. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
141298. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
141299. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
141300. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
141301. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
141302. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
141303. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
141304. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
141305. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
141306. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
141307. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
141308. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
141309. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
141310. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
141311. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
141312. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
141313. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
141314. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
141315. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
141316. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
141317. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
141318. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
141319. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
141320. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
141321. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
141322. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
141323. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
141324. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
141325. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
141326. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
141327. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
141328. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
141329. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
141330. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
141331. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
141332. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
141333. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
141334. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
141335. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
141336. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
141337. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
141338. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
141339. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
141340. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
141341. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
141342. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
141343. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
141344. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
141345. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
141346. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
141347. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
141348. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
141349. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
141350. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
141351. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
141352. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
141353. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
141354. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
141355. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
141356. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
141357. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
141358. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
141359. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
141360. BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
141361. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
141362. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
141363. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
141364. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
141365. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
141366. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
141367. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
141368. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
141369. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
141370. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
141371. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
141372. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
141373. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
141374. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
141375. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
141376. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
141377. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
141378. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
141379. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
141380. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
141381. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
141382. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
141383. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
141384. BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
141385. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
141386. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
141387. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
141388. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
141389. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
141390. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
141391. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
141392. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
141393. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
141394. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
141395. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
141396. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
141397. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
141398. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
141399. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
141400. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
141401. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
141402. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
141403. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
141404. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
141405. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
141406. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
141407. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
141408. BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
141409. BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
141410. BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
141411. BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
141412. BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
141413. BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
141414. BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
141415. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
141416. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
141417. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
141418. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
141419. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK
141420. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT
141421. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK
141422. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT
141423. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK
141424. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT
141425. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
141426. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
141427. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
141428. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
141429. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
141430. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
141431. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK
141432. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT
141433. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK
141434. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT
141435. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK
141436. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT
141437. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK
141438. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT
141439. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK
141440. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT
141441. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK
141442. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT
141443. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK
141444. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT
141445. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK
141446. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT
141447. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK
141448. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT
141449. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK
141450. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT
141451. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK
141452. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT
141453. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK
141454. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT
141455. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK
141456. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT
141457. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK
141458. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT
141459. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK
141460. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT
141461. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK
141462. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT
141463. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK
141464. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT
141465. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK
141466. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT
141467. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK
141468. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT
141469. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK
141470. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT
141471. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK
141472. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT
141473. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK
141474. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT
141475. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK
141476. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT
141477. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK
141478. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT
141479. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK
141480. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT
141481. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK
141482. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT
141483. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK
141484. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT
141485. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK
141486. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT
141487. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK
141488. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT
141489. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK
141490. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT
141491. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK
141492. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT
141493. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK
141494. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT
141495. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK
141496. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT
141497. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK
141498. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT
141499. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK
141500. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT
141501. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK
141502. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT
141503. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK
141504. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT
141505. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK
141506. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT
141507. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK
141508. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT
141509. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK
141510. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT
141511. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK
141512. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT
141513. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK
141514. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT
141515. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK
141516. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT
141517. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK
141518. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT
141519. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK
141520. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT
141521. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK
141522. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT
141523. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK
141524. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT
141525. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK
141526. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT
141527. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK
141528. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT
141529. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK
141530. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT
141531. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK
141532. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT
141533. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK
141534. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT
141535. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK
141536. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT
141537. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK
141538. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT
141539. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK
141540. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT
141541. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK
141542. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT
141543. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK
141544. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT
141545. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK
141546. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT
141547. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK
141548. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT
141549. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK
141550. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT
141551. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK
141552. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT
141553. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK
141554. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT
141555. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK
141556. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT
141557. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK
141558. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT
141559. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK
141560. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT
141561. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK
141562. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT
141563. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK
141564. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT
141565. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK
141566. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT
141567. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK
141568. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT
141569. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK
141570. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT
141571. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK
141572. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT
141573. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK
141574. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT
141575. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK
141576. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT
141577. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK
141578. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT
141579. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK
141580. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT
141581. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK
141582. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT
141583. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK
141584. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT
141585. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK
141586. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT
141587. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK
141588. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT
141589. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK
141590. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT
141591. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK
141592. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT
141593. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK
141594. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT
141595. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK
141596. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT
141597. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK
141598. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT
141599. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK
141600. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT
141601. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK
141602. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT
141603. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK
141604. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT
141605. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK
141606. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT
141607. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK
141608. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT
141609. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK
141610. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT
141611. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK
141612. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT
141613. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK
141614. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT
141615. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK
141616. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT
141617. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK
141618. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT
141619. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK
141620. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT
141621. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK
141622. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT
141623. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK
141624. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT
141625. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK
141626. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT
141627. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK
141628. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT
141629. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK
141630. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT
141631. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK
141632. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT
141633. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK
141634. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
141635. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK
141636. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
141637. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK
141638. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT
141639. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK
141640. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT
141641. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK
141642. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT
141643. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK
141644. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT
141645. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK
141646. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
141647. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK
141648. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
141649. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK
141650. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT
141651. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK
141652. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT
141653. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK
141654. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
141655. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK
141656. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
141657. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK
141658. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT
141659. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK
141660. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT
141661. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK
141662. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
141663. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK
141664. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
141665. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK
141666. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT
141667. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK
141668. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT
141669. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK
141670. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT
141671. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK
141672. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT
141673. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK
141674. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT
141675. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK
141676. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT
141677. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK
141678. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT
141679. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK
141680. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT
141681. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK
141682. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT
141683. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK
141684. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT
141685. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK
141686. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT
141687. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK
141688. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT
141689. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK
141690. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT
141691. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK
141692. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT
141693. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK
141694. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT
141695. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK
141696. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT
141697. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK
141698. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT
141699. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK
141700. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT
141701. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK
141702. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT
141703. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK
141704. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT
141705. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK
141706. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT
141707. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK
141708. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT
141709. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK
141710. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT
141711. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK
141712. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT
141713. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK
141714. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT
141715. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK
141716. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT
141717. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK
141718. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT
141719. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK
141720. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT
141721. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK
141722. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT
141723. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK
141724. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT
141725. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK
141726. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT
141727. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK
141728. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT
141729. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK
141730. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT
141731. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK
141732. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT
141733. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK
141734. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT
141735. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK
141736. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT
141737. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK
141738. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT
141739. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK
141740. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT
141741. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK
141742. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT
141743. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK
141744. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT
141745. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK
141746. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT
141747. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK
141748. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT
141749. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK
141750. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT
141751. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK
141752. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT
141753. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK
141754. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT
141755. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK
141756. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT
141757. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK
141758. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT
141759. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK
141760. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT
141761. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK
141762. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT
141763. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK
141764. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT
141765. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK
141766. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT
141767. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK
141768. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT
141769. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK
141770. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT
141771. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK
141772. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT
141773. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK
141774. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT
141775. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK
141776. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT
141777. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK
141778. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT
141779. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK
141780. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT
141781. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK
141782. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT
141783. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK
141784. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT
141785. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK
141786. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT
141787. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK
141788. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT
141789. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK
141790. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT
141791. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK
141792. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT
141793. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK
141794. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT
141795. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK
141796. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT
141797. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK
141798. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT
141799. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK
141800. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT
141801. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK
141802. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT
141803. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK
141804. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT
141805. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK
141806. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT
141807. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK
141808. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT
141809. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK
141810. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT
141811. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK
141812. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT
141813. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK
141814. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT
141815. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK
141816. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT
141817. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK
141818. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT
141819. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK
141820. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT
141821. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK
141822. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT
141823. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK
141824. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT
141825. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK
141826. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT
141827. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK
141828. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT
141829. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK
141830. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT
141831. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK
141832. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT
141833. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK
141834. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT
141835. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK
141836. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT
141837. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK
141838. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT
141839. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK
141840. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT
141841. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK
141842. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT
141843. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK
141844. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT
141845. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK
141846. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT
141847. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK
141848. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT
141849. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK
141850. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT
141851. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK
141852. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT
141853. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK
141854. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT
141855. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK
141856. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT
141857. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK
141858. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT
141859. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK
141860. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT
141861. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK
141862. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT
141863. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK
141864. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT
141865. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK
141866. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT
141867. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK
141868. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT
141869. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK
141870. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT
141871. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK
141872. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT
141873. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK
141874. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT
141875. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
141876. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
141877. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
141878. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
141879. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
141880. BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
141881. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK
141882. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
141883. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK
141884. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT
141885. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK
141886. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT
141887. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK
141888. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT
141889. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK
141890. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
141891. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK
141892. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT
141893. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK
141894. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT
141895. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK
141896. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT
141897. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK
141898. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
141899. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK
141900. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT
141901. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK
141902. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT
141903. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK
141904. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT
141905. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK
141906. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
141907. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK
141908. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT
141909. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK
141910. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT
141911. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK
141912. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT
141913. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK
141914. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
141915. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK
141916. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT
141917. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK
141918. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT
141919. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK
141920. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT
141921. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK
141922. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT
141923. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK
141924. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT
141925. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK
141926. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT
141927. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK
141928. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT
141929. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK
141930. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
141931. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK
141932. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
141933. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
141934. BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
141935. BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK
141936. BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT
141937. BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK
141938. BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT
141939. BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK
141940. BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT
141941. BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK
141942. BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT
141943. BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK
141944. BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT
141945. BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
141946. BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
141947. BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
141948. BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
141949. BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK
141950. BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT
141951. BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK
141952. BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT
141953. BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK
141954. BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT
141955. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
141956. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
141957. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
141958. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
141959. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK
141960. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
141961. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK
141962. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
141963. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
141964. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
141965. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK
141966. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT
141967. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK
141968. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
141969. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK
141970. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
141971. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK
141972. BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
141973. BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK
141974. BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
141975. BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK
141976. BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT
141977. BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK
141978. BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT
141979. BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK
141980. BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
141981. BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK
141982. BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT
141983. BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK
141984. BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT
141985. BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK
141986. BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT
141987. BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK
141988. BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT
141989. BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK
141990. BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT
141991. BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK
141992. BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT
141993. BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK
141994. BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT
141995. BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
141996. BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
141997. BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK
141998. BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT
141999. BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK
142000. BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT
142001. BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK
142002. BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
142003. BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK
142004. BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
142005. BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
142006. BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
142007. BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK
142008. BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
142009. BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK
142010. BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT
142011. BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK
142012. BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT
142013. BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK
142014. BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT
142015. BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK
142016. BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
142017. BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK
142018. BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT
142019. BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
142020. BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
142021. BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
142022. BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
142023. BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
142024. BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
142025. BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
142026. BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
142027. BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK
142028. BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT
142029. BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK
142030. BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT
142031. BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK
142032. BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT
142033. BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK
142034. BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT
142035. BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK
142036. BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT
142037. BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK
142038. BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT
142039. BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS_MASK
142040. BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT
142041. BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP_MASK
142042. BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP__SHIFT
142043. BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP_MASK
142044. BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP__SHIFT
142045. BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT_MASK
142046. BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT__SHIFT
142047. BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
142048. BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
142049. BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR_MASK
142050. BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR__SHIFT
142051. BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
142052. BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
142053. BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING_MASK
142054. BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING__SHIFT
142055. BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN_MASK
142056. BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT
142057. BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN_MASK
142058. BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT
142059. BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS_MASK
142060. BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS__SHIFT
142061. BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN_MASK
142062. BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT
142063. BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK
142064. BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT
142065. BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
142066. BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
142067. BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK
142068. BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT
142069. BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
142070. BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
142071. BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN_MASK
142072. BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN__SHIFT
142073. BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK
142074. BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
142075. BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD_MASK
142076. BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT
142077. BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL_MASK
142078. BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL__SHIFT
142079. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
142080. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
142081. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
142082. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
142083. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
142084. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
142085. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
142086. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
142087. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
142088. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
142089. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
142090. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
142091. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
142092. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
142093. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
142094. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
142095. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
142096. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
142097. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
142098. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
142099. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
142100. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
142101. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
142102. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
142103. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
142104. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
142105. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
142106. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
142107. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
142108. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
142109. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
142110. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
142111. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
142112. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
142113. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
142114. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
142115. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
142116. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
142117. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
142118. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
142119. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
142120. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
142121. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
142122. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
142123. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK
142124. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
142125. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK
142126. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
142127. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
142128. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
142129. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
142130. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
142131. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
142132. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
142133. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK
142134. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
142135. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
142136. BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
142137. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
142138. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
142139. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
142140. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
142141. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
142142. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
142143. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
142144. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
142145. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
142146. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
142147. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
142148. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
142149. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
142150. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
142151. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
142152. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
142153. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
142154. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
142155. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK
142156. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT
142157. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK
142158. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT
142159. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
142160. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
142161. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
142162. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
142163. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK
142164. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
142165. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
142166. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
142167. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
142168. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
142169. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK
142170. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
142171. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
142172. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
142173. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
142174. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
142175. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
142176. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
142177. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
142178. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
142179. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
142180. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
142181. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
142182. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
142183. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK
142184. BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
142185. BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID_MASK
142186. BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT
142187. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED_MASK
142188. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT
142189. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK
142190. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT
142191. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK
142192. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT
142193. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
142194. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
142195. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK
142196. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT
142197. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
142198. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
142199. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
142200. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
142201. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK
142202. BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT
142203. BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ_MASK
142204. BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ__SHIFT
142205. BIF_CFG_DEV0_EPF2_0_FLADJ__NFC_MASK
142206. BIF_CFG_DEV0_EPF2_0_FLADJ__NFC__SHIFT
142207. BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE_MASK
142208. BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE__SHIFT
142209. BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE_MASK
142210. BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE__SHIFT
142211. BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
142212. BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
142213. BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
142214. BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
142215. BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER_MASK
142216. BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT
142217. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
142218. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
142219. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
142220. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
142221. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
142222. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
142223. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
142224. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
142225. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RESERVED_MASK
142226. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RESERVED__SHIFT
142227. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
142228. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
142229. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
142230. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
142231. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
142232. BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
142233. BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
142234. BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
142235. BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
142236. BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
142237. BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
142238. BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
142239. BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
142240. BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
142241. BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK
142242. BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
142243. BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
142244. BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
142245. BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED_MASK
142246. BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT
142247. BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH_MASK
142248. BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT
142249. BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT_MASK
142250. BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT
142251. BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER_MASK
142252. BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT
142253. BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
142254. BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
142255. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
142256. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
142257. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
142258. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
142259. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
142260. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
142261. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
142262. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
142263. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
142264. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
142265. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
142266. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
142267. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
142268. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
142269. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK
142270. BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
142271. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
142272. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
142273. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
142274. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
142275. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
142276. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
142277. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK
142278. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
142279. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
142280. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
142281. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
142282. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
142283. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
142284. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
142285. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS_MASK
142286. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT
142287. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL_MASK
142288. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT
142289. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
142290. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
142291. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK
142292. BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT
142293. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
142294. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
142295. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
142296. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
142297. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
142298. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
142299. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
142300. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
142301. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
142302. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
142303. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
142304. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
142305. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
142306. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
142307. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
142308. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
142309. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
142310. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
142311. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
142312. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
142313. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
142314. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
142315. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
142316. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
142317. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
142318. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
142319. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
142320. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
142321. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
142322. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
142323. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
142324. BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
142325. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
142326. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
142327. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK
142328. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT
142329. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
142330. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
142331. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
142332. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
142333. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK
142334. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT
142335. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
142336. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
142337. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
142338. BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
142339. BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT_MASK
142340. BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT
142341. BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT_MASK
142342. BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT
142343. BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK
142344. BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT
142345. BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK
142346. BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
142347. BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK
142348. BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
142349. BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
142350. BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
142351. BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
142352. BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
142353. BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK
142354. BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
142355. BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
142356. BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
142357. BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
142358. BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
142359. BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
142360. BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
142361. BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK
142362. BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT
142363. BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK
142364. BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
142365. BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK
142366. BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT
142367. BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK_MASK
142368. BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK__SHIFT
142369. BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
142370. BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
142371. BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
142372. BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
142373. BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK
142374. BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
142375. BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK
142376. BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT
142377. BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
142378. BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
142379. BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
142380. BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
142381. BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
142382. BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
142383. BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
142384. BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
142385. BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK
142386. BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT
142387. BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK
142388. BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
142389. BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING_MASK
142390. BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT
142391. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
142392. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
142393. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
142394. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
142395. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
142396. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
142397. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
142398. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
142399. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
142400. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
142401. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
142402. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
142403. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
142404. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
142405. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
142406. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
142407. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
142408. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
142409. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
142410. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
142411. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
142412. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
142413. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
142414. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
142415. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
142416. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
142417. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
142418. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
142419. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
142420. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
142421. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
142422. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
142423. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
142424. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
142425. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
142426. BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
142427. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
142428. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
142429. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
142430. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
142431. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
142432. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
142433. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
142434. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
142435. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
142436. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
142437. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
142438. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
142439. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
142440. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
142441. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
142442. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
142443. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
142444. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
142445. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
142446. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
142447. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
142448. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
142449. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
142450. BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
142451. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
142452. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
142453. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
142454. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
142455. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
142456. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
142457. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
142458. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
142459. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
142460. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
142461. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
142462. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
142463. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
142464. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
142465. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
142466. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
142467. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
142468. BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
142469. BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
142470. BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
142471. BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK
142472. BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
142473. BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK
142474. BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
142475. BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
142476. BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
142477. BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
142478. BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
142479. BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK
142480. BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
142481. BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK
142482. BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
142483. BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
142484. BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
142485. BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
142486. BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
142487. BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK
142488. BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
142489. BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK
142490. BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
142491. BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
142492. BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
142493. BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
142494. BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
142495. BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK
142496. BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
142497. BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK
142498. BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
142499. BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
142500. BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
142501. BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
142502. BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
142503. BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK
142504. BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
142505. BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK
142506. BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
142507. BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
142508. BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
142509. BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
142510. BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
142511. BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK
142512. BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
142513. BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK
142514. BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
142515. BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
142516. BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
142517. BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
142518. BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
142519. BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
142520. BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
142521. BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
142522. BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
142523. BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK
142524. BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT
142525. BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK
142526. BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
142527. BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK
142528. BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT
142529. BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
142530. BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
142531. BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
142532. BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
142533. BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION_MASK
142534. BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION__SHIFT
142535. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
142536. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
142537. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
142538. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
142539. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
142540. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
142541. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
142542. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
142543. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
142544. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
142545. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
142546. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
142547. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
142548. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
142549. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
142550. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
142551. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
142552. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
142553. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
142554. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
142555. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
142556. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
142557. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
142558. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
142559. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
142560. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
142561. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
142562. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
142563. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
142564. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
142565. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
142566. BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
142567. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
142568. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
142569. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
142570. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
142571. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
142572. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
142573. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
142574. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
142575. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
142576. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
142577. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
142578. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
142579. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
142580. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
142581. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
142582. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
142583. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
142584. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
142585. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
142586. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
142587. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
142588. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
142589. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
142590. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
142591. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
142592. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
142593. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
142594. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
142595. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
142596. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
142597. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
142598. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
142599. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
142600. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
142601. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
142602. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
142603. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
142604. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
142605. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
142606. BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
142607. BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK
142608. BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
142609. BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK
142610. BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
142611. BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK
142612. BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
142613. BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK
142614. BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
142615. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
142616. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
142617. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
142618. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
142619. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
142620. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
142621. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK
142622. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
142623. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
142624. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
142625. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
142626. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
142627. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
142628. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
142629. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
142630. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
142631. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
142632. BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
142633. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
142634. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
142635. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
142636. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
142637. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
142638. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
142639. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
142640. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
142641. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
142642. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
142643. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
142644. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
142645. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
142646. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
142647. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK
142648. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
142649. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
142650. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
142651. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
142652. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
142653. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
142654. BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
142655. BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
142656. BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
142657. BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
142658. BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
142659. BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
142660. BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
142661. BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
142662. BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
142663. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
142664. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
142665. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
142666. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
142667. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
142668. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
142669. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
142670. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
142671. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
142672. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
142673. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
142674. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
142675. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
142676. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
142677. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
142678. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
142679. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
142680. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
142681. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
142682. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
142683. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
142684. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
142685. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK
142686. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT
142687. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK
142688. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT
142689. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK
142690. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT
142691. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK
142692. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT
142693. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK
142694. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT
142695. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK
142696. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT
142697. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK
142698. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT
142699. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK
142700. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT
142701. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK
142702. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT
142703. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK
142704. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT
142705. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK
142706. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT
142707. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK
142708. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT
142709. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK
142710. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT
142711. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK
142712. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT
142713. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK
142714. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT
142715. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK
142716. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT
142717. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK
142718. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT
142719. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK
142720. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT
142721. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK
142722. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT
142723. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK
142724. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT
142725. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK
142726. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT
142727. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK
142728. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT
142729. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK
142730. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT
142731. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK
142732. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT
142733. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK
142734. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT
142735. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK
142736. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT
142737. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK
142738. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT
142739. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK
142740. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT
142741. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK
142742. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT
142743. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK
142744. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT
142745. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK
142746. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT
142747. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK
142748. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT
142749. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK
142750. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT
142751. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK
142752. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT
142753. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK
142754. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT
142755. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK
142756. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT
142757. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK
142758. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT
142759. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK
142760. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT
142761. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK
142762. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT
142763. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK
142764. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT
142765. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK
142766. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT
142767. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK
142768. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT
142769. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK
142770. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT
142771. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK
142772. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT
142773. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK
142774. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT
142775. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK
142776. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT
142777. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK
142778. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT
142779. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK
142780. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT
142781. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK
142782. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT
142783. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK
142784. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT
142785. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK
142786. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT
142787. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK
142788. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT
142789. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK
142790. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT
142791. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK
142792. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT
142793. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK
142794. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT
142795. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK
142796. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT
142797. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK
142798. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT
142799. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK
142800. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT
142801. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK
142802. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT
142803. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK
142804. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT
142805. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK
142806. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT
142807. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK
142808. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT
142809. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK
142810. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT
142811. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK
142812. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT
142813. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK
142814. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT
142815. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK
142816. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT
142817. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK
142818. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT
142819. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK
142820. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT
142821. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK
142822. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT
142823. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK
142824. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT
142825. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK
142826. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT
142827. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK
142828. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT
142829. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK
142830. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT
142831. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK
142832. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT
142833. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK
142834. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT
142835. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK
142836. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT
142837. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK
142838. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT
142839. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK
142840. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT
142841. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK
142842. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT
142843. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK
142844. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT
142845. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK
142846. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT
142847. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK
142848. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT
142849. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK
142850. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT
142851. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK
142852. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT
142853. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK
142854. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT
142855. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK
142856. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT
142857. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK
142858. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT
142859. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK
142860. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT
142861. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK
142862. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT
142863. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK
142864. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT
142865. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK
142866. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT
142867. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK
142868. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT
142869. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK
142870. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT
142871. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK
142872. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT
142873. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK
142874. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT
142875. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK
142876. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT
142877. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK
142878. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT
142879. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK
142880. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT
142881. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK
142882. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT
142883. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK
142884. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT
142885. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK
142886. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT
142887. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK
142888. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT
142889. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK
142890. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT
142891. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK
142892. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT
142893. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK
142894. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT
142895. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK
142896. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT
142897. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK
142898. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT
142899. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK
142900. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT
142901. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK
142902. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT
142903. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK
142904. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT
142905. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK
142906. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT
142907. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK
142908. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT
142909. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK
142910. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT
142911. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK
142912. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT
142913. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK
142914. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT
142915. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK
142916. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT
142917. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK
142918. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT
142919. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK
142920. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT
142921. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK
142922. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT
142923. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK
142924. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT
142925. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK
142926. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT
142927. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK
142928. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT
142929. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK
142930. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT
142931. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK
142932. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT
142933. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK
142934. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT
142935. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK
142936. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT
142937. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK
142938. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT
142939. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK
142940. BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT
142941. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
142942. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
142943. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
142944. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
142945. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
142946. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
142947. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
142948. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
142949. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
142950. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
142951. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
142952. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
142953. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
142954. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
142955. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
142956. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
142957. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
142958. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
142959. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
142960. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
142961. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
142962. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
142963. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
142964. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
142965. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
142966. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
142967. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
142968. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
142969. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
142970. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
142971. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
142972. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
142973. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
142974. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
142975. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
142976. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
142977. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
142978. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
142979. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
142980. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
142981. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
142982. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
142983. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
142984. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
142985. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
142986. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
142987. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
142988. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
142989. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
142990. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
142991. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
142992. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
142993. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
142994. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
142995. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
142996. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
142997. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
142998. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
142999. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
143000. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
143001. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
143002. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
143003. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
143004. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
143005. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
143006. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
143007. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
143008. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
143009. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
143010. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
143011. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
143012. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
143013. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
143014. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
143015. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
143016. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
143017. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
143018. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
143019. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
143020. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
143021. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
143022. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
143023. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
143024. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
143025. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
143026. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
143027. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
143028. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
143029. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
143030. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
143031. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
143032. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
143033. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
143034. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
143035. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
143036. BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
143037. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
143038. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
143039. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
143040. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
143041. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
143042. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
143043. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
143044. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
143045. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
143046. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
143047. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
143048. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
143049. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
143050. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
143051. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
143052. BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
143053. BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK
143054. BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT
143055. BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK
143056. BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
143057. BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT_MASK
143058. BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT
143059. BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT_MASK
143060. BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT
143061. BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT_MASK
143062. BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT
143063. BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
143064. BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
143065. BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
143066. BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
143067. BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK_MASK
143068. BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT
143069. BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT_MASK
143070. BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT
143071. BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION_MASK
143072. BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION__SHIFT
143073. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
143074. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
143075. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
143076. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
143077. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
143078. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
143079. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
143080. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
143081. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
143082. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
143083. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK
143084. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT
143085. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK
143086. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
143087. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK
143088. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
143089. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK
143090. BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
143091. BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK
143092. BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
143093. BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK
143094. BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT
143095. BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK
143096. BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT
143097. BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK
143098. BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
143099. BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID_MASK
143100. BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT
143101. BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK
143102. BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT
143103. BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
143104. BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
143105. BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
143106. BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
143107. BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
143108. BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
143109. BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
143110. BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
143111. BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
143112. BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
143113. BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
143114. BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
143115. BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK
143116. BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT
143117. BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK
143118. BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT
143119. BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK
143120. BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
143121. BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK
143122. BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
143123. BIF_CFG_DEV0_EPF2_0_SBRN__SBRN_MASK
143124. BIF_CFG_DEV0_EPF2_0_SBRN__SBRN__SHIFT
143125. BIF_CFG_DEV0_EPF2_0_SLOT_CAP2__RESERVED_MASK
143126. BIF_CFG_DEV0_EPF2_0_SLOT_CAP2__RESERVED__SHIFT
143127. BIF_CFG_DEV0_EPF2_0_SLOT_CNTL2__RESERVED_MASK
143128. BIF_CFG_DEV0_EPF2_0_SLOT_CNTL2__RESERVED__SHIFT
143129. BIF_CFG_DEV0_EPF2_0_SLOT_STATUS2__RESERVED_MASK
143130. BIF_CFG_DEV0_EPF2_0_SLOT_STATUS2__RESERVED__SHIFT
143131. BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST_MASK
143132. BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST__SHIFT
143133. BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING_MASK
143134. BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT
143135. BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK
143136. BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT
143137. BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK
143138. BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT
143139. BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS_MASK
143140. BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS__SHIFT
143141. BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
143142. BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
143143. BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK
143144. BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
143145. BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP_MASK
143146. BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP__SHIFT
143147. BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_EN_MASK
143148. BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_EN__SHIFT
143149. BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK
143150. BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
143151. BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK
143152. BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
143153. BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
143154. BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
143155. BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK
143156. BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
143157. BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS_MASK
143158. BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT
143159. BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK
143160. BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT
143161. BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK
143162. BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT
143163. BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK
143164. BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
143165. BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID_MASK
143166. BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT
143167. BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
143168. BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
143169. BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
143170. BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
143171. BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
143172. BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
143173. BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
143174. BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
143175. BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK
143176. BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT
143177. BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK
143178. BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT
143179. BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK
143180. BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT
143181. BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK
143182. BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT
143183. BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK
143184. BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT
143185. BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK
143186. BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT
143187. BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS_MASK
143188. BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT
143189. BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP_MASK
143190. BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP__SHIFT
143191. BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP_MASK
143192. BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP__SHIFT
143193. BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT_MASK
143194. BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT__SHIFT
143195. BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
143196. BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
143197. BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR_MASK
143198. BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR__SHIFT
143199. BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
143200. BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
143201. BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING_MASK
143202. BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING__SHIFT
143203. BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN_MASK
143204. BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT
143205. BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN_MASK
143206. BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT
143207. BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS_MASK
143208. BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS__SHIFT
143209. BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN_MASK
143210. BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT
143211. BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK
143212. BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT
143213. BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
143214. BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
143215. BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK
143216. BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT
143217. BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
143218. BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
143219. BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN_MASK
143220. BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN__SHIFT
143221. BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK
143222. BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
143223. BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD_MASK
143224. BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT
143225. BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL_MASK
143226. BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL__SHIFT
143227. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
143228. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
143229. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
143230. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
143231. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
143232. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
143233. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
143234. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
143235. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
143236. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
143237. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
143238. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
143239. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
143240. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
143241. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
143242. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
143243. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
143244. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
143245. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
143246. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
143247. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
143248. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
143249. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
143250. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
143251. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
143252. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
143253. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
143254. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
143255. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
143256. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
143257. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
143258. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
143259. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
143260. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
143261. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
143262. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
143263. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
143264. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
143265. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
143266. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
143267. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
143268. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
143269. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
143270. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
143271. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK
143272. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
143273. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK
143274. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
143275. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
143276. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
143277. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
143278. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
143279. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
143280. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
143281. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK
143282. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
143283. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
143284. BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
143285. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
143286. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
143287. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
143288. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
143289. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
143290. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
143291. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
143292. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
143293. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
143294. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
143295. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
143296. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
143297. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
143298. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
143299. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
143300. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
143301. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
143302. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
143303. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK
143304. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT
143305. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK
143306. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT
143307. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
143308. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
143309. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
143310. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
143311. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK
143312. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
143313. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
143314. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
143315. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
143316. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
143317. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK
143318. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
143319. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
143320. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
143321. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
143322. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
143323. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
143324. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
143325. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
143326. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
143327. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
143328. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
143329. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
143330. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
143331. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK
143332. BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
143333. BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID_MASK
143334. BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT
143335. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED_MASK
143336. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT
143337. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK
143338. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT
143339. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK
143340. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT
143341. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
143342. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
143343. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK
143344. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT
143345. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
143346. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
143347. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
143348. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
143349. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK
143350. BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT
143351. BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ_MASK
143352. BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ__SHIFT
143353. BIF_CFG_DEV0_EPF2_1_FLADJ__NFC_MASK
143354. BIF_CFG_DEV0_EPF2_1_FLADJ__NFC__SHIFT
143355. BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE_MASK
143356. BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE__SHIFT
143357. BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE_MASK
143358. BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE__SHIFT
143359. BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
143360. BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
143361. BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
143362. BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
143363. BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER_MASK
143364. BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT
143365. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
143366. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
143367. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
143368. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
143369. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
143370. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
143371. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
143372. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
143373. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RESERVED_MASK
143374. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RESERVED__SHIFT
143375. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
143376. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
143377. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
143378. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
143379. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
143380. BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
143381. BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
143382. BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
143383. BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
143384. BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
143385. BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
143386. BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
143387. BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
143388. BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
143389. BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK
143390. BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
143391. BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
143392. BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
143393. BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED_MASK
143394. BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT
143395. BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH_MASK
143396. BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT
143397. BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT_MASK
143398. BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT
143399. BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER_MASK
143400. BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT
143401. BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
143402. BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
143403. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
143404. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
143405. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
143406. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
143407. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
143408. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
143409. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
143410. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
143411. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
143412. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
143413. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
143414. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
143415. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
143416. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
143417. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK
143418. BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
143419. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
143420. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
143421. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
143422. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
143423. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
143424. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
143425. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK
143426. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
143427. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
143428. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
143429. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
143430. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
143431. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
143432. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
143433. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS_MASK
143434. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT
143435. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL_MASK
143436. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT
143437. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
143438. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
143439. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK
143440. BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT
143441. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
143442. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
143443. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
143444. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
143445. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
143446. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
143447. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
143448. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
143449. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
143450. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
143451. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
143452. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
143453. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
143454. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
143455. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
143456. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
143457. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
143458. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
143459. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
143460. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
143461. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
143462. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
143463. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
143464. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
143465. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
143466. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
143467. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
143468. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
143469. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
143470. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
143471. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
143472. BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
143473. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
143474. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
143475. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK
143476. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT
143477. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
143478. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
143479. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
143480. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
143481. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK
143482. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT
143483. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
143484. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
143485. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
143486. BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
143487. BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT_MASK
143488. BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT
143489. BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT_MASK
143490. BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT
143491. BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK
143492. BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT
143493. BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK
143494. BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
143495. BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK
143496. BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
143497. BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
143498. BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
143499. BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
143500. BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
143501. BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK
143502. BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
143503. BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
143504. BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
143505. BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
143506. BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
143507. BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
143508. BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
143509. BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK
143510. BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT
143511. BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK
143512. BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
143513. BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK
143514. BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT
143515. BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK_MASK
143516. BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK__SHIFT
143517. BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
143518. BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
143519. BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
143520. BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
143521. BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK
143522. BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
143523. BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK
143524. BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT
143525. BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
143526. BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
143527. BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
143528. BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
143529. BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
143530. BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
143531. BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
143532. BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
143533. BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK
143534. BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT
143535. BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK
143536. BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
143537. BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING_MASK
143538. BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT
143539. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
143540. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
143541. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
143542. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
143543. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
143544. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
143545. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
143546. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
143547. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
143548. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
143549. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
143550. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
143551. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
143552. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
143553. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
143554. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
143555. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
143556. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
143557. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
143558. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
143559. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
143560. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
143561. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
143562. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
143563. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
143564. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
143565. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
143566. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
143567. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
143568. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
143569. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
143570. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
143571. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
143572. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
143573. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
143574. BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
143575. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
143576. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
143577. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
143578. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
143579. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
143580. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
143581. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
143582. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
143583. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
143584. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
143585. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
143586. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
143587. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
143588. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
143589. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
143590. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
143591. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
143592. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
143593. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
143594. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
143595. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
143596. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
143597. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
143598. BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
143599. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
143600. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
143601. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
143602. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
143603. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
143604. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
143605. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
143606. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
143607. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
143608. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
143609. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
143610. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
143611. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
143612. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
143613. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
143614. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
143615. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
143616. BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
143617. BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
143618. BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
143619. BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK
143620. BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
143621. BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK
143622. BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
143623. BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
143624. BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
143625. BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
143626. BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
143627. BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK
143628. BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
143629. BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK
143630. BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
143631. BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
143632. BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
143633. BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
143634. BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
143635. BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK
143636. BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
143637. BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK
143638. BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
143639. BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
143640. BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
143641. BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
143642. BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
143643. BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK
143644. BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
143645. BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK
143646. BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
143647. BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
143648. BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
143649. BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
143650. BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
143651. BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK
143652. BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
143653. BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK
143654. BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
143655. BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
143656. BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
143657. BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
143658. BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
143659. BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK
143660. BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
143661. BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK
143662. BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
143663. BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
143664. BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
143665. BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
143666. BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
143667. BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
143668. BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
143669. BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
143670. BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
143671. BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK
143672. BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT
143673. BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK
143674. BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
143675. BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK
143676. BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT
143677. BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
143678. BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
143679. BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
143680. BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
143681. BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION_MASK
143682. BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION__SHIFT
143683. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
143684. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
143685. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
143686. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
143687. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
143688. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
143689. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
143690. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
143691. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
143692. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
143693. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
143694. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
143695. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
143696. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
143697. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
143698. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
143699. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
143700. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
143701. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
143702. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
143703. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
143704. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
143705. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
143706. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
143707. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
143708. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
143709. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
143710. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
143711. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
143712. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
143713. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
143714. BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
143715. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
143716. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
143717. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
143718. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
143719. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
143720. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
143721. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
143722. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
143723. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
143724. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
143725. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
143726. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
143727. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
143728. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
143729. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
143730. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
143731. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
143732. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
143733. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
143734. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
143735. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
143736. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
143737. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
143738. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
143739. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
143740. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
143741. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
143742. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
143743. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
143744. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
143745. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
143746. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
143747. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
143748. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
143749. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
143750. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
143751. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
143752. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
143753. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
143754. BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
143755. BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK
143756. BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
143757. BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK
143758. BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
143759. BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK
143760. BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
143761. BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK
143762. BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
143763. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
143764. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
143765. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
143766. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
143767. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
143768. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
143769. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK
143770. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
143771. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
143772. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
143773. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
143774. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
143775. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
143776. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
143777. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
143778. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
143779. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
143780. BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
143781. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
143782. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
143783. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
143784. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
143785. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
143786. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
143787. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
143788. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
143789. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
143790. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
143791. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
143792. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
143793. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
143794. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
143795. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK
143796. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
143797. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
143798. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
143799. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
143800. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
143801. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
143802. BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
143803. BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
143804. BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
143805. BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
143806. BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
143807. BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
143808. BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
143809. BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
143810. BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
143811. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
143812. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
143813. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
143814. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
143815. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
143816. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
143817. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
143818. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
143819. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
143820. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
143821. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
143822. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
143823. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
143824. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
143825. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
143826. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
143827. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
143828. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
143829. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
143830. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
143831. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
143832. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
143833. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK
143834. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT
143835. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK
143836. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT
143837. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK
143838. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT
143839. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK
143840. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT
143841. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK
143842. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT
143843. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK
143844. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT
143845. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK
143846. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT
143847. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK
143848. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT
143849. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK
143850. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT
143851. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK
143852. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT
143853. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK
143854. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT
143855. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK
143856. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT
143857. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK
143858. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT
143859. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK
143860. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT
143861. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK
143862. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT
143863. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK
143864. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT
143865. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK
143866. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT
143867. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK
143868. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT
143869. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK
143870. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT
143871. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK
143872. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT
143873. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK
143874. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT
143875. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK
143876. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT
143877. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK
143878. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT
143879. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK
143880. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT
143881. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK
143882. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT
143883. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK
143884. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT
143885. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK
143886. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT
143887. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK
143888. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT
143889. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK
143890. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT
143891. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK
143892. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT
143893. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK
143894. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT
143895. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK
143896. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT
143897. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK
143898. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT
143899. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK
143900. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT
143901. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK
143902. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT
143903. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK
143904. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT
143905. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK
143906. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT
143907. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK
143908. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT
143909. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK
143910. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT
143911. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK
143912. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT
143913. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK
143914. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT
143915. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK
143916. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT
143917. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK
143918. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT
143919. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK
143920. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT
143921. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK
143922. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT
143923. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK
143924. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT
143925. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK
143926. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT
143927. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK
143928. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT
143929. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK
143930. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT
143931. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK
143932. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT
143933. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK
143934. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT
143935. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK
143936. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT
143937. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK
143938. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT
143939. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK
143940. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT
143941. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK
143942. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT
143943. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK
143944. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT
143945. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK
143946. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT
143947. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK
143948. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT
143949. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK
143950. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT
143951. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK
143952. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT
143953. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK
143954. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT
143955. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK
143956. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT
143957. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK
143958. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT
143959. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK
143960. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT
143961. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK
143962. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT
143963. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK
143964. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT
143965. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK
143966. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT
143967. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK
143968. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT
143969. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK
143970. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT
143971. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK
143972. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT
143973. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK
143974. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT
143975. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK
143976. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT
143977. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK
143978. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT
143979. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK
143980. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT
143981. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK
143982. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT
143983. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK
143984. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT
143985. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK
143986. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT
143987. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK
143988. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT
143989. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK
143990. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT
143991. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK
143992. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT
143993. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK
143994. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT
143995. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK
143996. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT
143997. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK
143998. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT
143999. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK
144000. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT
144001. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK
144002. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT
144003. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK
144004. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT
144005. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK
144006. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT
144007. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK
144008. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT
144009. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK
144010. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT
144011. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK
144012. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT
144013. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK
144014. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT
144015. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK
144016. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT
144017. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK
144018. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT
144019. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK
144020. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT
144021. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK
144022. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT
144023. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK
144024. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT
144025. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK
144026. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT
144027. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK
144028. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT
144029. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK
144030. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT
144031. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK
144032. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT
144033. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK
144034. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT
144035. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK
144036. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT
144037. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK
144038. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT
144039. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK
144040. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT
144041. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK
144042. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT
144043. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK
144044. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT
144045. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK
144046. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT
144047. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK
144048. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT
144049. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK
144050. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT
144051. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK
144052. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT
144053. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK
144054. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT
144055. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK
144056. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT
144057. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK
144058. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT
144059. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK
144060. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT
144061. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK
144062. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT
144063. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK
144064. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT
144065. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK
144066. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT
144067. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK
144068. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT
144069. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK
144070. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT
144071. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK
144072. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT
144073. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK
144074. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT
144075. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK
144076. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT
144077. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK
144078. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT
144079. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK
144080. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT
144081. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK
144082. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT
144083. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK
144084. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT
144085. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK
144086. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT
144087. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK
144088. BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT
144089. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
144090. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
144091. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
144092. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
144093. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
144094. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
144095. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
144096. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
144097. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
144098. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
144099. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
144100. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
144101. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
144102. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
144103. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
144104. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
144105. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
144106. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
144107. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
144108. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
144109. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
144110. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
144111. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
144112. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
144113. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
144114. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
144115. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
144116. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
144117. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
144118. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
144119. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
144120. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
144121. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
144122. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
144123. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
144124. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
144125. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
144126. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
144127. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
144128. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
144129. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
144130. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
144131. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
144132. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
144133. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
144134. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
144135. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
144136. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
144137. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
144138. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
144139. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
144140. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
144141. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
144142. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
144143. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
144144. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
144145. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
144146. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
144147. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
144148. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
144149. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
144150. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
144151. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
144152. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
144153. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
144154. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
144155. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
144156. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
144157. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
144158. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
144159. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
144160. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
144161. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
144162. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
144163. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
144164. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
144165. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
144166. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
144167. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
144168. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
144169. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
144170. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
144171. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
144172. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
144173. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
144174. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
144175. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
144176. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
144177. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
144178. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
144179. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
144180. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
144181. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
144182. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
144183. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
144184. BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
144185. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
144186. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
144187. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
144188. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
144189. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
144190. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
144191. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
144192. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
144193. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
144194. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
144195. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
144196. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
144197. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
144198. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
144199. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
144200. BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
144201. BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK
144202. BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT
144203. BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK
144204. BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
144205. BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT_MASK
144206. BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT
144207. BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT_MASK
144208. BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT
144209. BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT_MASK
144210. BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT
144211. BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
144212. BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
144213. BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
144214. BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
144215. BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK_MASK
144216. BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT
144217. BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT_MASK
144218. BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT
144219. BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION_MASK
144220. BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION__SHIFT
144221. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
144222. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
144223. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
144224. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
144225. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
144226. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
144227. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
144228. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
144229. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
144230. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
144231. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK
144232. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT
144233. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK
144234. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
144235. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK
144236. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
144237. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK
144238. BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
144239. BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK
144240. BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
144241. BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK
144242. BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT
144243. BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK
144244. BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT
144245. BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK
144246. BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
144247. BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__CAP_ID_MASK
144248. BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__CAP_ID__SHIFT
144249. BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__NEXT_PTR_MASK
144250. BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__NEXT_PTR__SHIFT
144251. BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
144252. BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
144253. BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
144254. BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
144255. BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
144256. BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
144257. BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
144258. BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
144259. BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
144260. BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
144261. BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
144262. BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
144263. BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA__IDP_DATA_MASK
144264. BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA__IDP_DATA__SHIFT
144265. BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_INDEX_MASK
144266. BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT
144267. BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK
144268. BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
144269. BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK
144270. BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
144271. BIF_CFG_DEV0_EPF2_1_SBRN__SBRN_MASK
144272. BIF_CFG_DEV0_EPF2_1_SBRN__SBRN__SHIFT
144273. BIF_CFG_DEV0_EPF2_1_SLOT_CAP2__RESERVED_MASK
144274. BIF_CFG_DEV0_EPF2_1_SLOT_CAP2__RESERVED__SHIFT
144275. BIF_CFG_DEV0_EPF2_1_SLOT_CNTL2__RESERVED_MASK
144276. BIF_CFG_DEV0_EPF2_1_SLOT_CNTL2__RESERVED__SHIFT
144277. BIF_CFG_DEV0_EPF2_1_SLOT_STATUS2__RESERVED_MASK
144278. BIF_CFG_DEV0_EPF2_1_SLOT_STATUS2__RESERVED__SHIFT
144279. BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST_MASK
144280. BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST__SHIFT
144281. BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING_MASK
144282. BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT
144283. BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK
144284. BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT
144285. BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS_MASK
144286. BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS__SHIFT
144287. BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS_MASK
144288. BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS__SHIFT
144289. BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
144290. BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
144291. BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK
144292. BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
144293. BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP_MASK
144294. BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP__SHIFT
144295. BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_EN_MASK
144296. BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_EN__SHIFT
144297. BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK
144298. BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
144299. BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK
144300. BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
144301. BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
144302. BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
144303. BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK
144304. BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
144305. BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS_MASK
144306. BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT
144307. BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK
144308. BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT
144309. BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK
144310. BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT
144311. BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK
144312. BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
144313. BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID_MASK
144314. BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT
144315. BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
144316. BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
144317. BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
144318. BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
144319. BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID_MASK
144320. BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
144321. BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
144322. BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
144323. BIF_CFG_DEV0_EPF2_2_BASE_ADDR_1__BASE_ADDR_MASK
144324. BIF_CFG_DEV0_EPF2_2_BASE_ADDR_1__BASE_ADDR__SHIFT
144325. BIF_CFG_DEV0_EPF2_2_BASE_ADDR_2__BASE_ADDR_MASK
144326. BIF_CFG_DEV0_EPF2_2_BASE_ADDR_2__BASE_ADDR__SHIFT
144327. BIF_CFG_DEV0_EPF2_2_BASE_ADDR_3__BASE_ADDR_MASK
144328. BIF_CFG_DEV0_EPF2_2_BASE_ADDR_3__BASE_ADDR__SHIFT
144329. BIF_CFG_DEV0_EPF2_2_BASE_ADDR_4__BASE_ADDR_MASK
144330. BIF_CFG_DEV0_EPF2_2_BASE_ADDR_4__BASE_ADDR__SHIFT
144331. BIF_CFG_DEV0_EPF2_2_BASE_ADDR_5__BASE_ADDR_MASK
144332. BIF_CFG_DEV0_EPF2_2_BASE_ADDR_5__BASE_ADDR__SHIFT
144333. BIF_CFG_DEV0_EPF2_2_BASE_ADDR_6__BASE_ADDR_MASK
144334. BIF_CFG_DEV0_EPF2_2_BASE_ADDR_6__BASE_ADDR__SHIFT
144335. BIF_CFG_DEV0_EPF2_2_BASE_CLASS__BASE_CLASS_MASK
144336. BIF_CFG_DEV0_EPF2_2_BASE_CLASS__BASE_CLASS__SHIFT
144337. BIF_CFG_DEV0_EPF2_2_BIST__BIST_CAP_MASK
144338. BIF_CFG_DEV0_EPF2_2_BIST__BIST_CAP__SHIFT
144339. BIF_CFG_DEV0_EPF2_2_BIST__BIST_COMP_MASK
144340. BIF_CFG_DEV0_EPF2_2_BIST__BIST_COMP__SHIFT
144341. BIF_CFG_DEV0_EPF2_2_BIST__BIST_STRT_MASK
144342. BIF_CFG_DEV0_EPF2_2_BIST__BIST_STRT__SHIFT
144343. BIF_CFG_DEV0_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
144344. BIF_CFG_DEV0_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
144345. BIF_CFG_DEV0_EPF2_2_CAP_PTR__CAP_PTR_MASK
144346. BIF_CFG_DEV0_EPF2_2_CAP_PTR__CAP_PTR__SHIFT
144347. BIF_CFG_DEV0_EPF2_2_COMMAND__AD_STEPPING_MASK
144348. BIF_CFG_DEV0_EPF2_2_COMMAND__AD_STEPPING__SHIFT
144349. BIF_CFG_DEV0_EPF2_2_COMMAND__BUS_MASTER_EN_MASK
144350. BIF_CFG_DEV0_EPF2_2_COMMAND__BUS_MASTER_EN__SHIFT
144351. BIF_CFG_DEV0_EPF2_2_COMMAND__FAST_B2B_EN_MASK
144352. BIF_CFG_DEV0_EPF2_2_COMMAND__FAST_B2B_EN__SHIFT
144353. BIF_CFG_DEV0_EPF2_2_COMMAND__INT_DIS_MASK
144354. BIF_CFG_DEV0_EPF2_2_COMMAND__INT_DIS__SHIFT
144355. BIF_CFG_DEV0_EPF2_2_COMMAND__IO_ACCESS_EN_MASK
144356. BIF_CFG_DEV0_EPF2_2_COMMAND__IO_ACCESS_EN__SHIFT
144357. BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_ACCESS_EN_MASK
144358. BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_ACCESS_EN__SHIFT
144359. BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
144360. BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
144361. BIF_CFG_DEV0_EPF2_2_COMMAND__PAL_SNOOP_EN_MASK
144362. BIF_CFG_DEV0_EPF2_2_COMMAND__PAL_SNOOP_EN__SHIFT
144363. BIF_CFG_DEV0_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
144364. BIF_CFG_DEV0_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
144365. BIF_CFG_DEV0_EPF2_2_COMMAND__SERR_EN_MASK
144366. BIF_CFG_DEV0_EPF2_2_COMMAND__SERR_EN__SHIFT
144367. BIF_CFG_DEV0_EPF2_2_COMMAND__SPECIAL_CYCLE_EN_MASK
144368. BIF_CFG_DEV0_EPF2_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
144369. BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESLD_MASK
144370. BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESLD__SHIFT
144371. BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESL_MASK
144372. BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESL__SHIFT
144373. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
144374. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
144375. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
144376. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
144377. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
144378. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
144379. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
144380. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
144381. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
144382. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
144383. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
144384. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
144385. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
144386. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
144387. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
144388. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
144389. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
144390. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
144391. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
144392. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
144393. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
144394. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
144395. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
144396. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
144397. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
144398. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
144399. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
144400. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
144401. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
144402. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
144403. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
144404. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
144405. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__EXTENDED_TAG_MASK
144406. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
144407. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__FLR_CAPABLE_MASK
144408. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
144409. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
144410. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
144411. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
144412. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
144413. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
144414. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
144415. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__PHANTOM_FUNC_MASK
144416. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
144417. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
144418. BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
144419. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
144420. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
144421. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
144422. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
144423. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
144424. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
144425. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
144426. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
144427. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
144428. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
144429. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
144430. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
144431. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
144432. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
144433. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
144434. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
144435. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__LTR_EN_MASK
144436. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__LTR_EN__SHIFT
144437. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__OBFF_EN_MASK
144438. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__OBFF_EN__SHIFT
144439. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
144440. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
144441. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__CORR_ERR_EN_MASK
144442. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
144443. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
144444. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
144445. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
144446. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
144447. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__INITIATE_FLR_MASK
144448. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__INITIATE_FLR__SHIFT
144449. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
144450. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
144451. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
144452. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
144453. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
144454. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
144455. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
144456. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
144457. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
144458. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
144459. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
144460. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
144461. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__USR_REPORT_EN_MASK
144462. BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
144463. BIF_CFG_DEV0_EPF2_2_DEVICE_ID__DEVICE_ID_MASK
144464. BIF_CFG_DEV0_EPF2_2_DEVICE_ID__DEVICE_ID__SHIFT
144465. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS2__RESERVED_MASK
144466. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS2__RESERVED__SHIFT
144467. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__AUX_PWR_MASK
144468. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__AUX_PWR__SHIFT
144469. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__CORR_ERR_MASK
144470. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__CORR_ERR__SHIFT
144471. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__FATAL_ERR_MASK
144472. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__FATAL_ERR__SHIFT
144473. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
144474. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
144475. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
144476. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
144477. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__USR_DETECTED_MASK
144478. BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__USR_DETECTED__SHIFT
144479. BIF_CFG_DEV0_EPF2_2_FLADJ__FLADJ_MASK
144480. BIF_CFG_DEV0_EPF2_2_FLADJ__FLADJ__SHIFT
144481. BIF_CFG_DEV0_EPF2_2_HEADER__DEVICE_TYPE_MASK
144482. BIF_CFG_DEV0_EPF2_2_HEADER__DEVICE_TYPE__SHIFT
144483. BIF_CFG_DEV0_EPF2_2_HEADER__HEADER_TYPE_MASK
144484. BIF_CFG_DEV0_EPF2_2_HEADER__HEADER_TYPE__SHIFT
144485. BIF_CFG_DEV0_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
144486. BIF_CFG_DEV0_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
144487. BIF_CFG_DEV0_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
144488. BIF_CFG_DEV0_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
144489. BIF_CFG_DEV0_EPF2_2_LATENCY__LATENCY_TIMER_MASK
144490. BIF_CFG_DEV0_EPF2_2_LATENCY__LATENCY_TIMER__SHIFT
144491. BIF_CFG_DEV0_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
144492. BIF_CFG_DEV0_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
144493. BIF_CFG_DEV0_EPF2_2_LINK_CAP2__RESERVED_MASK
144494. BIF_CFG_DEV0_EPF2_2_LINK_CAP2__RESERVED__SHIFT
144495. BIF_CFG_DEV0_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
144496. BIF_CFG_DEV0_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
144497. BIF_CFG_DEV0_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
144498. BIF_CFG_DEV0_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
144499. BIF_CFG_DEV0_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
144500. BIF_CFG_DEV0_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
144501. BIF_CFG_DEV0_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
144502. BIF_CFG_DEV0_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
144503. BIF_CFG_DEV0_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
144504. BIF_CFG_DEV0_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
144505. BIF_CFG_DEV0_EPF2_2_LINK_CAP__L1_EXIT_LATENCY_MASK
144506. BIF_CFG_DEV0_EPF2_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
144507. BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
144508. BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
144509. BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_SPEED_MASK
144510. BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_SPEED__SHIFT
144511. BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_WIDTH_MASK
144512. BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_WIDTH__SHIFT
144513. BIF_CFG_DEV0_EPF2_2_LINK_CAP__PM_SUPPORT_MASK
144514. BIF_CFG_DEV0_EPF2_2_LINK_CAP__PM_SUPPORT__SHIFT
144515. BIF_CFG_DEV0_EPF2_2_LINK_CAP__PORT_NUMBER_MASK
144516. BIF_CFG_DEV0_EPF2_2_LINK_CAP__PORT_NUMBER__SHIFT
144517. BIF_CFG_DEV0_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
144518. BIF_CFG_DEV0_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
144519. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
144520. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
144521. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
144522. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
144523. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
144524. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
144525. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
144526. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
144527. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
144528. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
144529. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
144530. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
144531. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
144532. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
144533. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__XMIT_MARGIN_MASK
144534. BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
144535. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
144536. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
144537. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
144538. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
144539. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__EXTENDED_SYNC_MASK
144540. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
144541. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
144542. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
144543. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
144544. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
144545. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
144546. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
144547. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_DIS_MASK
144548. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_DIS__SHIFT
144549. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__PM_CONTROL_MASK
144550. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__PM_CONTROL__SHIFT
144551. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
144552. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
144553. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__RETRAIN_LINK_MASK
144554. BIF_CFG_DEV0_EPF2_2_LINK_CNTL__RETRAIN_LINK__SHIFT
144555. BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
144556. BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
144557. BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
144558. BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
144559. BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
144560. BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
144561. BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
144562. BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
144563. BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
144564. BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
144565. BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
144566. BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
144567. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
144568. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
144569. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__DL_ACTIVE_MASK
144570. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__DL_ACTIVE__SHIFT
144571. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
144572. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
144573. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
144574. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
144575. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_TRAINING_MASK
144576. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_TRAINING__SHIFT
144577. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
144578. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
144579. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
144580. BIF_CFG_DEV0_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
144581. BIF_CFG_DEV0_EPF2_2_MAX_LATENCY__MAX_LAT_MASK
144582. BIF_CFG_DEV0_EPF2_2_MAX_LATENCY__MAX_LAT__SHIFT
144583. BIF_CFG_DEV0_EPF2_2_MIN_GRANT__MIN_GNT_MASK
144584. BIF_CFG_DEV0_EPF2_2_MIN_GRANT__MIN_GNT__SHIFT
144585. BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__CAP_ID_MASK
144586. BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__CAP_ID__SHIFT
144587. BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__NEXT_PTR_MASK
144588. BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT
144589. BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_EN_MASK
144590. BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT
144591. BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
144592. BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
144593. BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
144594. BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
144595. BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_BIR_MASK
144596. BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT
144597. BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK
144598. BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
144599. BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK
144600. BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
144601. BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
144602. BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
144603. BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__CAP_ID_MASK
144604. BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__CAP_ID__SHIFT
144605. BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__NEXT_PTR_MASK
144606. BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
144607. BIF_CFG_DEV0_EPF2_2_MSI_MASK_64__MSI_MASK_64_MASK
144608. BIF_CFG_DEV0_EPF2_2_MSI_MASK_64__MSI_MASK_64__SHIFT
144609. BIF_CFG_DEV0_EPF2_2_MSI_MASK__MSI_MASK_MASK
144610. BIF_CFG_DEV0_EPF2_2_MSI_MASK__MSI_MASK__SHIFT
144611. BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
144612. BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
144613. BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
144614. BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
144615. BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_64BIT_MASK
144616. BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
144617. BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_EN_MASK
144618. BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_EN__SHIFT
144619. BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
144620. BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
144621. BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
144622. BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
144623. BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
144624. BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
144625. BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
144626. BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
144627. BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA__MSI_DATA_MASK
144628. BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA__MSI_DATA__SHIFT
144629. BIF_CFG_DEV0_EPF2_2_MSI_PENDING_64__MSI_PENDING_64_MASK
144630. BIF_CFG_DEV0_EPF2_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT
144631. BIF_CFG_DEV0_EPF2_2_MSI_PENDING__MSI_PENDING_MASK
144632. BIF_CFG_DEV0_EPF2_2_MSI_PENDING__MSI_PENDING__SHIFT
144633. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
144634. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
144635. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
144636. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
144637. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
144638. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
144639. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
144640. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
144641. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
144642. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
144643. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
144644. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
144645. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
144646. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
144647. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
144648. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
144649. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
144650. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
144651. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
144652. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
144653. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
144654. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
144655. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
144656. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
144657. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
144658. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
144659. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
144660. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
144661. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
144662. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
144663. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
144664. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
144665. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
144666. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
144667. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
144668. BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
144669. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
144670. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
144671. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
144672. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
144673. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
144674. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
144675. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
144676. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
144677. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
144678. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
144679. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
144680. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
144681. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
144682. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
144683. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
144684. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
144685. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
144686. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
144687. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
144688. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
144689. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
144690. BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
144691. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
144692. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
144693. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
144694. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
144695. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
144696. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
144697. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
144698. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
144699. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
144700. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
144701. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
144702. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
144703. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
144704. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
144705. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
144706. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
144707. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
144708. BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
144709. BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
144710. BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
144711. BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK
144712. BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
144713. BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK
144714. BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
144715. BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
144716. BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
144717. BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
144718. BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
144719. BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK
144720. BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
144721. BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK
144722. BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
144723. BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
144724. BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
144725. BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
144726. BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
144727. BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK
144728. BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
144729. BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK
144730. BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
144731. BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
144732. BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
144733. BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
144734. BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
144735. BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK
144736. BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
144737. BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK
144738. BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
144739. BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
144740. BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
144741. BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
144742. BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
144743. BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK
144744. BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
144745. BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK
144746. BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
144747. BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
144748. BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
144749. BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
144750. BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
144751. BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK
144752. BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
144753. BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK
144754. BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
144755. BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
144756. BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
144757. BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
144758. BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
144759. BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
144760. BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
144761. BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
144762. BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
144763. BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__CAP_ID_MASK
144764. BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__CAP_ID__SHIFT
144765. BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__NEXT_PTR_MASK
144766. BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
144767. BIF_CFG_DEV0_EPF2_2_PCIE_CAP__DEVICE_TYPE_MASK
144768. BIF_CFG_DEV0_EPF2_2_PCIE_CAP__DEVICE_TYPE__SHIFT
144769. BIF_CFG_DEV0_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
144770. BIF_CFG_DEV0_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
144771. BIF_CFG_DEV0_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
144772. BIF_CFG_DEV0_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
144773. BIF_CFG_DEV0_EPF2_2_PCIE_CAP__VERSION_MASK
144774. BIF_CFG_DEV0_EPF2_2_PCIE_CAP__VERSION__SHIFT
144775. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
144776. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
144777. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
144778. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
144779. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
144780. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
144781. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
144782. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
144783. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
144784. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
144785. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
144786. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
144787. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
144788. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
144789. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
144790. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
144791. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
144792. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
144793. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
144794. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
144795. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
144796. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
144797. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
144798. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
144799. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
144800. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
144801. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
144802. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
144803. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
144804. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
144805. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
144806. BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
144807. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
144808. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
144809. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
144810. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
144811. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
144812. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
144813. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
144814. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
144815. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
144816. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
144817. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
144818. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
144819. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
144820. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
144821. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
144822. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
144823. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
144824. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
144825. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
144826. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
144827. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
144828. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
144829. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
144830. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
144831. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
144832. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
144833. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
144834. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
144835. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
144836. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
144837. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
144838. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
144839. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
144840. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
144841. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
144842. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
144843. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
144844. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
144845. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
144846. BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
144847. BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG0__TLP_HDR_MASK
144848. BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
144849. BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG1__TLP_HDR_MASK
144850. BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
144851. BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG2__TLP_HDR_MASK
144852. BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
144853. BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG3__TLP_HDR_MASK
144854. BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
144855. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
144856. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
144857. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
144858. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
144859. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
144860. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
144861. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
144862. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
144863. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
144864. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
144865. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
144866. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
144867. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
144868. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
144869. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK
144870. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
144871. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
144872. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
144873. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
144874. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
144875. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
144876. BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
144877. BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
144878. BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
144879. BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
144880. BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
144881. BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
144882. BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
144883. BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
144884. BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
144885. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
144886. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
144887. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
144888. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
144889. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
144890. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
144891. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
144892. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
144893. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
144894. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
144895. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
144896. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
144897. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
144898. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
144899. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
144900. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
144901. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
144902. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
144903. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
144904. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
144905. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
144906. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
144907. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
144908. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
144909. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
144910. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
144911. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
144912. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
144913. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
144914. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
144915. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
144916. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
144917. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
144918. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
144919. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
144920. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
144921. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
144922. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
144923. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
144924. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
144925. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
144926. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
144927. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
144928. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
144929. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
144930. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
144931. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
144932. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
144933. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
144934. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
144935. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
144936. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
144937. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
144938. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
144939. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
144940. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
144941. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
144942. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
144943. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
144944. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
144945. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
144946. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
144947. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
144948. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
144949. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
144950. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
144951. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
144952. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
144953. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
144954. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
144955. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
144956. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
144957. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
144958. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
144959. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
144960. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
144961. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
144962. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
144963. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
144964. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
144965. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
144966. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
144967. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
144968. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
144969. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
144970. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
144971. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
144972. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
144973. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
144974. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
144975. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
144976. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
144977. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
144978. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
144979. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
144980. BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
144981. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
144982. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
144983. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
144984. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
144985. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
144986. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
144987. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
144988. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
144989. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
144990. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
144991. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
144992. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
144993. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
144994. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
144995. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
144996. BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
144997. BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__CAP_ID_MASK
144998. BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__CAP_ID__SHIFT
144999. BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__NEXT_PTR_MASK
145000. BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
145001. BIF_CFG_DEV0_EPF2_2_PMI_CAP__AUX_CURRENT_MASK
145002. BIF_CFG_DEV0_EPF2_2_PMI_CAP__AUX_CURRENT__SHIFT
145003. BIF_CFG_DEV0_EPF2_2_PMI_CAP__D1_SUPPORT_MASK
145004. BIF_CFG_DEV0_EPF2_2_PMI_CAP__D1_SUPPORT__SHIFT
145005. BIF_CFG_DEV0_EPF2_2_PMI_CAP__D2_SUPPORT_MASK
145006. BIF_CFG_DEV0_EPF2_2_PMI_CAP__D2_SUPPORT__SHIFT
145007. BIF_CFG_DEV0_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
145008. BIF_CFG_DEV0_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
145009. BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_CLOCK_MASK
145010. BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_CLOCK__SHIFT
145011. BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_SUPPORT_MASK
145012. BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_SUPPORT__SHIFT
145013. BIF_CFG_DEV0_EPF2_2_PMI_CAP__VERSION_MASK
145014. BIF_CFG_DEV0_EPF2_2_PMI_CAP__VERSION__SHIFT
145015. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
145016. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
145017. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
145018. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
145019. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
145020. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
145021. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
145022. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
145023. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
145024. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
145025. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_EN_MASK
145026. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_EN__SHIFT
145027. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_STATUS_MASK
145028. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
145029. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PMI_DATA_MASK
145030. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
145031. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__POWER_STATE_MASK
145032. BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
145033. BIF_CFG_DEV0_EPF2_2_PROG_INTERFACE__PROG_INTERFACE_MASK
145034. BIF_CFG_DEV0_EPF2_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
145035. BIF_CFG_DEV0_EPF2_2_REVISION_ID__MAJOR_REV_ID_MASK
145036. BIF_CFG_DEV0_EPF2_2_REVISION_ID__MAJOR_REV_ID__SHIFT
145037. BIF_CFG_DEV0_EPF2_2_REVISION_ID__MINOR_REV_ID_MASK
145038. BIF_CFG_DEV0_EPF2_2_REVISION_ID__MINOR_REV_ID__SHIFT
145039. BIF_CFG_DEV0_EPF2_2_ROM_BASE_ADDR__BASE_ADDR_MASK
145040. BIF_CFG_DEV0_EPF2_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT
145041. BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__CAP_ID_MASK
145042. BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__CAP_ID__SHIFT
145043. BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__NEXT_PTR_MASK
145044. BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__NEXT_PTR__SHIFT
145045. BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
145046. BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
145047. BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
145048. BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
145049. BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
145050. BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
145051. BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
145052. BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
145053. BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
145054. BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
145055. BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
145056. BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
145057. BIF_CFG_DEV0_EPF2_2_SATA_IDP_DATA__IDP_DATA_MASK
145058. BIF_CFG_DEV0_EPF2_2_SATA_IDP_DATA__IDP_DATA__SHIFT
145059. BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_INDEX_MASK
145060. BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT
145061. BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK
145062. BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
145063. BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK
145064. BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
145065. BIF_CFG_DEV0_EPF2_2_SBRN__SBRN_MASK
145066. BIF_CFG_DEV0_EPF2_2_SBRN__SBRN__SHIFT
145067. BIF_CFG_DEV0_EPF2_2_SLOT_CAP2__RESERVED_MASK
145068. BIF_CFG_DEV0_EPF2_2_SLOT_CAP2__RESERVED__SHIFT
145069. BIF_CFG_DEV0_EPF2_2_SLOT_CNTL2__RESERVED_MASK
145070. BIF_CFG_DEV0_EPF2_2_SLOT_CNTL2__RESERVED__SHIFT
145071. BIF_CFG_DEV0_EPF2_2_SLOT_STATUS2__RESERVED_MASK
145072. BIF_CFG_DEV0_EPF2_2_SLOT_STATUS2__RESERVED__SHIFT
145073. BIF_CFG_DEV0_EPF2_2_STATUS__CAP_LIST_MASK
145074. BIF_CFG_DEV0_EPF2_2_STATUS__CAP_LIST__SHIFT
145075. BIF_CFG_DEV0_EPF2_2_STATUS__DEVSEL_TIMING_MASK
145076. BIF_CFG_DEV0_EPF2_2_STATUS__DEVSEL_TIMING__SHIFT
145077. BIF_CFG_DEV0_EPF2_2_STATUS__FAST_BACK_CAPABLE_MASK
145078. BIF_CFG_DEV0_EPF2_2_STATUS__FAST_BACK_CAPABLE__SHIFT
145079. BIF_CFG_DEV0_EPF2_2_STATUS__INT_STATUS_MASK
145080. BIF_CFG_DEV0_EPF2_2_STATUS__INT_STATUS__SHIFT
145081. BIF_CFG_DEV0_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
145082. BIF_CFG_DEV0_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
145083. BIF_CFG_DEV0_EPF2_2_STATUS__PARITY_ERROR_DETECTED_MASK
145084. BIF_CFG_DEV0_EPF2_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
145085. BIF_CFG_DEV0_EPF2_2_STATUS__PCI_66_EN_MASK
145086. BIF_CFG_DEV0_EPF2_2_STATUS__PCI_66_EN__SHIFT
145087. BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_MASTER_ABORT_MASK
145088. BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
145089. BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_TARGET_ABORT_MASK
145090. BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
145091. BIF_CFG_DEV0_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
145092. BIF_CFG_DEV0_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
145093. BIF_CFG_DEV0_EPF2_2_STATUS__SIGNAL_TARGET_ABORT_MASK
145094. BIF_CFG_DEV0_EPF2_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
145095. BIF_CFG_DEV0_EPF2_2_SUB_CLASS__SUB_CLASS_MASK
145096. BIF_CFG_DEV0_EPF2_2_SUB_CLASS__SUB_CLASS__SHIFT
145097. BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__CAP_ID_MASK
145098. BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__CAP_ID__SHIFT
145099. BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__LENGTH_MASK
145100. BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__LENGTH__SHIFT
145101. BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR_MASK
145102. BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
145103. BIF_CFG_DEV0_EPF2_2_VENDOR_ID__VENDOR_ID_MASK
145104. BIF_CFG_DEV0_EPF2_2_VENDOR_ID__VENDOR_ID__SHIFT
145105. BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
145106. BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
145107. BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
145108. BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
145109. BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID_MASK
145110. BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
145111. BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
145112. BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
145113. BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR_MASK
145114. BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR__SHIFT
145115. BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR_MASK
145116. BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR__SHIFT
145117. BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR_MASK
145118. BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR__SHIFT
145119. BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR_MASK
145120. BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR__SHIFT
145121. BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR_MASK
145122. BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR__SHIFT
145123. BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR_MASK
145124. BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR__SHIFT
145125. BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS_MASK
145126. BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS__SHIFT
145127. BIF_CFG_DEV0_EPF2_BIST__BIST_CAP_MASK
145128. BIF_CFG_DEV0_EPF2_BIST__BIST_CAP__SHIFT
145129. BIF_CFG_DEV0_EPF2_BIST__BIST_COMP_MASK
145130. BIF_CFG_DEV0_EPF2_BIST__BIST_COMP__SHIFT
145131. BIF_CFG_DEV0_EPF2_BIST__BIST_STRT_MASK
145132. BIF_CFG_DEV0_EPF2_BIST__BIST_STRT__SHIFT
145133. BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE_MASK
145134. BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
145135. BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR_MASK
145136. BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR__SHIFT
145137. BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
145138. BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
145139. BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING_MASK
145140. BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING__SHIFT
145141. BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN_MASK
145142. BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN__SHIFT
145143. BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN_MASK
145144. BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN__SHIFT
145145. BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS_MASK
145146. BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS__SHIFT
145147. BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN_MASK
145148. BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN__SHIFT
145149. BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN_MASK
145150. BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN__SHIFT
145151. BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
145152. BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
145153. BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN_MASK
145154. BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN__SHIFT
145155. BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE_MASK
145156. BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
145157. BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN_MASK
145158. BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN__SHIFT
145159. BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN_MASK
145160. BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
145161. BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD_MASK
145162. BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD__SHIFT
145163. BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL_MASK
145164. BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL__SHIFT
145165. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
145166. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
145167. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
145168. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
145169. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
145170. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
145171. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
145172. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
145173. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
145174. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
145175. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
145176. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
145177. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
145178. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
145179. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
145180. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
145181. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
145182. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
145183. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
145184. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
145185. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
145186. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
145187. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED_MASK
145188. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
145189. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
145190. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
145191. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED_MASK
145192. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
145193. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
145194. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
145195. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
145196. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
145197. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
145198. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
145199. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
145200. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
145201. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
145202. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
145203. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
145204. BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
145205. BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
145206. BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
145207. BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
145208. BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
145209. BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG_MASK
145210. BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG__SHIFT
145211. BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE_MASK
145212. BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE__SHIFT
145213. BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
145214. BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
145215. BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
145216. BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
145217. BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
145218. BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
145219. BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC_MASK
145220. BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
145221. BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
145222. BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
145223. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
145224. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
145225. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
145226. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
145227. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
145228. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
145229. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
145230. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
145231. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
145232. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
145233. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
145234. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
145235. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
145236. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
145237. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
145238. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
145239. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
145240. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
145241. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN_MASK
145242. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN__SHIFT
145243. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN_MASK
145244. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN__SHIFT
145245. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
145246. BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
145247. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
145248. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
145249. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN_MASK
145250. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
145251. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
145252. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
145253. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN_MASK
145254. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
145255. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR_MASK
145256. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR__SHIFT
145257. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
145258. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
145259. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
145260. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
145261. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
145262. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
145263. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN_MASK
145264. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
145265. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
145266. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
145267. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
145268. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
145269. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN_MASK
145270. BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
145271. BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID_MASK
145272. BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID__SHIFT
145273. BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED_MASK
145274. BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED__SHIFT
145275. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR_MASK
145276. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR__SHIFT
145277. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR_MASK
145278. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR__SHIFT
145279. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
145280. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
145281. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR_MASK
145282. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR__SHIFT
145283. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR_MASK
145284. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
145285. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
145286. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
145287. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED_MASK
145288. BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED__SHIFT
145289. BIF_CFG_DEV0_EPF2_FLADJ__FLADJ_MASK
145290. BIF_CFG_DEV0_EPF2_FLADJ__FLADJ__SHIFT
145291. BIF_CFG_DEV0_EPF2_FLADJ__NFC_MASK
145292. BIF_CFG_DEV0_EPF2_FLADJ__NFC__SHIFT
145293. BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE_MASK
145294. BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE__SHIFT
145295. BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE_MASK
145296. BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE__SHIFT
145297. BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
145298. BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
145299. BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
145300. BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
145301. BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER_MASK
145302. BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER__SHIFT
145303. BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
145304. BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
145305. BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
145306. BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
145307. BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
145308. BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
145309. BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
145310. BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
145311. BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
145312. BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
145313. BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
145314. BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
145315. BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
145316. BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
145317. BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
145318. BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
145319. BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
145320. BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
145321. BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
145322. BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
145323. BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY_MASK
145324. BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
145325. BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY_MASK
145326. BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
145327. BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
145328. BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
145329. BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED_MASK
145330. BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED__SHIFT
145331. BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH_MASK
145332. BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH__SHIFT
145333. BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT_MASK
145334. BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT__SHIFT
145335. BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER_MASK
145336. BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER__SHIFT
145337. BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
145338. BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
145339. BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
145340. BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
145341. BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS_MASK
145342. BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
145343. BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
145344. BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
145345. BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
145346. BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
145347. BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
145348. BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
145349. BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
145350. BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
145351. BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
145352. BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
145353. BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN_MASK
145354. BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN__SHIFT
145355. BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
145356. BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
145357. BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
145358. BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
145359. BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
145360. BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
145361. BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC_MASK
145362. BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC__SHIFT
145363. BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
145364. BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
145365. BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
145366. BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
145367. BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
145368. BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
145369. BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS_MASK
145370. BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS__SHIFT
145371. BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL_MASK
145372. BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL__SHIFT
145373. BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
145374. BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
145375. BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK_MASK
145376. BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK__SHIFT
145377. BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
145378. BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
145379. BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
145380. BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
145381. BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
145382. BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
145383. BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
145384. BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
145385. BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
145386. BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
145387. BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
145388. BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
145389. BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
145390. BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
145391. BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
145392. BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
145393. BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
145394. BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
145395. BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
145396. BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
145397. BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
145398. BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
145399. BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
145400. BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
145401. BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE_MASK
145402. BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE__SHIFT
145403. BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
145404. BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
145405. BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
145406. BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
145407. BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING_MASK
145408. BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING__SHIFT
145409. BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
145410. BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
145411. BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
145412. BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
145413. BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT_MASK
145414. BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT__SHIFT
145415. BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT_MASK
145416. BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT__SHIFT
145417. BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID_MASK
145418. BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID__SHIFT
145419. BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR_MASK
145420. BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT
145421. BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN_MASK
145422. BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT
145423. BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
145424. BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
145425. BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
145426. BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
145427. BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR_MASK
145428. BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT
145429. BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK
145430. BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
145431. BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK
145432. BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
145433. BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
145434. BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
145435. BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID_MASK
145436. BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID__SHIFT
145437. BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR_MASK
145438. BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR__SHIFT
145439. BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64_MASK
145440. BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64__SHIFT
145441. BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK_MASK
145442. BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK__SHIFT
145443. BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
145444. BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
145445. BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
145446. BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
145447. BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT_MASK
145448. BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
145449. BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN_MASK
145450. BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN__SHIFT
145451. BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
145452. BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
145453. BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
145454. BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
145455. BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
145456. BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
145457. BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
145458. BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
145459. BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA_MASK
145460. BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA__SHIFT
145461. BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64_MASK
145462. BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT
145463. BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING_MASK
145464. BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING__SHIFT
145465. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
145466. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
145467. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
145468. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
145469. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
145470. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
145471. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
145472. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
145473. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
145474. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
145475. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
145476. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
145477. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
145478. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
145479. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
145480. BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
145481. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
145482. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
145483. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
145484. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
145485. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
145486. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
145487. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
145488. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
145489. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
145490. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
145491. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
145492. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
145493. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
145494. BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
145495. BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
145496. BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
145497. BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
145498. BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
145499. BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
145500. BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
145501. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
145502. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
145503. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
145504. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
145505. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
145506. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
145507. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
145508. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
145509. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
145510. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
145511. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
145512. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
145513. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
145514. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
145515. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
145516. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
145517. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
145518. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
145519. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
145520. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
145521. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
145522. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
145523. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
145524. BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
145525. BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
145526. BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
145527. BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
145528. BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
145529. BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
145530. BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
145531. BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
145532. BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
145533. BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
145534. BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
145535. BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
145536. BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
145537. BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
145538. BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
145539. BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
145540. BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
145541. BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
145542. BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
145543. BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
145544. BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
145545. BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX_MASK
145546. BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
145547. BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_MASK
145548. BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
145549. BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
145550. BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
145551. BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
145552. BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
145553. BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX_MASK
145554. BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
145555. BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_MASK
145556. BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
145557. BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
145558. BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
145559. BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
145560. BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
145561. BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX_MASK
145562. BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
145563. BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_MASK
145564. BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
145565. BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
145566. BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
145567. BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
145568. BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
145569. BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX_MASK
145570. BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
145571. BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_MASK
145572. BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
145573. BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
145574. BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
145575. BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
145576. BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
145577. BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX_MASK
145578. BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
145579. BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_MASK
145580. BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
145581. BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
145582. BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
145583. BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
145584. BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
145585. BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX_MASK
145586. BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
145587. BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_MASK
145588. BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
145589. BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
145590. BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
145591. BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
145592. BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
145593. BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
145594. BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
145595. BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
145596. BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
145597. BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID_MASK
145598. BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID__SHIFT
145599. BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR_MASK
145600. BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
145601. BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE_MASK
145602. BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE__SHIFT
145603. BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM_MASK
145604. BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
145605. BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
145606. BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
145607. BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION_MASK
145608. BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION__SHIFT
145609. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
145610. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
145611. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
145612. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
145613. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
145614. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
145615. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
145616. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
145617. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
145618. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
145619. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
145620. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
145621. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
145622. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
145623. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
145624. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
145625. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
145626. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
145627. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
145628. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
145629. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
145630. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
145631. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
145632. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
145633. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
145634. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
145635. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
145636. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
145637. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
145638. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
145639. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
145640. BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
145641. BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
145642. BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
145643. BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
145644. BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
145645. BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
145646. BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
145647. BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
145648. BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
145649. BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
145650. BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
145651. BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
145652. BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
145653. BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
145654. BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
145655. BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
145656. BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
145657. BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
145658. BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
145659. BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
145660. BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
145661. BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
145662. BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
145663. BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
145664. BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
145665. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
145666. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
145667. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
145668. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
145669. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
145670. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
145671. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
145672. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
145673. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
145674. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
145675. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
145676. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
145677. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
145678. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
145679. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
145680. BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
145681. BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR_MASK
145682. BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
145683. BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR_MASK
145684. BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
145685. BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR_MASK
145686. BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
145687. BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR_MASK
145688. BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
145689. BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
145690. BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
145691. BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
145692. BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
145693. BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
145694. BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
145695. BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE_MASK
145696. BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
145697. BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
145698. BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
145699. BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
145700. BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
145701. BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
145702. BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
145703. BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
145704. BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
145705. BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
145706. BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
145707. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
145708. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
145709. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
145710. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
145711. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
145712. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
145713. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
145714. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
145715. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
145716. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
145717. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
145718. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
145719. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
145720. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
145721. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE_MASK
145722. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
145723. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
145724. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
145725. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
145726. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
145727. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
145728. BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
145729. BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
145730. BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
145731. BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
145732. BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
145733. BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
145734. BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
145735. BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
145736. BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
145737. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
145738. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
145739. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
145740. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
145741. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
145742. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
145743. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
145744. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
145745. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
145746. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
145747. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
145748. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
145749. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
145750. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
145751. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
145752. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
145753. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
145754. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
145755. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
145756. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
145757. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
145758. BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
145759. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK
145760. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT
145761. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK
145762. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT
145763. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK
145764. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT
145765. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK
145766. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT
145767. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK
145768. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT
145769. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK
145770. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT
145771. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK
145772. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT
145773. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK
145774. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT
145775. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK
145776. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT
145777. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK
145778. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT
145779. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK
145780. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT
145781. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK
145782. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT
145783. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK
145784. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT
145785. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK
145786. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT
145787. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK
145788. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT
145789. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK
145790. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT
145791. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK
145792. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT
145793. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK
145794. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT
145795. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK
145796. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT
145797. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK
145798. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT
145799. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK
145800. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT
145801. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK
145802. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT
145803. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK
145804. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT
145805. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK
145806. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT
145807. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK
145808. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT
145809. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK
145810. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT
145811. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK
145812. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT
145813. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK
145814. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT
145815. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK
145816. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT
145817. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK
145818. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT
145819. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK
145820. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT
145821. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK
145822. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT
145823. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK
145824. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT
145825. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK
145826. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT
145827. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK
145828. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT
145829. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK
145830. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT
145831. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK
145832. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT
145833. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK
145834. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT
145835. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK
145836. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT
145837. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK
145838. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT
145839. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK
145840. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT
145841. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK
145842. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT
145843. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK
145844. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT
145845. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK
145846. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT
145847. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK
145848. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT
145849. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK
145850. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT
145851. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK
145852. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT
145853. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK
145854. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT
145855. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK
145856. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT
145857. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK
145858. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT
145859. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK
145860. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT
145861. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK
145862. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT
145863. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK
145864. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT
145865. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK
145866. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT
145867. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK
145868. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT
145869. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK
145870. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT
145871. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK
145872. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT
145873. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK
145874. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT
145875. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK
145876. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT
145877. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK
145878. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT
145879. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK
145880. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT
145881. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK
145882. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT
145883. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK
145884. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT
145885. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK
145886. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT
145887. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK
145888. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT
145889. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK
145890. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT
145891. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK
145892. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT
145893. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK
145894. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT
145895. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK
145896. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT
145897. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK
145898. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT
145899. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK
145900. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT
145901. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK
145902. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT
145903. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK
145904. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT
145905. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK
145906. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT
145907. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK
145908. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT
145909. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK
145910. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT
145911. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK
145912. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT
145913. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK
145914. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT
145915. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK
145916. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT
145917. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK
145918. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT
145919. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK
145920. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT
145921. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK
145922. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT
145923. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK
145924. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT
145925. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK
145926. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT
145927. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK
145928. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT
145929. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK
145930. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT
145931. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK
145932. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT
145933. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK
145934. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT
145935. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK
145936. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT
145937. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK
145938. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT
145939. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK
145940. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT
145941. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK
145942. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT
145943. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK
145944. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT
145945. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK
145946. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT
145947. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK
145948. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT
145949. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK
145950. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT
145951. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK
145952. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT
145953. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK
145954. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT
145955. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK
145956. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT
145957. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK
145958. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT
145959. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK
145960. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT
145961. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK
145962. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT
145963. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK
145964. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT
145965. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK
145966. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT
145967. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK
145968. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT
145969. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK
145970. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT
145971. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK
145972. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT
145973. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK
145974. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT
145975. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK
145976. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT
145977. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK
145978. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT
145979. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK
145980. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT
145981. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK
145982. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT
145983. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK
145984. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT
145985. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK
145986. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT
145987. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK
145988. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT
145989. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK
145990. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT
145991. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK
145992. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT
145993. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK
145994. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT
145995. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK
145996. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT
145997. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK
145998. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT
145999. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK
146000. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT
146001. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK
146002. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT
146003. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK
146004. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT
146005. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK
146006. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT
146007. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK
146008. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT
146009. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK
146010. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT
146011. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK
146012. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT
146013. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK
146014. BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT
146015. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
146016. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
146017. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
146018. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
146019. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
146020. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
146021. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
146022. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
146023. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
146024. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
146025. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
146026. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
146027. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
146028. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
146029. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
146030. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
146031. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
146032. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
146033. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
146034. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
146035. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
146036. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
146037. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
146038. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
146039. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
146040. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
146041. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
146042. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
146043. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
146044. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
146045. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
146046. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
146047. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
146048. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
146049. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
146050. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
146051. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
146052. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
146053. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
146054. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
146055. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
146056. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
146057. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
146058. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
146059. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
146060. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
146061. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
146062. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
146063. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
146064. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
146065. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
146066. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
146067. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
146068. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
146069. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
146070. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
146071. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
146072. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
146073. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
146074. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
146075. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
146076. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
146077. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
146078. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
146079. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
146080. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
146081. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
146082. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
146083. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
146084. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
146085. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
146086. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
146087. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
146088. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
146089. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
146090. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
146091. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
146092. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
146093. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
146094. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
146095. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
146096. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
146097. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
146098. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
146099. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
146100. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
146101. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
146102. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
146103. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
146104. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
146105. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
146106. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
146107. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
146108. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
146109. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
146110. BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
146111. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
146112. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
146113. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
146114. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
146115. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
146116. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
146117. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
146118. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
146119. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
146120. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
146121. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
146122. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
146123. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
146124. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
146125. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
146126. BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
146127. BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID_MASK
146128. BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID__SHIFT
146129. BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR_MASK
146130. BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR__SHIFT
146131. BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT_MASK
146132. BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT__SHIFT
146133. BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT_MASK
146134. BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT__SHIFT
146135. BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT_MASK
146136. BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT__SHIFT
146137. BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
146138. BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
146139. BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
146140. BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
146141. BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK_MASK
146142. BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK__SHIFT
146143. BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT_MASK
146144. BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT__SHIFT
146145. BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION_MASK
146146. BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION__SHIFT
146147. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
146148. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
146149. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
146150. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
146151. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE_MASK
146152. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
146153. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT_MASK
146154. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
146155. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
146156. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
146157. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN_MASK
146158. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN__SHIFT
146159. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS_MASK
146160. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
146161. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA_MASK
146162. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
146163. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE_MASK
146164. BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
146165. BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE_MASK
146166. BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
146167. BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID_MASK
146168. BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID__SHIFT
146169. BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID_MASK
146170. BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID__SHIFT
146171. BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR_MASK
146172. BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT
146173. BIF_CFG_DEV0_EPF2_SATA_CAP_0__CAP_ID_MASK
146174. BIF_CFG_DEV0_EPF2_SATA_CAP_0__CAP_ID__SHIFT
146175. BIF_CFG_DEV0_EPF2_SATA_CAP_0__NEXT_PTR_MASK
146176. BIF_CFG_DEV0_EPF2_SATA_CAP_0__NEXT_PTR__SHIFT
146177. BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
146178. BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
146179. BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
146180. BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
146181. BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
146182. BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
146183. BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
146184. BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
146185. BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
146186. BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
146187. BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
146188. BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
146189. BIF_CFG_DEV0_EPF2_SATA_IDP_DATA__IDP_DATA_MASK
146190. BIF_CFG_DEV0_EPF2_SATA_IDP_DATA__IDP_DATA__SHIFT
146191. BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_INDEX_MASK
146192. BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_INDEX__SHIFT
146193. BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED1_MASK
146194. BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
146195. BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED2_MASK
146196. BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
146197. BIF_CFG_DEV0_EPF2_SBRN__SBRN_MASK
146198. BIF_CFG_DEV0_EPF2_SBRN__SBRN__SHIFT
146199. BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST_MASK
146200. BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST__SHIFT
146201. BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING_MASK
146202. BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING__SHIFT
146203. BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE_MASK
146204. BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE__SHIFT
146205. BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS_MASK
146206. BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS__SHIFT
146207. BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS_MASK
146208. BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS__SHIFT
146209. BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
146210. BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
146211. BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED_MASK
146212. BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED__SHIFT
146213. BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP_MASK
146214. BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP__SHIFT
146215. BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT_MASK
146216. BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
146217. BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT_MASK
146218. BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
146219. BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
146220. BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
146221. BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT_MASK
146222. BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
146223. BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS_MASK
146224. BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS__SHIFT
146225. BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID_MASK
146226. BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID__SHIFT
146227. BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH_MASK
146228. BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH__SHIFT
146229. BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR_MASK
146230. BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
146231. BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID_MASK
146232. BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID__SHIFT
146233. BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
146234. BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
146235. BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
146236. BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
146237. BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
146238. BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
146239. BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
146240. BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
146241. BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK
146242. BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT
146243. BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK
146244. BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT
146245. BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK
146246. BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT
146247. BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK
146248. BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT
146249. BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK
146250. BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT
146251. BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK
146252. BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT
146253. BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS_MASK
146254. BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT
146255. BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP_MASK
146256. BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP__SHIFT
146257. BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP_MASK
146258. BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP__SHIFT
146259. BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT_MASK
146260. BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT__SHIFT
146261. BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
146262. BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
146263. BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR_MASK
146264. BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR__SHIFT
146265. BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
146266. BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
146267. BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING_MASK
146268. BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING__SHIFT
146269. BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN_MASK
146270. BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT
146271. BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN_MASK
146272. BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT
146273. BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS_MASK
146274. BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS__SHIFT
146275. BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN_MASK
146276. BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT
146277. BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK
146278. BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT
146279. BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
146280. BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
146281. BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK
146282. BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT
146283. BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
146284. BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
146285. BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN_MASK
146286. BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN__SHIFT
146287. BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK
146288. BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
146289. BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD_MASK
146290. BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT
146291. BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL_MASK
146292. BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL__SHIFT
146293. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
146294. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
146295. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
146296. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
146297. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
146298. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
146299. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
146300. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
146301. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
146302. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
146303. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
146304. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
146305. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
146306. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
146307. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
146308. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
146309. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
146310. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
146311. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
146312. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
146313. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
146314. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
146315. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
146316. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
146317. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
146318. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
146319. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
146320. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
146321. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
146322. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
146323. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
146324. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
146325. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
146326. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
146327. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
146328. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
146329. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
146330. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
146331. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
146332. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
146333. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
146334. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
146335. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
146336. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
146337. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK
146338. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
146339. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK
146340. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
146341. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
146342. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
146343. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
146344. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
146345. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
146346. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
146347. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK
146348. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
146349. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
146350. BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
146351. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
146352. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
146353. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
146354. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
146355. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
146356. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
146357. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
146358. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
146359. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
146360. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
146361. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
146362. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
146363. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
146364. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
146365. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
146366. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
146367. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
146368. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
146369. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK
146370. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT
146371. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK
146372. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT
146373. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
146374. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
146375. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
146376. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
146377. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK
146378. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
146379. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
146380. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
146381. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
146382. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
146383. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK
146384. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
146385. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
146386. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
146387. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
146388. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
146389. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
146390. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
146391. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
146392. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
146393. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
146394. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
146395. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
146396. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
146397. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK
146398. BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
146399. BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID_MASK
146400. BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT
146401. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED_MASK
146402. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT
146403. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK
146404. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT
146405. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK
146406. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT
146407. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
146408. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
146409. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK
146410. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT
146411. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
146412. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
146413. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
146414. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
146415. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK
146416. BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT
146417. BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ_MASK
146418. BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ__SHIFT
146419. BIF_CFG_DEV0_EPF3_0_FLADJ__NFC_MASK
146420. BIF_CFG_DEV0_EPF3_0_FLADJ__NFC__SHIFT
146421. BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE_MASK
146422. BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE__SHIFT
146423. BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE_MASK
146424. BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE__SHIFT
146425. BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
146426. BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
146427. BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
146428. BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
146429. BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER_MASK
146430. BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT
146431. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
146432. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
146433. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
146434. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
146435. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
146436. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
146437. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
146438. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
146439. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RESERVED_MASK
146440. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RESERVED__SHIFT
146441. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
146442. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
146443. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
146444. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
146445. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
146446. BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
146447. BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
146448. BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
146449. BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
146450. BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
146451. BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
146452. BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
146453. BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
146454. BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
146455. BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK
146456. BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
146457. BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
146458. BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
146459. BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED_MASK
146460. BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT
146461. BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH_MASK
146462. BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT
146463. BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT_MASK
146464. BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT
146465. BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER_MASK
146466. BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT
146467. BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
146468. BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
146469. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
146470. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
146471. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
146472. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
146473. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
146474. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
146475. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
146476. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
146477. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
146478. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
146479. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
146480. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
146481. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
146482. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
146483. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK
146484. BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
146485. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
146486. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
146487. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
146488. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
146489. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
146490. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
146491. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK
146492. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
146493. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
146494. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
146495. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
146496. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
146497. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
146498. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
146499. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS_MASK
146500. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT
146501. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL_MASK
146502. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT
146503. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
146504. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
146505. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK
146506. BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT
146507. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
146508. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
146509. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
146510. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
146511. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
146512. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
146513. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
146514. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
146515. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
146516. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
146517. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
146518. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
146519. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
146520. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
146521. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
146522. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
146523. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
146524. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
146525. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
146526. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
146527. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
146528. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
146529. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
146530. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
146531. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
146532. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
146533. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
146534. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
146535. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
146536. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
146537. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
146538. BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
146539. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
146540. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
146541. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK
146542. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT
146543. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
146544. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
146545. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
146546. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
146547. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK
146548. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT
146549. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
146550. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
146551. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
146552. BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
146553. BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT_MASK
146554. BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT
146555. BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT_MASK
146556. BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT
146557. BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK
146558. BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT
146559. BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK
146560. BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
146561. BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK
146562. BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
146563. BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
146564. BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
146565. BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
146566. BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
146567. BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK
146568. BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
146569. BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
146570. BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
146571. BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
146572. BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
146573. BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
146574. BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
146575. BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK
146576. BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT
146577. BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK
146578. BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
146579. BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK
146580. BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT
146581. BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK_MASK
146582. BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK__SHIFT
146583. BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
146584. BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
146585. BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
146586. BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
146587. BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK
146588. BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
146589. BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK
146590. BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT
146591. BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
146592. BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
146593. BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
146594. BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
146595. BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
146596. BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
146597. BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
146598. BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
146599. BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK
146600. BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT
146601. BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK
146602. BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
146603. BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING_MASK
146604. BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT
146605. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
146606. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
146607. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
146608. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
146609. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
146610. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
146611. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
146612. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
146613. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
146614. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
146615. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
146616. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
146617. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
146618. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
146619. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
146620. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
146621. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
146622. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
146623. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
146624. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
146625. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
146626. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
146627. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
146628. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
146629. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
146630. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
146631. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
146632. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
146633. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
146634. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
146635. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
146636. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
146637. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
146638. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
146639. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
146640. BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
146641. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
146642. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
146643. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
146644. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
146645. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
146646. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
146647. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
146648. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
146649. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
146650. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
146651. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
146652. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
146653. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
146654. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
146655. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
146656. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
146657. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
146658. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
146659. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
146660. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
146661. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
146662. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
146663. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
146664. BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
146665. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
146666. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
146667. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
146668. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
146669. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
146670. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
146671. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
146672. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
146673. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
146674. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
146675. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
146676. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
146677. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
146678. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
146679. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
146680. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
146681. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
146682. BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
146683. BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
146684. BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
146685. BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK
146686. BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
146687. BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK
146688. BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
146689. BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
146690. BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
146691. BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
146692. BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
146693. BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK
146694. BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
146695. BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK
146696. BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
146697. BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
146698. BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
146699. BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
146700. BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
146701. BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK
146702. BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
146703. BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK
146704. BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
146705. BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
146706. BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
146707. BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
146708. BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
146709. BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK
146710. BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
146711. BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK
146712. BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
146713. BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
146714. BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
146715. BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
146716. BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
146717. BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK
146718. BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
146719. BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK
146720. BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
146721. BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
146722. BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
146723. BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
146724. BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
146725. BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK
146726. BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
146727. BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK
146728. BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
146729. BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
146730. BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
146731. BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
146732. BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
146733. BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
146734. BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
146735. BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
146736. BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
146737. BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK
146738. BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT
146739. BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK
146740. BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
146741. BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK
146742. BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT
146743. BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
146744. BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
146745. BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
146746. BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
146747. BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION_MASK
146748. BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION__SHIFT
146749. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
146750. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
146751. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
146752. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
146753. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
146754. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
146755. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
146756. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
146757. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
146758. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
146759. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
146760. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
146761. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
146762. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
146763. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
146764. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
146765. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
146766. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
146767. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
146768. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
146769. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
146770. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
146771. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
146772. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
146773. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
146774. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
146775. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
146776. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
146777. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
146778. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
146779. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
146780. BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
146781. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
146782. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
146783. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
146784. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
146785. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
146786. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
146787. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
146788. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
146789. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
146790. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
146791. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
146792. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
146793. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
146794. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
146795. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
146796. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
146797. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
146798. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
146799. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
146800. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
146801. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
146802. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
146803. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
146804. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
146805. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
146806. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
146807. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
146808. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
146809. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
146810. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
146811. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
146812. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
146813. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
146814. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
146815. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
146816. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
146817. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
146818. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
146819. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
146820. BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
146821. BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK
146822. BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
146823. BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK
146824. BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
146825. BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK
146826. BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
146827. BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK
146828. BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
146829. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
146830. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
146831. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
146832. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
146833. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
146834. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
146835. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK
146836. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
146837. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
146838. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
146839. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
146840. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
146841. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
146842. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
146843. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
146844. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
146845. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
146846. BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
146847. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
146848. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
146849. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
146850. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
146851. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
146852. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
146853. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
146854. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
146855. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
146856. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
146857. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
146858. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
146859. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
146860. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
146861. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK
146862. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
146863. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
146864. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
146865. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
146866. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
146867. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
146868. BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
146869. BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
146870. BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
146871. BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
146872. BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
146873. BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
146874. BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
146875. BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
146876. BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
146877. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
146878. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
146879. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
146880. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
146881. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
146882. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
146883. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
146884. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
146885. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
146886. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
146887. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
146888. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
146889. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
146890. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
146891. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
146892. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
146893. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
146894. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
146895. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
146896. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
146897. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
146898. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
146899. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK
146900. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT
146901. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK
146902. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT
146903. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK
146904. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT
146905. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK
146906. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT
146907. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK
146908. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT
146909. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK
146910. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT
146911. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK
146912. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT
146913. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK
146914. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT
146915. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK
146916. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT
146917. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK
146918. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT
146919. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK
146920. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT
146921. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK
146922. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT
146923. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK
146924. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT
146925. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK
146926. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT
146927. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK
146928. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT
146929. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK
146930. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT
146931. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK
146932. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT
146933. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK
146934. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT
146935. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK
146936. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT
146937. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK
146938. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT
146939. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK
146940. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT
146941. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK
146942. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT
146943. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK
146944. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT
146945. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK
146946. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT
146947. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK
146948. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT
146949. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK
146950. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT
146951. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK
146952. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT
146953. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK
146954. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT
146955. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK
146956. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT
146957. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK
146958. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT
146959. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK
146960. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT
146961. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK
146962. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT
146963. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK
146964. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT
146965. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK
146966. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT
146967. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK
146968. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT
146969. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK
146970. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT
146971. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK
146972. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT
146973. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK
146974. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT
146975. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK
146976. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT
146977. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK
146978. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT
146979. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK
146980. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT
146981. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK
146982. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT
146983. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK
146984. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT
146985. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK
146986. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT
146987. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK
146988. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT
146989. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK
146990. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT
146991. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK
146992. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT
146993. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK
146994. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT
146995. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK
146996. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT
146997. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK
146998. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT
146999. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK
147000. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT
147001. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK
147002. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT
147003. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK
147004. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT
147005. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK
147006. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT
147007. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK
147008. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT
147009. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK
147010. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT
147011. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK
147012. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT
147013. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK
147014. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT
147015. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK
147016. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT
147017. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK
147018. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT
147019. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK
147020. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT
147021. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK
147022. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT
147023. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK
147024. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT
147025. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK
147026. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT
147027. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK
147028. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT
147029. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK
147030. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT
147031. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK
147032. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT
147033. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK
147034. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT
147035. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK
147036. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT
147037. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK
147038. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT
147039. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK
147040. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT
147041. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK
147042. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT
147043. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK
147044. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT
147045. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK
147046. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT
147047. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK
147048. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT
147049. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK
147050. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT
147051. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK
147052. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT
147053. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK
147054. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT
147055. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK
147056. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT
147057. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK
147058. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT
147059. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK
147060. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT
147061. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK
147062. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT
147063. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK
147064. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT
147065. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK
147066. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT
147067. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK
147068. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT
147069. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK
147070. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT
147071. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK
147072. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT
147073. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK
147074. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT
147075. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK
147076. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT
147077. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK
147078. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT
147079. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK
147080. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT
147081. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK
147082. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT
147083. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK
147084. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT
147085. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK
147086. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT
147087. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK
147088. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT
147089. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK
147090. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT
147091. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK
147092. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT
147093. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK
147094. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT
147095. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK
147096. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT
147097. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK
147098. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT
147099. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK
147100. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT
147101. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK
147102. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT
147103. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK
147104. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT
147105. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK
147106. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT
147107. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK
147108. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT
147109. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK
147110. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT
147111. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK
147112. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT
147113. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK
147114. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT
147115. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK
147116. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT
147117. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK
147118. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT
147119. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK
147120. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT
147121. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK
147122. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT
147123. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK
147124. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT
147125. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK
147126. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT
147127. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK
147128. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT
147129. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK
147130. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT
147131. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK
147132. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT
147133. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK
147134. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT
147135. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK
147136. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT
147137. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK
147138. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT
147139. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK
147140. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT
147141. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK
147142. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT
147143. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK
147144. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT
147145. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK
147146. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT
147147. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK
147148. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT
147149. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK
147150. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT
147151. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK
147152. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT
147153. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK
147154. BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT
147155. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
147156. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
147157. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
147158. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
147159. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
147160. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
147161. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
147162. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
147163. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
147164. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
147165. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
147166. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
147167. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
147168. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
147169. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
147170. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
147171. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
147172. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
147173. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
147174. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
147175. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
147176. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
147177. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
147178. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
147179. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
147180. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
147181. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
147182. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
147183. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
147184. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
147185. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
147186. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
147187. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
147188. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
147189. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
147190. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
147191. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
147192. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
147193. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
147194. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
147195. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
147196. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
147197. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
147198. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
147199. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
147200. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
147201. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
147202. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
147203. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
147204. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
147205. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
147206. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
147207. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
147208. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
147209. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
147210. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
147211. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
147212. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
147213. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
147214. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
147215. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
147216. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
147217. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
147218. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
147219. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
147220. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
147221. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
147222. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
147223. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
147224. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
147225. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
147226. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
147227. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
147228. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
147229. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
147230. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
147231. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
147232. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
147233. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
147234. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
147235. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
147236. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
147237. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
147238. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
147239. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
147240. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
147241. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
147242. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
147243. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
147244. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
147245. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
147246. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
147247. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
147248. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
147249. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
147250. BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
147251. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
147252. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
147253. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
147254. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
147255. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
147256. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
147257. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
147258. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
147259. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
147260. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
147261. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
147262. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
147263. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
147264. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
147265. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
147266. BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
147267. BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK
147268. BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT
147269. BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK
147270. BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
147271. BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT_MASK
147272. BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT
147273. BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT_MASK
147274. BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT
147275. BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT_MASK
147276. BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT
147277. BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
147278. BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
147279. BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
147280. BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
147281. BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK_MASK
147282. BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT
147283. BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT_MASK
147284. BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT
147285. BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION_MASK
147286. BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION__SHIFT
147287. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
147288. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
147289. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
147290. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
147291. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
147292. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
147293. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
147294. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
147295. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
147296. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
147297. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK
147298. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT
147299. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK
147300. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
147301. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK
147302. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
147303. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK
147304. BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
147305. BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK
147306. BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
147307. BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK
147308. BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT
147309. BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK
147310. BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT
147311. BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK
147312. BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
147313. BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID_MASK
147314. BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID__SHIFT
147315. BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR_MASK
147316. BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR__SHIFT
147317. BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
147318. BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
147319. BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
147320. BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
147321. BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
147322. BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
147323. BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
147324. BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
147325. BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
147326. BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
147327. BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
147328. BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
147329. BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA_MASK
147330. BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA__SHIFT
147331. BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX_MASK
147332. BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT
147333. BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK
147334. BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
147335. BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK
147336. BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
147337. BIF_CFG_DEV0_EPF3_0_SBRN__SBRN_MASK
147338. BIF_CFG_DEV0_EPF3_0_SBRN__SBRN__SHIFT
147339. BIF_CFG_DEV0_EPF3_0_SLOT_CAP2__RESERVED_MASK
147340. BIF_CFG_DEV0_EPF3_0_SLOT_CAP2__RESERVED__SHIFT
147341. BIF_CFG_DEV0_EPF3_0_SLOT_CNTL2__RESERVED_MASK
147342. BIF_CFG_DEV0_EPF3_0_SLOT_CNTL2__RESERVED__SHIFT
147343. BIF_CFG_DEV0_EPF3_0_SLOT_STATUS2__RESERVED_MASK
147344. BIF_CFG_DEV0_EPF3_0_SLOT_STATUS2__RESERVED__SHIFT
147345. BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST_MASK
147346. BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST__SHIFT
147347. BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING_MASK
147348. BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT
147349. BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK
147350. BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT
147351. BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS_MASK
147352. BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS__SHIFT
147353. BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS_MASK
147354. BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS__SHIFT
147355. BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
147356. BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
147357. BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED_MASK
147358. BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
147359. BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP_MASK
147360. BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP__SHIFT
147361. BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_EN_MASK
147362. BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_EN__SHIFT
147363. BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK
147364. BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
147365. BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK
147366. BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
147367. BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
147368. BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
147369. BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK
147370. BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
147371. BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS_MASK
147372. BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT
147373. BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK
147374. BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT
147375. BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK
147376. BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT
147377. BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK
147378. BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
147379. BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID_MASK
147380. BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT
147381. BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
147382. BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
147383. BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
147384. BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
147385. BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
147386. BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
147387. BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
147388. BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
147389. BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR_MASK
147390. BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT
147391. BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR_MASK
147392. BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT
147393. BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR_MASK
147394. BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT
147395. BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR_MASK
147396. BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT
147397. BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR_MASK
147398. BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT
147399. BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR_MASK
147400. BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT
147401. BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS_MASK
147402. BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS__SHIFT
147403. BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP_MASK
147404. BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP__SHIFT
147405. BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP_MASK
147406. BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP__SHIFT
147407. BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT_MASK
147408. BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT__SHIFT
147409. BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
147410. BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
147411. BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR_MASK
147412. BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR__SHIFT
147413. BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
147414. BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
147415. BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING_MASK
147416. BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING__SHIFT
147417. BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN_MASK
147418. BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN__SHIFT
147419. BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN_MASK
147420. BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN__SHIFT
147421. BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS_MASK
147422. BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS__SHIFT
147423. BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN_MASK
147424. BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN__SHIFT
147425. BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN_MASK
147426. BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN__SHIFT
147427. BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
147428. BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
147429. BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN_MASK
147430. BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN__SHIFT
147431. BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
147432. BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
147433. BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN_MASK
147434. BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN__SHIFT
147435. BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK
147436. BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
147437. BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD_MASK
147438. BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD__SHIFT
147439. BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL_MASK
147440. BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL__SHIFT
147441. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
147442. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
147443. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
147444. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
147445. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
147446. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
147447. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
147448. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
147449. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
147450. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
147451. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
147452. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
147453. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
147454. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
147455. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
147456. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
147457. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
147458. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
147459. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
147460. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
147461. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
147462. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
147463. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
147464. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
147465. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
147466. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
147467. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
147468. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
147469. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
147470. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
147471. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
147472. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
147473. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
147474. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
147475. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
147476. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
147477. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
147478. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
147479. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
147480. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
147481. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
147482. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
147483. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
147484. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
147485. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG_MASK
147486. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
147487. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE_MASK
147488. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
147489. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
147490. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
147491. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
147492. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
147493. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
147494. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
147495. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK
147496. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
147497. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
147498. BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
147499. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
147500. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
147501. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
147502. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
147503. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
147504. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
147505. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
147506. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
147507. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
147508. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
147509. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
147510. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
147511. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
147512. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
147513. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
147514. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
147515. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
147516. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
147517. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN_MASK
147518. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN__SHIFT
147519. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN_MASK
147520. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT
147521. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
147522. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
147523. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
147524. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
147525. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK
147526. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
147527. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
147528. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
147529. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
147530. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
147531. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR_MASK
147532. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
147533. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
147534. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
147535. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
147536. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
147537. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
147538. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
147539. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
147540. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
147541. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
147542. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
147543. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
147544. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
147545. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK
147546. BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
147547. BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID_MASK
147548. BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID__SHIFT
147549. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED_MASK
147550. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED__SHIFT
147551. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR_MASK
147552. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR__SHIFT
147553. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR_MASK
147554. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR__SHIFT
147555. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
147556. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
147557. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR_MASK
147558. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT
147559. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
147560. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
147561. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
147562. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
147563. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED_MASK
147564. BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT
147565. BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ_MASK
147566. BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ__SHIFT
147567. BIF_CFG_DEV0_EPF3_1_FLADJ__NFC_MASK
147568. BIF_CFG_DEV0_EPF3_1_FLADJ__NFC__SHIFT
147569. BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE_MASK
147570. BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE__SHIFT
147571. BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE_MASK
147572. BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE__SHIFT
147573. BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
147574. BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
147575. BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
147576. BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
147577. BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER_MASK
147578. BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER__SHIFT
147579. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
147580. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
147581. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
147582. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
147583. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
147584. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
147585. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
147586. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
147587. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RESERVED_MASK
147588. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RESERVED__SHIFT
147589. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
147590. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
147591. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
147592. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
147593. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
147594. BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
147595. BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
147596. BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
147597. BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
147598. BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
147599. BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
147600. BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
147601. BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
147602. BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
147603. BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK
147604. BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
147605. BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
147606. BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
147607. BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED_MASK
147608. BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED__SHIFT
147609. BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH_MASK
147610. BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH__SHIFT
147611. BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT_MASK
147612. BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT__SHIFT
147613. BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER_MASK
147614. BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER__SHIFT
147615. BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
147616. BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
147617. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
147618. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
147619. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
147620. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
147621. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
147622. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
147623. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
147624. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
147625. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
147626. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
147627. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
147628. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
147629. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
147630. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
147631. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN_MASK
147632. BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
147633. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
147634. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
147635. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
147636. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
147637. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
147638. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
147639. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC_MASK
147640. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
147641. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
147642. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
147643. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
147644. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
147645. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
147646. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
147647. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS_MASK
147648. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS__SHIFT
147649. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL_MASK
147650. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL__SHIFT
147651. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
147652. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
147653. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK_MASK
147654. BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT
147655. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
147656. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
147657. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
147658. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
147659. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
147660. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
147661. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
147662. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
147663. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
147664. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
147665. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
147666. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
147667. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
147668. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
147669. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
147670. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
147671. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
147672. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
147673. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
147674. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
147675. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
147676. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
147677. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
147678. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
147679. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
147680. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
147681. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
147682. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
147683. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
147684. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
147685. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
147686. BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
147687. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
147688. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
147689. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE_MASK
147690. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE__SHIFT
147691. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
147692. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
147693. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
147694. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
147695. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING_MASK
147696. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING__SHIFT
147697. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
147698. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
147699. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
147700. BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
147701. BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT_MASK
147702. BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT__SHIFT
147703. BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT_MASK
147704. BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT__SHIFT
147705. BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID_MASK
147706. BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT
147707. BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK
147708. BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
147709. BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK
147710. BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
147711. BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
147712. BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
147713. BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
147714. BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
147715. BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK
147716. BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
147717. BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
147718. BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
147719. BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
147720. BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
147721. BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
147722. BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
147723. BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID_MASK
147724. BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID__SHIFT
147725. BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR_MASK
147726. BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
147727. BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64_MASK
147728. BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT
147729. BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK_MASK
147730. BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK__SHIFT
147731. BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
147732. BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
147733. BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
147734. BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
147735. BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK
147736. BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
147737. BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN_MASK
147738. BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT
147739. BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
147740. BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
147741. BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
147742. BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
147743. BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
147744. BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
147745. BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
147746. BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
147747. BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA_MASK
147748. BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT
147749. BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK
147750. BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
147751. BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING_MASK
147752. BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING__SHIFT
147753. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
147754. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
147755. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
147756. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
147757. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
147758. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
147759. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
147760. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
147761. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
147762. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
147763. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
147764. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
147765. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
147766. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
147767. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
147768. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
147769. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
147770. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
147771. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
147772. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
147773. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
147774. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
147775. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
147776. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
147777. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
147778. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
147779. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
147780. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
147781. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
147782. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
147783. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
147784. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
147785. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
147786. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
147787. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
147788. BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
147789. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
147790. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
147791. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
147792. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
147793. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
147794. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
147795. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
147796. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
147797. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
147798. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
147799. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
147800. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
147801. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
147802. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
147803. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
147804. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
147805. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
147806. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
147807. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
147808. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
147809. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
147810. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
147811. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
147812. BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
147813. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
147814. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
147815. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
147816. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
147817. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
147818. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
147819. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
147820. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
147821. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
147822. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
147823. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
147824. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
147825. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
147826. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
147827. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
147828. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
147829. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
147830. BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
147831. BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
147832. BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
147833. BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK
147834. BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
147835. BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK
147836. BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
147837. BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
147838. BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
147839. BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
147840. BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
147841. BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK
147842. BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
147843. BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK
147844. BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
147845. BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
147846. BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
147847. BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
147848. BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
147849. BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK
147850. BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
147851. BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK
147852. BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
147853. BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
147854. BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
147855. BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
147856. BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
147857. BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK
147858. BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
147859. BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK
147860. BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
147861. BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
147862. BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
147863. BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
147864. BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
147865. BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK
147866. BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
147867. BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK
147868. BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
147869. BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
147870. BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
147871. BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
147872. BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
147873. BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK
147874. BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
147875. BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK
147876. BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
147877. BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
147878. BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
147879. BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
147880. BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
147881. BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
147882. BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
147883. BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
147884. BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
147885. BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID_MASK
147886. BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT
147887. BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK
147888. BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
147889. BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE_MASK
147890. BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT
147891. BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
147892. BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
147893. BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
147894. BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
147895. BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION_MASK
147896. BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION__SHIFT
147897. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
147898. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
147899. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
147900. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
147901. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
147902. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
147903. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
147904. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
147905. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
147906. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
147907. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
147908. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
147909. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
147910. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
147911. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
147912. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
147913. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
147914. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
147915. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
147916. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
147917. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
147918. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
147919. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
147920. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
147921. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
147922. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
147923. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
147924. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
147925. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
147926. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
147927. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
147928. BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
147929. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
147930. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
147931. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
147932. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
147933. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
147934. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
147935. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
147936. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
147937. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
147938. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
147939. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
147940. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
147941. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
147942. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
147943. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
147944. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
147945. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
147946. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
147947. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
147948. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
147949. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
147950. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
147951. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
147952. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
147953. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
147954. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
147955. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
147956. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
147957. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
147958. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
147959. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
147960. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
147961. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
147962. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
147963. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
147964. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
147965. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
147966. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
147967. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
147968. BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
147969. BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK
147970. BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
147971. BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK
147972. BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
147973. BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK
147974. BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
147975. BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK
147976. BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
147977. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
147978. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
147979. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
147980. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
147981. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
147982. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
147983. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK
147984. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
147985. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
147986. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
147987. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
147988. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
147989. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
147990. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
147991. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
147992. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
147993. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
147994. BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
147995. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
147996. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
147997. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
147998. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
147999. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
148000. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
148001. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
148002. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
148003. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
148004. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
148005. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
148006. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
148007. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
148008. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
148009. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK
148010. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
148011. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
148012. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
148013. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
148014. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
148015. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
148016. BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
148017. BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
148018. BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
148019. BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
148020. BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
148021. BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
148022. BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
148023. BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
148024. BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
148025. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
148026. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
148027. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
148028. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
148029. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
148030. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
148031. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
148032. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
148033. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
148034. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
148035. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
148036. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
148037. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
148038. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
148039. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
148040. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
148041. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
148042. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
148043. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
148044. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
148045. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
148046. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
148047. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK
148048. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT
148049. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK
148050. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT
148051. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK
148052. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT
148053. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK
148054. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT
148055. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK
148056. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT
148057. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK
148058. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT
148059. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK
148060. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT
148061. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK
148062. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT
148063. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK
148064. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT
148065. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK
148066. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT
148067. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK
148068. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT
148069. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK
148070. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT
148071. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK
148072. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT
148073. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK
148074. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT
148075. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK
148076. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT
148077. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK
148078. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT
148079. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK
148080. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT
148081. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK
148082. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT
148083. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK
148084. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT
148085. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK
148086. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT
148087. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK
148088. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT
148089. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK
148090. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT
148091. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK
148092. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT
148093. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK
148094. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT
148095. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK
148096. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT
148097. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK
148098. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT
148099. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK
148100. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT
148101. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK
148102. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT
148103. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK
148104. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT
148105. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK
148106. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT
148107. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK
148108. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT
148109. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK
148110. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT
148111. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK
148112. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT
148113. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK
148114. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT
148115. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK
148116. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT
148117. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK
148118. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT
148119. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK
148120. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT
148121. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK
148122. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT
148123. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK
148124. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT
148125. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK
148126. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT
148127. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK
148128. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT
148129. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK
148130. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT
148131. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK
148132. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT
148133. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK
148134. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT
148135. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK
148136. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT
148137. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK
148138. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT
148139. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK
148140. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT
148141. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK
148142. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT
148143. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK
148144. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT
148145. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK
148146. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT
148147. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK
148148. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT
148149. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK
148150. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT
148151. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK
148152. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT
148153. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK
148154. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT
148155. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK
148156. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT
148157. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK
148158. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT
148159. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK
148160. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT
148161. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK
148162. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT
148163. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK
148164. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT
148165. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK
148166. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT
148167. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK
148168. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT
148169. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK
148170. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT
148171. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK
148172. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT
148173. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK
148174. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT
148175. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK
148176. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT
148177. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK
148178. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT
148179. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK
148180. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT
148181. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK
148182. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT
148183. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK
148184. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT
148185. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK
148186. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT
148187. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK
148188. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT
148189. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK
148190. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT
148191. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK
148192. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT
148193. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK
148194. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT
148195. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK
148196. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT
148197. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK
148198. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT
148199. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK
148200. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT
148201. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK
148202. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT
148203. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK
148204. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT
148205. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK
148206. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT
148207. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK
148208. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT
148209. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK
148210. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT
148211. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK
148212. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT
148213. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK
148214. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT
148215. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK
148216. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT
148217. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK
148218. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT
148219. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK
148220. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT
148221. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK
148222. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT
148223. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK
148224. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT
148225. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK
148226. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT
148227. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK
148228. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT
148229. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK
148230. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT
148231. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK
148232. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT
148233. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK
148234. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT
148235. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK
148236. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT
148237. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK
148238. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT
148239. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK
148240. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT
148241. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK
148242. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT
148243. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK
148244. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT
148245. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK
148246. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT
148247. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK
148248. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT
148249. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK
148250. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT
148251. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK
148252. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT
148253. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK
148254. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT
148255. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK
148256. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT
148257. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK
148258. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT
148259. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK
148260. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT
148261. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK
148262. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT
148263. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK
148264. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT
148265. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK
148266. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT
148267. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK
148268. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT
148269. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK
148270. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT
148271. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK
148272. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT
148273. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK
148274. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT
148275. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK
148276. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT
148277. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK
148278. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT
148279. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK
148280. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT
148281. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK
148282. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT
148283. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK
148284. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT
148285. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK
148286. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT
148287. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK
148288. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT
148289. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK
148290. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT
148291. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK
148292. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT
148293. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK
148294. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT
148295. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK
148296. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT
148297. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK
148298. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT
148299. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK
148300. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT
148301. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK
148302. BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT
148303. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
148304. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
148305. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
148306. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
148307. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
148308. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
148309. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
148310. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
148311. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
148312. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
148313. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
148314. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
148315. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
148316. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
148317. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
148318. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
148319. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
148320. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
148321. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
148322. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
148323. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
148324. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
148325. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
148326. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
148327. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
148328. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
148329. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
148330. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
148331. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
148332. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
148333. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
148334. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
148335. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
148336. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
148337. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
148338. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
148339. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
148340. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
148341. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
148342. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
148343. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
148344. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
148345. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
148346. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
148347. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
148348. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
148349. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
148350. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
148351. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
148352. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
148353. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
148354. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
148355. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
148356. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
148357. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
148358. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
148359. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
148360. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
148361. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
148362. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
148363. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
148364. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
148365. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
148366. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
148367. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
148368. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
148369. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
148370. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
148371. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
148372. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
148373. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
148374. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
148375. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
148376. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
148377. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
148378. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
148379. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
148380. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
148381. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
148382. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
148383. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
148384. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
148385. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
148386. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
148387. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
148388. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
148389. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
148390. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
148391. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
148392. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
148393. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
148394. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
148395. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
148396. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
148397. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
148398. BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
148399. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
148400. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
148401. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
148402. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
148403. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
148404. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
148405. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
148406. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
148407. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
148408. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
148409. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
148410. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
148411. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
148412. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
148413. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
148414. BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
148415. BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID_MASK
148416. BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID__SHIFT
148417. BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR_MASK
148418. BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
148419. BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT_MASK
148420. BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT__SHIFT
148421. BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT_MASK
148422. BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT__SHIFT
148423. BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT_MASK
148424. BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT__SHIFT
148425. BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
148426. BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
148427. BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
148428. BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
148429. BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK_MASK
148430. BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK__SHIFT
148431. BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT_MASK
148432. BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT__SHIFT
148433. BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION_MASK
148434. BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION__SHIFT
148435. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
148436. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
148437. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
148438. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
148439. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
148440. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
148441. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
148442. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
148443. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
148444. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
148445. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN_MASK
148446. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN__SHIFT
148447. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS_MASK
148448. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
148449. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA_MASK
148450. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
148451. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE_MASK
148452. BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
148453. BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK
148454. BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
148455. BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID_MASK
148456. BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT
148457. BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID_MASK
148458. BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID__SHIFT
148459. BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK
148460. BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
148461. BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__CAP_ID_MASK
148462. BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__CAP_ID__SHIFT
148463. BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__NEXT_PTR_MASK
148464. BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__NEXT_PTR__SHIFT
148465. BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
148466. BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
148467. BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
148468. BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
148469. BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
148470. BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
148471. BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
148472. BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
148473. BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
148474. BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
148475. BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
148476. BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
148477. BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA__IDP_DATA_MASK
148478. BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA__IDP_DATA__SHIFT
148479. BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_INDEX_MASK
148480. BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT
148481. BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK
148482. BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
148483. BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK
148484. BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
148485. BIF_CFG_DEV0_EPF3_1_SBRN__SBRN_MASK
148486. BIF_CFG_DEV0_EPF3_1_SBRN__SBRN__SHIFT
148487. BIF_CFG_DEV0_EPF3_1_SLOT_CAP2__RESERVED_MASK
148488. BIF_CFG_DEV0_EPF3_1_SLOT_CAP2__RESERVED__SHIFT
148489. BIF_CFG_DEV0_EPF3_1_SLOT_CNTL2__RESERVED_MASK
148490. BIF_CFG_DEV0_EPF3_1_SLOT_CNTL2__RESERVED__SHIFT
148491. BIF_CFG_DEV0_EPF3_1_SLOT_STATUS2__RESERVED_MASK
148492. BIF_CFG_DEV0_EPF3_1_SLOT_STATUS2__RESERVED__SHIFT
148493. BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST_MASK
148494. BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST__SHIFT
148495. BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING_MASK
148496. BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING__SHIFT
148497. BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE_MASK
148498. BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT
148499. BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS_MASK
148500. BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS__SHIFT
148501. BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS_MASK
148502. BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS__SHIFT
148503. BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
148504. BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
148505. BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED_MASK
148506. BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
148507. BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP_MASK
148508. BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP__SHIFT
148509. BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_EN_MASK
148510. BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_EN__SHIFT
148511. BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK
148512. BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
148513. BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK
148514. BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
148515. BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
148516. BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
148517. BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK
148518. BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
148519. BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS_MASK
148520. BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS__SHIFT
148521. BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID_MASK
148522. BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID__SHIFT
148523. BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH_MASK
148524. BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH__SHIFT
148525. BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR_MASK
148526. BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
148527. BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID_MASK
148528. BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID__SHIFT
148529. BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
148530. BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
148531. BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
148532. BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
148533. BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_ID_MASK
148534. BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
148535. BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
148536. BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
148537. BIF_CFG_DEV0_EPF3_2_BASE_ADDR_1__BASE_ADDR_MASK
148538. BIF_CFG_DEV0_EPF3_2_BASE_ADDR_1__BASE_ADDR__SHIFT
148539. BIF_CFG_DEV0_EPF3_2_BASE_ADDR_2__BASE_ADDR_MASK
148540. BIF_CFG_DEV0_EPF3_2_BASE_ADDR_2__BASE_ADDR__SHIFT
148541. BIF_CFG_DEV0_EPF3_2_BASE_ADDR_3__BASE_ADDR_MASK
148542. BIF_CFG_DEV0_EPF3_2_BASE_ADDR_3__BASE_ADDR__SHIFT
148543. BIF_CFG_DEV0_EPF3_2_BASE_ADDR_4__BASE_ADDR_MASK
148544. BIF_CFG_DEV0_EPF3_2_BASE_ADDR_4__BASE_ADDR__SHIFT
148545. BIF_CFG_DEV0_EPF3_2_BASE_ADDR_5__BASE_ADDR_MASK
148546. BIF_CFG_DEV0_EPF3_2_BASE_ADDR_5__BASE_ADDR__SHIFT
148547. BIF_CFG_DEV0_EPF3_2_BASE_ADDR_6__BASE_ADDR_MASK
148548. BIF_CFG_DEV0_EPF3_2_BASE_ADDR_6__BASE_ADDR__SHIFT
148549. BIF_CFG_DEV0_EPF3_2_BASE_CLASS__BASE_CLASS_MASK
148550. BIF_CFG_DEV0_EPF3_2_BASE_CLASS__BASE_CLASS__SHIFT
148551. BIF_CFG_DEV0_EPF3_2_BIST__BIST_CAP_MASK
148552. BIF_CFG_DEV0_EPF3_2_BIST__BIST_CAP__SHIFT
148553. BIF_CFG_DEV0_EPF3_2_BIST__BIST_COMP_MASK
148554. BIF_CFG_DEV0_EPF3_2_BIST__BIST_COMP__SHIFT
148555. BIF_CFG_DEV0_EPF3_2_BIST__BIST_STRT_MASK
148556. BIF_CFG_DEV0_EPF3_2_BIST__BIST_STRT__SHIFT
148557. BIF_CFG_DEV0_EPF3_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
148558. BIF_CFG_DEV0_EPF3_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
148559. BIF_CFG_DEV0_EPF3_2_CAP_PTR__CAP_PTR_MASK
148560. BIF_CFG_DEV0_EPF3_2_CAP_PTR__CAP_PTR__SHIFT
148561. BIF_CFG_DEV0_EPF3_2_COMMAND__AD_STEPPING_MASK
148562. BIF_CFG_DEV0_EPF3_2_COMMAND__AD_STEPPING__SHIFT
148563. BIF_CFG_DEV0_EPF3_2_COMMAND__BUS_MASTER_EN_MASK
148564. BIF_CFG_DEV0_EPF3_2_COMMAND__BUS_MASTER_EN__SHIFT
148565. BIF_CFG_DEV0_EPF3_2_COMMAND__FAST_B2B_EN_MASK
148566. BIF_CFG_DEV0_EPF3_2_COMMAND__FAST_B2B_EN__SHIFT
148567. BIF_CFG_DEV0_EPF3_2_COMMAND__INT_DIS_MASK
148568. BIF_CFG_DEV0_EPF3_2_COMMAND__INT_DIS__SHIFT
148569. BIF_CFG_DEV0_EPF3_2_COMMAND__IO_ACCESS_EN_MASK
148570. BIF_CFG_DEV0_EPF3_2_COMMAND__IO_ACCESS_EN__SHIFT
148571. BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_ACCESS_EN_MASK
148572. BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_ACCESS_EN__SHIFT
148573. BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
148574. BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
148575. BIF_CFG_DEV0_EPF3_2_COMMAND__PAL_SNOOP_EN_MASK
148576. BIF_CFG_DEV0_EPF3_2_COMMAND__PAL_SNOOP_EN__SHIFT
148577. BIF_CFG_DEV0_EPF3_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
148578. BIF_CFG_DEV0_EPF3_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
148579. BIF_CFG_DEV0_EPF3_2_COMMAND__SERR_EN_MASK
148580. BIF_CFG_DEV0_EPF3_2_COMMAND__SERR_EN__SHIFT
148581. BIF_CFG_DEV0_EPF3_2_COMMAND__SPECIAL_CYCLE_EN_MASK
148582. BIF_CFG_DEV0_EPF3_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
148583. BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESLD_MASK
148584. BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESLD__SHIFT
148585. BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESL_MASK
148586. BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESL__SHIFT
148587. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
148588. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
148589. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
148590. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
148591. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
148592. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
148593. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
148594. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
148595. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
148596. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
148597. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
148598. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
148599. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
148600. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
148601. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
148602. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
148603. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
148604. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
148605. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
148606. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
148607. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
148608. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
148609. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
148610. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
148611. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
148612. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
148613. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
148614. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
148615. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
148616. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
148617. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
148618. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
148619. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__EXTENDED_TAG_MASK
148620. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
148621. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__FLR_CAPABLE_MASK
148622. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
148623. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
148624. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
148625. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
148626. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
148627. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
148628. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
148629. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__PHANTOM_FUNC_MASK
148630. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
148631. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
148632. BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
148633. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
148634. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
148635. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
148636. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
148637. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
148638. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
148639. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
148640. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
148641. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
148642. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
148643. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
148644. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
148645. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
148646. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
148647. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
148648. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
148649. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__LTR_EN_MASK
148650. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__LTR_EN__SHIFT
148651. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__OBFF_EN_MASK
148652. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__OBFF_EN__SHIFT
148653. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
148654. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
148655. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__CORR_ERR_EN_MASK
148656. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
148657. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
148658. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
148659. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
148660. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
148661. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__INITIATE_FLR_MASK
148662. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__INITIATE_FLR__SHIFT
148663. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
148664. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
148665. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
148666. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
148667. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
148668. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
148669. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
148670. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
148671. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
148672. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
148673. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
148674. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
148675. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__USR_REPORT_EN_MASK
148676. BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
148677. BIF_CFG_DEV0_EPF3_2_DEVICE_ID__DEVICE_ID_MASK
148678. BIF_CFG_DEV0_EPF3_2_DEVICE_ID__DEVICE_ID__SHIFT
148679. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS2__RESERVED_MASK
148680. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS2__RESERVED__SHIFT
148681. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__AUX_PWR_MASK
148682. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__AUX_PWR__SHIFT
148683. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__CORR_ERR_MASK
148684. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__CORR_ERR__SHIFT
148685. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__FATAL_ERR_MASK
148686. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__FATAL_ERR__SHIFT
148687. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
148688. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
148689. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
148690. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
148691. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__USR_DETECTED_MASK
148692. BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__USR_DETECTED__SHIFT
148693. BIF_CFG_DEV0_EPF3_2_FLADJ__FLADJ_MASK
148694. BIF_CFG_DEV0_EPF3_2_FLADJ__FLADJ__SHIFT
148695. BIF_CFG_DEV0_EPF3_2_HEADER__DEVICE_TYPE_MASK
148696. BIF_CFG_DEV0_EPF3_2_HEADER__DEVICE_TYPE__SHIFT
148697. BIF_CFG_DEV0_EPF3_2_HEADER__HEADER_TYPE_MASK
148698. BIF_CFG_DEV0_EPF3_2_HEADER__HEADER_TYPE__SHIFT
148699. BIF_CFG_DEV0_EPF3_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
148700. BIF_CFG_DEV0_EPF3_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
148701. BIF_CFG_DEV0_EPF3_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
148702. BIF_CFG_DEV0_EPF3_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
148703. BIF_CFG_DEV0_EPF3_2_LATENCY__LATENCY_TIMER_MASK
148704. BIF_CFG_DEV0_EPF3_2_LATENCY__LATENCY_TIMER__SHIFT
148705. BIF_CFG_DEV0_EPF3_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
148706. BIF_CFG_DEV0_EPF3_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
148707. BIF_CFG_DEV0_EPF3_2_LINK_CAP2__RESERVED_MASK
148708. BIF_CFG_DEV0_EPF3_2_LINK_CAP2__RESERVED__SHIFT
148709. BIF_CFG_DEV0_EPF3_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
148710. BIF_CFG_DEV0_EPF3_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
148711. BIF_CFG_DEV0_EPF3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
148712. BIF_CFG_DEV0_EPF3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
148713. BIF_CFG_DEV0_EPF3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
148714. BIF_CFG_DEV0_EPF3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
148715. BIF_CFG_DEV0_EPF3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
148716. BIF_CFG_DEV0_EPF3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
148717. BIF_CFG_DEV0_EPF3_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
148718. BIF_CFG_DEV0_EPF3_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
148719. BIF_CFG_DEV0_EPF3_2_LINK_CAP__L1_EXIT_LATENCY_MASK
148720. BIF_CFG_DEV0_EPF3_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
148721. BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
148722. BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
148723. BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_SPEED_MASK
148724. BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_SPEED__SHIFT
148725. BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_WIDTH_MASK
148726. BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_WIDTH__SHIFT
148727. BIF_CFG_DEV0_EPF3_2_LINK_CAP__PM_SUPPORT_MASK
148728. BIF_CFG_DEV0_EPF3_2_LINK_CAP__PM_SUPPORT__SHIFT
148729. BIF_CFG_DEV0_EPF3_2_LINK_CAP__PORT_NUMBER_MASK
148730. BIF_CFG_DEV0_EPF3_2_LINK_CAP__PORT_NUMBER__SHIFT
148731. BIF_CFG_DEV0_EPF3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
148732. BIF_CFG_DEV0_EPF3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
148733. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
148734. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
148735. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
148736. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
148737. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
148738. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
148739. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
148740. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
148741. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
148742. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
148743. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
148744. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
148745. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
148746. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
148747. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__XMIT_MARGIN_MASK
148748. BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
148749. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
148750. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
148751. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
148752. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
148753. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__EXTENDED_SYNC_MASK
148754. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
148755. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
148756. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
148757. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
148758. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
148759. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
148760. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
148761. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_DIS_MASK
148762. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_DIS__SHIFT
148763. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__PM_CONTROL_MASK
148764. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__PM_CONTROL__SHIFT
148765. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
148766. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
148767. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__RETRAIN_LINK_MASK
148768. BIF_CFG_DEV0_EPF3_2_LINK_CNTL__RETRAIN_LINK__SHIFT
148769. BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
148770. BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
148771. BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
148772. BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
148773. BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
148774. BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
148775. BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
148776. BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
148777. BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
148778. BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
148779. BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
148780. BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
148781. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
148782. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
148783. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__DL_ACTIVE_MASK
148784. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__DL_ACTIVE__SHIFT
148785. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
148786. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
148787. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
148788. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
148789. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_TRAINING_MASK
148790. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_TRAINING__SHIFT
148791. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
148792. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
148793. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
148794. BIF_CFG_DEV0_EPF3_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
148795. BIF_CFG_DEV0_EPF3_2_MAX_LATENCY__MAX_LAT_MASK
148796. BIF_CFG_DEV0_EPF3_2_MAX_LATENCY__MAX_LAT__SHIFT
148797. BIF_CFG_DEV0_EPF3_2_MIN_GRANT__MIN_GNT_MASK
148798. BIF_CFG_DEV0_EPF3_2_MIN_GRANT__MIN_GNT__SHIFT
148799. BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__CAP_ID_MASK
148800. BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__CAP_ID__SHIFT
148801. BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__NEXT_PTR_MASK
148802. BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT
148803. BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_EN_MASK
148804. BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT
148805. BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
148806. BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
148807. BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
148808. BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
148809. BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_BIR_MASK
148810. BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT
148811. BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK
148812. BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
148813. BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK
148814. BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
148815. BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
148816. BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
148817. BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__CAP_ID_MASK
148818. BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__CAP_ID__SHIFT
148819. BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__NEXT_PTR_MASK
148820. BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
148821. BIF_CFG_DEV0_EPF3_2_MSI_MASK_64__MSI_MASK_64_MASK
148822. BIF_CFG_DEV0_EPF3_2_MSI_MASK_64__MSI_MASK_64__SHIFT
148823. BIF_CFG_DEV0_EPF3_2_MSI_MASK__MSI_MASK_MASK
148824. BIF_CFG_DEV0_EPF3_2_MSI_MASK__MSI_MASK__SHIFT
148825. BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
148826. BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
148827. BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
148828. BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
148829. BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_64BIT_MASK
148830. BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
148831. BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_EN_MASK
148832. BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_EN__SHIFT
148833. BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
148834. BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
148835. BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
148836. BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
148837. BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
148838. BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
148839. BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
148840. BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
148841. BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA__MSI_DATA_MASK
148842. BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA__MSI_DATA__SHIFT
148843. BIF_CFG_DEV0_EPF3_2_MSI_PENDING_64__MSI_PENDING_64_MASK
148844. BIF_CFG_DEV0_EPF3_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT
148845. BIF_CFG_DEV0_EPF3_2_MSI_PENDING__MSI_PENDING_MASK
148846. BIF_CFG_DEV0_EPF3_2_MSI_PENDING__MSI_PENDING__SHIFT
148847. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
148848. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
148849. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
148850. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
148851. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
148852. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
148853. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
148854. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
148855. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
148856. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
148857. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
148858. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
148859. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
148860. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
148861. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
148862. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
148863. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
148864. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
148865. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
148866. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
148867. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
148868. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
148869. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
148870. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
148871. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
148872. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
148873. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
148874. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
148875. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
148876. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
148877. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
148878. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
148879. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
148880. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
148881. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
148882. BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
148883. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
148884. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
148885. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
148886. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
148887. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
148888. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
148889. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
148890. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
148891. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
148892. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
148893. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
148894. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
148895. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
148896. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
148897. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
148898. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
148899. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
148900. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
148901. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
148902. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
148903. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
148904. BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
148905. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
148906. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
148907. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
148908. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
148909. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
148910. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
148911. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
148912. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
148913. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
148914. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
148915. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
148916. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
148917. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
148918. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
148919. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
148920. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
148921. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
148922. BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
148923. BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
148924. BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
148925. BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK
148926. BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
148927. BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK
148928. BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
148929. BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
148930. BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
148931. BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
148932. BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
148933. BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK
148934. BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
148935. BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK
148936. BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
148937. BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
148938. BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
148939. BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
148940. BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
148941. BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK
148942. BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
148943. BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK
148944. BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
148945. BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
148946. BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
148947. BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
148948. BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
148949. BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK
148950. BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
148951. BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK
148952. BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
148953. BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
148954. BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
148955. BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
148956. BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
148957. BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK
148958. BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
148959. BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK
148960. BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
148961. BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
148962. BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
148963. BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
148964. BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
148965. BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK
148966. BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
148967. BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK
148968. BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
148969. BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
148970. BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
148971. BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
148972. BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
148973. BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
148974. BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
148975. BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
148976. BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
148977. BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__CAP_ID_MASK
148978. BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__CAP_ID__SHIFT
148979. BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__NEXT_PTR_MASK
148980. BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
148981. BIF_CFG_DEV0_EPF3_2_PCIE_CAP__DEVICE_TYPE_MASK
148982. BIF_CFG_DEV0_EPF3_2_PCIE_CAP__DEVICE_TYPE__SHIFT
148983. BIF_CFG_DEV0_EPF3_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
148984. BIF_CFG_DEV0_EPF3_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
148985. BIF_CFG_DEV0_EPF3_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
148986. BIF_CFG_DEV0_EPF3_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
148987. BIF_CFG_DEV0_EPF3_2_PCIE_CAP__VERSION_MASK
148988. BIF_CFG_DEV0_EPF3_2_PCIE_CAP__VERSION__SHIFT
148989. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
148990. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
148991. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
148992. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
148993. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
148994. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
148995. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
148996. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
148997. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
148998. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
148999. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
149000. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
149001. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
149002. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
149003. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
149004. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
149005. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
149006. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
149007. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
149008. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
149009. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
149010. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
149011. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
149012. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
149013. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
149014. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
149015. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
149016. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
149017. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
149018. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
149019. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
149020. BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
149021. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
149022. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
149023. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
149024. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
149025. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
149026. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
149027. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
149028. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
149029. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
149030. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
149031. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
149032. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
149033. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
149034. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
149035. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
149036. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
149037. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
149038. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
149039. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
149040. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
149041. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
149042. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
149043. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
149044. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
149045. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
149046. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
149047. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
149048. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
149049. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
149050. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
149051. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
149052. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
149053. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
149054. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
149055. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
149056. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
149057. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
149058. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
149059. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
149060. BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
149061. BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG0__TLP_HDR_MASK
149062. BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
149063. BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG1__TLP_HDR_MASK
149064. BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
149065. BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG2__TLP_HDR_MASK
149066. BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
149067. BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG3__TLP_HDR_MASK
149068. BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
149069. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
149070. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
149071. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
149072. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
149073. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
149074. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
149075. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
149076. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
149077. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
149078. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
149079. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
149080. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
149081. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
149082. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
149083. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK
149084. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
149085. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
149086. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
149087. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
149088. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
149089. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
149090. BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
149091. BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
149092. BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
149093. BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
149094. BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
149095. BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
149096. BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
149097. BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
149098. BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
149099. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
149100. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
149101. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
149102. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
149103. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
149104. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
149105. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
149106. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
149107. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
149108. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
149109. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
149110. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
149111. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
149112. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
149113. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
149114. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
149115. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
149116. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
149117. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
149118. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
149119. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
149120. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
149121. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
149122. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
149123. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
149124. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
149125. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
149126. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
149127. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
149128. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
149129. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
149130. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
149131. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
149132. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
149133. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
149134. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
149135. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
149136. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
149137. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
149138. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
149139. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
149140. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
149141. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
149142. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
149143. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
149144. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
149145. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
149146. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
149147. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
149148. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
149149. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
149150. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
149151. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
149152. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
149153. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
149154. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
149155. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
149156. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
149157. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
149158. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
149159. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
149160. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
149161. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
149162. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
149163. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
149164. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
149165. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
149166. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
149167. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
149168. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
149169. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
149170. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
149171. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
149172. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
149173. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
149174. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
149175. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
149176. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
149177. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
149178. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
149179. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
149180. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
149181. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
149182. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
149183. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
149184. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
149185. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
149186. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
149187. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
149188. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
149189. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
149190. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
149191. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
149192. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
149193. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
149194. BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
149195. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
149196. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
149197. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
149198. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
149199. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
149200. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
149201. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
149202. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
149203. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
149204. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
149205. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
149206. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
149207. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
149208. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
149209. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
149210. BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
149211. BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__CAP_ID_MASK
149212. BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__CAP_ID__SHIFT
149213. BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__NEXT_PTR_MASK
149214. BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
149215. BIF_CFG_DEV0_EPF3_2_PMI_CAP__AUX_CURRENT_MASK
149216. BIF_CFG_DEV0_EPF3_2_PMI_CAP__AUX_CURRENT__SHIFT
149217. BIF_CFG_DEV0_EPF3_2_PMI_CAP__D1_SUPPORT_MASK
149218. BIF_CFG_DEV0_EPF3_2_PMI_CAP__D1_SUPPORT__SHIFT
149219. BIF_CFG_DEV0_EPF3_2_PMI_CAP__D2_SUPPORT_MASK
149220. BIF_CFG_DEV0_EPF3_2_PMI_CAP__D2_SUPPORT__SHIFT
149221. BIF_CFG_DEV0_EPF3_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
149222. BIF_CFG_DEV0_EPF3_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
149223. BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_CLOCK_MASK
149224. BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_CLOCK__SHIFT
149225. BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_SUPPORT_MASK
149226. BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_SUPPORT__SHIFT
149227. BIF_CFG_DEV0_EPF3_2_PMI_CAP__VERSION_MASK
149228. BIF_CFG_DEV0_EPF3_2_PMI_CAP__VERSION__SHIFT
149229. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
149230. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
149231. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
149232. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
149233. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
149234. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
149235. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
149236. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
149237. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
149238. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
149239. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_EN_MASK
149240. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_EN__SHIFT
149241. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_STATUS_MASK
149242. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
149243. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PMI_DATA_MASK
149244. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
149245. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__POWER_STATE_MASK
149246. BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
149247. BIF_CFG_DEV0_EPF3_2_PROG_INTERFACE__PROG_INTERFACE_MASK
149248. BIF_CFG_DEV0_EPF3_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
149249. BIF_CFG_DEV0_EPF3_2_REVISION_ID__MAJOR_REV_ID_MASK
149250. BIF_CFG_DEV0_EPF3_2_REVISION_ID__MAJOR_REV_ID__SHIFT
149251. BIF_CFG_DEV0_EPF3_2_REVISION_ID__MINOR_REV_ID_MASK
149252. BIF_CFG_DEV0_EPF3_2_REVISION_ID__MINOR_REV_ID__SHIFT
149253. BIF_CFG_DEV0_EPF3_2_ROM_BASE_ADDR__BASE_ADDR_MASK
149254. BIF_CFG_DEV0_EPF3_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT
149255. BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__CAP_ID_MASK
149256. BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__CAP_ID__SHIFT
149257. BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__NEXT_PTR_MASK
149258. BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__NEXT_PTR__SHIFT
149259. BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
149260. BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
149261. BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
149262. BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
149263. BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
149264. BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
149265. BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
149266. BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
149267. BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
149268. BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
149269. BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
149270. BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
149271. BIF_CFG_DEV0_EPF3_2_SATA_IDP_DATA__IDP_DATA_MASK
149272. BIF_CFG_DEV0_EPF3_2_SATA_IDP_DATA__IDP_DATA__SHIFT
149273. BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_INDEX_MASK
149274. BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT
149275. BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK
149276. BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
149277. BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK
149278. BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
149279. BIF_CFG_DEV0_EPF3_2_SBRN__SBRN_MASK
149280. BIF_CFG_DEV0_EPF3_2_SBRN__SBRN__SHIFT
149281. BIF_CFG_DEV0_EPF3_2_SLOT_CAP2__RESERVED_MASK
149282. BIF_CFG_DEV0_EPF3_2_SLOT_CAP2__RESERVED__SHIFT
149283. BIF_CFG_DEV0_EPF3_2_SLOT_CNTL2__RESERVED_MASK
149284. BIF_CFG_DEV0_EPF3_2_SLOT_CNTL2__RESERVED__SHIFT
149285. BIF_CFG_DEV0_EPF3_2_SLOT_STATUS2__RESERVED_MASK
149286. BIF_CFG_DEV0_EPF3_2_SLOT_STATUS2__RESERVED__SHIFT
149287. BIF_CFG_DEV0_EPF3_2_STATUS__CAP_LIST_MASK
149288. BIF_CFG_DEV0_EPF3_2_STATUS__CAP_LIST__SHIFT
149289. BIF_CFG_DEV0_EPF3_2_STATUS__DEVSEL_TIMING_MASK
149290. BIF_CFG_DEV0_EPF3_2_STATUS__DEVSEL_TIMING__SHIFT
149291. BIF_CFG_DEV0_EPF3_2_STATUS__FAST_BACK_CAPABLE_MASK
149292. BIF_CFG_DEV0_EPF3_2_STATUS__FAST_BACK_CAPABLE__SHIFT
149293. BIF_CFG_DEV0_EPF3_2_STATUS__INT_STATUS_MASK
149294. BIF_CFG_DEV0_EPF3_2_STATUS__INT_STATUS__SHIFT
149295. BIF_CFG_DEV0_EPF3_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
149296. BIF_CFG_DEV0_EPF3_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
149297. BIF_CFG_DEV0_EPF3_2_STATUS__PARITY_ERROR_DETECTED_MASK
149298. BIF_CFG_DEV0_EPF3_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
149299. BIF_CFG_DEV0_EPF3_2_STATUS__PCI_66_EN_MASK
149300. BIF_CFG_DEV0_EPF3_2_STATUS__PCI_66_EN__SHIFT
149301. BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_MASTER_ABORT_MASK
149302. BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
149303. BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_TARGET_ABORT_MASK
149304. BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
149305. BIF_CFG_DEV0_EPF3_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
149306. BIF_CFG_DEV0_EPF3_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
149307. BIF_CFG_DEV0_EPF3_2_STATUS__SIGNAL_TARGET_ABORT_MASK
149308. BIF_CFG_DEV0_EPF3_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
149309. BIF_CFG_DEV0_EPF3_2_SUB_CLASS__SUB_CLASS_MASK
149310. BIF_CFG_DEV0_EPF3_2_SUB_CLASS__SUB_CLASS__SHIFT
149311. BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__CAP_ID_MASK
149312. BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__CAP_ID__SHIFT
149313. BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__LENGTH_MASK
149314. BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__LENGTH__SHIFT
149315. BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__NEXT_PTR_MASK
149316. BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
149317. BIF_CFG_DEV0_EPF3_2_VENDOR_ID__VENDOR_ID_MASK
149318. BIF_CFG_DEV0_EPF3_2_VENDOR_ID__VENDOR_ID__SHIFT
149319. BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
149320. BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
149321. BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
149322. BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
149323. BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID_MASK
149324. BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
149325. BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
149326. BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
149327. BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR_MASK
149328. BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR__SHIFT
149329. BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR_MASK
149330. BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR__SHIFT
149331. BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR_MASK
149332. BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR__SHIFT
149333. BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR_MASK
149334. BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR__SHIFT
149335. BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR_MASK
149336. BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR__SHIFT
149337. BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR_MASK
149338. BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR__SHIFT
149339. BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS_MASK
149340. BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS__SHIFT
149341. BIF_CFG_DEV0_EPF3_BIST__BIST_CAP_MASK
149342. BIF_CFG_DEV0_EPF3_BIST__BIST_CAP__SHIFT
149343. BIF_CFG_DEV0_EPF3_BIST__BIST_COMP_MASK
149344. BIF_CFG_DEV0_EPF3_BIST__BIST_COMP__SHIFT
149345. BIF_CFG_DEV0_EPF3_BIST__BIST_STRT_MASK
149346. BIF_CFG_DEV0_EPF3_BIST__BIST_STRT__SHIFT
149347. BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE_MASK
149348. BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
149349. BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR_MASK
149350. BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR__SHIFT
149351. BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK
149352. BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT
149353. BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING_MASK
149354. BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING__SHIFT
149355. BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN_MASK
149356. BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN__SHIFT
149357. BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN_MASK
149358. BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN__SHIFT
149359. BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS_MASK
149360. BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS__SHIFT
149361. BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN_MASK
149362. BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN__SHIFT
149363. BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN_MASK
149364. BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN__SHIFT
149365. BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
149366. BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
149367. BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN_MASK
149368. BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN__SHIFT
149369. BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE_MASK
149370. BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
149371. BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN_MASK
149372. BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN__SHIFT
149373. BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN_MASK
149374. BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT
149375. BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD_MASK
149376. BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD__SHIFT
149377. BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL_MASK
149378. BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL__SHIFT
149379. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
149380. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
149381. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
149382. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
149383. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
149384. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
149385. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
149386. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
149387. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
149388. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
149389. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
149390. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
149391. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
149392. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
149393. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
149394. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
149395. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
149396. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
149397. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
149398. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
149399. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
149400. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
149401. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED_MASK
149402. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
149403. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
149404. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
149405. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED_MASK
149406. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
149407. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
149408. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
149409. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
149410. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
149411. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK
149412. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
149413. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
149414. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
149415. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
149416. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
149417. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
149418. BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
149419. BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
149420. BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
149421. BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
149422. BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
149423. BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG_MASK
149424. BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG__SHIFT
149425. BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE_MASK
149426. BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE__SHIFT
149427. BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
149428. BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
149429. BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
149430. BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
149431. BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
149432. BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
149433. BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC_MASK
149434. BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT
149435. BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
149436. BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
149437. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
149438. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
149439. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
149440. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
149441. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
149442. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
149443. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
149444. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
149445. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
149446. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
149447. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
149448. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
149449. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
149450. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
149451. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
149452. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
149453. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
149454. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
149455. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN_MASK
149456. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN__SHIFT
149457. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN_MASK
149458. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN__SHIFT
149459. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
149460. BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
149461. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
149462. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
149463. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN_MASK
149464. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT
149465. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
149466. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
149467. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN_MASK
149468. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
149469. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR_MASK
149470. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR__SHIFT
149471. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
149472. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
149473. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
149474. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
149475. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
149476. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
149477. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN_MASK
149478. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
149479. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
149480. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
149481. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK
149482. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
149483. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN_MASK
149484. BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT
149485. BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID_MASK
149486. BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID__SHIFT
149487. BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED_MASK
149488. BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED__SHIFT
149489. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR_MASK
149490. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR__SHIFT
149491. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR_MASK
149492. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR__SHIFT
149493. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
149494. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
149495. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR_MASK
149496. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR__SHIFT
149497. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR_MASK
149498. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
149499. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
149500. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
149501. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED_MASK
149502. BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED__SHIFT
149503. BIF_CFG_DEV0_EPF3_FLADJ__FLADJ_MASK
149504. BIF_CFG_DEV0_EPF3_FLADJ__FLADJ__SHIFT
149505. BIF_CFG_DEV0_EPF3_FLADJ__NFC_MASK
149506. BIF_CFG_DEV0_EPF3_FLADJ__NFC__SHIFT
149507. BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE_MASK
149508. BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE__SHIFT
149509. BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE_MASK
149510. BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE__SHIFT
149511. BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK
149512. BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
149513. BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK
149514. BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
149515. BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER_MASK
149516. BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER__SHIFT
149517. BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
149518. BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
149519. BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
149520. BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
149521. BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
149522. BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
149523. BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
149524. BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
149525. BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
149526. BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
149527. BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
149528. BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
149529. BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
149530. BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
149531. BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
149532. BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
149533. BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
149534. BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
149535. BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
149536. BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
149537. BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY_MASK
149538. BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
149539. BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY_MASK
149540. BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT
149541. BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
149542. BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
149543. BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED_MASK
149544. BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED__SHIFT
149545. BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH_MASK
149546. BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH__SHIFT
149547. BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT_MASK
149548. BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT__SHIFT
149549. BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER_MASK
149550. BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER__SHIFT
149551. BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
149552. BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
149553. BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
149554. BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
149555. BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS_MASK
149556. BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
149557. BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK
149558. BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
149559. BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
149560. BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
149561. BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
149562. BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
149563. BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
149564. BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
149565. BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK
149566. BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
149567. BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN_MASK
149568. BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN__SHIFT
149569. BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
149570. BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
149571. BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK
149572. BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
149573. BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
149574. BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
149575. BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC_MASK
149576. BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC__SHIFT
149577. BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
149578. BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
149579. BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
149580. BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
149581. BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
149582. BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
149583. BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS_MASK
149584. BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS__SHIFT
149585. BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL_MASK
149586. BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL__SHIFT
149587. BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK
149588. BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
149589. BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK_MASK
149590. BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK__SHIFT
149591. BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
149592. BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
149593. BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
149594. BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
149595. BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
149596. BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
149597. BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
149598. BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
149599. BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
149600. BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
149601. BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
149602. BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
149603. BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
149604. BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
149605. BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
149606. BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
149607. BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
149608. BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
149609. BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
149610. BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
149611. BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
149612. BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
149613. BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK
149614. BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
149615. BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE_MASK
149616. BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE__SHIFT
149617. BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
149618. BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
149619. BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
149620. BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
149621. BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING_MASK
149622. BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING__SHIFT
149623. BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
149624. BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
149625. BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK
149626. BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
149627. BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT_MASK
149628. BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT__SHIFT
149629. BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT_MASK
149630. BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT__SHIFT
149631. BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID_MASK
149632. BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID__SHIFT
149633. BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR_MASK
149634. BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT
149635. BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN_MASK
149636. BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT
149637. BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
149638. BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
149639. BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
149640. BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
149641. BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR_MASK
149642. BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT
149643. BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK
149644. BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
149645. BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK
149646. BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
149647. BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
149648. BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
149649. BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID_MASK
149650. BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID__SHIFT
149651. BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR_MASK
149652. BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR__SHIFT
149653. BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64_MASK
149654. BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64__SHIFT
149655. BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK_MASK
149656. BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK__SHIFT
149657. BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
149658. BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
149659. BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
149660. BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
149661. BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT_MASK
149662. BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT
149663. BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN_MASK
149664. BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN__SHIFT
149665. BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
149666. BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
149667. BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
149668. BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
149669. BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
149670. BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
149671. BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK
149672. BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
149673. BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA_MASK
149674. BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA__SHIFT
149675. BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64_MASK
149676. BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT
149677. BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING_MASK
149678. BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING__SHIFT
149679. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
149680. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
149681. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
149682. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
149683. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
149684. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
149685. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
149686. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
149687. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
149688. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
149689. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
149690. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
149691. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
149692. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
149693. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
149694. BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
149695. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
149696. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
149697. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
149698. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
149699. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
149700. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
149701. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
149702. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
149703. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
149704. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
149705. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
149706. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
149707. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
149708. BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
149709. BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
149710. BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
149711. BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
149712. BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
149713. BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
149714. BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
149715. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
149716. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
149717. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
149718. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
149719. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
149720. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
149721. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
149722. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
149723. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
149724. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
149725. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
149726. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
149727. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
149728. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
149729. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
149730. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
149731. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
149732. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
149733. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
149734. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
149735. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
149736. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
149737. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
149738. BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
149739. BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
149740. BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
149741. BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
149742. BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
149743. BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
149744. BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
149745. BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
149746. BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
149747. BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
149748. BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
149749. BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
149750. BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
149751. BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
149752. BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
149753. BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
149754. BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
149755. BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
149756. BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
149757. BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
149758. BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
149759. BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX_MASK
149760. BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
149761. BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_MASK
149762. BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
149763. BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
149764. BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
149765. BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
149766. BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
149767. BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX_MASK
149768. BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
149769. BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_MASK
149770. BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
149771. BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
149772. BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
149773. BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
149774. BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
149775. BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX_MASK
149776. BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
149777. BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_MASK
149778. BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
149779. BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
149780. BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
149781. BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
149782. BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
149783. BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX_MASK
149784. BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
149785. BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_MASK
149786. BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
149787. BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
149788. BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
149789. BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
149790. BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
149791. BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX_MASK
149792. BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
149793. BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_MASK
149794. BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
149795. BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
149796. BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
149797. BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
149798. BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
149799. BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX_MASK
149800. BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
149801. BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_MASK
149802. BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
149803. BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
149804. BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
149805. BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
149806. BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
149807. BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
149808. BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
149809. BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
149810. BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
149811. BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID_MASK
149812. BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID__SHIFT
149813. BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR_MASK
149814. BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT
149815. BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE_MASK
149816. BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE__SHIFT
149817. BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM_MASK
149818. BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
149819. BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK
149820. BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
149821. BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION_MASK
149822. BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION__SHIFT
149823. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
149824. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
149825. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
149826. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
149827. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
149828. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
149829. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
149830. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
149831. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
149832. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
149833. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
149834. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
149835. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
149836. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
149837. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
149838. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
149839. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
149840. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
149841. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
149842. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
149843. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
149844. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
149845. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
149846. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
149847. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
149848. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
149849. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
149850. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
149851. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
149852. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
149853. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
149854. BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
149855. BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
149856. BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
149857. BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
149858. BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
149859. BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
149860. BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
149861. BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
149862. BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
149863. BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
149864. BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
149865. BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
149866. BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
149867. BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
149868. BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
149869. BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
149870. BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
149871. BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
149872. BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
149873. BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
149874. BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
149875. BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
149876. BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
149877. BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
149878. BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
149879. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
149880. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
149881. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
149882. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
149883. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
149884. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
149885. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
149886. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
149887. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
149888. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
149889. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
149890. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
149891. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
149892. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
149893. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
149894. BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
149895. BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR_MASK
149896. BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT
149897. BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR_MASK
149898. BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT
149899. BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR_MASK
149900. BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT
149901. BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR_MASK
149902. BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT
149903. BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
149904. BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
149905. BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
149906. BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
149907. BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
149908. BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
149909. BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE_MASK
149910. BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
149911. BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
149912. BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
149913. BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
149914. BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
149915. BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
149916. BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
149917. BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
149918. BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
149919. BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
149920. BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
149921. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
149922. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
149923. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
149924. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
149925. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
149926. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
149927. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
149928. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
149929. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
149930. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
149931. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
149932. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
149933. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
149934. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
149935. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE_MASK
149936. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
149937. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
149938. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
149939. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
149940. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
149941. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
149942. BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
149943. BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
149944. BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
149945. BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
149946. BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
149947. BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
149948. BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
149949. BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
149950. BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
149951. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
149952. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
149953. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
149954. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
149955. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
149956. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
149957. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
149958. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
149959. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
149960. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
149961. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
149962. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
149963. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
149964. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
149965. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
149966. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
149967. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
149968. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
149969. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
149970. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
149971. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
149972. BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
149973. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK
149974. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT
149975. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK
149976. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT
149977. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK
149978. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT
149979. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK
149980. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT
149981. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK
149982. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT
149983. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK
149984. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT
149985. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK
149986. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT
149987. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK
149988. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT
149989. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK
149990. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT
149991. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK
149992. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT
149993. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK
149994. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT
149995. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK
149996. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT
149997. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK
149998. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT
149999. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK
150000. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT
150001. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK
150002. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT
150003. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK
150004. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT
150005. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK
150006. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT
150007. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK
150008. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT
150009. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK
150010. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT
150011. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK
150012. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT
150013. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK
150014. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT
150015. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK
150016. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT
150017. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK
150018. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT
150019. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK
150020. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT
150021. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK
150022. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT
150023. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK
150024. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT
150025. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK
150026. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT
150027. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK
150028. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT
150029. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK
150030. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT
150031. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK
150032. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT
150033. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK
150034. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT
150035. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK
150036. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT
150037. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK
150038. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT
150039. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK
150040. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT
150041. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK
150042. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT
150043. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK
150044. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT
150045. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK
150046. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT
150047. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK
150048. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT
150049. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK
150050. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT
150051. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK
150052. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT
150053. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK
150054. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT
150055. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK
150056. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT
150057. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK
150058. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT
150059. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK
150060. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT
150061. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK
150062. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT
150063. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK
150064. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT
150065. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK
150066. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT
150067. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK
150068. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT
150069. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK
150070. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT
150071. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK
150072. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT
150073. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK
150074. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT
150075. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK
150076. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT
150077. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK
150078. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT
150079. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK
150080. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT
150081. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK
150082. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT
150083. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK
150084. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT
150085. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK
150086. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT
150087. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK
150088. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT
150089. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK
150090. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT
150091. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK
150092. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT
150093. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK
150094. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT
150095. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK
150096. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT
150097. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK
150098. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT
150099. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK
150100. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT
150101. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK
150102. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT
150103. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK
150104. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT
150105. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK
150106. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT
150107. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK
150108. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT
150109. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK
150110. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT
150111. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK
150112. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT
150113. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK
150114. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT
150115. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK
150116. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT
150117. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK
150118. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT
150119. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK
150120. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT
150121. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK
150122. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT
150123. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK
150124. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT
150125. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK
150126. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT
150127. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK
150128. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT
150129. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK
150130. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT
150131. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK
150132. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT
150133. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK
150134. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT
150135. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK
150136. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT
150137. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK
150138. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT
150139. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK
150140. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT
150141. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK
150142. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT
150143. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK
150144. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT
150145. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK
150146. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT
150147. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK
150148. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT
150149. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK
150150. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT
150151. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK
150152. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT
150153. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK
150154. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT
150155. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK
150156. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT
150157. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK
150158. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT
150159. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK
150160. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT
150161. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK
150162. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT
150163. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK
150164. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT
150165. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK
150166. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT
150167. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK
150168. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT
150169. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK
150170. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT
150171. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK
150172. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT
150173. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK
150174. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT
150175. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK
150176. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT
150177. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK
150178. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT
150179. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK
150180. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT
150181. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK
150182. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT
150183. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK
150184. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT
150185. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK
150186. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT
150187. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK
150188. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT
150189. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK
150190. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT
150191. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK
150192. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT
150193. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK
150194. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT
150195. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK
150196. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT
150197. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK
150198. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT
150199. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK
150200. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT
150201. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK
150202. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT
150203. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK
150204. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT
150205. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK
150206. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT
150207. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK
150208. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT
150209. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK
150210. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT
150211. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK
150212. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT
150213. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK
150214. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT
150215. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK
150216. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT
150217. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK
150218. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT
150219. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK
150220. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT
150221. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK
150222. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT
150223. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK
150224. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT
150225. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK
150226. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT
150227. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK
150228. BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT
150229. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
150230. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
150231. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
150232. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
150233. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
150234. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
150235. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
150236. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
150237. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
150238. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
150239. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
150240. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
150241. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
150242. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
150243. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
150244. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
150245. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
150246. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
150247. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
150248. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
150249. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
150250. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
150251. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
150252. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
150253. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
150254. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
150255. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
150256. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
150257. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
150258. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
150259. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
150260. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
150261. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
150262. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
150263. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
150264. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
150265. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
150266. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
150267. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
150268. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
150269. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
150270. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
150271. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
150272. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
150273. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
150274. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
150275. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
150276. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
150277. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
150278. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
150279. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
150280. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
150281. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
150282. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
150283. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
150284. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
150285. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
150286. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
150287. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
150288. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
150289. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
150290. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
150291. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
150292. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
150293. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
150294. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
150295. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
150296. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
150297. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
150298. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
150299. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
150300. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
150301. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
150302. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
150303. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
150304. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
150305. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
150306. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
150307. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
150308. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
150309. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
150310. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
150311. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
150312. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
150313. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
150314. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
150315. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
150316. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
150317. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
150318. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
150319. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
150320. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
150321. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
150322. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
150323. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
150324. BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
150325. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
150326. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
150327. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
150328. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
150329. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
150330. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
150331. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
150332. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
150333. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
150334. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
150335. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
150336. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
150337. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
150338. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
150339. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
150340. BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
150341. BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID_MASK
150342. BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID__SHIFT
150343. BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR_MASK
150344. BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR__SHIFT
150345. BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT_MASK
150346. BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT__SHIFT
150347. BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT_MASK
150348. BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT__SHIFT
150349. BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT_MASK
150350. BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT__SHIFT
150351. BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT_MASK
150352. BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
150353. BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
150354. BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
150355. BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK_MASK
150356. BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK__SHIFT
150357. BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT_MASK
150358. BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT__SHIFT
150359. BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION_MASK
150360. BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION__SHIFT
150361. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
150362. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
150363. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
150364. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
150365. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE_MASK
150366. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
150367. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT_MASK
150368. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
150369. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
150370. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
150371. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN_MASK
150372. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN__SHIFT
150373. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS_MASK
150374. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS__SHIFT
150375. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA_MASK
150376. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA__SHIFT
150377. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE_MASK
150378. BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE__SHIFT
150379. BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE_MASK
150380. BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT
150381. BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID_MASK
150382. BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID__SHIFT
150383. BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID_MASK
150384. BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID__SHIFT
150385. BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR_MASK
150386. BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT
150387. BIF_CFG_DEV0_EPF3_SATA_CAP_0__CAP_ID_MASK
150388. BIF_CFG_DEV0_EPF3_SATA_CAP_0__CAP_ID__SHIFT
150389. BIF_CFG_DEV0_EPF3_SATA_CAP_0__NEXT_PTR_MASK
150390. BIF_CFG_DEV0_EPF3_SATA_CAP_0__NEXT_PTR__SHIFT
150391. BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
150392. BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
150393. BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
150394. BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
150395. BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
150396. BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
150397. BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
150398. BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
150399. BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
150400. BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
150401. BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
150402. BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
150403. BIF_CFG_DEV0_EPF3_SATA_IDP_DATA__IDP_DATA_MASK
150404. BIF_CFG_DEV0_EPF3_SATA_IDP_DATA__IDP_DATA__SHIFT
150405. BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_INDEX_MASK
150406. BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_INDEX__SHIFT
150407. BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_RESERVED1_MASK
150408. BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
150409. BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_RESERVED2_MASK
150410. BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
150411. BIF_CFG_DEV0_EPF3_SBRN__SBRN_MASK
150412. BIF_CFG_DEV0_EPF3_SBRN__SBRN__SHIFT
150413. BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST_MASK
150414. BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST__SHIFT
150415. BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING_MASK
150416. BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING__SHIFT
150417. BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE_MASK
150418. BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE__SHIFT
150419. BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS_MASK
150420. BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS__SHIFT
150421. BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS_MASK
150422. BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS__SHIFT
150423. BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK
150424. BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
150425. BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED_MASK
150426. BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED__SHIFT
150427. BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP_MASK
150428. BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP__SHIFT
150429. BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT_MASK
150430. BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT
150431. BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT_MASK
150432. BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT
150433. BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK
150434. BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
150435. BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT_MASK
150436. BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT
150437. BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS_MASK
150438. BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS__SHIFT
150439. BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID_MASK
150440. BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID__SHIFT
150441. BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH_MASK
150442. BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH__SHIFT
150443. BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR_MASK
150444. BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
150445. BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID_MASK
150446. BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID__SHIFT
150447. BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
150448. BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
150449. BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
150450. BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
150451. BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
150452. BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
150453. BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
150454. BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
150455. BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR_MASK
150456. BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT
150457. BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR_MASK
150458. BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT
150459. BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR_MASK
150460. BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT
150461. BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR_MASK
150462. BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT
150463. BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR_MASK
150464. BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT
150465. BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR_MASK
150466. BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT
150467. BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS_MASK
150468. BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS__SHIFT
150469. BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP_MASK
150470. BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP__SHIFT
150471. BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP_MASK
150472. BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP__SHIFT
150473. BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT_MASK
150474. BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT__SHIFT
150475. BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
150476. BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
150477. BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR_MASK
150478. BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR__SHIFT
150479. BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING_MASK
150480. BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING__SHIFT
150481. BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN_MASK
150482. BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN__SHIFT
150483. BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN_MASK
150484. BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN__SHIFT
150485. BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS_MASK
150486. BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS__SHIFT
150487. BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN_MASK
150488. BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN__SHIFT
150489. BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN_MASK
150490. BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN__SHIFT
150491. BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
150492. BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
150493. BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN_MASK
150494. BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN__SHIFT
150495. BIF_CFG_DEV0_EPF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
150496. BIF_CFG_DEV0_EPF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
150497. BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN_MASK
150498. BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN__SHIFT
150499. BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK
150500. BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
150501. BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD_MASK
150502. BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD__SHIFT
150503. BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL_MASK
150504. BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL__SHIFT
150505. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
150506. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
150507. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
150508. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
150509. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
150510. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
150511. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
150512. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
150513. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
150514. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
150515. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
150516. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
150517. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
150518. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
150519. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
150520. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
150521. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
150522. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
150523. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
150524. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
150525. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
150526. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
150527. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
150528. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
150529. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
150530. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
150531. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
150532. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
150533. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
150534. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
150535. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
150536. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
150537. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG_MASK
150538. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
150539. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE_MASK
150540. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
150541. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
150542. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
150543. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
150544. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
150545. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
150546. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
150547. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK
150548. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
150549. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
150550. BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
150551. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
150552. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
150553. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
150554. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
150555. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
150556. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
150557. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
150558. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
150559. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
150560. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
150561. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
150562. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
150563. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
150564. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
150565. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
150566. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
150567. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN_MASK
150568. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN__SHIFT
150569. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN_MASK
150570. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT
150571. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
150572. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
150573. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK
150574. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
150575. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
150576. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
150577. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
150578. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
150579. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR_MASK
150580. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
150581. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
150582. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
150583. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
150584. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
150585. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
150586. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
150587. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
150588. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
150589. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
150590. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
150591. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
150592. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
150593. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK
150594. BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
150595. BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID_MASK
150596. BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID__SHIFT
150597. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED_MASK
150598. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED__SHIFT
150599. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR_MASK
150600. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR__SHIFT
150601. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR_MASK
150602. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR__SHIFT
150603. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR_MASK
150604. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT
150605. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
150606. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
150607. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
150608. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
150609. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED_MASK
150610. BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT
150611. BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ_MASK
150612. BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ__SHIFT
150613. BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE_MASK
150614. BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE__SHIFT
150615. BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE_MASK
150616. BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE__SHIFT
150617. BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
150618. BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
150619. BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
150620. BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
150621. BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER_MASK
150622. BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER__SHIFT
150623. BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
150624. BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
150625. BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RESERVED_MASK
150626. BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RESERVED__SHIFT
150627. BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
150628. BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
150629. BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
150630. BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
150631. BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
150632. BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
150633. BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
150634. BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
150635. BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
150636. BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
150637. BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK
150638. BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
150639. BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
150640. BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
150641. BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED_MASK
150642. BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED__SHIFT
150643. BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH_MASK
150644. BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH__SHIFT
150645. BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT_MASK
150646. BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT__SHIFT
150647. BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER_MASK
150648. BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER__SHIFT
150649. BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
150650. BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
150651. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
150652. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
150653. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
150654. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
150655. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
150656. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
150657. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
150658. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
150659. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
150660. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
150661. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
150662. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
150663. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
150664. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
150665. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN_MASK
150666. BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
150667. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
150668. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
150669. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
150670. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
150671. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC_MASK
150672. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
150673. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
150674. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
150675. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
150676. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
150677. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
150678. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
150679. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS_MASK
150680. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS__SHIFT
150681. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL_MASK
150682. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL__SHIFT
150683. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
150684. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
150685. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK_MASK
150686. BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT
150687. BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
150688. BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
150689. BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
150690. BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
150691. BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
150692. BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
150693. BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
150694. BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
150695. BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
150696. BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
150697. BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
150698. BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
150699. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
150700. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
150701. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE_MASK
150702. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE__SHIFT
150703. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
150704. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
150705. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
150706. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
150707. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING_MASK
150708. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING__SHIFT
150709. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
150710. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
150711. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
150712. BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
150713. BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT_MASK
150714. BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT__SHIFT
150715. BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT_MASK
150716. BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT__SHIFT
150717. BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID_MASK
150718. BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT
150719. BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK
150720. BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
150721. BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK
150722. BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
150723. BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
150724. BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
150725. BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
150726. BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
150727. BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK
150728. BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
150729. BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
150730. BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
150731. BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
150732. BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
150733. BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
150734. BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
150735. BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID_MASK
150736. BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID__SHIFT
150737. BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR_MASK
150738. BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
150739. BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64_MASK
150740. BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT
150741. BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK_MASK
150742. BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK__SHIFT
150743. BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
150744. BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
150745. BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
150746. BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
150747. BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK
150748. BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
150749. BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN_MASK
150750. BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT
150751. BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
150752. BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
150753. BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
150754. BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
150755. BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
150756. BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
150757. BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
150758. BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
150759. BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA_MASK
150760. BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT
150761. BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK
150762. BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
150763. BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING_MASK
150764. BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING__SHIFT
150765. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
150766. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
150767. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
150768. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
150769. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
150770. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
150771. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
150772. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
150773. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
150774. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
150775. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
150776. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
150777. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
150778. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
150779. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
150780. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
150781. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
150782. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
150783. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
150784. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
150785. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
150786. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
150787. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
150788. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
150789. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
150790. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
150791. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
150792. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
150793. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
150794. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
150795. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
150796. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
150797. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
150798. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
150799. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
150800. BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
150801. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
150802. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
150803. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
150804. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
150805. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
150806. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
150807. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
150808. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
150809. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
150810. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
150811. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
150812. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
150813. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
150814. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
150815. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
150816. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
150817. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
150818. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
150819. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
150820. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
150821. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
150822. BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
150823. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
150824. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
150825. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
150826. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
150827. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
150828. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
150829. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
150830. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
150831. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
150832. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
150833. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
150834. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
150835. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
150836. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
150837. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
150838. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
150839. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
150840. BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
150841. BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
150842. BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
150843. BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK
150844. BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
150845. BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK
150846. BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
150847. BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
150848. BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
150849. BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
150850. BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
150851. BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK
150852. BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
150853. BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK
150854. BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
150855. BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
150856. BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
150857. BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
150858. BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
150859. BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK
150860. BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
150861. BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK
150862. BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
150863. BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
150864. BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
150865. BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
150866. BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
150867. BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK
150868. BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
150869. BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK
150870. BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
150871. BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
150872. BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
150873. BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
150874. BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
150875. BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK
150876. BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
150877. BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK
150878. BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
150879. BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
150880. BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
150881. BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
150882. BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
150883. BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK
150884. BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
150885. BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK
150886. BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
150887. BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
150888. BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
150889. BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
150890. BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
150891. BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
150892. BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
150893. BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
150894. BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
150895. BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID_MASK
150896. BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT
150897. BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK
150898. BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
150899. BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE_MASK
150900. BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT
150901. BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
150902. BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
150903. BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
150904. BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
150905. BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION_MASK
150906. BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION__SHIFT
150907. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
150908. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
150909. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
150910. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
150911. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
150912. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
150913. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
150914. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
150915. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
150916. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
150917. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
150918. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
150919. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
150920. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
150921. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
150922. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
150923. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
150924. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
150925. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
150926. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
150927. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
150928. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
150929. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
150930. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
150931. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
150932. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
150933. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
150934. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
150935. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
150936. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
150937. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
150938. BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
150939. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
150940. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
150941. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
150942. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
150943. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
150944. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
150945. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
150946. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
150947. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
150948. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
150949. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
150950. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
150951. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
150952. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
150953. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
150954. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
150955. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
150956. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
150957. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
150958. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
150959. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
150960. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
150961. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
150962. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
150963. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
150964. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
150965. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
150966. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
150967. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
150968. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
150969. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
150970. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
150971. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
150972. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
150973. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
150974. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
150975. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
150976. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
150977. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
150978. BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
150979. BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK
150980. BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
150981. BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK
150982. BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
150983. BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK
150984. BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
150985. BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK
150986. BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
150987. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
150988. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
150989. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
150990. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
150991. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
150992. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
150993. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
150994. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
150995. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
150996. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
150997. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
150998. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
150999. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
151000. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
151001. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK
151002. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
151003. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
151004. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
151005. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
151006. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
151007. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
151008. BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
151009. BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
151010. BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
151011. BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
151012. BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
151013. BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
151014. BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
151015. BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
151016. BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
151017. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
151018. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
151019. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
151020. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
151021. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
151022. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
151023. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
151024. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
151025. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
151026. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
151027. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
151028. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
151029. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
151030. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
151031. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
151032. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
151033. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
151034. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
151035. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
151036. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
151037. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
151038. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
151039. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
151040. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
151041. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
151042. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
151043. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
151044. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
151045. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
151046. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
151047. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
151048. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
151049. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
151050. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
151051. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
151052. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
151053. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
151054. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
151055. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
151056. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
151057. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
151058. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
151059. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
151060. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
151061. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
151062. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
151063. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
151064. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
151065. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
151066. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
151067. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
151068. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
151069. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
151070. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
151071. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
151072. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
151073. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
151074. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
151075. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
151076. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
151077. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
151078. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
151079. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
151080. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
151081. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
151082. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
151083. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
151084. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
151085. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
151086. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
151087. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
151088. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
151089. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
151090. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
151091. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
151092. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
151093. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
151094. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
151095. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
151096. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
151097. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
151098. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
151099. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
151100. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
151101. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
151102. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
151103. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
151104. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
151105. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
151106. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
151107. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
151108. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
151109. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
151110. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
151111. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
151112. BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
151113. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
151114. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
151115. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
151116. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
151117. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
151118. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
151119. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
151120. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
151121. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
151122. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
151123. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
151124. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
151125. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
151126. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
151127. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
151128. BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
151129. BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID_MASK
151130. BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID__SHIFT
151131. BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR_MASK
151132. BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
151133. BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT_MASK
151134. BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT__SHIFT
151135. BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT_MASK
151136. BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT__SHIFT
151137. BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT_MASK
151138. BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT__SHIFT
151139. BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
151140. BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
151141. BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK_MASK
151142. BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK__SHIFT
151143. BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT_MASK
151144. BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT__SHIFT
151145. BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION_MASK
151146. BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION__SHIFT
151147. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
151148. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
151149. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
151150. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
151151. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
151152. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
151153. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
151154. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
151155. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
151156. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
151157. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN_MASK
151158. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN__SHIFT
151159. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS_MASK
151160. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
151161. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA_MASK
151162. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
151163. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE_MASK
151164. BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
151165. BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK
151166. BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
151167. BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID_MASK
151168. BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT
151169. BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID_MASK
151170. BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID__SHIFT
151171. BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK
151172. BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
151173. BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__CAP_ID_MASK
151174. BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__CAP_ID__SHIFT
151175. BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__NEXT_PTR_MASK
151176. BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__NEXT_PTR__SHIFT
151177. BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
151178. BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
151179. BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
151180. BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
151181. BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
151182. BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
151183. BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
151184. BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
151185. BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
151186. BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
151187. BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
151188. BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
151189. BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA__IDP_DATA_MASK
151190. BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA__IDP_DATA__SHIFT
151191. BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_INDEX_MASK
151192. BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT
151193. BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK
151194. BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
151195. BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK
151196. BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
151197. BIF_CFG_DEV0_EPF4_0_SBRN__SBRN_MASK
151198. BIF_CFG_DEV0_EPF4_0_SBRN__SBRN__SHIFT
151199. BIF_CFG_DEV0_EPF4_0_SLOT_CAP2__RESERVED_MASK
151200. BIF_CFG_DEV0_EPF4_0_SLOT_CAP2__RESERVED__SHIFT
151201. BIF_CFG_DEV0_EPF4_0_SLOT_CNTL2__RESERVED_MASK
151202. BIF_CFG_DEV0_EPF4_0_SLOT_CNTL2__RESERVED__SHIFT
151203. BIF_CFG_DEV0_EPF4_0_SLOT_STATUS2__RESERVED_MASK
151204. BIF_CFG_DEV0_EPF4_0_SLOT_STATUS2__RESERVED__SHIFT
151205. BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST_MASK
151206. BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST__SHIFT
151207. BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING_MASK
151208. BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING__SHIFT
151209. BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE_MASK
151210. BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT
151211. BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS_MASK
151212. BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS__SHIFT
151213. BIF_CFG_DEV0_EPF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
151214. BIF_CFG_DEV0_EPF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
151215. BIF_CFG_DEV0_EPF4_0_STATUS__PARITY_ERROR_DETECTED_MASK
151216. BIF_CFG_DEV0_EPF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
151217. BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_EN_MASK
151218. BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_EN__SHIFT
151219. BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK
151220. BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
151221. BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK
151222. BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
151223. BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
151224. BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
151225. BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK
151226. BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
151227. BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS_MASK
151228. BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS__SHIFT
151229. BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID_MASK
151230. BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID__SHIFT
151231. BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH_MASK
151232. BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH__SHIFT
151233. BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR_MASK
151234. BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
151235. BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID_MASK
151236. BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID__SHIFT
151237. BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
151238. BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
151239. BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
151240. BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
151241. BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
151242. BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
151243. BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
151244. BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
151245. BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1__BASE_ADDR_MASK
151246. BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT
151247. BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2__BASE_ADDR_MASK
151248. BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT
151249. BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3__BASE_ADDR_MASK
151250. BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT
151251. BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4__BASE_ADDR_MASK
151252. BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT
151253. BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5__BASE_ADDR_MASK
151254. BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT
151255. BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6__BASE_ADDR_MASK
151256. BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT
151257. BIF_CFG_DEV0_EPF4_1_BASE_CLASS__BASE_CLASS_MASK
151258. BIF_CFG_DEV0_EPF4_1_BASE_CLASS__BASE_CLASS__SHIFT
151259. BIF_CFG_DEV0_EPF4_1_BIST__BIST_CAP_MASK
151260. BIF_CFG_DEV0_EPF4_1_BIST__BIST_CAP__SHIFT
151261. BIF_CFG_DEV0_EPF4_1_BIST__BIST_COMP_MASK
151262. BIF_CFG_DEV0_EPF4_1_BIST__BIST_COMP__SHIFT
151263. BIF_CFG_DEV0_EPF4_1_BIST__BIST_STRT_MASK
151264. BIF_CFG_DEV0_EPF4_1_BIST__BIST_STRT__SHIFT
151265. BIF_CFG_DEV0_EPF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
151266. BIF_CFG_DEV0_EPF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
151267. BIF_CFG_DEV0_EPF4_1_CAP_PTR__CAP_PTR_MASK
151268. BIF_CFG_DEV0_EPF4_1_CAP_PTR__CAP_PTR__SHIFT
151269. BIF_CFG_DEV0_EPF4_1_COMMAND__AD_STEPPING_MASK
151270. BIF_CFG_DEV0_EPF4_1_COMMAND__AD_STEPPING__SHIFT
151271. BIF_CFG_DEV0_EPF4_1_COMMAND__BUS_MASTER_EN_MASK
151272. BIF_CFG_DEV0_EPF4_1_COMMAND__BUS_MASTER_EN__SHIFT
151273. BIF_CFG_DEV0_EPF4_1_COMMAND__FAST_B2B_EN_MASK
151274. BIF_CFG_DEV0_EPF4_1_COMMAND__FAST_B2B_EN__SHIFT
151275. BIF_CFG_DEV0_EPF4_1_COMMAND__INT_DIS_MASK
151276. BIF_CFG_DEV0_EPF4_1_COMMAND__INT_DIS__SHIFT
151277. BIF_CFG_DEV0_EPF4_1_COMMAND__IO_ACCESS_EN_MASK
151278. BIF_CFG_DEV0_EPF4_1_COMMAND__IO_ACCESS_EN__SHIFT
151279. BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_ACCESS_EN_MASK
151280. BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_ACCESS_EN__SHIFT
151281. BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
151282. BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
151283. BIF_CFG_DEV0_EPF4_1_COMMAND__PAL_SNOOP_EN_MASK
151284. BIF_CFG_DEV0_EPF4_1_COMMAND__PAL_SNOOP_EN__SHIFT
151285. BIF_CFG_DEV0_EPF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
151286. BIF_CFG_DEV0_EPF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
151287. BIF_CFG_DEV0_EPF4_1_COMMAND__SERR_EN_MASK
151288. BIF_CFG_DEV0_EPF4_1_COMMAND__SERR_EN__SHIFT
151289. BIF_CFG_DEV0_EPF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK
151290. BIF_CFG_DEV0_EPF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
151291. BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESLD_MASK
151292. BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESLD__SHIFT
151293. BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESL_MASK
151294. BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESL__SHIFT
151295. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
151296. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
151297. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
151298. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
151299. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
151300. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
151301. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
151302. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
151303. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
151304. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
151305. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
151306. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
151307. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
151308. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
151309. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
151310. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
151311. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
151312. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
151313. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
151314. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
151315. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
151316. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
151317. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
151318. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
151319. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
151320. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
151321. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
151322. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
151323. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
151324. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
151325. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
151326. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
151327. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__EXTENDED_TAG_MASK
151328. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
151329. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__FLR_CAPABLE_MASK
151330. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
151331. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
151332. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
151333. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
151334. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
151335. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
151336. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
151337. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK
151338. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
151339. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
151340. BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
151341. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
151342. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
151343. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
151344. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
151345. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
151346. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
151347. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
151348. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
151349. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
151350. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
151351. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
151352. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
151353. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
151354. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
151355. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
151356. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
151357. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__LTR_EN_MASK
151358. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__LTR_EN__SHIFT
151359. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__OBFF_EN_MASK
151360. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT
151361. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
151362. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
151363. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK
151364. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
151365. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
151366. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
151367. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
151368. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
151369. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__INITIATE_FLR_MASK
151370. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
151371. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
151372. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
151373. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
151374. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
151375. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
151376. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
151377. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
151378. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
151379. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
151380. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
151381. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
151382. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
151383. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK
151384. BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
151385. BIF_CFG_DEV0_EPF4_1_DEVICE_ID__DEVICE_ID_MASK
151386. BIF_CFG_DEV0_EPF4_1_DEVICE_ID__DEVICE_ID__SHIFT
151387. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2__RESERVED_MASK
151388. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2__RESERVED__SHIFT
151389. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__AUX_PWR_MASK
151390. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__AUX_PWR__SHIFT
151391. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__CORR_ERR_MASK
151392. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__CORR_ERR__SHIFT
151393. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__FATAL_ERR_MASK
151394. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT
151395. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
151396. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
151397. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
151398. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
151399. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__USR_DETECTED_MASK
151400. BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT
151401. BIF_CFG_DEV0_EPF4_1_FLADJ__FLADJ_MASK
151402. BIF_CFG_DEV0_EPF4_1_FLADJ__FLADJ__SHIFT
151403. BIF_CFG_DEV0_EPF4_1_HEADER__DEVICE_TYPE_MASK
151404. BIF_CFG_DEV0_EPF4_1_HEADER__DEVICE_TYPE__SHIFT
151405. BIF_CFG_DEV0_EPF4_1_HEADER__HEADER_TYPE_MASK
151406. BIF_CFG_DEV0_EPF4_1_HEADER__HEADER_TYPE__SHIFT
151407. BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
151408. BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
151409. BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
151410. BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
151411. BIF_CFG_DEV0_EPF4_1_LATENCY__LATENCY_TIMER_MASK
151412. BIF_CFG_DEV0_EPF4_1_LATENCY__LATENCY_TIMER__SHIFT
151413. BIF_CFG_DEV0_EPF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
151414. BIF_CFG_DEV0_EPF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
151415. BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RESERVED_MASK
151416. BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RESERVED__SHIFT
151417. BIF_CFG_DEV0_EPF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
151418. BIF_CFG_DEV0_EPF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
151419. BIF_CFG_DEV0_EPF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
151420. BIF_CFG_DEV0_EPF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
151421. BIF_CFG_DEV0_EPF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
151422. BIF_CFG_DEV0_EPF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
151423. BIF_CFG_DEV0_EPF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
151424. BIF_CFG_DEV0_EPF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
151425. BIF_CFG_DEV0_EPF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
151426. BIF_CFG_DEV0_EPF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
151427. BIF_CFG_DEV0_EPF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK
151428. BIF_CFG_DEV0_EPF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
151429. BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
151430. BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
151431. BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_SPEED_MASK
151432. BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_SPEED__SHIFT
151433. BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_WIDTH_MASK
151434. BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_WIDTH__SHIFT
151435. BIF_CFG_DEV0_EPF4_1_LINK_CAP__PM_SUPPORT_MASK
151436. BIF_CFG_DEV0_EPF4_1_LINK_CAP__PM_SUPPORT__SHIFT
151437. BIF_CFG_DEV0_EPF4_1_LINK_CAP__PORT_NUMBER_MASK
151438. BIF_CFG_DEV0_EPF4_1_LINK_CAP__PORT_NUMBER__SHIFT
151439. BIF_CFG_DEV0_EPF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
151440. BIF_CFG_DEV0_EPF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
151441. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
151442. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
151443. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
151444. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
151445. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
151446. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
151447. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
151448. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
151449. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
151450. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
151451. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
151452. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
151453. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
151454. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
151455. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__XMIT_MARGIN_MASK
151456. BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
151457. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
151458. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
151459. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
151460. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
151461. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__EXTENDED_SYNC_MASK
151462. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
151463. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
151464. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
151465. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
151466. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
151467. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
151468. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
151469. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_DIS_MASK
151470. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_DIS__SHIFT
151471. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__PM_CONTROL_MASK
151472. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__PM_CONTROL__SHIFT
151473. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
151474. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
151475. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__RETRAIN_LINK_MASK
151476. BIF_CFG_DEV0_EPF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT
151477. BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
151478. BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
151479. BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
151480. BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
151481. BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
151482. BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
151483. BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
151484. BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
151485. BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
151486. BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
151487. BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
151488. BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
151489. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
151490. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
151491. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__DL_ACTIVE_MASK
151492. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__DL_ACTIVE__SHIFT
151493. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
151494. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
151495. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
151496. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
151497. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_TRAINING_MASK
151498. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_TRAINING__SHIFT
151499. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
151500. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
151501. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
151502. BIF_CFG_DEV0_EPF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
151503. BIF_CFG_DEV0_EPF4_1_MAX_LATENCY__MAX_LAT_MASK
151504. BIF_CFG_DEV0_EPF4_1_MAX_LATENCY__MAX_LAT__SHIFT
151505. BIF_CFG_DEV0_EPF4_1_MIN_GRANT__MIN_GNT_MASK
151506. BIF_CFG_DEV0_EPF4_1_MIN_GRANT__MIN_GNT__SHIFT
151507. BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__CAP_ID_MASK
151508. BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT
151509. BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK
151510. BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
151511. BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK
151512. BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
151513. BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
151514. BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
151515. BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
151516. BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
151517. BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK
151518. BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
151519. BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
151520. BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
151521. BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
151522. BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
151523. BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
151524. BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
151525. BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__CAP_ID_MASK
151526. BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__CAP_ID__SHIFT
151527. BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__NEXT_PTR_MASK
151528. BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
151529. BIF_CFG_DEV0_EPF4_1_MSI_MASK_64__MSI_MASK_64_MASK
151530. BIF_CFG_DEV0_EPF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT
151531. BIF_CFG_DEV0_EPF4_1_MSI_MASK__MSI_MASK_MASK
151532. BIF_CFG_DEV0_EPF4_1_MSI_MASK__MSI_MASK__SHIFT
151533. BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
151534. BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
151535. BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
151536. BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
151537. BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK
151538. BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
151539. BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EN_MASK
151540. BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT
151541. BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
151542. BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
151543. BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
151544. BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
151545. BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
151546. BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
151547. BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
151548. BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
151549. BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA__MSI_DATA_MASK
151550. BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT
151551. BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK
151552. BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
151553. BIF_CFG_DEV0_EPF4_1_MSI_PENDING__MSI_PENDING_MASK
151554. BIF_CFG_DEV0_EPF4_1_MSI_PENDING__MSI_PENDING__SHIFT
151555. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
151556. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
151557. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
151558. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
151559. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
151560. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
151561. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
151562. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
151563. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
151564. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
151565. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
151566. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
151567. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
151568. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
151569. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
151570. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
151571. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
151572. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
151573. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
151574. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
151575. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
151576. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
151577. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
151578. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
151579. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
151580. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
151581. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
151582. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
151583. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
151584. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
151585. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
151586. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
151587. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
151588. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
151589. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
151590. BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
151591. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
151592. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
151593. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
151594. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
151595. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
151596. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
151597. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
151598. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
151599. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
151600. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
151601. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
151602. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
151603. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
151604. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
151605. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
151606. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
151607. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
151608. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
151609. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
151610. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
151611. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
151612. BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
151613. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
151614. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
151615. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
151616. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
151617. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
151618. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
151619. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
151620. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
151621. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
151622. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
151623. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
151624. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
151625. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
151626. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
151627. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
151628. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
151629. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
151630. BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
151631. BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
151632. BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
151633. BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK
151634. BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
151635. BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK
151636. BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
151637. BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
151638. BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
151639. BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
151640. BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
151641. BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK
151642. BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
151643. BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK
151644. BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
151645. BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
151646. BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
151647. BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
151648. BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
151649. BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK
151650. BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
151651. BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK
151652. BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
151653. BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
151654. BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
151655. BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
151656. BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
151657. BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK
151658. BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
151659. BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK
151660. BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
151661. BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
151662. BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
151663. BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
151664. BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
151665. BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK
151666. BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
151667. BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK
151668. BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
151669. BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
151670. BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
151671. BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
151672. BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
151673. BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK
151674. BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
151675. BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK
151676. BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
151677. BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
151678. BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
151679. BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
151680. BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
151681. BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
151682. BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
151683. BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
151684. BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
151685. BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__CAP_ID_MASK
151686. BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT
151687. BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK
151688. BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
151689. BIF_CFG_DEV0_EPF4_1_PCIE_CAP__DEVICE_TYPE_MASK
151690. BIF_CFG_DEV0_EPF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT
151691. BIF_CFG_DEV0_EPF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
151692. BIF_CFG_DEV0_EPF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
151693. BIF_CFG_DEV0_EPF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
151694. BIF_CFG_DEV0_EPF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
151695. BIF_CFG_DEV0_EPF4_1_PCIE_CAP__VERSION_MASK
151696. BIF_CFG_DEV0_EPF4_1_PCIE_CAP__VERSION__SHIFT
151697. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
151698. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
151699. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
151700. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
151701. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
151702. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
151703. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
151704. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
151705. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
151706. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
151707. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
151708. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
151709. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
151710. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
151711. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
151712. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
151713. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
151714. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
151715. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
151716. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
151717. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
151718. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
151719. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
151720. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
151721. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
151722. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
151723. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
151724. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
151725. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
151726. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
151727. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
151728. BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
151729. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
151730. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
151731. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
151732. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
151733. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
151734. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
151735. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
151736. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
151737. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
151738. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
151739. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
151740. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
151741. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
151742. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
151743. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
151744. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
151745. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
151746. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
151747. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
151748. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
151749. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
151750. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
151751. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
151752. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
151753. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
151754. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
151755. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
151756. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
151757. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
151758. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
151759. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
151760. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
151761. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
151762. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
151763. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
151764. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
151765. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
151766. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
151767. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
151768. BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
151769. BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK
151770. BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
151771. BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK
151772. BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
151773. BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK
151774. BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
151775. BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK
151776. BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
151777. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
151778. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
151779. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
151780. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
151781. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
151782. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
151783. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
151784. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
151785. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
151786. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
151787. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
151788. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
151789. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
151790. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
151791. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK
151792. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
151793. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
151794. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
151795. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
151796. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
151797. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
151798. BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
151799. BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
151800. BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
151801. BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
151802. BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
151803. BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
151804. BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
151805. BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
151806. BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
151807. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
151808. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
151809. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
151810. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
151811. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
151812. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
151813. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
151814. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
151815. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
151816. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
151817. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
151818. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
151819. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
151820. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
151821. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
151822. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
151823. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
151824. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
151825. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
151826. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
151827. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
151828. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
151829. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
151830. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
151831. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
151832. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
151833. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
151834. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
151835. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
151836. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
151837. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
151838. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
151839. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
151840. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
151841. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
151842. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
151843. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
151844. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
151845. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
151846. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
151847. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
151848. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
151849. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
151850. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
151851. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
151852. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
151853. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
151854. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
151855. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
151856. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
151857. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
151858. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
151859. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
151860. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
151861. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
151862. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
151863. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
151864. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
151865. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
151866. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
151867. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
151868. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
151869. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
151870. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
151871. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
151872. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
151873. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
151874. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
151875. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
151876. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
151877. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
151878. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
151879. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
151880. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
151881. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
151882. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
151883. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
151884. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
151885. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
151886. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
151887. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
151888. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
151889. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
151890. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
151891. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
151892. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
151893. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
151894. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
151895. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
151896. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
151897. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
151898. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
151899. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
151900. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
151901. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
151902. BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
151903. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
151904. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
151905. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
151906. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
151907. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
151908. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
151909. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
151910. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
151911. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
151912. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
151913. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
151914. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
151915. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
151916. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
151917. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
151918. BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
151919. BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__CAP_ID_MASK
151920. BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__CAP_ID__SHIFT
151921. BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__NEXT_PTR_MASK
151922. BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
151923. BIF_CFG_DEV0_EPF4_1_PMI_CAP__AUX_CURRENT_MASK
151924. BIF_CFG_DEV0_EPF4_1_PMI_CAP__AUX_CURRENT__SHIFT
151925. BIF_CFG_DEV0_EPF4_1_PMI_CAP__D1_SUPPORT_MASK
151926. BIF_CFG_DEV0_EPF4_1_PMI_CAP__D1_SUPPORT__SHIFT
151927. BIF_CFG_DEV0_EPF4_1_PMI_CAP__D2_SUPPORT_MASK
151928. BIF_CFG_DEV0_EPF4_1_PMI_CAP__D2_SUPPORT__SHIFT
151929. BIF_CFG_DEV0_EPF4_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
151930. BIF_CFG_DEV0_EPF4_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
151931. BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_CLOCK_MASK
151932. BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_CLOCK__SHIFT
151933. BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_SUPPORT_MASK
151934. BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_SUPPORT__SHIFT
151935. BIF_CFG_DEV0_EPF4_1_PMI_CAP__VERSION_MASK
151936. BIF_CFG_DEV0_EPF4_1_PMI_CAP__VERSION__SHIFT
151937. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
151938. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
151939. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
151940. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
151941. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
151942. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
151943. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
151944. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
151945. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
151946. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
151947. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_EN_MASK
151948. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_EN__SHIFT
151949. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_STATUS_MASK
151950. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
151951. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PMI_DATA_MASK
151952. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
151953. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__POWER_STATE_MASK
151954. BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
151955. BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK
151956. BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
151957. BIF_CFG_DEV0_EPF4_1_REVISION_ID__MAJOR_REV_ID_MASK
151958. BIF_CFG_DEV0_EPF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT
151959. BIF_CFG_DEV0_EPF4_1_REVISION_ID__MINOR_REV_ID_MASK
151960. BIF_CFG_DEV0_EPF4_1_REVISION_ID__MINOR_REV_ID__SHIFT
151961. BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK
151962. BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
151963. BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__CAP_ID_MASK
151964. BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__CAP_ID__SHIFT
151965. BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__NEXT_PTR_MASK
151966. BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__NEXT_PTR__SHIFT
151967. BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
151968. BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
151969. BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
151970. BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
151971. BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
151972. BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
151973. BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
151974. BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
151975. BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
151976. BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
151977. BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
151978. BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
151979. BIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA__IDP_DATA_MASK
151980. BIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA__IDP_DATA__SHIFT
151981. BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_INDEX_MASK
151982. BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT
151983. BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK
151984. BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
151985. BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK
151986. BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
151987. BIF_CFG_DEV0_EPF4_1_SBRN__SBRN_MASK
151988. BIF_CFG_DEV0_EPF4_1_SBRN__SBRN__SHIFT
151989. BIF_CFG_DEV0_EPF4_1_SLOT_CAP2__RESERVED_MASK
151990. BIF_CFG_DEV0_EPF4_1_SLOT_CAP2__RESERVED__SHIFT
151991. BIF_CFG_DEV0_EPF4_1_SLOT_CNTL2__RESERVED_MASK
151992. BIF_CFG_DEV0_EPF4_1_SLOT_CNTL2__RESERVED__SHIFT
151993. BIF_CFG_DEV0_EPF4_1_SLOT_STATUS2__RESERVED_MASK
151994. BIF_CFG_DEV0_EPF4_1_SLOT_STATUS2__RESERVED__SHIFT
151995. BIF_CFG_DEV0_EPF4_1_STATUS__CAP_LIST_MASK
151996. BIF_CFG_DEV0_EPF4_1_STATUS__CAP_LIST__SHIFT
151997. BIF_CFG_DEV0_EPF4_1_STATUS__DEVSEL_TIMING_MASK
151998. BIF_CFG_DEV0_EPF4_1_STATUS__DEVSEL_TIMING__SHIFT
151999. BIF_CFG_DEV0_EPF4_1_STATUS__FAST_BACK_CAPABLE_MASK
152000. BIF_CFG_DEV0_EPF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT
152001. BIF_CFG_DEV0_EPF4_1_STATUS__INT_STATUS_MASK
152002. BIF_CFG_DEV0_EPF4_1_STATUS__INT_STATUS__SHIFT
152003. BIF_CFG_DEV0_EPF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
152004. BIF_CFG_DEV0_EPF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
152005. BIF_CFG_DEV0_EPF4_1_STATUS__PARITY_ERROR_DETECTED_MASK
152006. BIF_CFG_DEV0_EPF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
152007. BIF_CFG_DEV0_EPF4_1_STATUS__PCI_66_EN_MASK
152008. BIF_CFG_DEV0_EPF4_1_STATUS__PCI_66_EN__SHIFT
152009. BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK
152010. BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
152011. BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK
152012. BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
152013. BIF_CFG_DEV0_EPF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
152014. BIF_CFG_DEV0_EPF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
152015. BIF_CFG_DEV0_EPF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK
152016. BIF_CFG_DEV0_EPF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
152017. BIF_CFG_DEV0_EPF4_1_SUB_CLASS__SUB_CLASS_MASK
152018. BIF_CFG_DEV0_EPF4_1_SUB_CLASS__SUB_CLASS__SHIFT
152019. BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__CAP_ID_MASK
152020. BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__CAP_ID__SHIFT
152021. BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__LENGTH_MASK
152022. BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__LENGTH__SHIFT
152023. BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__NEXT_PTR_MASK
152024. BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
152025. BIF_CFG_DEV0_EPF4_1_VENDOR_ID__VENDOR_ID_MASK
152026. BIF_CFG_DEV0_EPF4_1_VENDOR_ID__VENDOR_ID__SHIFT
152027. BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
152028. BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
152029. BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
152030. BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
152031. BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_ID_MASK
152032. BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
152033. BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
152034. BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
152035. BIF_CFG_DEV0_EPF4_2_BASE_ADDR_1__BASE_ADDR_MASK
152036. BIF_CFG_DEV0_EPF4_2_BASE_ADDR_1__BASE_ADDR__SHIFT
152037. BIF_CFG_DEV0_EPF4_2_BASE_ADDR_2__BASE_ADDR_MASK
152038. BIF_CFG_DEV0_EPF4_2_BASE_ADDR_2__BASE_ADDR__SHIFT
152039. BIF_CFG_DEV0_EPF4_2_BASE_ADDR_3__BASE_ADDR_MASK
152040. BIF_CFG_DEV0_EPF4_2_BASE_ADDR_3__BASE_ADDR__SHIFT
152041. BIF_CFG_DEV0_EPF4_2_BASE_ADDR_4__BASE_ADDR_MASK
152042. BIF_CFG_DEV0_EPF4_2_BASE_ADDR_4__BASE_ADDR__SHIFT
152043. BIF_CFG_DEV0_EPF4_2_BASE_ADDR_5__BASE_ADDR_MASK
152044. BIF_CFG_DEV0_EPF4_2_BASE_ADDR_5__BASE_ADDR__SHIFT
152045. BIF_CFG_DEV0_EPF4_2_BASE_ADDR_6__BASE_ADDR_MASK
152046. BIF_CFG_DEV0_EPF4_2_BASE_ADDR_6__BASE_ADDR__SHIFT
152047. BIF_CFG_DEV0_EPF4_2_BASE_CLASS__BASE_CLASS_MASK
152048. BIF_CFG_DEV0_EPF4_2_BASE_CLASS__BASE_CLASS__SHIFT
152049. BIF_CFG_DEV0_EPF4_2_BIST__BIST_CAP_MASK
152050. BIF_CFG_DEV0_EPF4_2_BIST__BIST_CAP__SHIFT
152051. BIF_CFG_DEV0_EPF4_2_BIST__BIST_COMP_MASK
152052. BIF_CFG_DEV0_EPF4_2_BIST__BIST_COMP__SHIFT
152053. BIF_CFG_DEV0_EPF4_2_BIST__BIST_STRT_MASK
152054. BIF_CFG_DEV0_EPF4_2_BIST__BIST_STRT__SHIFT
152055. BIF_CFG_DEV0_EPF4_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
152056. BIF_CFG_DEV0_EPF4_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
152057. BIF_CFG_DEV0_EPF4_2_CAP_PTR__CAP_PTR_MASK
152058. BIF_CFG_DEV0_EPF4_2_CAP_PTR__CAP_PTR__SHIFT
152059. BIF_CFG_DEV0_EPF4_2_COMMAND__AD_STEPPING_MASK
152060. BIF_CFG_DEV0_EPF4_2_COMMAND__AD_STEPPING__SHIFT
152061. BIF_CFG_DEV0_EPF4_2_COMMAND__BUS_MASTER_EN_MASK
152062. BIF_CFG_DEV0_EPF4_2_COMMAND__BUS_MASTER_EN__SHIFT
152063. BIF_CFG_DEV0_EPF4_2_COMMAND__FAST_B2B_EN_MASK
152064. BIF_CFG_DEV0_EPF4_2_COMMAND__FAST_B2B_EN__SHIFT
152065. BIF_CFG_DEV0_EPF4_2_COMMAND__INT_DIS_MASK
152066. BIF_CFG_DEV0_EPF4_2_COMMAND__INT_DIS__SHIFT
152067. BIF_CFG_DEV0_EPF4_2_COMMAND__IO_ACCESS_EN_MASK
152068. BIF_CFG_DEV0_EPF4_2_COMMAND__IO_ACCESS_EN__SHIFT
152069. BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_ACCESS_EN_MASK
152070. BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_ACCESS_EN__SHIFT
152071. BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
152072. BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
152073. BIF_CFG_DEV0_EPF4_2_COMMAND__PAL_SNOOP_EN_MASK
152074. BIF_CFG_DEV0_EPF4_2_COMMAND__PAL_SNOOP_EN__SHIFT
152075. BIF_CFG_DEV0_EPF4_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
152076. BIF_CFG_DEV0_EPF4_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
152077. BIF_CFG_DEV0_EPF4_2_COMMAND__SERR_EN_MASK
152078. BIF_CFG_DEV0_EPF4_2_COMMAND__SERR_EN__SHIFT
152079. BIF_CFG_DEV0_EPF4_2_COMMAND__SPECIAL_CYCLE_EN_MASK
152080. BIF_CFG_DEV0_EPF4_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
152081. BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESLD_MASK
152082. BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESLD__SHIFT
152083. BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESL_MASK
152084. BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESL__SHIFT
152085. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
152086. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
152087. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
152088. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
152089. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
152090. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
152091. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
152092. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
152093. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
152094. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
152095. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
152096. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
152097. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
152098. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
152099. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
152100. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
152101. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
152102. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
152103. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
152104. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
152105. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
152106. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
152107. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
152108. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
152109. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
152110. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
152111. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
152112. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
152113. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
152114. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
152115. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
152116. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
152117. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__EXTENDED_TAG_MASK
152118. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
152119. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__FLR_CAPABLE_MASK
152120. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
152121. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
152122. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
152123. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
152124. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
152125. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
152126. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
152127. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__PHANTOM_FUNC_MASK
152128. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
152129. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
152130. BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
152131. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
152132. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
152133. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
152134. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
152135. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
152136. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
152137. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
152138. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
152139. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
152140. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
152141. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
152142. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
152143. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
152144. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
152145. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
152146. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
152147. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__LTR_EN_MASK
152148. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__LTR_EN__SHIFT
152149. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__OBFF_EN_MASK
152150. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__OBFF_EN__SHIFT
152151. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
152152. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
152153. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__CORR_ERR_EN_MASK
152154. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
152155. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
152156. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
152157. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
152158. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
152159. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__INITIATE_FLR_MASK
152160. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__INITIATE_FLR__SHIFT
152161. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
152162. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
152163. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
152164. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
152165. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
152166. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
152167. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
152168. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
152169. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
152170. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
152171. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
152172. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
152173. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__USR_REPORT_EN_MASK
152174. BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
152175. BIF_CFG_DEV0_EPF4_2_DEVICE_ID__DEVICE_ID_MASK
152176. BIF_CFG_DEV0_EPF4_2_DEVICE_ID__DEVICE_ID__SHIFT
152177. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS2__RESERVED_MASK
152178. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS2__RESERVED__SHIFT
152179. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__AUX_PWR_MASK
152180. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__AUX_PWR__SHIFT
152181. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__CORR_ERR_MASK
152182. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__CORR_ERR__SHIFT
152183. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__FATAL_ERR_MASK
152184. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__FATAL_ERR__SHIFT
152185. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
152186. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
152187. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
152188. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
152189. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__USR_DETECTED_MASK
152190. BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__USR_DETECTED__SHIFT
152191. BIF_CFG_DEV0_EPF4_2_FLADJ__FLADJ_MASK
152192. BIF_CFG_DEV0_EPF4_2_FLADJ__FLADJ__SHIFT
152193. BIF_CFG_DEV0_EPF4_2_HEADER__DEVICE_TYPE_MASK
152194. BIF_CFG_DEV0_EPF4_2_HEADER__DEVICE_TYPE__SHIFT
152195. BIF_CFG_DEV0_EPF4_2_HEADER__HEADER_TYPE_MASK
152196. BIF_CFG_DEV0_EPF4_2_HEADER__HEADER_TYPE__SHIFT
152197. BIF_CFG_DEV0_EPF4_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
152198. BIF_CFG_DEV0_EPF4_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
152199. BIF_CFG_DEV0_EPF4_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
152200. BIF_CFG_DEV0_EPF4_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
152201. BIF_CFG_DEV0_EPF4_2_LATENCY__LATENCY_TIMER_MASK
152202. BIF_CFG_DEV0_EPF4_2_LATENCY__LATENCY_TIMER__SHIFT
152203. BIF_CFG_DEV0_EPF4_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
152204. BIF_CFG_DEV0_EPF4_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
152205. BIF_CFG_DEV0_EPF4_2_LINK_CAP2__RESERVED_MASK
152206. BIF_CFG_DEV0_EPF4_2_LINK_CAP2__RESERVED__SHIFT
152207. BIF_CFG_DEV0_EPF4_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
152208. BIF_CFG_DEV0_EPF4_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
152209. BIF_CFG_DEV0_EPF4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
152210. BIF_CFG_DEV0_EPF4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
152211. BIF_CFG_DEV0_EPF4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
152212. BIF_CFG_DEV0_EPF4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
152213. BIF_CFG_DEV0_EPF4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
152214. BIF_CFG_DEV0_EPF4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
152215. BIF_CFG_DEV0_EPF4_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
152216. BIF_CFG_DEV0_EPF4_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
152217. BIF_CFG_DEV0_EPF4_2_LINK_CAP__L1_EXIT_LATENCY_MASK
152218. BIF_CFG_DEV0_EPF4_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
152219. BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
152220. BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
152221. BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_SPEED_MASK
152222. BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_SPEED__SHIFT
152223. BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_WIDTH_MASK
152224. BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_WIDTH__SHIFT
152225. BIF_CFG_DEV0_EPF4_2_LINK_CAP__PM_SUPPORT_MASK
152226. BIF_CFG_DEV0_EPF4_2_LINK_CAP__PM_SUPPORT__SHIFT
152227. BIF_CFG_DEV0_EPF4_2_LINK_CAP__PORT_NUMBER_MASK
152228. BIF_CFG_DEV0_EPF4_2_LINK_CAP__PORT_NUMBER__SHIFT
152229. BIF_CFG_DEV0_EPF4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
152230. BIF_CFG_DEV0_EPF4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
152231. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
152232. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
152233. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
152234. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
152235. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
152236. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
152237. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
152238. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
152239. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
152240. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
152241. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
152242. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
152243. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
152244. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
152245. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__XMIT_MARGIN_MASK
152246. BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
152247. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
152248. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
152249. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
152250. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
152251. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__EXTENDED_SYNC_MASK
152252. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
152253. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
152254. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
152255. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
152256. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
152257. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
152258. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
152259. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_DIS_MASK
152260. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_DIS__SHIFT
152261. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__PM_CONTROL_MASK
152262. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__PM_CONTROL__SHIFT
152263. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
152264. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
152265. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__RETRAIN_LINK_MASK
152266. BIF_CFG_DEV0_EPF4_2_LINK_CNTL__RETRAIN_LINK__SHIFT
152267. BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
152268. BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
152269. BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
152270. BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
152271. BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
152272. BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
152273. BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
152274. BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
152275. BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
152276. BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
152277. BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
152278. BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
152279. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
152280. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
152281. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__DL_ACTIVE_MASK
152282. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__DL_ACTIVE__SHIFT
152283. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
152284. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
152285. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
152286. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
152287. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_TRAINING_MASK
152288. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_TRAINING__SHIFT
152289. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
152290. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
152291. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
152292. BIF_CFG_DEV0_EPF4_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
152293. BIF_CFG_DEV0_EPF4_2_MAX_LATENCY__MAX_LAT_MASK
152294. BIF_CFG_DEV0_EPF4_2_MAX_LATENCY__MAX_LAT__SHIFT
152295. BIF_CFG_DEV0_EPF4_2_MIN_GRANT__MIN_GNT_MASK
152296. BIF_CFG_DEV0_EPF4_2_MIN_GRANT__MIN_GNT__SHIFT
152297. BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__CAP_ID_MASK
152298. BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__CAP_ID__SHIFT
152299. BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__NEXT_PTR_MASK
152300. BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT
152301. BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_EN_MASK
152302. BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT
152303. BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
152304. BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
152305. BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
152306. BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
152307. BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_BIR_MASK
152308. BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT
152309. BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK
152310. BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
152311. BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK
152312. BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
152313. BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
152314. BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
152315. BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__CAP_ID_MASK
152316. BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__CAP_ID__SHIFT
152317. BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__NEXT_PTR_MASK
152318. BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
152319. BIF_CFG_DEV0_EPF4_2_MSI_MASK_64__MSI_MASK_64_MASK
152320. BIF_CFG_DEV0_EPF4_2_MSI_MASK_64__MSI_MASK_64__SHIFT
152321. BIF_CFG_DEV0_EPF4_2_MSI_MASK__MSI_MASK_MASK
152322. BIF_CFG_DEV0_EPF4_2_MSI_MASK__MSI_MASK__SHIFT
152323. BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
152324. BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
152325. BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
152326. BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
152327. BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_64BIT_MASK
152328. BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
152329. BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_EN_MASK
152330. BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_EN__SHIFT
152331. BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
152332. BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
152333. BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
152334. BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
152335. BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
152336. BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
152337. BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
152338. BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
152339. BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA__MSI_DATA_MASK
152340. BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA__MSI_DATA__SHIFT
152341. BIF_CFG_DEV0_EPF4_2_MSI_PENDING_64__MSI_PENDING_64_MASK
152342. BIF_CFG_DEV0_EPF4_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT
152343. BIF_CFG_DEV0_EPF4_2_MSI_PENDING__MSI_PENDING_MASK
152344. BIF_CFG_DEV0_EPF4_2_MSI_PENDING__MSI_PENDING__SHIFT
152345. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
152346. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
152347. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
152348. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
152349. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
152350. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
152351. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
152352. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
152353. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
152354. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
152355. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
152356. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
152357. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
152358. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
152359. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
152360. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
152361. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
152362. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
152363. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
152364. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
152365. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
152366. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
152367. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
152368. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
152369. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
152370. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
152371. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
152372. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
152373. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
152374. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
152375. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
152376. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
152377. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
152378. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
152379. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
152380. BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
152381. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
152382. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
152383. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
152384. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
152385. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
152386. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
152387. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
152388. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
152389. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
152390. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
152391. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
152392. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
152393. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
152394. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
152395. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
152396. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
152397. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
152398. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
152399. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
152400. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
152401. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
152402. BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
152403. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
152404. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
152405. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
152406. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
152407. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
152408. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
152409. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
152410. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
152411. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
152412. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
152413. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
152414. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
152415. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
152416. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
152417. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
152418. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
152419. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
152420. BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
152421. BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
152422. BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
152423. BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK
152424. BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
152425. BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK
152426. BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
152427. BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
152428. BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
152429. BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
152430. BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
152431. BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK
152432. BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
152433. BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK
152434. BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
152435. BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
152436. BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
152437. BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
152438. BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
152439. BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK
152440. BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
152441. BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK
152442. BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
152443. BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
152444. BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
152445. BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
152446. BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
152447. BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK
152448. BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
152449. BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK
152450. BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
152451. BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
152452. BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
152453. BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
152454. BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
152455. BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK
152456. BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
152457. BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK
152458. BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
152459. BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
152460. BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
152461. BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
152462. BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
152463. BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK
152464. BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
152465. BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK
152466. BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
152467. BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
152468. BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
152469. BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
152470. BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
152471. BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
152472. BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
152473. BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
152474. BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
152475. BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__CAP_ID_MASK
152476. BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__CAP_ID__SHIFT
152477. BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__NEXT_PTR_MASK
152478. BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
152479. BIF_CFG_DEV0_EPF4_2_PCIE_CAP__DEVICE_TYPE_MASK
152480. BIF_CFG_DEV0_EPF4_2_PCIE_CAP__DEVICE_TYPE__SHIFT
152481. BIF_CFG_DEV0_EPF4_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
152482. BIF_CFG_DEV0_EPF4_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
152483. BIF_CFG_DEV0_EPF4_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
152484. BIF_CFG_DEV0_EPF4_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
152485. BIF_CFG_DEV0_EPF4_2_PCIE_CAP__VERSION_MASK
152486. BIF_CFG_DEV0_EPF4_2_PCIE_CAP__VERSION__SHIFT
152487. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
152488. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
152489. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
152490. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
152491. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
152492. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
152493. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
152494. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
152495. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
152496. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
152497. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
152498. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
152499. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
152500. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
152501. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
152502. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
152503. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
152504. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
152505. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
152506. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
152507. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
152508. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
152509. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
152510. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
152511. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
152512. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
152513. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
152514. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
152515. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
152516. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
152517. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
152518. BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
152519. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
152520. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
152521. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
152522. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
152523. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
152524. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
152525. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
152526. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
152527. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
152528. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
152529. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
152530. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
152531. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
152532. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
152533. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
152534. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
152535. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
152536. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
152537. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
152538. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
152539. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
152540. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
152541. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
152542. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
152543. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
152544. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
152545. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
152546. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
152547. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
152548. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
152549. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
152550. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
152551. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
152552. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
152553. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
152554. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
152555. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
152556. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
152557. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
152558. BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
152559. BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG0__TLP_HDR_MASK
152560. BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
152561. BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG1__TLP_HDR_MASK
152562. BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
152563. BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG2__TLP_HDR_MASK
152564. BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
152565. BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG3__TLP_HDR_MASK
152566. BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
152567. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
152568. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
152569. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
152570. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
152571. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
152572. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
152573. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
152574. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
152575. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
152576. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
152577. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
152578. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
152579. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
152580. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
152581. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK
152582. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
152583. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
152584. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
152585. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
152586. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
152587. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
152588. BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
152589. BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
152590. BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
152591. BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
152592. BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
152593. BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
152594. BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
152595. BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
152596. BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
152597. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
152598. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
152599. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
152600. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
152601. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
152602. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
152603. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
152604. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
152605. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
152606. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
152607. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
152608. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
152609. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
152610. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
152611. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
152612. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
152613. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
152614. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
152615. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
152616. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
152617. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
152618. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
152619. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
152620. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
152621. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
152622. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
152623. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
152624. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
152625. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
152626. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
152627. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
152628. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
152629. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
152630. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
152631. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
152632. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
152633. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
152634. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
152635. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
152636. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
152637. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
152638. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
152639. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
152640. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
152641. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
152642. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
152643. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
152644. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
152645. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
152646. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
152647. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
152648. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
152649. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
152650. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
152651. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
152652. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
152653. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
152654. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
152655. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
152656. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
152657. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
152658. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
152659. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
152660. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
152661. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
152662. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
152663. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
152664. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
152665. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
152666. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
152667. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
152668. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
152669. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
152670. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
152671. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
152672. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
152673. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
152674. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
152675. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
152676. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
152677. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
152678. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
152679. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
152680. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
152681. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
152682. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
152683. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
152684. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
152685. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
152686. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
152687. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
152688. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
152689. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
152690. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
152691. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
152692. BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
152693. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
152694. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
152695. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
152696. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
152697. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
152698. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
152699. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
152700. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
152701. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
152702. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
152703. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
152704. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
152705. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
152706. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
152707. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
152708. BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
152709. BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__CAP_ID_MASK
152710. BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__CAP_ID__SHIFT
152711. BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__NEXT_PTR_MASK
152712. BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
152713. BIF_CFG_DEV0_EPF4_2_PMI_CAP__AUX_CURRENT_MASK
152714. BIF_CFG_DEV0_EPF4_2_PMI_CAP__AUX_CURRENT__SHIFT
152715. BIF_CFG_DEV0_EPF4_2_PMI_CAP__D1_SUPPORT_MASK
152716. BIF_CFG_DEV0_EPF4_2_PMI_CAP__D1_SUPPORT__SHIFT
152717. BIF_CFG_DEV0_EPF4_2_PMI_CAP__D2_SUPPORT_MASK
152718. BIF_CFG_DEV0_EPF4_2_PMI_CAP__D2_SUPPORT__SHIFT
152719. BIF_CFG_DEV0_EPF4_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
152720. BIF_CFG_DEV0_EPF4_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
152721. BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_CLOCK_MASK
152722. BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_CLOCK__SHIFT
152723. BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_SUPPORT_MASK
152724. BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_SUPPORT__SHIFT
152725. BIF_CFG_DEV0_EPF4_2_PMI_CAP__VERSION_MASK
152726. BIF_CFG_DEV0_EPF4_2_PMI_CAP__VERSION__SHIFT
152727. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
152728. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
152729. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
152730. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
152731. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
152732. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
152733. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
152734. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
152735. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
152736. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
152737. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_EN_MASK
152738. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_EN__SHIFT
152739. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_STATUS_MASK
152740. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
152741. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PMI_DATA_MASK
152742. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
152743. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__POWER_STATE_MASK
152744. BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
152745. BIF_CFG_DEV0_EPF4_2_PROG_INTERFACE__PROG_INTERFACE_MASK
152746. BIF_CFG_DEV0_EPF4_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
152747. BIF_CFG_DEV0_EPF4_2_REVISION_ID__MAJOR_REV_ID_MASK
152748. BIF_CFG_DEV0_EPF4_2_REVISION_ID__MAJOR_REV_ID__SHIFT
152749. BIF_CFG_DEV0_EPF4_2_REVISION_ID__MINOR_REV_ID_MASK
152750. BIF_CFG_DEV0_EPF4_2_REVISION_ID__MINOR_REV_ID__SHIFT
152751. BIF_CFG_DEV0_EPF4_2_ROM_BASE_ADDR__BASE_ADDR_MASK
152752. BIF_CFG_DEV0_EPF4_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT
152753. BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__CAP_ID_MASK
152754. BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__CAP_ID__SHIFT
152755. BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__NEXT_PTR_MASK
152756. BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__NEXT_PTR__SHIFT
152757. BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
152758. BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
152759. BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
152760. BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
152761. BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
152762. BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
152763. BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
152764. BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
152765. BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
152766. BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
152767. BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
152768. BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
152769. BIF_CFG_DEV0_EPF4_2_SATA_IDP_DATA__IDP_DATA_MASK
152770. BIF_CFG_DEV0_EPF4_2_SATA_IDP_DATA__IDP_DATA__SHIFT
152771. BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_INDEX_MASK
152772. BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT
152773. BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK
152774. BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
152775. BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK
152776. BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
152777. BIF_CFG_DEV0_EPF4_2_SBRN__SBRN_MASK
152778. BIF_CFG_DEV0_EPF4_2_SBRN__SBRN__SHIFT
152779. BIF_CFG_DEV0_EPF4_2_SLOT_CAP2__RESERVED_MASK
152780. BIF_CFG_DEV0_EPF4_2_SLOT_CAP2__RESERVED__SHIFT
152781. BIF_CFG_DEV0_EPF4_2_SLOT_CNTL2__RESERVED_MASK
152782. BIF_CFG_DEV0_EPF4_2_SLOT_CNTL2__RESERVED__SHIFT
152783. BIF_CFG_DEV0_EPF4_2_SLOT_STATUS2__RESERVED_MASK
152784. BIF_CFG_DEV0_EPF4_2_SLOT_STATUS2__RESERVED__SHIFT
152785. BIF_CFG_DEV0_EPF4_2_STATUS__CAP_LIST_MASK
152786. BIF_CFG_DEV0_EPF4_2_STATUS__CAP_LIST__SHIFT
152787. BIF_CFG_DEV0_EPF4_2_STATUS__DEVSEL_TIMING_MASK
152788. BIF_CFG_DEV0_EPF4_2_STATUS__DEVSEL_TIMING__SHIFT
152789. BIF_CFG_DEV0_EPF4_2_STATUS__FAST_BACK_CAPABLE_MASK
152790. BIF_CFG_DEV0_EPF4_2_STATUS__FAST_BACK_CAPABLE__SHIFT
152791. BIF_CFG_DEV0_EPF4_2_STATUS__INT_STATUS_MASK
152792. BIF_CFG_DEV0_EPF4_2_STATUS__INT_STATUS__SHIFT
152793. BIF_CFG_DEV0_EPF4_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
152794. BIF_CFG_DEV0_EPF4_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
152795. BIF_CFG_DEV0_EPF4_2_STATUS__PARITY_ERROR_DETECTED_MASK
152796. BIF_CFG_DEV0_EPF4_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
152797. BIF_CFG_DEV0_EPF4_2_STATUS__PCI_66_EN_MASK
152798. BIF_CFG_DEV0_EPF4_2_STATUS__PCI_66_EN__SHIFT
152799. BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_MASTER_ABORT_MASK
152800. BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
152801. BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_TARGET_ABORT_MASK
152802. BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
152803. BIF_CFG_DEV0_EPF4_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
152804. BIF_CFG_DEV0_EPF4_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
152805. BIF_CFG_DEV0_EPF4_2_STATUS__SIGNAL_TARGET_ABORT_MASK
152806. BIF_CFG_DEV0_EPF4_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
152807. BIF_CFG_DEV0_EPF4_2_SUB_CLASS__SUB_CLASS_MASK
152808. BIF_CFG_DEV0_EPF4_2_SUB_CLASS__SUB_CLASS__SHIFT
152809. BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__CAP_ID_MASK
152810. BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__CAP_ID__SHIFT
152811. BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__LENGTH_MASK
152812. BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__LENGTH__SHIFT
152813. BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__NEXT_PTR_MASK
152814. BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
152815. BIF_CFG_DEV0_EPF4_2_VENDOR_ID__VENDOR_ID_MASK
152816. BIF_CFG_DEV0_EPF4_2_VENDOR_ID__VENDOR_ID__SHIFT
152817. BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
152818. BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
152819. BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
152820. BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
152821. BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
152822. BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
152823. BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
152824. BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
152825. BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR_MASK
152826. BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT
152827. BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR_MASK
152828. BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT
152829. BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR_MASK
152830. BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT
152831. BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR_MASK
152832. BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT
152833. BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR_MASK
152834. BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT
152835. BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR_MASK
152836. BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT
152837. BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS_MASK
152838. BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS__SHIFT
152839. BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP_MASK
152840. BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP__SHIFT
152841. BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP_MASK
152842. BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP__SHIFT
152843. BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT_MASK
152844. BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT__SHIFT
152845. BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
152846. BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
152847. BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR_MASK
152848. BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR__SHIFT
152849. BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING_MASK
152850. BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING__SHIFT
152851. BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN_MASK
152852. BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN__SHIFT
152853. BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN_MASK
152854. BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN__SHIFT
152855. BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS_MASK
152856. BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS__SHIFT
152857. BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN_MASK
152858. BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN__SHIFT
152859. BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN_MASK
152860. BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN__SHIFT
152861. BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
152862. BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
152863. BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN_MASK
152864. BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN__SHIFT
152865. BIF_CFG_DEV0_EPF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
152866. BIF_CFG_DEV0_EPF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
152867. BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN_MASK
152868. BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN__SHIFT
152869. BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK
152870. BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
152871. BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD_MASK
152872. BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD__SHIFT
152873. BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL_MASK
152874. BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL__SHIFT
152875. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
152876. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
152877. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
152878. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
152879. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
152880. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
152881. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
152882. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
152883. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
152884. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
152885. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
152886. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
152887. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
152888. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
152889. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
152890. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
152891. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
152892. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
152893. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
152894. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
152895. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
152896. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
152897. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
152898. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
152899. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
152900. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
152901. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
152902. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
152903. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
152904. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
152905. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
152906. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
152907. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG_MASK
152908. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
152909. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE_MASK
152910. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
152911. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
152912. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
152913. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
152914. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
152915. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
152916. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
152917. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK
152918. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
152919. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
152920. BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
152921. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
152922. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
152923. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
152924. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
152925. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
152926. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
152927. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
152928. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
152929. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
152930. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
152931. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
152932. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
152933. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
152934. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
152935. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
152936. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
152937. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN_MASK
152938. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN__SHIFT
152939. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN_MASK
152940. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT
152941. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
152942. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
152943. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK
152944. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
152945. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
152946. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
152947. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
152948. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
152949. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR_MASK
152950. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
152951. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
152952. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
152953. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
152954. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
152955. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
152956. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
152957. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
152958. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
152959. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
152960. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
152961. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
152962. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
152963. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK
152964. BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
152965. BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID_MASK
152966. BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID__SHIFT
152967. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED_MASK
152968. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED__SHIFT
152969. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR_MASK
152970. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR__SHIFT
152971. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR_MASK
152972. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR__SHIFT
152973. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR_MASK
152974. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT
152975. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
152976. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
152977. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
152978. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
152979. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED_MASK
152980. BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT
152981. BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ_MASK
152982. BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ__SHIFT
152983. BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE_MASK
152984. BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE__SHIFT
152985. BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE_MASK
152986. BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE__SHIFT
152987. BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
152988. BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
152989. BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
152990. BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
152991. BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER_MASK
152992. BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER__SHIFT
152993. BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
152994. BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
152995. BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RESERVED_MASK
152996. BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RESERVED__SHIFT
152997. BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
152998. BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
152999. BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
153000. BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
153001. BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
153002. BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
153003. BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
153004. BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
153005. BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
153006. BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
153007. BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK
153008. BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
153009. BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
153010. BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
153011. BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED_MASK
153012. BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED__SHIFT
153013. BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH_MASK
153014. BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH__SHIFT
153015. BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT_MASK
153016. BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT__SHIFT
153017. BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER_MASK
153018. BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER__SHIFT
153019. BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
153020. BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
153021. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
153022. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
153023. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
153024. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
153025. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
153026. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
153027. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
153028. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
153029. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
153030. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
153031. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
153032. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
153033. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
153034. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
153035. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN_MASK
153036. BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
153037. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
153038. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
153039. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
153040. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
153041. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC_MASK
153042. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
153043. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
153044. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
153045. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
153046. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
153047. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
153048. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
153049. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS_MASK
153050. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS__SHIFT
153051. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL_MASK
153052. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL__SHIFT
153053. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
153054. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
153055. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK_MASK
153056. BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT
153057. BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
153058. BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
153059. BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
153060. BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
153061. BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
153062. BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
153063. BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
153064. BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
153065. BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
153066. BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
153067. BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
153068. BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
153069. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
153070. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
153071. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE_MASK
153072. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE__SHIFT
153073. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
153074. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
153075. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
153076. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
153077. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING_MASK
153078. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING__SHIFT
153079. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
153080. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
153081. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
153082. BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
153083. BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT_MASK
153084. BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT__SHIFT
153085. BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT_MASK
153086. BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT__SHIFT
153087. BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID_MASK
153088. BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT
153089. BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK
153090. BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
153091. BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK
153092. BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
153093. BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
153094. BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
153095. BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
153096. BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
153097. BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK
153098. BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
153099. BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
153100. BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
153101. BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
153102. BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
153103. BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
153104. BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
153105. BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID_MASK
153106. BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID__SHIFT
153107. BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR_MASK
153108. BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
153109. BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64_MASK
153110. BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT
153111. BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK_MASK
153112. BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK__SHIFT
153113. BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
153114. BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
153115. BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
153116. BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
153117. BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK
153118. BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
153119. BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN_MASK
153120. BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT
153121. BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
153122. BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
153123. BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
153124. BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
153125. BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
153126. BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
153127. BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
153128. BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
153129. BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA_MASK
153130. BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT
153131. BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK
153132. BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
153133. BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING_MASK
153134. BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING__SHIFT
153135. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
153136. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
153137. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
153138. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
153139. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
153140. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
153141. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
153142. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
153143. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
153144. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
153145. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
153146. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
153147. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
153148. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
153149. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
153150. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
153151. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
153152. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
153153. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
153154. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
153155. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
153156. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
153157. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
153158. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
153159. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
153160. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
153161. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
153162. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
153163. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
153164. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
153165. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
153166. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
153167. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
153168. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
153169. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
153170. BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
153171. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
153172. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
153173. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
153174. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
153175. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
153176. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
153177. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
153178. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
153179. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
153180. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
153181. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
153182. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
153183. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
153184. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
153185. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
153186. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
153187. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
153188. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
153189. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
153190. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
153191. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
153192. BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
153193. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
153194. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
153195. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
153196. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
153197. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
153198. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
153199. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
153200. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
153201. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
153202. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
153203. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
153204. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
153205. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
153206. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
153207. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
153208. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
153209. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
153210. BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
153211. BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
153212. BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
153213. BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK
153214. BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
153215. BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK
153216. BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
153217. BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
153218. BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
153219. BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
153220. BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
153221. BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK
153222. BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
153223. BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK
153224. BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
153225. BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
153226. BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
153227. BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
153228. BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
153229. BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK
153230. BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
153231. BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK
153232. BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
153233. BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
153234. BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
153235. BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
153236. BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
153237. BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK
153238. BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
153239. BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK
153240. BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
153241. BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
153242. BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
153243. BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
153244. BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
153245. BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK
153246. BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
153247. BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK
153248. BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
153249. BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
153250. BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
153251. BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
153252. BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
153253. BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK
153254. BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
153255. BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK
153256. BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
153257. BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
153258. BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
153259. BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
153260. BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
153261. BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
153262. BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
153263. BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
153264. BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
153265. BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID_MASK
153266. BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT
153267. BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK
153268. BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
153269. BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE_MASK
153270. BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT
153271. BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
153272. BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
153273. BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
153274. BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
153275. BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION_MASK
153276. BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION__SHIFT
153277. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
153278. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
153279. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
153280. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
153281. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
153282. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
153283. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
153284. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
153285. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
153286. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
153287. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
153288. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
153289. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
153290. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
153291. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
153292. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
153293. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
153294. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
153295. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
153296. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
153297. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
153298. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
153299. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
153300. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
153301. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
153302. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
153303. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
153304. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
153305. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
153306. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
153307. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
153308. BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
153309. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
153310. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
153311. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
153312. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
153313. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
153314. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
153315. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
153316. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
153317. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
153318. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
153319. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
153320. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
153321. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
153322. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
153323. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
153324. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
153325. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
153326. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
153327. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
153328. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
153329. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
153330. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
153331. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
153332. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
153333. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
153334. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
153335. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
153336. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
153337. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
153338. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
153339. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
153340. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
153341. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
153342. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
153343. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
153344. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
153345. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
153346. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
153347. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
153348. BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
153349. BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK
153350. BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
153351. BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK
153352. BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
153353. BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK
153354. BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
153355. BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK
153356. BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
153357. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
153358. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
153359. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
153360. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
153361. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
153362. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
153363. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
153364. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
153365. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
153366. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
153367. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
153368. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
153369. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
153370. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
153371. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK
153372. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
153373. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
153374. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
153375. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
153376. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
153377. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
153378. BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
153379. BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
153380. BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
153381. BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
153382. BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
153383. BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
153384. BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
153385. BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
153386. BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
153387. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
153388. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
153389. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
153390. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
153391. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
153392. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
153393. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
153394. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
153395. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
153396. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
153397. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
153398. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
153399. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
153400. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
153401. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
153402. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
153403. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
153404. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
153405. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
153406. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
153407. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
153408. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
153409. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
153410. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
153411. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
153412. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
153413. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
153414. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
153415. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
153416. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
153417. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
153418. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
153419. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
153420. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
153421. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
153422. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
153423. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
153424. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
153425. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
153426. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
153427. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
153428. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
153429. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
153430. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
153431. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
153432. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
153433. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
153434. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
153435. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
153436. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
153437. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
153438. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
153439. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
153440. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
153441. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
153442. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
153443. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
153444. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
153445. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
153446. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
153447. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
153448. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
153449. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
153450. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
153451. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
153452. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
153453. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
153454. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
153455. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
153456. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
153457. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
153458. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
153459. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
153460. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
153461. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
153462. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
153463. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
153464. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
153465. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
153466. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
153467. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
153468. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
153469. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
153470. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
153471. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
153472. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
153473. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
153474. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
153475. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
153476. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
153477. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
153478. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
153479. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
153480. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
153481. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
153482. BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
153483. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
153484. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
153485. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
153486. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
153487. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
153488. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
153489. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
153490. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
153491. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
153492. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
153493. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
153494. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
153495. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
153496. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
153497. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
153498. BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
153499. BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID_MASK
153500. BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID__SHIFT
153501. BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR_MASK
153502. BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
153503. BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT_MASK
153504. BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT__SHIFT
153505. BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT_MASK
153506. BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT__SHIFT
153507. BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT_MASK
153508. BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT__SHIFT
153509. BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
153510. BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
153511. BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK_MASK
153512. BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK__SHIFT
153513. BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT_MASK
153514. BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT__SHIFT
153515. BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION_MASK
153516. BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION__SHIFT
153517. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
153518. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
153519. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
153520. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
153521. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
153522. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
153523. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
153524. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
153525. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
153526. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
153527. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN_MASK
153528. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN__SHIFT
153529. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS_MASK
153530. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
153531. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA_MASK
153532. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
153533. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE_MASK
153534. BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
153535. BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK
153536. BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
153537. BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID_MASK
153538. BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT
153539. BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID_MASK
153540. BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID__SHIFT
153541. BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK
153542. BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
153543. BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__CAP_ID_MASK
153544. BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__CAP_ID__SHIFT
153545. BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__NEXT_PTR_MASK
153546. BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__NEXT_PTR__SHIFT
153547. BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
153548. BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
153549. BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
153550. BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
153551. BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
153552. BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
153553. BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
153554. BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
153555. BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
153556. BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
153557. BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
153558. BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
153559. BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA__IDP_DATA_MASK
153560. BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA__IDP_DATA__SHIFT
153561. BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_INDEX_MASK
153562. BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT
153563. BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK
153564. BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
153565. BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK
153566. BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
153567. BIF_CFG_DEV0_EPF5_0_SBRN__SBRN_MASK
153568. BIF_CFG_DEV0_EPF5_0_SBRN__SBRN__SHIFT
153569. BIF_CFG_DEV0_EPF5_0_SLOT_CAP2__RESERVED_MASK
153570. BIF_CFG_DEV0_EPF5_0_SLOT_CAP2__RESERVED__SHIFT
153571. BIF_CFG_DEV0_EPF5_0_SLOT_CNTL2__RESERVED_MASK
153572. BIF_CFG_DEV0_EPF5_0_SLOT_CNTL2__RESERVED__SHIFT
153573. BIF_CFG_DEV0_EPF5_0_SLOT_STATUS2__RESERVED_MASK
153574. BIF_CFG_DEV0_EPF5_0_SLOT_STATUS2__RESERVED__SHIFT
153575. BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST_MASK
153576. BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST__SHIFT
153577. BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING_MASK
153578. BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING__SHIFT
153579. BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE_MASK
153580. BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT
153581. BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS_MASK
153582. BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS__SHIFT
153583. BIF_CFG_DEV0_EPF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
153584. BIF_CFG_DEV0_EPF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
153585. BIF_CFG_DEV0_EPF5_0_STATUS__PARITY_ERROR_DETECTED_MASK
153586. BIF_CFG_DEV0_EPF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
153587. BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_EN_MASK
153588. BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_EN__SHIFT
153589. BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK
153590. BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
153591. BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK
153592. BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
153593. BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
153594. BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
153595. BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK
153596. BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
153597. BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS_MASK
153598. BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS__SHIFT
153599. BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID_MASK
153600. BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID__SHIFT
153601. BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH_MASK
153602. BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH__SHIFT
153603. BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR_MASK
153604. BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
153605. BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID_MASK
153606. BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID__SHIFT
153607. BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
153608. BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
153609. BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
153610. BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
153611. BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
153612. BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
153613. BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
153614. BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
153615. BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1__BASE_ADDR_MASK
153616. BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT
153617. BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2__BASE_ADDR_MASK
153618. BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT
153619. BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3__BASE_ADDR_MASK
153620. BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT
153621. BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4__BASE_ADDR_MASK
153622. BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT
153623. BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5__BASE_ADDR_MASK
153624. BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT
153625. BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6__BASE_ADDR_MASK
153626. BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT
153627. BIF_CFG_DEV0_EPF5_1_BASE_CLASS__BASE_CLASS_MASK
153628. BIF_CFG_DEV0_EPF5_1_BASE_CLASS__BASE_CLASS__SHIFT
153629. BIF_CFG_DEV0_EPF5_1_BIST__BIST_CAP_MASK
153630. BIF_CFG_DEV0_EPF5_1_BIST__BIST_CAP__SHIFT
153631. BIF_CFG_DEV0_EPF5_1_BIST__BIST_COMP_MASK
153632. BIF_CFG_DEV0_EPF5_1_BIST__BIST_COMP__SHIFT
153633. BIF_CFG_DEV0_EPF5_1_BIST__BIST_STRT_MASK
153634. BIF_CFG_DEV0_EPF5_1_BIST__BIST_STRT__SHIFT
153635. BIF_CFG_DEV0_EPF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
153636. BIF_CFG_DEV0_EPF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
153637. BIF_CFG_DEV0_EPF5_1_CAP_PTR__CAP_PTR_MASK
153638. BIF_CFG_DEV0_EPF5_1_CAP_PTR__CAP_PTR__SHIFT
153639. BIF_CFG_DEV0_EPF5_1_COMMAND__AD_STEPPING_MASK
153640. BIF_CFG_DEV0_EPF5_1_COMMAND__AD_STEPPING__SHIFT
153641. BIF_CFG_DEV0_EPF5_1_COMMAND__BUS_MASTER_EN_MASK
153642. BIF_CFG_DEV0_EPF5_1_COMMAND__BUS_MASTER_EN__SHIFT
153643. BIF_CFG_DEV0_EPF5_1_COMMAND__FAST_B2B_EN_MASK
153644. BIF_CFG_DEV0_EPF5_1_COMMAND__FAST_B2B_EN__SHIFT
153645. BIF_CFG_DEV0_EPF5_1_COMMAND__INT_DIS_MASK
153646. BIF_CFG_DEV0_EPF5_1_COMMAND__INT_DIS__SHIFT
153647. BIF_CFG_DEV0_EPF5_1_COMMAND__IO_ACCESS_EN_MASK
153648. BIF_CFG_DEV0_EPF5_1_COMMAND__IO_ACCESS_EN__SHIFT
153649. BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_ACCESS_EN_MASK
153650. BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_ACCESS_EN__SHIFT
153651. BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
153652. BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
153653. BIF_CFG_DEV0_EPF5_1_COMMAND__PAL_SNOOP_EN_MASK
153654. BIF_CFG_DEV0_EPF5_1_COMMAND__PAL_SNOOP_EN__SHIFT
153655. BIF_CFG_DEV0_EPF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
153656. BIF_CFG_DEV0_EPF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
153657. BIF_CFG_DEV0_EPF5_1_COMMAND__SERR_EN_MASK
153658. BIF_CFG_DEV0_EPF5_1_COMMAND__SERR_EN__SHIFT
153659. BIF_CFG_DEV0_EPF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK
153660. BIF_CFG_DEV0_EPF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
153661. BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESLD_MASK
153662. BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESLD__SHIFT
153663. BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESL_MASK
153664. BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESL__SHIFT
153665. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
153666. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
153667. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
153668. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
153669. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
153670. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
153671. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
153672. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
153673. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
153674. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
153675. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
153676. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
153677. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
153678. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
153679. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
153680. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
153681. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
153682. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
153683. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
153684. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
153685. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
153686. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
153687. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
153688. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
153689. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
153690. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
153691. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
153692. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
153693. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
153694. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
153695. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
153696. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
153697. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__EXTENDED_TAG_MASK
153698. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
153699. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__FLR_CAPABLE_MASK
153700. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
153701. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
153702. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
153703. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
153704. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
153705. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
153706. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
153707. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK
153708. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
153709. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
153710. BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
153711. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
153712. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
153713. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
153714. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
153715. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
153716. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
153717. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
153718. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
153719. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
153720. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
153721. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
153722. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
153723. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
153724. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
153725. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
153726. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
153727. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__LTR_EN_MASK
153728. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__LTR_EN__SHIFT
153729. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__OBFF_EN_MASK
153730. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT
153731. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
153732. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
153733. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK
153734. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
153735. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
153736. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
153737. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
153738. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
153739. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__INITIATE_FLR_MASK
153740. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
153741. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
153742. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
153743. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
153744. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
153745. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
153746. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
153747. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
153748. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
153749. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
153750. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
153751. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
153752. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
153753. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK
153754. BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
153755. BIF_CFG_DEV0_EPF5_1_DEVICE_ID__DEVICE_ID_MASK
153756. BIF_CFG_DEV0_EPF5_1_DEVICE_ID__DEVICE_ID__SHIFT
153757. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2__RESERVED_MASK
153758. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2__RESERVED__SHIFT
153759. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__AUX_PWR_MASK
153760. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__AUX_PWR__SHIFT
153761. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__CORR_ERR_MASK
153762. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__CORR_ERR__SHIFT
153763. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__FATAL_ERR_MASK
153764. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT
153765. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
153766. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
153767. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
153768. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
153769. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__USR_DETECTED_MASK
153770. BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT
153771. BIF_CFG_DEV0_EPF5_1_FLADJ__FLADJ_MASK
153772. BIF_CFG_DEV0_EPF5_1_FLADJ__FLADJ__SHIFT
153773. BIF_CFG_DEV0_EPF5_1_HEADER__DEVICE_TYPE_MASK
153774. BIF_CFG_DEV0_EPF5_1_HEADER__DEVICE_TYPE__SHIFT
153775. BIF_CFG_DEV0_EPF5_1_HEADER__HEADER_TYPE_MASK
153776. BIF_CFG_DEV0_EPF5_1_HEADER__HEADER_TYPE__SHIFT
153777. BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
153778. BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
153779. BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
153780. BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
153781. BIF_CFG_DEV0_EPF5_1_LATENCY__LATENCY_TIMER_MASK
153782. BIF_CFG_DEV0_EPF5_1_LATENCY__LATENCY_TIMER__SHIFT
153783. BIF_CFG_DEV0_EPF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
153784. BIF_CFG_DEV0_EPF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
153785. BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RESERVED_MASK
153786. BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RESERVED__SHIFT
153787. BIF_CFG_DEV0_EPF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
153788. BIF_CFG_DEV0_EPF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
153789. BIF_CFG_DEV0_EPF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
153790. BIF_CFG_DEV0_EPF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
153791. BIF_CFG_DEV0_EPF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
153792. BIF_CFG_DEV0_EPF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
153793. BIF_CFG_DEV0_EPF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
153794. BIF_CFG_DEV0_EPF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
153795. BIF_CFG_DEV0_EPF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
153796. BIF_CFG_DEV0_EPF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
153797. BIF_CFG_DEV0_EPF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK
153798. BIF_CFG_DEV0_EPF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
153799. BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
153800. BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
153801. BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_SPEED_MASK
153802. BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_SPEED__SHIFT
153803. BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_WIDTH_MASK
153804. BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_WIDTH__SHIFT
153805. BIF_CFG_DEV0_EPF5_1_LINK_CAP__PM_SUPPORT_MASK
153806. BIF_CFG_DEV0_EPF5_1_LINK_CAP__PM_SUPPORT__SHIFT
153807. BIF_CFG_DEV0_EPF5_1_LINK_CAP__PORT_NUMBER_MASK
153808. BIF_CFG_DEV0_EPF5_1_LINK_CAP__PORT_NUMBER__SHIFT
153809. BIF_CFG_DEV0_EPF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
153810. BIF_CFG_DEV0_EPF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
153811. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
153812. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
153813. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
153814. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
153815. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
153816. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
153817. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
153818. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
153819. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
153820. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
153821. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
153822. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
153823. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
153824. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
153825. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__XMIT_MARGIN_MASK
153826. BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
153827. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
153828. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
153829. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
153830. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
153831. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__EXTENDED_SYNC_MASK
153832. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
153833. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
153834. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
153835. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
153836. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
153837. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
153838. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
153839. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_DIS_MASK
153840. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_DIS__SHIFT
153841. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__PM_CONTROL_MASK
153842. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__PM_CONTROL__SHIFT
153843. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
153844. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
153845. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__RETRAIN_LINK_MASK
153846. BIF_CFG_DEV0_EPF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT
153847. BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
153848. BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
153849. BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
153850. BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
153851. BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
153852. BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
153853. BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
153854. BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
153855. BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
153856. BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
153857. BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
153858. BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
153859. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
153860. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
153861. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__DL_ACTIVE_MASK
153862. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__DL_ACTIVE__SHIFT
153863. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
153864. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
153865. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
153866. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
153867. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_TRAINING_MASK
153868. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_TRAINING__SHIFT
153869. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
153870. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
153871. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
153872. BIF_CFG_DEV0_EPF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
153873. BIF_CFG_DEV0_EPF5_1_MAX_LATENCY__MAX_LAT_MASK
153874. BIF_CFG_DEV0_EPF5_1_MAX_LATENCY__MAX_LAT__SHIFT
153875. BIF_CFG_DEV0_EPF5_1_MIN_GRANT__MIN_GNT_MASK
153876. BIF_CFG_DEV0_EPF5_1_MIN_GRANT__MIN_GNT__SHIFT
153877. BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__CAP_ID_MASK
153878. BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT
153879. BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK
153880. BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
153881. BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK
153882. BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
153883. BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
153884. BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
153885. BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
153886. BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
153887. BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK
153888. BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
153889. BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
153890. BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
153891. BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
153892. BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
153893. BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
153894. BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
153895. BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__CAP_ID_MASK
153896. BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__CAP_ID__SHIFT
153897. BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__NEXT_PTR_MASK
153898. BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
153899. BIF_CFG_DEV0_EPF5_1_MSI_MASK_64__MSI_MASK_64_MASK
153900. BIF_CFG_DEV0_EPF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT
153901. BIF_CFG_DEV0_EPF5_1_MSI_MASK__MSI_MASK_MASK
153902. BIF_CFG_DEV0_EPF5_1_MSI_MASK__MSI_MASK__SHIFT
153903. BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
153904. BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
153905. BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
153906. BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
153907. BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK
153908. BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
153909. BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EN_MASK
153910. BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT
153911. BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
153912. BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
153913. BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
153914. BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
153915. BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
153916. BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
153917. BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
153918. BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
153919. BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA__MSI_DATA_MASK
153920. BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT
153921. BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK
153922. BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
153923. BIF_CFG_DEV0_EPF5_1_MSI_PENDING__MSI_PENDING_MASK
153924. BIF_CFG_DEV0_EPF5_1_MSI_PENDING__MSI_PENDING__SHIFT
153925. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
153926. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
153927. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
153928. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
153929. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
153930. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
153931. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
153932. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
153933. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
153934. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
153935. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
153936. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
153937. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
153938. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
153939. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
153940. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
153941. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
153942. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
153943. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
153944. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
153945. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
153946. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
153947. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
153948. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
153949. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
153950. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
153951. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
153952. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
153953. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
153954. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
153955. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
153956. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
153957. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
153958. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
153959. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
153960. BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
153961. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
153962. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
153963. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
153964. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
153965. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
153966. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
153967. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
153968. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
153969. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
153970. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
153971. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
153972. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
153973. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
153974. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
153975. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
153976. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
153977. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
153978. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
153979. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
153980. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
153981. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
153982. BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
153983. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
153984. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
153985. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
153986. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
153987. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
153988. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
153989. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
153990. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
153991. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
153992. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
153993. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
153994. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
153995. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
153996. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
153997. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
153998. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
153999. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
154000. BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
154001. BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
154002. BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
154003. BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK
154004. BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
154005. BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK
154006. BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
154007. BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
154008. BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
154009. BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
154010. BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
154011. BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK
154012. BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
154013. BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK
154014. BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
154015. BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
154016. BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
154017. BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
154018. BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
154019. BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK
154020. BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
154021. BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK
154022. BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
154023. BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
154024. BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
154025. BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
154026. BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
154027. BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK
154028. BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
154029. BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK
154030. BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
154031. BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
154032. BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
154033. BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
154034. BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
154035. BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK
154036. BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
154037. BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK
154038. BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
154039. BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
154040. BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
154041. BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
154042. BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
154043. BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK
154044. BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
154045. BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK
154046. BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
154047. BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
154048. BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
154049. BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
154050. BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
154051. BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
154052. BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
154053. BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
154054. BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
154055. BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__CAP_ID_MASK
154056. BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT
154057. BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK
154058. BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
154059. BIF_CFG_DEV0_EPF5_1_PCIE_CAP__DEVICE_TYPE_MASK
154060. BIF_CFG_DEV0_EPF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT
154061. BIF_CFG_DEV0_EPF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
154062. BIF_CFG_DEV0_EPF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
154063. BIF_CFG_DEV0_EPF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
154064. BIF_CFG_DEV0_EPF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
154065. BIF_CFG_DEV0_EPF5_1_PCIE_CAP__VERSION_MASK
154066. BIF_CFG_DEV0_EPF5_1_PCIE_CAP__VERSION__SHIFT
154067. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
154068. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
154069. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
154070. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
154071. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
154072. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
154073. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
154074. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
154075. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
154076. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
154077. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
154078. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
154079. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
154080. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
154081. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
154082. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
154083. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
154084. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
154085. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
154086. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
154087. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
154088. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
154089. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
154090. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
154091. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
154092. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
154093. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
154094. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
154095. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
154096. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
154097. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
154098. BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
154099. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
154100. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
154101. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
154102. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
154103. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
154104. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
154105. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
154106. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
154107. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
154108. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
154109. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
154110. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
154111. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
154112. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
154113. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
154114. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
154115. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
154116. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
154117. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
154118. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
154119. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
154120. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
154121. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
154122. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
154123. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
154124. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
154125. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
154126. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
154127. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
154128. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
154129. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
154130. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
154131. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
154132. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
154133. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
154134. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
154135. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
154136. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
154137. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
154138. BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
154139. BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK
154140. BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
154141. BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK
154142. BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
154143. BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK
154144. BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
154145. BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK
154146. BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
154147. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
154148. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
154149. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
154150. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
154151. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
154152. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
154153. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
154154. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
154155. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
154156. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
154157. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
154158. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
154159. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
154160. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
154161. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK
154162. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
154163. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
154164. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
154165. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
154166. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
154167. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
154168. BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
154169. BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
154170. BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
154171. BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
154172. BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
154173. BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
154174. BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
154175. BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
154176. BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
154177. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
154178. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
154179. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
154180. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
154181. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
154182. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
154183. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
154184. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
154185. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
154186. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
154187. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
154188. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
154189. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
154190. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
154191. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
154192. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
154193. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
154194. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
154195. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
154196. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
154197. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
154198. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
154199. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
154200. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
154201. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
154202. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
154203. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
154204. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
154205. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
154206. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
154207. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
154208. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
154209. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
154210. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
154211. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
154212. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
154213. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
154214. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
154215. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
154216. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
154217. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
154218. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
154219. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
154220. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
154221. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
154222. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
154223. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
154224. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
154225. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
154226. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
154227. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
154228. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
154229. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
154230. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
154231. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
154232. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
154233. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
154234. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
154235. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
154236. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
154237. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
154238. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
154239. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
154240. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
154241. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
154242. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
154243. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
154244. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
154245. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
154246. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
154247. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
154248. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
154249. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
154250. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
154251. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
154252. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
154253. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
154254. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
154255. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
154256. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
154257. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
154258. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
154259. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
154260. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
154261. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
154262. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
154263. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
154264. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
154265. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
154266. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
154267. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
154268. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
154269. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
154270. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
154271. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
154272. BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
154273. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
154274. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
154275. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
154276. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
154277. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
154278. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
154279. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
154280. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
154281. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
154282. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
154283. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
154284. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
154285. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
154286. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
154287. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
154288. BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
154289. BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__CAP_ID_MASK
154290. BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__CAP_ID__SHIFT
154291. BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__NEXT_PTR_MASK
154292. BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
154293. BIF_CFG_DEV0_EPF5_1_PMI_CAP__AUX_CURRENT_MASK
154294. BIF_CFG_DEV0_EPF5_1_PMI_CAP__AUX_CURRENT__SHIFT
154295. BIF_CFG_DEV0_EPF5_1_PMI_CAP__D1_SUPPORT_MASK
154296. BIF_CFG_DEV0_EPF5_1_PMI_CAP__D1_SUPPORT__SHIFT
154297. BIF_CFG_DEV0_EPF5_1_PMI_CAP__D2_SUPPORT_MASK
154298. BIF_CFG_DEV0_EPF5_1_PMI_CAP__D2_SUPPORT__SHIFT
154299. BIF_CFG_DEV0_EPF5_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
154300. BIF_CFG_DEV0_EPF5_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
154301. BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_CLOCK_MASK
154302. BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_CLOCK__SHIFT
154303. BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_SUPPORT_MASK
154304. BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_SUPPORT__SHIFT
154305. BIF_CFG_DEV0_EPF5_1_PMI_CAP__VERSION_MASK
154306. BIF_CFG_DEV0_EPF5_1_PMI_CAP__VERSION__SHIFT
154307. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
154308. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
154309. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
154310. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
154311. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
154312. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
154313. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
154314. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
154315. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
154316. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
154317. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_EN_MASK
154318. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_EN__SHIFT
154319. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_STATUS_MASK
154320. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
154321. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PMI_DATA_MASK
154322. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
154323. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__POWER_STATE_MASK
154324. BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
154325. BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK
154326. BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
154327. BIF_CFG_DEV0_EPF5_1_REVISION_ID__MAJOR_REV_ID_MASK
154328. BIF_CFG_DEV0_EPF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT
154329. BIF_CFG_DEV0_EPF5_1_REVISION_ID__MINOR_REV_ID_MASK
154330. BIF_CFG_DEV0_EPF5_1_REVISION_ID__MINOR_REV_ID__SHIFT
154331. BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK
154332. BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
154333. BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__CAP_ID_MASK
154334. BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__CAP_ID__SHIFT
154335. BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__NEXT_PTR_MASK
154336. BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__NEXT_PTR__SHIFT
154337. BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
154338. BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
154339. BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
154340. BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
154341. BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
154342. BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
154343. BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
154344. BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
154345. BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
154346. BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
154347. BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
154348. BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
154349. BIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA__IDP_DATA_MASK
154350. BIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA__IDP_DATA__SHIFT
154351. BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_INDEX_MASK
154352. BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT
154353. BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK
154354. BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
154355. BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK
154356. BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
154357. BIF_CFG_DEV0_EPF5_1_SBRN__SBRN_MASK
154358. BIF_CFG_DEV0_EPF5_1_SBRN__SBRN__SHIFT
154359. BIF_CFG_DEV0_EPF5_1_SLOT_CAP2__RESERVED_MASK
154360. BIF_CFG_DEV0_EPF5_1_SLOT_CAP2__RESERVED__SHIFT
154361. BIF_CFG_DEV0_EPF5_1_SLOT_CNTL2__RESERVED_MASK
154362. BIF_CFG_DEV0_EPF5_1_SLOT_CNTL2__RESERVED__SHIFT
154363. BIF_CFG_DEV0_EPF5_1_SLOT_STATUS2__RESERVED_MASK
154364. BIF_CFG_DEV0_EPF5_1_SLOT_STATUS2__RESERVED__SHIFT
154365. BIF_CFG_DEV0_EPF5_1_STATUS__CAP_LIST_MASK
154366. BIF_CFG_DEV0_EPF5_1_STATUS__CAP_LIST__SHIFT
154367. BIF_CFG_DEV0_EPF5_1_STATUS__DEVSEL_TIMING_MASK
154368. BIF_CFG_DEV0_EPF5_1_STATUS__DEVSEL_TIMING__SHIFT
154369. BIF_CFG_DEV0_EPF5_1_STATUS__FAST_BACK_CAPABLE_MASK
154370. BIF_CFG_DEV0_EPF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT
154371. BIF_CFG_DEV0_EPF5_1_STATUS__INT_STATUS_MASK
154372. BIF_CFG_DEV0_EPF5_1_STATUS__INT_STATUS__SHIFT
154373. BIF_CFG_DEV0_EPF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
154374. BIF_CFG_DEV0_EPF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
154375. BIF_CFG_DEV0_EPF5_1_STATUS__PARITY_ERROR_DETECTED_MASK
154376. BIF_CFG_DEV0_EPF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
154377. BIF_CFG_DEV0_EPF5_1_STATUS__PCI_66_EN_MASK
154378. BIF_CFG_DEV0_EPF5_1_STATUS__PCI_66_EN__SHIFT
154379. BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK
154380. BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
154381. BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK
154382. BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
154383. BIF_CFG_DEV0_EPF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
154384. BIF_CFG_DEV0_EPF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
154385. BIF_CFG_DEV0_EPF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK
154386. BIF_CFG_DEV0_EPF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
154387. BIF_CFG_DEV0_EPF5_1_SUB_CLASS__SUB_CLASS_MASK
154388. BIF_CFG_DEV0_EPF5_1_SUB_CLASS__SUB_CLASS__SHIFT
154389. BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__CAP_ID_MASK
154390. BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__CAP_ID__SHIFT
154391. BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__LENGTH_MASK
154392. BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__LENGTH__SHIFT
154393. BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__NEXT_PTR_MASK
154394. BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
154395. BIF_CFG_DEV0_EPF5_1_VENDOR_ID__VENDOR_ID_MASK
154396. BIF_CFG_DEV0_EPF5_1_VENDOR_ID__VENDOR_ID__SHIFT
154397. BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
154398. BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
154399. BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
154400. BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
154401. BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_ID_MASK
154402. BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
154403. BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
154404. BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
154405. BIF_CFG_DEV0_EPF5_2_BASE_ADDR_1__BASE_ADDR_MASK
154406. BIF_CFG_DEV0_EPF5_2_BASE_ADDR_1__BASE_ADDR__SHIFT
154407. BIF_CFG_DEV0_EPF5_2_BASE_ADDR_2__BASE_ADDR_MASK
154408. BIF_CFG_DEV0_EPF5_2_BASE_ADDR_2__BASE_ADDR__SHIFT
154409. BIF_CFG_DEV0_EPF5_2_BASE_ADDR_3__BASE_ADDR_MASK
154410. BIF_CFG_DEV0_EPF5_2_BASE_ADDR_3__BASE_ADDR__SHIFT
154411. BIF_CFG_DEV0_EPF5_2_BASE_ADDR_4__BASE_ADDR_MASK
154412. BIF_CFG_DEV0_EPF5_2_BASE_ADDR_4__BASE_ADDR__SHIFT
154413. BIF_CFG_DEV0_EPF5_2_BASE_ADDR_5__BASE_ADDR_MASK
154414. BIF_CFG_DEV0_EPF5_2_BASE_ADDR_5__BASE_ADDR__SHIFT
154415. BIF_CFG_DEV0_EPF5_2_BASE_ADDR_6__BASE_ADDR_MASK
154416. BIF_CFG_DEV0_EPF5_2_BASE_ADDR_6__BASE_ADDR__SHIFT
154417. BIF_CFG_DEV0_EPF5_2_BASE_CLASS__BASE_CLASS_MASK
154418. BIF_CFG_DEV0_EPF5_2_BASE_CLASS__BASE_CLASS__SHIFT
154419. BIF_CFG_DEV0_EPF5_2_BIST__BIST_CAP_MASK
154420. BIF_CFG_DEV0_EPF5_2_BIST__BIST_CAP__SHIFT
154421. BIF_CFG_DEV0_EPF5_2_BIST__BIST_COMP_MASK
154422. BIF_CFG_DEV0_EPF5_2_BIST__BIST_COMP__SHIFT
154423. BIF_CFG_DEV0_EPF5_2_BIST__BIST_STRT_MASK
154424. BIF_CFG_DEV0_EPF5_2_BIST__BIST_STRT__SHIFT
154425. BIF_CFG_DEV0_EPF5_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
154426. BIF_CFG_DEV0_EPF5_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
154427. BIF_CFG_DEV0_EPF5_2_CAP_PTR__CAP_PTR_MASK
154428. BIF_CFG_DEV0_EPF5_2_CAP_PTR__CAP_PTR__SHIFT
154429. BIF_CFG_DEV0_EPF5_2_COMMAND__AD_STEPPING_MASK
154430. BIF_CFG_DEV0_EPF5_2_COMMAND__AD_STEPPING__SHIFT
154431. BIF_CFG_DEV0_EPF5_2_COMMAND__BUS_MASTER_EN_MASK
154432. BIF_CFG_DEV0_EPF5_2_COMMAND__BUS_MASTER_EN__SHIFT
154433. BIF_CFG_DEV0_EPF5_2_COMMAND__FAST_B2B_EN_MASK
154434. BIF_CFG_DEV0_EPF5_2_COMMAND__FAST_B2B_EN__SHIFT
154435. BIF_CFG_DEV0_EPF5_2_COMMAND__INT_DIS_MASK
154436. BIF_CFG_DEV0_EPF5_2_COMMAND__INT_DIS__SHIFT
154437. BIF_CFG_DEV0_EPF5_2_COMMAND__IO_ACCESS_EN_MASK
154438. BIF_CFG_DEV0_EPF5_2_COMMAND__IO_ACCESS_EN__SHIFT
154439. BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_ACCESS_EN_MASK
154440. BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_ACCESS_EN__SHIFT
154441. BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
154442. BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
154443. BIF_CFG_DEV0_EPF5_2_COMMAND__PAL_SNOOP_EN_MASK
154444. BIF_CFG_DEV0_EPF5_2_COMMAND__PAL_SNOOP_EN__SHIFT
154445. BIF_CFG_DEV0_EPF5_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
154446. BIF_CFG_DEV0_EPF5_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
154447. BIF_CFG_DEV0_EPF5_2_COMMAND__SERR_EN_MASK
154448. BIF_CFG_DEV0_EPF5_2_COMMAND__SERR_EN__SHIFT
154449. BIF_CFG_DEV0_EPF5_2_COMMAND__SPECIAL_CYCLE_EN_MASK
154450. BIF_CFG_DEV0_EPF5_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
154451. BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESLD_MASK
154452. BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESLD__SHIFT
154453. BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESL_MASK
154454. BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESL__SHIFT
154455. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
154456. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
154457. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
154458. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
154459. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
154460. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
154461. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
154462. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
154463. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
154464. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
154465. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
154466. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
154467. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
154468. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
154469. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
154470. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
154471. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
154472. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
154473. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
154474. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
154475. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
154476. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
154477. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
154478. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
154479. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
154480. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
154481. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
154482. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
154483. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
154484. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
154485. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
154486. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
154487. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__EXTENDED_TAG_MASK
154488. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
154489. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__FLR_CAPABLE_MASK
154490. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
154491. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
154492. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
154493. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
154494. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
154495. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
154496. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
154497. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__PHANTOM_FUNC_MASK
154498. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
154499. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
154500. BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
154501. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
154502. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
154503. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
154504. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
154505. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
154506. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
154507. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
154508. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
154509. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
154510. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
154511. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
154512. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
154513. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
154514. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
154515. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
154516. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
154517. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__LTR_EN_MASK
154518. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__LTR_EN__SHIFT
154519. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__OBFF_EN_MASK
154520. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__OBFF_EN__SHIFT
154521. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
154522. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
154523. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__CORR_ERR_EN_MASK
154524. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
154525. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
154526. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
154527. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
154528. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
154529. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__INITIATE_FLR_MASK
154530. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__INITIATE_FLR__SHIFT
154531. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
154532. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
154533. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
154534. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
154535. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
154536. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
154537. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
154538. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
154539. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
154540. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
154541. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
154542. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
154543. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__USR_REPORT_EN_MASK
154544. BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
154545. BIF_CFG_DEV0_EPF5_2_DEVICE_ID__DEVICE_ID_MASK
154546. BIF_CFG_DEV0_EPF5_2_DEVICE_ID__DEVICE_ID__SHIFT
154547. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS2__RESERVED_MASK
154548. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS2__RESERVED__SHIFT
154549. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__AUX_PWR_MASK
154550. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__AUX_PWR__SHIFT
154551. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__CORR_ERR_MASK
154552. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__CORR_ERR__SHIFT
154553. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__FATAL_ERR_MASK
154554. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__FATAL_ERR__SHIFT
154555. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
154556. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
154557. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
154558. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
154559. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__USR_DETECTED_MASK
154560. BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__USR_DETECTED__SHIFT
154561. BIF_CFG_DEV0_EPF5_2_FLADJ__FLADJ_MASK
154562. BIF_CFG_DEV0_EPF5_2_FLADJ__FLADJ__SHIFT
154563. BIF_CFG_DEV0_EPF5_2_HEADER__DEVICE_TYPE_MASK
154564. BIF_CFG_DEV0_EPF5_2_HEADER__DEVICE_TYPE__SHIFT
154565. BIF_CFG_DEV0_EPF5_2_HEADER__HEADER_TYPE_MASK
154566. BIF_CFG_DEV0_EPF5_2_HEADER__HEADER_TYPE__SHIFT
154567. BIF_CFG_DEV0_EPF5_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
154568. BIF_CFG_DEV0_EPF5_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
154569. BIF_CFG_DEV0_EPF5_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
154570. BIF_CFG_DEV0_EPF5_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
154571. BIF_CFG_DEV0_EPF5_2_LATENCY__LATENCY_TIMER_MASK
154572. BIF_CFG_DEV0_EPF5_2_LATENCY__LATENCY_TIMER__SHIFT
154573. BIF_CFG_DEV0_EPF5_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
154574. BIF_CFG_DEV0_EPF5_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
154575. BIF_CFG_DEV0_EPF5_2_LINK_CAP2__RESERVED_MASK
154576. BIF_CFG_DEV0_EPF5_2_LINK_CAP2__RESERVED__SHIFT
154577. BIF_CFG_DEV0_EPF5_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
154578. BIF_CFG_DEV0_EPF5_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
154579. BIF_CFG_DEV0_EPF5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
154580. BIF_CFG_DEV0_EPF5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
154581. BIF_CFG_DEV0_EPF5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
154582. BIF_CFG_DEV0_EPF5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
154583. BIF_CFG_DEV0_EPF5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
154584. BIF_CFG_DEV0_EPF5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
154585. BIF_CFG_DEV0_EPF5_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
154586. BIF_CFG_DEV0_EPF5_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
154587. BIF_CFG_DEV0_EPF5_2_LINK_CAP__L1_EXIT_LATENCY_MASK
154588. BIF_CFG_DEV0_EPF5_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
154589. BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
154590. BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
154591. BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_SPEED_MASK
154592. BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_SPEED__SHIFT
154593. BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_WIDTH_MASK
154594. BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_WIDTH__SHIFT
154595. BIF_CFG_DEV0_EPF5_2_LINK_CAP__PM_SUPPORT_MASK
154596. BIF_CFG_DEV0_EPF5_2_LINK_CAP__PM_SUPPORT__SHIFT
154597. BIF_CFG_DEV0_EPF5_2_LINK_CAP__PORT_NUMBER_MASK
154598. BIF_CFG_DEV0_EPF5_2_LINK_CAP__PORT_NUMBER__SHIFT
154599. BIF_CFG_DEV0_EPF5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
154600. BIF_CFG_DEV0_EPF5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
154601. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
154602. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
154603. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
154604. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
154605. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
154606. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
154607. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
154608. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
154609. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
154610. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
154611. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
154612. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
154613. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
154614. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
154615. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__XMIT_MARGIN_MASK
154616. BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
154617. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
154618. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
154619. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
154620. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
154621. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__EXTENDED_SYNC_MASK
154622. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
154623. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
154624. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
154625. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
154626. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
154627. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
154628. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
154629. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_DIS_MASK
154630. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_DIS__SHIFT
154631. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__PM_CONTROL_MASK
154632. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__PM_CONTROL__SHIFT
154633. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
154634. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
154635. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__RETRAIN_LINK_MASK
154636. BIF_CFG_DEV0_EPF5_2_LINK_CNTL__RETRAIN_LINK__SHIFT
154637. BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
154638. BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
154639. BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
154640. BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
154641. BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
154642. BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
154643. BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
154644. BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
154645. BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
154646. BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
154647. BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
154648. BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
154649. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
154650. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
154651. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__DL_ACTIVE_MASK
154652. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__DL_ACTIVE__SHIFT
154653. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
154654. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
154655. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
154656. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
154657. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_TRAINING_MASK
154658. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_TRAINING__SHIFT
154659. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
154660. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
154661. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
154662. BIF_CFG_DEV0_EPF5_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
154663. BIF_CFG_DEV0_EPF5_2_MAX_LATENCY__MAX_LAT_MASK
154664. BIF_CFG_DEV0_EPF5_2_MAX_LATENCY__MAX_LAT__SHIFT
154665. BIF_CFG_DEV0_EPF5_2_MIN_GRANT__MIN_GNT_MASK
154666. BIF_CFG_DEV0_EPF5_2_MIN_GRANT__MIN_GNT__SHIFT
154667. BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__CAP_ID_MASK
154668. BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__CAP_ID__SHIFT
154669. BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__NEXT_PTR_MASK
154670. BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT
154671. BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_EN_MASK
154672. BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT
154673. BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
154674. BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
154675. BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
154676. BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
154677. BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_BIR_MASK
154678. BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT
154679. BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK
154680. BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
154681. BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK
154682. BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
154683. BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
154684. BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
154685. BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__CAP_ID_MASK
154686. BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__CAP_ID__SHIFT
154687. BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__NEXT_PTR_MASK
154688. BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
154689. BIF_CFG_DEV0_EPF5_2_MSI_MASK_64__MSI_MASK_64_MASK
154690. BIF_CFG_DEV0_EPF5_2_MSI_MASK_64__MSI_MASK_64__SHIFT
154691. BIF_CFG_DEV0_EPF5_2_MSI_MASK__MSI_MASK_MASK
154692. BIF_CFG_DEV0_EPF5_2_MSI_MASK__MSI_MASK__SHIFT
154693. BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
154694. BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
154695. BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
154696. BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
154697. BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_64BIT_MASK
154698. BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
154699. BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_EN_MASK
154700. BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_EN__SHIFT
154701. BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
154702. BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
154703. BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
154704. BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
154705. BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
154706. BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
154707. BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
154708. BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
154709. BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA__MSI_DATA_MASK
154710. BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA__MSI_DATA__SHIFT
154711. BIF_CFG_DEV0_EPF5_2_MSI_PENDING_64__MSI_PENDING_64_MASK
154712. BIF_CFG_DEV0_EPF5_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT
154713. BIF_CFG_DEV0_EPF5_2_MSI_PENDING__MSI_PENDING_MASK
154714. BIF_CFG_DEV0_EPF5_2_MSI_PENDING__MSI_PENDING__SHIFT
154715. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
154716. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
154717. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
154718. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
154719. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
154720. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
154721. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
154722. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
154723. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
154724. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
154725. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
154726. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
154727. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
154728. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
154729. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
154730. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
154731. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
154732. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
154733. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
154734. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
154735. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
154736. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
154737. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
154738. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
154739. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
154740. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
154741. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
154742. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
154743. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
154744. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
154745. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
154746. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
154747. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
154748. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
154749. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
154750. BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
154751. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
154752. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
154753. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
154754. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
154755. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
154756. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
154757. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
154758. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
154759. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
154760. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
154761. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
154762. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
154763. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
154764. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
154765. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
154766. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
154767. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
154768. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
154769. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
154770. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
154771. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
154772. BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
154773. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
154774. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
154775. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
154776. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
154777. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
154778. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
154779. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
154780. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
154781. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
154782. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
154783. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
154784. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
154785. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
154786. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
154787. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
154788. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
154789. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
154790. BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
154791. BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
154792. BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
154793. BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK
154794. BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
154795. BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK
154796. BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
154797. BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
154798. BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
154799. BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
154800. BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
154801. BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK
154802. BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
154803. BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK
154804. BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
154805. BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
154806. BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
154807. BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
154808. BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
154809. BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK
154810. BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
154811. BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK
154812. BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
154813. BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
154814. BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
154815. BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
154816. BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
154817. BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK
154818. BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
154819. BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK
154820. BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
154821. BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
154822. BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
154823. BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
154824. BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
154825. BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK
154826. BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
154827. BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK
154828. BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
154829. BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
154830. BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
154831. BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
154832. BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
154833. BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK
154834. BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
154835. BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK
154836. BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
154837. BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
154838. BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
154839. BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
154840. BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
154841. BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
154842. BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
154843. BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
154844. BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
154845. BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__CAP_ID_MASK
154846. BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__CAP_ID__SHIFT
154847. BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__NEXT_PTR_MASK
154848. BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
154849. BIF_CFG_DEV0_EPF5_2_PCIE_CAP__DEVICE_TYPE_MASK
154850. BIF_CFG_DEV0_EPF5_2_PCIE_CAP__DEVICE_TYPE__SHIFT
154851. BIF_CFG_DEV0_EPF5_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
154852. BIF_CFG_DEV0_EPF5_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
154853. BIF_CFG_DEV0_EPF5_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
154854. BIF_CFG_DEV0_EPF5_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
154855. BIF_CFG_DEV0_EPF5_2_PCIE_CAP__VERSION_MASK
154856. BIF_CFG_DEV0_EPF5_2_PCIE_CAP__VERSION__SHIFT
154857. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
154858. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
154859. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
154860. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
154861. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
154862. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
154863. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
154864. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
154865. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
154866. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
154867. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
154868. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
154869. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
154870. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
154871. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
154872. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
154873. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
154874. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
154875. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
154876. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
154877. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
154878. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
154879. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
154880. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
154881. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
154882. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
154883. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
154884. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
154885. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
154886. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
154887. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
154888. BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
154889. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
154890. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
154891. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
154892. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
154893. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
154894. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
154895. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
154896. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
154897. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
154898. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
154899. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
154900. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
154901. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
154902. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
154903. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
154904. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
154905. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
154906. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
154907. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
154908. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
154909. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
154910. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
154911. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
154912. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
154913. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
154914. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
154915. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
154916. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
154917. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
154918. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
154919. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
154920. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
154921. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
154922. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
154923. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
154924. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
154925. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
154926. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
154927. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
154928. BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
154929. BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG0__TLP_HDR_MASK
154930. BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
154931. BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG1__TLP_HDR_MASK
154932. BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
154933. BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG2__TLP_HDR_MASK
154934. BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
154935. BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG3__TLP_HDR_MASK
154936. BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
154937. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
154938. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
154939. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
154940. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
154941. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
154942. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
154943. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
154944. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
154945. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
154946. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
154947. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
154948. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
154949. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
154950. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
154951. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK
154952. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
154953. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
154954. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
154955. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
154956. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
154957. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
154958. BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
154959. BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
154960. BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
154961. BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
154962. BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
154963. BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
154964. BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
154965. BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
154966. BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
154967. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
154968. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
154969. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
154970. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
154971. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
154972. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
154973. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
154974. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
154975. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
154976. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
154977. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
154978. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
154979. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
154980. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
154981. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
154982. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
154983. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
154984. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
154985. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
154986. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
154987. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
154988. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
154989. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
154990. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
154991. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
154992. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
154993. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
154994. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
154995. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
154996. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
154997. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
154998. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
154999. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
155000. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
155001. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
155002. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
155003. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
155004. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
155005. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
155006. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
155007. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
155008. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
155009. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
155010. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
155011. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
155012. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
155013. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
155014. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
155015. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
155016. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
155017. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
155018. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
155019. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
155020. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
155021. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
155022. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
155023. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
155024. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
155025. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
155026. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
155027. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
155028. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
155029. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
155030. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
155031. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
155032. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
155033. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
155034. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
155035. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
155036. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
155037. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
155038. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
155039. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
155040. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
155041. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
155042. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
155043. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
155044. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
155045. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
155046. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
155047. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
155048. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
155049. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
155050. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
155051. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
155052. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
155053. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
155054. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
155055. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
155056. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
155057. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
155058. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
155059. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
155060. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
155061. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
155062. BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
155063. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
155064. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
155065. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
155066. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
155067. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
155068. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
155069. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
155070. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
155071. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
155072. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
155073. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
155074. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
155075. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
155076. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
155077. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
155078. BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
155079. BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__CAP_ID_MASK
155080. BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__CAP_ID__SHIFT
155081. BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__NEXT_PTR_MASK
155082. BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
155083. BIF_CFG_DEV0_EPF5_2_PMI_CAP__AUX_CURRENT_MASK
155084. BIF_CFG_DEV0_EPF5_2_PMI_CAP__AUX_CURRENT__SHIFT
155085. BIF_CFG_DEV0_EPF5_2_PMI_CAP__D1_SUPPORT_MASK
155086. BIF_CFG_DEV0_EPF5_2_PMI_CAP__D1_SUPPORT__SHIFT
155087. BIF_CFG_DEV0_EPF5_2_PMI_CAP__D2_SUPPORT_MASK
155088. BIF_CFG_DEV0_EPF5_2_PMI_CAP__D2_SUPPORT__SHIFT
155089. BIF_CFG_DEV0_EPF5_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
155090. BIF_CFG_DEV0_EPF5_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
155091. BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_CLOCK_MASK
155092. BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_CLOCK__SHIFT
155093. BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_SUPPORT_MASK
155094. BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_SUPPORT__SHIFT
155095. BIF_CFG_DEV0_EPF5_2_PMI_CAP__VERSION_MASK
155096. BIF_CFG_DEV0_EPF5_2_PMI_CAP__VERSION__SHIFT
155097. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
155098. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
155099. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
155100. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
155101. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
155102. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
155103. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
155104. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
155105. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
155106. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
155107. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_EN_MASK
155108. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_EN__SHIFT
155109. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_STATUS_MASK
155110. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
155111. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PMI_DATA_MASK
155112. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
155113. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__POWER_STATE_MASK
155114. BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
155115. BIF_CFG_DEV0_EPF5_2_PROG_INTERFACE__PROG_INTERFACE_MASK
155116. BIF_CFG_DEV0_EPF5_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
155117. BIF_CFG_DEV0_EPF5_2_REVISION_ID__MAJOR_REV_ID_MASK
155118. BIF_CFG_DEV0_EPF5_2_REVISION_ID__MAJOR_REV_ID__SHIFT
155119. BIF_CFG_DEV0_EPF5_2_REVISION_ID__MINOR_REV_ID_MASK
155120. BIF_CFG_DEV0_EPF5_2_REVISION_ID__MINOR_REV_ID__SHIFT
155121. BIF_CFG_DEV0_EPF5_2_ROM_BASE_ADDR__BASE_ADDR_MASK
155122. BIF_CFG_DEV0_EPF5_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT
155123. BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__CAP_ID_MASK
155124. BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__CAP_ID__SHIFT
155125. BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__NEXT_PTR_MASK
155126. BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__NEXT_PTR__SHIFT
155127. BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
155128. BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
155129. BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
155130. BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
155131. BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
155132. BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
155133. BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
155134. BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
155135. BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
155136. BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
155137. BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
155138. BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
155139. BIF_CFG_DEV0_EPF5_2_SATA_IDP_DATA__IDP_DATA_MASK
155140. BIF_CFG_DEV0_EPF5_2_SATA_IDP_DATA__IDP_DATA__SHIFT
155141. BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_INDEX_MASK
155142. BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT
155143. BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK
155144. BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
155145. BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK
155146. BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
155147. BIF_CFG_DEV0_EPF5_2_SBRN__SBRN_MASK
155148. BIF_CFG_DEV0_EPF5_2_SBRN__SBRN__SHIFT
155149. BIF_CFG_DEV0_EPF5_2_SLOT_CAP2__RESERVED_MASK
155150. BIF_CFG_DEV0_EPF5_2_SLOT_CAP2__RESERVED__SHIFT
155151. BIF_CFG_DEV0_EPF5_2_SLOT_CNTL2__RESERVED_MASK
155152. BIF_CFG_DEV0_EPF5_2_SLOT_CNTL2__RESERVED__SHIFT
155153. BIF_CFG_DEV0_EPF5_2_SLOT_STATUS2__RESERVED_MASK
155154. BIF_CFG_DEV0_EPF5_2_SLOT_STATUS2__RESERVED__SHIFT
155155. BIF_CFG_DEV0_EPF5_2_STATUS__CAP_LIST_MASK
155156. BIF_CFG_DEV0_EPF5_2_STATUS__CAP_LIST__SHIFT
155157. BIF_CFG_DEV0_EPF5_2_STATUS__DEVSEL_TIMING_MASK
155158. BIF_CFG_DEV0_EPF5_2_STATUS__DEVSEL_TIMING__SHIFT
155159. BIF_CFG_DEV0_EPF5_2_STATUS__FAST_BACK_CAPABLE_MASK
155160. BIF_CFG_DEV0_EPF5_2_STATUS__FAST_BACK_CAPABLE__SHIFT
155161. BIF_CFG_DEV0_EPF5_2_STATUS__INT_STATUS_MASK
155162. BIF_CFG_DEV0_EPF5_2_STATUS__INT_STATUS__SHIFT
155163. BIF_CFG_DEV0_EPF5_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
155164. BIF_CFG_DEV0_EPF5_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
155165. BIF_CFG_DEV0_EPF5_2_STATUS__PARITY_ERROR_DETECTED_MASK
155166. BIF_CFG_DEV0_EPF5_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
155167. BIF_CFG_DEV0_EPF5_2_STATUS__PCI_66_EN_MASK
155168. BIF_CFG_DEV0_EPF5_2_STATUS__PCI_66_EN__SHIFT
155169. BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_MASTER_ABORT_MASK
155170. BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
155171. BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_TARGET_ABORT_MASK
155172. BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
155173. BIF_CFG_DEV0_EPF5_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
155174. BIF_CFG_DEV0_EPF5_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
155175. BIF_CFG_DEV0_EPF5_2_STATUS__SIGNAL_TARGET_ABORT_MASK
155176. BIF_CFG_DEV0_EPF5_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
155177. BIF_CFG_DEV0_EPF5_2_SUB_CLASS__SUB_CLASS_MASK
155178. BIF_CFG_DEV0_EPF5_2_SUB_CLASS__SUB_CLASS__SHIFT
155179. BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__CAP_ID_MASK
155180. BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__CAP_ID__SHIFT
155181. BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__LENGTH_MASK
155182. BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__LENGTH__SHIFT
155183. BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__NEXT_PTR_MASK
155184. BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
155185. BIF_CFG_DEV0_EPF5_2_VENDOR_ID__VENDOR_ID_MASK
155186. BIF_CFG_DEV0_EPF5_2_VENDOR_ID__VENDOR_ID__SHIFT
155187. BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
155188. BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
155189. BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
155190. BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
155191. BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
155192. BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
155193. BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
155194. BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
155195. BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR_MASK
155196. BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT
155197. BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR_MASK
155198. BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT
155199. BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR_MASK
155200. BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT
155201. BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR_MASK
155202. BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT
155203. BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR_MASK
155204. BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT
155205. BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR_MASK
155206. BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT
155207. BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS_MASK
155208. BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS__SHIFT
155209. BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP_MASK
155210. BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP__SHIFT
155211. BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP_MASK
155212. BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP__SHIFT
155213. BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT_MASK
155214. BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT__SHIFT
155215. BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
155216. BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
155217. BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR_MASK
155218. BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR__SHIFT
155219. BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING_MASK
155220. BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING__SHIFT
155221. BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN_MASK
155222. BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN__SHIFT
155223. BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN_MASK
155224. BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN__SHIFT
155225. BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS_MASK
155226. BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS__SHIFT
155227. BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN_MASK
155228. BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN__SHIFT
155229. BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN_MASK
155230. BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN__SHIFT
155231. BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
155232. BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
155233. BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN_MASK
155234. BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN__SHIFT
155235. BIF_CFG_DEV0_EPF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
155236. BIF_CFG_DEV0_EPF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
155237. BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN_MASK
155238. BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN__SHIFT
155239. BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK
155240. BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
155241. BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD_MASK
155242. BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD__SHIFT
155243. BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL_MASK
155244. BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL__SHIFT
155245. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
155246. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
155247. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
155248. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
155249. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
155250. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
155251. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
155252. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
155253. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
155254. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
155255. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
155256. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
155257. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
155258. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
155259. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
155260. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
155261. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
155262. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
155263. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
155264. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
155265. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
155266. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
155267. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
155268. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
155269. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
155270. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
155271. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
155272. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
155273. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
155274. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
155275. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
155276. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
155277. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG_MASK
155278. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
155279. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE_MASK
155280. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
155281. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
155282. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
155283. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
155284. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
155285. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
155286. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
155287. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK
155288. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
155289. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
155290. BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
155291. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
155292. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
155293. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
155294. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
155295. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
155296. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
155297. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
155298. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
155299. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
155300. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
155301. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
155302. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
155303. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
155304. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
155305. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
155306. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
155307. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN_MASK
155308. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN__SHIFT
155309. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN_MASK
155310. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT
155311. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
155312. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
155313. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK
155314. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
155315. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
155316. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
155317. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
155318. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
155319. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR_MASK
155320. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
155321. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
155322. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
155323. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
155324. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
155325. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
155326. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
155327. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
155328. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
155329. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
155330. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
155331. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
155332. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
155333. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK
155334. BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
155335. BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID_MASK
155336. BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID__SHIFT
155337. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED_MASK
155338. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED__SHIFT
155339. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR_MASK
155340. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR__SHIFT
155341. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR_MASK
155342. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR__SHIFT
155343. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR_MASK
155344. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT
155345. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
155346. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
155347. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
155348. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
155349. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED_MASK
155350. BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT
155351. BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ_MASK
155352. BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ__SHIFT
155353. BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE_MASK
155354. BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE__SHIFT
155355. BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE_MASK
155356. BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE__SHIFT
155357. BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
155358. BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
155359. BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
155360. BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
155361. BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER_MASK
155362. BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER__SHIFT
155363. BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
155364. BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
155365. BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RESERVED_MASK
155366. BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RESERVED__SHIFT
155367. BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
155368. BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
155369. BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
155370. BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
155371. BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
155372. BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
155373. BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
155374. BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
155375. BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
155376. BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
155377. BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK
155378. BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
155379. BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
155380. BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
155381. BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED_MASK
155382. BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED__SHIFT
155383. BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH_MASK
155384. BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH__SHIFT
155385. BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT_MASK
155386. BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT__SHIFT
155387. BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER_MASK
155388. BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER__SHIFT
155389. BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
155390. BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
155391. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
155392. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
155393. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
155394. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
155395. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
155396. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
155397. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
155398. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
155399. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
155400. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
155401. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
155402. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
155403. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
155404. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
155405. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN_MASK
155406. BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
155407. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
155408. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
155409. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
155410. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
155411. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC_MASK
155412. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
155413. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
155414. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
155415. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
155416. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
155417. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
155418. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
155419. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS_MASK
155420. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS__SHIFT
155421. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL_MASK
155422. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL__SHIFT
155423. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
155424. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
155425. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK_MASK
155426. BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT
155427. BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
155428. BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
155429. BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
155430. BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
155431. BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
155432. BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
155433. BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
155434. BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
155435. BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
155436. BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
155437. BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
155438. BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
155439. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
155440. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
155441. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE_MASK
155442. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE__SHIFT
155443. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
155444. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
155445. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
155446. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
155447. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING_MASK
155448. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING__SHIFT
155449. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
155450. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
155451. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
155452. BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
155453. BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT_MASK
155454. BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT__SHIFT
155455. BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT_MASK
155456. BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT__SHIFT
155457. BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID_MASK
155458. BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT
155459. BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK
155460. BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
155461. BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK
155462. BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
155463. BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
155464. BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
155465. BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
155466. BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
155467. BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK
155468. BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
155469. BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
155470. BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
155471. BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
155472. BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
155473. BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
155474. BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
155475. BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID_MASK
155476. BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID__SHIFT
155477. BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR_MASK
155478. BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
155479. BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64_MASK
155480. BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT
155481. BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK_MASK
155482. BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK__SHIFT
155483. BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
155484. BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
155485. BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
155486. BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
155487. BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK
155488. BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
155489. BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN_MASK
155490. BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT
155491. BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
155492. BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
155493. BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
155494. BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
155495. BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
155496. BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
155497. BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
155498. BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
155499. BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA_MASK
155500. BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT
155501. BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK
155502. BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
155503. BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING_MASK
155504. BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING__SHIFT
155505. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
155506. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
155507. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
155508. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
155509. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
155510. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
155511. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
155512. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
155513. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
155514. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
155515. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
155516. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
155517. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
155518. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
155519. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
155520. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
155521. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
155522. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
155523. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
155524. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
155525. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
155526. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
155527. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
155528. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
155529. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
155530. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
155531. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
155532. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
155533. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
155534. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
155535. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
155536. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
155537. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
155538. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
155539. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
155540. BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
155541. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
155542. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
155543. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
155544. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
155545. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
155546. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
155547. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
155548. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
155549. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
155550. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
155551. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
155552. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
155553. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
155554. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
155555. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
155556. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
155557. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
155558. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
155559. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
155560. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
155561. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
155562. BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
155563. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
155564. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
155565. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
155566. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
155567. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
155568. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
155569. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
155570. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
155571. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
155572. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
155573. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
155574. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
155575. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
155576. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
155577. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
155578. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
155579. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
155580. BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
155581. BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
155582. BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
155583. BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK
155584. BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
155585. BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK
155586. BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
155587. BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
155588. BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
155589. BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
155590. BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
155591. BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK
155592. BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
155593. BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK
155594. BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
155595. BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
155596. BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
155597. BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
155598. BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
155599. BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK
155600. BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
155601. BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK
155602. BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
155603. BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
155604. BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
155605. BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
155606. BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
155607. BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK
155608. BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
155609. BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK
155610. BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
155611. BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
155612. BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
155613. BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
155614. BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
155615. BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK
155616. BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
155617. BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK
155618. BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
155619. BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
155620. BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
155621. BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
155622. BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
155623. BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK
155624. BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
155625. BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK
155626. BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
155627. BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
155628. BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
155629. BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
155630. BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
155631. BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
155632. BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
155633. BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
155634. BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
155635. BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID_MASK
155636. BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT
155637. BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK
155638. BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
155639. BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE_MASK
155640. BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT
155641. BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
155642. BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
155643. BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
155644. BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
155645. BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION_MASK
155646. BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION__SHIFT
155647. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
155648. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
155649. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
155650. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
155651. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
155652. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
155653. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
155654. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
155655. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
155656. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
155657. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
155658. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
155659. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
155660. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
155661. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
155662. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
155663. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
155664. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
155665. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
155666. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
155667. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
155668. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
155669. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
155670. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
155671. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
155672. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
155673. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
155674. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
155675. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
155676. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
155677. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
155678. BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
155679. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
155680. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
155681. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
155682. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
155683. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
155684. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
155685. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
155686. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
155687. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
155688. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
155689. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
155690. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
155691. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
155692. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
155693. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
155694. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
155695. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
155696. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
155697. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
155698. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
155699. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
155700. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
155701. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
155702. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
155703. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
155704. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
155705. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
155706. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
155707. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
155708. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
155709. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
155710. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
155711. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
155712. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
155713. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
155714. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
155715. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
155716. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
155717. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
155718. BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
155719. BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK
155720. BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
155721. BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK
155722. BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
155723. BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK
155724. BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
155725. BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK
155726. BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
155727. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
155728. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
155729. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
155730. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
155731. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
155732. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
155733. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
155734. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
155735. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
155736. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
155737. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
155738. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
155739. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
155740. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
155741. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK
155742. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
155743. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
155744. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
155745. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
155746. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
155747. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
155748. BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
155749. BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
155750. BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
155751. BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
155752. BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
155753. BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
155754. BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
155755. BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
155756. BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
155757. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
155758. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
155759. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
155760. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
155761. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
155762. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
155763. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
155764. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
155765. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
155766. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
155767. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
155768. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
155769. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
155770. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
155771. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
155772. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
155773. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
155774. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
155775. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
155776. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
155777. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
155778. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
155779. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
155780. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
155781. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
155782. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
155783. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
155784. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
155785. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
155786. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
155787. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
155788. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
155789. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
155790. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
155791. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
155792. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
155793. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
155794. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
155795. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
155796. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
155797. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
155798. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
155799. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
155800. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
155801. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
155802. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
155803. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
155804. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
155805. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
155806. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
155807. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
155808. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
155809. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
155810. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
155811. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
155812. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
155813. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
155814. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
155815. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
155816. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
155817. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
155818. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
155819. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
155820. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
155821. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
155822. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
155823. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
155824. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
155825. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
155826. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
155827. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
155828. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
155829. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
155830. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
155831. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
155832. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
155833. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
155834. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
155835. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
155836. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
155837. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
155838. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
155839. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
155840. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
155841. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
155842. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
155843. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
155844. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
155845. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
155846. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
155847. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
155848. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
155849. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
155850. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
155851. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
155852. BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
155853. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
155854. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
155855. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
155856. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
155857. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
155858. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
155859. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
155860. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
155861. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
155862. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
155863. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
155864. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
155865. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
155866. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
155867. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
155868. BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
155869. BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID_MASK
155870. BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID__SHIFT
155871. BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR_MASK
155872. BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
155873. BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT_MASK
155874. BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT__SHIFT
155875. BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT_MASK
155876. BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT__SHIFT
155877. BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT_MASK
155878. BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT__SHIFT
155879. BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
155880. BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
155881. BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK_MASK
155882. BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK__SHIFT
155883. BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT_MASK
155884. BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT__SHIFT
155885. BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION_MASK
155886. BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION__SHIFT
155887. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
155888. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
155889. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
155890. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
155891. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
155892. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
155893. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
155894. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
155895. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
155896. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
155897. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN_MASK
155898. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN__SHIFT
155899. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS_MASK
155900. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
155901. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA_MASK
155902. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
155903. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE_MASK
155904. BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
155905. BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK
155906. BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
155907. BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID_MASK
155908. BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT
155909. BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID_MASK
155910. BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID__SHIFT
155911. BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK
155912. BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
155913. BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__CAP_ID_MASK
155914. BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__CAP_ID__SHIFT
155915. BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__NEXT_PTR_MASK
155916. BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__NEXT_PTR__SHIFT
155917. BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
155918. BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
155919. BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
155920. BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
155921. BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
155922. BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
155923. BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
155924. BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
155925. BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
155926. BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
155927. BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
155928. BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
155929. BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA__IDP_DATA_MASK
155930. BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA__IDP_DATA__SHIFT
155931. BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_INDEX_MASK
155932. BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT
155933. BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK
155934. BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
155935. BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK
155936. BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
155937. BIF_CFG_DEV0_EPF6_0_SBRN__SBRN_MASK
155938. BIF_CFG_DEV0_EPF6_0_SBRN__SBRN__SHIFT
155939. BIF_CFG_DEV0_EPF6_0_SLOT_CAP2__RESERVED_MASK
155940. BIF_CFG_DEV0_EPF6_0_SLOT_CAP2__RESERVED__SHIFT
155941. BIF_CFG_DEV0_EPF6_0_SLOT_CNTL2__RESERVED_MASK
155942. BIF_CFG_DEV0_EPF6_0_SLOT_CNTL2__RESERVED__SHIFT
155943. BIF_CFG_DEV0_EPF6_0_SLOT_STATUS2__RESERVED_MASK
155944. BIF_CFG_DEV0_EPF6_0_SLOT_STATUS2__RESERVED__SHIFT
155945. BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST_MASK
155946. BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST__SHIFT
155947. BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING_MASK
155948. BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING__SHIFT
155949. BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE_MASK
155950. BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT
155951. BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS_MASK
155952. BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS__SHIFT
155953. BIF_CFG_DEV0_EPF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
155954. BIF_CFG_DEV0_EPF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
155955. BIF_CFG_DEV0_EPF6_0_STATUS__PARITY_ERROR_DETECTED_MASK
155956. BIF_CFG_DEV0_EPF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
155957. BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_EN_MASK
155958. BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_EN__SHIFT
155959. BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK
155960. BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
155961. BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK
155962. BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
155963. BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
155964. BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
155965. BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK
155966. BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
155967. BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS_MASK
155968. BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS__SHIFT
155969. BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID_MASK
155970. BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID__SHIFT
155971. BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH_MASK
155972. BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH__SHIFT
155973. BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR_MASK
155974. BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
155975. BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID_MASK
155976. BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID__SHIFT
155977. BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
155978. BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
155979. BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
155980. BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
155981. BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
155982. BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
155983. BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
155984. BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
155985. BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1__BASE_ADDR_MASK
155986. BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT
155987. BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2__BASE_ADDR_MASK
155988. BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT
155989. BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3__BASE_ADDR_MASK
155990. BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT
155991. BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4__BASE_ADDR_MASK
155992. BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT
155993. BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5__BASE_ADDR_MASK
155994. BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT
155995. BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6__BASE_ADDR_MASK
155996. BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT
155997. BIF_CFG_DEV0_EPF6_1_BASE_CLASS__BASE_CLASS_MASK
155998. BIF_CFG_DEV0_EPF6_1_BASE_CLASS__BASE_CLASS__SHIFT
155999. BIF_CFG_DEV0_EPF6_1_BIST__BIST_CAP_MASK
156000. BIF_CFG_DEV0_EPF6_1_BIST__BIST_CAP__SHIFT
156001. BIF_CFG_DEV0_EPF6_1_BIST__BIST_COMP_MASK
156002. BIF_CFG_DEV0_EPF6_1_BIST__BIST_COMP__SHIFT
156003. BIF_CFG_DEV0_EPF6_1_BIST__BIST_STRT_MASK
156004. BIF_CFG_DEV0_EPF6_1_BIST__BIST_STRT__SHIFT
156005. BIF_CFG_DEV0_EPF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
156006. BIF_CFG_DEV0_EPF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
156007. BIF_CFG_DEV0_EPF6_1_CAP_PTR__CAP_PTR_MASK
156008. BIF_CFG_DEV0_EPF6_1_CAP_PTR__CAP_PTR__SHIFT
156009. BIF_CFG_DEV0_EPF6_1_COMMAND__AD_STEPPING_MASK
156010. BIF_CFG_DEV0_EPF6_1_COMMAND__AD_STEPPING__SHIFT
156011. BIF_CFG_DEV0_EPF6_1_COMMAND__BUS_MASTER_EN_MASK
156012. BIF_CFG_DEV0_EPF6_1_COMMAND__BUS_MASTER_EN__SHIFT
156013. BIF_CFG_DEV0_EPF6_1_COMMAND__FAST_B2B_EN_MASK
156014. BIF_CFG_DEV0_EPF6_1_COMMAND__FAST_B2B_EN__SHIFT
156015. BIF_CFG_DEV0_EPF6_1_COMMAND__INT_DIS_MASK
156016. BIF_CFG_DEV0_EPF6_1_COMMAND__INT_DIS__SHIFT
156017. BIF_CFG_DEV0_EPF6_1_COMMAND__IO_ACCESS_EN_MASK
156018. BIF_CFG_DEV0_EPF6_1_COMMAND__IO_ACCESS_EN__SHIFT
156019. BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_ACCESS_EN_MASK
156020. BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_ACCESS_EN__SHIFT
156021. BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
156022. BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
156023. BIF_CFG_DEV0_EPF6_1_COMMAND__PAL_SNOOP_EN_MASK
156024. BIF_CFG_DEV0_EPF6_1_COMMAND__PAL_SNOOP_EN__SHIFT
156025. BIF_CFG_DEV0_EPF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
156026. BIF_CFG_DEV0_EPF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
156027. BIF_CFG_DEV0_EPF6_1_COMMAND__SERR_EN_MASK
156028. BIF_CFG_DEV0_EPF6_1_COMMAND__SERR_EN__SHIFT
156029. BIF_CFG_DEV0_EPF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK
156030. BIF_CFG_DEV0_EPF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
156031. BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESLD_MASK
156032. BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESLD__SHIFT
156033. BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESL_MASK
156034. BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESL__SHIFT
156035. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
156036. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
156037. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
156038. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
156039. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
156040. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
156041. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
156042. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
156043. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
156044. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
156045. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
156046. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
156047. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
156048. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
156049. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
156050. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
156051. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
156052. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
156053. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
156054. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
156055. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
156056. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
156057. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
156058. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
156059. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
156060. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
156061. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
156062. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
156063. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
156064. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
156065. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
156066. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
156067. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__EXTENDED_TAG_MASK
156068. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
156069. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__FLR_CAPABLE_MASK
156070. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
156071. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
156072. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
156073. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
156074. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
156075. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
156076. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
156077. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK
156078. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
156079. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
156080. BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
156081. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
156082. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
156083. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
156084. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
156085. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
156086. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
156087. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
156088. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
156089. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
156090. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
156091. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
156092. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
156093. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
156094. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
156095. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
156096. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
156097. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__LTR_EN_MASK
156098. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__LTR_EN__SHIFT
156099. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__OBFF_EN_MASK
156100. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT
156101. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
156102. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
156103. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK
156104. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
156105. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
156106. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
156107. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
156108. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
156109. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__INITIATE_FLR_MASK
156110. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
156111. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
156112. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
156113. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
156114. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
156115. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
156116. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
156117. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
156118. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
156119. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
156120. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
156121. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
156122. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
156123. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK
156124. BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
156125. BIF_CFG_DEV0_EPF6_1_DEVICE_ID__DEVICE_ID_MASK
156126. BIF_CFG_DEV0_EPF6_1_DEVICE_ID__DEVICE_ID__SHIFT
156127. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2__RESERVED_MASK
156128. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2__RESERVED__SHIFT
156129. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__AUX_PWR_MASK
156130. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__AUX_PWR__SHIFT
156131. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__CORR_ERR_MASK
156132. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__CORR_ERR__SHIFT
156133. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__FATAL_ERR_MASK
156134. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT
156135. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
156136. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
156137. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
156138. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
156139. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__USR_DETECTED_MASK
156140. BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT
156141. BIF_CFG_DEV0_EPF6_1_FLADJ__FLADJ_MASK
156142. BIF_CFG_DEV0_EPF6_1_FLADJ__FLADJ__SHIFT
156143. BIF_CFG_DEV0_EPF6_1_HEADER__DEVICE_TYPE_MASK
156144. BIF_CFG_DEV0_EPF6_1_HEADER__DEVICE_TYPE__SHIFT
156145. BIF_CFG_DEV0_EPF6_1_HEADER__HEADER_TYPE_MASK
156146. BIF_CFG_DEV0_EPF6_1_HEADER__HEADER_TYPE__SHIFT
156147. BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
156148. BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
156149. BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
156150. BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
156151. BIF_CFG_DEV0_EPF6_1_LATENCY__LATENCY_TIMER_MASK
156152. BIF_CFG_DEV0_EPF6_1_LATENCY__LATENCY_TIMER__SHIFT
156153. BIF_CFG_DEV0_EPF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
156154. BIF_CFG_DEV0_EPF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
156155. BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RESERVED_MASK
156156. BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RESERVED__SHIFT
156157. BIF_CFG_DEV0_EPF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
156158. BIF_CFG_DEV0_EPF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
156159. BIF_CFG_DEV0_EPF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
156160. BIF_CFG_DEV0_EPF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
156161. BIF_CFG_DEV0_EPF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
156162. BIF_CFG_DEV0_EPF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
156163. BIF_CFG_DEV0_EPF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
156164. BIF_CFG_DEV0_EPF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
156165. BIF_CFG_DEV0_EPF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
156166. BIF_CFG_DEV0_EPF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
156167. BIF_CFG_DEV0_EPF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK
156168. BIF_CFG_DEV0_EPF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
156169. BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
156170. BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
156171. BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_SPEED_MASK
156172. BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_SPEED__SHIFT
156173. BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_WIDTH_MASK
156174. BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_WIDTH__SHIFT
156175. BIF_CFG_DEV0_EPF6_1_LINK_CAP__PM_SUPPORT_MASK
156176. BIF_CFG_DEV0_EPF6_1_LINK_CAP__PM_SUPPORT__SHIFT
156177. BIF_CFG_DEV0_EPF6_1_LINK_CAP__PORT_NUMBER_MASK
156178. BIF_CFG_DEV0_EPF6_1_LINK_CAP__PORT_NUMBER__SHIFT
156179. BIF_CFG_DEV0_EPF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
156180. BIF_CFG_DEV0_EPF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
156181. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
156182. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
156183. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
156184. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
156185. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
156186. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
156187. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
156188. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
156189. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
156190. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
156191. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
156192. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
156193. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
156194. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
156195. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__XMIT_MARGIN_MASK
156196. BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
156197. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
156198. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
156199. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
156200. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
156201. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__EXTENDED_SYNC_MASK
156202. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
156203. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
156204. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
156205. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
156206. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
156207. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
156208. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
156209. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_DIS_MASK
156210. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_DIS__SHIFT
156211. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__PM_CONTROL_MASK
156212. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__PM_CONTROL__SHIFT
156213. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
156214. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
156215. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__RETRAIN_LINK_MASK
156216. BIF_CFG_DEV0_EPF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT
156217. BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
156218. BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
156219. BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
156220. BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
156221. BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
156222. BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
156223. BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
156224. BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
156225. BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
156226. BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
156227. BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
156228. BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
156229. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
156230. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
156231. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__DL_ACTIVE_MASK
156232. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__DL_ACTIVE__SHIFT
156233. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
156234. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
156235. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
156236. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
156237. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_TRAINING_MASK
156238. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_TRAINING__SHIFT
156239. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
156240. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
156241. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
156242. BIF_CFG_DEV0_EPF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
156243. BIF_CFG_DEV0_EPF6_1_MAX_LATENCY__MAX_LAT_MASK
156244. BIF_CFG_DEV0_EPF6_1_MAX_LATENCY__MAX_LAT__SHIFT
156245. BIF_CFG_DEV0_EPF6_1_MIN_GRANT__MIN_GNT_MASK
156246. BIF_CFG_DEV0_EPF6_1_MIN_GRANT__MIN_GNT__SHIFT
156247. BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__CAP_ID_MASK
156248. BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT
156249. BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK
156250. BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
156251. BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK
156252. BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
156253. BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
156254. BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
156255. BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
156256. BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
156257. BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK
156258. BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
156259. BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
156260. BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
156261. BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
156262. BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
156263. BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
156264. BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
156265. BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__CAP_ID_MASK
156266. BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__CAP_ID__SHIFT
156267. BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__NEXT_PTR_MASK
156268. BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
156269. BIF_CFG_DEV0_EPF6_1_MSI_MASK_64__MSI_MASK_64_MASK
156270. BIF_CFG_DEV0_EPF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT
156271. BIF_CFG_DEV0_EPF6_1_MSI_MASK__MSI_MASK_MASK
156272. BIF_CFG_DEV0_EPF6_1_MSI_MASK__MSI_MASK__SHIFT
156273. BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
156274. BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
156275. BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
156276. BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
156277. BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK
156278. BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
156279. BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EN_MASK
156280. BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT
156281. BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
156282. BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
156283. BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
156284. BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
156285. BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
156286. BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
156287. BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
156288. BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
156289. BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA__MSI_DATA_MASK
156290. BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT
156291. BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK
156292. BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
156293. BIF_CFG_DEV0_EPF6_1_MSI_PENDING__MSI_PENDING_MASK
156294. BIF_CFG_DEV0_EPF6_1_MSI_PENDING__MSI_PENDING__SHIFT
156295. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
156296. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
156297. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
156298. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
156299. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
156300. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
156301. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
156302. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
156303. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
156304. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
156305. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
156306. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
156307. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
156308. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
156309. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
156310. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
156311. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
156312. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
156313. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
156314. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
156315. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
156316. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
156317. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
156318. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
156319. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
156320. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
156321. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
156322. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
156323. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
156324. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
156325. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
156326. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
156327. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
156328. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
156329. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
156330. BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
156331. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
156332. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
156333. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
156334. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
156335. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
156336. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
156337. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
156338. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
156339. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
156340. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
156341. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
156342. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
156343. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
156344. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
156345. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
156346. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
156347. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
156348. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
156349. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
156350. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
156351. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
156352. BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
156353. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
156354. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
156355. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
156356. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
156357. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
156358. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
156359. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
156360. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
156361. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
156362. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
156363. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
156364. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
156365. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
156366. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
156367. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
156368. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
156369. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
156370. BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
156371. BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
156372. BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
156373. BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK
156374. BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
156375. BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK
156376. BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
156377. BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
156378. BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
156379. BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
156380. BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
156381. BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK
156382. BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
156383. BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK
156384. BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
156385. BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
156386. BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
156387. BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
156388. BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
156389. BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK
156390. BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
156391. BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK
156392. BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
156393. BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
156394. BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
156395. BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
156396. BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
156397. BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK
156398. BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
156399. BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK
156400. BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
156401. BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
156402. BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
156403. BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
156404. BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
156405. BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK
156406. BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
156407. BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK
156408. BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
156409. BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
156410. BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
156411. BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
156412. BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
156413. BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK
156414. BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
156415. BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK
156416. BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
156417. BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
156418. BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
156419. BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
156420. BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
156421. BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
156422. BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
156423. BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
156424. BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
156425. BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__CAP_ID_MASK
156426. BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT
156427. BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK
156428. BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
156429. BIF_CFG_DEV0_EPF6_1_PCIE_CAP__DEVICE_TYPE_MASK
156430. BIF_CFG_DEV0_EPF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT
156431. BIF_CFG_DEV0_EPF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
156432. BIF_CFG_DEV0_EPF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
156433. BIF_CFG_DEV0_EPF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
156434. BIF_CFG_DEV0_EPF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
156435. BIF_CFG_DEV0_EPF6_1_PCIE_CAP__VERSION_MASK
156436. BIF_CFG_DEV0_EPF6_1_PCIE_CAP__VERSION__SHIFT
156437. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
156438. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
156439. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
156440. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
156441. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
156442. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
156443. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
156444. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
156445. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
156446. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
156447. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
156448. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
156449. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
156450. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
156451. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
156452. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
156453. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
156454. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
156455. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
156456. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
156457. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
156458. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
156459. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
156460. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
156461. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
156462. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
156463. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
156464. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
156465. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
156466. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
156467. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
156468. BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
156469. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
156470. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
156471. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
156472. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
156473. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
156474. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
156475. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
156476. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
156477. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
156478. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
156479. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
156480. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
156481. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
156482. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
156483. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
156484. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
156485. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
156486. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
156487. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
156488. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
156489. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
156490. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
156491. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
156492. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
156493. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
156494. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
156495. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
156496. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
156497. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
156498. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
156499. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
156500. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
156501. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
156502. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
156503. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
156504. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
156505. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
156506. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
156507. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
156508. BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
156509. BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK
156510. BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
156511. BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK
156512. BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
156513. BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK
156514. BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
156515. BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK
156516. BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
156517. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
156518. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
156519. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
156520. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
156521. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
156522. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
156523. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
156524. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
156525. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
156526. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
156527. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
156528. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
156529. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
156530. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
156531. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK
156532. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
156533. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
156534. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
156535. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
156536. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
156537. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
156538. BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
156539. BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
156540. BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
156541. BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
156542. BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
156543. BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
156544. BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
156545. BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
156546. BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
156547. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
156548. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
156549. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
156550. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
156551. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
156552. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
156553. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
156554. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
156555. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
156556. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
156557. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
156558. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
156559. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
156560. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
156561. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
156562. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
156563. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
156564. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
156565. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
156566. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
156567. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
156568. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
156569. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
156570. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
156571. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
156572. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
156573. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
156574. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
156575. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
156576. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
156577. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
156578. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
156579. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
156580. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
156581. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
156582. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
156583. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
156584. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
156585. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
156586. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
156587. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
156588. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
156589. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
156590. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
156591. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
156592. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
156593. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
156594. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
156595. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
156596. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
156597. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
156598. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
156599. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
156600. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
156601. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
156602. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
156603. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
156604. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
156605. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
156606. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
156607. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
156608. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
156609. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
156610. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
156611. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
156612. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
156613. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
156614. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
156615. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
156616. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
156617. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
156618. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
156619. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
156620. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
156621. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
156622. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
156623. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
156624. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
156625. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
156626. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
156627. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
156628. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
156629. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
156630. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
156631. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
156632. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
156633. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
156634. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
156635. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
156636. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
156637. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
156638. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
156639. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
156640. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
156641. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
156642. BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
156643. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
156644. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
156645. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
156646. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
156647. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
156648. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
156649. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
156650. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
156651. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
156652. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
156653. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
156654. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
156655. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
156656. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
156657. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
156658. BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
156659. BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__CAP_ID_MASK
156660. BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__CAP_ID__SHIFT
156661. BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__NEXT_PTR_MASK
156662. BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
156663. BIF_CFG_DEV0_EPF6_1_PMI_CAP__AUX_CURRENT_MASK
156664. BIF_CFG_DEV0_EPF6_1_PMI_CAP__AUX_CURRENT__SHIFT
156665. BIF_CFG_DEV0_EPF6_1_PMI_CAP__D1_SUPPORT_MASK
156666. BIF_CFG_DEV0_EPF6_1_PMI_CAP__D1_SUPPORT__SHIFT
156667. BIF_CFG_DEV0_EPF6_1_PMI_CAP__D2_SUPPORT_MASK
156668. BIF_CFG_DEV0_EPF6_1_PMI_CAP__D2_SUPPORT__SHIFT
156669. BIF_CFG_DEV0_EPF6_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
156670. BIF_CFG_DEV0_EPF6_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
156671. BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_CLOCK_MASK
156672. BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_CLOCK__SHIFT
156673. BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_SUPPORT_MASK
156674. BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_SUPPORT__SHIFT
156675. BIF_CFG_DEV0_EPF6_1_PMI_CAP__VERSION_MASK
156676. BIF_CFG_DEV0_EPF6_1_PMI_CAP__VERSION__SHIFT
156677. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
156678. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
156679. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
156680. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
156681. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
156682. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
156683. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
156684. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
156685. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
156686. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
156687. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_EN_MASK
156688. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_EN__SHIFT
156689. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_STATUS_MASK
156690. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
156691. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PMI_DATA_MASK
156692. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
156693. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__POWER_STATE_MASK
156694. BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
156695. BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK
156696. BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
156697. BIF_CFG_DEV0_EPF6_1_REVISION_ID__MAJOR_REV_ID_MASK
156698. BIF_CFG_DEV0_EPF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT
156699. BIF_CFG_DEV0_EPF6_1_REVISION_ID__MINOR_REV_ID_MASK
156700. BIF_CFG_DEV0_EPF6_1_REVISION_ID__MINOR_REV_ID__SHIFT
156701. BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK
156702. BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
156703. BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__CAP_ID_MASK
156704. BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__CAP_ID__SHIFT
156705. BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__NEXT_PTR_MASK
156706. BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__NEXT_PTR__SHIFT
156707. BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
156708. BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
156709. BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
156710. BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
156711. BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
156712. BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
156713. BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
156714. BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
156715. BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
156716. BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
156717. BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
156718. BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
156719. BIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA__IDP_DATA_MASK
156720. BIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA__IDP_DATA__SHIFT
156721. BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_INDEX_MASK
156722. BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT
156723. BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK
156724. BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
156725. BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK
156726. BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
156727. BIF_CFG_DEV0_EPF6_1_SBRN__SBRN_MASK
156728. BIF_CFG_DEV0_EPF6_1_SBRN__SBRN__SHIFT
156729. BIF_CFG_DEV0_EPF6_1_SLOT_CAP2__RESERVED_MASK
156730. BIF_CFG_DEV0_EPF6_1_SLOT_CAP2__RESERVED__SHIFT
156731. BIF_CFG_DEV0_EPF6_1_SLOT_CNTL2__RESERVED_MASK
156732. BIF_CFG_DEV0_EPF6_1_SLOT_CNTL2__RESERVED__SHIFT
156733. BIF_CFG_DEV0_EPF6_1_SLOT_STATUS2__RESERVED_MASK
156734. BIF_CFG_DEV0_EPF6_1_SLOT_STATUS2__RESERVED__SHIFT
156735. BIF_CFG_DEV0_EPF6_1_STATUS__CAP_LIST_MASK
156736. BIF_CFG_DEV0_EPF6_1_STATUS__CAP_LIST__SHIFT
156737. BIF_CFG_DEV0_EPF6_1_STATUS__DEVSEL_TIMING_MASK
156738. BIF_CFG_DEV0_EPF6_1_STATUS__DEVSEL_TIMING__SHIFT
156739. BIF_CFG_DEV0_EPF6_1_STATUS__FAST_BACK_CAPABLE_MASK
156740. BIF_CFG_DEV0_EPF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT
156741. BIF_CFG_DEV0_EPF6_1_STATUS__INT_STATUS_MASK
156742. BIF_CFG_DEV0_EPF6_1_STATUS__INT_STATUS__SHIFT
156743. BIF_CFG_DEV0_EPF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
156744. BIF_CFG_DEV0_EPF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
156745. BIF_CFG_DEV0_EPF6_1_STATUS__PARITY_ERROR_DETECTED_MASK
156746. BIF_CFG_DEV0_EPF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
156747. BIF_CFG_DEV0_EPF6_1_STATUS__PCI_66_EN_MASK
156748. BIF_CFG_DEV0_EPF6_1_STATUS__PCI_66_EN__SHIFT
156749. BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK
156750. BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
156751. BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK
156752. BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
156753. BIF_CFG_DEV0_EPF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
156754. BIF_CFG_DEV0_EPF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
156755. BIF_CFG_DEV0_EPF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK
156756. BIF_CFG_DEV0_EPF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
156757. BIF_CFG_DEV0_EPF6_1_SUB_CLASS__SUB_CLASS_MASK
156758. BIF_CFG_DEV0_EPF6_1_SUB_CLASS__SUB_CLASS__SHIFT
156759. BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__CAP_ID_MASK
156760. BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__CAP_ID__SHIFT
156761. BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__LENGTH_MASK
156762. BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__LENGTH__SHIFT
156763. BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__NEXT_PTR_MASK
156764. BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
156765. BIF_CFG_DEV0_EPF6_1_VENDOR_ID__VENDOR_ID_MASK
156766. BIF_CFG_DEV0_EPF6_1_VENDOR_ID__VENDOR_ID__SHIFT
156767. BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
156768. BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
156769. BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
156770. BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
156771. BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_ID_MASK
156772. BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
156773. BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
156774. BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
156775. BIF_CFG_DEV0_EPF6_2_BASE_ADDR_1__BASE_ADDR_MASK
156776. BIF_CFG_DEV0_EPF6_2_BASE_ADDR_1__BASE_ADDR__SHIFT
156777. BIF_CFG_DEV0_EPF6_2_BASE_ADDR_2__BASE_ADDR_MASK
156778. BIF_CFG_DEV0_EPF6_2_BASE_ADDR_2__BASE_ADDR__SHIFT
156779. BIF_CFG_DEV0_EPF6_2_BASE_ADDR_3__BASE_ADDR_MASK
156780. BIF_CFG_DEV0_EPF6_2_BASE_ADDR_3__BASE_ADDR__SHIFT
156781. BIF_CFG_DEV0_EPF6_2_BASE_ADDR_4__BASE_ADDR_MASK
156782. BIF_CFG_DEV0_EPF6_2_BASE_ADDR_4__BASE_ADDR__SHIFT
156783. BIF_CFG_DEV0_EPF6_2_BASE_ADDR_5__BASE_ADDR_MASK
156784. BIF_CFG_DEV0_EPF6_2_BASE_ADDR_5__BASE_ADDR__SHIFT
156785. BIF_CFG_DEV0_EPF6_2_BASE_ADDR_6__BASE_ADDR_MASK
156786. BIF_CFG_DEV0_EPF6_2_BASE_ADDR_6__BASE_ADDR__SHIFT
156787. BIF_CFG_DEV0_EPF6_2_BASE_CLASS__BASE_CLASS_MASK
156788. BIF_CFG_DEV0_EPF6_2_BASE_CLASS__BASE_CLASS__SHIFT
156789. BIF_CFG_DEV0_EPF6_2_BIST__BIST_CAP_MASK
156790. BIF_CFG_DEV0_EPF6_2_BIST__BIST_CAP__SHIFT
156791. BIF_CFG_DEV0_EPF6_2_BIST__BIST_COMP_MASK
156792. BIF_CFG_DEV0_EPF6_2_BIST__BIST_COMP__SHIFT
156793. BIF_CFG_DEV0_EPF6_2_BIST__BIST_STRT_MASK
156794. BIF_CFG_DEV0_EPF6_2_BIST__BIST_STRT__SHIFT
156795. BIF_CFG_DEV0_EPF6_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
156796. BIF_CFG_DEV0_EPF6_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
156797. BIF_CFG_DEV0_EPF6_2_CAP_PTR__CAP_PTR_MASK
156798. BIF_CFG_DEV0_EPF6_2_CAP_PTR__CAP_PTR__SHIFT
156799. BIF_CFG_DEV0_EPF6_2_COMMAND__AD_STEPPING_MASK
156800. BIF_CFG_DEV0_EPF6_2_COMMAND__AD_STEPPING__SHIFT
156801. BIF_CFG_DEV0_EPF6_2_COMMAND__BUS_MASTER_EN_MASK
156802. BIF_CFG_DEV0_EPF6_2_COMMAND__BUS_MASTER_EN__SHIFT
156803. BIF_CFG_DEV0_EPF6_2_COMMAND__FAST_B2B_EN_MASK
156804. BIF_CFG_DEV0_EPF6_2_COMMAND__FAST_B2B_EN__SHIFT
156805. BIF_CFG_DEV0_EPF6_2_COMMAND__INT_DIS_MASK
156806. BIF_CFG_DEV0_EPF6_2_COMMAND__INT_DIS__SHIFT
156807. BIF_CFG_DEV0_EPF6_2_COMMAND__IO_ACCESS_EN_MASK
156808. BIF_CFG_DEV0_EPF6_2_COMMAND__IO_ACCESS_EN__SHIFT
156809. BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_ACCESS_EN_MASK
156810. BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_ACCESS_EN__SHIFT
156811. BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
156812. BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
156813. BIF_CFG_DEV0_EPF6_2_COMMAND__PAL_SNOOP_EN_MASK
156814. BIF_CFG_DEV0_EPF6_2_COMMAND__PAL_SNOOP_EN__SHIFT
156815. BIF_CFG_DEV0_EPF6_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
156816. BIF_CFG_DEV0_EPF6_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
156817. BIF_CFG_DEV0_EPF6_2_COMMAND__SERR_EN_MASK
156818. BIF_CFG_DEV0_EPF6_2_COMMAND__SERR_EN__SHIFT
156819. BIF_CFG_DEV0_EPF6_2_COMMAND__SPECIAL_CYCLE_EN_MASK
156820. BIF_CFG_DEV0_EPF6_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
156821. BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESLD_MASK
156822. BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESLD__SHIFT
156823. BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESL_MASK
156824. BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESL__SHIFT
156825. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
156826. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
156827. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
156828. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
156829. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
156830. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
156831. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
156832. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
156833. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
156834. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
156835. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
156836. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
156837. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
156838. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
156839. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
156840. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
156841. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
156842. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
156843. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
156844. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
156845. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
156846. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
156847. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
156848. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
156849. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
156850. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
156851. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
156852. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
156853. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
156854. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
156855. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
156856. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
156857. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__EXTENDED_TAG_MASK
156858. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
156859. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__FLR_CAPABLE_MASK
156860. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
156861. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
156862. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
156863. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
156864. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
156865. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
156866. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
156867. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__PHANTOM_FUNC_MASK
156868. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
156869. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
156870. BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
156871. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
156872. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
156873. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
156874. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
156875. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
156876. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
156877. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
156878. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
156879. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
156880. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
156881. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
156882. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
156883. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
156884. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
156885. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
156886. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
156887. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__LTR_EN_MASK
156888. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__LTR_EN__SHIFT
156889. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__OBFF_EN_MASK
156890. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__OBFF_EN__SHIFT
156891. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
156892. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
156893. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__CORR_ERR_EN_MASK
156894. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
156895. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
156896. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
156897. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
156898. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
156899. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__INITIATE_FLR_MASK
156900. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__INITIATE_FLR__SHIFT
156901. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
156902. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
156903. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
156904. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
156905. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
156906. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
156907. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
156908. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
156909. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
156910. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
156911. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
156912. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
156913. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__USR_REPORT_EN_MASK
156914. BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
156915. BIF_CFG_DEV0_EPF6_2_DEVICE_ID__DEVICE_ID_MASK
156916. BIF_CFG_DEV0_EPF6_2_DEVICE_ID__DEVICE_ID__SHIFT
156917. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS2__RESERVED_MASK
156918. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS2__RESERVED__SHIFT
156919. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__AUX_PWR_MASK
156920. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__AUX_PWR__SHIFT
156921. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__CORR_ERR_MASK
156922. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__CORR_ERR__SHIFT
156923. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__FATAL_ERR_MASK
156924. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__FATAL_ERR__SHIFT
156925. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
156926. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
156927. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
156928. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
156929. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__USR_DETECTED_MASK
156930. BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__USR_DETECTED__SHIFT
156931. BIF_CFG_DEV0_EPF6_2_FLADJ__FLADJ_MASK
156932. BIF_CFG_DEV0_EPF6_2_FLADJ__FLADJ__SHIFT
156933. BIF_CFG_DEV0_EPF6_2_HEADER__DEVICE_TYPE_MASK
156934. BIF_CFG_DEV0_EPF6_2_HEADER__DEVICE_TYPE__SHIFT
156935. BIF_CFG_DEV0_EPF6_2_HEADER__HEADER_TYPE_MASK
156936. BIF_CFG_DEV0_EPF6_2_HEADER__HEADER_TYPE__SHIFT
156937. BIF_CFG_DEV0_EPF6_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
156938. BIF_CFG_DEV0_EPF6_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
156939. BIF_CFG_DEV0_EPF6_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
156940. BIF_CFG_DEV0_EPF6_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
156941. BIF_CFG_DEV0_EPF6_2_LATENCY__LATENCY_TIMER_MASK
156942. BIF_CFG_DEV0_EPF6_2_LATENCY__LATENCY_TIMER__SHIFT
156943. BIF_CFG_DEV0_EPF6_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
156944. BIF_CFG_DEV0_EPF6_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
156945. BIF_CFG_DEV0_EPF6_2_LINK_CAP2__RESERVED_MASK
156946. BIF_CFG_DEV0_EPF6_2_LINK_CAP2__RESERVED__SHIFT
156947. BIF_CFG_DEV0_EPF6_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
156948. BIF_CFG_DEV0_EPF6_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
156949. BIF_CFG_DEV0_EPF6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
156950. BIF_CFG_DEV0_EPF6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
156951. BIF_CFG_DEV0_EPF6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
156952. BIF_CFG_DEV0_EPF6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
156953. BIF_CFG_DEV0_EPF6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
156954. BIF_CFG_DEV0_EPF6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
156955. BIF_CFG_DEV0_EPF6_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
156956. BIF_CFG_DEV0_EPF6_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
156957. BIF_CFG_DEV0_EPF6_2_LINK_CAP__L1_EXIT_LATENCY_MASK
156958. BIF_CFG_DEV0_EPF6_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
156959. BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
156960. BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
156961. BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_SPEED_MASK
156962. BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_SPEED__SHIFT
156963. BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_WIDTH_MASK
156964. BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_WIDTH__SHIFT
156965. BIF_CFG_DEV0_EPF6_2_LINK_CAP__PM_SUPPORT_MASK
156966. BIF_CFG_DEV0_EPF6_2_LINK_CAP__PM_SUPPORT__SHIFT
156967. BIF_CFG_DEV0_EPF6_2_LINK_CAP__PORT_NUMBER_MASK
156968. BIF_CFG_DEV0_EPF6_2_LINK_CAP__PORT_NUMBER__SHIFT
156969. BIF_CFG_DEV0_EPF6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
156970. BIF_CFG_DEV0_EPF6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
156971. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
156972. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
156973. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
156974. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
156975. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
156976. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
156977. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
156978. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
156979. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
156980. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
156981. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
156982. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
156983. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
156984. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
156985. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__XMIT_MARGIN_MASK
156986. BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
156987. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
156988. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
156989. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
156990. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
156991. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__EXTENDED_SYNC_MASK
156992. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
156993. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
156994. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
156995. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
156996. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
156997. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
156998. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
156999. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_DIS_MASK
157000. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_DIS__SHIFT
157001. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__PM_CONTROL_MASK
157002. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__PM_CONTROL__SHIFT
157003. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
157004. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
157005. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__RETRAIN_LINK_MASK
157006. BIF_CFG_DEV0_EPF6_2_LINK_CNTL__RETRAIN_LINK__SHIFT
157007. BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
157008. BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
157009. BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
157010. BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
157011. BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
157012. BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
157013. BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
157014. BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
157015. BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
157016. BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
157017. BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
157018. BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
157019. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
157020. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
157021. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__DL_ACTIVE_MASK
157022. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__DL_ACTIVE__SHIFT
157023. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
157024. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
157025. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
157026. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
157027. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_TRAINING_MASK
157028. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_TRAINING__SHIFT
157029. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
157030. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
157031. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
157032. BIF_CFG_DEV0_EPF6_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
157033. BIF_CFG_DEV0_EPF6_2_MAX_LATENCY__MAX_LAT_MASK
157034. BIF_CFG_DEV0_EPF6_2_MAX_LATENCY__MAX_LAT__SHIFT
157035. BIF_CFG_DEV0_EPF6_2_MIN_GRANT__MIN_GNT_MASK
157036. BIF_CFG_DEV0_EPF6_2_MIN_GRANT__MIN_GNT__SHIFT
157037. BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__CAP_ID_MASK
157038. BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__CAP_ID__SHIFT
157039. BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__NEXT_PTR_MASK
157040. BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT
157041. BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_EN_MASK
157042. BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT
157043. BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
157044. BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
157045. BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
157046. BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
157047. BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_BIR_MASK
157048. BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT
157049. BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK
157050. BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
157051. BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK
157052. BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
157053. BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
157054. BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
157055. BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__CAP_ID_MASK
157056. BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__CAP_ID__SHIFT
157057. BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__NEXT_PTR_MASK
157058. BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
157059. BIF_CFG_DEV0_EPF6_2_MSI_MASK_64__MSI_MASK_64_MASK
157060. BIF_CFG_DEV0_EPF6_2_MSI_MASK_64__MSI_MASK_64__SHIFT
157061. BIF_CFG_DEV0_EPF6_2_MSI_MASK__MSI_MASK_MASK
157062. BIF_CFG_DEV0_EPF6_2_MSI_MASK__MSI_MASK__SHIFT
157063. BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
157064. BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
157065. BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
157066. BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
157067. BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_64BIT_MASK
157068. BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
157069. BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_EN_MASK
157070. BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_EN__SHIFT
157071. BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
157072. BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
157073. BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
157074. BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
157075. BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
157076. BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
157077. BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
157078. BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
157079. BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA__MSI_DATA_MASK
157080. BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA__MSI_DATA__SHIFT
157081. BIF_CFG_DEV0_EPF6_2_MSI_PENDING_64__MSI_PENDING_64_MASK
157082. BIF_CFG_DEV0_EPF6_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT
157083. BIF_CFG_DEV0_EPF6_2_MSI_PENDING__MSI_PENDING_MASK
157084. BIF_CFG_DEV0_EPF6_2_MSI_PENDING__MSI_PENDING__SHIFT
157085. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
157086. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
157087. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
157088. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
157089. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
157090. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
157091. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
157092. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
157093. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
157094. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
157095. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
157096. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
157097. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
157098. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
157099. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
157100. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
157101. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
157102. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
157103. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
157104. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
157105. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
157106. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
157107. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
157108. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
157109. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
157110. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
157111. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
157112. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
157113. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
157114. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
157115. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
157116. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
157117. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
157118. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
157119. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
157120. BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
157121. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
157122. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
157123. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
157124. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
157125. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
157126. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
157127. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
157128. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
157129. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
157130. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
157131. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
157132. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
157133. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
157134. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
157135. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
157136. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
157137. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
157138. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
157139. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
157140. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
157141. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
157142. BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
157143. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
157144. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
157145. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
157146. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
157147. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
157148. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
157149. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
157150. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
157151. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
157152. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
157153. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
157154. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
157155. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
157156. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
157157. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
157158. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
157159. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
157160. BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
157161. BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
157162. BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
157163. BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK
157164. BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
157165. BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK
157166. BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
157167. BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
157168. BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
157169. BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
157170. BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
157171. BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK
157172. BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
157173. BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK
157174. BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
157175. BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
157176. BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
157177. BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
157178. BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
157179. BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK
157180. BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
157181. BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK
157182. BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
157183. BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
157184. BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
157185. BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
157186. BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
157187. BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK
157188. BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
157189. BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK
157190. BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
157191. BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
157192. BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
157193. BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
157194. BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
157195. BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK
157196. BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
157197. BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK
157198. BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
157199. BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
157200. BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
157201. BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
157202. BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
157203. BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK
157204. BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
157205. BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK
157206. BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
157207. BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
157208. BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
157209. BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
157210. BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
157211. BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
157212. BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
157213. BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
157214. BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
157215. BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__CAP_ID_MASK
157216. BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__CAP_ID__SHIFT
157217. BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__NEXT_PTR_MASK
157218. BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
157219. BIF_CFG_DEV0_EPF6_2_PCIE_CAP__DEVICE_TYPE_MASK
157220. BIF_CFG_DEV0_EPF6_2_PCIE_CAP__DEVICE_TYPE__SHIFT
157221. BIF_CFG_DEV0_EPF6_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
157222. BIF_CFG_DEV0_EPF6_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
157223. BIF_CFG_DEV0_EPF6_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
157224. BIF_CFG_DEV0_EPF6_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
157225. BIF_CFG_DEV0_EPF6_2_PCIE_CAP__VERSION_MASK
157226. BIF_CFG_DEV0_EPF6_2_PCIE_CAP__VERSION__SHIFT
157227. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
157228. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
157229. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
157230. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
157231. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
157232. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
157233. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
157234. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
157235. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
157236. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
157237. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
157238. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
157239. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
157240. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
157241. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
157242. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
157243. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
157244. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
157245. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
157246. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
157247. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
157248. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
157249. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
157250. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
157251. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
157252. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
157253. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
157254. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
157255. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
157256. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
157257. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
157258. BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
157259. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
157260. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
157261. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
157262. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
157263. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
157264. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
157265. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
157266. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
157267. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
157268. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
157269. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
157270. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
157271. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
157272. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
157273. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
157274. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
157275. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
157276. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
157277. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
157278. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
157279. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
157280. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
157281. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
157282. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
157283. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
157284. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
157285. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
157286. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
157287. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
157288. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
157289. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
157290. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
157291. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
157292. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
157293. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
157294. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
157295. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
157296. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
157297. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
157298. BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
157299. BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG0__TLP_HDR_MASK
157300. BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
157301. BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG1__TLP_HDR_MASK
157302. BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
157303. BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG2__TLP_HDR_MASK
157304. BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
157305. BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG3__TLP_HDR_MASK
157306. BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
157307. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
157308. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
157309. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
157310. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
157311. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
157312. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
157313. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
157314. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
157315. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
157316. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
157317. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
157318. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
157319. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
157320. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
157321. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK
157322. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
157323. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
157324. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
157325. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
157326. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
157327. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
157328. BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
157329. BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
157330. BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
157331. BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
157332. BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
157333. BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
157334. BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
157335. BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
157336. BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
157337. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
157338. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
157339. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
157340. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
157341. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
157342. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
157343. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
157344. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
157345. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
157346. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
157347. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
157348. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
157349. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
157350. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
157351. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
157352. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
157353. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
157354. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
157355. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
157356. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
157357. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
157358. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
157359. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
157360. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
157361. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
157362. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
157363. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
157364. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
157365. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
157366. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
157367. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
157368. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
157369. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
157370. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
157371. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
157372. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
157373. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
157374. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
157375. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
157376. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
157377. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
157378. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
157379. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
157380. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
157381. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
157382. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
157383. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
157384. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
157385. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
157386. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
157387. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
157388. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
157389. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
157390. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
157391. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
157392. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
157393. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
157394. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
157395. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
157396. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
157397. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
157398. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
157399. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
157400. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
157401. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
157402. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
157403. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
157404. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
157405. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
157406. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
157407. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
157408. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
157409. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
157410. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
157411. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
157412. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
157413. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
157414. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
157415. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
157416. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
157417. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
157418. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
157419. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
157420. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
157421. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
157422. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
157423. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
157424. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
157425. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
157426. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
157427. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
157428. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
157429. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
157430. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
157431. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
157432. BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
157433. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
157434. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
157435. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
157436. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
157437. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
157438. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
157439. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
157440. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
157441. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
157442. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
157443. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
157444. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
157445. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
157446. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
157447. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
157448. BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
157449. BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__CAP_ID_MASK
157450. BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__CAP_ID__SHIFT
157451. BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__NEXT_PTR_MASK
157452. BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
157453. BIF_CFG_DEV0_EPF6_2_PMI_CAP__AUX_CURRENT_MASK
157454. BIF_CFG_DEV0_EPF6_2_PMI_CAP__AUX_CURRENT__SHIFT
157455. BIF_CFG_DEV0_EPF6_2_PMI_CAP__D1_SUPPORT_MASK
157456. BIF_CFG_DEV0_EPF6_2_PMI_CAP__D1_SUPPORT__SHIFT
157457. BIF_CFG_DEV0_EPF6_2_PMI_CAP__D2_SUPPORT_MASK
157458. BIF_CFG_DEV0_EPF6_2_PMI_CAP__D2_SUPPORT__SHIFT
157459. BIF_CFG_DEV0_EPF6_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
157460. BIF_CFG_DEV0_EPF6_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
157461. BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_CLOCK_MASK
157462. BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_CLOCK__SHIFT
157463. BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_SUPPORT_MASK
157464. BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_SUPPORT__SHIFT
157465. BIF_CFG_DEV0_EPF6_2_PMI_CAP__VERSION_MASK
157466. BIF_CFG_DEV0_EPF6_2_PMI_CAP__VERSION__SHIFT
157467. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
157468. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
157469. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
157470. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
157471. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
157472. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
157473. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
157474. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
157475. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
157476. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
157477. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_EN_MASK
157478. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_EN__SHIFT
157479. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_STATUS_MASK
157480. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
157481. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PMI_DATA_MASK
157482. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
157483. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__POWER_STATE_MASK
157484. BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
157485. BIF_CFG_DEV0_EPF6_2_PROG_INTERFACE__PROG_INTERFACE_MASK
157486. BIF_CFG_DEV0_EPF6_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
157487. BIF_CFG_DEV0_EPF6_2_REVISION_ID__MAJOR_REV_ID_MASK
157488. BIF_CFG_DEV0_EPF6_2_REVISION_ID__MAJOR_REV_ID__SHIFT
157489. BIF_CFG_DEV0_EPF6_2_REVISION_ID__MINOR_REV_ID_MASK
157490. BIF_CFG_DEV0_EPF6_2_REVISION_ID__MINOR_REV_ID__SHIFT
157491. BIF_CFG_DEV0_EPF6_2_ROM_BASE_ADDR__BASE_ADDR_MASK
157492. BIF_CFG_DEV0_EPF6_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT
157493. BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__CAP_ID_MASK
157494. BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__CAP_ID__SHIFT
157495. BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__NEXT_PTR_MASK
157496. BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__NEXT_PTR__SHIFT
157497. BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
157498. BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
157499. BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
157500. BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
157501. BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
157502. BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
157503. BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
157504. BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
157505. BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
157506. BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
157507. BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
157508. BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
157509. BIF_CFG_DEV0_EPF6_2_SATA_IDP_DATA__IDP_DATA_MASK
157510. BIF_CFG_DEV0_EPF6_2_SATA_IDP_DATA__IDP_DATA__SHIFT
157511. BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_INDEX_MASK
157512. BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT
157513. BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK
157514. BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
157515. BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK
157516. BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
157517. BIF_CFG_DEV0_EPF6_2_SBRN__SBRN_MASK
157518. BIF_CFG_DEV0_EPF6_2_SBRN__SBRN__SHIFT
157519. BIF_CFG_DEV0_EPF6_2_SLOT_CAP2__RESERVED_MASK
157520. BIF_CFG_DEV0_EPF6_2_SLOT_CAP2__RESERVED__SHIFT
157521. BIF_CFG_DEV0_EPF6_2_SLOT_CNTL2__RESERVED_MASK
157522. BIF_CFG_DEV0_EPF6_2_SLOT_CNTL2__RESERVED__SHIFT
157523. BIF_CFG_DEV0_EPF6_2_SLOT_STATUS2__RESERVED_MASK
157524. BIF_CFG_DEV0_EPF6_2_SLOT_STATUS2__RESERVED__SHIFT
157525. BIF_CFG_DEV0_EPF6_2_STATUS__CAP_LIST_MASK
157526. BIF_CFG_DEV0_EPF6_2_STATUS__CAP_LIST__SHIFT
157527. BIF_CFG_DEV0_EPF6_2_STATUS__DEVSEL_TIMING_MASK
157528. BIF_CFG_DEV0_EPF6_2_STATUS__DEVSEL_TIMING__SHIFT
157529. BIF_CFG_DEV0_EPF6_2_STATUS__FAST_BACK_CAPABLE_MASK
157530. BIF_CFG_DEV0_EPF6_2_STATUS__FAST_BACK_CAPABLE__SHIFT
157531. BIF_CFG_DEV0_EPF6_2_STATUS__INT_STATUS_MASK
157532. BIF_CFG_DEV0_EPF6_2_STATUS__INT_STATUS__SHIFT
157533. BIF_CFG_DEV0_EPF6_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
157534. BIF_CFG_DEV0_EPF6_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
157535. BIF_CFG_DEV0_EPF6_2_STATUS__PARITY_ERROR_DETECTED_MASK
157536. BIF_CFG_DEV0_EPF6_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
157537. BIF_CFG_DEV0_EPF6_2_STATUS__PCI_66_EN_MASK
157538. BIF_CFG_DEV0_EPF6_2_STATUS__PCI_66_EN__SHIFT
157539. BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_MASTER_ABORT_MASK
157540. BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
157541. BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_TARGET_ABORT_MASK
157542. BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
157543. BIF_CFG_DEV0_EPF6_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
157544. BIF_CFG_DEV0_EPF6_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
157545. BIF_CFG_DEV0_EPF6_2_STATUS__SIGNAL_TARGET_ABORT_MASK
157546. BIF_CFG_DEV0_EPF6_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
157547. BIF_CFG_DEV0_EPF6_2_SUB_CLASS__SUB_CLASS_MASK
157548. BIF_CFG_DEV0_EPF6_2_SUB_CLASS__SUB_CLASS__SHIFT
157549. BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__CAP_ID_MASK
157550. BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__CAP_ID__SHIFT
157551. BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__LENGTH_MASK
157552. BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__LENGTH__SHIFT
157553. BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__NEXT_PTR_MASK
157554. BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
157555. BIF_CFG_DEV0_EPF6_2_VENDOR_ID__VENDOR_ID_MASK
157556. BIF_CFG_DEV0_EPF6_2_VENDOR_ID__VENDOR_ID__SHIFT
157557. BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
157558. BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
157559. BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
157560. BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
157561. BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
157562. BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
157563. BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
157564. BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
157565. BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR_MASK
157566. BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT
157567. BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR_MASK
157568. BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT
157569. BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR_MASK
157570. BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT
157571. BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR_MASK
157572. BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT
157573. BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR_MASK
157574. BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT
157575. BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR_MASK
157576. BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT
157577. BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS_MASK
157578. BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS__SHIFT
157579. BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP_MASK
157580. BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP__SHIFT
157581. BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP_MASK
157582. BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP__SHIFT
157583. BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT_MASK
157584. BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT__SHIFT
157585. BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
157586. BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
157587. BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR_MASK
157588. BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR__SHIFT
157589. BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING_MASK
157590. BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING__SHIFT
157591. BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN_MASK
157592. BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN__SHIFT
157593. BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN_MASK
157594. BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN__SHIFT
157595. BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS_MASK
157596. BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS__SHIFT
157597. BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN_MASK
157598. BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN__SHIFT
157599. BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN_MASK
157600. BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN__SHIFT
157601. BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
157602. BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
157603. BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN_MASK
157604. BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN__SHIFT
157605. BIF_CFG_DEV0_EPF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
157606. BIF_CFG_DEV0_EPF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
157607. BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN_MASK
157608. BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN__SHIFT
157609. BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK
157610. BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
157611. BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD_MASK
157612. BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD__SHIFT
157613. BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL_MASK
157614. BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL__SHIFT
157615. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
157616. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
157617. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
157618. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
157619. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
157620. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
157621. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
157622. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
157623. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
157624. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
157625. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
157626. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
157627. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
157628. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
157629. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
157630. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
157631. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
157632. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
157633. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
157634. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
157635. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
157636. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
157637. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
157638. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
157639. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
157640. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
157641. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
157642. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
157643. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
157644. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
157645. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
157646. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
157647. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG_MASK
157648. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
157649. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE_MASK
157650. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
157651. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
157652. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
157653. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
157654. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
157655. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
157656. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
157657. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK
157658. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
157659. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
157660. BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
157661. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
157662. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
157663. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
157664. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
157665. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
157666. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
157667. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
157668. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
157669. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
157670. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
157671. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
157672. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
157673. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
157674. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
157675. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
157676. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
157677. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN_MASK
157678. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN__SHIFT
157679. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN_MASK
157680. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT
157681. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
157682. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
157683. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK
157684. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
157685. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
157686. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
157687. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
157688. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
157689. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR_MASK
157690. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
157691. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
157692. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
157693. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
157694. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
157695. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
157696. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
157697. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
157698. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
157699. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
157700. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
157701. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
157702. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
157703. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK
157704. BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
157705. BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID_MASK
157706. BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID__SHIFT
157707. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED_MASK
157708. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED__SHIFT
157709. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR_MASK
157710. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR__SHIFT
157711. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR_MASK
157712. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR__SHIFT
157713. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR_MASK
157714. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT
157715. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
157716. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
157717. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
157718. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
157719. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED_MASK
157720. BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT
157721. BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ_MASK
157722. BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ__SHIFT
157723. BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE_MASK
157724. BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE__SHIFT
157725. BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE_MASK
157726. BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE__SHIFT
157727. BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
157728. BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
157729. BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
157730. BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
157731. BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER_MASK
157732. BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER__SHIFT
157733. BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
157734. BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
157735. BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RESERVED_MASK
157736. BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RESERVED__SHIFT
157737. BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
157738. BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
157739. BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
157740. BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
157741. BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
157742. BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
157743. BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
157744. BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
157745. BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
157746. BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
157747. BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK
157748. BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
157749. BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
157750. BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
157751. BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED_MASK
157752. BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED__SHIFT
157753. BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH_MASK
157754. BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH__SHIFT
157755. BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT_MASK
157756. BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT__SHIFT
157757. BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER_MASK
157758. BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER__SHIFT
157759. BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
157760. BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
157761. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
157762. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
157763. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
157764. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
157765. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
157766. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
157767. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
157768. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
157769. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
157770. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
157771. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
157772. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
157773. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
157774. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
157775. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN_MASK
157776. BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
157777. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
157778. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
157779. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
157780. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
157781. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC_MASK
157782. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
157783. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
157784. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
157785. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
157786. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
157787. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
157788. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
157789. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS_MASK
157790. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS__SHIFT
157791. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL_MASK
157792. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL__SHIFT
157793. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
157794. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
157795. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK_MASK
157796. BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT
157797. BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
157798. BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
157799. BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
157800. BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
157801. BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
157802. BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
157803. BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
157804. BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
157805. BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
157806. BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
157807. BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
157808. BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
157809. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
157810. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
157811. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE_MASK
157812. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE__SHIFT
157813. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
157814. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
157815. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
157816. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
157817. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING_MASK
157818. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING__SHIFT
157819. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
157820. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
157821. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
157822. BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
157823. BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT_MASK
157824. BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT__SHIFT
157825. BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT_MASK
157826. BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT__SHIFT
157827. BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID_MASK
157828. BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT
157829. BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK
157830. BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
157831. BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK
157832. BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
157833. BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
157834. BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
157835. BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
157836. BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
157837. BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK
157838. BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
157839. BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
157840. BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
157841. BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
157842. BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
157843. BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
157844. BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
157845. BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID_MASK
157846. BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID__SHIFT
157847. BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR_MASK
157848. BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
157849. BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64_MASK
157850. BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT
157851. BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK_MASK
157852. BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK__SHIFT
157853. BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
157854. BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
157855. BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
157856. BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
157857. BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK
157858. BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
157859. BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN_MASK
157860. BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT
157861. BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
157862. BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
157863. BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
157864. BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
157865. BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
157866. BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
157867. BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
157868. BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
157869. BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA_MASK
157870. BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT
157871. BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK
157872. BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
157873. BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING_MASK
157874. BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING__SHIFT
157875. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
157876. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
157877. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
157878. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
157879. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
157880. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
157881. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
157882. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
157883. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
157884. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
157885. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
157886. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
157887. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
157888. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
157889. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
157890. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
157891. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
157892. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
157893. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
157894. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
157895. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
157896. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
157897. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
157898. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
157899. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
157900. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
157901. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
157902. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
157903. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
157904. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
157905. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
157906. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
157907. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
157908. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
157909. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
157910. BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
157911. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
157912. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
157913. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
157914. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
157915. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
157916. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
157917. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
157918. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
157919. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
157920. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
157921. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
157922. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
157923. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
157924. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
157925. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
157926. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
157927. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
157928. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
157929. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
157930. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
157931. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
157932. BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
157933. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
157934. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
157935. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
157936. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
157937. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
157938. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
157939. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
157940. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
157941. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
157942. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
157943. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
157944. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
157945. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
157946. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
157947. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
157948. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
157949. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
157950. BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
157951. BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
157952. BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
157953. BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK
157954. BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
157955. BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK
157956. BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
157957. BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
157958. BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
157959. BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
157960. BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
157961. BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK
157962. BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
157963. BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK
157964. BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
157965. BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
157966. BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
157967. BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
157968. BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
157969. BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK
157970. BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
157971. BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK
157972. BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
157973. BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
157974. BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
157975. BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
157976. BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
157977. BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK
157978. BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
157979. BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK
157980. BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
157981. BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
157982. BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
157983. BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
157984. BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
157985. BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK
157986. BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
157987. BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK
157988. BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
157989. BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
157990. BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
157991. BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
157992. BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
157993. BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK
157994. BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
157995. BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK
157996. BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
157997. BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
157998. BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
157999. BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
158000. BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
158001. BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
158002. BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
158003. BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
158004. BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
158005. BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID_MASK
158006. BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT
158007. BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK
158008. BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
158009. BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE_MASK
158010. BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT
158011. BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
158012. BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
158013. BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
158014. BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
158015. BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION_MASK
158016. BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION__SHIFT
158017. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
158018. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
158019. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
158020. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
158021. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
158022. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
158023. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
158024. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
158025. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
158026. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
158027. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
158028. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
158029. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
158030. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
158031. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
158032. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
158033. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
158034. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
158035. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
158036. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
158037. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
158038. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
158039. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
158040. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
158041. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
158042. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
158043. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
158044. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
158045. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
158046. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
158047. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
158048. BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
158049. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
158050. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
158051. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
158052. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
158053. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
158054. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
158055. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
158056. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
158057. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
158058. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
158059. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
158060. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
158061. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
158062. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
158063. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
158064. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
158065. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
158066. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
158067. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
158068. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
158069. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
158070. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
158071. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
158072. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
158073. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
158074. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
158075. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
158076. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
158077. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
158078. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
158079. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
158080. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
158081. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
158082. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
158083. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
158084. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
158085. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
158086. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
158087. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
158088. BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
158089. BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK
158090. BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
158091. BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK
158092. BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
158093. BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK
158094. BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
158095. BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK
158096. BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
158097. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
158098. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
158099. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
158100. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
158101. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
158102. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
158103. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
158104. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
158105. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
158106. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
158107. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
158108. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
158109. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
158110. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
158111. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK
158112. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
158113. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
158114. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
158115. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
158116. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
158117. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
158118. BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
158119. BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
158120. BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
158121. BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
158122. BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
158123. BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
158124. BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
158125. BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
158126. BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
158127. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
158128. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
158129. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
158130. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
158131. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
158132. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
158133. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
158134. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
158135. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
158136. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
158137. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
158138. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
158139. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
158140. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
158141. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
158142. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
158143. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
158144. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
158145. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
158146. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
158147. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
158148. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
158149. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
158150. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
158151. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
158152. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
158153. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
158154. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
158155. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
158156. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
158157. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
158158. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
158159. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
158160. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
158161. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
158162. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
158163. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
158164. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
158165. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
158166. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
158167. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
158168. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
158169. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
158170. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
158171. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
158172. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
158173. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
158174. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
158175. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
158176. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
158177. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
158178. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
158179. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
158180. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
158181. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
158182. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
158183. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
158184. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
158185. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
158186. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
158187. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
158188. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
158189. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
158190. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
158191. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
158192. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
158193. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
158194. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
158195. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
158196. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
158197. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
158198. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
158199. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
158200. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
158201. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
158202. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
158203. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
158204. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
158205. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
158206. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
158207. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
158208. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
158209. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
158210. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
158211. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
158212. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
158213. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
158214. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
158215. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
158216. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
158217. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
158218. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
158219. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
158220. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
158221. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
158222. BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
158223. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
158224. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
158225. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
158226. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
158227. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
158228. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
158229. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
158230. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
158231. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
158232. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
158233. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
158234. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
158235. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
158236. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
158237. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
158238. BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
158239. BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID_MASK
158240. BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID__SHIFT
158241. BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR_MASK
158242. BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
158243. BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT_MASK
158244. BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT__SHIFT
158245. BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT_MASK
158246. BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT__SHIFT
158247. BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT_MASK
158248. BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT__SHIFT
158249. BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
158250. BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
158251. BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK_MASK
158252. BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK__SHIFT
158253. BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT_MASK
158254. BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT__SHIFT
158255. BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION_MASK
158256. BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION__SHIFT
158257. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
158258. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
158259. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
158260. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
158261. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
158262. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
158263. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
158264. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
158265. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
158266. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
158267. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN_MASK
158268. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN__SHIFT
158269. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS_MASK
158270. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
158271. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA_MASK
158272. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
158273. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE_MASK
158274. BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
158275. BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK
158276. BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
158277. BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID_MASK
158278. BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT
158279. BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID_MASK
158280. BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID__SHIFT
158281. BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK
158282. BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
158283. BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__CAP_ID_MASK
158284. BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__CAP_ID__SHIFT
158285. BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__NEXT_PTR_MASK
158286. BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__NEXT_PTR__SHIFT
158287. BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
158288. BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
158289. BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
158290. BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
158291. BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
158292. BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
158293. BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
158294. BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
158295. BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
158296. BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
158297. BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
158298. BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
158299. BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA__IDP_DATA_MASK
158300. BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA__IDP_DATA__SHIFT
158301. BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_INDEX_MASK
158302. BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT
158303. BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK
158304. BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
158305. BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK
158306. BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
158307. BIF_CFG_DEV0_EPF7_0_SBRN__SBRN_MASK
158308. BIF_CFG_DEV0_EPF7_0_SBRN__SBRN__SHIFT
158309. BIF_CFG_DEV0_EPF7_0_SLOT_CAP2__RESERVED_MASK
158310. BIF_CFG_DEV0_EPF7_0_SLOT_CAP2__RESERVED__SHIFT
158311. BIF_CFG_DEV0_EPF7_0_SLOT_CNTL2__RESERVED_MASK
158312. BIF_CFG_DEV0_EPF7_0_SLOT_CNTL2__RESERVED__SHIFT
158313. BIF_CFG_DEV0_EPF7_0_SLOT_STATUS2__RESERVED_MASK
158314. BIF_CFG_DEV0_EPF7_0_SLOT_STATUS2__RESERVED__SHIFT
158315. BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST_MASK
158316. BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST__SHIFT
158317. BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING_MASK
158318. BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING__SHIFT
158319. BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE_MASK
158320. BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT
158321. BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS_MASK
158322. BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS__SHIFT
158323. BIF_CFG_DEV0_EPF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
158324. BIF_CFG_DEV0_EPF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
158325. BIF_CFG_DEV0_EPF7_0_STATUS__PARITY_ERROR_DETECTED_MASK
158326. BIF_CFG_DEV0_EPF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
158327. BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_EN_MASK
158328. BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_EN__SHIFT
158329. BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK
158330. BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
158331. BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK
158332. BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
158333. BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
158334. BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
158335. BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK
158336. BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
158337. BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS_MASK
158338. BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS__SHIFT
158339. BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID_MASK
158340. BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID__SHIFT
158341. BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH_MASK
158342. BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH__SHIFT
158343. BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR_MASK
158344. BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
158345. BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID_MASK
158346. BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID__SHIFT
158347. BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
158348. BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
158349. BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
158350. BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
158351. BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
158352. BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
158353. BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
158354. BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
158355. BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1__BASE_ADDR_MASK
158356. BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT
158357. BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2__BASE_ADDR_MASK
158358. BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT
158359. BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3__BASE_ADDR_MASK
158360. BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT
158361. BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4__BASE_ADDR_MASK
158362. BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT
158363. BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5__BASE_ADDR_MASK
158364. BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT
158365. BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6__BASE_ADDR_MASK
158366. BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT
158367. BIF_CFG_DEV0_EPF7_1_BASE_CLASS__BASE_CLASS_MASK
158368. BIF_CFG_DEV0_EPF7_1_BASE_CLASS__BASE_CLASS__SHIFT
158369. BIF_CFG_DEV0_EPF7_1_BIST__BIST_CAP_MASK
158370. BIF_CFG_DEV0_EPF7_1_BIST__BIST_CAP__SHIFT
158371. BIF_CFG_DEV0_EPF7_1_BIST__BIST_COMP_MASK
158372. BIF_CFG_DEV0_EPF7_1_BIST__BIST_COMP__SHIFT
158373. BIF_CFG_DEV0_EPF7_1_BIST__BIST_STRT_MASK
158374. BIF_CFG_DEV0_EPF7_1_BIST__BIST_STRT__SHIFT
158375. BIF_CFG_DEV0_EPF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
158376. BIF_CFG_DEV0_EPF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
158377. BIF_CFG_DEV0_EPF7_1_CAP_PTR__CAP_PTR_MASK
158378. BIF_CFG_DEV0_EPF7_1_CAP_PTR__CAP_PTR__SHIFT
158379. BIF_CFG_DEV0_EPF7_1_COMMAND__AD_STEPPING_MASK
158380. BIF_CFG_DEV0_EPF7_1_COMMAND__AD_STEPPING__SHIFT
158381. BIF_CFG_DEV0_EPF7_1_COMMAND__BUS_MASTER_EN_MASK
158382. BIF_CFG_DEV0_EPF7_1_COMMAND__BUS_MASTER_EN__SHIFT
158383. BIF_CFG_DEV0_EPF7_1_COMMAND__FAST_B2B_EN_MASK
158384. BIF_CFG_DEV0_EPF7_1_COMMAND__FAST_B2B_EN__SHIFT
158385. BIF_CFG_DEV0_EPF7_1_COMMAND__INT_DIS_MASK
158386. BIF_CFG_DEV0_EPF7_1_COMMAND__INT_DIS__SHIFT
158387. BIF_CFG_DEV0_EPF7_1_COMMAND__IO_ACCESS_EN_MASK
158388. BIF_CFG_DEV0_EPF7_1_COMMAND__IO_ACCESS_EN__SHIFT
158389. BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_ACCESS_EN_MASK
158390. BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_ACCESS_EN__SHIFT
158391. BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
158392. BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
158393. BIF_CFG_DEV0_EPF7_1_COMMAND__PAL_SNOOP_EN_MASK
158394. BIF_CFG_DEV0_EPF7_1_COMMAND__PAL_SNOOP_EN__SHIFT
158395. BIF_CFG_DEV0_EPF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
158396. BIF_CFG_DEV0_EPF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
158397. BIF_CFG_DEV0_EPF7_1_COMMAND__SERR_EN_MASK
158398. BIF_CFG_DEV0_EPF7_1_COMMAND__SERR_EN__SHIFT
158399. BIF_CFG_DEV0_EPF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK
158400. BIF_CFG_DEV0_EPF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
158401. BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESLD_MASK
158402. BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESLD__SHIFT
158403. BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESL_MASK
158404. BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESL__SHIFT
158405. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
158406. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
158407. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
158408. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
158409. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
158410. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
158411. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
158412. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
158413. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
158414. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
158415. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
158416. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
158417. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
158418. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
158419. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
158420. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
158421. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
158422. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
158423. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
158424. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
158425. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
158426. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
158427. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
158428. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
158429. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
158430. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
158431. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
158432. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
158433. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
158434. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
158435. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
158436. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
158437. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__EXTENDED_TAG_MASK
158438. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
158439. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__FLR_CAPABLE_MASK
158440. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
158441. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
158442. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
158443. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
158444. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
158445. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
158446. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
158447. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK
158448. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
158449. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
158450. BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
158451. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
158452. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
158453. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
158454. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
158455. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
158456. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
158457. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
158458. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
158459. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
158460. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
158461. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
158462. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
158463. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
158464. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
158465. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
158466. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
158467. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__LTR_EN_MASK
158468. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__LTR_EN__SHIFT
158469. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__OBFF_EN_MASK
158470. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT
158471. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
158472. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
158473. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK
158474. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
158475. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
158476. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
158477. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
158478. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
158479. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__INITIATE_FLR_MASK
158480. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
158481. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
158482. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
158483. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
158484. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
158485. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
158486. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
158487. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
158488. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
158489. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
158490. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
158491. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
158492. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
158493. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK
158494. BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
158495. BIF_CFG_DEV0_EPF7_1_DEVICE_ID__DEVICE_ID_MASK
158496. BIF_CFG_DEV0_EPF7_1_DEVICE_ID__DEVICE_ID__SHIFT
158497. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2__RESERVED_MASK
158498. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2__RESERVED__SHIFT
158499. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__AUX_PWR_MASK
158500. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__AUX_PWR__SHIFT
158501. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__CORR_ERR_MASK
158502. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__CORR_ERR__SHIFT
158503. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__FATAL_ERR_MASK
158504. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT
158505. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
158506. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
158507. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
158508. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
158509. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__USR_DETECTED_MASK
158510. BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT
158511. BIF_CFG_DEV0_EPF7_1_FLADJ__FLADJ_MASK
158512. BIF_CFG_DEV0_EPF7_1_FLADJ__FLADJ__SHIFT
158513. BIF_CFG_DEV0_EPF7_1_HEADER__DEVICE_TYPE_MASK
158514. BIF_CFG_DEV0_EPF7_1_HEADER__DEVICE_TYPE__SHIFT
158515. BIF_CFG_DEV0_EPF7_1_HEADER__HEADER_TYPE_MASK
158516. BIF_CFG_DEV0_EPF7_1_HEADER__HEADER_TYPE__SHIFT
158517. BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
158518. BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
158519. BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
158520. BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
158521. BIF_CFG_DEV0_EPF7_1_LATENCY__LATENCY_TIMER_MASK
158522. BIF_CFG_DEV0_EPF7_1_LATENCY__LATENCY_TIMER__SHIFT
158523. BIF_CFG_DEV0_EPF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
158524. BIF_CFG_DEV0_EPF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
158525. BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RESERVED_MASK
158526. BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RESERVED__SHIFT
158527. BIF_CFG_DEV0_EPF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
158528. BIF_CFG_DEV0_EPF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
158529. BIF_CFG_DEV0_EPF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
158530. BIF_CFG_DEV0_EPF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
158531. BIF_CFG_DEV0_EPF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
158532. BIF_CFG_DEV0_EPF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
158533. BIF_CFG_DEV0_EPF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
158534. BIF_CFG_DEV0_EPF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
158535. BIF_CFG_DEV0_EPF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
158536. BIF_CFG_DEV0_EPF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
158537. BIF_CFG_DEV0_EPF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK
158538. BIF_CFG_DEV0_EPF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
158539. BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
158540. BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
158541. BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_SPEED_MASK
158542. BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_SPEED__SHIFT
158543. BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_WIDTH_MASK
158544. BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_WIDTH__SHIFT
158545. BIF_CFG_DEV0_EPF7_1_LINK_CAP__PM_SUPPORT_MASK
158546. BIF_CFG_DEV0_EPF7_1_LINK_CAP__PM_SUPPORT__SHIFT
158547. BIF_CFG_DEV0_EPF7_1_LINK_CAP__PORT_NUMBER_MASK
158548. BIF_CFG_DEV0_EPF7_1_LINK_CAP__PORT_NUMBER__SHIFT
158549. BIF_CFG_DEV0_EPF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
158550. BIF_CFG_DEV0_EPF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
158551. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
158552. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
158553. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
158554. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
158555. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
158556. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
158557. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
158558. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
158559. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
158560. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
158561. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
158562. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
158563. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
158564. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
158565. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__XMIT_MARGIN_MASK
158566. BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
158567. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
158568. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
158569. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
158570. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
158571. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__EXTENDED_SYNC_MASK
158572. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
158573. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
158574. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
158575. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
158576. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
158577. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
158578. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
158579. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_DIS_MASK
158580. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_DIS__SHIFT
158581. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__PM_CONTROL_MASK
158582. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__PM_CONTROL__SHIFT
158583. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
158584. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
158585. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__RETRAIN_LINK_MASK
158586. BIF_CFG_DEV0_EPF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT
158587. BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
158588. BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
158589. BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
158590. BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
158591. BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
158592. BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
158593. BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
158594. BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
158595. BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
158596. BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
158597. BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
158598. BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
158599. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
158600. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
158601. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__DL_ACTIVE_MASK
158602. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__DL_ACTIVE__SHIFT
158603. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
158604. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
158605. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
158606. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
158607. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_TRAINING_MASK
158608. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_TRAINING__SHIFT
158609. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
158610. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
158611. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
158612. BIF_CFG_DEV0_EPF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
158613. BIF_CFG_DEV0_EPF7_1_MAX_LATENCY__MAX_LAT_MASK
158614. BIF_CFG_DEV0_EPF7_1_MAX_LATENCY__MAX_LAT__SHIFT
158615. BIF_CFG_DEV0_EPF7_1_MIN_GRANT__MIN_GNT_MASK
158616. BIF_CFG_DEV0_EPF7_1_MIN_GRANT__MIN_GNT__SHIFT
158617. BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__CAP_ID_MASK
158618. BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT
158619. BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK
158620. BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
158621. BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK
158622. BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
158623. BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
158624. BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
158625. BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
158626. BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
158627. BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK
158628. BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
158629. BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
158630. BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
158631. BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
158632. BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
158633. BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
158634. BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
158635. BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__CAP_ID_MASK
158636. BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__CAP_ID__SHIFT
158637. BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__NEXT_PTR_MASK
158638. BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
158639. BIF_CFG_DEV0_EPF7_1_MSI_MASK_64__MSI_MASK_64_MASK
158640. BIF_CFG_DEV0_EPF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT
158641. BIF_CFG_DEV0_EPF7_1_MSI_MASK__MSI_MASK_MASK
158642. BIF_CFG_DEV0_EPF7_1_MSI_MASK__MSI_MASK__SHIFT
158643. BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
158644. BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
158645. BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
158646. BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
158647. BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK
158648. BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
158649. BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EN_MASK
158650. BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT
158651. BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
158652. BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
158653. BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
158654. BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
158655. BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
158656. BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
158657. BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
158658. BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
158659. BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA__MSI_DATA_MASK
158660. BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT
158661. BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK
158662. BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
158663. BIF_CFG_DEV0_EPF7_1_MSI_PENDING__MSI_PENDING_MASK
158664. BIF_CFG_DEV0_EPF7_1_MSI_PENDING__MSI_PENDING__SHIFT
158665. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
158666. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
158667. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
158668. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
158669. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
158670. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
158671. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
158672. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
158673. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
158674. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
158675. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
158676. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
158677. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
158678. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
158679. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
158680. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
158681. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
158682. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
158683. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
158684. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
158685. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
158686. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
158687. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
158688. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
158689. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
158690. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
158691. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
158692. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
158693. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
158694. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
158695. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
158696. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
158697. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
158698. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
158699. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
158700. BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
158701. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
158702. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
158703. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
158704. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
158705. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
158706. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
158707. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
158708. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
158709. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
158710. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
158711. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
158712. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
158713. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
158714. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
158715. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
158716. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
158717. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
158718. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
158719. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
158720. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
158721. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
158722. BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
158723. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
158724. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
158725. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
158726. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
158727. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
158728. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
158729. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
158730. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
158731. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
158732. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
158733. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
158734. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
158735. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
158736. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
158737. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
158738. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
158739. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
158740. BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
158741. BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
158742. BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
158743. BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK
158744. BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
158745. BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK
158746. BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
158747. BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
158748. BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
158749. BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
158750. BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
158751. BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK
158752. BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
158753. BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK
158754. BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
158755. BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
158756. BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
158757. BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
158758. BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
158759. BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK
158760. BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
158761. BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK
158762. BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
158763. BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
158764. BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
158765. BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
158766. BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
158767. BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK
158768. BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
158769. BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK
158770. BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
158771. BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
158772. BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
158773. BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
158774. BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
158775. BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK
158776. BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
158777. BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK
158778. BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
158779. BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
158780. BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
158781. BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
158782. BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
158783. BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK
158784. BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
158785. BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK
158786. BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
158787. BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
158788. BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
158789. BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
158790. BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
158791. BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
158792. BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
158793. BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
158794. BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
158795. BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__CAP_ID_MASK
158796. BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT
158797. BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK
158798. BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
158799. BIF_CFG_DEV0_EPF7_1_PCIE_CAP__DEVICE_TYPE_MASK
158800. BIF_CFG_DEV0_EPF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT
158801. BIF_CFG_DEV0_EPF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
158802. BIF_CFG_DEV0_EPF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
158803. BIF_CFG_DEV0_EPF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
158804. BIF_CFG_DEV0_EPF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
158805. BIF_CFG_DEV0_EPF7_1_PCIE_CAP__VERSION_MASK
158806. BIF_CFG_DEV0_EPF7_1_PCIE_CAP__VERSION__SHIFT
158807. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
158808. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
158809. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
158810. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
158811. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
158812. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
158813. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
158814. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
158815. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
158816. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
158817. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
158818. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
158819. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
158820. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
158821. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
158822. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
158823. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
158824. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
158825. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
158826. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
158827. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
158828. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
158829. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
158830. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
158831. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
158832. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
158833. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
158834. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
158835. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
158836. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
158837. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
158838. BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
158839. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
158840. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
158841. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
158842. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
158843. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
158844. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
158845. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
158846. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
158847. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
158848. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
158849. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
158850. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
158851. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
158852. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
158853. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
158854. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
158855. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
158856. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
158857. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
158858. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
158859. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
158860. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
158861. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
158862. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
158863. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
158864. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
158865. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
158866. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
158867. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
158868. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
158869. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
158870. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
158871. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
158872. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
158873. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
158874. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
158875. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
158876. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
158877. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
158878. BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
158879. BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK
158880. BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
158881. BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK
158882. BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
158883. BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK
158884. BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
158885. BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK
158886. BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
158887. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
158888. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
158889. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
158890. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
158891. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
158892. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
158893. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
158894. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
158895. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
158896. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
158897. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
158898. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
158899. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
158900. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
158901. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK
158902. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
158903. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
158904. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
158905. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
158906. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
158907. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
158908. BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
158909. BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
158910. BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
158911. BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
158912. BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
158913. BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
158914. BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
158915. BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
158916. BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
158917. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
158918. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
158919. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
158920. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
158921. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
158922. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
158923. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
158924. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
158925. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
158926. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
158927. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
158928. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
158929. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
158930. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
158931. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
158932. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
158933. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
158934. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
158935. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
158936. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
158937. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
158938. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
158939. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
158940. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
158941. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
158942. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
158943. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
158944. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
158945. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
158946. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
158947. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
158948. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
158949. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
158950. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
158951. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
158952. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
158953. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
158954. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
158955. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
158956. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
158957. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
158958. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
158959. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
158960. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
158961. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
158962. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
158963. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
158964. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
158965. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
158966. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
158967. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
158968. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
158969. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
158970. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
158971. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
158972. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
158973. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
158974. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
158975. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
158976. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
158977. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
158978. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
158979. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
158980. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
158981. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
158982. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
158983. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
158984. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
158985. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
158986. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
158987. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
158988. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
158989. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
158990. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
158991. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
158992. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
158993. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
158994. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
158995. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
158996. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
158997. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
158998. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
158999. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
159000. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
159001. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
159002. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
159003. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
159004. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
159005. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
159006. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
159007. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
159008. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
159009. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
159010. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
159011. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
159012. BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
159013. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
159014. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
159015. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
159016. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
159017. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
159018. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
159019. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
159020. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
159021. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
159022. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
159023. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
159024. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
159025. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
159026. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
159027. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
159028. BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
159029. BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__CAP_ID_MASK
159030. BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__CAP_ID__SHIFT
159031. BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__NEXT_PTR_MASK
159032. BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
159033. BIF_CFG_DEV0_EPF7_1_PMI_CAP__AUX_CURRENT_MASK
159034. BIF_CFG_DEV0_EPF7_1_PMI_CAP__AUX_CURRENT__SHIFT
159035. BIF_CFG_DEV0_EPF7_1_PMI_CAP__D1_SUPPORT_MASK
159036. BIF_CFG_DEV0_EPF7_1_PMI_CAP__D1_SUPPORT__SHIFT
159037. BIF_CFG_DEV0_EPF7_1_PMI_CAP__D2_SUPPORT_MASK
159038. BIF_CFG_DEV0_EPF7_1_PMI_CAP__D2_SUPPORT__SHIFT
159039. BIF_CFG_DEV0_EPF7_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
159040. BIF_CFG_DEV0_EPF7_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
159041. BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_CLOCK_MASK
159042. BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_CLOCK__SHIFT
159043. BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_SUPPORT_MASK
159044. BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_SUPPORT__SHIFT
159045. BIF_CFG_DEV0_EPF7_1_PMI_CAP__VERSION_MASK
159046. BIF_CFG_DEV0_EPF7_1_PMI_CAP__VERSION__SHIFT
159047. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
159048. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
159049. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
159050. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
159051. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
159052. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
159053. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
159054. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
159055. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
159056. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
159057. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_EN_MASK
159058. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_EN__SHIFT
159059. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_STATUS_MASK
159060. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
159061. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PMI_DATA_MASK
159062. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
159063. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__POWER_STATE_MASK
159064. BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
159065. BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK
159066. BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
159067. BIF_CFG_DEV0_EPF7_1_REVISION_ID__MAJOR_REV_ID_MASK
159068. BIF_CFG_DEV0_EPF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT
159069. BIF_CFG_DEV0_EPF7_1_REVISION_ID__MINOR_REV_ID_MASK
159070. BIF_CFG_DEV0_EPF7_1_REVISION_ID__MINOR_REV_ID__SHIFT
159071. BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK
159072. BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
159073. BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__CAP_ID_MASK
159074. BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__CAP_ID__SHIFT
159075. BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__NEXT_PTR_MASK
159076. BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__NEXT_PTR__SHIFT
159077. BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
159078. BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
159079. BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
159080. BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
159081. BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
159082. BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
159083. BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
159084. BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
159085. BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
159086. BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
159087. BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
159088. BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
159089. BIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA__IDP_DATA_MASK
159090. BIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA__IDP_DATA__SHIFT
159091. BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_INDEX_MASK
159092. BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT
159093. BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK
159094. BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
159095. BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK
159096. BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
159097. BIF_CFG_DEV0_EPF7_1_SBRN__SBRN_MASK
159098. BIF_CFG_DEV0_EPF7_1_SBRN__SBRN__SHIFT
159099. BIF_CFG_DEV0_EPF7_1_SLOT_CAP2__RESERVED_MASK
159100. BIF_CFG_DEV0_EPF7_1_SLOT_CAP2__RESERVED__SHIFT
159101. BIF_CFG_DEV0_EPF7_1_SLOT_CNTL2__RESERVED_MASK
159102. BIF_CFG_DEV0_EPF7_1_SLOT_CNTL2__RESERVED__SHIFT
159103. BIF_CFG_DEV0_EPF7_1_SLOT_STATUS2__RESERVED_MASK
159104. BIF_CFG_DEV0_EPF7_1_SLOT_STATUS2__RESERVED__SHIFT
159105. BIF_CFG_DEV0_EPF7_1_STATUS__CAP_LIST_MASK
159106. BIF_CFG_DEV0_EPF7_1_STATUS__CAP_LIST__SHIFT
159107. BIF_CFG_DEV0_EPF7_1_STATUS__DEVSEL_TIMING_MASK
159108. BIF_CFG_DEV0_EPF7_1_STATUS__DEVSEL_TIMING__SHIFT
159109. BIF_CFG_DEV0_EPF7_1_STATUS__FAST_BACK_CAPABLE_MASK
159110. BIF_CFG_DEV0_EPF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT
159111. BIF_CFG_DEV0_EPF7_1_STATUS__INT_STATUS_MASK
159112. BIF_CFG_DEV0_EPF7_1_STATUS__INT_STATUS__SHIFT
159113. BIF_CFG_DEV0_EPF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
159114. BIF_CFG_DEV0_EPF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
159115. BIF_CFG_DEV0_EPF7_1_STATUS__PARITY_ERROR_DETECTED_MASK
159116. BIF_CFG_DEV0_EPF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
159117. BIF_CFG_DEV0_EPF7_1_STATUS__PCI_66_EN_MASK
159118. BIF_CFG_DEV0_EPF7_1_STATUS__PCI_66_EN__SHIFT
159119. BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK
159120. BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
159121. BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK
159122. BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
159123. BIF_CFG_DEV0_EPF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
159124. BIF_CFG_DEV0_EPF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
159125. BIF_CFG_DEV0_EPF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK
159126. BIF_CFG_DEV0_EPF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
159127. BIF_CFG_DEV0_EPF7_1_SUB_CLASS__SUB_CLASS_MASK
159128. BIF_CFG_DEV0_EPF7_1_SUB_CLASS__SUB_CLASS__SHIFT
159129. BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__CAP_ID_MASK
159130. BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__CAP_ID__SHIFT
159131. BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__LENGTH_MASK
159132. BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__LENGTH__SHIFT
159133. BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__NEXT_PTR_MASK
159134. BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
159135. BIF_CFG_DEV0_EPF7_1_VENDOR_ID__VENDOR_ID_MASK
159136. BIF_CFG_DEV0_EPF7_1_VENDOR_ID__VENDOR_ID__SHIFT
159137. BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
159138. BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
159139. BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
159140. BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
159141. BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_ID_MASK
159142. BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
159143. BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
159144. BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
159145. BIF_CFG_DEV0_EPF7_2_BASE_ADDR_1__BASE_ADDR_MASK
159146. BIF_CFG_DEV0_EPF7_2_BASE_ADDR_1__BASE_ADDR__SHIFT
159147. BIF_CFG_DEV0_EPF7_2_BASE_ADDR_2__BASE_ADDR_MASK
159148. BIF_CFG_DEV0_EPF7_2_BASE_ADDR_2__BASE_ADDR__SHIFT
159149. BIF_CFG_DEV0_EPF7_2_BASE_ADDR_3__BASE_ADDR_MASK
159150. BIF_CFG_DEV0_EPF7_2_BASE_ADDR_3__BASE_ADDR__SHIFT
159151. BIF_CFG_DEV0_EPF7_2_BASE_ADDR_4__BASE_ADDR_MASK
159152. BIF_CFG_DEV0_EPF7_2_BASE_ADDR_4__BASE_ADDR__SHIFT
159153. BIF_CFG_DEV0_EPF7_2_BASE_ADDR_5__BASE_ADDR_MASK
159154. BIF_CFG_DEV0_EPF7_2_BASE_ADDR_5__BASE_ADDR__SHIFT
159155. BIF_CFG_DEV0_EPF7_2_BASE_ADDR_6__BASE_ADDR_MASK
159156. BIF_CFG_DEV0_EPF7_2_BASE_ADDR_6__BASE_ADDR__SHIFT
159157. BIF_CFG_DEV0_EPF7_2_BASE_CLASS__BASE_CLASS_MASK
159158. BIF_CFG_DEV0_EPF7_2_BASE_CLASS__BASE_CLASS__SHIFT
159159. BIF_CFG_DEV0_EPF7_2_BIST__BIST_CAP_MASK
159160. BIF_CFG_DEV0_EPF7_2_BIST__BIST_CAP__SHIFT
159161. BIF_CFG_DEV0_EPF7_2_BIST__BIST_COMP_MASK
159162. BIF_CFG_DEV0_EPF7_2_BIST__BIST_COMP__SHIFT
159163. BIF_CFG_DEV0_EPF7_2_BIST__BIST_STRT_MASK
159164. BIF_CFG_DEV0_EPF7_2_BIST__BIST_STRT__SHIFT
159165. BIF_CFG_DEV0_EPF7_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
159166. BIF_CFG_DEV0_EPF7_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
159167. BIF_CFG_DEV0_EPF7_2_CAP_PTR__CAP_PTR_MASK
159168. BIF_CFG_DEV0_EPF7_2_CAP_PTR__CAP_PTR__SHIFT
159169. BIF_CFG_DEV0_EPF7_2_COMMAND__AD_STEPPING_MASK
159170. BIF_CFG_DEV0_EPF7_2_COMMAND__AD_STEPPING__SHIFT
159171. BIF_CFG_DEV0_EPF7_2_COMMAND__BUS_MASTER_EN_MASK
159172. BIF_CFG_DEV0_EPF7_2_COMMAND__BUS_MASTER_EN__SHIFT
159173. BIF_CFG_DEV0_EPF7_2_COMMAND__FAST_B2B_EN_MASK
159174. BIF_CFG_DEV0_EPF7_2_COMMAND__FAST_B2B_EN__SHIFT
159175. BIF_CFG_DEV0_EPF7_2_COMMAND__INT_DIS_MASK
159176. BIF_CFG_DEV0_EPF7_2_COMMAND__INT_DIS__SHIFT
159177. BIF_CFG_DEV0_EPF7_2_COMMAND__IO_ACCESS_EN_MASK
159178. BIF_CFG_DEV0_EPF7_2_COMMAND__IO_ACCESS_EN__SHIFT
159179. BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_ACCESS_EN_MASK
159180. BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_ACCESS_EN__SHIFT
159181. BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
159182. BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
159183. BIF_CFG_DEV0_EPF7_2_COMMAND__PAL_SNOOP_EN_MASK
159184. BIF_CFG_DEV0_EPF7_2_COMMAND__PAL_SNOOP_EN__SHIFT
159185. BIF_CFG_DEV0_EPF7_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
159186. BIF_CFG_DEV0_EPF7_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
159187. BIF_CFG_DEV0_EPF7_2_COMMAND__SERR_EN_MASK
159188. BIF_CFG_DEV0_EPF7_2_COMMAND__SERR_EN__SHIFT
159189. BIF_CFG_DEV0_EPF7_2_COMMAND__SPECIAL_CYCLE_EN_MASK
159190. BIF_CFG_DEV0_EPF7_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
159191. BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESLD_MASK
159192. BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESLD__SHIFT
159193. BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESL_MASK
159194. BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESL__SHIFT
159195. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
159196. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
159197. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
159198. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
159199. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
159200. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
159201. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
159202. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
159203. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
159204. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
159205. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
159206. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
159207. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
159208. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
159209. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
159210. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
159211. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
159212. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
159213. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
159214. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
159215. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
159216. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
159217. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
159218. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
159219. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
159220. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
159221. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
159222. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
159223. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
159224. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
159225. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
159226. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
159227. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__EXTENDED_TAG_MASK
159228. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
159229. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__FLR_CAPABLE_MASK
159230. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
159231. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
159232. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
159233. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
159234. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
159235. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
159236. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
159237. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__PHANTOM_FUNC_MASK
159238. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
159239. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
159240. BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
159241. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
159242. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
159243. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
159244. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
159245. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
159246. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
159247. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
159248. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
159249. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
159250. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
159251. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
159252. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
159253. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
159254. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
159255. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
159256. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
159257. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__LTR_EN_MASK
159258. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__LTR_EN__SHIFT
159259. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__OBFF_EN_MASK
159260. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__OBFF_EN__SHIFT
159261. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
159262. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
159263. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__CORR_ERR_EN_MASK
159264. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
159265. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
159266. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
159267. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
159268. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
159269. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__INITIATE_FLR_MASK
159270. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__INITIATE_FLR__SHIFT
159271. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
159272. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
159273. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
159274. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
159275. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
159276. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
159277. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
159278. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
159279. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
159280. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
159281. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
159282. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
159283. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__USR_REPORT_EN_MASK
159284. BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
159285. BIF_CFG_DEV0_EPF7_2_DEVICE_ID__DEVICE_ID_MASK
159286. BIF_CFG_DEV0_EPF7_2_DEVICE_ID__DEVICE_ID__SHIFT
159287. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS2__RESERVED_MASK
159288. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS2__RESERVED__SHIFT
159289. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__AUX_PWR_MASK
159290. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__AUX_PWR__SHIFT
159291. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__CORR_ERR_MASK
159292. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__CORR_ERR__SHIFT
159293. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__FATAL_ERR_MASK
159294. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__FATAL_ERR__SHIFT
159295. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
159296. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
159297. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
159298. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
159299. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__USR_DETECTED_MASK
159300. BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__USR_DETECTED__SHIFT
159301. BIF_CFG_DEV0_EPF7_2_FLADJ__FLADJ_MASK
159302. BIF_CFG_DEV0_EPF7_2_FLADJ__FLADJ__SHIFT
159303. BIF_CFG_DEV0_EPF7_2_HEADER__DEVICE_TYPE_MASK
159304. BIF_CFG_DEV0_EPF7_2_HEADER__DEVICE_TYPE__SHIFT
159305. BIF_CFG_DEV0_EPF7_2_HEADER__HEADER_TYPE_MASK
159306. BIF_CFG_DEV0_EPF7_2_HEADER__HEADER_TYPE__SHIFT
159307. BIF_CFG_DEV0_EPF7_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
159308. BIF_CFG_DEV0_EPF7_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
159309. BIF_CFG_DEV0_EPF7_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
159310. BIF_CFG_DEV0_EPF7_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
159311. BIF_CFG_DEV0_EPF7_2_LATENCY__LATENCY_TIMER_MASK
159312. BIF_CFG_DEV0_EPF7_2_LATENCY__LATENCY_TIMER__SHIFT
159313. BIF_CFG_DEV0_EPF7_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
159314. BIF_CFG_DEV0_EPF7_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
159315. BIF_CFG_DEV0_EPF7_2_LINK_CAP2__RESERVED_MASK
159316. BIF_CFG_DEV0_EPF7_2_LINK_CAP2__RESERVED__SHIFT
159317. BIF_CFG_DEV0_EPF7_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
159318. BIF_CFG_DEV0_EPF7_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
159319. BIF_CFG_DEV0_EPF7_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
159320. BIF_CFG_DEV0_EPF7_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
159321. BIF_CFG_DEV0_EPF7_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
159322. BIF_CFG_DEV0_EPF7_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
159323. BIF_CFG_DEV0_EPF7_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
159324. BIF_CFG_DEV0_EPF7_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
159325. BIF_CFG_DEV0_EPF7_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
159326. BIF_CFG_DEV0_EPF7_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
159327. BIF_CFG_DEV0_EPF7_2_LINK_CAP__L1_EXIT_LATENCY_MASK
159328. BIF_CFG_DEV0_EPF7_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
159329. BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
159330. BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
159331. BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_SPEED_MASK
159332. BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_SPEED__SHIFT
159333. BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_WIDTH_MASK
159334. BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_WIDTH__SHIFT
159335. BIF_CFG_DEV0_EPF7_2_LINK_CAP__PM_SUPPORT_MASK
159336. BIF_CFG_DEV0_EPF7_2_LINK_CAP__PM_SUPPORT__SHIFT
159337. BIF_CFG_DEV0_EPF7_2_LINK_CAP__PORT_NUMBER_MASK
159338. BIF_CFG_DEV0_EPF7_2_LINK_CAP__PORT_NUMBER__SHIFT
159339. BIF_CFG_DEV0_EPF7_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
159340. BIF_CFG_DEV0_EPF7_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
159341. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
159342. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
159343. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
159344. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
159345. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
159346. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
159347. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
159348. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
159349. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
159350. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
159351. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
159352. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
159353. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
159354. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
159355. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__XMIT_MARGIN_MASK
159356. BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
159357. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
159358. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
159359. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
159360. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
159361. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__EXTENDED_SYNC_MASK
159362. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
159363. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
159364. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
159365. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
159366. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
159367. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
159368. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
159369. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_DIS_MASK
159370. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_DIS__SHIFT
159371. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__PM_CONTROL_MASK
159372. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__PM_CONTROL__SHIFT
159373. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
159374. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
159375. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__RETRAIN_LINK_MASK
159376. BIF_CFG_DEV0_EPF7_2_LINK_CNTL__RETRAIN_LINK__SHIFT
159377. BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
159378. BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
159379. BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
159380. BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
159381. BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
159382. BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
159383. BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
159384. BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
159385. BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
159386. BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
159387. BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
159388. BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
159389. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
159390. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
159391. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__DL_ACTIVE_MASK
159392. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__DL_ACTIVE__SHIFT
159393. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
159394. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
159395. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
159396. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
159397. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_TRAINING_MASK
159398. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_TRAINING__SHIFT
159399. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
159400. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
159401. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
159402. BIF_CFG_DEV0_EPF7_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
159403. BIF_CFG_DEV0_EPF7_2_MAX_LATENCY__MAX_LAT_MASK
159404. BIF_CFG_DEV0_EPF7_2_MAX_LATENCY__MAX_LAT__SHIFT
159405. BIF_CFG_DEV0_EPF7_2_MIN_GRANT__MIN_GNT_MASK
159406. BIF_CFG_DEV0_EPF7_2_MIN_GRANT__MIN_GNT__SHIFT
159407. BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__CAP_ID_MASK
159408. BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__CAP_ID__SHIFT
159409. BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__NEXT_PTR_MASK
159410. BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT
159411. BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_EN_MASK
159412. BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT
159413. BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
159414. BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
159415. BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
159416. BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
159417. BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_BIR_MASK
159418. BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT
159419. BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK
159420. BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
159421. BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK
159422. BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
159423. BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
159424. BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
159425. BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__CAP_ID_MASK
159426. BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__CAP_ID__SHIFT
159427. BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__NEXT_PTR_MASK
159428. BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
159429. BIF_CFG_DEV0_EPF7_2_MSI_MASK_64__MSI_MASK_64_MASK
159430. BIF_CFG_DEV0_EPF7_2_MSI_MASK_64__MSI_MASK_64__SHIFT
159431. BIF_CFG_DEV0_EPF7_2_MSI_MASK__MSI_MASK_MASK
159432. BIF_CFG_DEV0_EPF7_2_MSI_MASK__MSI_MASK__SHIFT
159433. BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
159434. BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
159435. BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
159436. BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
159437. BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_64BIT_MASK
159438. BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
159439. BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_EN_MASK
159440. BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_EN__SHIFT
159441. BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
159442. BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
159443. BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
159444. BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
159445. BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
159446. BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
159447. BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
159448. BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
159449. BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA__MSI_DATA_MASK
159450. BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA__MSI_DATA__SHIFT
159451. BIF_CFG_DEV0_EPF7_2_MSI_PENDING_64__MSI_PENDING_64_MASK
159452. BIF_CFG_DEV0_EPF7_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT
159453. BIF_CFG_DEV0_EPF7_2_MSI_PENDING__MSI_PENDING_MASK
159454. BIF_CFG_DEV0_EPF7_2_MSI_PENDING__MSI_PENDING__SHIFT
159455. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
159456. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
159457. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
159458. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
159459. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
159460. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
159461. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
159462. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
159463. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
159464. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
159465. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
159466. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
159467. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
159468. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
159469. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
159470. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
159471. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
159472. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
159473. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
159474. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
159475. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
159476. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
159477. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
159478. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
159479. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
159480. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
159481. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
159482. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
159483. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
159484. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
159485. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
159486. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
159487. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
159488. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
159489. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
159490. BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
159491. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
159492. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
159493. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
159494. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
159495. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
159496. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
159497. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
159498. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
159499. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
159500. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
159501. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
159502. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
159503. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
159504. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
159505. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
159506. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
159507. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
159508. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
159509. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
159510. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
159511. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
159512. BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
159513. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
159514. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
159515. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
159516. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
159517. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
159518. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
159519. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
159520. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
159521. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
159522. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
159523. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
159524. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
159525. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
159526. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
159527. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
159528. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
159529. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
159530. BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
159531. BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
159532. BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
159533. BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK
159534. BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
159535. BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK
159536. BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
159537. BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
159538. BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
159539. BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
159540. BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
159541. BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK
159542. BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
159543. BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK
159544. BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
159545. BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
159546. BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
159547. BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
159548. BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
159549. BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK
159550. BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
159551. BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK
159552. BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
159553. BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
159554. BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
159555. BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
159556. BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
159557. BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK
159558. BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
159559. BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK
159560. BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
159561. BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
159562. BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
159563. BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
159564. BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
159565. BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK
159566. BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
159567. BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK
159568. BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
159569. BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
159570. BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
159571. BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
159572. BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
159573. BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK
159574. BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
159575. BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK
159576. BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
159577. BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
159578. BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
159579. BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
159580. BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
159581. BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
159582. BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
159583. BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
159584. BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
159585. BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__CAP_ID_MASK
159586. BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__CAP_ID__SHIFT
159587. BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__NEXT_PTR_MASK
159588. BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
159589. BIF_CFG_DEV0_EPF7_2_PCIE_CAP__DEVICE_TYPE_MASK
159590. BIF_CFG_DEV0_EPF7_2_PCIE_CAP__DEVICE_TYPE__SHIFT
159591. BIF_CFG_DEV0_EPF7_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
159592. BIF_CFG_DEV0_EPF7_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
159593. BIF_CFG_DEV0_EPF7_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
159594. BIF_CFG_DEV0_EPF7_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
159595. BIF_CFG_DEV0_EPF7_2_PCIE_CAP__VERSION_MASK
159596. BIF_CFG_DEV0_EPF7_2_PCIE_CAP__VERSION__SHIFT
159597. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
159598. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
159599. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
159600. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
159601. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
159602. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
159603. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
159604. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
159605. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
159606. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
159607. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
159608. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
159609. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
159610. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
159611. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
159612. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
159613. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
159614. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
159615. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
159616. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
159617. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
159618. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
159619. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
159620. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
159621. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
159622. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
159623. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
159624. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
159625. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
159626. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
159627. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
159628. BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
159629. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
159630. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
159631. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
159632. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
159633. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
159634. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
159635. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
159636. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
159637. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
159638. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
159639. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
159640. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
159641. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
159642. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
159643. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
159644. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
159645. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
159646. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
159647. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
159648. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
159649. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
159650. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
159651. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
159652. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
159653. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
159654. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
159655. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
159656. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
159657. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
159658. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
159659. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
159660. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
159661. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
159662. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
159663. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
159664. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
159665. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
159666. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
159667. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
159668. BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
159669. BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG0__TLP_HDR_MASK
159670. BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
159671. BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG1__TLP_HDR_MASK
159672. BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
159673. BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG2__TLP_HDR_MASK
159674. BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
159675. BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG3__TLP_HDR_MASK
159676. BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
159677. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
159678. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
159679. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
159680. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
159681. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
159682. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
159683. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
159684. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
159685. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
159686. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
159687. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
159688. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
159689. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
159690. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
159691. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK
159692. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
159693. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
159694. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
159695. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
159696. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
159697. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
159698. BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
159699. BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
159700. BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
159701. BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
159702. BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
159703. BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
159704. BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
159705. BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
159706. BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
159707. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
159708. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
159709. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
159710. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
159711. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
159712. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
159713. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
159714. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
159715. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
159716. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
159717. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
159718. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
159719. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
159720. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
159721. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
159722. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
159723. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
159724. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
159725. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
159726. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
159727. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
159728. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
159729. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
159730. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
159731. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
159732. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
159733. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
159734. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
159735. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
159736. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
159737. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
159738. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
159739. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
159740. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
159741. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
159742. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
159743. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
159744. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
159745. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
159746. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
159747. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
159748. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
159749. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
159750. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
159751. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
159752. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
159753. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
159754. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
159755. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
159756. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
159757. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
159758. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
159759. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
159760. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
159761. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
159762. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
159763. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
159764. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
159765. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
159766. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
159767. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
159768. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
159769. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
159770. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
159771. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
159772. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
159773. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
159774. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
159775. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
159776. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
159777. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
159778. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
159779. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
159780. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
159781. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
159782. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
159783. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
159784. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
159785. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
159786. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
159787. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
159788. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
159789. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
159790. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
159791. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
159792. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
159793. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
159794. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
159795. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
159796. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
159797. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
159798. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
159799. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
159800. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
159801. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
159802. BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
159803. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
159804. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
159805. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
159806. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
159807. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
159808. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
159809. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
159810. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
159811. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
159812. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
159813. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
159814. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
159815. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
159816. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
159817. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
159818. BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
159819. BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__CAP_ID_MASK
159820. BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__CAP_ID__SHIFT
159821. BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__NEXT_PTR_MASK
159822. BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
159823. BIF_CFG_DEV0_EPF7_2_PMI_CAP__AUX_CURRENT_MASK
159824. BIF_CFG_DEV0_EPF7_2_PMI_CAP__AUX_CURRENT__SHIFT
159825. BIF_CFG_DEV0_EPF7_2_PMI_CAP__D1_SUPPORT_MASK
159826. BIF_CFG_DEV0_EPF7_2_PMI_CAP__D1_SUPPORT__SHIFT
159827. BIF_CFG_DEV0_EPF7_2_PMI_CAP__D2_SUPPORT_MASK
159828. BIF_CFG_DEV0_EPF7_2_PMI_CAP__D2_SUPPORT__SHIFT
159829. BIF_CFG_DEV0_EPF7_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
159830. BIF_CFG_DEV0_EPF7_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
159831. BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_CLOCK_MASK
159832. BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_CLOCK__SHIFT
159833. BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_SUPPORT_MASK
159834. BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_SUPPORT__SHIFT
159835. BIF_CFG_DEV0_EPF7_2_PMI_CAP__VERSION_MASK
159836. BIF_CFG_DEV0_EPF7_2_PMI_CAP__VERSION__SHIFT
159837. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
159838. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
159839. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
159840. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
159841. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
159842. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
159843. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
159844. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
159845. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
159846. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
159847. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_EN_MASK
159848. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_EN__SHIFT
159849. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_STATUS_MASK
159850. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
159851. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PMI_DATA_MASK
159852. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
159853. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__POWER_STATE_MASK
159854. BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
159855. BIF_CFG_DEV0_EPF7_2_PROG_INTERFACE__PROG_INTERFACE_MASK
159856. BIF_CFG_DEV0_EPF7_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
159857. BIF_CFG_DEV0_EPF7_2_REVISION_ID__MAJOR_REV_ID_MASK
159858. BIF_CFG_DEV0_EPF7_2_REVISION_ID__MAJOR_REV_ID__SHIFT
159859. BIF_CFG_DEV0_EPF7_2_REVISION_ID__MINOR_REV_ID_MASK
159860. BIF_CFG_DEV0_EPF7_2_REVISION_ID__MINOR_REV_ID__SHIFT
159861. BIF_CFG_DEV0_EPF7_2_ROM_BASE_ADDR__BASE_ADDR_MASK
159862. BIF_CFG_DEV0_EPF7_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT
159863. BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__CAP_ID_MASK
159864. BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__CAP_ID__SHIFT
159865. BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__NEXT_PTR_MASK
159866. BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__NEXT_PTR__SHIFT
159867. BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
159868. BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
159869. BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
159870. BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
159871. BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
159872. BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
159873. BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
159874. BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
159875. BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
159876. BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
159877. BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
159878. BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
159879. BIF_CFG_DEV0_EPF7_2_SATA_IDP_DATA__IDP_DATA_MASK
159880. BIF_CFG_DEV0_EPF7_2_SATA_IDP_DATA__IDP_DATA__SHIFT
159881. BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_INDEX_MASK
159882. BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT
159883. BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK
159884. BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
159885. BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK
159886. BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
159887. BIF_CFG_DEV0_EPF7_2_SBRN__SBRN_MASK
159888. BIF_CFG_DEV0_EPF7_2_SBRN__SBRN__SHIFT
159889. BIF_CFG_DEV0_EPF7_2_SLOT_CAP2__RESERVED_MASK
159890. BIF_CFG_DEV0_EPF7_2_SLOT_CAP2__RESERVED__SHIFT
159891. BIF_CFG_DEV0_EPF7_2_SLOT_CNTL2__RESERVED_MASK
159892. BIF_CFG_DEV0_EPF7_2_SLOT_CNTL2__RESERVED__SHIFT
159893. BIF_CFG_DEV0_EPF7_2_SLOT_STATUS2__RESERVED_MASK
159894. BIF_CFG_DEV0_EPF7_2_SLOT_STATUS2__RESERVED__SHIFT
159895. BIF_CFG_DEV0_EPF7_2_STATUS__CAP_LIST_MASK
159896. BIF_CFG_DEV0_EPF7_2_STATUS__CAP_LIST__SHIFT
159897. BIF_CFG_DEV0_EPF7_2_STATUS__DEVSEL_TIMING_MASK
159898. BIF_CFG_DEV0_EPF7_2_STATUS__DEVSEL_TIMING__SHIFT
159899. BIF_CFG_DEV0_EPF7_2_STATUS__FAST_BACK_CAPABLE_MASK
159900. BIF_CFG_DEV0_EPF7_2_STATUS__FAST_BACK_CAPABLE__SHIFT
159901. BIF_CFG_DEV0_EPF7_2_STATUS__INT_STATUS_MASK
159902. BIF_CFG_DEV0_EPF7_2_STATUS__INT_STATUS__SHIFT
159903. BIF_CFG_DEV0_EPF7_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
159904. BIF_CFG_DEV0_EPF7_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
159905. BIF_CFG_DEV0_EPF7_2_STATUS__PARITY_ERROR_DETECTED_MASK
159906. BIF_CFG_DEV0_EPF7_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
159907. BIF_CFG_DEV0_EPF7_2_STATUS__PCI_66_EN_MASK
159908. BIF_CFG_DEV0_EPF7_2_STATUS__PCI_66_EN__SHIFT
159909. BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_MASTER_ABORT_MASK
159910. BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
159911. BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_TARGET_ABORT_MASK
159912. BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
159913. BIF_CFG_DEV0_EPF7_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
159914. BIF_CFG_DEV0_EPF7_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
159915. BIF_CFG_DEV0_EPF7_2_STATUS__SIGNAL_TARGET_ABORT_MASK
159916. BIF_CFG_DEV0_EPF7_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
159917. BIF_CFG_DEV0_EPF7_2_SUB_CLASS__SUB_CLASS_MASK
159918. BIF_CFG_DEV0_EPF7_2_SUB_CLASS__SUB_CLASS__SHIFT
159919. BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__CAP_ID_MASK
159920. BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__CAP_ID__SHIFT
159921. BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__LENGTH_MASK
159922. BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__LENGTH__SHIFT
159923. BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__NEXT_PTR_MASK
159924. BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
159925. BIF_CFG_DEV0_EPF7_2_VENDOR_ID__VENDOR_ID_MASK
159926. BIF_CFG_DEV0_EPF7_2_VENDOR_ID__VENDOR_ID__SHIFT
159927. BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK
159928. BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT
159929. BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK
159930. BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT
159931. BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK
159932. BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT
159933. BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK
159934. BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT
159935. BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK
159936. BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT
159937. BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK
159938. BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
159939. BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK
159940. BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT
159941. BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK
159942. BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT
159943. BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK
159944. BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT
159945. BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK
159946. BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT
159947. BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK
159948. BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT
159949. BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK
159950. BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT
159951. BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK
159952. BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT
159953. BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
159954. BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
159955. BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK
159956. BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT
159957. BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK
159958. BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
159959. BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK
159960. BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT
159961. BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK
159962. BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
159963. BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
159964. BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
159965. BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
159966. BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
159967. BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
159968. BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
159969. BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
159970. BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
159971. BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
159972. BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
159973. BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
159974. BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
159975. BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
159976. BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
159977. BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
159978. BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
159979. BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
159980. BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
159981. BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK
159982. BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
159983. BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
159984. BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
159985. BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
159986. BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
159987. BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
159988. BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
159989. BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
159990. BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
159991. BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
159992. BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
159993. BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
159994. BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
159995. BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK
159996. BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT
159997. BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK
159998. BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT
159999. BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
160000. BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
160001. BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
160002. BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
160003. BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
160004. BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
160005. BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK
160006. BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
160007. BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
160008. BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
160009. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
160010. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
160011. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
160012. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
160013. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
160014. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
160015. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
160016. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
160017. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
160018. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
160019. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
160020. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
160021. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
160022. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
160023. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
160024. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
160025. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK
160026. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT
160027. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK
160028. BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT
160029. BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
160030. BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
160031. BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
160032. BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
160033. BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK
160034. BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
160035. BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
160036. BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
160037. BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK
160038. BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
160039. BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
160040. BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
160041. BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
160042. BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
160043. BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
160044. BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
160045. BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK
160046. BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
160047. BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
160048. BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
160049. BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
160050. BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
160051. BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK
160052. BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
160053. BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK
160054. BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT
160055. BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK
160056. BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT
160057. BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK
160058. BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT
160059. BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK
160060. BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT
160061. BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK
160062. BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT
160063. BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK
160064. BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
160065. BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
160066. BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
160067. BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK
160068. BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT
160069. BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
160070. BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
160071. BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK
160072. BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT
160073. BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK
160074. BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT
160075. BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
160076. BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
160077. BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
160078. BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
160079. BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
160080. BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
160081. BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
160082. BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
160083. BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK
160084. BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
160085. BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
160086. BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT
160087. BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK
160088. BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
160089. BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
160090. BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT
160091. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
160092. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
160093. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK
160094. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
160095. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
160096. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
160097. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
160098. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
160099. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
160100. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
160101. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK
160102. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
160103. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
160104. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
160105. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK
160106. BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
160107. BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK
160108. BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT
160109. BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
160110. BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
160111. BIF_CFG_DEV0_RC0_LINK_CAP2__RESERVED_MASK
160112. BIF_CFG_DEV0_RC0_LINK_CAP2__RESERVED__SHIFT
160113. BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
160114. BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
160115. BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
160116. BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
160117. BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
160118. BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
160119. BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
160120. BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
160121. BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK
160122. BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
160123. BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK
160124. BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
160125. BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
160126. BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
160127. BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK
160128. BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT
160129. BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK
160130. BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT
160131. BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK
160132. BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT
160133. BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK
160134. BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT
160135. BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
160136. BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
160137. BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
160138. BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
160139. BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK
160140. BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
160141. BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
160142. BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
160143. BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
160144. BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
160145. BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
160146. BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
160147. BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
160148. BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
160149. BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
160150. BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
160151. BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK
160152. BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT
160153. BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
160154. BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
160155. BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
160156. BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
160157. BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK
160158. BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT
160159. BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
160160. BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
160161. BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
160162. BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
160163. BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
160164. BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
160165. BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK
160166. BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT
160167. BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK
160168. BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT
160169. BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
160170. BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
160171. BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK
160172. BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT
160173. BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
160174. BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
160175. BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
160176. BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
160177. BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
160178. BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
160179. BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
160180. BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
160181. BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
160182. BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
160183. BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
160184. BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
160185. BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
160186. BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
160187. BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK
160188. BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT
160189. BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
160190. BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
160191. BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
160192. BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
160193. BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK
160194. BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT
160195. BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
160196. BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
160197. BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
160198. BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
160199. BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
160200. BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
160201. BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
160202. BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
160203. BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
160204. BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
160205. BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
160206. BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
160207. BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK
160208. BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT
160209. BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK
160210. BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT
160211. BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
160212. BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
160213. BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
160214. BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
160215. BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK
160216. BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
160217. BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
160218. BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
160219. BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE_MASK
160220. BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT
160221. BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN_MASK
160222. BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN__SHIFT
160223. BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD_MASK
160224. BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD__SHIFT
160225. BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
160226. BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
160227. BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
160228. BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
160229. BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK
160230. BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
160231. BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK
160232. BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT
160233. BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
160234. BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
160235. BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
160236. BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
160237. BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
160238. BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
160239. BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
160240. BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
160241. BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK
160242. BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT
160243. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
160244. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
160245. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
160246. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
160247. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
160248. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
160249. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
160250. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
160251. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
160252. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
160253. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
160254. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
160255. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
160256. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
160257. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
160258. BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
160259. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
160260. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
160261. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
160262. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
160263. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
160264. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
160265. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
160266. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
160267. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
160268. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
160269. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
160270. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
160271. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
160272. BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
160273. BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
160274. BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
160275. BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
160276. BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
160277. BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
160278. BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
160279. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
160280. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
160281. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
160282. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
160283. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
160284. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
160285. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
160286. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
160287. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
160288. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
160289. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
160290. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
160291. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
160292. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
160293. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
160294. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
160295. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
160296. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
160297. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
160298. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
160299. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
160300. BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
160301. BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK
160302. BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT
160303. BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK
160304. BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
160305. BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK
160306. BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT
160307. BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK
160308. BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
160309. BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
160310. BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
160311. BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK
160312. BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT
160313. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
160314. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
160315. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
160316. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
160317. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
160318. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
160319. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
160320. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
160321. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
160322. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
160323. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
160324. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
160325. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
160326. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
160327. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
160328. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
160329. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
160330. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
160331. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
160332. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
160333. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
160334. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
160335. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
160336. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
160337. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
160338. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
160339. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
160340. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
160341. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
160342. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
160343. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
160344. BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
160345. BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
160346. BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
160347. BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
160348. BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
160349. BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
160350. BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
160351. BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
160352. BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
160353. BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
160354. BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
160355. BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
160356. BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
160357. BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
160358. BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
160359. BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK
160360. BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
160361. BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK
160362. BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
160363. BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK
160364. BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
160365. BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK
160366. BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
160367. BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160368. BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160369. BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160370. BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160371. BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
160372. BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
160373. BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160374. BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160375. BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160376. BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160377. BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160378. BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160379. BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160380. BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160381. BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
160382. BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
160383. BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160384. BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160385. BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160386. BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160387. BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160388. BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160389. BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160390. BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160391. BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
160392. BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
160393. BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160394. BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160395. BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160396. BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160397. BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160398. BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160399. BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160400. BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160401. BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
160402. BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
160403. BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160404. BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160405. BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160406. BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160407. BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160408. BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160409. BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160410. BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160411. BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
160412. BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
160413. BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160414. BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160415. BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160416. BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160417. BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160418. BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160419. BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160420. BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160421. BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
160422. BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
160423. BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160424. BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160425. BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160426. BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160427. BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160428. BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160429. BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160430. BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160431. BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
160432. BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
160433. BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160434. BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160435. BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160436. BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160437. BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160438. BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160439. BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160440. BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160441. BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
160442. BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
160443. BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160444. BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160445. BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160446. BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160447. BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160448. BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160449. BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160450. BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160451. BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
160452. BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
160453. BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160454. BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160455. BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160456. BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160457. BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160458. BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160459. BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160460. BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160461. BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
160462. BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
160463. BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160464. BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160465. BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160466. BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160467. BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160468. BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160469. BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160470. BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160471. BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
160472. BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
160473. BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160474. BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160475. BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160476. BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160477. BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160478. BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160479. BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160480. BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160481. BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
160482. BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
160483. BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160484. BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160485. BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160486. BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160487. BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160488. BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160489. BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160490. BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160491. BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
160492. BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
160493. BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160494. BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160495. BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160496. BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160497. BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160498. BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160499. BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160500. BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160501. BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
160502. BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
160503. BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160504. BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160505. BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160506. BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160507. BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160508. BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160509. BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160510. BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160511. BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
160512. BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
160513. BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160514. BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160515. BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160516. BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160517. BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
160518. BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
160519. BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
160520. BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
160521. BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
160522. BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
160523. BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
160524. BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
160525. BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
160526. BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
160527. BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
160528. BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
160529. BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
160530. BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
160531. BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
160532. BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
160533. BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
160534. BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
160535. BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__RESERVED_MASK
160536. BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__RESERVED__SHIFT
160537. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
160538. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
160539. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
160540. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
160541. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
160542. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
160543. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
160544. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
160545. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
160546. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
160547. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
160548. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
160549. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
160550. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
160551. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
160552. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
160553. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
160554. BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
160555. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
160556. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
160557. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
160558. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
160559. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
160560. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
160561. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
160562. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
160563. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
160564. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
160565. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
160566. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
160567. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
160568. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
160569. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
160570. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
160571. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
160572. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
160573. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
160574. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
160575. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
160576. BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
160577. BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
160578. BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
160579. BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
160580. BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
160581. BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
160582. BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
160583. BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
160584. BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
160585. BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
160586. BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
160587. BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
160588. BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
160589. BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
160590. BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
160591. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
160592. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
160593. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
160594. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
160595. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
160596. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
160597. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
160598. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
160599. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
160600. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
160601. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
160602. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
160603. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
160604. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
160605. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
160606. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
160607. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
160608. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
160609. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
160610. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
160611. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
160612. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
160613. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
160614. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
160615. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
160616. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
160617. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
160618. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
160619. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
160620. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
160621. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
160622. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
160623. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
160624. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
160625. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
160626. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
160627. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
160628. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
160629. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
160630. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
160631. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
160632. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
160633. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
160634. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
160635. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
160636. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
160637. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
160638. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
160639. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
160640. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
160641. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
160642. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
160643. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
160644. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
160645. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
160646. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
160647. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
160648. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
160649. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
160650. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
160651. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
160652. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
160653. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
160654. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
160655. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
160656. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
160657. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
160658. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
160659. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
160660. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
160661. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
160662. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
160663. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
160664. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
160665. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
160666. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
160667. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
160668. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
160669. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
160670. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
160671. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
160672. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
160673. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
160674. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
160675. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
160676. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
160677. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
160678. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
160679. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
160680. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
160681. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
160682. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
160683. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
160684. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
160685. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
160686. BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
160687. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
160688. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
160689. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
160690. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
160691. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
160692. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
160693. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
160694. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
160695. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
160696. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
160697. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
160698. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
160699. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
160700. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
160701. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
160702. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
160703. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
160704. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
160705. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
160706. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
160707. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
160708. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
160709. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
160710. BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
160711. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
160712. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
160713. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
160714. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
160715. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
160716. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
160717. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
160718. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
160719. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
160720. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
160721. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
160722. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
160723. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
160724. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
160725. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
160726. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
160727. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
160728. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
160729. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
160730. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
160731. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
160732. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
160733. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
160734. BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
160735. BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
160736. BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
160737. BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
160738. BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
160739. BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
160740. BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
160741. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
160742. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
160743. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
160744. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
160745. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
160746. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
160747. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
160748. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
160749. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
160750. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
160751. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
160752. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
160753. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
160754. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
160755. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
160756. BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
160757. BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK
160758. BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT
160759. BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK
160760. BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT
160761. BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK
160762. BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT
160763. BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK
160764. BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT
160765. BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK
160766. BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT
160767. BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
160768. BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
160769. BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK
160770. BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT
160771. BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK
160772. BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT
160773. BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK
160774. BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT
160775. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
160776. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
160777. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
160778. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
160779. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK
160780. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
160781. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK
160782. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
160783. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
160784. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
160785. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK
160786. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT
160787. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK
160788. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
160789. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK
160790. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
160791. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK
160792. BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
160793. BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
160794. BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
160795. BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
160796. BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
160797. BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
160798. BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
160799. BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
160800. BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
160801. BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
160802. BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
160803. BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
160804. BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
160805. BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK
160806. BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
160807. BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK
160808. BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT
160809. BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK
160810. BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT
160811. BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
160812. BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
160813. BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
160814. BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
160815. BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK
160816. BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
160817. BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
160818. BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
160819. BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
160820. BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
160821. BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
160822. BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
160823. BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK
160824. BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT
160825. BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK
160826. BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
160827. BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK
160828. BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT
160829. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__CAP_LIST_MASK
160830. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__CAP_LIST__SHIFT
160831. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK
160832. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
160833. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
160834. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
160835. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
160836. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
160837. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
160838. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
160839. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_EN_MASK
160840. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_EN__SHIFT
160841. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
160842. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
160843. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
160844. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
160845. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
160846. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
160847. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
160848. BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
160849. BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED_MASK
160850. BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED__SHIFT
160851. BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
160852. BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
160853. BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
160854. BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
160855. BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
160856. BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
160857. BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK
160858. BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
160859. BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK
160860. BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
160861. BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
160862. BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
160863. BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
160864. BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
160865. BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
160866. BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
160867. BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
160868. BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
160869. BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
160870. BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
160871. BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
160872. BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
160873. BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
160874. BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
160875. BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK
160876. BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT
160877. BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
160878. BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
160879. BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
160880. BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
160881. BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
160882. BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
160883. BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
160884. BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
160885. BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
160886. BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
160887. BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
160888. BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
160889. BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
160890. BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
160891. BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
160892. BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
160893. BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
160894. BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
160895. BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
160896. BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
160897. BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
160898. BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
160899. BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK
160900. BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT
160901. BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
160902. BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
160903. BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK
160904. BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
160905. BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK
160906. BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
160907. BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
160908. BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
160909. BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
160910. BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
160911. BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK
160912. BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
160913. BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
160914. BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
160915. BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
160916. BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
160917. BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
160918. BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
160919. BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK
160920. BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT
160921. BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK
160922. BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT
160923. BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK
160924. BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT
160925. BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
160926. BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
160927. BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK
160928. BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT
160929. BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK
160930. BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT
160931. BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK
160932. BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT
160933. BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK
160934. BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT
160935. BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
160936. BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
160937. BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK
160938. BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT
160939. BIF_CFG_DEV0_RC0_STATUS__PCI_66_EN_MASK
160940. BIF_CFG_DEV0_RC0_STATUS__PCI_66_EN__SHIFT
160941. BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK
160942. BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
160943. BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK
160944. BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
160945. BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
160946. BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
160947. BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK
160948. BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
160949. BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
160950. BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
160951. BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
160952. BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
160953. BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
160954. BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
160955. BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
160956. BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
160957. BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK
160958. BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT
160959. BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK
160960. BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT
160961. BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR_MASK
160962. BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT
160963. BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS_MASK
160964. BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS__SHIFT
160965. BIF_CFG_DEV0_RC1_BIST__BIST_CAP_MASK
160966. BIF_CFG_DEV0_RC1_BIST__BIST_CAP__SHIFT
160967. BIF_CFG_DEV0_RC1_BIST__BIST_COMP_MASK
160968. BIF_CFG_DEV0_RC1_BIST__BIST_COMP__SHIFT
160969. BIF_CFG_DEV0_RC1_BIST__BIST_STRT_MASK
160970. BIF_CFG_DEV0_RC1_BIST__BIST_STRT__SHIFT
160971. BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK
160972. BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
160973. BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR_MASK
160974. BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR__SHIFT
160975. BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING_MASK
160976. BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING__SHIFT
160977. BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN_MASK
160978. BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN__SHIFT
160979. BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN_MASK
160980. BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN__SHIFT
160981. BIF_CFG_DEV0_RC1_COMMAND__INT_DIS_MASK
160982. BIF_CFG_DEV0_RC1_COMMAND__INT_DIS__SHIFT
160983. BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN_MASK
160984. BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN__SHIFT
160985. BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN_MASK
160986. BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN__SHIFT
160987. BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
160988. BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
160989. BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN_MASK
160990. BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN__SHIFT
160991. BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK
160992. BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
160993. BIF_CFG_DEV0_RC1_COMMAND__SERR_EN_MASK
160994. BIF_CFG_DEV0_RC1_COMMAND__SERR_EN__SHIFT
160995. BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK
160996. BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
160997. BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
160998. BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
160999. BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
161000. BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
161001. BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
161002. BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
161003. BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
161004. BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
161005. BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
161006. BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
161007. BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
161008. BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
161009. BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
161010. BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
161011. BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
161012. BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
161013. BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
161014. BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
161015. BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK
161016. BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
161017. BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
161018. BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
161019. BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
161020. BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
161021. BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
161022. BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
161023. BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
161024. BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
161025. BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
161026. BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
161027. BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
161028. BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
161029. BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG_MASK
161030. BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT
161031. BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE_MASK
161032. BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT
161033. BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
161034. BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
161035. BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
161036. BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
161037. BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
161038. BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
161039. BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK
161040. BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
161041. BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
161042. BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
161043. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
161044. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
161045. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
161046. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
161047. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
161048. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
161049. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
161050. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
161051. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
161052. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
161053. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
161054. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
161055. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
161056. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
161057. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
161058. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
161059. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN_MASK
161060. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN__SHIFT
161061. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN_MASK
161062. BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT
161063. BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
161064. BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
161065. BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
161066. BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
161067. BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK
161068. BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
161069. BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
161070. BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
161071. BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK
161072. BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
161073. BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
161074. BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
161075. BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
161076. BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
161077. BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
161078. BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
161079. BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK
161080. BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
161081. BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
161082. BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
161083. BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
161084. BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
161085. BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK
161086. BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
161087. BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID_MASK
161088. BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID__SHIFT
161089. BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED_MASK
161090. BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED__SHIFT
161091. BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR_MASK
161092. BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR__SHIFT
161093. BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR_MASK
161094. BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR__SHIFT
161095. BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR_MASK
161096. BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT
161097. BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK
161098. BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
161099. BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
161100. BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
161101. BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED_MASK
161102. BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT
161103. BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
161104. BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
161105. BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE_MASK
161106. BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE__SHIFT
161107. BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE_MASK
161108. BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE__SHIFT
161109. BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
161110. BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
161111. BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
161112. BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
161113. BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
161114. BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
161115. BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
161116. BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
161117. BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_MASK
161118. BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
161119. BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
161120. BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT
161121. BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK
161122. BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
161123. BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
161124. BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT
161125. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
161126. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
161127. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK
161128. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
161129. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
161130. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
161131. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
161132. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
161133. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
161134. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
161135. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK
161136. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
161137. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
161138. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
161139. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK
161140. BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
161141. BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER_MASK
161142. BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER__SHIFT
161143. BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
161144. BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
161145. BIF_CFG_DEV0_RC1_LINK_CAP2__RESERVED_MASK
161146. BIF_CFG_DEV0_RC1_LINK_CAP2__RESERVED__SHIFT
161147. BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
161148. BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
161149. BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
161150. BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
161151. BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
161152. BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
161153. BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
161154. BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
161155. BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK
161156. BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
161157. BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK
161158. BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
161159. BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
161160. BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
161161. BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED_MASK
161162. BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED__SHIFT
161163. BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH_MASK
161164. BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH__SHIFT
161165. BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT_MASK
161166. BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT__SHIFT
161167. BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER_MASK
161168. BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER__SHIFT
161169. BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
161170. BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
161171. BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
161172. BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
161173. BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK
161174. BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
161175. BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
161176. BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
161177. BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
161178. BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
161179. BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
161180. BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
161181. BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
161182. BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
161183. BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
161184. BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
161185. BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN_MASK
161186. BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT
161187. BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
161188. BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
161189. BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
161190. BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
161191. BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC_MASK
161192. BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT
161193. BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
161194. BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
161195. BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
161196. BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
161197. BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
161198. BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
161199. BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS_MASK
161200. BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS__SHIFT
161201. BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL_MASK
161202. BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL__SHIFT
161203. BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
161204. BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
161205. BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK_MASK
161206. BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT
161207. BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
161208. BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
161209. BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
161210. BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
161211. BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
161212. BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
161213. BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
161214. BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
161215. BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
161216. BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
161217. BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
161218. BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
161219. BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
161220. BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
161221. BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE_MASK
161222. BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE__SHIFT
161223. BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
161224. BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
161225. BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
161226. BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
161227. BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING_MASK
161228. BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING__SHIFT
161229. BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
161230. BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
161231. BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
161232. BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
161233. BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
161234. BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
161235. BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
161236. BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
161237. BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
161238. BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
161239. BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
161240. BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
161241. BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID_MASK
161242. BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID__SHIFT
161243. BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR_MASK
161244. BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT
161245. BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
161246. BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
161247. BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
161248. BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
161249. BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK
161250. BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
161251. BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
161252. BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
161253. BIF_CFG_DEV0_RC1_MSI_MAP_CAP__CAP_TYPE_MASK
161254. BIF_CFG_DEV0_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT
161255. BIF_CFG_DEV0_RC1_MSI_MAP_CAP__EN_MASK
161256. BIF_CFG_DEV0_RC1_MSI_MAP_CAP__EN__SHIFT
161257. BIF_CFG_DEV0_RC1_MSI_MAP_CAP__FIXD_MASK
161258. BIF_CFG_DEV0_RC1_MSI_MAP_CAP__FIXD__SHIFT
161259. BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
161260. BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
161261. BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
161262. BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
161263. BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK
161264. BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
161265. BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN_MASK
161266. BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT
161267. BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
161268. BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
161269. BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
161270. BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
161271. BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
161272. BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
161273. BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
161274. BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
161275. BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA_MASK
161276. BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT
161277. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
161278. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
161279. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
161280. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
161281. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
161282. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
161283. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
161284. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
161285. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
161286. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
161287. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
161288. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
161289. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
161290. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
161291. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
161292. BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
161293. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
161294. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
161295. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
161296. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
161297. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
161298. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
161299. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
161300. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
161301. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
161302. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
161303. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
161304. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
161305. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
161306. BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
161307. BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
161308. BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
161309. BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
161310. BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
161311. BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
161312. BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
161313. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
161314. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
161315. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
161316. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
161317. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
161318. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
161319. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
161320. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
161321. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
161322. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
161323. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
161324. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
161325. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
161326. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
161327. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
161328. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
161329. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
161330. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
161331. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
161332. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
161333. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
161334. BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
161335. BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID_MASK
161336. BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT
161337. BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK
161338. BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
161339. BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE_MASK
161340. BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT
161341. BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK
161342. BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
161343. BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
161344. BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
161345. BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION_MASK
161346. BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION__SHIFT
161347. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
161348. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
161349. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
161350. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
161351. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
161352. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
161353. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
161354. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
161355. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
161356. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
161357. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
161358. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
161359. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
161360. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
161361. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
161362. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
161363. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
161364. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
161365. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
161366. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
161367. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
161368. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
161369. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
161370. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
161371. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
161372. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
161373. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
161374. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
161375. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
161376. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
161377. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
161378. BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
161379. BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
161380. BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
161381. BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
161382. BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
161383. BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
161384. BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
161385. BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
161386. BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
161387. BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
161388. BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
161389. BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
161390. BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
161391. BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
161392. BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
161393. BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK
161394. BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
161395. BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK
161396. BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
161397. BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK
161398. BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
161399. BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK
161400. BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
161401. BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161402. BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161403. BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161404. BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161405. BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
161406. BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
161407. BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161408. BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161409. BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161410. BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161411. BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161412. BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161413. BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161414. BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161415. BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
161416. BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
161417. BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161418. BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161419. BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161420. BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161421. BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161422. BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161423. BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161424. BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161425. BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
161426. BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
161427. BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161428. BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161429. BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161430. BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161431. BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161432. BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161433. BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161434. BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161435. BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
161436. BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
161437. BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161438. BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161439. BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161440. BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161441. BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161442. BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161443. BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161444. BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161445. BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
161446. BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
161447. BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161448. BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161449. BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161450. BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161451. BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161452. BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161453. BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161454. BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161455. BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
161456. BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
161457. BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161458. BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161459. BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161460. BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161461. BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161462. BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161463. BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161464. BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161465. BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
161466. BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
161467. BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161468. BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161469. BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161470. BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161471. BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161472. BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161473. BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161474. BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161475. BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
161476. BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
161477. BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161478. BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161479. BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161480. BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161481. BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161482. BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161483. BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161484. BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161485. BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
161486. BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
161487. BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161488. BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161489. BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161490. BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161491. BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161492. BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161493. BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161494. BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161495. BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
161496. BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
161497. BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161498. BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161499. BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161500. BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161501. BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161502. BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161503. BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161504. BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161505. BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
161506. BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
161507. BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161508. BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161509. BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161510. BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161511. BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161512. BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161513. BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161514. BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161515. BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
161516. BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
161517. BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161518. BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161519. BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161520. BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161521. BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161522. BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161523. BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161524. BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161525. BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
161526. BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
161527. BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161528. BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161529. BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161530. BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161531. BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161532. BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161533. BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161534. BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161535. BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
161536. BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
161537. BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161538. BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161539. BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161540. BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161541. BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161542. BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161543. BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161544. BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161545. BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
161546. BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
161547. BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161548. BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161549. BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161550. BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161551. BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
161552. BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
161553. BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
161554. BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
161555. BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
161556. BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
161557. BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
161558. BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
161559. BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
161560. BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
161561. BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
161562. BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
161563. BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
161564. BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
161565. BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
161566. BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
161567. BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
161568. BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
161569. BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__RESERVED_MASK
161570. BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__RESERVED__SHIFT
161571. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
161572. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
161573. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
161574. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
161575. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
161576. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
161577. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
161578. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
161579. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
161580. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
161581. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
161582. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
161583. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
161584. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
161585. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
161586. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
161587. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
161588. BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
161589. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
161590. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
161591. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
161592. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
161593. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
161594. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
161595. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
161596. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
161597. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
161598. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
161599. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
161600. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
161601. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
161602. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
161603. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
161604. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
161605. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
161606. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
161607. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
161608. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
161609. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
161610. BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
161611. BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
161612. BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
161613. BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
161614. BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
161615. BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
161616. BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
161617. BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
161618. BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
161619. BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
161620. BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
161621. BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
161622. BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
161623. BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
161624. BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
161625. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
161626. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
161627. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
161628. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
161629. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
161630. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
161631. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
161632. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
161633. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
161634. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
161635. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
161636. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
161637. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
161638. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
161639. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
161640. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
161641. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
161642. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
161643. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
161644. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
161645. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
161646. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
161647. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
161648. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
161649. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
161650. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
161651. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
161652. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
161653. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
161654. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
161655. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
161656. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
161657. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
161658. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
161659. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
161660. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
161661. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
161662. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
161663. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
161664. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
161665. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
161666. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
161667. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
161668. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
161669. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
161670. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
161671. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
161672. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
161673. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
161674. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
161675. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
161676. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
161677. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
161678. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
161679. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
161680. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
161681. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
161682. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
161683. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
161684. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
161685. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
161686. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
161687. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
161688. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
161689. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
161690. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
161691. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
161692. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
161693. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
161694. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
161695. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
161696. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
161697. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
161698. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
161699. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
161700. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
161701. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
161702. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
161703. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
161704. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
161705. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
161706. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
161707. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
161708. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
161709. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
161710. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
161711. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
161712. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
161713. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
161714. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
161715. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
161716. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
161717. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
161718. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
161719. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
161720. BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
161721. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
161722. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
161723. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
161724. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
161725. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
161726. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
161727. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
161728. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
161729. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
161730. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
161731. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
161732. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
161733. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
161734. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
161735. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
161736. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
161737. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
161738. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
161739. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
161740. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
161741. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
161742. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
161743. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
161744. BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
161745. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
161746. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
161747. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
161748. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
161749. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
161750. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
161751. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
161752. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
161753. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
161754. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
161755. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
161756. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
161757. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
161758. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
161759. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
161760. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
161761. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
161762. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
161763. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
161764. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
161765. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
161766. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
161767. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
161768. BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
161769. BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
161770. BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
161771. BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
161772. BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
161773. BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
161774. BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
161775. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
161776. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
161777. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
161778. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
161779. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
161780. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
161781. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
161782. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
161783. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
161784. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
161785. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
161786. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
161787. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
161788. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
161789. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
161790. BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
161791. BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID_MASK
161792. BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID__SHIFT
161793. BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR_MASK
161794. BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT
161795. BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT_MASK
161796. BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT__SHIFT
161797. BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT_MASK
161798. BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT__SHIFT
161799. BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT_MASK
161800. BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT__SHIFT
161801. BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
161802. BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
161803. BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK_MASK
161804. BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK__SHIFT
161805. BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT_MASK
161806. BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT__SHIFT
161807. BIF_CFG_DEV0_RC1_PMI_CAP__VERSION_MASK
161808. BIF_CFG_DEV0_RC1_PMI_CAP__VERSION__SHIFT
161809. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
161810. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
161811. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
161812. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
161813. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK
161814. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
161815. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK
161816. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
161817. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
161818. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
161819. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN_MASK
161820. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT
161821. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK
161822. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
161823. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK
161824. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
161825. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK
161826. BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
161827. BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
161828. BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
161829. BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
161830. BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
161831. BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
161832. BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
161833. BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
161834. BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
161835. BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
161836. BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
161837. BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
161838. BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
161839. BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK
161840. BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
161841. BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID_MASK
161842. BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT
161843. BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID_MASK
161844. BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID__SHIFT
161845. BIF_CFG_DEV0_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
161846. BIF_CFG_DEV0_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
161847. BIF_CFG_DEV0_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
161848. BIF_CFG_DEV0_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
161849. BIF_CFG_DEV0_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK
161850. BIF_CFG_DEV0_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
161851. BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
161852. BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
161853. BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
161854. BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
161855. BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
161856. BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
161857. BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_PENDING_MASK
161858. BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_PENDING__SHIFT
161859. BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK
161860. BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
161861. BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_STATUS_MASK
161862. BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_STATUS__SHIFT
161863. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__CAP_LIST_MASK
161864. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__CAP_LIST__SHIFT
161865. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK
161866. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
161867. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
161868. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
161869. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
161870. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
161871. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
161872. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
161873. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_EN_MASK
161874. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_EN__SHIFT
161875. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
161876. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
161877. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
161878. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
161879. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
161880. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
161881. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
161882. BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
161883. BIF_CFG_DEV0_RC1_SLOT_CAP2__RESERVED_MASK
161884. BIF_CFG_DEV0_RC1_SLOT_CAP2__RESERVED__SHIFT
161885. BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
161886. BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
161887. BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
161888. BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
161889. BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
161890. BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
161891. BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK
161892. BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
161893. BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK
161894. BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
161895. BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
161896. BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
161897. BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
161898. BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
161899. BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
161900. BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
161901. BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
161902. BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
161903. BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
161904. BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
161905. BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
161906. BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
161907. BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
161908. BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
161909. BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED_MASK
161910. BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED__SHIFT
161911. BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
161912. BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
161913. BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
161914. BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
161915. BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
161916. BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
161917. BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
161918. BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
161919. BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
161920. BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
161921. BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
161922. BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
161923. BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
161924. BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
161925. BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
161926. BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
161927. BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
161928. BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
161929. BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
161930. BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
161931. BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
161932. BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
161933. BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED_MASK
161934. BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED__SHIFT
161935. BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
161936. BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
161937. BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK
161938. BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
161939. BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK
161940. BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
161941. BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
161942. BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
161943. BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
161944. BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
161945. BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK
161946. BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
161947. BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
161948. BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
161949. BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
161950. BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
161951. BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
161952. BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
161953. BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID_MASK
161954. BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID__SHIFT
161955. BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR_MASK
161956. BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT
161957. BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID_MASK
161958. BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT
161959. BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
161960. BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
161961. BIF_CFG_DEV0_RC1_STATUS__CAP_LIST_MASK
161962. BIF_CFG_DEV0_RC1_STATUS__CAP_LIST__SHIFT
161963. BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING_MASK
161964. BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING__SHIFT
161965. BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE_MASK
161966. BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT
161967. BIF_CFG_DEV0_RC1_STATUS__INT_STATUS_MASK
161968. BIF_CFG_DEV0_RC1_STATUS__INT_STATUS__SHIFT
161969. BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
161970. BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
161971. BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED_MASK
161972. BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT
161973. BIF_CFG_DEV0_RC1_STATUS__PCI_66_EN_MASK
161974. BIF_CFG_DEV0_RC1_STATUS__PCI_66_EN__SHIFT
161975. BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK
161976. BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
161977. BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK
161978. BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
161979. BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
161980. BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
161981. BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK
161982. BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
161983. BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
161984. BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
161985. BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
161986. BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
161987. BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
161988. BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
161989. BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
161990. BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
161991. BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS_MASK
161992. BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS__SHIFT
161993. BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID_MASK
161994. BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID__SHIFT
161995. BIF_CFG_DEV0_RC2_BASE_ADDR_1__BASE_ADDR_MASK
161996. BIF_CFG_DEV0_RC2_BASE_ADDR_1__BASE_ADDR__SHIFT
161997. BIF_CFG_DEV0_RC2_BASE_CLASS__BASE_CLASS_MASK
161998. BIF_CFG_DEV0_RC2_BASE_CLASS__BASE_CLASS__SHIFT
161999. BIF_CFG_DEV0_RC2_BIST__BIST_CAP_MASK
162000. BIF_CFG_DEV0_RC2_BIST__BIST_CAP__SHIFT
162001. BIF_CFG_DEV0_RC2_BIST__BIST_COMP_MASK
162002. BIF_CFG_DEV0_RC2_BIST__BIST_COMP__SHIFT
162003. BIF_CFG_DEV0_RC2_BIST__BIST_STRT_MASK
162004. BIF_CFG_DEV0_RC2_BIST__BIST_STRT__SHIFT
162005. BIF_CFG_DEV0_RC2_CACHE_LINE__CACHE_LINE_SIZE_MASK
162006. BIF_CFG_DEV0_RC2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
162007. BIF_CFG_DEV0_RC2_CAP_PTR__CAP_PTR_MASK
162008. BIF_CFG_DEV0_RC2_CAP_PTR__CAP_PTR__SHIFT
162009. BIF_CFG_DEV0_RC2_COMMAND__AD_STEPPING_MASK
162010. BIF_CFG_DEV0_RC2_COMMAND__AD_STEPPING__SHIFT
162011. BIF_CFG_DEV0_RC2_COMMAND__BUS_MASTER_EN_MASK
162012. BIF_CFG_DEV0_RC2_COMMAND__BUS_MASTER_EN__SHIFT
162013. BIF_CFG_DEV0_RC2_COMMAND__FAST_B2B_EN_MASK
162014. BIF_CFG_DEV0_RC2_COMMAND__FAST_B2B_EN__SHIFT
162015. BIF_CFG_DEV0_RC2_COMMAND__INT_DIS_MASK
162016. BIF_CFG_DEV0_RC2_COMMAND__INT_DIS__SHIFT
162017. BIF_CFG_DEV0_RC2_COMMAND__IOEN_DN_MASK
162018. BIF_CFG_DEV0_RC2_COMMAND__IOEN_DN__SHIFT
162019. BIF_CFG_DEV0_RC2_COMMAND__MEMEN_DN_MASK
162020. BIF_CFG_DEV0_RC2_COMMAND__MEMEN_DN__SHIFT
162021. BIF_CFG_DEV0_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
162022. BIF_CFG_DEV0_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
162023. BIF_CFG_DEV0_RC2_COMMAND__PAL_SNOOP_EN_MASK
162024. BIF_CFG_DEV0_RC2_COMMAND__PAL_SNOOP_EN__SHIFT
162025. BIF_CFG_DEV0_RC2_COMMAND__PARITY_ERROR_RESPONSE_MASK
162026. BIF_CFG_DEV0_RC2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
162027. BIF_CFG_DEV0_RC2_COMMAND__SERR_EN_MASK
162028. BIF_CFG_DEV0_RC2_COMMAND__SERR_EN__SHIFT
162029. BIF_CFG_DEV0_RC2_COMMAND__SPECIAL_CYCLE_EN_MASK
162030. BIF_CFG_DEV0_RC2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
162031. BIF_CFG_DEV0_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
162032. BIF_CFG_DEV0_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
162033. BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
162034. BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
162035. BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
162036. BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
162037. BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
162038. BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
162039. BIF_CFG_DEV0_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
162040. BIF_CFG_DEV0_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
162041. BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
162042. BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
162043. BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
162044. BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
162045. BIF_CFG_DEV0_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
162046. BIF_CFG_DEV0_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
162047. BIF_CFG_DEV0_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
162048. BIF_CFG_DEV0_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
162049. BIF_CFG_DEV0_RC2_DEVICE_CAP2__LTR_SUPPORTED_MASK
162050. BIF_CFG_DEV0_RC2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
162051. BIF_CFG_DEV0_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
162052. BIF_CFG_DEV0_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
162053. BIF_CFG_DEV0_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
162054. BIF_CFG_DEV0_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
162055. BIF_CFG_DEV0_RC2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
162056. BIF_CFG_DEV0_RC2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
162057. BIF_CFG_DEV0_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
162058. BIF_CFG_DEV0_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
162059. BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
162060. BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
162061. BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
162062. BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
162063. BIF_CFG_DEV0_RC2_DEVICE_CAP__EXTENDED_TAG_MASK
162064. BIF_CFG_DEV0_RC2_DEVICE_CAP__EXTENDED_TAG__SHIFT
162065. BIF_CFG_DEV0_RC2_DEVICE_CAP__FLR_CAPABLE_MASK
162066. BIF_CFG_DEV0_RC2_DEVICE_CAP__FLR_CAPABLE__SHIFT
162067. BIF_CFG_DEV0_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
162068. BIF_CFG_DEV0_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
162069. BIF_CFG_DEV0_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
162070. BIF_CFG_DEV0_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
162071. BIF_CFG_DEV0_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
162072. BIF_CFG_DEV0_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
162073. BIF_CFG_DEV0_RC2_DEVICE_CAP__PHANTOM_FUNC_MASK
162074. BIF_CFG_DEV0_RC2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
162075. BIF_CFG_DEV0_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
162076. BIF_CFG_DEV0_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
162077. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
162078. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
162079. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
162080. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
162081. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
162082. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
162083. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
162084. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
162085. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
162086. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
162087. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
162088. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
162089. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
162090. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
162091. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
162092. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
162093. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__LTR_EN_MASK
162094. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__LTR_EN__SHIFT
162095. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__OBFF_EN_MASK
162096. BIF_CFG_DEV0_RC2_DEVICE_CNTL2__OBFF_EN__SHIFT
162097. BIF_CFG_DEV0_RC2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
162098. BIF_CFG_DEV0_RC2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
162099. BIF_CFG_DEV0_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
162100. BIF_CFG_DEV0_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
162101. BIF_CFG_DEV0_RC2_DEVICE_CNTL__CORR_ERR_EN_MASK
162102. BIF_CFG_DEV0_RC2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
162103. BIF_CFG_DEV0_RC2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
162104. BIF_CFG_DEV0_RC2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
162105. BIF_CFG_DEV0_RC2_DEVICE_CNTL__FATAL_ERR_EN_MASK
162106. BIF_CFG_DEV0_RC2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
162107. BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
162108. BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
162109. BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
162110. BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
162111. BIF_CFG_DEV0_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
162112. BIF_CFG_DEV0_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
162113. BIF_CFG_DEV0_RC2_DEVICE_CNTL__NO_SNOOP_EN_MASK
162114. BIF_CFG_DEV0_RC2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
162115. BIF_CFG_DEV0_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
162116. BIF_CFG_DEV0_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
162117. BIF_CFG_DEV0_RC2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
162118. BIF_CFG_DEV0_RC2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
162119. BIF_CFG_DEV0_RC2_DEVICE_CNTL__USR_REPORT_EN_MASK
162120. BIF_CFG_DEV0_RC2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
162121. BIF_CFG_DEV0_RC2_DEVICE_ID__DEVICE_ID_MASK
162122. BIF_CFG_DEV0_RC2_DEVICE_ID__DEVICE_ID__SHIFT
162123. BIF_CFG_DEV0_RC2_DEVICE_STATUS2__RESERVED_MASK
162124. BIF_CFG_DEV0_RC2_DEVICE_STATUS2__RESERVED__SHIFT
162125. BIF_CFG_DEV0_RC2_DEVICE_STATUS__AUX_PWR_MASK
162126. BIF_CFG_DEV0_RC2_DEVICE_STATUS__AUX_PWR__SHIFT
162127. BIF_CFG_DEV0_RC2_DEVICE_STATUS__CORR_ERR_MASK
162128. BIF_CFG_DEV0_RC2_DEVICE_STATUS__CORR_ERR__SHIFT
162129. BIF_CFG_DEV0_RC2_DEVICE_STATUS__FATAL_ERR_MASK
162130. BIF_CFG_DEV0_RC2_DEVICE_STATUS__FATAL_ERR__SHIFT
162131. BIF_CFG_DEV0_RC2_DEVICE_STATUS__NON_FATAL_ERR_MASK
162132. BIF_CFG_DEV0_RC2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
162133. BIF_CFG_DEV0_RC2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
162134. BIF_CFG_DEV0_RC2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
162135. BIF_CFG_DEV0_RC2_DEVICE_STATUS__USR_DETECTED_MASK
162136. BIF_CFG_DEV0_RC2_DEVICE_STATUS__USR_DETECTED__SHIFT
162137. BIF_CFG_DEV0_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
162138. BIF_CFG_DEV0_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
162139. BIF_CFG_DEV0_RC2_HEADER__DEVICE_TYPE_MASK
162140. BIF_CFG_DEV0_RC2_HEADER__DEVICE_TYPE__SHIFT
162141. BIF_CFG_DEV0_RC2_HEADER__HEADER_TYPE_MASK
162142. BIF_CFG_DEV0_RC2_HEADER__HEADER_TYPE__SHIFT
162143. BIF_CFG_DEV0_RC2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
162144. BIF_CFG_DEV0_RC2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
162145. BIF_CFG_DEV0_RC2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
162146. BIF_CFG_DEV0_RC2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
162147. BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
162148. BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
162149. BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
162150. BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
162151. BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE_MASK
162152. BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
162153. BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
162154. BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE__SHIFT
162155. BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT_MASK
162156. BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
162157. BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
162158. BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT__SHIFT
162159. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
162160. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
162161. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__ISA_EN_MASK
162162. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
162163. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
162164. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
162165. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
162166. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
162167. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
162168. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
162169. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SERR_EN_MASK
162170. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
162171. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
162172. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
162173. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_EN_MASK
162174. BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
162175. BIF_CFG_DEV0_RC2_LATENCY__LATENCY_TIMER_MASK
162176. BIF_CFG_DEV0_RC2_LATENCY__LATENCY_TIMER__SHIFT
162177. BIF_CFG_DEV0_RC2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
162178. BIF_CFG_DEV0_RC2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
162179. BIF_CFG_DEV0_RC2_LINK_CAP2__RESERVED_MASK
162180. BIF_CFG_DEV0_RC2_LINK_CAP2__RESERVED__SHIFT
162181. BIF_CFG_DEV0_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
162182. BIF_CFG_DEV0_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
162183. BIF_CFG_DEV0_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
162184. BIF_CFG_DEV0_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
162185. BIF_CFG_DEV0_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
162186. BIF_CFG_DEV0_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
162187. BIF_CFG_DEV0_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
162188. BIF_CFG_DEV0_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
162189. BIF_CFG_DEV0_RC2_LINK_CAP__L0S_EXIT_LATENCY_MASK
162190. BIF_CFG_DEV0_RC2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
162191. BIF_CFG_DEV0_RC2_LINK_CAP__L1_EXIT_LATENCY_MASK
162192. BIF_CFG_DEV0_RC2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
162193. BIF_CFG_DEV0_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
162194. BIF_CFG_DEV0_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
162195. BIF_CFG_DEV0_RC2_LINK_CAP__LINK_SPEED_MASK
162196. BIF_CFG_DEV0_RC2_LINK_CAP__LINK_SPEED__SHIFT
162197. BIF_CFG_DEV0_RC2_LINK_CAP__LINK_WIDTH_MASK
162198. BIF_CFG_DEV0_RC2_LINK_CAP__LINK_WIDTH__SHIFT
162199. BIF_CFG_DEV0_RC2_LINK_CAP__PM_SUPPORT_MASK
162200. BIF_CFG_DEV0_RC2_LINK_CAP__PM_SUPPORT__SHIFT
162201. BIF_CFG_DEV0_RC2_LINK_CAP__PORT_NUMBER_MASK
162202. BIF_CFG_DEV0_RC2_LINK_CAP__PORT_NUMBER__SHIFT
162203. BIF_CFG_DEV0_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
162204. BIF_CFG_DEV0_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
162205. BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
162206. BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
162207. BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_SOS_MASK
162208. BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
162209. BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
162210. BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
162211. BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
162212. BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
162213. BIF_CFG_DEV0_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
162214. BIF_CFG_DEV0_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
162215. BIF_CFG_DEV0_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
162216. BIF_CFG_DEV0_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
162217. BIF_CFG_DEV0_RC2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
162218. BIF_CFG_DEV0_RC2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
162219. BIF_CFG_DEV0_RC2_LINK_CNTL2__XMIT_MARGIN_MASK
162220. BIF_CFG_DEV0_RC2_LINK_CNTL2__XMIT_MARGIN__SHIFT
162221. BIF_CFG_DEV0_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
162222. BIF_CFG_DEV0_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
162223. BIF_CFG_DEV0_RC2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
162224. BIF_CFG_DEV0_RC2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
162225. BIF_CFG_DEV0_RC2_LINK_CNTL__EXTENDED_SYNC_MASK
162226. BIF_CFG_DEV0_RC2_LINK_CNTL__EXTENDED_SYNC__SHIFT
162227. BIF_CFG_DEV0_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
162228. BIF_CFG_DEV0_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
162229. BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
162230. BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
162231. BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
162232. BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
162233. BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_DIS_MASK
162234. BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_DIS__SHIFT
162235. BIF_CFG_DEV0_RC2_LINK_CNTL__PM_CONTROL_MASK
162236. BIF_CFG_DEV0_RC2_LINK_CNTL__PM_CONTROL__SHIFT
162237. BIF_CFG_DEV0_RC2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
162238. BIF_CFG_DEV0_RC2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
162239. BIF_CFG_DEV0_RC2_LINK_CNTL__RETRAIN_LINK_MASK
162240. BIF_CFG_DEV0_RC2_LINK_CNTL__RETRAIN_LINK__SHIFT
162241. BIF_CFG_DEV0_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
162242. BIF_CFG_DEV0_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
162243. BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
162244. BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
162245. BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
162246. BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
162247. BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
162248. BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
162249. BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
162250. BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
162251. BIF_CFG_DEV0_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
162252. BIF_CFG_DEV0_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
162253. BIF_CFG_DEV0_RC2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
162254. BIF_CFG_DEV0_RC2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
162255. BIF_CFG_DEV0_RC2_LINK_STATUS__DL_ACTIVE_MASK
162256. BIF_CFG_DEV0_RC2_LINK_STATUS__DL_ACTIVE__SHIFT
162257. BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
162258. BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
162259. BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
162260. BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
162261. BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_TRAINING_MASK
162262. BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_TRAINING__SHIFT
162263. BIF_CFG_DEV0_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
162264. BIF_CFG_DEV0_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
162265. BIF_CFG_DEV0_RC2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
162266. BIF_CFG_DEV0_RC2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
162267. BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
162268. BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
162269. BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
162270. BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
162271. BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
162272. BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
162273. BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
162274. BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
162275. BIF_CFG_DEV0_RC2_MSI_CAP_LIST__CAP_ID_MASK
162276. BIF_CFG_DEV0_RC2_MSI_CAP_LIST__CAP_ID__SHIFT
162277. BIF_CFG_DEV0_RC2_MSI_CAP_LIST__NEXT_PTR_MASK
162278. BIF_CFG_DEV0_RC2_MSI_CAP_LIST__NEXT_PTR__SHIFT
162279. BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
162280. BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
162281. BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
162282. BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
162283. BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__CAP_ID_MASK
162284. BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
162285. BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
162286. BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
162287. BIF_CFG_DEV0_RC2_MSI_MAP_CAP__CAP_TYPE_MASK
162288. BIF_CFG_DEV0_RC2_MSI_MAP_CAP__CAP_TYPE__SHIFT
162289. BIF_CFG_DEV0_RC2_MSI_MAP_CAP__EN_MASK
162290. BIF_CFG_DEV0_RC2_MSI_MAP_CAP__EN__SHIFT
162291. BIF_CFG_DEV0_RC2_MSI_MAP_CAP__FIXD_MASK
162292. BIF_CFG_DEV0_RC2_MSI_MAP_CAP__FIXD__SHIFT
162293. BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
162294. BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
162295. BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
162296. BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
162297. BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_64BIT_MASK
162298. BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
162299. BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_EN_MASK
162300. BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_EN__SHIFT
162301. BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
162302. BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
162303. BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
162304. BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
162305. BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
162306. BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
162307. BIF_CFG_DEV0_RC2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
162308. BIF_CFG_DEV0_RC2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
162309. BIF_CFG_DEV0_RC2_MSI_MSG_DATA__MSI_DATA_MASK
162310. BIF_CFG_DEV0_RC2_MSI_MSG_DATA__MSI_DATA__SHIFT
162311. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
162312. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
162313. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
162314. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
162315. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
162316. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
162317. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
162318. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
162319. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
162320. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
162321. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
162322. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
162323. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
162324. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
162325. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
162326. BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
162327. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
162328. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
162329. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
162330. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
162331. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
162332. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
162333. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
162334. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
162335. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
162336. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
162337. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
162338. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
162339. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
162340. BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
162341. BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
162342. BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
162343. BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
162344. BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
162345. BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
162346. BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
162347. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
162348. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
162349. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
162350. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
162351. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
162352. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
162353. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
162354. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
162355. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
162356. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
162357. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
162358. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
162359. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
162360. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
162361. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
162362. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
162363. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
162364. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
162365. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
162366. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
162367. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
162368. BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
162369. BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__CAP_ID_MASK
162370. BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__CAP_ID__SHIFT
162371. BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__NEXT_PTR_MASK
162372. BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
162373. BIF_CFG_DEV0_RC2_PCIE_CAP__DEVICE_TYPE_MASK
162374. BIF_CFG_DEV0_RC2_PCIE_CAP__DEVICE_TYPE__SHIFT
162375. BIF_CFG_DEV0_RC2_PCIE_CAP__INT_MESSAGE_NUM_MASK
162376. BIF_CFG_DEV0_RC2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
162377. BIF_CFG_DEV0_RC2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
162378. BIF_CFG_DEV0_RC2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
162379. BIF_CFG_DEV0_RC2_PCIE_CAP__VERSION_MASK
162380. BIF_CFG_DEV0_RC2_PCIE_CAP__VERSION__SHIFT
162381. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
162382. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
162383. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
162384. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
162385. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
162386. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
162387. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
162388. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
162389. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
162390. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
162391. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
162392. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
162393. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
162394. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
162395. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
162396. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
162397. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
162398. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
162399. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
162400. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
162401. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
162402. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
162403. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
162404. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
162405. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
162406. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
162407. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
162408. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
162409. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
162410. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
162411. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
162412. BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
162413. BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
162414. BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
162415. BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
162416. BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
162417. BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
162418. BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
162419. BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
162420. BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
162421. BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
162422. BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
162423. BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
162424. BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
162425. BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
162426. BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
162427. BIF_CFG_DEV0_RC2_PCIE_HDR_LOG0__TLP_HDR_MASK
162428. BIF_CFG_DEV0_RC2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
162429. BIF_CFG_DEV0_RC2_PCIE_HDR_LOG1__TLP_HDR_MASK
162430. BIF_CFG_DEV0_RC2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
162431. BIF_CFG_DEV0_RC2_PCIE_HDR_LOG2__TLP_HDR_MASK
162432. BIF_CFG_DEV0_RC2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
162433. BIF_CFG_DEV0_RC2_PCIE_HDR_LOG3__TLP_HDR_MASK
162434. BIF_CFG_DEV0_RC2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
162435. BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162436. BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162437. BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162438. BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162439. BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
162440. BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
162441. BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162442. BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162443. BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162444. BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162445. BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162446. BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162447. BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162448. BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162449. BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
162450. BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
162451. BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162452. BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162453. BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162454. BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162455. BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162456. BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162457. BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162458. BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162459. BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
162460. BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
162461. BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162462. BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162463. BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162464. BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162465. BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162466. BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162467. BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162468. BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162469. BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
162470. BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
162471. BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162472. BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162473. BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162474. BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162475. BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162476. BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162477. BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162478. BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162479. BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
162480. BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
162481. BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162482. BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162483. BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162484. BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162485. BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162486. BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162487. BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162488. BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162489. BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
162490. BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
162491. BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162492. BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162493. BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162494. BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162495. BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162496. BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162497. BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162498. BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162499. BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
162500. BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
162501. BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162502. BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162503. BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162504. BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162505. BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162506. BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162507. BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162508. BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162509. BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
162510. BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
162511. BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162512. BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162513. BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162514. BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162515. BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162516. BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162517. BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162518. BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162519. BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
162520. BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
162521. BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162522. BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162523. BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162524. BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162525. BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162526. BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162527. BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162528. BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162529. BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
162530. BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
162531. BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162532. BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162533. BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162534. BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162535. BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162536. BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162537. BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162538. BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162539. BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
162540. BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
162541. BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162542. BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162543. BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162544. BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162545. BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162546. BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162547. BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162548. BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162549. BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
162550. BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
162551. BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162552. BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162553. BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162554. BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162555. BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162556. BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162557. BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162558. BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162559. BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
162560. BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
162561. BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162562. BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162563. BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162564. BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162565. BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162566. BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162567. BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162568. BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162569. BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
162570. BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
162571. BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162572. BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162573. BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162574. BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162575. BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162576. BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162577. BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162578. BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162579. BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
162580. BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
162581. BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162582. BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162583. BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162584. BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162585. BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
162586. BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
162587. BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
162588. BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
162589. BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
162590. BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
162591. BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
162592. BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
162593. BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
162594. BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
162595. BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
162596. BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
162597. BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
162598. BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
162599. BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
162600. BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
162601. BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
162602. BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
162603. BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__RESERVED_MASK
162604. BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__RESERVED__SHIFT
162605. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
162606. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
162607. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
162608. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
162609. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
162610. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
162611. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
162612. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
162613. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
162614. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
162615. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
162616. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
162617. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
162618. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
162619. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
162620. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
162621. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
162622. BIF_CFG_DEV0_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
162623. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
162624. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
162625. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
162626. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
162627. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
162628. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
162629. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
162630. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
162631. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
162632. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
162633. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
162634. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
162635. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
162636. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
162637. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
162638. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
162639. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
162640. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
162641. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
162642. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
162643. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
162644. BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
162645. BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
162646. BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
162647. BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
162648. BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
162649. BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
162650. BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
162651. BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
162652. BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
162653. BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
162654. BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
162655. BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
162656. BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
162657. BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
162658. BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
162659. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
162660. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
162661. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
162662. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
162663. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
162664. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
162665. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
162666. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
162667. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
162668. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
162669. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
162670. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
162671. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
162672. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
162673. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
162674. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
162675. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
162676. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
162677. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
162678. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
162679. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
162680. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
162681. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
162682. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
162683. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
162684. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
162685. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
162686. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
162687. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
162688. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
162689. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
162690. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
162691. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
162692. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
162693. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
162694. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
162695. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
162696. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
162697. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
162698. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
162699. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
162700. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
162701. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
162702. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
162703. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
162704. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
162705. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
162706. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
162707. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
162708. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
162709. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
162710. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
162711. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
162712. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
162713. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
162714. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
162715. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
162716. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
162717. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
162718. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
162719. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
162720. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
162721. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
162722. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
162723. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
162724. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
162725. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
162726. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
162727. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
162728. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
162729. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
162730. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
162731. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
162732. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
162733. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
162734. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
162735. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
162736. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
162737. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
162738. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
162739. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
162740. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
162741. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
162742. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
162743. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
162744. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
162745. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
162746. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
162747. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
162748. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
162749. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
162750. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
162751. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
162752. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
162753. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
162754. BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
162755. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
162756. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
162757. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
162758. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
162759. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
162760. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
162761. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
162762. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
162763. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
162764. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
162765. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
162766. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
162767. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
162768. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
162769. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
162770. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
162771. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
162772. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
162773. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
162774. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
162775. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
162776. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
162777. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
162778. BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
162779. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
162780. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
162781. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
162782. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
162783. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
162784. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
162785. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
162786. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
162787. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
162788. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
162789. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
162790. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
162791. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
162792. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
162793. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
162794. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
162795. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
162796. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
162797. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
162798. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
162799. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
162800. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
162801. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
162802. BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
162803. BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
162804. BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
162805. BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
162806. BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
162807. BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
162808. BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
162809. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
162810. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
162811. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
162812. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
162813. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
162814. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
162815. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
162816. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
162817. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
162818. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
162819. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
162820. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
162821. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
162822. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
162823. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
162824. BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
162825. BIF_CFG_DEV0_RC2_PMI_CAP_LIST__CAP_ID_MASK
162826. BIF_CFG_DEV0_RC2_PMI_CAP_LIST__CAP_ID__SHIFT
162827. BIF_CFG_DEV0_RC2_PMI_CAP_LIST__NEXT_PTR_MASK
162828. BIF_CFG_DEV0_RC2_PMI_CAP_LIST__NEXT_PTR__SHIFT
162829. BIF_CFG_DEV0_RC2_PMI_CAP__AUX_CURRENT_MASK
162830. BIF_CFG_DEV0_RC2_PMI_CAP__AUX_CURRENT__SHIFT
162831. BIF_CFG_DEV0_RC2_PMI_CAP__D1_SUPPORT_MASK
162832. BIF_CFG_DEV0_RC2_PMI_CAP__D1_SUPPORT__SHIFT
162833. BIF_CFG_DEV0_RC2_PMI_CAP__D2_SUPPORT_MASK
162834. BIF_CFG_DEV0_RC2_PMI_CAP__D2_SUPPORT__SHIFT
162835. BIF_CFG_DEV0_RC2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
162836. BIF_CFG_DEV0_RC2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
162837. BIF_CFG_DEV0_RC2_PMI_CAP__PME_CLOCK_MASK
162838. BIF_CFG_DEV0_RC2_PMI_CAP__PME_CLOCK__SHIFT
162839. BIF_CFG_DEV0_RC2_PMI_CAP__PME_SUPPORT_MASK
162840. BIF_CFG_DEV0_RC2_PMI_CAP__PME_SUPPORT__SHIFT
162841. BIF_CFG_DEV0_RC2_PMI_CAP__VERSION_MASK
162842. BIF_CFG_DEV0_RC2_PMI_CAP__VERSION__SHIFT
162843. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
162844. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
162845. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
162846. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
162847. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SCALE_MASK
162848. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
162849. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SELECT_MASK
162850. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
162851. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
162852. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
162853. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_EN_MASK
162854. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_EN__SHIFT
162855. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_STATUS_MASK
162856. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
162857. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PMI_DATA_MASK
162858. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
162859. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__POWER_STATE_MASK
162860. BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
162861. BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
162862. BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
162863. BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
162864. BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
162865. BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
162866. BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
162867. BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
162868. BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
162869. BIF_CFG_DEV0_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
162870. BIF_CFG_DEV0_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
162871. BIF_CFG_DEV0_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
162872. BIF_CFG_DEV0_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
162873. BIF_CFG_DEV0_RC2_PROG_INTERFACE__PROG_INTERFACE_MASK
162874. BIF_CFG_DEV0_RC2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
162875. BIF_CFG_DEV0_RC2_REVISION_ID__MAJOR_REV_ID_MASK
162876. BIF_CFG_DEV0_RC2_REVISION_ID__MAJOR_REV_ID__SHIFT
162877. BIF_CFG_DEV0_RC2_REVISION_ID__MINOR_REV_ID_MASK
162878. BIF_CFG_DEV0_RC2_REVISION_ID__MINOR_REV_ID__SHIFT
162879. BIF_CFG_DEV0_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
162880. BIF_CFG_DEV0_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
162881. BIF_CFG_DEV0_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
162882. BIF_CFG_DEV0_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
162883. BIF_CFG_DEV0_RC2_ROOT_CNTL__PM_INTERRUPT_EN_MASK
162884. BIF_CFG_DEV0_RC2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
162885. BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
162886. BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
162887. BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
162888. BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
162889. BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
162890. BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
162891. BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_PENDING_MASK
162892. BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_PENDING__SHIFT
162893. BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_REQUESTOR_ID_MASK
162894. BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
162895. BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_STATUS_MASK
162896. BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_STATUS__SHIFT
162897. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__CAP_LIST_MASK
162898. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__CAP_LIST__SHIFT
162899. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__DEVSEL_TIMING_MASK
162900. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
162901. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
162902. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
162903. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
162904. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
162905. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
162906. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
162907. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PCI_66_EN_MASK
162908. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PCI_66_EN__SHIFT
162909. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
162910. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
162911. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
162912. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
162913. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
162914. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
162915. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
162916. BIF_CFG_DEV0_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
162917. BIF_CFG_DEV0_RC2_SLOT_CAP2__RESERVED_MASK
162918. BIF_CFG_DEV0_RC2_SLOT_CAP2__RESERVED__SHIFT
162919. BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
162920. BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
162921. BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
162922. BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
162923. BIF_CFG_DEV0_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
162924. BIF_CFG_DEV0_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
162925. BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_CAPABLE_MASK
162926. BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
162927. BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_SURPRISE_MASK
162928. BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
162929. BIF_CFG_DEV0_RC2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
162930. BIF_CFG_DEV0_RC2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
162931. BIF_CFG_DEV0_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
162932. BIF_CFG_DEV0_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
162933. BIF_CFG_DEV0_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
162934. BIF_CFG_DEV0_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
162935. BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
162936. BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
162937. BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
162938. BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
162939. BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
162940. BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
162941. BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
162942. BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
162943. BIF_CFG_DEV0_RC2_SLOT_CNTL2__RESERVED_MASK
162944. BIF_CFG_DEV0_RC2_SLOT_CNTL2__RESERVED__SHIFT
162945. BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
162946. BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
162947. BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
162948. BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
162949. BIF_CFG_DEV0_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
162950. BIF_CFG_DEV0_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
162951. BIF_CFG_DEV0_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
162952. BIF_CFG_DEV0_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
162953. BIF_CFG_DEV0_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
162954. BIF_CFG_DEV0_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
162955. BIF_CFG_DEV0_RC2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
162956. BIF_CFG_DEV0_RC2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
162957. BIF_CFG_DEV0_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
162958. BIF_CFG_DEV0_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
162959. BIF_CFG_DEV0_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
162960. BIF_CFG_DEV0_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
162961. BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
162962. BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
162963. BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
162964. BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
162965. BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
162966. BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
162967. BIF_CFG_DEV0_RC2_SLOT_STATUS2__RESERVED_MASK
162968. BIF_CFG_DEV0_RC2_SLOT_STATUS2__RESERVED__SHIFT
162969. BIF_CFG_DEV0_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
162970. BIF_CFG_DEV0_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
162971. BIF_CFG_DEV0_RC2_SLOT_STATUS__COMMAND_COMPLETED_MASK
162972. BIF_CFG_DEV0_RC2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
162973. BIF_CFG_DEV0_RC2_SLOT_STATUS__DL_STATE_CHANGED_MASK
162974. BIF_CFG_DEV0_RC2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
162975. BIF_CFG_DEV0_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
162976. BIF_CFG_DEV0_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
162977. BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
162978. BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
162979. BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_STATE_MASK
162980. BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
162981. BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
162982. BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
162983. BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
162984. BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
162985. BIF_CFG_DEV0_RC2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
162986. BIF_CFG_DEV0_RC2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
162987. BIF_CFG_DEV0_RC2_SSID_CAP_LIST__CAP_ID_MASK
162988. BIF_CFG_DEV0_RC2_SSID_CAP_LIST__CAP_ID__SHIFT
162989. BIF_CFG_DEV0_RC2_SSID_CAP_LIST__NEXT_PTR_MASK
162990. BIF_CFG_DEV0_RC2_SSID_CAP_LIST__NEXT_PTR__SHIFT
162991. BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_ID_MASK
162992. BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_ID__SHIFT
162993. BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
162994. BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
162995. BIF_CFG_DEV0_RC2_STATUS__CAP_LIST_MASK
162996. BIF_CFG_DEV0_RC2_STATUS__CAP_LIST__SHIFT
162997. BIF_CFG_DEV0_RC2_STATUS__DEVSEL_TIMING_MASK
162998. BIF_CFG_DEV0_RC2_STATUS__DEVSEL_TIMING__SHIFT
162999. BIF_CFG_DEV0_RC2_STATUS__FAST_BACK_CAPABLE_MASK
163000. BIF_CFG_DEV0_RC2_STATUS__FAST_BACK_CAPABLE__SHIFT
163001. BIF_CFG_DEV0_RC2_STATUS__INT_STATUS_MASK
163002. BIF_CFG_DEV0_RC2_STATUS__INT_STATUS__SHIFT
163003. BIF_CFG_DEV0_RC2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
163004. BIF_CFG_DEV0_RC2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
163005. BIF_CFG_DEV0_RC2_STATUS__PARITY_ERROR_DETECTED_MASK
163006. BIF_CFG_DEV0_RC2_STATUS__PARITY_ERROR_DETECTED__SHIFT
163007. BIF_CFG_DEV0_RC2_STATUS__PCI_66_EN_MASK
163008. BIF_CFG_DEV0_RC2_STATUS__PCI_66_EN__SHIFT
163009. BIF_CFG_DEV0_RC2_STATUS__RECEIVED_MASTER_ABORT_MASK
163010. BIF_CFG_DEV0_RC2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
163011. BIF_CFG_DEV0_RC2_STATUS__RECEIVED_TARGET_ABORT_MASK
163012. BIF_CFG_DEV0_RC2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
163013. BIF_CFG_DEV0_RC2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
163014. BIF_CFG_DEV0_RC2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
163015. BIF_CFG_DEV0_RC2_STATUS__SIGNAL_TARGET_ABORT_MASK
163016. BIF_CFG_DEV0_RC2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
163017. BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
163018. BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
163019. BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
163020. BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
163021. BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
163022. BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
163023. BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
163024. BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
163025. BIF_CFG_DEV0_RC2_SUB_CLASS__SUB_CLASS_MASK
163026. BIF_CFG_DEV0_RC2_SUB_CLASS__SUB_CLASS__SHIFT
163027. BIF_CFG_DEV0_RC2_VENDOR_ID__VENDOR_ID_MASK
163028. BIF_CFG_DEV0_RC2_VENDOR_ID__VENDOR_ID__SHIFT
163029. BIF_CFG_DEV0_SWDS0_BASE_ADDR_1__BASE_ADDR_MASK
163030. BIF_CFG_DEV0_SWDS0_BASE_ADDR_1__BASE_ADDR__SHIFT
163031. BIF_CFG_DEV0_SWDS0_BASE_ADDR_2__BASE_ADDR_MASK
163032. BIF_CFG_DEV0_SWDS0_BASE_ADDR_2__BASE_ADDR__SHIFT
163033. BIF_CFG_DEV0_SWDS0_BASE_CLASS__BASE_CLASS_MASK
163034. BIF_CFG_DEV0_SWDS0_BASE_CLASS__BASE_CLASS__SHIFT
163035. BIF_CFG_DEV0_SWDS0_BIST__BIST_CAP_MASK
163036. BIF_CFG_DEV0_SWDS0_BIST__BIST_CAP__SHIFT
163037. BIF_CFG_DEV0_SWDS0_BIST__BIST_COMP_MASK
163038. BIF_CFG_DEV0_SWDS0_BIST__BIST_COMP__SHIFT
163039. BIF_CFG_DEV0_SWDS0_BIST__BIST_STRT_MASK
163040. BIF_CFG_DEV0_SWDS0_BIST__BIST_STRT__SHIFT
163041. BIF_CFG_DEV0_SWDS0_CACHE_LINE__CACHE_LINE_SIZE_MASK
163042. BIF_CFG_DEV0_SWDS0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
163043. BIF_CFG_DEV0_SWDS0_CAP_PTR__CAP_PTR_MASK
163044. BIF_CFG_DEV0_SWDS0_CAP_PTR__CAP_PTR__SHIFT
163045. BIF_CFG_DEV0_SWDS0_COMMAND__AD_STEPPING_MASK
163046. BIF_CFG_DEV0_SWDS0_COMMAND__AD_STEPPING__SHIFT
163047. BIF_CFG_DEV0_SWDS0_COMMAND__BUS_MASTER_EN_MASK
163048. BIF_CFG_DEV0_SWDS0_COMMAND__BUS_MASTER_EN__SHIFT
163049. BIF_CFG_DEV0_SWDS0_COMMAND__FAST_B2B_EN_MASK
163050. BIF_CFG_DEV0_SWDS0_COMMAND__FAST_B2B_EN__SHIFT
163051. BIF_CFG_DEV0_SWDS0_COMMAND__INT_DIS_MASK
163052. BIF_CFG_DEV0_SWDS0_COMMAND__INT_DIS__SHIFT
163053. BIF_CFG_DEV0_SWDS0_COMMAND__IOEN_DN_MASK
163054. BIF_CFG_DEV0_SWDS0_COMMAND__IOEN_DN__SHIFT
163055. BIF_CFG_DEV0_SWDS0_COMMAND__MEMEN_DN_MASK
163056. BIF_CFG_DEV0_SWDS0_COMMAND__MEMEN_DN__SHIFT
163057. BIF_CFG_DEV0_SWDS0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
163058. BIF_CFG_DEV0_SWDS0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
163059. BIF_CFG_DEV0_SWDS0_COMMAND__PAL_SNOOP_EN_MASK
163060. BIF_CFG_DEV0_SWDS0_COMMAND__PAL_SNOOP_EN__SHIFT
163061. BIF_CFG_DEV0_SWDS0_COMMAND__PARITY_ERROR_RESPONSE_MASK
163062. BIF_CFG_DEV0_SWDS0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
163063. BIF_CFG_DEV0_SWDS0_COMMAND__SERR_EN_MASK
163064. BIF_CFG_DEV0_SWDS0_COMMAND__SERR_EN__SHIFT
163065. BIF_CFG_DEV0_SWDS0_COMMAND__SPECIAL_CYCLE_EN_MASK
163066. BIF_CFG_DEV0_SWDS0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
163067. BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK
163068. BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT
163069. BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK
163070. BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT
163071. BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK
163072. BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK
163073. BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT
163074. BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT
163075. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
163076. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
163077. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
163078. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
163079. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
163080. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
163081. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
163082. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
163083. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
163084. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
163085. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
163086. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
163087. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
163088. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
163089. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
163090. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
163091. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
163092. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
163093. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
163094. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
163095. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
163096. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
163097. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__FRS_SUPPORTED_MASK
163098. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
163099. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
163100. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
163101. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LTR_SUPPORTED_MASK
163102. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
163103. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
163104. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
163105. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
163106. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
163107. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
163108. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
163109. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
163110. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
163111. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
163112. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
163113. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
163114. BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
163115. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
163116. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
163117. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
163118. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
163119. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__EXTENDED_TAG_MASK
163120. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__EXTENDED_TAG__SHIFT
163121. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__FLR_CAPABLE_MASK
163122. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__FLR_CAPABLE__SHIFT
163123. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
163124. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
163125. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
163126. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
163127. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
163128. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
163129. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__PHANTOM_FUNC_MASK
163130. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
163131. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
163132. BIF_CFG_DEV0_SWDS0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
163133. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
163134. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
163135. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
163136. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
163137. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
163138. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
163139. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
163140. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
163141. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
163142. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
163143. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
163144. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
163145. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
163146. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
163147. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
163148. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
163149. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
163150. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
163151. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__LTR_EN_MASK
163152. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__LTR_EN__SHIFT
163153. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__OBFF_EN_MASK
163154. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__OBFF_EN__SHIFT
163155. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
163156. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
163157. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
163158. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
163159. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
163160. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
163161. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__CORR_ERR_EN_MASK
163162. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
163163. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
163164. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
163165. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__FATAL_ERR_EN_MASK
163166. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
163167. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
163168. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
163169. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
163170. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
163171. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
163172. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
163173. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NO_SNOOP_EN_MASK
163174. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
163175. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
163176. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
163177. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
163178. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
163179. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__USR_REPORT_EN_MASK
163180. BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
163181. BIF_CFG_DEV0_SWDS0_DEVICE_ID__DEVICE_ID_MASK
163182. BIF_CFG_DEV0_SWDS0_DEVICE_ID__DEVICE_ID__SHIFT
163183. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2__RESERVED_MASK
163184. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2__RESERVED__SHIFT
163185. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__AUX_PWR_MASK
163186. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__AUX_PWR__SHIFT
163187. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__CORR_ERR_MASK
163188. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__CORR_ERR__SHIFT
163189. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
163190. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
163191. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__FATAL_ERR_MASK
163192. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__FATAL_ERR__SHIFT
163193. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__NON_FATAL_ERR_MASK
163194. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
163195. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
163196. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
163197. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__USR_DETECTED_MASK
163198. BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__USR_DETECTED__SHIFT
163199. BIF_CFG_DEV0_SWDS0_HEADER__DEVICE_TYPE_MASK
163200. BIF_CFG_DEV0_SWDS0_HEADER__DEVICE_TYPE__SHIFT
163201. BIF_CFG_DEV0_SWDS0_HEADER__HEADER_TYPE_MASK
163202. BIF_CFG_DEV0_SWDS0_HEADER__HEADER_TYPE__SHIFT
163203. BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
163204. BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
163205. BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
163206. BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
163207. BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
163208. BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
163209. BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
163210. BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
163211. BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_MASK
163212. BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
163213. BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
163214. BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE__SHIFT
163215. BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_MASK
163216. BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
163217. BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
163218. BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT__SHIFT
163219. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK
163220. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT
163221. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK
163222. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT
163223. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
163224. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
163225. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__ISA_EN_MASK
163226. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
163227. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
163228. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
163229. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
163230. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
163231. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK
163232. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT
163233. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
163234. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
163235. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK
163236. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT
163237. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SERR_EN_MASK
163238. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
163239. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
163240. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
163241. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_EN_MASK
163242. BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
163243. BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK
163244. BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT
163245. BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK
163246. BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT
163247. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK
163248. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT
163249. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK
163250. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT
163251. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK
163252. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT
163253. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK
163254. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT
163255. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK
163256. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT
163257. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK
163258. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT
163259. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK
163260. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT
163261. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK
163262. BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT
163263. BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK
163264. BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT
163265. BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK
163266. BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT
163267. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK
163268. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT
163269. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK
163270. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT
163271. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK
163272. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT
163273. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK
163274. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT
163275. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK
163276. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT
163277. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK
163278. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT
163279. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK
163280. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT
163281. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK
163282. BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT
163283. BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK
163284. BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT
163285. BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK
163286. BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT
163287. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK
163288. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT
163289. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK
163290. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT
163291. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK
163292. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT
163293. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK
163294. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT
163295. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK
163296. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT
163297. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK
163298. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT
163299. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK
163300. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT
163301. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK
163302. BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT
163303. BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK
163304. BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT
163305. BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK
163306. BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT
163307. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK
163308. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT
163309. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK
163310. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT
163311. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK
163312. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT
163313. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK
163314. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT
163315. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK
163316. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT
163317. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK
163318. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT
163319. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK
163320. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT
163321. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK
163322. BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT
163323. BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK
163324. BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT
163325. BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK
163326. BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT
163327. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK
163328. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT
163329. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK
163330. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT
163331. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK
163332. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT
163333. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK
163334. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT
163335. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK
163336. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT
163337. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK
163338. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT
163339. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK
163340. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT
163341. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK
163342. BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT
163343. BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK
163344. BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT
163345. BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK
163346. BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT
163347. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK
163348. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT
163349. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK
163350. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT
163351. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK
163352. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT
163353. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK
163354. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT
163355. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK
163356. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT
163357. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK
163358. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT
163359. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK
163360. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT
163361. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK
163362. BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT
163363. BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK
163364. BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT
163365. BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK
163366. BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT
163367. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK
163368. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT
163369. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK
163370. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT
163371. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK
163372. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT
163373. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK
163374. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT
163375. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK
163376. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT
163377. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK
163378. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT
163379. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK
163380. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT
163381. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK
163382. BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT
163383. BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK
163384. BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT
163385. BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK
163386. BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT
163387. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK
163388. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT
163389. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK
163390. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT
163391. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK
163392. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT
163393. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK
163394. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT
163395. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK
163396. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT
163397. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK
163398. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT
163399. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK
163400. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT
163401. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK
163402. BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT
163403. BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK
163404. BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT
163405. BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK
163406. BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT
163407. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK
163408. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT
163409. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK
163410. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT
163411. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK
163412. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT
163413. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK
163414. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT
163415. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK
163416. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT
163417. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK
163418. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT
163419. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK
163420. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT
163421. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK
163422. BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT
163423. BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK
163424. BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT
163425. BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK
163426. BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT
163427. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK
163428. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT
163429. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK
163430. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT
163431. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK
163432. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT
163433. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK
163434. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT
163435. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK
163436. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT
163437. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK
163438. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT
163439. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK
163440. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT
163441. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK
163442. BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT
163443. BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK
163444. BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT
163445. BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK
163446. BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT
163447. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK
163448. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT
163449. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK
163450. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT
163451. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK
163452. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT
163453. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK
163454. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT
163455. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK
163456. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT
163457. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK
163458. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT
163459. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK
163460. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT
163461. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK
163462. BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT
163463. BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK
163464. BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT
163465. BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK
163466. BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT
163467. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK
163468. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT
163469. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK
163470. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT
163471. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK
163472. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT
163473. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK
163474. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT
163475. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK
163476. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT
163477. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK
163478. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT
163479. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK
163480. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT
163481. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK
163482. BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT
163483. BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK
163484. BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT
163485. BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK
163486. BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT
163487. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK
163488. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT
163489. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK
163490. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT
163491. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK
163492. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT
163493. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK
163494. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT
163495. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK
163496. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT
163497. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK
163498. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT
163499. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK
163500. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT
163501. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK
163502. BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT
163503. BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK
163504. BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT
163505. BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK
163506. BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT
163507. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK
163508. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT
163509. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK
163510. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT
163511. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK
163512. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT
163513. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK
163514. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT
163515. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK
163516. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT
163517. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK
163518. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT
163519. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK
163520. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT
163521. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK
163522. BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT
163523. BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK
163524. BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT
163525. BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK
163526. BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT
163527. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK
163528. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT
163529. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK
163530. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT
163531. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK
163532. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT
163533. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK
163534. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT
163535. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK
163536. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT
163537. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK
163538. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT
163539. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK
163540. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT
163541. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK
163542. BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT
163543. BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK
163544. BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT
163545. BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK
163546. BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT
163547. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK
163548. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT
163549. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK
163550. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT
163551. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK
163552. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT
163553. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK
163554. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT
163555. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK
163556. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT
163557. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK
163558. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT
163559. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK
163560. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT
163561. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK
163562. BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT
163563. BIF_CFG_DEV0_SWDS0_LATENCY__LATENCY_TIMER_MASK
163564. BIF_CFG_DEV0_SWDS0_LATENCY__LATENCY_TIMER__SHIFT
163565. BIF_CFG_DEV0_SWDS0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
163566. BIF_CFG_DEV0_SWDS0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
163567. BIF_CFG_DEV0_SWDS0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
163568. BIF_CFG_DEV0_SWDS0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
163569. BIF_CFG_DEV0_SWDS0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
163570. BIF_CFG_DEV0_SWDS0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
163571. BIF_CFG_DEV0_SWDS0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
163572. BIF_CFG_DEV0_SWDS0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
163573. BIF_CFG_DEV0_SWDS0_LINK_CAP2__RESERVED_MASK
163574. BIF_CFG_DEV0_SWDS0_LINK_CAP2__RESERVED__SHIFT
163575. BIF_CFG_DEV0_SWDS0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
163576. BIF_CFG_DEV0_SWDS0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
163577. BIF_CFG_DEV0_SWDS0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
163578. BIF_CFG_DEV0_SWDS0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
163579. BIF_CFG_DEV0_SWDS0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
163580. BIF_CFG_DEV0_SWDS0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
163581. BIF_CFG_DEV0_SWDS0_LINK_CAP_16GT__RESERVED_MASK
163582. BIF_CFG_DEV0_SWDS0_LINK_CAP_16GT__RESERVED__SHIFT
163583. BIF_CFG_DEV0_SWDS0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
163584. BIF_CFG_DEV0_SWDS0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
163585. BIF_CFG_DEV0_SWDS0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
163586. BIF_CFG_DEV0_SWDS0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
163587. BIF_CFG_DEV0_SWDS0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
163588. BIF_CFG_DEV0_SWDS0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
163589. BIF_CFG_DEV0_SWDS0_LINK_CAP__L0S_EXIT_LATENCY_MASK
163590. BIF_CFG_DEV0_SWDS0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
163591. BIF_CFG_DEV0_SWDS0_LINK_CAP__L1_EXIT_LATENCY_MASK
163592. BIF_CFG_DEV0_SWDS0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
163593. BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
163594. BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
163595. BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_SPEED_MASK
163596. BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_SPEED__SHIFT
163597. BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_WIDTH_MASK
163598. BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_WIDTH__SHIFT
163599. BIF_CFG_DEV0_SWDS0_LINK_CAP__PM_SUPPORT_MASK
163600. BIF_CFG_DEV0_SWDS0_LINK_CAP__PM_SUPPORT__SHIFT
163601. BIF_CFG_DEV0_SWDS0_LINK_CAP__PORT_NUMBER_MASK
163602. BIF_CFG_DEV0_SWDS0_LINK_CAP__PORT_NUMBER__SHIFT
163603. BIF_CFG_DEV0_SWDS0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
163604. BIF_CFG_DEV0_SWDS0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
163605. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
163606. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
163607. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_SOS_MASK
163608. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
163609. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
163610. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
163611. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
163612. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
163613. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
163614. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
163615. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
163616. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
163617. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
163618. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
163619. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__XMIT_MARGIN_MASK
163620. BIF_CFG_DEV0_SWDS0_LINK_CNTL2__XMIT_MARGIN__SHIFT
163621. BIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT__RESERVED_MASK
163622. BIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT__RESERVED__SHIFT
163623. BIF_CFG_DEV0_SWDS0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
163624. BIF_CFG_DEV0_SWDS0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
163625. BIF_CFG_DEV0_SWDS0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
163626. BIF_CFG_DEV0_SWDS0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
163627. BIF_CFG_DEV0_SWDS0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
163628. BIF_CFG_DEV0_SWDS0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
163629. BIF_CFG_DEV0_SWDS0_LINK_CNTL__EXTENDED_SYNC_MASK
163630. BIF_CFG_DEV0_SWDS0_LINK_CNTL__EXTENDED_SYNC__SHIFT
163631. BIF_CFG_DEV0_SWDS0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
163632. BIF_CFG_DEV0_SWDS0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
163633. BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
163634. BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
163635. BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
163636. BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
163637. BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_DIS_MASK
163638. BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_DIS__SHIFT
163639. BIF_CFG_DEV0_SWDS0_LINK_CNTL__PM_CONTROL_MASK
163640. BIF_CFG_DEV0_SWDS0_LINK_CNTL__PM_CONTROL__SHIFT
163641. BIF_CFG_DEV0_SWDS0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
163642. BIF_CFG_DEV0_SWDS0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
163643. BIF_CFG_DEV0_SWDS0_LINK_CNTL__RETRAIN_LINK_MASK
163644. BIF_CFG_DEV0_SWDS0_LINK_CNTL__RETRAIN_LINK__SHIFT
163645. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
163646. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
163647. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
163648. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
163649. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
163650. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
163651. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
163652. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
163653. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
163654. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
163655. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
163656. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
163657. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
163658. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
163659. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
163660. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
163661. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
163662. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
163663. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
163664. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
163665. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
163666. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
163667. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
163668. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
163669. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
163670. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
163671. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
163672. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
163673. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
163674. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
163675. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
163676. BIF_CFG_DEV0_SWDS0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
163677. BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK
163678. BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT
163679. BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK
163680. BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT
163681. BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK
163682. BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT
163683. BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK
163684. BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT
163685. BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK
163686. BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT
163687. BIF_CFG_DEV0_SWDS0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
163688. BIF_CFG_DEV0_SWDS0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
163689. BIF_CFG_DEV0_SWDS0_LINK_STATUS__DL_ACTIVE_MASK
163690. BIF_CFG_DEV0_SWDS0_LINK_STATUS__DL_ACTIVE__SHIFT
163691. BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
163692. BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
163693. BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
163694. BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
163695. BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_TRAINING_MASK
163696. BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_TRAINING__SHIFT
163697. BIF_CFG_DEV0_SWDS0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
163698. BIF_CFG_DEV0_SWDS0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
163699. BIF_CFG_DEV0_SWDS0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
163700. BIF_CFG_DEV0_SWDS0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
163701. BIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK
163702. BIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT
163703. BIF_CFG_DEV0_SWDS0_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
163704. BIF_CFG_DEV0_SWDS0_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
163705. BIF_CFG_DEV0_SWDS0_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
163706. BIF_CFG_DEV0_SWDS0_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
163707. BIF_CFG_DEV0_SWDS0_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
163708. BIF_CFG_DEV0_SWDS0_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
163709. BIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK
163710. BIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT
163711. BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS__MARGINING_READY_MASK
163712. BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT
163713. BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK
163714. BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT
163715. BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
163716. BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
163717. BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
163718. BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
163719. BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
163720. BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
163721. BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
163722. BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
163723. BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__CAP_ID_MASK
163724. BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__CAP_ID__SHIFT
163725. BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__NEXT_PTR_MASK
163726. BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__NEXT_PTR__SHIFT
163727. BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
163728. BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
163729. BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
163730. BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
163731. BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_64BIT_MASK
163732. BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
163733. BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_EN_MASK
163734. BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_EN__SHIFT
163735. BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
163736. BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
163737. BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
163738. BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
163739. BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
163740. BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
163741. BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
163742. BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
163743. BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA__MSI_DATA_MASK
163744. BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA__MSI_DATA__SHIFT
163745. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
163746. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
163747. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
163748. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
163749. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
163750. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
163751. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
163752. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
163753. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
163754. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
163755. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
163756. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
163757. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
163758. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
163759. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
163760. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
163761. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
163762. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
163763. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
163764. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
163765. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
163766. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
163767. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
163768. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
163769. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
163770. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
163771. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
163772. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
163773. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
163774. BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
163775. BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
163776. BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
163777. BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
163778. BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
163779. BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
163780. BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
163781. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
163782. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
163783. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
163784. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
163785. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
163786. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
163787. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
163788. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
163789. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
163790. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
163791. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
163792. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
163793. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
163794. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
163795. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
163796. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
163797. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
163798. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
163799. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
163800. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
163801. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
163802. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
163803. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
163804. BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
163805. BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__CAP_ID_MASK
163806. BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__CAP_ID__SHIFT
163807. BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__NEXT_PTR_MASK
163808. BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
163809. BIF_CFG_DEV0_SWDS0_PCIE_CAP__DEVICE_TYPE_MASK
163810. BIF_CFG_DEV0_SWDS0_PCIE_CAP__DEVICE_TYPE__SHIFT
163811. BIF_CFG_DEV0_SWDS0_PCIE_CAP__INT_MESSAGE_NUM_MASK
163812. BIF_CFG_DEV0_SWDS0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
163813. BIF_CFG_DEV0_SWDS0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
163814. BIF_CFG_DEV0_SWDS0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
163815. BIF_CFG_DEV0_SWDS0_PCIE_CAP__VERSION_MASK
163816. BIF_CFG_DEV0_SWDS0_PCIE_CAP__VERSION__SHIFT
163817. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
163818. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
163819. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
163820. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
163821. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
163822. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
163823. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
163824. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
163825. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
163826. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
163827. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
163828. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
163829. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
163830. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
163831. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
163832. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
163833. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
163834. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
163835. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
163836. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
163837. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
163838. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
163839. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
163840. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
163841. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
163842. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
163843. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
163844. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
163845. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
163846. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
163847. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
163848. BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
163849. BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
163850. BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
163851. BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
163852. BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
163853. BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
163854. BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
163855. BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
163856. BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
163857. BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
163858. BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
163859. BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK
163860. BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT
163861. BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK
163862. BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT
163863. BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK
163864. BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT
163865. BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0__TLP_HDR_MASK
163866. BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
163867. BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1__TLP_HDR_MASK
163868. BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
163869. BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2__TLP_HDR_MASK
163870. BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
163871. BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3__TLP_HDR_MASK
163872. BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
163873. BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
163874. BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
163875. BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
163876. BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
163877. BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
163878. BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
163879. BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
163880. BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
163881. BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
163882. BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
163883. BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
163884. BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
163885. BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
163886. BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
163887. BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
163888. BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
163889. BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
163890. BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
163891. BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
163892. BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
163893. BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
163894. BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
163895. BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
163896. BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
163897. BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
163898. BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
163899. BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
163900. BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
163901. BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
163902. BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
163903. BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
163904. BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
163905. BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
163906. BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
163907. BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
163908. BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
163909. BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
163910. BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
163911. BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
163912. BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
163913. BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
163914. BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
163915. BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
163916. BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
163917. BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
163918. BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
163919. BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
163920. BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
163921. BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
163922. BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
163923. BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
163924. BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
163925. BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
163926. BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
163927. BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
163928. BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
163929. BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
163930. BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
163931. BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
163932. BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
163933. BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
163934. BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
163935. BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
163936. BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
163937. BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
163938. BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
163939. BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
163940. BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
163941. BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
163942. BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
163943. BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
163944. BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
163945. BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
163946. BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
163947. BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
163948. BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
163949. BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
163950. BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
163951. BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
163952. BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
163953. BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
163954. BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
163955. BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
163956. BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
163957. BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
163958. BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
163959. BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
163960. BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
163961. BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
163962. BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
163963. BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
163964. BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
163965. BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
163966. BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
163967. BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
163968. BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
163969. BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
163970. BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
163971. BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
163972. BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
163973. BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
163974. BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
163975. BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
163976. BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
163977. BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
163978. BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
163979. BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
163980. BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
163981. BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
163982. BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
163983. BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
163984. BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
163985. BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
163986. BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
163987. BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
163988. BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
163989. BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
163990. BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
163991. BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
163992. BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
163993. BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
163994. BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
163995. BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
163996. BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
163997. BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
163998. BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
163999. BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
164000. BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
164001. BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
164002. BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
164003. BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
164004. BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
164005. BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
164006. BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
164007. BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
164008. BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
164009. BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
164010. BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
164011. BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
164012. BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
164013. BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
164014. BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
164015. BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
164016. BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
164017. BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
164018. BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
164019. BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
164020. BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
164021. BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
164022. BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
164023. BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
164024. BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
164025. BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
164026. BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
164027. BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
164028. BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
164029. BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
164030. BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
164031. BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
164032. BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
164033. BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
164034. BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
164035. BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
164036. BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
164037. BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
164038. BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
164039. BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
164040. BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
164041. BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
164042. BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
164043. BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__RESERVED_MASK
164044. BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__RESERVED__SHIFT
164045. BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
164046. BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
164047. BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
164048. BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
164049. BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
164050. BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
164051. BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
164052. BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
164053. BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
164054. BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
164055. BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
164056. BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
164057. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
164058. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
164059. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
164060. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
164061. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
164062. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
164063. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
164064. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
164065. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
164066. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
164067. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
164068. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
164069. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
164070. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
164071. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
164072. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
164073. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
164074. BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
164075. BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
164076. BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
164077. BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
164078. BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
164079. BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
164080. BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
164081. BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
164082. BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
164083. BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
164084. BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
164085. BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
164086. BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
164087. BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
164088. BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
164089. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
164090. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
164091. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
164092. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
164093. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
164094. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
164095. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
164096. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
164097. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
164098. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
164099. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
164100. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
164101. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
164102. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
164103. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
164104. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
164105. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
164106. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
164107. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
164108. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
164109. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
164110. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
164111. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
164112. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
164113. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
164114. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
164115. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
164116. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
164117. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
164118. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
164119. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
164120. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
164121. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
164122. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
164123. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
164124. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
164125. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
164126. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
164127. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
164128. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
164129. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
164130. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
164131. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
164132. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
164133. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
164134. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
164135. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
164136. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
164137. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
164138. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
164139. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
164140. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
164141. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
164142. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
164143. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
164144. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
164145. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
164146. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
164147. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
164148. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
164149. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
164150. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
164151. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
164152. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
164153. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
164154. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
164155. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
164156. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
164157. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
164158. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
164159. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
164160. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
164161. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
164162. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
164163. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
164164. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
164165. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
164166. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
164167. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
164168. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
164169. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
164170. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
164171. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
164172. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
164173. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
164174. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
164175. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
164176. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
164177. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
164178. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
164179. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
164180. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
164181. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
164182. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
164183. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
164184. BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
164185. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
164186. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
164187. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
164188. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
164189. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
164190. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
164191. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
164192. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
164193. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
164194. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
164195. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
164196. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
164197. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
164198. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
164199. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
164200. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
164201. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
164202. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
164203. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
164204. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
164205. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
164206. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
164207. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
164208. BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
164209. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
164210. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
164211. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
164212. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
164213. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
164214. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
164215. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
164216. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
164217. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
164218. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
164219. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
164220. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
164221. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
164222. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
164223. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
164224. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
164225. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
164226. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
164227. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
164228. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
164229. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
164230. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
164231. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
164232. BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
164233. BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
164234. BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
164235. BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
164236. BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
164237. BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
164238. BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
164239. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
164240. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
164241. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
164242. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
164243. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
164244. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
164245. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
164246. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
164247. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
164248. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
164249. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
164250. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
164251. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
164252. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
164253. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
164254. BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
164255. BIF_CFG_DEV0_SWDS0_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
164256. BIF_CFG_DEV0_SWDS0_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
164257. BIF_CFG_DEV0_SWDS0_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
164258. BIF_CFG_DEV0_SWDS0_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
164259. BIF_CFG_DEV0_SWDS0_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
164260. BIF_CFG_DEV0_SWDS0_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
164261. BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__CAP_ID_MASK
164262. BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__CAP_ID__SHIFT
164263. BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__NEXT_PTR_MASK
164264. BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__NEXT_PTR__SHIFT
164265. BIF_CFG_DEV0_SWDS0_PMI_CAP__AUX_CURRENT_MASK
164266. BIF_CFG_DEV0_SWDS0_PMI_CAP__AUX_CURRENT__SHIFT
164267. BIF_CFG_DEV0_SWDS0_PMI_CAP__D1_SUPPORT_MASK
164268. BIF_CFG_DEV0_SWDS0_PMI_CAP__D1_SUPPORT__SHIFT
164269. BIF_CFG_DEV0_SWDS0_PMI_CAP__D2_SUPPORT_MASK
164270. BIF_CFG_DEV0_SWDS0_PMI_CAP__D2_SUPPORT__SHIFT
164271. BIF_CFG_DEV0_SWDS0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
164272. BIF_CFG_DEV0_SWDS0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
164273. BIF_CFG_DEV0_SWDS0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
164274. BIF_CFG_DEV0_SWDS0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
164275. BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_CLOCK_MASK
164276. BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_CLOCK__SHIFT
164277. BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_SUPPORT_MASK
164278. BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_SUPPORT__SHIFT
164279. BIF_CFG_DEV0_SWDS0_PMI_CAP__VERSION_MASK
164280. BIF_CFG_DEV0_SWDS0_PMI_CAP__VERSION__SHIFT
164281. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
164282. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
164283. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
164284. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
164285. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SCALE_MASK
164286. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
164287. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SELECT_MASK
164288. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
164289. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
164290. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
164291. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_EN_MASK
164292. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_EN__SHIFT
164293. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_STATUS_MASK
164294. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
164295. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PMI_DATA_MASK
164296. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
164297. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__POWER_STATE_MASK
164298. BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
164299. BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
164300. BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
164301. BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
164302. BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
164303. BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
164304. BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
164305. BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
164306. BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
164307. BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
164308. BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
164309. BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
164310. BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
164311. BIF_CFG_DEV0_SWDS0_PROG_INTERFACE__PROG_INTERFACE_MASK
164312. BIF_CFG_DEV0_SWDS0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
164313. BIF_CFG_DEV0_SWDS0_REVISION_ID__MAJOR_REV_ID_MASK
164314. BIF_CFG_DEV0_SWDS0_REVISION_ID__MAJOR_REV_ID__SHIFT
164315. BIF_CFG_DEV0_SWDS0_REVISION_ID__MINOR_REV_ID_MASK
164316. BIF_CFG_DEV0_SWDS0_REVISION_ID__MINOR_REV_ID__SHIFT
164317. BIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR__BASE_ADDR_MASK
164318. BIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
164319. BIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK
164320. BIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT
164321. BIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK
164322. BIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT
164323. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__CAP_LIST_MASK
164324. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__CAP_LIST__SHIFT
164325. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__DEVSEL_TIMING_MASK
164326. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
164327. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
164328. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
164329. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
164330. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
164331. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
164332. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
164333. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PCI_66_CAP_MASK
164334. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PCI_66_CAP__SHIFT
164335. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PCI_66_EN_MASK
164336. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PCI_66_EN__SHIFT
164337. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
164338. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
164339. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
164340. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
164341. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
164342. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
164343. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
164344. BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
164345. BIF_CFG_DEV0_SWDS0_SLOT_CAP2__RESERVED_MASK
164346. BIF_CFG_DEV0_SWDS0_SLOT_CAP2__RESERVED__SHIFT
164347. BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
164348. BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
164349. BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
164350. BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
164351. BIF_CFG_DEV0_SWDS0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
164352. BIF_CFG_DEV0_SWDS0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
164353. BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_CAPABLE_MASK
164354. BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
164355. BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_SURPRISE_MASK
164356. BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
164357. BIF_CFG_DEV0_SWDS0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
164358. BIF_CFG_DEV0_SWDS0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
164359. BIF_CFG_DEV0_SWDS0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
164360. BIF_CFG_DEV0_SWDS0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
164361. BIF_CFG_DEV0_SWDS0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
164362. BIF_CFG_DEV0_SWDS0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
164363. BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
164364. BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
164365. BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
164366. BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
164367. BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
164368. BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
164369. BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
164370. BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
164371. BIF_CFG_DEV0_SWDS0_SLOT_CNTL2__RESERVED_MASK
164372. BIF_CFG_DEV0_SWDS0_SLOT_CNTL2__RESERVED__SHIFT
164373. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
164374. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
164375. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
164376. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
164377. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
164378. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
164379. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
164380. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
164381. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
164382. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
164383. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
164384. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
164385. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
164386. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
164387. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
164388. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
164389. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
164390. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
164391. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
164392. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
164393. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
164394. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
164395. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
164396. BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
164397. BIF_CFG_DEV0_SWDS0_SLOT_STATUS2__RESERVED_MASK
164398. BIF_CFG_DEV0_SWDS0_SLOT_STATUS2__RESERVED__SHIFT
164399. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
164400. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
164401. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__COMMAND_COMPLETED_MASK
164402. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
164403. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__DL_STATE_CHANGED_MASK
164404. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
164405. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
164406. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
164407. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
164408. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
164409. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_STATE_MASK
164410. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
164411. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
164412. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
164413. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
164414. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
164415. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
164416. BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
164417. BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__CAP_ID_MASK
164418. BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__CAP_ID__SHIFT
164419. BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__NEXT_PTR_MASK
164420. BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__NEXT_PTR__SHIFT
164421. BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_ID_MASK
164422. BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_ID__SHIFT
164423. BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
164424. BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
164425. BIF_CFG_DEV0_SWDS0_STATUS__CAP_LIST_MASK
164426. BIF_CFG_DEV0_SWDS0_STATUS__CAP_LIST__SHIFT
164427. BIF_CFG_DEV0_SWDS0_STATUS__DEVSEL_TIMING_MASK
164428. BIF_CFG_DEV0_SWDS0_STATUS__DEVSEL_TIMING__SHIFT
164429. BIF_CFG_DEV0_SWDS0_STATUS__FAST_BACK_CAPABLE_MASK
164430. BIF_CFG_DEV0_SWDS0_STATUS__FAST_BACK_CAPABLE__SHIFT
164431. BIF_CFG_DEV0_SWDS0_STATUS__IMMEDIATE_READINESS_MASK
164432. BIF_CFG_DEV0_SWDS0_STATUS__IMMEDIATE_READINESS__SHIFT
164433. BIF_CFG_DEV0_SWDS0_STATUS__INT_STATUS_MASK
164434. BIF_CFG_DEV0_SWDS0_STATUS__INT_STATUS__SHIFT
164435. BIF_CFG_DEV0_SWDS0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
164436. BIF_CFG_DEV0_SWDS0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
164437. BIF_CFG_DEV0_SWDS0_STATUS__PARITY_ERROR_DETECTED_MASK
164438. BIF_CFG_DEV0_SWDS0_STATUS__PARITY_ERROR_DETECTED__SHIFT
164439. BIF_CFG_DEV0_SWDS0_STATUS__PCI_66_CAP_MASK
164440. BIF_CFG_DEV0_SWDS0_STATUS__PCI_66_CAP__SHIFT
164441. BIF_CFG_DEV0_SWDS0_STATUS__PCI_66_EN_MASK
164442. BIF_CFG_DEV0_SWDS0_STATUS__PCI_66_EN__SHIFT
164443. BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_MASTER_ABORT_MASK
164444. BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
164445. BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_TARGET_ABORT_MASK
164446. BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
164447. BIF_CFG_DEV0_SWDS0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
164448. BIF_CFG_DEV0_SWDS0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
164449. BIF_CFG_DEV0_SWDS0_STATUS__SIGNAL_TARGET_ABORT_MASK
164450. BIF_CFG_DEV0_SWDS0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
164451. BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
164452. BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
164453. BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
164454. BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
164455. BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
164456. BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
164457. BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
164458. BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
164459. BIF_CFG_DEV0_SWDS0_SUB_CLASS__SUB_CLASS_MASK
164460. BIF_CFG_DEV0_SWDS0_SUB_CLASS__SUB_CLASS__SHIFT
164461. BIF_CFG_DEV0_SWDS0_VENDOR_ID__VENDOR_ID_MASK
164462. BIF_CFG_DEV0_SWDS0_VENDOR_ID__VENDOR_ID__SHIFT
164463. BIF_CFG_DEV0_SWDS1_BASE_ADDR_1__BASE_ADDR_MASK
164464. BIF_CFG_DEV0_SWDS1_BASE_ADDR_1__BASE_ADDR__SHIFT
164465. BIF_CFG_DEV0_SWDS1_BASE_ADDR_2__BASE_ADDR_MASK
164466. BIF_CFG_DEV0_SWDS1_BASE_ADDR_2__BASE_ADDR__SHIFT
164467. BIF_CFG_DEV0_SWDS1_BASE_CLASS__BASE_CLASS_MASK
164468. BIF_CFG_DEV0_SWDS1_BASE_CLASS__BASE_CLASS__SHIFT
164469. BIF_CFG_DEV0_SWDS1_BIST__BIST_CAP_MASK
164470. BIF_CFG_DEV0_SWDS1_BIST__BIST_CAP__SHIFT
164471. BIF_CFG_DEV0_SWDS1_BIST__BIST_COMP_MASK
164472. BIF_CFG_DEV0_SWDS1_BIST__BIST_COMP__SHIFT
164473. BIF_CFG_DEV0_SWDS1_BIST__BIST_STRT_MASK
164474. BIF_CFG_DEV0_SWDS1_BIST__BIST_STRT__SHIFT
164475. BIF_CFG_DEV0_SWDS1_CACHE_LINE__CACHE_LINE_SIZE_MASK
164476. BIF_CFG_DEV0_SWDS1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
164477. BIF_CFG_DEV0_SWDS1_CAP_PTR__CAP_PTR_MASK
164478. BIF_CFG_DEV0_SWDS1_CAP_PTR__CAP_PTR__SHIFT
164479. BIF_CFG_DEV0_SWDS1_COMMAND__AD_STEPPING_MASK
164480. BIF_CFG_DEV0_SWDS1_COMMAND__AD_STEPPING__SHIFT
164481. BIF_CFG_DEV0_SWDS1_COMMAND__BUS_MASTER_EN_MASK
164482. BIF_CFG_DEV0_SWDS1_COMMAND__BUS_MASTER_EN__SHIFT
164483. BIF_CFG_DEV0_SWDS1_COMMAND__FAST_B2B_EN_MASK
164484. BIF_CFG_DEV0_SWDS1_COMMAND__FAST_B2B_EN__SHIFT
164485. BIF_CFG_DEV0_SWDS1_COMMAND__INT_DIS_MASK
164486. BIF_CFG_DEV0_SWDS1_COMMAND__INT_DIS__SHIFT
164487. BIF_CFG_DEV0_SWDS1_COMMAND__IOEN_DN_MASK
164488. BIF_CFG_DEV0_SWDS1_COMMAND__IOEN_DN__SHIFT
164489. BIF_CFG_DEV0_SWDS1_COMMAND__MEMEN_DN_MASK
164490. BIF_CFG_DEV0_SWDS1_COMMAND__MEMEN_DN__SHIFT
164491. BIF_CFG_DEV0_SWDS1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
164492. BIF_CFG_DEV0_SWDS1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
164493. BIF_CFG_DEV0_SWDS1_COMMAND__PAL_SNOOP_EN_MASK
164494. BIF_CFG_DEV0_SWDS1_COMMAND__PAL_SNOOP_EN__SHIFT
164495. BIF_CFG_DEV0_SWDS1_COMMAND__PARITY_ERROR_RESPONSE_MASK
164496. BIF_CFG_DEV0_SWDS1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
164497. BIF_CFG_DEV0_SWDS1_COMMAND__SERR_EN_MASK
164498. BIF_CFG_DEV0_SWDS1_COMMAND__SERR_EN__SHIFT
164499. BIF_CFG_DEV0_SWDS1_COMMAND__SPECIAL_CYCLE_EN_MASK
164500. BIF_CFG_DEV0_SWDS1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
164501. BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK
164502. BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT
164503. BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK
164504. BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT
164505. BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK
164506. BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK
164507. BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT
164508. BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT
164509. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
164510. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
164511. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
164512. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
164513. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
164514. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
164515. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
164516. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
164517. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
164518. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
164519. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
164520. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
164521. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
164522. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
164523. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
164524. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
164525. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
164526. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
164527. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
164528. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
164529. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
164530. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
164531. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__FRS_SUPPORTED_MASK
164532. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
164533. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
164534. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
164535. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LTR_SUPPORTED_MASK
164536. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
164537. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
164538. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
164539. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
164540. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
164541. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
164542. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
164543. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
164544. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
164545. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
164546. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
164547. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
164548. BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
164549. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
164550. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
164551. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
164552. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
164553. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__EXTENDED_TAG_MASK
164554. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__EXTENDED_TAG__SHIFT
164555. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__FLR_CAPABLE_MASK
164556. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__FLR_CAPABLE__SHIFT
164557. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
164558. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
164559. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
164560. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
164561. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
164562. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
164563. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__PHANTOM_FUNC_MASK
164564. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
164565. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
164566. BIF_CFG_DEV0_SWDS1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
164567. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
164568. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
164569. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
164570. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
164571. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
164572. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
164573. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
164574. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
164575. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
164576. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
164577. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
164578. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
164579. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
164580. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
164581. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
164582. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
164583. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
164584. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
164585. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__LTR_EN_MASK
164586. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__LTR_EN__SHIFT
164587. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__OBFF_EN_MASK
164588. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__OBFF_EN__SHIFT
164589. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
164590. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
164591. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
164592. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
164593. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
164594. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
164595. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__CORR_ERR_EN_MASK
164596. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
164597. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
164598. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
164599. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__FATAL_ERR_EN_MASK
164600. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
164601. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
164602. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
164603. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
164604. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
164605. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
164606. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
164607. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NO_SNOOP_EN_MASK
164608. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
164609. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
164610. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
164611. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
164612. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
164613. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__USR_REPORT_EN_MASK
164614. BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
164615. BIF_CFG_DEV0_SWDS1_DEVICE_ID__DEVICE_ID_MASK
164616. BIF_CFG_DEV0_SWDS1_DEVICE_ID__DEVICE_ID__SHIFT
164617. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2__RESERVED_MASK
164618. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2__RESERVED__SHIFT
164619. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__AUX_PWR_MASK
164620. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__AUX_PWR__SHIFT
164621. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__CORR_ERR_MASK
164622. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__CORR_ERR__SHIFT
164623. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
164624. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
164625. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__FATAL_ERR_MASK
164626. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__FATAL_ERR__SHIFT
164627. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__NON_FATAL_ERR_MASK
164628. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
164629. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
164630. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
164631. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__USR_DETECTED_MASK
164632. BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__USR_DETECTED__SHIFT
164633. BIF_CFG_DEV0_SWDS1_HEADER__DEVICE_TYPE_MASK
164634. BIF_CFG_DEV0_SWDS1_HEADER__DEVICE_TYPE__SHIFT
164635. BIF_CFG_DEV0_SWDS1_HEADER__HEADER_TYPE_MASK
164636. BIF_CFG_DEV0_SWDS1_HEADER__HEADER_TYPE__SHIFT
164637. BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
164638. BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
164639. BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
164640. BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
164641. BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
164642. BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
164643. BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
164644. BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
164645. BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_MASK
164646. BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
164647. BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
164648. BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE__SHIFT
164649. BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_MASK
164650. BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
164651. BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
164652. BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT__SHIFT
164653. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK
164654. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT
164655. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK
164656. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT
164657. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
164658. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
164659. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__ISA_EN_MASK
164660. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
164661. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
164662. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
164663. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
164664. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
164665. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK
164666. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT
164667. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
164668. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
164669. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK
164670. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT
164671. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SERR_EN_MASK
164672. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
164673. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
164674. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
164675. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_EN_MASK
164676. BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
164677. BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK
164678. BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT
164679. BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK
164680. BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT
164681. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK
164682. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT
164683. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK
164684. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT
164685. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK
164686. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT
164687. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK
164688. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT
164689. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK
164690. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT
164691. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK
164692. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT
164693. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK
164694. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT
164695. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK
164696. BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT
164697. BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK
164698. BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT
164699. BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK
164700. BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT
164701. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK
164702. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT
164703. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK
164704. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT
164705. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK
164706. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT
164707. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK
164708. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT
164709. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK
164710. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT
164711. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK
164712. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT
164713. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK
164714. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT
164715. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK
164716. BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT
164717. BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK
164718. BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT
164719. BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK
164720. BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT
164721. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK
164722. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT
164723. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK
164724. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT
164725. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK
164726. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT
164727. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK
164728. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT
164729. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK
164730. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT
164731. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK
164732. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT
164733. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK
164734. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT
164735. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK
164736. BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT
164737. BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK
164738. BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT
164739. BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK
164740. BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT
164741. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK
164742. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT
164743. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK
164744. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT
164745. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK
164746. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT
164747. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK
164748. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT
164749. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK
164750. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT
164751. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK
164752. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT
164753. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK
164754. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT
164755. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK
164756. BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT
164757. BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK
164758. BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT
164759. BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK
164760. BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT
164761. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK
164762. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT
164763. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK
164764. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT
164765. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK
164766. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT
164767. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK
164768. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT
164769. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK
164770. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT
164771. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK
164772. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT
164773. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK
164774. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT
164775. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK
164776. BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT
164777. BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK
164778. BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT
164779. BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK
164780. BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT
164781. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK
164782. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT
164783. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK
164784. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT
164785. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK
164786. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT
164787. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK
164788. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT
164789. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK
164790. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT
164791. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK
164792. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT
164793. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK
164794. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT
164795. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK
164796. BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT
164797. BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK
164798. BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT
164799. BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK
164800. BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT
164801. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK
164802. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT
164803. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK
164804. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT
164805. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK
164806. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT
164807. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK
164808. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT
164809. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK
164810. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT
164811. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK
164812. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT
164813. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK
164814. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT
164815. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK
164816. BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT
164817. BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK
164818. BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT
164819. BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK
164820. BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT
164821. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK
164822. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT
164823. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK
164824. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT
164825. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK
164826. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT
164827. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK
164828. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT
164829. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK
164830. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT
164831. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK
164832. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT
164833. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK
164834. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT
164835. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK
164836. BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT
164837. BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK
164838. BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT
164839. BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK
164840. BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT
164841. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK
164842. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT
164843. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK
164844. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT
164845. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK
164846. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT
164847. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK
164848. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT
164849. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK
164850. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT
164851. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK
164852. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT
164853. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK
164854. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT
164855. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK
164856. BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT
164857. BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK
164858. BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT
164859. BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK
164860. BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT
164861. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK
164862. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT
164863. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK
164864. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT
164865. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK
164866. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT
164867. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK
164868. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT
164869. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK
164870. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT
164871. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK
164872. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT
164873. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK
164874. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT
164875. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK
164876. BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT
164877. BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK
164878. BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT
164879. BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK
164880. BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT
164881. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK
164882. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT
164883. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK
164884. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT
164885. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK
164886. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT
164887. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK
164888. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT
164889. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK
164890. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT
164891. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK
164892. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT
164893. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK
164894. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT
164895. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK
164896. BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT
164897. BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK
164898. BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT
164899. BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK
164900. BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT
164901. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK
164902. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT
164903. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK
164904. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT
164905. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK
164906. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT
164907. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK
164908. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT
164909. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK
164910. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT
164911. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK
164912. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT
164913. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK
164914. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT
164915. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK
164916. BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT
164917. BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK
164918. BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT
164919. BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK
164920. BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT
164921. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK
164922. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT
164923. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK
164924. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT
164925. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK
164926. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT
164927. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK
164928. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT
164929. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK
164930. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT
164931. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK
164932. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT
164933. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK
164934. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT
164935. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK
164936. BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT
164937. BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK
164938. BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT
164939. BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK
164940. BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT
164941. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK
164942. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT
164943. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK
164944. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT
164945. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK
164946. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT
164947. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK
164948. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT
164949. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK
164950. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT
164951. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK
164952. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT
164953. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK
164954. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT
164955. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK
164956. BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT
164957. BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK
164958. BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT
164959. BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK
164960. BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT
164961. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK
164962. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT
164963. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK
164964. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT
164965. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK
164966. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT
164967. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK
164968. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT
164969. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK
164970. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT
164971. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK
164972. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT
164973. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK
164974. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT
164975. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK
164976. BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT
164977. BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK
164978. BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT
164979. BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK
164980. BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT
164981. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK
164982. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT
164983. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK
164984. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT
164985. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK
164986. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT
164987. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK
164988. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT
164989. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK
164990. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT
164991. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK
164992. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT
164993. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK
164994. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT
164995. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK
164996. BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT
164997. BIF_CFG_DEV0_SWDS1_LATENCY__LATENCY_TIMER_MASK
164998. BIF_CFG_DEV0_SWDS1_LATENCY__LATENCY_TIMER__SHIFT
164999. BIF_CFG_DEV0_SWDS1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
165000. BIF_CFG_DEV0_SWDS1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
165001. BIF_CFG_DEV0_SWDS1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
165002. BIF_CFG_DEV0_SWDS1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
165003. BIF_CFG_DEV0_SWDS1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
165004. BIF_CFG_DEV0_SWDS1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
165005. BIF_CFG_DEV0_SWDS1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
165006. BIF_CFG_DEV0_SWDS1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
165007. BIF_CFG_DEV0_SWDS1_LINK_CAP2__RESERVED_MASK
165008. BIF_CFG_DEV0_SWDS1_LINK_CAP2__RESERVED__SHIFT
165009. BIF_CFG_DEV0_SWDS1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
165010. BIF_CFG_DEV0_SWDS1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
165011. BIF_CFG_DEV0_SWDS1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
165012. BIF_CFG_DEV0_SWDS1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
165013. BIF_CFG_DEV0_SWDS1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
165014. BIF_CFG_DEV0_SWDS1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
165015. BIF_CFG_DEV0_SWDS1_LINK_CAP_16GT__RESERVED_MASK
165016. BIF_CFG_DEV0_SWDS1_LINK_CAP_16GT__RESERVED__SHIFT
165017. BIF_CFG_DEV0_SWDS1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
165018. BIF_CFG_DEV0_SWDS1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
165019. BIF_CFG_DEV0_SWDS1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
165020. BIF_CFG_DEV0_SWDS1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
165021. BIF_CFG_DEV0_SWDS1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
165022. BIF_CFG_DEV0_SWDS1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
165023. BIF_CFG_DEV0_SWDS1_LINK_CAP__L0S_EXIT_LATENCY_MASK
165024. BIF_CFG_DEV0_SWDS1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
165025. BIF_CFG_DEV0_SWDS1_LINK_CAP__L1_EXIT_LATENCY_MASK
165026. BIF_CFG_DEV0_SWDS1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
165027. BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
165028. BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
165029. BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_SPEED_MASK
165030. BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_SPEED__SHIFT
165031. BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_WIDTH_MASK
165032. BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_WIDTH__SHIFT
165033. BIF_CFG_DEV0_SWDS1_LINK_CAP__PM_SUPPORT_MASK
165034. BIF_CFG_DEV0_SWDS1_LINK_CAP__PM_SUPPORT__SHIFT
165035. BIF_CFG_DEV0_SWDS1_LINK_CAP__PORT_NUMBER_MASK
165036. BIF_CFG_DEV0_SWDS1_LINK_CAP__PORT_NUMBER__SHIFT
165037. BIF_CFG_DEV0_SWDS1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
165038. BIF_CFG_DEV0_SWDS1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
165039. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
165040. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
165041. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_SOS_MASK
165042. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
165043. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
165044. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
165045. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
165046. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
165047. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
165048. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
165049. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
165050. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
165051. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
165052. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
165053. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__XMIT_MARGIN_MASK
165054. BIF_CFG_DEV0_SWDS1_LINK_CNTL2__XMIT_MARGIN__SHIFT
165055. BIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT__RESERVED_MASK
165056. BIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT__RESERVED__SHIFT
165057. BIF_CFG_DEV0_SWDS1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
165058. BIF_CFG_DEV0_SWDS1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
165059. BIF_CFG_DEV0_SWDS1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
165060. BIF_CFG_DEV0_SWDS1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
165061. BIF_CFG_DEV0_SWDS1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
165062. BIF_CFG_DEV0_SWDS1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
165063. BIF_CFG_DEV0_SWDS1_LINK_CNTL__EXTENDED_SYNC_MASK
165064. BIF_CFG_DEV0_SWDS1_LINK_CNTL__EXTENDED_SYNC__SHIFT
165065. BIF_CFG_DEV0_SWDS1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
165066. BIF_CFG_DEV0_SWDS1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
165067. BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
165068. BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
165069. BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
165070. BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
165071. BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_DIS_MASK
165072. BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_DIS__SHIFT
165073. BIF_CFG_DEV0_SWDS1_LINK_CNTL__PM_CONTROL_MASK
165074. BIF_CFG_DEV0_SWDS1_LINK_CNTL__PM_CONTROL__SHIFT
165075. BIF_CFG_DEV0_SWDS1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
165076. BIF_CFG_DEV0_SWDS1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
165077. BIF_CFG_DEV0_SWDS1_LINK_CNTL__RETRAIN_LINK_MASK
165078. BIF_CFG_DEV0_SWDS1_LINK_CNTL__RETRAIN_LINK__SHIFT
165079. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
165080. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
165081. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
165082. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
165083. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
165084. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
165085. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
165086. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
165087. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
165088. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
165089. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
165090. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
165091. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
165092. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
165093. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
165094. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
165095. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
165096. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
165097. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
165098. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
165099. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
165100. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
165101. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
165102. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
165103. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
165104. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
165105. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
165106. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
165107. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
165108. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
165109. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
165110. BIF_CFG_DEV0_SWDS1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
165111. BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK
165112. BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT
165113. BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK
165114. BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT
165115. BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK
165116. BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT
165117. BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK
165118. BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT
165119. BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK
165120. BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT
165121. BIF_CFG_DEV0_SWDS1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
165122. BIF_CFG_DEV0_SWDS1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
165123. BIF_CFG_DEV0_SWDS1_LINK_STATUS__DL_ACTIVE_MASK
165124. BIF_CFG_DEV0_SWDS1_LINK_STATUS__DL_ACTIVE__SHIFT
165125. BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
165126. BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
165127. BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
165128. BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
165129. BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_TRAINING_MASK
165130. BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_TRAINING__SHIFT
165131. BIF_CFG_DEV0_SWDS1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
165132. BIF_CFG_DEV0_SWDS1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
165133. BIF_CFG_DEV0_SWDS1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
165134. BIF_CFG_DEV0_SWDS1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
165135. BIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK
165136. BIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT
165137. BIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK
165138. BIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT
165139. BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS__MARGINING_READY_MASK
165140. BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT
165141. BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK
165142. BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT
165143. BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
165144. BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
165145. BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
165146. BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
165147. BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
165148. BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
165149. BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
165150. BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
165151. BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__CAP_ID_MASK
165152. BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__CAP_ID__SHIFT
165153. BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__NEXT_PTR_MASK
165154. BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__NEXT_PTR__SHIFT
165155. BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
165156. BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
165157. BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
165158. BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
165159. BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_64BIT_MASK
165160. BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
165161. BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_EN_MASK
165162. BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_EN__SHIFT
165163. BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
165164. BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
165165. BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
165166. BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
165167. BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
165168. BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
165169. BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
165170. BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
165171. BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA__MSI_DATA_MASK
165172. BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA__MSI_DATA__SHIFT
165173. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
165174. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
165175. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
165176. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
165177. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
165178. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
165179. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
165180. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
165181. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
165182. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
165183. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
165184. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
165185. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
165186. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
165187. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
165188. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
165189. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
165190. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
165191. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
165192. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
165193. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
165194. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
165195. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
165196. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
165197. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
165198. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
165199. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
165200. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
165201. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
165202. BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
165203. BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
165204. BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
165205. BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
165206. BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
165207. BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
165208. BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
165209. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
165210. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
165211. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
165212. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
165213. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
165214. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
165215. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
165216. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
165217. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
165218. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
165219. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
165220. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
165221. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
165222. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
165223. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
165224. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
165225. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
165226. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
165227. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
165228. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
165229. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
165230. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
165231. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
165232. BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
165233. BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__CAP_ID_MASK
165234. BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__CAP_ID__SHIFT
165235. BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__NEXT_PTR_MASK
165236. BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
165237. BIF_CFG_DEV0_SWDS1_PCIE_CAP__DEVICE_TYPE_MASK
165238. BIF_CFG_DEV0_SWDS1_PCIE_CAP__DEVICE_TYPE__SHIFT
165239. BIF_CFG_DEV0_SWDS1_PCIE_CAP__INT_MESSAGE_NUM_MASK
165240. BIF_CFG_DEV0_SWDS1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
165241. BIF_CFG_DEV0_SWDS1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
165242. BIF_CFG_DEV0_SWDS1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
165243. BIF_CFG_DEV0_SWDS1_PCIE_CAP__VERSION_MASK
165244. BIF_CFG_DEV0_SWDS1_PCIE_CAP__VERSION__SHIFT
165245. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
165246. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
165247. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
165248. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
165249. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
165250. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
165251. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
165252. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
165253. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
165254. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
165255. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
165256. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
165257. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
165258. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
165259. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
165260. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
165261. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
165262. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
165263. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
165264. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
165265. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
165266. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
165267. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
165268. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
165269. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
165270. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
165271. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
165272. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
165273. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
165274. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
165275. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
165276. BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
165277. BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
165278. BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
165279. BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
165280. BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
165281. BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
165282. BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
165283. BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
165284. BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
165285. BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
165286. BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
165287. BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK
165288. BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT
165289. BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK
165290. BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT
165291. BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK
165292. BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT
165293. BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0__TLP_HDR_MASK
165294. BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
165295. BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1__TLP_HDR_MASK
165296. BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
165297. BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2__TLP_HDR_MASK
165298. BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
165299. BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3__TLP_HDR_MASK
165300. BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
165301. BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165302. BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165303. BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165304. BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165305. BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
165306. BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
165307. BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165308. BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165309. BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165310. BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165311. BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165312. BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165313. BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165314. BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165315. BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
165316. BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
165317. BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165318. BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165319. BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165320. BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165321. BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165322. BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165323. BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165324. BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165325. BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
165326. BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
165327. BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165328. BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165329. BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165330. BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165331. BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165332. BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165333. BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165334. BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165335. BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
165336. BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
165337. BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165338. BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165339. BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165340. BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165341. BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165342. BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165343. BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165344. BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165345. BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
165346. BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
165347. BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165348. BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165349. BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165350. BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165351. BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165352. BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165353. BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165354. BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165355. BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
165356. BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
165357. BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165358. BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165359. BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165360. BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165361. BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165362. BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165363. BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165364. BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165365. BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
165366. BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
165367. BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165368. BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165369. BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165370. BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165371. BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165372. BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165373. BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165374. BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165375. BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
165376. BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
165377. BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165378. BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165379. BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165380. BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165381. BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165382. BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165383. BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165384. BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165385. BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
165386. BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
165387. BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165388. BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165389. BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165390. BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165391. BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165392. BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165393. BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165394. BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165395. BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
165396. BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
165397. BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165398. BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165399. BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165400. BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165401. BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165402. BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165403. BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165404. BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165405. BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
165406. BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
165407. BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165408. BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165409. BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165410. BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165411. BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165412. BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165413. BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165414. BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165415. BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
165416. BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
165417. BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165418. BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165419. BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165420. BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165421. BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165422. BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165423. BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165424. BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165425. BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
165426. BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
165427. BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165428. BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165429. BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165430. BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165431. BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165432. BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165433. BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165434. BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165435. BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
165436. BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
165437. BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165438. BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165439. BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165440. BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165441. BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165442. BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165443. BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165444. BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165445. BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
165446. BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
165447. BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165448. BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165449. BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165450. BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165451. BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
165452. BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
165453. BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
165454. BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
165455. BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
165456. BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
165457. BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
165458. BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
165459. BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
165460. BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
165461. BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
165462. BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
165463. BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
165464. BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
165465. BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
165466. BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
165467. BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
165468. BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
165469. BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
165470. BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
165471. BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__RESERVED_MASK
165472. BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__RESERVED__SHIFT
165473. BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
165474. BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
165475. BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
165476. BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
165477. BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
165478. BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
165479. BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
165480. BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
165481. BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
165482. BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
165483. BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
165484. BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
165485. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
165486. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
165487. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
165488. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
165489. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
165490. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
165491. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
165492. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
165493. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
165494. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
165495. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
165496. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
165497. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
165498. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
165499. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
165500. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
165501. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
165502. BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
165503. BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
165504. BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
165505. BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
165506. BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
165507. BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
165508. BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
165509. BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
165510. BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
165511. BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
165512. BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
165513. BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
165514. BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
165515. BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
165516. BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
165517. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
165518. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
165519. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
165520. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
165521. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
165522. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
165523. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
165524. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
165525. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
165526. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
165527. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
165528. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
165529. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
165530. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
165531. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
165532. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
165533. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
165534. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
165535. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
165536. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
165537. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
165538. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
165539. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
165540. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
165541. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
165542. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
165543. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
165544. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
165545. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
165546. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
165547. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
165548. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
165549. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
165550. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
165551. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
165552. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
165553. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
165554. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
165555. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
165556. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
165557. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
165558. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
165559. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
165560. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
165561. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
165562. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
165563. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
165564. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
165565. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
165566. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
165567. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
165568. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
165569. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
165570. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
165571. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
165572. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
165573. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
165574. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
165575. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
165576. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
165577. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
165578. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
165579. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
165580. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
165581. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
165582. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
165583. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
165584. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
165585. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
165586. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
165587. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
165588. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
165589. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
165590. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
165591. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
165592. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
165593. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
165594. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
165595. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
165596. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
165597. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
165598. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
165599. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
165600. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
165601. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
165602. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
165603. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
165604. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
165605. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
165606. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
165607. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
165608. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
165609. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
165610. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
165611. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
165612. BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
165613. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
165614. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
165615. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
165616. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
165617. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
165618. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
165619. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
165620. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
165621. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
165622. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
165623. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
165624. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
165625. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
165626. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
165627. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
165628. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
165629. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
165630. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
165631. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
165632. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
165633. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
165634. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
165635. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
165636. BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
165637. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
165638. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
165639. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
165640. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
165641. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
165642. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
165643. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
165644. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
165645. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
165646. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
165647. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
165648. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
165649. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
165650. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
165651. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
165652. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
165653. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
165654. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
165655. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
165656. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
165657. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
165658. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
165659. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
165660. BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
165661. BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
165662. BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
165663. BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
165664. BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
165665. BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
165666. BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
165667. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
165668. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
165669. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
165670. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
165671. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
165672. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
165673. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
165674. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
165675. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
165676. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
165677. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
165678. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
165679. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
165680. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
165681. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
165682. BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
165683. BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__CAP_ID_MASK
165684. BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__CAP_ID__SHIFT
165685. BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__NEXT_PTR_MASK
165686. BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__NEXT_PTR__SHIFT
165687. BIF_CFG_DEV0_SWDS1_PMI_CAP__AUX_CURRENT_MASK
165688. BIF_CFG_DEV0_SWDS1_PMI_CAP__AUX_CURRENT__SHIFT
165689. BIF_CFG_DEV0_SWDS1_PMI_CAP__D1_SUPPORT_MASK
165690. BIF_CFG_DEV0_SWDS1_PMI_CAP__D1_SUPPORT__SHIFT
165691. BIF_CFG_DEV0_SWDS1_PMI_CAP__D2_SUPPORT_MASK
165692. BIF_CFG_DEV0_SWDS1_PMI_CAP__D2_SUPPORT__SHIFT
165693. BIF_CFG_DEV0_SWDS1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
165694. BIF_CFG_DEV0_SWDS1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
165695. BIF_CFG_DEV0_SWDS1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
165696. BIF_CFG_DEV0_SWDS1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
165697. BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_CLOCK_MASK
165698. BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_CLOCK__SHIFT
165699. BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_SUPPORT_MASK
165700. BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_SUPPORT__SHIFT
165701. BIF_CFG_DEV0_SWDS1_PMI_CAP__VERSION_MASK
165702. BIF_CFG_DEV0_SWDS1_PMI_CAP__VERSION__SHIFT
165703. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
165704. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
165705. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
165706. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
165707. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SCALE_MASK
165708. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
165709. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SELECT_MASK
165710. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
165711. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
165712. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
165713. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_EN_MASK
165714. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_EN__SHIFT
165715. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_STATUS_MASK
165716. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
165717. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PMI_DATA_MASK
165718. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
165719. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__POWER_STATE_MASK
165720. BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
165721. BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
165722. BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
165723. BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
165724. BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
165725. BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
165726. BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
165727. BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
165728. BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
165729. BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
165730. BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
165731. BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
165732. BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
165733. BIF_CFG_DEV0_SWDS1_PROG_INTERFACE__PROG_INTERFACE_MASK
165734. BIF_CFG_DEV0_SWDS1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
165735. BIF_CFG_DEV0_SWDS1_REVISION_ID__MAJOR_REV_ID_MASK
165736. BIF_CFG_DEV0_SWDS1_REVISION_ID__MAJOR_REV_ID__SHIFT
165737. BIF_CFG_DEV0_SWDS1_REVISION_ID__MINOR_REV_ID_MASK
165738. BIF_CFG_DEV0_SWDS1_REVISION_ID__MINOR_REV_ID__SHIFT
165739. BIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR__BASE_ADDR_MASK
165740. BIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
165741. BIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK
165742. BIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT
165743. BIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK
165744. BIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT
165745. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__CAP_LIST_MASK
165746. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__CAP_LIST__SHIFT
165747. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__DEVSEL_TIMING_MASK
165748. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
165749. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
165750. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
165751. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
165752. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
165753. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
165754. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
165755. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PCI_66_CAP_MASK
165756. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PCI_66_CAP__SHIFT
165757. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PCI_66_EN_MASK
165758. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PCI_66_EN__SHIFT
165759. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
165760. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
165761. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
165762. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
165763. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
165764. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
165765. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
165766. BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
165767. BIF_CFG_DEV0_SWDS1_SLOT_CAP2__RESERVED_MASK
165768. BIF_CFG_DEV0_SWDS1_SLOT_CAP2__RESERVED__SHIFT
165769. BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
165770. BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
165771. BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
165772. BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
165773. BIF_CFG_DEV0_SWDS1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
165774. BIF_CFG_DEV0_SWDS1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
165775. BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_CAPABLE_MASK
165776. BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
165777. BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_SURPRISE_MASK
165778. BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
165779. BIF_CFG_DEV0_SWDS1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
165780. BIF_CFG_DEV0_SWDS1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
165781. BIF_CFG_DEV0_SWDS1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
165782. BIF_CFG_DEV0_SWDS1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
165783. BIF_CFG_DEV0_SWDS1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
165784. BIF_CFG_DEV0_SWDS1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
165785. BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
165786. BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
165787. BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
165788. BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
165789. BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
165790. BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
165791. BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
165792. BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
165793. BIF_CFG_DEV0_SWDS1_SLOT_CNTL2__RESERVED_MASK
165794. BIF_CFG_DEV0_SWDS1_SLOT_CNTL2__RESERVED__SHIFT
165795. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
165796. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
165797. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
165798. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
165799. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK
165800. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT
165801. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
165802. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
165803. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
165804. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
165805. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
165806. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
165807. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
165808. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
165809. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
165810. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
165811. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
165812. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
165813. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
165814. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
165815. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
165816. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
165817. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
165818. BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
165819. BIF_CFG_DEV0_SWDS1_SLOT_STATUS2__RESERVED_MASK
165820. BIF_CFG_DEV0_SWDS1_SLOT_STATUS2__RESERVED__SHIFT
165821. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
165822. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
165823. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__COMMAND_COMPLETED_MASK
165824. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
165825. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__DL_STATE_CHANGED_MASK
165826. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
165827. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
165828. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
165829. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
165830. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
165831. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_STATE_MASK
165832. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
165833. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
165834. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
165835. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
165836. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
165837. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
165838. BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
165839. BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__CAP_ID_MASK
165840. BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__CAP_ID__SHIFT
165841. BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__NEXT_PTR_MASK
165842. BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__NEXT_PTR__SHIFT
165843. BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_ID_MASK
165844. BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_ID__SHIFT
165845. BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
165846. BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
165847. BIF_CFG_DEV0_SWDS1_STATUS__CAP_LIST_MASK
165848. BIF_CFG_DEV0_SWDS1_STATUS__CAP_LIST__SHIFT
165849. BIF_CFG_DEV0_SWDS1_STATUS__DEVSEL_TIMING_MASK
165850. BIF_CFG_DEV0_SWDS1_STATUS__DEVSEL_TIMING__SHIFT
165851. BIF_CFG_DEV0_SWDS1_STATUS__FAST_BACK_CAPABLE_MASK
165852. BIF_CFG_DEV0_SWDS1_STATUS__FAST_BACK_CAPABLE__SHIFT
165853. BIF_CFG_DEV0_SWDS1_STATUS__IMMEDIATE_READINESS_MASK
165854. BIF_CFG_DEV0_SWDS1_STATUS__IMMEDIATE_READINESS__SHIFT
165855. BIF_CFG_DEV0_SWDS1_STATUS__INT_STATUS_MASK
165856. BIF_CFG_DEV0_SWDS1_STATUS__INT_STATUS__SHIFT
165857. BIF_CFG_DEV0_SWDS1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
165858. BIF_CFG_DEV0_SWDS1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
165859. BIF_CFG_DEV0_SWDS1_STATUS__PARITY_ERROR_DETECTED_MASK
165860. BIF_CFG_DEV0_SWDS1_STATUS__PARITY_ERROR_DETECTED__SHIFT
165861. BIF_CFG_DEV0_SWDS1_STATUS__PCI_66_CAP_MASK
165862. BIF_CFG_DEV0_SWDS1_STATUS__PCI_66_CAP__SHIFT
165863. BIF_CFG_DEV0_SWDS1_STATUS__PCI_66_EN_MASK
165864. BIF_CFG_DEV0_SWDS1_STATUS__PCI_66_EN__SHIFT
165865. BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_MASTER_ABORT_MASK
165866. BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
165867. BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_TARGET_ABORT_MASK
165868. BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
165869. BIF_CFG_DEV0_SWDS1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
165870. BIF_CFG_DEV0_SWDS1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
165871. BIF_CFG_DEV0_SWDS1_STATUS__SIGNAL_TARGET_ABORT_MASK
165872. BIF_CFG_DEV0_SWDS1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
165873. BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
165874. BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
165875. BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
165876. BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
165877. BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
165878. BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
165879. BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
165880. BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
165881. BIF_CFG_DEV0_SWDS1_SUB_CLASS__SUB_CLASS_MASK
165882. BIF_CFG_DEV0_SWDS1_SUB_CLASS__SUB_CLASS__SHIFT
165883. BIF_CFG_DEV0_SWDS1_VENDOR_ID__VENDOR_ID_MASK
165884. BIF_CFG_DEV0_SWDS1_VENDOR_ID__VENDOR_ID__SHIFT
165885. BIF_CFG_DEV0_SWDS_BASE_ADDR_1__BASE_ADDR_MASK
165886. BIF_CFG_DEV0_SWDS_BASE_ADDR_1__BASE_ADDR__SHIFT
165887. BIF_CFG_DEV0_SWDS_BASE_ADDR_2__BASE_ADDR_MASK
165888. BIF_CFG_DEV0_SWDS_BASE_ADDR_2__BASE_ADDR__SHIFT
165889. BIF_CFG_DEV0_SWDS_BASE_CLASS__BASE_CLASS_MASK
165890. BIF_CFG_DEV0_SWDS_BASE_CLASS__BASE_CLASS__SHIFT
165891. BIF_CFG_DEV0_SWDS_BIST__BIST_CAP_MASK
165892. BIF_CFG_DEV0_SWDS_BIST__BIST_CAP__SHIFT
165893. BIF_CFG_DEV0_SWDS_BIST__BIST_COMP_MASK
165894. BIF_CFG_DEV0_SWDS_BIST__BIST_COMP__SHIFT
165895. BIF_CFG_DEV0_SWDS_BIST__BIST_STRT_MASK
165896. BIF_CFG_DEV0_SWDS_BIST__BIST_STRT__SHIFT
165897. BIF_CFG_DEV0_SWDS_CACHE_LINE__CACHE_LINE_SIZE_MASK
165898. BIF_CFG_DEV0_SWDS_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
165899. BIF_CFG_DEV0_SWDS_CAP_PTR__CAP_PTR_MASK
165900. BIF_CFG_DEV0_SWDS_CAP_PTR__CAP_PTR__SHIFT
165901. BIF_CFG_DEV0_SWDS_COMMAND__AD_STEPPING_MASK
165902. BIF_CFG_DEV0_SWDS_COMMAND__AD_STEPPING__SHIFT
165903. BIF_CFG_DEV0_SWDS_COMMAND__BUS_MASTER_EN_MASK
165904. BIF_CFG_DEV0_SWDS_COMMAND__BUS_MASTER_EN__SHIFT
165905. BIF_CFG_DEV0_SWDS_COMMAND__FAST_B2B_EN_MASK
165906. BIF_CFG_DEV0_SWDS_COMMAND__FAST_B2B_EN__SHIFT
165907. BIF_CFG_DEV0_SWDS_COMMAND__INT_DIS_MASK
165908. BIF_CFG_DEV0_SWDS_COMMAND__INT_DIS__SHIFT
165909. BIF_CFG_DEV0_SWDS_COMMAND__IOEN_DN_MASK
165910. BIF_CFG_DEV0_SWDS_COMMAND__IOEN_DN__SHIFT
165911. BIF_CFG_DEV0_SWDS_COMMAND__MEMEN_DN_MASK
165912. BIF_CFG_DEV0_SWDS_COMMAND__MEMEN_DN__SHIFT
165913. BIF_CFG_DEV0_SWDS_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
165914. BIF_CFG_DEV0_SWDS_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
165915. BIF_CFG_DEV0_SWDS_COMMAND__PAL_SNOOP_EN_MASK
165916. BIF_CFG_DEV0_SWDS_COMMAND__PAL_SNOOP_EN__SHIFT
165917. BIF_CFG_DEV0_SWDS_COMMAND__PARITY_ERROR_RESPONSE_MASK
165918. BIF_CFG_DEV0_SWDS_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
165919. BIF_CFG_DEV0_SWDS_COMMAND__SERR_EN_MASK
165920. BIF_CFG_DEV0_SWDS_COMMAND__SERR_EN__SHIFT
165921. BIF_CFG_DEV0_SWDS_COMMAND__SPECIAL_CYCLE_EN_MASK
165922. BIF_CFG_DEV0_SWDS_COMMAND__SPECIAL_CYCLE_EN__SHIFT
165923. BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK
165924. BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT
165925. BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK
165926. BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT
165927. BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK
165928. BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK
165929. BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT
165930. BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT
165931. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
165932. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
165933. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
165934. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
165935. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
165936. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
165937. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
165938. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
165939. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
165940. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
165941. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
165942. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
165943. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
165944. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
165945. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK
165946. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT
165947. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK
165948. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT
165949. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
165950. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
165951. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
165952. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
165953. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__FRS_SUPPORTED_MASK
165954. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
165955. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
165956. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
165957. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__LTR_SUPPORTED_MASK
165958. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
165959. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
165960. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
165961. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
165962. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
165963. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__OBFF_SUPPORTED_MASK
165964. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
165965. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
165966. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
165967. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
165968. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
165969. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
165970. BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
165971. BIF_CFG_DEV0_SWDS_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
165972. BIF_CFG_DEV0_SWDS_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
165973. BIF_CFG_DEV0_SWDS_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
165974. BIF_CFG_DEV0_SWDS_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
165975. BIF_CFG_DEV0_SWDS_DEVICE_CAP__EXTENDED_TAG_MASK
165976. BIF_CFG_DEV0_SWDS_DEVICE_CAP__EXTENDED_TAG__SHIFT
165977. BIF_CFG_DEV0_SWDS_DEVICE_CAP__FLR_CAPABLE_MASK
165978. BIF_CFG_DEV0_SWDS_DEVICE_CAP__FLR_CAPABLE__SHIFT
165979. BIF_CFG_DEV0_SWDS_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
165980. BIF_CFG_DEV0_SWDS_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
165981. BIF_CFG_DEV0_SWDS_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
165982. BIF_CFG_DEV0_SWDS_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
165983. BIF_CFG_DEV0_SWDS_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
165984. BIF_CFG_DEV0_SWDS_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
165985. BIF_CFG_DEV0_SWDS_DEVICE_CAP__PHANTOM_FUNC_MASK
165986. BIF_CFG_DEV0_SWDS_DEVICE_CAP__PHANTOM_FUNC__SHIFT
165987. BIF_CFG_DEV0_SWDS_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
165988. BIF_CFG_DEV0_SWDS_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
165989. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
165990. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
165991. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
165992. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
165993. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
165994. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
165995. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
165996. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
165997. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
165998. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
165999. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
166000. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
166001. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
166002. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
166003. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
166004. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
166005. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
166006. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
166007. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__LTR_EN_MASK
166008. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__LTR_EN__SHIFT
166009. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__OBFF_EN_MASK
166010. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__OBFF_EN__SHIFT
166011. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
166012. BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
166013. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
166014. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
166015. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
166016. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
166017. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__CORR_ERR_EN_MASK
166018. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__CORR_ERR_EN__SHIFT
166019. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
166020. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
166021. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__FATAL_ERR_EN_MASK
166022. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
166023. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
166024. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
166025. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
166026. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
166027. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
166028. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
166029. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__NO_SNOOP_EN_MASK
166030. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
166031. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
166032. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
166033. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__RELAXED_ORD_EN_MASK
166034. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
166035. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__USR_REPORT_EN_MASK
166036. BIF_CFG_DEV0_SWDS_DEVICE_CNTL__USR_REPORT_EN__SHIFT
166037. BIF_CFG_DEV0_SWDS_DEVICE_ID__DEVICE_ID_MASK
166038. BIF_CFG_DEV0_SWDS_DEVICE_ID__DEVICE_ID__SHIFT
166039. BIF_CFG_DEV0_SWDS_DEVICE_STATUS2__RESERVED_MASK
166040. BIF_CFG_DEV0_SWDS_DEVICE_STATUS2__RESERVED__SHIFT
166041. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__AUX_PWR_MASK
166042. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__AUX_PWR__SHIFT
166043. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__CORR_ERR_MASK
166044. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__CORR_ERR__SHIFT
166045. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK
166046. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT
166047. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__FATAL_ERR_MASK
166048. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__FATAL_ERR__SHIFT
166049. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__NON_FATAL_ERR_MASK
166050. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
166051. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
166052. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
166053. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__USR_DETECTED_MASK
166054. BIF_CFG_DEV0_SWDS_DEVICE_STATUS__USR_DETECTED__SHIFT
166055. BIF_CFG_DEV0_SWDS_HEADER__DEVICE_TYPE_MASK
166056. BIF_CFG_DEV0_SWDS_HEADER__DEVICE_TYPE__SHIFT
166057. BIF_CFG_DEV0_SWDS_HEADER__HEADER_TYPE_MASK
166058. BIF_CFG_DEV0_SWDS_HEADER__HEADER_TYPE__SHIFT
166059. BIF_CFG_DEV0_SWDS_INTERRUPT_LINE__INTERRUPT_LINE_MASK
166060. BIF_CFG_DEV0_SWDS_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
166061. BIF_CFG_DEV0_SWDS_INTERRUPT_PIN__INTERRUPT_PIN_MASK
166062. BIF_CFG_DEV0_SWDS_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
166063. BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK
166064. BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT
166065. BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK
166066. BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT
166067. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK
166068. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT
166069. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK
166070. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT
166071. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK
166072. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT
166073. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK
166074. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT
166075. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK
166076. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT
166077. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK
166078. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT
166079. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK
166080. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT
166081. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK
166082. BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT
166083. BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK
166084. BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT
166085. BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK
166086. BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT
166087. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK
166088. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT
166089. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK
166090. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT
166091. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK
166092. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT
166093. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK
166094. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT
166095. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK
166096. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT
166097. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK
166098. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT
166099. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK
166100. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT
166101. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK
166102. BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT
166103. BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK
166104. BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT
166105. BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK
166106. BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT
166107. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK
166108. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT
166109. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK
166110. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT
166111. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK
166112. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT
166113. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK
166114. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT
166115. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK
166116. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT
166117. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK
166118. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT
166119. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK
166120. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT
166121. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK
166122. BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT
166123. BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK
166124. BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT
166125. BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK
166126. BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT
166127. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK
166128. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT
166129. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK
166130. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT
166131. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK
166132. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT
166133. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK
166134. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT
166135. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK
166136. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT
166137. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK
166138. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT
166139. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK
166140. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT
166141. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK
166142. BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT
166143. BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK
166144. BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT
166145. BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK
166146. BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT
166147. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK
166148. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT
166149. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK
166150. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT
166151. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK
166152. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT
166153. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK
166154. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT
166155. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK
166156. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT
166157. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK
166158. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT
166159. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK
166160. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT
166161. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK
166162. BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT
166163. BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK
166164. BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT
166165. BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK
166166. BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT
166167. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK
166168. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT
166169. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK
166170. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT
166171. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK
166172. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT
166173. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK
166174. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT
166175. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK
166176. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT
166177. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK
166178. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT
166179. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK
166180. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT
166181. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK
166182. BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT
166183. BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK
166184. BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT
166185. BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK
166186. BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT
166187. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK
166188. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT
166189. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK
166190. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT
166191. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK
166192. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT
166193. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK
166194. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT
166195. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK
166196. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT
166197. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK
166198. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT
166199. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK
166200. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT
166201. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK
166202. BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT
166203. BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK
166204. BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT
166205. BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK
166206. BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT
166207. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK
166208. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT
166209. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK
166210. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT
166211. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK
166212. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT
166213. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK
166214. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT
166215. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK
166216. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT
166217. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK
166218. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT
166219. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK
166220. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT
166221. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK
166222. BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT
166223. BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK
166224. BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT
166225. BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK
166226. BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT
166227. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK
166228. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT
166229. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK
166230. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT
166231. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK
166232. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT
166233. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK
166234. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT
166235. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK
166236. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT
166237. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK
166238. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT
166239. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK
166240. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT
166241. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK
166242. BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT
166243. BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK
166244. BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT
166245. BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK
166246. BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT
166247. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK
166248. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT
166249. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK
166250. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT
166251. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK
166252. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT
166253. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK
166254. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT
166255. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK
166256. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT
166257. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK
166258. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT
166259. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK
166260. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT
166261. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK
166262. BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT
166263. BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK
166264. BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT
166265. BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK
166266. BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT
166267. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK
166268. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT
166269. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK
166270. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT
166271. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK
166272. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT
166273. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK
166274. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT
166275. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK
166276. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT
166277. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK
166278. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT
166279. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK
166280. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT
166281. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK
166282. BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT
166283. BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK
166284. BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT
166285. BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK
166286. BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT
166287. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK
166288. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT
166289. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK
166290. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT
166291. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK
166292. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT
166293. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK
166294. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT
166295. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK
166296. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT
166297. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK
166298. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT
166299. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK
166300. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT
166301. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK
166302. BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT
166303. BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK
166304. BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT
166305. BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK
166306. BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT
166307. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK
166308. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT
166309. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK
166310. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT
166311. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK
166312. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT
166313. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK
166314. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT
166315. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK
166316. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT
166317. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK
166318. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT
166319. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK
166320. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT
166321. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK
166322. BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT
166323. BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK
166324. BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT
166325. BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK
166326. BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT
166327. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK
166328. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT
166329. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK
166330. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT
166331. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK
166332. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT
166333. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK
166334. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT
166335. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK
166336. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT
166337. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK
166338. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT
166339. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK
166340. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT
166341. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK
166342. BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT
166343. BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK
166344. BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT
166345. BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK
166346. BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT
166347. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK
166348. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT
166349. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK
166350. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT
166351. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK
166352. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT
166353. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK
166354. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT
166355. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK
166356. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT
166357. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK
166358. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT
166359. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK
166360. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT
166361. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK
166362. BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT
166363. BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK
166364. BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT
166365. BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK
166366. BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT
166367. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK
166368. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT
166369. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK
166370. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT
166371. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK
166372. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT
166373. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK
166374. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT
166375. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK
166376. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT
166377. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK
166378. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT
166379. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK
166380. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT
166381. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK
166382. BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT
166383. BIF_CFG_DEV0_SWDS_LATENCY__LATENCY_TIMER_MASK
166384. BIF_CFG_DEV0_SWDS_LATENCY__LATENCY_TIMER__SHIFT
166385. BIF_CFG_DEV0_SWDS_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
166386. BIF_CFG_DEV0_SWDS_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
166387. BIF_CFG_DEV0_SWDS_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK
166388. BIF_CFG_DEV0_SWDS_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT
166389. BIF_CFG_DEV0_SWDS_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
166390. BIF_CFG_DEV0_SWDS_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
166391. BIF_CFG_DEV0_SWDS_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
166392. BIF_CFG_DEV0_SWDS_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
166393. BIF_CFG_DEV0_SWDS_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
166394. BIF_CFG_DEV0_SWDS_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
166395. BIF_CFG_DEV0_SWDS_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
166396. BIF_CFG_DEV0_SWDS_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
166397. BIF_CFG_DEV0_SWDS_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
166398. BIF_CFG_DEV0_SWDS_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
166399. BIF_CFG_DEV0_SWDS_LINK_CAP_16GT__RESERVED_MASK
166400. BIF_CFG_DEV0_SWDS_LINK_CAP_16GT__RESERVED__SHIFT
166401. BIF_CFG_DEV0_SWDS_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
166402. BIF_CFG_DEV0_SWDS_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
166403. BIF_CFG_DEV0_SWDS_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
166404. BIF_CFG_DEV0_SWDS_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
166405. BIF_CFG_DEV0_SWDS_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
166406. BIF_CFG_DEV0_SWDS_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
166407. BIF_CFG_DEV0_SWDS_LINK_CAP__L0S_EXIT_LATENCY_MASK
166408. BIF_CFG_DEV0_SWDS_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
166409. BIF_CFG_DEV0_SWDS_LINK_CAP__L1_EXIT_LATENCY_MASK
166410. BIF_CFG_DEV0_SWDS_LINK_CAP__L1_EXIT_LATENCY__SHIFT
166411. BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
166412. BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
166413. BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_SPEED_MASK
166414. BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_SPEED__SHIFT
166415. BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_WIDTH_MASK
166416. BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_WIDTH__SHIFT
166417. BIF_CFG_DEV0_SWDS_LINK_CAP__PM_SUPPORT_MASK
166418. BIF_CFG_DEV0_SWDS_LINK_CAP__PM_SUPPORT__SHIFT
166419. BIF_CFG_DEV0_SWDS_LINK_CAP__PORT_NUMBER_MASK
166420. BIF_CFG_DEV0_SWDS_LINK_CAP__PORT_NUMBER__SHIFT
166421. BIF_CFG_DEV0_SWDS_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
166422. BIF_CFG_DEV0_SWDS_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
166423. BIF_CFG_DEV0_SWDS_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
166424. BIF_CFG_DEV0_SWDS_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
166425. BIF_CFG_DEV0_SWDS_LINK_CNTL2__COMPLIANCE_SOS_MASK
166426. BIF_CFG_DEV0_SWDS_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
166427. BIF_CFG_DEV0_SWDS_LINK_CNTL2__ENTER_COMPLIANCE_MASK
166428. BIF_CFG_DEV0_SWDS_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
166429. BIF_CFG_DEV0_SWDS_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
166430. BIF_CFG_DEV0_SWDS_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
166431. BIF_CFG_DEV0_SWDS_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
166432. BIF_CFG_DEV0_SWDS_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
166433. BIF_CFG_DEV0_SWDS_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
166434. BIF_CFG_DEV0_SWDS_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
166435. BIF_CFG_DEV0_SWDS_LINK_CNTL2__TARGET_LINK_SPEED_MASK
166436. BIF_CFG_DEV0_SWDS_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
166437. BIF_CFG_DEV0_SWDS_LINK_CNTL2__XMIT_MARGIN_MASK
166438. BIF_CFG_DEV0_SWDS_LINK_CNTL2__XMIT_MARGIN__SHIFT
166439. BIF_CFG_DEV0_SWDS_LINK_CNTL_16GT__RESERVED_MASK
166440. BIF_CFG_DEV0_SWDS_LINK_CNTL_16GT__RESERVED__SHIFT
166441. BIF_CFG_DEV0_SWDS_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
166442. BIF_CFG_DEV0_SWDS_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
166443. BIF_CFG_DEV0_SWDS_LINK_CNTL__COMMON_CLOCK_CFG_MASK
166444. BIF_CFG_DEV0_SWDS_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
166445. BIF_CFG_DEV0_SWDS_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
166446. BIF_CFG_DEV0_SWDS_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
166447. BIF_CFG_DEV0_SWDS_LINK_CNTL__EXTENDED_SYNC_MASK
166448. BIF_CFG_DEV0_SWDS_LINK_CNTL__EXTENDED_SYNC__SHIFT
166449. BIF_CFG_DEV0_SWDS_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
166450. BIF_CFG_DEV0_SWDS_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
166451. BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
166452. BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
166453. BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
166454. BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
166455. BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_DIS_MASK
166456. BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_DIS__SHIFT
166457. BIF_CFG_DEV0_SWDS_LINK_CNTL__PM_CONTROL_MASK
166458. BIF_CFG_DEV0_SWDS_LINK_CNTL__PM_CONTROL__SHIFT
166459. BIF_CFG_DEV0_SWDS_LINK_CNTL__READ_CPL_BOUNDARY_MASK
166460. BIF_CFG_DEV0_SWDS_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
166461. BIF_CFG_DEV0_SWDS_LINK_CNTL__RETRAIN_LINK_MASK
166462. BIF_CFG_DEV0_SWDS_LINK_CNTL__RETRAIN_LINK__SHIFT
166463. BIF_CFG_DEV0_SWDS_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
166464. BIF_CFG_DEV0_SWDS_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
166465. BIF_CFG_DEV0_SWDS_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
166466. BIF_CFG_DEV0_SWDS_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
166467. BIF_CFG_DEV0_SWDS_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
166468. BIF_CFG_DEV0_SWDS_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
166469. BIF_CFG_DEV0_SWDS_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
166470. BIF_CFG_DEV0_SWDS_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
166471. BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
166472. BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
166473. BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
166474. BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
166475. BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
166476. BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
166477. BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
166478. BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
166479. BIF_CFG_DEV0_SWDS_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
166480. BIF_CFG_DEV0_SWDS_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
166481. BIF_CFG_DEV0_SWDS_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
166482. BIF_CFG_DEV0_SWDS_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
166483. BIF_CFG_DEV0_SWDS_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
166484. BIF_CFG_DEV0_SWDS_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
166485. BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK
166486. BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT
166487. BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK
166488. BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT
166489. BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK
166490. BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT
166491. BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK
166492. BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT
166493. BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK
166494. BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT
166495. BIF_CFG_DEV0_SWDS_LINK_STATUS__CURRENT_LINK_SPEED_MASK
166496. BIF_CFG_DEV0_SWDS_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
166497. BIF_CFG_DEV0_SWDS_LINK_STATUS__DL_ACTIVE_MASK
166498. BIF_CFG_DEV0_SWDS_LINK_STATUS__DL_ACTIVE__SHIFT
166499. BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
166500. BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
166501. BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
166502. BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
166503. BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_TRAINING_MASK
166504. BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_TRAINING__SHIFT
166505. BIF_CFG_DEV0_SWDS_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
166506. BIF_CFG_DEV0_SWDS_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
166507. BIF_CFG_DEV0_SWDS_LINK_STATUS__SLOT_CLOCK_CFG_MASK
166508. BIF_CFG_DEV0_SWDS_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
166509. BIF_CFG_DEV0_SWDS_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK
166510. BIF_CFG_DEV0_SWDS_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT
166511. BIF_CFG_DEV0_SWDS_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK
166512. BIF_CFG_DEV0_SWDS_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT
166513. BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS__MARGINING_READY_MASK
166514. BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT
166515. BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK
166516. BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT
166517. BIF_CFG_DEV0_SWDS_MSI_CAP_LIST__CAP_ID_MASK
166518. BIF_CFG_DEV0_SWDS_MSI_CAP_LIST__CAP_ID__SHIFT
166519. BIF_CFG_DEV0_SWDS_MSI_CAP_LIST__NEXT_PTR_MASK
166520. BIF_CFG_DEV0_SWDS_MSI_CAP_LIST__NEXT_PTR__SHIFT
166521. BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
166522. BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
166523. BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
166524. BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
166525. BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_64BIT_MASK
166526. BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_64BIT__SHIFT
166527. BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_EN_MASK
166528. BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_EN__SHIFT
166529. BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
166530. BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
166531. BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
166532. BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
166533. BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
166534. BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
166535. BIF_CFG_DEV0_SWDS_MSI_MSG_DATA_64__MSI_DATA_64_MASK
166536. BIF_CFG_DEV0_SWDS_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
166537. BIF_CFG_DEV0_SWDS_MSI_MSG_DATA__MSI_DATA_MASK
166538. BIF_CFG_DEV0_SWDS_MSI_MSG_DATA__MSI_DATA__SHIFT
166539. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
166540. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
166541. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
166542. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
166543. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
166544. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
166545. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
166546. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
166547. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
166548. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
166549. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
166550. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
166551. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
166552. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
166553. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
166554. BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
166555. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
166556. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
166557. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
166558. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
166559. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
166560. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
166561. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
166562. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
166563. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
166564. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
166565. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
166566. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
166567. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
166568. BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
166569. BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
166570. BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
166571. BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
166572. BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
166573. BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
166574. BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
166575. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
166576. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
166577. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
166578. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
166579. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
166580. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
166581. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
166582. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
166583. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
166584. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
166585. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
166586. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
166587. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
166588. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
166589. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
166590. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
166591. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
166592. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
166593. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
166594. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
166595. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
166596. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
166597. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
166598. BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
166599. BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST__CAP_ID_MASK
166600. BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST__CAP_ID__SHIFT
166601. BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST__NEXT_PTR_MASK
166602. BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST__NEXT_PTR__SHIFT
166603. BIF_CFG_DEV0_SWDS_PCIE_CAP__DEVICE_TYPE_MASK
166604. BIF_CFG_DEV0_SWDS_PCIE_CAP__DEVICE_TYPE__SHIFT
166605. BIF_CFG_DEV0_SWDS_PCIE_CAP__INT_MESSAGE_NUM_MASK
166606. BIF_CFG_DEV0_SWDS_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
166607. BIF_CFG_DEV0_SWDS_PCIE_CAP__SLOT_IMPLEMENTED_MASK
166608. BIF_CFG_DEV0_SWDS_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
166609. BIF_CFG_DEV0_SWDS_PCIE_CAP__VERSION_MASK
166610. BIF_CFG_DEV0_SWDS_PCIE_CAP__VERSION__SHIFT
166611. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
166612. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
166613. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
166614. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
166615. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
166616. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
166617. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
166618. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
166619. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
166620. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
166621. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
166622. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
166623. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
166624. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
166625. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
166626. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
166627. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
166628. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
166629. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
166630. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
166631. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
166632. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
166633. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
166634. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
166635. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
166636. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
166637. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
166638. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
166639. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
166640. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
166641. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
166642. BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
166643. BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
166644. BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
166645. BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
166646. BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
166647. BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
166648. BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
166649. BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
166650. BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
166651. BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
166652. BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
166653. BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK
166654. BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT
166655. BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK
166656. BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT
166657. BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK
166658. BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT
166659. BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG0__TLP_HDR_MASK
166660. BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG0__TLP_HDR__SHIFT
166661. BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG1__TLP_HDR_MASK
166662. BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG1__TLP_HDR__SHIFT
166663. BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG2__TLP_HDR_MASK
166664. BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG2__TLP_HDR__SHIFT
166665. BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG3__TLP_HDR_MASK
166666. BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG3__TLP_HDR__SHIFT
166667. BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166668. BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166669. BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166670. BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166671. BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
166672. BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
166673. BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166674. BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166675. BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166676. BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166677. BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166678. BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166679. BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166680. BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166681. BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
166682. BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
166683. BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166684. BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166685. BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166686. BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166687. BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166688. BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166689. BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166690. BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166691. BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
166692. BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
166693. BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166694. BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166695. BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166696. BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166697. BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166698. BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166699. BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166700. BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166701. BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
166702. BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
166703. BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166704. BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166705. BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166706. BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166707. BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166708. BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166709. BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166710. BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166711. BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
166712. BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
166713. BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166714. BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166715. BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166716. BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166717. BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166718. BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166719. BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166720. BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166721. BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
166722. BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
166723. BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166724. BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166725. BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166726. BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166727. BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166728. BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166729. BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166730. BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166731. BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
166732. BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
166733. BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166734. BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166735. BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166736. BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166737. BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166738. BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166739. BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166740. BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166741. BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
166742. BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
166743. BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166744. BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166745. BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166746. BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166747. BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166748. BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166749. BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166750. BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166751. BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
166752. BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
166753. BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166754. BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166755. BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166756. BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166757. BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166758. BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166759. BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166760. BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166761. BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
166762. BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
166763. BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166764. BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166765. BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166766. BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166767. BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166768. BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166769. BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166770. BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166771. BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
166772. BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
166773. BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166774. BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166775. BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166776. BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166777. BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166778. BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166779. BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166780. BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166781. BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
166782. BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
166783. BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166784. BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166785. BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166786. BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166787. BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166788. BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166789. BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166790. BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166791. BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
166792. BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
166793. BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166794. BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166795. BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166796. BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166797. BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166798. BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166799. BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166800. BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166801. BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
166802. BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
166803. BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166804. BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166805. BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166806. BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166807. BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166808. BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166809. BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166810. BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166811. BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
166812. BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
166813. BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166814. BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166815. BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166816. BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166817. BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
166818. BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
166819. BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
166820. BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
166821. BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
166822. BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
166823. BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
166824. BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
166825. BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
166826. BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
166827. BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
166828. BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
166829. BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
166830. BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
166831. BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
166832. BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
166833. BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
166834. BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
166835. BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
166836. BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
166837. BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
166838. BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
166839. BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
166840. BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
166841. BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
166842. BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
166843. BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
166844. BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
166845. BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
166846. BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
166847. BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
166848. BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
166849. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
166850. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
166851. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
166852. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
166853. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
166854. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
166855. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
166856. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
166857. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
166858. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
166859. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
166860. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
166861. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
166862. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
166863. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
166864. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
166865. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
166866. BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
166867. BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
166868. BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
166869. BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
166870. BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
166871. BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
166872. BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
166873. BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
166874. BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
166875. BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
166876. BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
166877. BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
166878. BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
166879. BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
166880. BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
166881. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
166882. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
166883. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
166884. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
166885. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
166886. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
166887. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
166888. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
166889. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
166890. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
166891. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
166892. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
166893. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
166894. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
166895. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
166896. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
166897. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
166898. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
166899. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
166900. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
166901. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
166902. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
166903. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
166904. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
166905. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
166906. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
166907. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
166908. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
166909. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
166910. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
166911. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
166912. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
166913. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
166914. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
166915. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
166916. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
166917. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
166918. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
166919. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
166920. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
166921. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
166922. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
166923. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
166924. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
166925. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
166926. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
166927. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
166928. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
166929. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
166930. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
166931. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
166932. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
166933. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
166934. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
166935. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
166936. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
166937. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
166938. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
166939. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
166940. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
166941. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
166942. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
166943. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
166944. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
166945. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
166946. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
166947. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
166948. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
166949. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
166950. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
166951. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
166952. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
166953. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
166954. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
166955. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
166956. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
166957. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
166958. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
166959. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
166960. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
166961. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
166962. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
166963. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
166964. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
166965. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
166966. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
166967. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
166968. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
166969. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
166970. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
166971. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
166972. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
166973. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
166974. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
166975. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
166976. BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
166977. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
166978. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
166979. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
166980. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
166981. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
166982. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
166983. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
166984. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
166985. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
166986. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
166987. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
166988. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
166989. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
166990. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
166991. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
166992. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
166993. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
166994. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
166995. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
166996. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
166997. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
166998. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
166999. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
167000. BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
167001. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
167002. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
167003. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
167004. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
167005. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
167006. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
167007. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
167008. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
167009. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
167010. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
167011. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
167012. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
167013. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
167014. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
167015. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
167016. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
167017. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
167018. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
167019. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
167020. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
167021. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
167022. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
167023. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
167024. BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
167025. BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
167026. BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
167027. BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
167028. BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
167029. BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
167030. BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
167031. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
167032. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
167033. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
167034. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
167035. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
167036. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
167037. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
167038. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
167039. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
167040. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
167041. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
167042. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
167043. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
167044. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
167045. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
167046. BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
167047. BIF_CFG_DEV0_SWDS_PMI_CAP_LIST__CAP_ID_MASK
167048. BIF_CFG_DEV0_SWDS_PMI_CAP_LIST__CAP_ID__SHIFT
167049. BIF_CFG_DEV0_SWDS_PMI_CAP_LIST__NEXT_PTR_MASK
167050. BIF_CFG_DEV0_SWDS_PMI_CAP_LIST__NEXT_PTR__SHIFT
167051. BIF_CFG_DEV0_SWDS_PMI_CAP__AUX_CURRENT_MASK
167052. BIF_CFG_DEV0_SWDS_PMI_CAP__AUX_CURRENT__SHIFT
167053. BIF_CFG_DEV0_SWDS_PMI_CAP__D1_SUPPORT_MASK
167054. BIF_CFG_DEV0_SWDS_PMI_CAP__D1_SUPPORT__SHIFT
167055. BIF_CFG_DEV0_SWDS_PMI_CAP__D2_SUPPORT_MASK
167056. BIF_CFG_DEV0_SWDS_PMI_CAP__D2_SUPPORT__SHIFT
167057. BIF_CFG_DEV0_SWDS_PMI_CAP__DEV_SPECIFIC_INIT_MASK
167058. BIF_CFG_DEV0_SWDS_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
167059. BIF_CFG_DEV0_SWDS_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
167060. BIF_CFG_DEV0_SWDS_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
167061. BIF_CFG_DEV0_SWDS_PMI_CAP__PME_CLOCK_MASK
167062. BIF_CFG_DEV0_SWDS_PMI_CAP__PME_CLOCK__SHIFT
167063. BIF_CFG_DEV0_SWDS_PMI_CAP__PME_SUPPORT_MASK
167064. BIF_CFG_DEV0_SWDS_PMI_CAP__PME_SUPPORT__SHIFT
167065. BIF_CFG_DEV0_SWDS_PMI_CAP__VERSION_MASK
167066. BIF_CFG_DEV0_SWDS_PMI_CAP__VERSION__SHIFT
167067. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
167068. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
167069. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
167070. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
167071. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__DATA_SCALE_MASK
167072. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
167073. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__DATA_SELECT_MASK
167074. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
167075. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
167076. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
167077. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PME_EN_MASK
167078. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PME_EN__SHIFT
167079. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PME_STATUS_MASK
167080. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PME_STATUS__SHIFT
167081. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PMI_DATA_MASK
167082. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PMI_DATA__SHIFT
167083. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__POWER_STATE_MASK
167084. BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__POWER_STATE__SHIFT
167085. BIF_CFG_DEV0_SWDS_PROG_INTERFACE__PROG_INTERFACE_MASK
167086. BIF_CFG_DEV0_SWDS_PROG_INTERFACE__PROG_INTERFACE__SHIFT
167087. BIF_CFG_DEV0_SWDS_REVISION_ID__MAJOR_REV_ID_MASK
167088. BIF_CFG_DEV0_SWDS_REVISION_ID__MAJOR_REV_ID__SHIFT
167089. BIF_CFG_DEV0_SWDS_REVISION_ID__MINOR_REV_ID_MASK
167090. BIF_CFG_DEV0_SWDS_REVISION_ID__MINOR_REV_ID__SHIFT
167091. BIF_CFG_DEV0_SWDS_ROM_BASE_ADDR__BASE_ADDR_MASK
167092. BIF_CFG_DEV0_SWDS_ROM_BASE_ADDR__BASE_ADDR__SHIFT
167093. BIF_CFG_DEV0_SWDS_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK
167094. BIF_CFG_DEV0_SWDS_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT
167095. BIF_CFG_DEV0_SWDS_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK
167096. BIF_CFG_DEV0_SWDS_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT
167097. BIF_CFG_DEV0_SWDS_STATUS__CAP_LIST_MASK
167098. BIF_CFG_DEV0_SWDS_STATUS__CAP_LIST__SHIFT
167099. BIF_CFG_DEV0_SWDS_STATUS__DEVSEL_TIMING_MASK
167100. BIF_CFG_DEV0_SWDS_STATUS__DEVSEL_TIMING__SHIFT
167101. BIF_CFG_DEV0_SWDS_STATUS__FAST_BACK_CAPABLE_MASK
167102. BIF_CFG_DEV0_SWDS_STATUS__FAST_BACK_CAPABLE__SHIFT
167103. BIF_CFG_DEV0_SWDS_STATUS__IMMEDIATE_READINESS_MASK
167104. BIF_CFG_DEV0_SWDS_STATUS__IMMEDIATE_READINESS__SHIFT
167105. BIF_CFG_DEV0_SWDS_STATUS__INT_STATUS_MASK
167106. BIF_CFG_DEV0_SWDS_STATUS__INT_STATUS__SHIFT
167107. BIF_CFG_DEV0_SWDS_STATUS__MASTER_DATA_PARITY_ERROR_MASK
167108. BIF_CFG_DEV0_SWDS_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
167109. BIF_CFG_DEV0_SWDS_STATUS__PARITY_ERROR_DETECTED_MASK
167110. BIF_CFG_DEV0_SWDS_STATUS__PARITY_ERROR_DETECTED__SHIFT
167111. BIF_CFG_DEV0_SWDS_STATUS__PCI_66_CAP_MASK
167112. BIF_CFG_DEV0_SWDS_STATUS__PCI_66_CAP__SHIFT
167113. BIF_CFG_DEV0_SWDS_STATUS__RECEIVED_MASTER_ABORT_MASK
167114. BIF_CFG_DEV0_SWDS_STATUS__RECEIVED_MASTER_ABORT__SHIFT
167115. BIF_CFG_DEV0_SWDS_STATUS__RECEIVED_TARGET_ABORT_MASK
167116. BIF_CFG_DEV0_SWDS_STATUS__RECEIVED_TARGET_ABORT__SHIFT
167117. BIF_CFG_DEV0_SWDS_STATUS__SIGNALED_SYSTEM_ERROR_MASK
167118. BIF_CFG_DEV0_SWDS_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
167119. BIF_CFG_DEV0_SWDS_STATUS__SIGNAL_TARGET_ABORT_MASK
167120. BIF_CFG_DEV0_SWDS_STATUS__SIGNAL_TARGET_ABORT__SHIFT
167121. BIF_CFG_DEV0_SWDS_SUB_CLASS__SUB_CLASS_MASK
167122. BIF_CFG_DEV0_SWDS_SUB_CLASS__SUB_CLASS__SHIFT
167123. BIF_CFG_DEV0_SWDS_VENDOR_ID__VENDOR_ID_MASK
167124. BIF_CFG_DEV0_SWDS_VENDOR_ID__VENDOR_ID__SHIFT
167125. BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
167126. BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
167127. BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
167128. BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
167129. BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
167130. BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
167131. BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
167132. BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
167133. BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK
167134. BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT
167135. BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK
167136. BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT
167137. BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK
167138. BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT
167139. BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK
167140. BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT
167141. BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK
167142. BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT
167143. BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK
167144. BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT
167145. BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS_MASK
167146. BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT
167147. BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP_MASK
167148. BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP__SHIFT
167149. BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP_MASK
167150. BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP__SHIFT
167151. BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT_MASK
167152. BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT__SHIFT
167153. BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
167154. BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
167155. BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR_MASK
167156. BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR__SHIFT
167157. BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING_MASK
167158. BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING__SHIFT
167159. BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN_MASK
167160. BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT
167161. BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN_MASK
167162. BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT
167163. BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS_MASK
167164. BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS__SHIFT
167165. BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN_MASK
167166. BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT
167167. BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK
167168. BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT
167169. BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
167170. BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
167171. BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK
167172. BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT
167173. BIF_CFG_DEV1_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
167174. BIF_CFG_DEV1_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
167175. BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN_MASK
167176. BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN__SHIFT
167177. BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK
167178. BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
167179. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
167180. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
167181. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
167182. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
167183. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
167184. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
167185. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
167186. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
167187. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
167188. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
167189. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
167190. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
167191. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
167192. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
167193. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
167194. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
167195. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
167196. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
167197. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
167198. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
167199. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
167200. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
167201. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
167202. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
167203. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
167204. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
167205. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
167206. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
167207. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
167208. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
167209. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
167210. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
167211. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK
167212. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
167213. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK
167214. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
167215. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
167216. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
167217. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
167218. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
167219. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
167220. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
167221. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK
167222. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
167223. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
167224. BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
167225. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
167226. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
167227. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
167228. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
167229. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
167230. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
167231. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
167232. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
167233. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
167234. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
167235. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
167236. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
167237. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
167238. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
167239. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
167240. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
167241. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK
167242. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT
167243. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK
167244. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT
167245. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
167246. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
167247. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK
167248. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
167249. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
167250. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
167251. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
167252. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
167253. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK
167254. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
167255. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
167256. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
167257. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
167258. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
167259. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
167260. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
167261. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
167262. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
167263. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
167264. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
167265. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
167266. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
167267. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK
167268. BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
167269. BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID_MASK
167270. BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT
167271. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED_MASK
167272. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT
167273. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK
167274. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT
167275. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK
167276. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT
167277. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK
167278. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT
167279. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
167280. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
167281. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
167282. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
167283. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK
167284. BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT
167285. BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE_MASK
167286. BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE__SHIFT
167287. BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE_MASK
167288. BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE__SHIFT
167289. BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
167290. BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
167291. BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
167292. BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
167293. BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER_MASK
167294. BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT
167295. BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
167296. BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
167297. BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RESERVED_MASK
167298. BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RESERVED__SHIFT
167299. BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
167300. BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
167301. BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
167302. BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
167303. BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
167304. BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
167305. BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
167306. BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
167307. BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
167308. BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
167309. BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK
167310. BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
167311. BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
167312. BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
167313. BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED_MASK
167314. BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT
167315. BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH_MASK
167316. BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT
167317. BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT_MASK
167318. BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT
167319. BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER_MASK
167320. BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT
167321. BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
167322. BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
167323. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
167324. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
167325. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
167326. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
167327. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
167328. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
167329. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
167330. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
167331. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
167332. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
167333. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
167334. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
167335. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
167336. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
167337. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK
167338. BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
167339. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
167340. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
167341. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
167342. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
167343. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK
167344. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
167345. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
167346. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
167347. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
167348. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
167349. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
167350. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
167351. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS_MASK
167352. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT
167353. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL_MASK
167354. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT
167355. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
167356. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
167357. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK
167358. BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT
167359. BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
167360. BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
167361. BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
167362. BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
167363. BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
167364. BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
167365. BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
167366. BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
167367. BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
167368. BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
167369. BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
167370. BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
167371. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
167372. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
167373. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK
167374. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT
167375. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
167376. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
167377. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
167378. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
167379. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK
167380. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT
167381. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
167382. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
167383. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
167384. BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
167385. BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT_MASK
167386. BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT
167387. BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT_MASK
167388. BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT
167389. BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK
167390. BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT
167391. BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK
167392. BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
167393. BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK
167394. BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
167395. BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
167396. BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
167397. BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
167398. BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
167399. BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK
167400. BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
167401. BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
167402. BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
167403. BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
167404. BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
167405. BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
167406. BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
167407. BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK
167408. BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT
167409. BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK
167410. BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
167411. BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK
167412. BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT
167413. BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK_MASK
167414. BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK__SHIFT
167415. BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
167416. BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
167417. BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
167418. BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
167419. BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK
167420. BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
167421. BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK
167422. BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT
167423. BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
167424. BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
167425. BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
167426. BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
167427. BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
167428. BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
167429. BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
167430. BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
167431. BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK
167432. BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT
167433. BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK
167434. BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
167435. BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING_MASK
167436. BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT
167437. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
167438. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
167439. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
167440. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
167441. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
167442. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
167443. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
167444. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
167445. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
167446. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
167447. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
167448. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
167449. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
167450. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
167451. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
167452. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
167453. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
167454. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
167455. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
167456. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
167457. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
167458. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
167459. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
167460. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
167461. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
167462. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
167463. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
167464. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
167465. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
167466. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
167467. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
167468. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
167469. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
167470. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
167471. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
167472. BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
167473. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
167474. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
167475. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
167476. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
167477. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
167478. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
167479. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
167480. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
167481. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
167482. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
167483. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
167484. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
167485. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
167486. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
167487. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
167488. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
167489. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
167490. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
167491. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
167492. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
167493. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
167494. BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
167495. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
167496. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
167497. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
167498. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
167499. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
167500. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
167501. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
167502. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
167503. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
167504. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
167505. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
167506. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
167507. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
167508. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
167509. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
167510. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
167511. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
167512. BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
167513. BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
167514. BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
167515. BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK
167516. BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
167517. BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK
167518. BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
167519. BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
167520. BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
167521. BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
167522. BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
167523. BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK
167524. BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
167525. BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK
167526. BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
167527. BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
167528. BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
167529. BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
167530. BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
167531. BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK
167532. BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
167533. BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK
167534. BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
167535. BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
167536. BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
167537. BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
167538. BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
167539. BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK
167540. BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
167541. BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK
167542. BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
167543. BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
167544. BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
167545. BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
167546. BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
167547. BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK
167548. BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
167549. BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK
167550. BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
167551. BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
167552. BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
167553. BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
167554. BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
167555. BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK
167556. BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
167557. BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK
167558. BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
167559. BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
167560. BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
167561. BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
167562. BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
167563. BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
167564. BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
167565. BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
167566. BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
167567. BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK
167568. BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT
167569. BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK
167570. BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
167571. BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK
167572. BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT
167573. BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
167574. BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
167575. BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
167576. BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
167577. BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION_MASK
167578. BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION__SHIFT
167579. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
167580. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
167581. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
167582. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
167583. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
167584. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
167585. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
167586. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
167587. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
167588. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
167589. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
167590. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
167591. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
167592. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
167593. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
167594. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
167595. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
167596. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
167597. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
167598. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
167599. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
167600. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
167601. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
167602. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
167603. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
167604. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
167605. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
167606. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
167607. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
167608. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
167609. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
167610. BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
167611. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
167612. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
167613. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
167614. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
167615. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
167616. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
167617. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
167618. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
167619. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
167620. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
167621. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
167622. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
167623. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
167624. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
167625. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
167626. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
167627. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
167628. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
167629. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
167630. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
167631. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
167632. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
167633. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
167634. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
167635. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
167636. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
167637. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
167638. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
167639. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
167640. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
167641. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
167642. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
167643. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
167644. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
167645. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
167646. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
167647. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
167648. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
167649. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
167650. BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
167651. BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK
167652. BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
167653. BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK
167654. BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
167655. BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK
167656. BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
167657. BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK
167658. BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
167659. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167660. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167661. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167662. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167663. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
167664. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
167665. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167666. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167667. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167668. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167669. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167670. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167671. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167672. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167673. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
167674. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
167675. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167676. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167677. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167678. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167679. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167680. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167681. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167682. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167683. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
167684. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
167685. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167686. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167687. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167688. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167689. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167690. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167691. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167692. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167693. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
167694. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
167695. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167696. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167697. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167698. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167699. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167700. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167701. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167702. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167703. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
167704. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
167705. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167706. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167707. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167708. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167709. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167710. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167711. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167712. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167713. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
167714. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
167715. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167716. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167717. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167718. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167719. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167720. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167721. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167722. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167723. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
167724. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
167725. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167726. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167727. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167728. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167729. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167730. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167731. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167732. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167733. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
167734. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
167735. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167736. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167737. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167738. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167739. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167740. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167741. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167742. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167743. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
167744. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
167745. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167746. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167747. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167748. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167749. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167750. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167751. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167752. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167753. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
167754. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
167755. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167756. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167757. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167758. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167759. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167760. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167761. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167762. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167763. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
167764. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
167765. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167766. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167767. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167768. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167769. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167770. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167771. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167772. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167773. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
167774. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
167775. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167776. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167777. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167778. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167779. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167780. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167781. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167782. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167783. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
167784. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
167785. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167786. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167787. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167788. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167789. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167790. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167791. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167792. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167793. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
167794. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
167795. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167796. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167797. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167798. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167799. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167800. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167801. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167802. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167803. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
167804. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
167805. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167806. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167807. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167808. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167809. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
167810. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
167811. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
167812. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
167813. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
167814. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
167815. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
167816. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
167817. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
167818. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
167819. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
167820. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
167821. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
167822. BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
167823. BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
167824. BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
167825. BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
167826. BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
167827. BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__RESERVED_MASK
167828. BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__RESERVED__SHIFT
167829. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
167830. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
167831. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
167832. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
167833. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
167834. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
167835. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
167836. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
167837. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
167838. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
167839. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
167840. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
167841. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
167842. BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
167843. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
167844. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
167845. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
167846. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
167847. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
167848. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
167849. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
167850. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
167851. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
167852. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
167853. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
167854. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
167855. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
167856. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
167857. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
167858. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
167859. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
167860. BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
167861. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
167862. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
167863. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
167864. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
167865. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
167866. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
167867. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
167868. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
167869. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
167870. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
167871. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
167872. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
167873. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
167874. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
167875. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK
167876. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
167877. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
167878. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
167879. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
167880. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
167881. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
167882. BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
167883. BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
167884. BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
167885. BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
167886. BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
167887. BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
167888. BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
167889. BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
167890. BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
167891. BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
167892. BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
167893. BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
167894. BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
167895. BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
167896. BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
167897. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
167898. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
167899. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
167900. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
167901. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
167902. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
167903. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
167904. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
167905. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
167906. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
167907. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
167908. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
167909. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
167910. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
167911. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
167912. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
167913. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
167914. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
167915. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
167916. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
167917. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
167918. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
167919. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
167920. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
167921. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
167922. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
167923. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
167924. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
167925. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
167926. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
167927. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
167928. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
167929. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
167930. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
167931. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
167932. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
167933. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
167934. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
167935. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
167936. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
167937. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
167938. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
167939. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
167940. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
167941. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
167942. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
167943. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
167944. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
167945. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
167946. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
167947. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
167948. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
167949. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
167950. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
167951. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
167952. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
167953. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
167954. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
167955. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
167956. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
167957. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
167958. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
167959. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
167960. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
167961. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
167962. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
167963. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
167964. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
167965. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
167966. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
167967. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
167968. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
167969. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
167970. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
167971. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
167972. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
167973. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
167974. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
167975. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
167976. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
167977. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
167978. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
167979. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
167980. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
167981. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
167982. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
167983. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
167984. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
167985. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
167986. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
167987. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
167988. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
167989. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
167990. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
167991. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
167992. BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
167993. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
167994. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
167995. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
167996. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
167997. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
167998. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
167999. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
168000. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
168001. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
168002. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
168003. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
168004. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
168005. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
168006. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
168007. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
168008. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
168009. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
168010. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
168011. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
168012. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
168013. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
168014. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
168015. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
168016. BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
168017. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
168018. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
168019. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
168020. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
168021. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
168022. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
168023. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
168024. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
168025. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
168026. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
168027. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
168028. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
168029. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
168030. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
168031. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
168032. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
168033. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
168034. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
168035. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
168036. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
168037. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
168038. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
168039. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
168040. BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
168041. BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
168042. BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
168043. BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
168044. BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
168045. BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
168046. BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
168047. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
168048. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
168049. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
168050. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
168051. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
168052. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
168053. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
168054. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
168055. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
168056. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
168057. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
168058. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
168059. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
168060. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
168061. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
168062. BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
168063. BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK
168064. BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT
168065. BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK
168066. BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
168067. BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT_MASK
168068. BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT
168069. BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT_MASK
168070. BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT
168071. BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT_MASK
168072. BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT
168073. BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
168074. BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
168075. BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK_MASK
168076. BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT
168077. BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT_MASK
168078. BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT
168079. BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION_MASK
168080. BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION__SHIFT
168081. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
168082. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
168083. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
168084. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
168085. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
168086. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
168087. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
168088. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
168089. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
168090. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
168091. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK
168092. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT
168093. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK
168094. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
168095. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK
168096. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
168097. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK
168098. BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
168099. BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK
168100. BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
168101. BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK
168102. BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT
168103. BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK
168104. BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT
168105. BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK
168106. BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
168107. BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__CAP_ID_MASK
168108. BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__CAP_ID__SHIFT
168109. BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__NEXT_PTR_MASK
168110. BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__NEXT_PTR__SHIFT
168111. BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
168112. BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
168113. BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
168114. BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
168115. BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
168116. BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
168117. BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
168118. BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
168119. BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
168120. BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
168121. BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
168122. BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
168123. BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA__IDP_DATA_MASK
168124. BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA__IDP_DATA__SHIFT
168125. BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_INDEX_MASK
168126. BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT
168127. BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK
168128. BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
168129. BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK
168130. BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
168131. BIF_CFG_DEV1_EPF0_0_SLOT_CAP2__RESERVED_MASK
168132. BIF_CFG_DEV1_EPF0_0_SLOT_CAP2__RESERVED__SHIFT
168133. BIF_CFG_DEV1_EPF0_0_SLOT_CNTL2__RESERVED_MASK
168134. BIF_CFG_DEV1_EPF0_0_SLOT_CNTL2__RESERVED__SHIFT
168135. BIF_CFG_DEV1_EPF0_0_SLOT_STATUS2__RESERVED_MASK
168136. BIF_CFG_DEV1_EPF0_0_SLOT_STATUS2__RESERVED__SHIFT
168137. BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST_MASK
168138. BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST__SHIFT
168139. BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING_MASK
168140. BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT
168141. BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK
168142. BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT
168143. BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS_MASK
168144. BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS__SHIFT
168145. BIF_CFG_DEV1_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
168146. BIF_CFG_DEV1_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
168147. BIF_CFG_DEV1_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK
168148. BIF_CFG_DEV1_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
168149. BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_EN_MASK
168150. BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_EN__SHIFT
168151. BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK
168152. BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
168153. BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK
168154. BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
168155. BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
168156. BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
168157. BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK
168158. BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
168159. BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS_MASK
168160. BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT
168161. BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK
168162. BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT
168163. BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK
168164. BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT
168165. BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK
168166. BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
168167. BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID_MASK
168168. BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT
168169. BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
168170. BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
168171. BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
168172. BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
168173. BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
168174. BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
168175. BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
168176. BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
168177. BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK
168178. BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT
168179. BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK
168180. BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT
168181. BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK
168182. BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT
168183. BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK
168184. BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT
168185. BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK
168186. BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT
168187. BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK
168188. BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT
168189. BIF_CFG_DEV1_EPF0_1_BASE_CLASS__BASE_CLASS_MASK
168190. BIF_CFG_DEV1_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT
168191. BIF_CFG_DEV1_EPF0_1_BIST__BIST_CAP_MASK
168192. BIF_CFG_DEV1_EPF0_1_BIST__BIST_CAP__SHIFT
168193. BIF_CFG_DEV1_EPF0_1_BIST__BIST_COMP_MASK
168194. BIF_CFG_DEV1_EPF0_1_BIST__BIST_COMP__SHIFT
168195. BIF_CFG_DEV1_EPF0_1_BIST__BIST_STRT_MASK
168196. BIF_CFG_DEV1_EPF0_1_BIST__BIST_STRT__SHIFT
168197. BIF_CFG_DEV1_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
168198. BIF_CFG_DEV1_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
168199. BIF_CFG_DEV1_EPF0_1_CAP_PTR__CAP_PTR_MASK
168200. BIF_CFG_DEV1_EPF0_1_CAP_PTR__CAP_PTR__SHIFT
168201. BIF_CFG_DEV1_EPF0_1_COMMAND__AD_STEPPING_MASK
168202. BIF_CFG_DEV1_EPF0_1_COMMAND__AD_STEPPING__SHIFT
168203. BIF_CFG_DEV1_EPF0_1_COMMAND__BUS_MASTER_EN_MASK
168204. BIF_CFG_DEV1_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT
168205. BIF_CFG_DEV1_EPF0_1_COMMAND__FAST_B2B_EN_MASK
168206. BIF_CFG_DEV1_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT
168207. BIF_CFG_DEV1_EPF0_1_COMMAND__INT_DIS_MASK
168208. BIF_CFG_DEV1_EPF0_1_COMMAND__INT_DIS__SHIFT
168209. BIF_CFG_DEV1_EPF0_1_COMMAND__IO_ACCESS_EN_MASK
168210. BIF_CFG_DEV1_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT
168211. BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK
168212. BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT
168213. BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
168214. BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
168215. BIF_CFG_DEV1_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK
168216. BIF_CFG_DEV1_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT
168217. BIF_CFG_DEV1_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
168218. BIF_CFG_DEV1_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
168219. BIF_CFG_DEV1_EPF0_1_COMMAND__SERR_EN_MASK
168220. BIF_CFG_DEV1_EPF0_1_COMMAND__SERR_EN__SHIFT
168221. BIF_CFG_DEV1_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK
168222. BIF_CFG_DEV1_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
168223. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
168224. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
168225. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
168226. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
168227. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
168228. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
168229. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
168230. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
168231. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
168232. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
168233. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
168234. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
168235. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
168236. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
168237. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
168238. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
168239. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
168240. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
168241. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
168242. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
168243. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
168244. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
168245. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
168246. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
168247. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
168248. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
168249. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
168250. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
168251. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
168252. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
168253. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
168254. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
168255. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK
168256. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
168257. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK
168258. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
168259. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
168260. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
168261. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
168262. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
168263. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
168264. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
168265. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK
168266. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
168267. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
168268. BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
168269. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
168270. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
168271. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
168272. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
168273. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
168274. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
168275. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
168276. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
168277. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
168278. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
168279. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
168280. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
168281. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
168282. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
168283. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
168284. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
168285. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK
168286. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT
168287. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK
168288. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT
168289. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
168290. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
168291. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK
168292. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
168293. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
168294. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
168295. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
168296. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
168297. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK
168298. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
168299. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
168300. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
168301. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
168302. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
168303. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
168304. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
168305. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
168306. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
168307. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
168308. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
168309. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
168310. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
168311. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK
168312. BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
168313. BIF_CFG_DEV1_EPF0_1_DEVICE_ID__DEVICE_ID_MASK
168314. BIF_CFG_DEV1_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT
168315. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2__RESERVED_MASK
168316. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT
168317. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK
168318. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT
168319. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK
168320. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT
168321. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK
168322. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT
168323. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
168324. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
168325. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
168326. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
168327. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK
168328. BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT
168329. BIF_CFG_DEV1_EPF0_1_HEADER__DEVICE_TYPE_MASK
168330. BIF_CFG_DEV1_EPF0_1_HEADER__DEVICE_TYPE__SHIFT
168331. BIF_CFG_DEV1_EPF0_1_HEADER__HEADER_TYPE_MASK
168332. BIF_CFG_DEV1_EPF0_1_HEADER__HEADER_TYPE__SHIFT
168333. BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
168334. BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
168335. BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
168336. BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
168337. BIF_CFG_DEV1_EPF0_1_LATENCY__LATENCY_TIMER_MASK
168338. BIF_CFG_DEV1_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT
168339. BIF_CFG_DEV1_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
168340. BIF_CFG_DEV1_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
168341. BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RESERVED_MASK
168342. BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RESERVED__SHIFT
168343. BIF_CFG_DEV1_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
168344. BIF_CFG_DEV1_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
168345. BIF_CFG_DEV1_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
168346. BIF_CFG_DEV1_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
168347. BIF_CFG_DEV1_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
168348. BIF_CFG_DEV1_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
168349. BIF_CFG_DEV1_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
168350. BIF_CFG_DEV1_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
168351. BIF_CFG_DEV1_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
168352. BIF_CFG_DEV1_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
168353. BIF_CFG_DEV1_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK
168354. BIF_CFG_DEV1_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
168355. BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
168356. BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
168357. BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_SPEED_MASK
168358. BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT
168359. BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_WIDTH_MASK
168360. BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT
168361. BIF_CFG_DEV1_EPF0_1_LINK_CAP__PM_SUPPORT_MASK
168362. BIF_CFG_DEV1_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT
168363. BIF_CFG_DEV1_EPF0_1_LINK_CAP__PORT_NUMBER_MASK
168364. BIF_CFG_DEV1_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT
168365. BIF_CFG_DEV1_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
168366. BIF_CFG_DEV1_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
168367. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
168368. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
168369. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
168370. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
168371. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
168372. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
168373. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
168374. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
168375. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
168376. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
168377. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
168378. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
168379. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
168380. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
168381. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK
168382. BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
168383. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
168384. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
168385. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
168386. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
168387. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK
168388. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
168389. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
168390. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
168391. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
168392. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
168393. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
168394. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
168395. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_DIS_MASK
168396. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT
168397. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__PM_CONTROL_MASK
168398. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT
168399. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
168400. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
168401. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK
168402. BIF_CFG_DEV1_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT
168403. BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
168404. BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
168405. BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
168406. BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
168407. BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
168408. BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
168409. BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
168410. BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
168411. BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
168412. BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
168413. BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
168414. BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
168415. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
168416. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
168417. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK
168418. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT
168419. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
168420. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
168421. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
168422. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
168423. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK
168424. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT
168425. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
168426. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
168427. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
168428. BIF_CFG_DEV1_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
168429. BIF_CFG_DEV1_EPF0_1_MAX_LATENCY__MAX_LAT_MASK
168430. BIF_CFG_DEV1_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT
168431. BIF_CFG_DEV1_EPF0_1_MIN_GRANT__MIN_GNT_MASK
168432. BIF_CFG_DEV1_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT
168433. BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK
168434. BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT
168435. BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK
168436. BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
168437. BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK
168438. BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
168439. BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
168440. BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
168441. BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
168442. BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
168443. BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK
168444. BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
168445. BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
168446. BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
168447. BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
168448. BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
168449. BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
168450. BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
168451. BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK
168452. BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT
168453. BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK
168454. BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
168455. BIF_CFG_DEV1_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK
168456. BIF_CFG_DEV1_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT
168457. BIF_CFG_DEV1_EPF0_1_MSI_MASK__MSI_MASK_MASK
168458. BIF_CFG_DEV1_EPF0_1_MSI_MASK__MSI_MASK__SHIFT
168459. BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
168460. BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
168461. BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
168462. BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
168463. BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK
168464. BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
168465. BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK
168466. BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT
168467. BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
168468. BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
168469. BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
168470. BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
168471. BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
168472. BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
168473. BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
168474. BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
168475. BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK
168476. BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT
168477. BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK
168478. BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
168479. BIF_CFG_DEV1_EPF0_1_MSI_PENDING__MSI_PENDING_MASK
168480. BIF_CFG_DEV1_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT
168481. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
168482. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
168483. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
168484. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
168485. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
168486. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
168487. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
168488. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
168489. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
168490. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
168491. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
168492. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
168493. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
168494. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
168495. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
168496. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
168497. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
168498. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
168499. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
168500. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
168501. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
168502. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
168503. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
168504. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
168505. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
168506. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
168507. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
168508. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
168509. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
168510. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
168511. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
168512. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
168513. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
168514. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
168515. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
168516. BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
168517. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
168518. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
168519. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
168520. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
168521. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
168522. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
168523. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
168524. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
168525. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
168526. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
168527. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
168528. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
168529. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
168530. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
168531. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
168532. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
168533. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
168534. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
168535. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
168536. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
168537. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
168538. BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
168539. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
168540. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
168541. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
168542. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
168543. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
168544. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
168545. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
168546. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
168547. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
168548. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
168549. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
168550. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
168551. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
168552. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
168553. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
168554. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
168555. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
168556. BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
168557. BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
168558. BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
168559. BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK
168560. BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
168561. BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK
168562. BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
168563. BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
168564. BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
168565. BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
168566. BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
168567. BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK
168568. BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
168569. BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK
168570. BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
168571. BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
168572. BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
168573. BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
168574. BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
168575. BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK
168576. BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
168577. BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK
168578. BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
168579. BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
168580. BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
168581. BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
168582. BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
168583. BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK
168584. BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
168585. BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK
168586. BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
168587. BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
168588. BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
168589. BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
168590. BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
168591. BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK
168592. BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
168593. BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK
168594. BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
168595. BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
168596. BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
168597. BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
168598. BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
168599. BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK
168600. BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
168601. BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK
168602. BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
168603. BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
168604. BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
168605. BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
168606. BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
168607. BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
168608. BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
168609. BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
168610. BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
168611. BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK
168612. BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT
168613. BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK
168614. BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
168615. BIF_CFG_DEV1_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK
168616. BIF_CFG_DEV1_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT
168617. BIF_CFG_DEV1_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
168618. BIF_CFG_DEV1_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
168619. BIF_CFG_DEV1_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
168620. BIF_CFG_DEV1_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
168621. BIF_CFG_DEV1_EPF0_1_PCIE_CAP__VERSION_MASK
168622. BIF_CFG_DEV1_EPF0_1_PCIE_CAP__VERSION__SHIFT
168623. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
168624. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
168625. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
168626. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
168627. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
168628. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
168629. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
168630. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
168631. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
168632. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
168633. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
168634. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
168635. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
168636. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
168637. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
168638. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
168639. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
168640. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
168641. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
168642. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
168643. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
168644. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
168645. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
168646. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
168647. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
168648. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
168649. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
168650. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
168651. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
168652. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
168653. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
168654. BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
168655. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
168656. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
168657. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
168658. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
168659. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
168660. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
168661. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
168662. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
168663. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
168664. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
168665. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
168666. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
168667. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
168668. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
168669. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
168670. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
168671. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
168672. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
168673. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
168674. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
168675. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
168676. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
168677. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
168678. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
168679. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
168680. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
168681. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
168682. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
168683. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
168684. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
168685. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
168686. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
168687. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
168688. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
168689. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
168690. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
168691. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
168692. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
168693. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
168694. BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
168695. BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK
168696. BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
168697. BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK
168698. BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
168699. BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK
168700. BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
168701. BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK
168702. BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
168703. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168704. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168705. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168706. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168707. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
168708. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
168709. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168710. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168711. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168712. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168713. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168714. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168715. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168716. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168717. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
168718. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
168719. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168720. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168721. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168722. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168723. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168724. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168725. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168726. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168727. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
168728. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
168729. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168730. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168731. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168732. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168733. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168734. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168735. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168736. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168737. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
168738. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
168739. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168740. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168741. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168742. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168743. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168744. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168745. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168746. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168747. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
168748. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
168749. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168750. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168751. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168752. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168753. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168754. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168755. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168756. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168757. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
168758. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
168759. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168760. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168761. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168762. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168763. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168764. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168765. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168766. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168767. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
168768. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
168769. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168770. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168771. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168772. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168773. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168774. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168775. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168776. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168777. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
168778. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
168779. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168780. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168781. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168782. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168783. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168784. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168785. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168786. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168787. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
168788. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
168789. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168790. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168791. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168792. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168793. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168794. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168795. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168796. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168797. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
168798. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
168799. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168800. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168801. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168802. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168803. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168804. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168805. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168806. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168807. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
168808. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
168809. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168810. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168811. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168812. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168813. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168814. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168815. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168816. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168817. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
168818. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
168819. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168820. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168821. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168822. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168823. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168824. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168825. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168826. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168827. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
168828. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
168829. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168830. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168831. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168832. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168833. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168834. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168835. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168836. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168837. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
168838. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
168839. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168840. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168841. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168842. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168843. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168844. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168845. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168846. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168847. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
168848. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
168849. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168850. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168851. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168852. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168853. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
168854. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
168855. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
168856. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
168857. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
168858. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
168859. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
168860. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
168861. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
168862. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
168863. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
168864. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
168865. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
168866. BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
168867. BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
168868. BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
168869. BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
168870. BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
168871. BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__RESERVED_MASK
168872. BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__RESERVED__SHIFT
168873. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
168874. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
168875. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
168876. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
168877. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
168878. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
168879. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
168880. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
168881. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
168882. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
168883. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
168884. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
168885. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
168886. BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
168887. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
168888. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
168889. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
168890. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
168891. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
168892. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
168893. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
168894. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
168895. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
168896. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
168897. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
168898. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
168899. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
168900. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
168901. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
168902. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
168903. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
168904. BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
168905. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
168906. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
168907. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
168908. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
168909. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
168910. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
168911. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
168912. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
168913. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
168914. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
168915. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
168916. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
168917. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
168918. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
168919. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK
168920. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
168921. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
168922. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
168923. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
168924. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
168925. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
168926. BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
168927. BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
168928. BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
168929. BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
168930. BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
168931. BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
168932. BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
168933. BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
168934. BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
168935. BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
168936. BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
168937. BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
168938. BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
168939. BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
168940. BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
168941. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
168942. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
168943. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
168944. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
168945. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
168946. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
168947. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
168948. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
168949. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
168950. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
168951. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
168952. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
168953. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
168954. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
168955. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
168956. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
168957. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
168958. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
168959. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
168960. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
168961. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
168962. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
168963. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
168964. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
168965. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
168966. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
168967. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
168968. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
168969. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
168970. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
168971. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
168972. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
168973. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
168974. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
168975. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
168976. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
168977. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
168978. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
168979. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
168980. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
168981. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
168982. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
168983. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
168984. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
168985. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
168986. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
168987. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
168988. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
168989. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
168990. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
168991. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
168992. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
168993. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
168994. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
168995. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
168996. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
168997. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
168998. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
168999. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
169000. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
169001. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
169002. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
169003. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
169004. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
169005. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
169006. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
169007. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
169008. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
169009. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
169010. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
169011. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
169012. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
169013. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
169014. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
169015. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
169016. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
169017. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
169018. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
169019. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
169020. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
169021. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
169022. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
169023. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
169024. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
169025. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
169026. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
169027. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
169028. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
169029. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
169030. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
169031. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
169032. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
169033. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
169034. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
169035. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
169036. BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
169037. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
169038. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
169039. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
169040. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
169041. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
169042. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
169043. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
169044. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
169045. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
169046. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
169047. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
169048. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
169049. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
169050. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
169051. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
169052. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
169053. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
169054. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
169055. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
169056. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
169057. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
169058. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
169059. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
169060. BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
169061. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
169062. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
169063. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
169064. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
169065. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
169066. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
169067. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
169068. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
169069. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
169070. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
169071. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
169072. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
169073. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
169074. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
169075. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
169076. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
169077. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
169078. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
169079. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
169080. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
169081. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
169082. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
169083. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
169084. BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
169085. BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
169086. BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
169087. BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
169088. BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
169089. BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
169090. BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
169091. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
169092. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
169093. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
169094. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
169095. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
169096. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
169097. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
169098. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
169099. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
169100. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
169101. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
169102. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
169103. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
169104. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
169105. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
169106. BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
169107. BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK
169108. BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT
169109. BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK
169110. BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
169111. BIF_CFG_DEV1_EPF0_1_PMI_CAP__AUX_CURRENT_MASK
169112. BIF_CFG_DEV1_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT
169113. BIF_CFG_DEV1_EPF0_1_PMI_CAP__D1_SUPPORT_MASK
169114. BIF_CFG_DEV1_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT
169115. BIF_CFG_DEV1_EPF0_1_PMI_CAP__D2_SUPPORT_MASK
169116. BIF_CFG_DEV1_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT
169117. BIF_CFG_DEV1_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
169118. BIF_CFG_DEV1_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
169119. BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_CLOCK_MASK
169120. BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT
169121. BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_SUPPORT_MASK
169122. BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT
169123. BIF_CFG_DEV1_EPF0_1_PMI_CAP__VERSION_MASK
169124. BIF_CFG_DEV1_EPF0_1_PMI_CAP__VERSION__SHIFT
169125. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
169126. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
169127. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
169128. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
169129. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
169130. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
169131. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
169132. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
169133. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
169134. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
169135. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK
169136. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT
169137. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK
169138. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
169139. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK
169140. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
169141. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK
169142. BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
169143. BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK
169144. BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
169145. BIF_CFG_DEV1_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK
169146. BIF_CFG_DEV1_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT
169147. BIF_CFG_DEV1_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK
169148. BIF_CFG_DEV1_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT
169149. BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK
169150. BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
169151. BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__CAP_ID_MASK
169152. BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__CAP_ID__SHIFT
169153. BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__NEXT_PTR_MASK
169154. BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__NEXT_PTR__SHIFT
169155. BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
169156. BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
169157. BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
169158. BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
169159. BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
169160. BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
169161. BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
169162. BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
169163. BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
169164. BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
169165. BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
169166. BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
169167. BIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA__IDP_DATA_MASK
169168. BIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA__IDP_DATA__SHIFT
169169. BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_INDEX_MASK
169170. BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT
169171. BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK
169172. BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
169173. BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK
169174. BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
169175. BIF_CFG_DEV1_EPF0_1_SLOT_CAP2__RESERVED_MASK
169176. BIF_CFG_DEV1_EPF0_1_SLOT_CAP2__RESERVED__SHIFT
169177. BIF_CFG_DEV1_EPF0_1_SLOT_CNTL2__RESERVED_MASK
169178. BIF_CFG_DEV1_EPF0_1_SLOT_CNTL2__RESERVED__SHIFT
169179. BIF_CFG_DEV1_EPF0_1_SLOT_STATUS2__RESERVED_MASK
169180. BIF_CFG_DEV1_EPF0_1_SLOT_STATUS2__RESERVED__SHIFT
169181. BIF_CFG_DEV1_EPF0_1_STATUS__CAP_LIST_MASK
169182. BIF_CFG_DEV1_EPF0_1_STATUS__CAP_LIST__SHIFT
169183. BIF_CFG_DEV1_EPF0_1_STATUS__DEVSEL_TIMING_MASK
169184. BIF_CFG_DEV1_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT
169185. BIF_CFG_DEV1_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK
169186. BIF_CFG_DEV1_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT
169187. BIF_CFG_DEV1_EPF0_1_STATUS__INT_STATUS_MASK
169188. BIF_CFG_DEV1_EPF0_1_STATUS__INT_STATUS__SHIFT
169189. BIF_CFG_DEV1_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
169190. BIF_CFG_DEV1_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
169191. BIF_CFG_DEV1_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK
169192. BIF_CFG_DEV1_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
169193. BIF_CFG_DEV1_EPF0_1_STATUS__PCI_66_EN_MASK
169194. BIF_CFG_DEV1_EPF0_1_STATUS__PCI_66_EN__SHIFT
169195. BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK
169196. BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
169197. BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK
169198. BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
169199. BIF_CFG_DEV1_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
169200. BIF_CFG_DEV1_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
169201. BIF_CFG_DEV1_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK
169202. BIF_CFG_DEV1_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
169203. BIF_CFG_DEV1_EPF0_1_SUB_CLASS__SUB_CLASS_MASK
169204. BIF_CFG_DEV1_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT
169205. BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK
169206. BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT
169207. BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK
169208. BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT
169209. BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK
169210. BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
169211. BIF_CFG_DEV1_EPF0_1_VENDOR_ID__VENDOR_ID_MASK
169212. BIF_CFG_DEV1_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT
169213. BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
169214. BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
169215. BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
169216. BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
169217. BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID_MASK
169218. BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
169219. BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
169220. BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
169221. BIF_CFG_DEV1_EPF0_2_BASE_ADDR_1__BASE_ADDR_MASK
169222. BIF_CFG_DEV1_EPF0_2_BASE_ADDR_1__BASE_ADDR__SHIFT
169223. BIF_CFG_DEV1_EPF0_2_BASE_ADDR_2__BASE_ADDR_MASK
169224. BIF_CFG_DEV1_EPF0_2_BASE_ADDR_2__BASE_ADDR__SHIFT
169225. BIF_CFG_DEV1_EPF0_2_BASE_ADDR_3__BASE_ADDR_MASK
169226. BIF_CFG_DEV1_EPF0_2_BASE_ADDR_3__BASE_ADDR__SHIFT
169227. BIF_CFG_DEV1_EPF0_2_BASE_ADDR_4__BASE_ADDR_MASK
169228. BIF_CFG_DEV1_EPF0_2_BASE_ADDR_4__BASE_ADDR__SHIFT
169229. BIF_CFG_DEV1_EPF0_2_BASE_ADDR_5__BASE_ADDR_MASK
169230. BIF_CFG_DEV1_EPF0_2_BASE_ADDR_5__BASE_ADDR__SHIFT
169231. BIF_CFG_DEV1_EPF0_2_BASE_ADDR_6__BASE_ADDR_MASK
169232. BIF_CFG_DEV1_EPF0_2_BASE_ADDR_6__BASE_ADDR__SHIFT
169233. BIF_CFG_DEV1_EPF0_2_BASE_CLASS__BASE_CLASS_MASK
169234. BIF_CFG_DEV1_EPF0_2_BASE_CLASS__BASE_CLASS__SHIFT
169235. BIF_CFG_DEV1_EPF0_2_BIST__BIST_CAP_MASK
169236. BIF_CFG_DEV1_EPF0_2_BIST__BIST_CAP__SHIFT
169237. BIF_CFG_DEV1_EPF0_2_BIST__BIST_COMP_MASK
169238. BIF_CFG_DEV1_EPF0_2_BIST__BIST_COMP__SHIFT
169239. BIF_CFG_DEV1_EPF0_2_BIST__BIST_STRT_MASK
169240. BIF_CFG_DEV1_EPF0_2_BIST__BIST_STRT__SHIFT
169241. BIF_CFG_DEV1_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
169242. BIF_CFG_DEV1_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
169243. BIF_CFG_DEV1_EPF0_2_CAP_PTR__CAP_PTR_MASK
169244. BIF_CFG_DEV1_EPF0_2_CAP_PTR__CAP_PTR__SHIFT
169245. BIF_CFG_DEV1_EPF0_2_COMMAND__AD_STEPPING_MASK
169246. BIF_CFG_DEV1_EPF0_2_COMMAND__AD_STEPPING__SHIFT
169247. BIF_CFG_DEV1_EPF0_2_COMMAND__BUS_MASTER_EN_MASK
169248. BIF_CFG_DEV1_EPF0_2_COMMAND__BUS_MASTER_EN__SHIFT
169249. BIF_CFG_DEV1_EPF0_2_COMMAND__FAST_B2B_EN_MASK
169250. BIF_CFG_DEV1_EPF0_2_COMMAND__FAST_B2B_EN__SHIFT
169251. BIF_CFG_DEV1_EPF0_2_COMMAND__INT_DIS_MASK
169252. BIF_CFG_DEV1_EPF0_2_COMMAND__INT_DIS__SHIFT
169253. BIF_CFG_DEV1_EPF0_2_COMMAND__IO_ACCESS_EN_MASK
169254. BIF_CFG_DEV1_EPF0_2_COMMAND__IO_ACCESS_EN__SHIFT
169255. BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_ACCESS_EN_MASK
169256. BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_ACCESS_EN__SHIFT
169257. BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
169258. BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
169259. BIF_CFG_DEV1_EPF0_2_COMMAND__PAL_SNOOP_EN_MASK
169260. BIF_CFG_DEV1_EPF0_2_COMMAND__PAL_SNOOP_EN__SHIFT
169261. BIF_CFG_DEV1_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
169262. BIF_CFG_DEV1_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
169263. BIF_CFG_DEV1_EPF0_2_COMMAND__SERR_EN_MASK
169264. BIF_CFG_DEV1_EPF0_2_COMMAND__SERR_EN__SHIFT
169265. BIF_CFG_DEV1_EPF0_2_COMMAND__SPECIAL_CYCLE_EN_MASK
169266. BIF_CFG_DEV1_EPF0_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
169267. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
169268. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
169269. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
169270. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
169271. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
169272. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
169273. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
169274. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
169275. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
169276. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
169277. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
169278. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
169279. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
169280. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
169281. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
169282. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
169283. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
169284. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
169285. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
169286. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
169287. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
169288. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
169289. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
169290. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
169291. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
169292. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
169293. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
169294. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
169295. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
169296. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
169297. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
169298. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
169299. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__EXTENDED_TAG_MASK
169300. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
169301. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__FLR_CAPABLE_MASK
169302. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
169303. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
169304. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
169305. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
169306. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
169307. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
169308. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
169309. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__PHANTOM_FUNC_MASK
169310. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
169311. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
169312. BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
169313. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
169314. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
169315. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
169316. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
169317. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
169318. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
169319. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
169320. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
169321. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
169322. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
169323. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
169324. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
169325. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
169326. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
169327. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
169328. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
169329. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__LTR_EN_MASK
169330. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__LTR_EN__SHIFT
169331. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__OBFF_EN_MASK
169332. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__OBFF_EN__SHIFT
169333. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
169334. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
169335. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__CORR_ERR_EN_MASK
169336. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
169337. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
169338. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
169339. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
169340. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
169341. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__INITIATE_FLR_MASK
169342. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__INITIATE_FLR__SHIFT
169343. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
169344. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
169345. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
169346. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
169347. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
169348. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
169349. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
169350. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
169351. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
169352. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
169353. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
169354. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
169355. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__USR_REPORT_EN_MASK
169356. BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
169357. BIF_CFG_DEV1_EPF0_2_DEVICE_ID__DEVICE_ID_MASK
169358. BIF_CFG_DEV1_EPF0_2_DEVICE_ID__DEVICE_ID__SHIFT
169359. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS2__RESERVED_MASK
169360. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS2__RESERVED__SHIFT
169361. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__AUX_PWR_MASK
169362. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__AUX_PWR__SHIFT
169363. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__CORR_ERR_MASK
169364. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__CORR_ERR__SHIFT
169365. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__FATAL_ERR_MASK
169366. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__FATAL_ERR__SHIFT
169367. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
169368. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
169369. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
169370. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
169371. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__USR_DETECTED_MASK
169372. BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__USR_DETECTED__SHIFT
169373. BIF_CFG_DEV1_EPF0_2_HEADER__DEVICE_TYPE_MASK
169374. BIF_CFG_DEV1_EPF0_2_HEADER__DEVICE_TYPE__SHIFT
169375. BIF_CFG_DEV1_EPF0_2_HEADER__HEADER_TYPE_MASK
169376. BIF_CFG_DEV1_EPF0_2_HEADER__HEADER_TYPE__SHIFT
169377. BIF_CFG_DEV1_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
169378. BIF_CFG_DEV1_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
169379. BIF_CFG_DEV1_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
169380. BIF_CFG_DEV1_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
169381. BIF_CFG_DEV1_EPF0_2_LATENCY__LATENCY_TIMER_MASK
169382. BIF_CFG_DEV1_EPF0_2_LATENCY__LATENCY_TIMER__SHIFT
169383. BIF_CFG_DEV1_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
169384. BIF_CFG_DEV1_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
169385. BIF_CFG_DEV1_EPF0_2_LINK_CAP2__RESERVED_MASK
169386. BIF_CFG_DEV1_EPF0_2_LINK_CAP2__RESERVED__SHIFT
169387. BIF_CFG_DEV1_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
169388. BIF_CFG_DEV1_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
169389. BIF_CFG_DEV1_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
169390. BIF_CFG_DEV1_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
169391. BIF_CFG_DEV1_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
169392. BIF_CFG_DEV1_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
169393. BIF_CFG_DEV1_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
169394. BIF_CFG_DEV1_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
169395. BIF_CFG_DEV1_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
169396. BIF_CFG_DEV1_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
169397. BIF_CFG_DEV1_EPF0_2_LINK_CAP__L1_EXIT_LATENCY_MASK
169398. BIF_CFG_DEV1_EPF0_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
169399. BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
169400. BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
169401. BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_SPEED_MASK
169402. BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_SPEED__SHIFT
169403. BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_WIDTH_MASK
169404. BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_WIDTH__SHIFT
169405. BIF_CFG_DEV1_EPF0_2_LINK_CAP__PM_SUPPORT_MASK
169406. BIF_CFG_DEV1_EPF0_2_LINK_CAP__PM_SUPPORT__SHIFT
169407. BIF_CFG_DEV1_EPF0_2_LINK_CAP__PORT_NUMBER_MASK
169408. BIF_CFG_DEV1_EPF0_2_LINK_CAP__PORT_NUMBER__SHIFT
169409. BIF_CFG_DEV1_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
169410. BIF_CFG_DEV1_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
169411. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
169412. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
169413. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
169414. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
169415. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
169416. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
169417. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
169418. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
169419. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
169420. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
169421. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
169422. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
169423. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
169424. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
169425. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__XMIT_MARGIN_MASK
169426. BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
169427. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
169428. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
169429. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
169430. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
169431. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__EXTENDED_SYNC_MASK
169432. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
169433. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
169434. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
169435. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
169436. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
169437. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
169438. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
169439. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_DIS_MASK
169440. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_DIS__SHIFT
169441. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__PM_CONTROL_MASK
169442. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__PM_CONTROL__SHIFT
169443. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
169444. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
169445. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__RETRAIN_LINK_MASK
169446. BIF_CFG_DEV1_EPF0_2_LINK_CNTL__RETRAIN_LINK__SHIFT
169447. BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
169448. BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
169449. BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
169450. BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
169451. BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
169452. BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
169453. BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
169454. BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
169455. BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
169456. BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
169457. BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
169458. BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
169459. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
169460. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
169461. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__DL_ACTIVE_MASK
169462. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__DL_ACTIVE__SHIFT
169463. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
169464. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
169465. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
169466. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
169467. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_TRAINING_MASK
169468. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_TRAINING__SHIFT
169469. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
169470. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
169471. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
169472. BIF_CFG_DEV1_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
169473. BIF_CFG_DEV1_EPF0_2_MAX_LATENCY__MAX_LAT_MASK
169474. BIF_CFG_DEV1_EPF0_2_MAX_LATENCY__MAX_LAT__SHIFT
169475. BIF_CFG_DEV1_EPF0_2_MIN_GRANT__MIN_GNT_MASK
169476. BIF_CFG_DEV1_EPF0_2_MIN_GRANT__MIN_GNT__SHIFT
169477. BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__CAP_ID_MASK
169478. BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__CAP_ID__SHIFT
169479. BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__NEXT_PTR_MASK
169480. BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT
169481. BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_EN_MASK
169482. BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT
169483. BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
169484. BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
169485. BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
169486. BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
169487. BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_BIR_MASK
169488. BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT
169489. BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK
169490. BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
169491. BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK
169492. BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
169493. BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
169494. BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
169495. BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__CAP_ID_MASK
169496. BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__CAP_ID__SHIFT
169497. BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__NEXT_PTR_MASK
169498. BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
169499. BIF_CFG_DEV1_EPF0_2_MSI_MASK_64__MSI_MASK_64_MASK
169500. BIF_CFG_DEV1_EPF0_2_MSI_MASK_64__MSI_MASK_64__SHIFT
169501. BIF_CFG_DEV1_EPF0_2_MSI_MASK__MSI_MASK_MASK
169502. BIF_CFG_DEV1_EPF0_2_MSI_MASK__MSI_MASK__SHIFT
169503. BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
169504. BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
169505. BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
169506. BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
169507. BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_64BIT_MASK
169508. BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
169509. BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_EN_MASK
169510. BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_EN__SHIFT
169511. BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
169512. BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
169513. BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
169514. BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
169515. BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
169516. BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
169517. BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
169518. BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
169519. BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA__MSI_DATA_MASK
169520. BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA__MSI_DATA__SHIFT
169521. BIF_CFG_DEV1_EPF0_2_MSI_PENDING_64__MSI_PENDING_64_MASK
169522. BIF_CFG_DEV1_EPF0_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT
169523. BIF_CFG_DEV1_EPF0_2_MSI_PENDING__MSI_PENDING_MASK
169524. BIF_CFG_DEV1_EPF0_2_MSI_PENDING__MSI_PENDING__SHIFT
169525. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
169526. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
169527. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
169528. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
169529. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
169530. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
169531. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
169532. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
169533. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
169534. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
169535. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
169536. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
169537. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
169538. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
169539. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
169540. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
169541. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
169542. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
169543. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
169544. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
169545. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
169546. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
169547. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
169548. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
169549. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
169550. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
169551. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
169552. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
169553. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
169554. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
169555. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
169556. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
169557. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
169558. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
169559. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
169560. BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
169561. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
169562. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
169563. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
169564. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
169565. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
169566. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
169567. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
169568. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
169569. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
169570. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
169571. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
169572. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
169573. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
169574. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
169575. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
169576. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
169577. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
169578. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
169579. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
169580. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
169581. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
169582. BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
169583. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
169584. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
169585. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
169586. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
169587. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
169588. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
169589. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
169590. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
169591. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
169592. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
169593. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
169594. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
169595. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
169596. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
169597. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
169598. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
169599. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
169600. BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
169601. BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
169602. BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
169603. BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK
169604. BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
169605. BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK
169606. BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
169607. BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
169608. BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
169609. BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
169610. BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
169611. BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK
169612. BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
169613. BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK
169614. BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
169615. BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
169616. BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
169617. BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
169618. BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
169619. BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK
169620. BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
169621. BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK
169622. BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
169623. BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
169624. BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
169625. BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
169626. BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
169627. BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK
169628. BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
169629. BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK
169630. BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
169631. BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
169632. BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
169633. BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
169634. BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
169635. BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK
169636. BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
169637. BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK
169638. BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
169639. BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
169640. BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
169641. BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
169642. BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
169643. BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK
169644. BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
169645. BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK
169646. BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
169647. BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
169648. BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
169649. BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
169650. BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
169651. BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
169652. BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
169653. BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
169654. BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
169655. BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__CAP_ID_MASK
169656. BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__CAP_ID__SHIFT
169657. BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__NEXT_PTR_MASK
169658. BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
169659. BIF_CFG_DEV1_EPF0_2_PCIE_CAP__DEVICE_TYPE_MASK
169660. BIF_CFG_DEV1_EPF0_2_PCIE_CAP__DEVICE_TYPE__SHIFT
169661. BIF_CFG_DEV1_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
169662. BIF_CFG_DEV1_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
169663. BIF_CFG_DEV1_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
169664. BIF_CFG_DEV1_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
169665. BIF_CFG_DEV1_EPF0_2_PCIE_CAP__VERSION_MASK
169666. BIF_CFG_DEV1_EPF0_2_PCIE_CAP__VERSION__SHIFT
169667. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
169668. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
169669. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
169670. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
169671. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
169672. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
169673. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
169674. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
169675. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
169676. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
169677. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
169678. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
169679. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
169680. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
169681. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
169682. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
169683. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
169684. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
169685. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
169686. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
169687. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
169688. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
169689. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
169690. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
169691. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
169692. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
169693. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
169694. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
169695. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
169696. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
169697. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
169698. BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
169699. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
169700. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
169701. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
169702. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
169703. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
169704. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
169705. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
169706. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
169707. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
169708. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
169709. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
169710. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
169711. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
169712. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
169713. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
169714. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
169715. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
169716. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
169717. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
169718. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
169719. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
169720. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
169721. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
169722. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
169723. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
169724. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
169725. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
169726. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
169727. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
169728. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
169729. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
169730. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
169731. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
169732. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
169733. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
169734. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
169735. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
169736. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
169737. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
169738. BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
169739. BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG0__TLP_HDR_MASK
169740. BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
169741. BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG1__TLP_HDR_MASK
169742. BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
169743. BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG2__TLP_HDR_MASK
169744. BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
169745. BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG3__TLP_HDR_MASK
169746. BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
169747. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169748. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169749. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169750. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169751. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
169752. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
169753. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169754. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169755. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169756. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169757. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169758. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169759. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169760. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169761. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
169762. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
169763. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169764. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169765. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169766. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169767. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169768. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169769. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169770. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169771. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
169772. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
169773. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169774. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169775. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169776. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169777. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169778. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169779. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169780. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169781. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
169782. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
169783. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169784. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169785. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169786. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169787. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169788. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169789. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169790. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169791. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
169792. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
169793. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169794. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169795. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169796. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169797. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169798. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169799. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169800. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169801. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
169802. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
169803. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169804. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169805. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169806. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169807. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169808. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169809. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169810. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169811. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
169812. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
169813. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169814. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169815. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169816. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169817. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169818. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169819. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169820. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169821. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
169822. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
169823. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169824. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169825. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169826. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169827. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169828. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169829. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169830. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169831. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
169832. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
169833. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169834. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169835. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169836. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169837. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169838. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169839. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169840. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169841. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
169842. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
169843. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169844. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169845. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169846. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169847. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169848. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169849. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169850. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169851. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
169852. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
169853. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169854. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169855. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169856. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169857. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169858. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169859. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169860. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169861. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
169862. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
169863. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169864. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169865. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169866. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169867. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169868. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169869. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169870. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169871. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
169872. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
169873. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169874. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169875. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169876. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169877. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169878. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169879. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169880. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169881. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
169882. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
169883. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169884. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169885. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169886. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169887. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169888. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169889. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169890. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169891. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
169892. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
169893. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169894. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169895. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169896. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169897. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
169898. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
169899. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
169900. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
169901. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
169902. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
169903. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
169904. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
169905. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
169906. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
169907. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
169908. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
169909. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
169910. BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
169911. BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
169912. BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
169913. BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
169914. BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
169915. BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__RESERVED_MASK
169916. BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__RESERVED__SHIFT
169917. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
169918. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
169919. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
169920. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
169921. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
169922. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
169923. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
169924. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
169925. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
169926. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
169927. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
169928. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
169929. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
169930. BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
169931. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
169932. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
169933. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
169934. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
169935. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
169936. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
169937. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
169938. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
169939. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
169940. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
169941. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
169942. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
169943. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
169944. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
169945. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
169946. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
169947. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
169948. BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
169949. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
169950. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
169951. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
169952. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
169953. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
169954. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
169955. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
169956. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
169957. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
169958. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
169959. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
169960. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
169961. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
169962. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
169963. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK
169964. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
169965. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
169966. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
169967. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
169968. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
169969. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
169970. BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
169971. BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
169972. BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
169973. BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
169974. BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
169975. BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
169976. BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
169977. BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
169978. BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
169979. BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
169980. BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
169981. BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
169982. BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
169983. BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
169984. BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
169985. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
169986. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
169987. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
169988. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
169989. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
169990. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
169991. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
169992. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
169993. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
169994. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
169995. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
169996. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
169997. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
169998. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
169999. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
170000. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
170001. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
170002. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
170003. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
170004. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
170005. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
170006. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
170007. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
170008. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
170009. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
170010. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
170011. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
170012. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
170013. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
170014. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
170015. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
170016. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
170017. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
170018. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
170019. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
170020. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
170021. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
170022. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
170023. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
170024. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
170025. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
170026. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
170027. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
170028. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
170029. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
170030. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
170031. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
170032. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
170033. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
170034. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
170035. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
170036. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
170037. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
170038. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
170039. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
170040. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
170041. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
170042. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
170043. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
170044. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
170045. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
170046. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
170047. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
170048. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
170049. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
170050. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
170051. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
170052. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
170053. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
170054. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
170055. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
170056. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
170057. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
170058. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
170059. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
170060. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
170061. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
170062. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
170063. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
170064. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
170065. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
170066. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
170067. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
170068. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
170069. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
170070. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
170071. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
170072. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
170073. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
170074. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
170075. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
170076. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
170077. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
170078. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
170079. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
170080. BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
170081. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
170082. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
170083. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
170084. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
170085. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
170086. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
170087. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
170088. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
170089. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
170090. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
170091. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
170092. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
170093. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
170094. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
170095. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
170096. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
170097. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
170098. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
170099. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
170100. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
170101. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
170102. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
170103. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
170104. BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
170105. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
170106. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
170107. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
170108. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
170109. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
170110. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
170111. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
170112. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
170113. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
170114. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
170115. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
170116. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
170117. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
170118. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
170119. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
170120. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
170121. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
170122. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
170123. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
170124. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
170125. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
170126. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
170127. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
170128. BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
170129. BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
170130. BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
170131. BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
170132. BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
170133. BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
170134. BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
170135. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
170136. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
170137. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
170138. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
170139. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
170140. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
170141. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
170142. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
170143. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
170144. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
170145. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
170146. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
170147. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
170148. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
170149. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
170150. BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
170151. BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__CAP_ID_MASK
170152. BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__CAP_ID__SHIFT
170153. BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__NEXT_PTR_MASK
170154. BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
170155. BIF_CFG_DEV1_EPF0_2_PMI_CAP__AUX_CURRENT_MASK
170156. BIF_CFG_DEV1_EPF0_2_PMI_CAP__AUX_CURRENT__SHIFT
170157. BIF_CFG_DEV1_EPF0_2_PMI_CAP__D1_SUPPORT_MASK
170158. BIF_CFG_DEV1_EPF0_2_PMI_CAP__D1_SUPPORT__SHIFT
170159. BIF_CFG_DEV1_EPF0_2_PMI_CAP__D2_SUPPORT_MASK
170160. BIF_CFG_DEV1_EPF0_2_PMI_CAP__D2_SUPPORT__SHIFT
170161. BIF_CFG_DEV1_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
170162. BIF_CFG_DEV1_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
170163. BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_CLOCK_MASK
170164. BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_CLOCK__SHIFT
170165. BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_SUPPORT_MASK
170166. BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_SUPPORT__SHIFT
170167. BIF_CFG_DEV1_EPF0_2_PMI_CAP__VERSION_MASK
170168. BIF_CFG_DEV1_EPF0_2_PMI_CAP__VERSION__SHIFT
170169. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
170170. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
170171. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
170172. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
170173. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
170174. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
170175. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
170176. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
170177. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
170178. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
170179. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_EN_MASK
170180. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_EN__SHIFT
170181. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_STATUS_MASK
170182. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
170183. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PMI_DATA_MASK
170184. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
170185. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__POWER_STATE_MASK
170186. BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
170187. BIF_CFG_DEV1_EPF0_2_PROG_INTERFACE__PROG_INTERFACE_MASK
170188. BIF_CFG_DEV1_EPF0_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
170189. BIF_CFG_DEV1_EPF0_2_REVISION_ID__MAJOR_REV_ID_MASK
170190. BIF_CFG_DEV1_EPF0_2_REVISION_ID__MAJOR_REV_ID__SHIFT
170191. BIF_CFG_DEV1_EPF0_2_REVISION_ID__MINOR_REV_ID_MASK
170192. BIF_CFG_DEV1_EPF0_2_REVISION_ID__MINOR_REV_ID__SHIFT
170193. BIF_CFG_DEV1_EPF0_2_ROM_BASE_ADDR__BASE_ADDR_MASK
170194. BIF_CFG_DEV1_EPF0_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT
170195. BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__CAP_ID_MASK
170196. BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__CAP_ID__SHIFT
170197. BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__NEXT_PTR_MASK
170198. BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__NEXT_PTR__SHIFT
170199. BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
170200. BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
170201. BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
170202. BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
170203. BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
170204. BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
170205. BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
170206. BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
170207. BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
170208. BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
170209. BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
170210. BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
170211. BIF_CFG_DEV1_EPF0_2_SATA_IDP_DATA__IDP_DATA_MASK
170212. BIF_CFG_DEV1_EPF0_2_SATA_IDP_DATA__IDP_DATA__SHIFT
170213. BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_INDEX_MASK
170214. BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT
170215. BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK
170216. BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
170217. BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK
170218. BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
170219. BIF_CFG_DEV1_EPF0_2_SLOT_CAP2__RESERVED_MASK
170220. BIF_CFG_DEV1_EPF0_2_SLOT_CAP2__RESERVED__SHIFT
170221. BIF_CFG_DEV1_EPF0_2_SLOT_CNTL2__RESERVED_MASK
170222. BIF_CFG_DEV1_EPF0_2_SLOT_CNTL2__RESERVED__SHIFT
170223. BIF_CFG_DEV1_EPF0_2_SLOT_STATUS2__RESERVED_MASK
170224. BIF_CFG_DEV1_EPF0_2_SLOT_STATUS2__RESERVED__SHIFT
170225. BIF_CFG_DEV1_EPF0_2_STATUS__CAP_LIST_MASK
170226. BIF_CFG_DEV1_EPF0_2_STATUS__CAP_LIST__SHIFT
170227. BIF_CFG_DEV1_EPF0_2_STATUS__DEVSEL_TIMING_MASK
170228. BIF_CFG_DEV1_EPF0_2_STATUS__DEVSEL_TIMING__SHIFT
170229. BIF_CFG_DEV1_EPF0_2_STATUS__FAST_BACK_CAPABLE_MASK
170230. BIF_CFG_DEV1_EPF0_2_STATUS__FAST_BACK_CAPABLE__SHIFT
170231. BIF_CFG_DEV1_EPF0_2_STATUS__INT_STATUS_MASK
170232. BIF_CFG_DEV1_EPF0_2_STATUS__INT_STATUS__SHIFT
170233. BIF_CFG_DEV1_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
170234. BIF_CFG_DEV1_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
170235. BIF_CFG_DEV1_EPF0_2_STATUS__PARITY_ERROR_DETECTED_MASK
170236. BIF_CFG_DEV1_EPF0_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
170237. BIF_CFG_DEV1_EPF0_2_STATUS__PCI_66_EN_MASK
170238. BIF_CFG_DEV1_EPF0_2_STATUS__PCI_66_EN__SHIFT
170239. BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_MASTER_ABORT_MASK
170240. BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
170241. BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_TARGET_ABORT_MASK
170242. BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
170243. BIF_CFG_DEV1_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
170244. BIF_CFG_DEV1_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
170245. BIF_CFG_DEV1_EPF0_2_STATUS__SIGNAL_TARGET_ABORT_MASK
170246. BIF_CFG_DEV1_EPF0_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
170247. BIF_CFG_DEV1_EPF0_2_SUB_CLASS__SUB_CLASS_MASK
170248. BIF_CFG_DEV1_EPF0_2_SUB_CLASS__SUB_CLASS__SHIFT
170249. BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__CAP_ID_MASK
170250. BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__CAP_ID__SHIFT
170251. BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__LENGTH_MASK
170252. BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__LENGTH__SHIFT
170253. BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR_MASK
170254. BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
170255. BIF_CFG_DEV1_EPF0_2_VENDOR_ID__VENDOR_ID_MASK
170256. BIF_CFG_DEV1_EPF0_2_VENDOR_ID__VENDOR_ID__SHIFT
170257. BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
170258. BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
170259. BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
170260. BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
170261. BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
170262. BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
170263. BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
170264. BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
170265. BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK
170266. BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT
170267. BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK
170268. BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT
170269. BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK
170270. BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT
170271. BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK
170272. BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT
170273. BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK
170274. BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT
170275. BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK
170276. BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT
170277. BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS_MASK
170278. BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT
170279. BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP_MASK
170280. BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP__SHIFT
170281. BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP_MASK
170282. BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP__SHIFT
170283. BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT_MASK
170284. BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT__SHIFT
170285. BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
170286. BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
170287. BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR_MASK
170288. BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR__SHIFT
170289. BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING_MASK
170290. BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING__SHIFT
170291. BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN_MASK
170292. BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT
170293. BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN_MASK
170294. BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT
170295. BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS_MASK
170296. BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS__SHIFT
170297. BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN_MASK
170298. BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT
170299. BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK
170300. BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT
170301. BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
170302. BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
170303. BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK
170304. BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT
170305. BIF_CFG_DEV1_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
170306. BIF_CFG_DEV1_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
170307. BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN_MASK
170308. BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN__SHIFT
170309. BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK
170310. BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
170311. BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD_MASK
170312. BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD__SHIFT
170313. BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL_MASK
170314. BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL__SHIFT
170315. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
170316. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
170317. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
170318. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
170319. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
170320. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
170321. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
170322. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
170323. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
170324. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
170325. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
170326. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
170327. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
170328. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
170329. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
170330. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
170331. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
170332. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
170333. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
170334. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
170335. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
170336. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
170337. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
170338. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
170339. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
170340. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
170341. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
170342. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
170343. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
170344. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
170345. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
170346. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
170347. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK
170348. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
170349. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK
170350. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
170351. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
170352. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
170353. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
170354. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
170355. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
170356. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
170357. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK
170358. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
170359. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
170360. BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
170361. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
170362. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
170363. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
170364. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
170365. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
170366. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
170367. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
170368. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
170369. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
170370. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
170371. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
170372. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
170373. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
170374. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
170375. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
170376. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
170377. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK
170378. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT
170379. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK
170380. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT
170381. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
170382. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
170383. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK
170384. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
170385. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
170386. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
170387. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
170388. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
170389. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK
170390. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
170391. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
170392. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
170393. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
170394. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
170395. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
170396. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
170397. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
170398. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
170399. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
170400. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
170401. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
170402. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
170403. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK
170404. BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
170405. BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID_MASK
170406. BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT
170407. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED_MASK
170408. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT
170409. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK
170410. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT
170411. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK
170412. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT
170413. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK
170414. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT
170415. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
170416. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
170417. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
170418. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
170419. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK
170420. BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT
170421. BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ_MASK
170422. BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ__SHIFT
170423. BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE_MASK
170424. BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE__SHIFT
170425. BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE_MASK
170426. BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE__SHIFT
170427. BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
170428. BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
170429. BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
170430. BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
170431. BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER_MASK
170432. BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT
170433. BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
170434. BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
170435. BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RESERVED_MASK
170436. BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RESERVED__SHIFT
170437. BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
170438. BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
170439. BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
170440. BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
170441. BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
170442. BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
170443. BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
170444. BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
170445. BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
170446. BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
170447. BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK
170448. BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
170449. BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
170450. BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
170451. BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED_MASK
170452. BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT
170453. BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH_MASK
170454. BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT
170455. BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT_MASK
170456. BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT
170457. BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER_MASK
170458. BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT
170459. BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
170460. BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
170461. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
170462. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
170463. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
170464. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
170465. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
170466. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
170467. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
170468. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
170469. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
170470. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
170471. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
170472. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
170473. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
170474. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
170475. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK
170476. BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
170477. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
170478. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
170479. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
170480. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
170481. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK
170482. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
170483. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
170484. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
170485. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
170486. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
170487. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
170488. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
170489. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS_MASK
170490. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT
170491. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL_MASK
170492. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT
170493. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
170494. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
170495. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK
170496. BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT
170497. BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
170498. BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
170499. BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
170500. BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
170501. BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
170502. BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
170503. BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
170504. BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
170505. BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
170506. BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
170507. BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
170508. BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
170509. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
170510. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
170511. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK
170512. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT
170513. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
170514. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
170515. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
170516. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
170517. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK
170518. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT
170519. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
170520. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
170521. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
170522. BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
170523. BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT_MASK
170524. BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT
170525. BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT_MASK
170526. BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT
170527. BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK
170528. BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT
170529. BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK
170530. BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
170531. BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK
170532. BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
170533. BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
170534. BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
170535. BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
170536. BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
170537. BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK
170538. BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
170539. BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
170540. BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
170541. BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
170542. BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
170543. BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
170544. BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
170545. BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK
170546. BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT
170547. BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK
170548. BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
170549. BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK
170550. BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT
170551. BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK_MASK
170552. BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK__SHIFT
170553. BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
170554. BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
170555. BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
170556. BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
170557. BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK
170558. BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
170559. BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK
170560. BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT
170561. BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
170562. BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
170563. BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
170564. BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
170565. BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
170566. BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
170567. BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
170568. BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
170569. BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK
170570. BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT
170571. BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK
170572. BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
170573. BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING_MASK
170574. BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT
170575. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
170576. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
170577. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
170578. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
170579. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
170580. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
170581. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
170582. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
170583. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
170584. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
170585. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
170586. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
170587. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
170588. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
170589. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
170590. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
170591. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
170592. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
170593. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
170594. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
170595. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
170596. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
170597. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
170598. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
170599. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
170600. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
170601. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
170602. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
170603. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
170604. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
170605. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
170606. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
170607. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
170608. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
170609. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
170610. BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
170611. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
170612. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
170613. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
170614. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
170615. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
170616. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
170617. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
170618. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
170619. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
170620. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
170621. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
170622. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
170623. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
170624. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
170625. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
170626. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
170627. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
170628. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
170629. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
170630. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
170631. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
170632. BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
170633. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
170634. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
170635. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
170636. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
170637. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
170638. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
170639. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
170640. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
170641. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
170642. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
170643. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
170644. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
170645. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
170646. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
170647. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
170648. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
170649. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
170650. BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
170651. BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
170652. BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
170653. BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK
170654. BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
170655. BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK
170656. BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
170657. BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
170658. BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
170659. BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
170660. BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
170661. BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK
170662. BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
170663. BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK
170664. BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
170665. BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
170666. BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
170667. BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
170668. BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
170669. BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK
170670. BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
170671. BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK
170672. BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
170673. BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
170674. BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
170675. BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
170676. BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
170677. BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK
170678. BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
170679. BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK
170680. BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
170681. BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
170682. BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
170683. BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
170684. BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
170685. BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK
170686. BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
170687. BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK
170688. BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
170689. BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
170690. BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
170691. BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
170692. BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
170693. BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK
170694. BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
170695. BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK
170696. BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
170697. BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
170698. BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
170699. BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
170700. BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
170701. BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
170702. BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
170703. BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
170704. BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
170705. BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK
170706. BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT
170707. BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK
170708. BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
170709. BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK
170710. BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT
170711. BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
170712. BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
170713. BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
170714. BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
170715. BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION_MASK
170716. BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION__SHIFT
170717. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
170718. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
170719. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
170720. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
170721. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
170722. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
170723. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
170724. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
170725. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
170726. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
170727. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
170728. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
170729. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
170730. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
170731. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
170732. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
170733. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
170734. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
170735. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
170736. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
170737. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
170738. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
170739. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
170740. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
170741. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
170742. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
170743. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
170744. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
170745. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
170746. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
170747. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
170748. BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
170749. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
170750. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
170751. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
170752. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
170753. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
170754. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
170755. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
170756. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
170757. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
170758. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
170759. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
170760. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
170761. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
170762. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
170763. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
170764. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
170765. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
170766. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
170767. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
170768. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
170769. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
170770. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
170771. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
170772. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
170773. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
170774. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
170775. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
170776. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
170777. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
170778. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
170779. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
170780. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
170781. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
170782. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
170783. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
170784. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
170785. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
170786. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
170787. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
170788. BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
170789. BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK
170790. BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
170791. BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK
170792. BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
170793. BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK
170794. BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
170795. BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK
170796. BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
170797. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
170798. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
170799. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
170800. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
170801. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
170802. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
170803. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
170804. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
170805. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
170806. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
170807. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
170808. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
170809. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
170810. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
170811. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK
170812. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
170813. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
170814. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
170815. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
170816. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
170817. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
170818. BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
170819. BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
170820. BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
170821. BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
170822. BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
170823. BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
170824. BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
170825. BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
170826. BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
170827. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
170828. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
170829. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
170830. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
170831. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
170832. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
170833. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
170834. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
170835. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
170836. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
170837. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
170838. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
170839. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
170840. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
170841. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
170842. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
170843. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
170844. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
170845. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
170846. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
170847. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
170848. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
170849. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
170850. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
170851. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
170852. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
170853. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
170854. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
170855. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
170856. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
170857. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
170858. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
170859. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
170860. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
170861. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
170862. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
170863. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
170864. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
170865. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
170866. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
170867. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
170868. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
170869. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
170870. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
170871. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
170872. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
170873. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
170874. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
170875. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
170876. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
170877. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
170878. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
170879. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
170880. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
170881. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
170882. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
170883. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
170884. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
170885. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
170886. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
170887. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
170888. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
170889. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
170890. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
170891. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
170892. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
170893. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
170894. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
170895. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
170896. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
170897. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
170898. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
170899. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
170900. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
170901. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
170902. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
170903. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
170904. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
170905. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
170906. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
170907. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
170908. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
170909. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
170910. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
170911. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
170912. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
170913. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
170914. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
170915. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
170916. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
170917. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
170918. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
170919. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
170920. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
170921. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
170922. BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
170923. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
170924. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
170925. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
170926. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
170927. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
170928. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
170929. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
170930. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
170931. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
170932. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
170933. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
170934. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
170935. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
170936. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
170937. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
170938. BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
170939. BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK
170940. BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT
170941. BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK
170942. BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
170943. BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT_MASK
170944. BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT
170945. BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT_MASK
170946. BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT
170947. BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT_MASK
170948. BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT
170949. BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
170950. BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
170951. BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK_MASK
170952. BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT
170953. BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT_MASK
170954. BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT
170955. BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION_MASK
170956. BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION__SHIFT
170957. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
170958. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
170959. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
170960. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
170961. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
170962. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
170963. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
170964. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
170965. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
170966. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
170967. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK
170968. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT
170969. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK
170970. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
170971. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK
170972. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
170973. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK
170974. BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
170975. BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK
170976. BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
170977. BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK
170978. BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT
170979. BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK
170980. BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT
170981. BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK
170982. BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
170983. BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__CAP_ID_MASK
170984. BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__CAP_ID__SHIFT
170985. BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__NEXT_PTR_MASK
170986. BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__NEXT_PTR__SHIFT
170987. BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
170988. BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
170989. BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
170990. BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
170991. BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
170992. BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
170993. BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
170994. BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
170995. BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
170996. BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
170997. BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
170998. BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
170999. BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA__IDP_DATA_MASK
171000. BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA__IDP_DATA__SHIFT
171001. BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_INDEX_MASK
171002. BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT
171003. BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK
171004. BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
171005. BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK
171006. BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
171007. BIF_CFG_DEV1_EPF1_0_SBRN__SBRN_MASK
171008. BIF_CFG_DEV1_EPF1_0_SBRN__SBRN__SHIFT
171009. BIF_CFG_DEV1_EPF1_0_SLOT_CAP2__RESERVED_MASK
171010. BIF_CFG_DEV1_EPF1_0_SLOT_CAP2__RESERVED__SHIFT
171011. BIF_CFG_DEV1_EPF1_0_SLOT_CNTL2__RESERVED_MASK
171012. BIF_CFG_DEV1_EPF1_0_SLOT_CNTL2__RESERVED__SHIFT
171013. BIF_CFG_DEV1_EPF1_0_SLOT_STATUS2__RESERVED_MASK
171014. BIF_CFG_DEV1_EPF1_0_SLOT_STATUS2__RESERVED__SHIFT
171015. BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST_MASK
171016. BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST__SHIFT
171017. BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING_MASK
171018. BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT
171019. BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK
171020. BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT
171021. BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS_MASK
171022. BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS__SHIFT
171023. BIF_CFG_DEV1_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
171024. BIF_CFG_DEV1_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
171025. BIF_CFG_DEV1_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK
171026. BIF_CFG_DEV1_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
171027. BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_EN_MASK
171028. BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_EN__SHIFT
171029. BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK
171030. BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
171031. BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK
171032. BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
171033. BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
171034. BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
171035. BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK
171036. BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
171037. BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS_MASK
171038. BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT
171039. BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK
171040. BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT
171041. BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK
171042. BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT
171043. BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK
171044. BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
171045. BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID_MASK
171046. BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT
171047. BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
171048. BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
171049. BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
171050. BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
171051. BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
171052. BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
171053. BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
171054. BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
171055. BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK
171056. BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT
171057. BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK
171058. BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT
171059. BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK
171060. BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT
171061. BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK
171062. BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT
171063. BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK
171064. BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT
171065. BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK
171066. BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT
171067. BIF_CFG_DEV1_EPF1_1_BASE_CLASS__BASE_CLASS_MASK
171068. BIF_CFG_DEV1_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT
171069. BIF_CFG_DEV1_EPF1_1_BIST__BIST_CAP_MASK
171070. BIF_CFG_DEV1_EPF1_1_BIST__BIST_CAP__SHIFT
171071. BIF_CFG_DEV1_EPF1_1_BIST__BIST_COMP_MASK
171072. BIF_CFG_DEV1_EPF1_1_BIST__BIST_COMP__SHIFT
171073. BIF_CFG_DEV1_EPF1_1_BIST__BIST_STRT_MASK
171074. BIF_CFG_DEV1_EPF1_1_BIST__BIST_STRT__SHIFT
171075. BIF_CFG_DEV1_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
171076. BIF_CFG_DEV1_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
171077. BIF_CFG_DEV1_EPF1_1_CAP_PTR__CAP_PTR_MASK
171078. BIF_CFG_DEV1_EPF1_1_CAP_PTR__CAP_PTR__SHIFT
171079. BIF_CFG_DEV1_EPF1_1_COMMAND__AD_STEPPING_MASK
171080. BIF_CFG_DEV1_EPF1_1_COMMAND__AD_STEPPING__SHIFT
171081. BIF_CFG_DEV1_EPF1_1_COMMAND__BUS_MASTER_EN_MASK
171082. BIF_CFG_DEV1_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT
171083. BIF_CFG_DEV1_EPF1_1_COMMAND__FAST_B2B_EN_MASK
171084. BIF_CFG_DEV1_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT
171085. BIF_CFG_DEV1_EPF1_1_COMMAND__INT_DIS_MASK
171086. BIF_CFG_DEV1_EPF1_1_COMMAND__INT_DIS__SHIFT
171087. BIF_CFG_DEV1_EPF1_1_COMMAND__IO_ACCESS_EN_MASK
171088. BIF_CFG_DEV1_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT
171089. BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK
171090. BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT
171091. BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
171092. BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
171093. BIF_CFG_DEV1_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK
171094. BIF_CFG_DEV1_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT
171095. BIF_CFG_DEV1_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
171096. BIF_CFG_DEV1_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
171097. BIF_CFG_DEV1_EPF1_1_COMMAND__SERR_EN_MASK
171098. BIF_CFG_DEV1_EPF1_1_COMMAND__SERR_EN__SHIFT
171099. BIF_CFG_DEV1_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK
171100. BIF_CFG_DEV1_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
171101. BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESLD_MASK
171102. BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESLD__SHIFT
171103. BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESL_MASK
171104. BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESL__SHIFT
171105. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
171106. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
171107. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
171108. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
171109. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
171110. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
171111. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
171112. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
171113. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
171114. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
171115. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
171116. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
171117. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
171118. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
171119. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
171120. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
171121. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
171122. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
171123. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
171124. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
171125. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
171126. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
171127. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
171128. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
171129. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
171130. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
171131. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
171132. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
171133. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
171134. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
171135. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
171136. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
171137. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK
171138. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
171139. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK
171140. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
171141. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
171142. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
171143. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
171144. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
171145. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
171146. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
171147. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK
171148. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
171149. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
171150. BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
171151. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
171152. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
171153. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
171154. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
171155. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
171156. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
171157. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
171158. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
171159. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
171160. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
171161. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
171162. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
171163. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
171164. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
171165. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
171166. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
171167. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK
171168. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT
171169. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK
171170. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT
171171. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
171172. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
171173. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK
171174. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
171175. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
171176. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
171177. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
171178. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
171179. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK
171180. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
171181. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
171182. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
171183. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
171184. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
171185. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
171186. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
171187. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
171188. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
171189. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
171190. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
171191. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
171192. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
171193. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK
171194. BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
171195. BIF_CFG_DEV1_EPF1_1_DEVICE_ID__DEVICE_ID_MASK
171196. BIF_CFG_DEV1_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT
171197. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2__RESERVED_MASK
171198. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT
171199. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK
171200. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT
171201. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK
171202. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT
171203. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK
171204. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT
171205. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
171206. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
171207. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
171208. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
171209. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK
171210. BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT
171211. BIF_CFG_DEV1_EPF1_1_FLADJ__FLADJ_MASK
171212. BIF_CFG_DEV1_EPF1_1_FLADJ__FLADJ__SHIFT
171213. BIF_CFG_DEV1_EPF1_1_HEADER__DEVICE_TYPE_MASK
171214. BIF_CFG_DEV1_EPF1_1_HEADER__DEVICE_TYPE__SHIFT
171215. BIF_CFG_DEV1_EPF1_1_HEADER__HEADER_TYPE_MASK
171216. BIF_CFG_DEV1_EPF1_1_HEADER__HEADER_TYPE__SHIFT
171217. BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
171218. BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
171219. BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
171220. BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
171221. BIF_CFG_DEV1_EPF1_1_LATENCY__LATENCY_TIMER_MASK
171222. BIF_CFG_DEV1_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT
171223. BIF_CFG_DEV1_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
171224. BIF_CFG_DEV1_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
171225. BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RESERVED_MASK
171226. BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RESERVED__SHIFT
171227. BIF_CFG_DEV1_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
171228. BIF_CFG_DEV1_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
171229. BIF_CFG_DEV1_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
171230. BIF_CFG_DEV1_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
171231. BIF_CFG_DEV1_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
171232. BIF_CFG_DEV1_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
171233. BIF_CFG_DEV1_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
171234. BIF_CFG_DEV1_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
171235. BIF_CFG_DEV1_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
171236. BIF_CFG_DEV1_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
171237. BIF_CFG_DEV1_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK
171238. BIF_CFG_DEV1_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
171239. BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
171240. BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
171241. BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_SPEED_MASK
171242. BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT
171243. BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_WIDTH_MASK
171244. BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT
171245. BIF_CFG_DEV1_EPF1_1_LINK_CAP__PM_SUPPORT_MASK
171246. BIF_CFG_DEV1_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT
171247. BIF_CFG_DEV1_EPF1_1_LINK_CAP__PORT_NUMBER_MASK
171248. BIF_CFG_DEV1_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT
171249. BIF_CFG_DEV1_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
171250. BIF_CFG_DEV1_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
171251. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
171252. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
171253. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
171254. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
171255. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
171256. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
171257. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
171258. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
171259. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
171260. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
171261. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
171262. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
171263. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
171264. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
171265. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK
171266. BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
171267. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
171268. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
171269. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
171270. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
171271. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK
171272. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
171273. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
171274. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
171275. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
171276. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
171277. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
171278. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
171279. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_DIS_MASK
171280. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT
171281. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__PM_CONTROL_MASK
171282. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT
171283. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
171284. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
171285. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK
171286. BIF_CFG_DEV1_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT
171287. BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
171288. BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
171289. BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
171290. BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
171291. BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
171292. BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
171293. BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
171294. BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
171295. BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
171296. BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
171297. BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
171298. BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
171299. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
171300. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
171301. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK
171302. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT
171303. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
171304. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
171305. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
171306. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
171307. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK
171308. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT
171309. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
171310. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
171311. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
171312. BIF_CFG_DEV1_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
171313. BIF_CFG_DEV1_EPF1_1_MAX_LATENCY__MAX_LAT_MASK
171314. BIF_CFG_DEV1_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT
171315. BIF_CFG_DEV1_EPF1_1_MIN_GRANT__MIN_GNT_MASK
171316. BIF_CFG_DEV1_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT
171317. BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK
171318. BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT
171319. BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK
171320. BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
171321. BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK
171322. BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
171323. BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
171324. BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
171325. BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
171326. BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
171327. BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK
171328. BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
171329. BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
171330. BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
171331. BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
171332. BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
171333. BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
171334. BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
171335. BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK
171336. BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT
171337. BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK
171338. BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
171339. BIF_CFG_DEV1_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK
171340. BIF_CFG_DEV1_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT
171341. BIF_CFG_DEV1_EPF1_1_MSI_MASK__MSI_MASK_MASK
171342. BIF_CFG_DEV1_EPF1_1_MSI_MASK__MSI_MASK__SHIFT
171343. BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
171344. BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
171345. BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
171346. BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
171347. BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK
171348. BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
171349. BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK
171350. BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT
171351. BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
171352. BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
171353. BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
171354. BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
171355. BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
171356. BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
171357. BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
171358. BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
171359. BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK
171360. BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT
171361. BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK
171362. BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
171363. BIF_CFG_DEV1_EPF1_1_MSI_PENDING__MSI_PENDING_MASK
171364. BIF_CFG_DEV1_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT
171365. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
171366. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
171367. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
171368. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
171369. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
171370. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
171371. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
171372. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
171373. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
171374. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
171375. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
171376. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
171377. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
171378. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
171379. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
171380. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
171381. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
171382. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
171383. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
171384. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
171385. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
171386. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
171387. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
171388. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
171389. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
171390. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
171391. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
171392. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
171393. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
171394. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
171395. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
171396. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
171397. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
171398. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
171399. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
171400. BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
171401. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
171402. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
171403. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
171404. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
171405. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
171406. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
171407. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
171408. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
171409. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
171410. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
171411. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
171412. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
171413. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
171414. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
171415. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
171416. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
171417. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
171418. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
171419. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
171420. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
171421. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
171422. BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
171423. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
171424. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
171425. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
171426. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
171427. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
171428. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
171429. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
171430. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
171431. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
171432. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
171433. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
171434. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
171435. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
171436. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
171437. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
171438. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
171439. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
171440. BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
171441. BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
171442. BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
171443. BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK
171444. BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
171445. BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK
171446. BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
171447. BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
171448. BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
171449. BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
171450. BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
171451. BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK
171452. BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
171453. BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK
171454. BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
171455. BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
171456. BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
171457. BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
171458. BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
171459. BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK
171460. BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
171461. BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK
171462. BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
171463. BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
171464. BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
171465. BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
171466. BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
171467. BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK
171468. BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
171469. BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK
171470. BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
171471. BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
171472. BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
171473. BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
171474. BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
171475. BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK
171476. BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
171477. BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK
171478. BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
171479. BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
171480. BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
171481. BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
171482. BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
171483. BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK
171484. BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
171485. BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK
171486. BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
171487. BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
171488. BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
171489. BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
171490. BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
171491. BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
171492. BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
171493. BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
171494. BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
171495. BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK
171496. BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT
171497. BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK
171498. BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
171499. BIF_CFG_DEV1_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK
171500. BIF_CFG_DEV1_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT
171501. BIF_CFG_DEV1_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
171502. BIF_CFG_DEV1_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
171503. BIF_CFG_DEV1_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
171504. BIF_CFG_DEV1_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
171505. BIF_CFG_DEV1_EPF1_1_PCIE_CAP__VERSION_MASK
171506. BIF_CFG_DEV1_EPF1_1_PCIE_CAP__VERSION__SHIFT
171507. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
171508. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
171509. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
171510. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
171511. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
171512. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
171513. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
171514. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
171515. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
171516. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
171517. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
171518. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
171519. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
171520. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
171521. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
171522. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
171523. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
171524. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
171525. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
171526. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
171527. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
171528. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
171529. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
171530. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
171531. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
171532. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
171533. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
171534. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
171535. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
171536. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
171537. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
171538. BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
171539. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
171540. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
171541. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
171542. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
171543. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
171544. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
171545. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
171546. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
171547. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
171548. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
171549. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
171550. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
171551. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
171552. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
171553. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
171554. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
171555. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
171556. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
171557. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
171558. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
171559. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
171560. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
171561. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
171562. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
171563. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
171564. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
171565. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
171566. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
171567. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
171568. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
171569. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
171570. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
171571. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
171572. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
171573. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
171574. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
171575. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
171576. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
171577. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
171578. BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
171579. BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK
171580. BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
171581. BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK
171582. BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
171583. BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK
171584. BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
171585. BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK
171586. BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
171587. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
171588. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
171589. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
171590. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
171591. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
171592. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
171593. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
171594. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
171595. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
171596. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
171597. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
171598. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
171599. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
171600. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
171601. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK
171602. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
171603. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
171604. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
171605. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
171606. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
171607. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
171608. BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
171609. BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
171610. BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
171611. BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
171612. BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
171613. BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
171614. BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
171615. BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
171616. BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
171617. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
171618. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
171619. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
171620. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
171621. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
171622. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
171623. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
171624. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
171625. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
171626. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
171627. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
171628. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
171629. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
171630. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
171631. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
171632. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
171633. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
171634. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
171635. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
171636. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
171637. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
171638. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
171639. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
171640. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
171641. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
171642. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
171643. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
171644. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
171645. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
171646. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
171647. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
171648. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
171649. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
171650. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
171651. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
171652. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
171653. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
171654. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
171655. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
171656. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
171657. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
171658. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
171659. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
171660. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
171661. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
171662. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
171663. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
171664. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
171665. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
171666. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
171667. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
171668. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
171669. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
171670. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
171671. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
171672. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
171673. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
171674. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
171675. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
171676. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
171677. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
171678. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
171679. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
171680. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
171681. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
171682. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
171683. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
171684. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
171685. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
171686. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
171687. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
171688. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
171689. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
171690. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
171691. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
171692. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
171693. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
171694. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
171695. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
171696. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
171697. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
171698. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
171699. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
171700. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
171701. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
171702. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
171703. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
171704. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
171705. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
171706. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
171707. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
171708. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
171709. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
171710. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
171711. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
171712. BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
171713. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
171714. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
171715. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
171716. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
171717. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
171718. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
171719. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
171720. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
171721. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
171722. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
171723. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
171724. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
171725. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
171726. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
171727. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
171728. BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
171729. BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK
171730. BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT
171731. BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK
171732. BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
171733. BIF_CFG_DEV1_EPF1_1_PMI_CAP__AUX_CURRENT_MASK
171734. BIF_CFG_DEV1_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT
171735. BIF_CFG_DEV1_EPF1_1_PMI_CAP__D1_SUPPORT_MASK
171736. BIF_CFG_DEV1_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT
171737. BIF_CFG_DEV1_EPF1_1_PMI_CAP__D2_SUPPORT_MASK
171738. BIF_CFG_DEV1_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT
171739. BIF_CFG_DEV1_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
171740. BIF_CFG_DEV1_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
171741. BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_CLOCK_MASK
171742. BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT
171743. BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_SUPPORT_MASK
171744. BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT
171745. BIF_CFG_DEV1_EPF1_1_PMI_CAP__VERSION_MASK
171746. BIF_CFG_DEV1_EPF1_1_PMI_CAP__VERSION__SHIFT
171747. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
171748. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
171749. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
171750. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
171751. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
171752. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
171753. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
171754. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
171755. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
171756. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
171757. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK
171758. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT
171759. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK
171760. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
171761. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK
171762. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
171763. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK
171764. BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
171765. BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK
171766. BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
171767. BIF_CFG_DEV1_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK
171768. BIF_CFG_DEV1_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT
171769. BIF_CFG_DEV1_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK
171770. BIF_CFG_DEV1_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT
171771. BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK
171772. BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
171773. BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__CAP_ID_MASK
171774. BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__CAP_ID__SHIFT
171775. BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__NEXT_PTR_MASK
171776. BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__NEXT_PTR__SHIFT
171777. BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
171778. BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
171779. BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
171780. BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
171781. BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
171782. BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
171783. BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
171784. BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
171785. BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
171786. BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
171787. BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
171788. BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
171789. BIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA__IDP_DATA_MASK
171790. BIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA__IDP_DATA__SHIFT
171791. BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_INDEX_MASK
171792. BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT
171793. BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK
171794. BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
171795. BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK
171796. BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
171797. BIF_CFG_DEV1_EPF1_1_SBRN__SBRN_MASK
171798. BIF_CFG_DEV1_EPF1_1_SBRN__SBRN__SHIFT
171799. BIF_CFG_DEV1_EPF1_1_SLOT_CAP2__RESERVED_MASK
171800. BIF_CFG_DEV1_EPF1_1_SLOT_CAP2__RESERVED__SHIFT
171801. BIF_CFG_DEV1_EPF1_1_SLOT_CNTL2__RESERVED_MASK
171802. BIF_CFG_DEV1_EPF1_1_SLOT_CNTL2__RESERVED__SHIFT
171803. BIF_CFG_DEV1_EPF1_1_SLOT_STATUS2__RESERVED_MASK
171804. BIF_CFG_DEV1_EPF1_1_SLOT_STATUS2__RESERVED__SHIFT
171805. BIF_CFG_DEV1_EPF1_1_STATUS__CAP_LIST_MASK
171806. BIF_CFG_DEV1_EPF1_1_STATUS__CAP_LIST__SHIFT
171807. BIF_CFG_DEV1_EPF1_1_STATUS__DEVSEL_TIMING_MASK
171808. BIF_CFG_DEV1_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT
171809. BIF_CFG_DEV1_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK
171810. BIF_CFG_DEV1_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT
171811. BIF_CFG_DEV1_EPF1_1_STATUS__INT_STATUS_MASK
171812. BIF_CFG_DEV1_EPF1_1_STATUS__INT_STATUS__SHIFT
171813. BIF_CFG_DEV1_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
171814. BIF_CFG_DEV1_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
171815. BIF_CFG_DEV1_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK
171816. BIF_CFG_DEV1_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
171817. BIF_CFG_DEV1_EPF1_1_STATUS__PCI_66_EN_MASK
171818. BIF_CFG_DEV1_EPF1_1_STATUS__PCI_66_EN__SHIFT
171819. BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK
171820. BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
171821. BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK
171822. BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
171823. BIF_CFG_DEV1_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
171824. BIF_CFG_DEV1_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
171825. BIF_CFG_DEV1_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK
171826. BIF_CFG_DEV1_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
171827. BIF_CFG_DEV1_EPF1_1_SUB_CLASS__SUB_CLASS_MASK
171828. BIF_CFG_DEV1_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT
171829. BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK
171830. BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT
171831. BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK
171832. BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT
171833. BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK
171834. BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
171835. BIF_CFG_DEV1_EPF1_1_VENDOR_ID__VENDOR_ID_MASK
171836. BIF_CFG_DEV1_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT
171837. BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
171838. BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
171839. BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
171840. BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
171841. BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID_MASK
171842. BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
171843. BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
171844. BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
171845. BIF_CFG_DEV1_EPF1_2_BASE_ADDR_1__BASE_ADDR_MASK
171846. BIF_CFG_DEV1_EPF1_2_BASE_ADDR_1__BASE_ADDR__SHIFT
171847. BIF_CFG_DEV1_EPF1_2_BASE_ADDR_2__BASE_ADDR_MASK
171848. BIF_CFG_DEV1_EPF1_2_BASE_ADDR_2__BASE_ADDR__SHIFT
171849. BIF_CFG_DEV1_EPF1_2_BASE_ADDR_3__BASE_ADDR_MASK
171850. BIF_CFG_DEV1_EPF1_2_BASE_ADDR_3__BASE_ADDR__SHIFT
171851. BIF_CFG_DEV1_EPF1_2_BASE_ADDR_4__BASE_ADDR_MASK
171852. BIF_CFG_DEV1_EPF1_2_BASE_ADDR_4__BASE_ADDR__SHIFT
171853. BIF_CFG_DEV1_EPF1_2_BASE_ADDR_5__BASE_ADDR_MASK
171854. BIF_CFG_DEV1_EPF1_2_BASE_ADDR_5__BASE_ADDR__SHIFT
171855. BIF_CFG_DEV1_EPF1_2_BASE_ADDR_6__BASE_ADDR_MASK
171856. BIF_CFG_DEV1_EPF1_2_BASE_ADDR_6__BASE_ADDR__SHIFT
171857. BIF_CFG_DEV1_EPF1_2_BASE_CLASS__BASE_CLASS_MASK
171858. BIF_CFG_DEV1_EPF1_2_BASE_CLASS__BASE_CLASS__SHIFT
171859. BIF_CFG_DEV1_EPF1_2_BIST__BIST_CAP_MASK
171860. BIF_CFG_DEV1_EPF1_2_BIST__BIST_CAP__SHIFT
171861. BIF_CFG_DEV1_EPF1_2_BIST__BIST_COMP_MASK
171862. BIF_CFG_DEV1_EPF1_2_BIST__BIST_COMP__SHIFT
171863. BIF_CFG_DEV1_EPF1_2_BIST__BIST_STRT_MASK
171864. BIF_CFG_DEV1_EPF1_2_BIST__BIST_STRT__SHIFT
171865. BIF_CFG_DEV1_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
171866. BIF_CFG_DEV1_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
171867. BIF_CFG_DEV1_EPF1_2_CAP_PTR__CAP_PTR_MASK
171868. BIF_CFG_DEV1_EPF1_2_CAP_PTR__CAP_PTR__SHIFT
171869. BIF_CFG_DEV1_EPF1_2_COMMAND__AD_STEPPING_MASK
171870. BIF_CFG_DEV1_EPF1_2_COMMAND__AD_STEPPING__SHIFT
171871. BIF_CFG_DEV1_EPF1_2_COMMAND__BUS_MASTER_EN_MASK
171872. BIF_CFG_DEV1_EPF1_2_COMMAND__BUS_MASTER_EN__SHIFT
171873. BIF_CFG_DEV1_EPF1_2_COMMAND__FAST_B2B_EN_MASK
171874. BIF_CFG_DEV1_EPF1_2_COMMAND__FAST_B2B_EN__SHIFT
171875. BIF_CFG_DEV1_EPF1_2_COMMAND__INT_DIS_MASK
171876. BIF_CFG_DEV1_EPF1_2_COMMAND__INT_DIS__SHIFT
171877. BIF_CFG_DEV1_EPF1_2_COMMAND__IO_ACCESS_EN_MASK
171878. BIF_CFG_DEV1_EPF1_2_COMMAND__IO_ACCESS_EN__SHIFT
171879. BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_ACCESS_EN_MASK
171880. BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_ACCESS_EN__SHIFT
171881. BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
171882. BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
171883. BIF_CFG_DEV1_EPF1_2_COMMAND__PAL_SNOOP_EN_MASK
171884. BIF_CFG_DEV1_EPF1_2_COMMAND__PAL_SNOOP_EN__SHIFT
171885. BIF_CFG_DEV1_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
171886. BIF_CFG_DEV1_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
171887. BIF_CFG_DEV1_EPF1_2_COMMAND__SERR_EN_MASK
171888. BIF_CFG_DEV1_EPF1_2_COMMAND__SERR_EN__SHIFT
171889. BIF_CFG_DEV1_EPF1_2_COMMAND__SPECIAL_CYCLE_EN_MASK
171890. BIF_CFG_DEV1_EPF1_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
171891. BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESLD_MASK
171892. BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESLD__SHIFT
171893. BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESL_MASK
171894. BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESL__SHIFT
171895. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
171896. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
171897. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
171898. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
171899. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
171900. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
171901. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
171902. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
171903. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
171904. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
171905. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
171906. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
171907. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
171908. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
171909. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
171910. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
171911. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
171912. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
171913. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
171914. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
171915. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
171916. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
171917. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
171918. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
171919. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
171920. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
171921. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
171922. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
171923. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
171924. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
171925. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
171926. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
171927. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__EXTENDED_TAG_MASK
171928. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
171929. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__FLR_CAPABLE_MASK
171930. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
171931. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
171932. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
171933. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
171934. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
171935. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
171936. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
171937. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__PHANTOM_FUNC_MASK
171938. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
171939. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
171940. BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
171941. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
171942. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
171943. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
171944. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
171945. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
171946. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
171947. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
171948. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
171949. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
171950. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
171951. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
171952. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
171953. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
171954. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
171955. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
171956. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
171957. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__LTR_EN_MASK
171958. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__LTR_EN__SHIFT
171959. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__OBFF_EN_MASK
171960. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__OBFF_EN__SHIFT
171961. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
171962. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
171963. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__CORR_ERR_EN_MASK
171964. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
171965. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
171966. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
171967. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
171968. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
171969. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__INITIATE_FLR_MASK
171970. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__INITIATE_FLR__SHIFT
171971. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
171972. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
171973. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
171974. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
171975. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
171976. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
171977. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
171978. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
171979. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
171980. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
171981. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
171982. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
171983. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__USR_REPORT_EN_MASK
171984. BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
171985. BIF_CFG_DEV1_EPF1_2_DEVICE_ID__DEVICE_ID_MASK
171986. BIF_CFG_DEV1_EPF1_2_DEVICE_ID__DEVICE_ID__SHIFT
171987. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS2__RESERVED_MASK
171988. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS2__RESERVED__SHIFT
171989. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__AUX_PWR_MASK
171990. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__AUX_PWR__SHIFT
171991. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__CORR_ERR_MASK
171992. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__CORR_ERR__SHIFT
171993. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__FATAL_ERR_MASK
171994. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__FATAL_ERR__SHIFT
171995. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
171996. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
171997. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
171998. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
171999. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__USR_DETECTED_MASK
172000. BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__USR_DETECTED__SHIFT
172001. BIF_CFG_DEV1_EPF1_2_FLADJ__FLADJ_MASK
172002. BIF_CFG_DEV1_EPF1_2_FLADJ__FLADJ__SHIFT
172003. BIF_CFG_DEV1_EPF1_2_HEADER__DEVICE_TYPE_MASK
172004. BIF_CFG_DEV1_EPF1_2_HEADER__DEVICE_TYPE__SHIFT
172005. BIF_CFG_DEV1_EPF1_2_HEADER__HEADER_TYPE_MASK
172006. BIF_CFG_DEV1_EPF1_2_HEADER__HEADER_TYPE__SHIFT
172007. BIF_CFG_DEV1_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
172008. BIF_CFG_DEV1_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
172009. BIF_CFG_DEV1_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
172010. BIF_CFG_DEV1_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
172011. BIF_CFG_DEV1_EPF1_2_LATENCY__LATENCY_TIMER_MASK
172012. BIF_CFG_DEV1_EPF1_2_LATENCY__LATENCY_TIMER__SHIFT
172013. BIF_CFG_DEV1_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
172014. BIF_CFG_DEV1_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
172015. BIF_CFG_DEV1_EPF1_2_LINK_CAP2__RESERVED_MASK
172016. BIF_CFG_DEV1_EPF1_2_LINK_CAP2__RESERVED__SHIFT
172017. BIF_CFG_DEV1_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
172018. BIF_CFG_DEV1_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
172019. BIF_CFG_DEV1_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
172020. BIF_CFG_DEV1_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
172021. BIF_CFG_DEV1_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
172022. BIF_CFG_DEV1_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
172023. BIF_CFG_DEV1_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
172024. BIF_CFG_DEV1_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
172025. BIF_CFG_DEV1_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
172026. BIF_CFG_DEV1_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
172027. BIF_CFG_DEV1_EPF1_2_LINK_CAP__L1_EXIT_LATENCY_MASK
172028. BIF_CFG_DEV1_EPF1_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
172029. BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
172030. BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
172031. BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_SPEED_MASK
172032. BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_SPEED__SHIFT
172033. BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_WIDTH_MASK
172034. BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_WIDTH__SHIFT
172035. BIF_CFG_DEV1_EPF1_2_LINK_CAP__PM_SUPPORT_MASK
172036. BIF_CFG_DEV1_EPF1_2_LINK_CAP__PM_SUPPORT__SHIFT
172037. BIF_CFG_DEV1_EPF1_2_LINK_CAP__PORT_NUMBER_MASK
172038. BIF_CFG_DEV1_EPF1_2_LINK_CAP__PORT_NUMBER__SHIFT
172039. BIF_CFG_DEV1_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
172040. BIF_CFG_DEV1_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
172041. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
172042. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
172043. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
172044. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
172045. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
172046. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
172047. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
172048. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
172049. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
172050. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
172051. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
172052. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
172053. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
172054. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
172055. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__XMIT_MARGIN_MASK
172056. BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
172057. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
172058. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
172059. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
172060. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
172061. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__EXTENDED_SYNC_MASK
172062. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
172063. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
172064. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
172065. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
172066. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
172067. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
172068. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
172069. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_DIS_MASK
172070. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_DIS__SHIFT
172071. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__PM_CONTROL_MASK
172072. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__PM_CONTROL__SHIFT
172073. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
172074. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
172075. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__RETRAIN_LINK_MASK
172076. BIF_CFG_DEV1_EPF1_2_LINK_CNTL__RETRAIN_LINK__SHIFT
172077. BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
172078. BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
172079. BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
172080. BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
172081. BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
172082. BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
172083. BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
172084. BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
172085. BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
172086. BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
172087. BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
172088. BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
172089. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
172090. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
172091. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__DL_ACTIVE_MASK
172092. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__DL_ACTIVE__SHIFT
172093. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
172094. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
172095. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
172096. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
172097. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_TRAINING_MASK
172098. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_TRAINING__SHIFT
172099. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
172100. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
172101. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
172102. BIF_CFG_DEV1_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
172103. BIF_CFG_DEV1_EPF1_2_MAX_LATENCY__MAX_LAT_MASK
172104. BIF_CFG_DEV1_EPF1_2_MAX_LATENCY__MAX_LAT__SHIFT
172105. BIF_CFG_DEV1_EPF1_2_MIN_GRANT__MIN_GNT_MASK
172106. BIF_CFG_DEV1_EPF1_2_MIN_GRANT__MIN_GNT__SHIFT
172107. BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__CAP_ID_MASK
172108. BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__CAP_ID__SHIFT
172109. BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__NEXT_PTR_MASK
172110. BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT
172111. BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_EN_MASK
172112. BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT
172113. BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
172114. BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
172115. BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
172116. BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
172117. BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_BIR_MASK
172118. BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT
172119. BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK
172120. BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
172121. BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK
172122. BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
172123. BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
172124. BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
172125. BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__CAP_ID_MASK
172126. BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__CAP_ID__SHIFT
172127. BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__NEXT_PTR_MASK
172128. BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
172129. BIF_CFG_DEV1_EPF1_2_MSI_MASK_64__MSI_MASK_64_MASK
172130. BIF_CFG_DEV1_EPF1_2_MSI_MASK_64__MSI_MASK_64__SHIFT
172131. BIF_CFG_DEV1_EPF1_2_MSI_MASK__MSI_MASK_MASK
172132. BIF_CFG_DEV1_EPF1_2_MSI_MASK__MSI_MASK__SHIFT
172133. BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
172134. BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
172135. BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
172136. BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
172137. BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_64BIT_MASK
172138. BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
172139. BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_EN_MASK
172140. BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_EN__SHIFT
172141. BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
172142. BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
172143. BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
172144. BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
172145. BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
172146. BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
172147. BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
172148. BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
172149. BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA__MSI_DATA_MASK
172150. BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA__MSI_DATA__SHIFT
172151. BIF_CFG_DEV1_EPF1_2_MSI_PENDING_64__MSI_PENDING_64_MASK
172152. BIF_CFG_DEV1_EPF1_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT
172153. BIF_CFG_DEV1_EPF1_2_MSI_PENDING__MSI_PENDING_MASK
172154. BIF_CFG_DEV1_EPF1_2_MSI_PENDING__MSI_PENDING__SHIFT
172155. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
172156. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
172157. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
172158. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
172159. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
172160. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
172161. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
172162. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
172163. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
172164. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
172165. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
172166. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
172167. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
172168. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
172169. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
172170. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
172171. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
172172. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
172173. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
172174. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
172175. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
172176. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
172177. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
172178. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
172179. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
172180. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
172181. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
172182. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
172183. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
172184. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
172185. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
172186. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
172187. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
172188. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
172189. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
172190. BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
172191. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
172192. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
172193. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
172194. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
172195. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
172196. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
172197. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
172198. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
172199. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
172200. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
172201. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
172202. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
172203. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
172204. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
172205. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
172206. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
172207. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
172208. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
172209. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
172210. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
172211. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
172212. BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
172213. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
172214. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
172215. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
172216. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
172217. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
172218. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
172219. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
172220. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
172221. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
172222. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
172223. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
172224. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
172225. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
172226. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
172227. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
172228. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
172229. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
172230. BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
172231. BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
172232. BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
172233. BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK
172234. BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
172235. BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK
172236. BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
172237. BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
172238. BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
172239. BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
172240. BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
172241. BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK
172242. BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
172243. BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK
172244. BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
172245. BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
172246. BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
172247. BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
172248. BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
172249. BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK
172250. BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
172251. BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK
172252. BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
172253. BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
172254. BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
172255. BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
172256. BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
172257. BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK
172258. BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
172259. BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK
172260. BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
172261. BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
172262. BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
172263. BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
172264. BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
172265. BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK
172266. BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
172267. BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK
172268. BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
172269. BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
172270. BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
172271. BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
172272. BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
172273. BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK
172274. BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
172275. BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK
172276. BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
172277. BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
172278. BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
172279. BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
172280. BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
172281. BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
172282. BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
172283. BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
172284. BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
172285. BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__CAP_ID_MASK
172286. BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__CAP_ID__SHIFT
172287. BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__NEXT_PTR_MASK
172288. BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
172289. BIF_CFG_DEV1_EPF1_2_PCIE_CAP__DEVICE_TYPE_MASK
172290. BIF_CFG_DEV1_EPF1_2_PCIE_CAP__DEVICE_TYPE__SHIFT
172291. BIF_CFG_DEV1_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
172292. BIF_CFG_DEV1_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
172293. BIF_CFG_DEV1_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
172294. BIF_CFG_DEV1_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
172295. BIF_CFG_DEV1_EPF1_2_PCIE_CAP__VERSION_MASK
172296. BIF_CFG_DEV1_EPF1_2_PCIE_CAP__VERSION__SHIFT
172297. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
172298. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
172299. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
172300. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
172301. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
172302. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
172303. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
172304. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
172305. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
172306. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
172307. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
172308. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
172309. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
172310. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
172311. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
172312. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
172313. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
172314. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
172315. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
172316. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
172317. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
172318. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
172319. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
172320. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
172321. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
172322. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
172323. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
172324. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
172325. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
172326. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
172327. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
172328. BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
172329. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
172330. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
172331. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
172332. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
172333. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
172334. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
172335. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
172336. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
172337. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
172338. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
172339. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
172340. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
172341. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
172342. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
172343. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
172344. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
172345. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
172346. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
172347. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
172348. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
172349. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
172350. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
172351. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
172352. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
172353. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
172354. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
172355. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
172356. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
172357. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
172358. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
172359. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
172360. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
172361. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
172362. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
172363. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
172364. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
172365. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
172366. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
172367. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
172368. BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
172369. BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG0__TLP_HDR_MASK
172370. BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
172371. BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG1__TLP_HDR_MASK
172372. BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
172373. BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG2__TLP_HDR_MASK
172374. BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
172375. BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG3__TLP_HDR_MASK
172376. BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
172377. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
172378. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
172379. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
172380. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
172381. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
172382. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
172383. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
172384. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
172385. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
172386. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
172387. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
172388. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
172389. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
172390. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
172391. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK
172392. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
172393. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
172394. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
172395. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
172396. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
172397. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
172398. BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
172399. BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
172400. BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
172401. BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
172402. BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
172403. BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
172404. BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
172405. BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
172406. BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
172407. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
172408. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
172409. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
172410. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
172411. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
172412. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
172413. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
172414. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
172415. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
172416. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
172417. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
172418. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
172419. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
172420. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
172421. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
172422. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
172423. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
172424. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
172425. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
172426. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
172427. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
172428. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
172429. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
172430. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
172431. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
172432. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
172433. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
172434. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
172435. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
172436. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
172437. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
172438. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
172439. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
172440. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
172441. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
172442. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
172443. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
172444. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
172445. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
172446. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
172447. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
172448. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
172449. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
172450. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
172451. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
172452. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
172453. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
172454. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
172455. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
172456. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
172457. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
172458. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
172459. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
172460. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
172461. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
172462. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
172463. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
172464. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
172465. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
172466. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
172467. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
172468. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
172469. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
172470. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
172471. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
172472. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
172473. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
172474. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
172475. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
172476. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
172477. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
172478. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
172479. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
172480. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
172481. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
172482. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
172483. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
172484. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
172485. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
172486. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
172487. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
172488. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
172489. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
172490. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
172491. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
172492. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
172493. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
172494. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
172495. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
172496. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
172497. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
172498. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
172499. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
172500. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
172501. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
172502. BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
172503. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
172504. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
172505. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
172506. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
172507. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
172508. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
172509. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
172510. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
172511. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
172512. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
172513. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
172514. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
172515. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
172516. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
172517. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
172518. BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
172519. BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__CAP_ID_MASK
172520. BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__CAP_ID__SHIFT
172521. BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__NEXT_PTR_MASK
172522. BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
172523. BIF_CFG_DEV1_EPF1_2_PMI_CAP__AUX_CURRENT_MASK
172524. BIF_CFG_DEV1_EPF1_2_PMI_CAP__AUX_CURRENT__SHIFT
172525. BIF_CFG_DEV1_EPF1_2_PMI_CAP__D1_SUPPORT_MASK
172526. BIF_CFG_DEV1_EPF1_2_PMI_CAP__D1_SUPPORT__SHIFT
172527. BIF_CFG_DEV1_EPF1_2_PMI_CAP__D2_SUPPORT_MASK
172528. BIF_CFG_DEV1_EPF1_2_PMI_CAP__D2_SUPPORT__SHIFT
172529. BIF_CFG_DEV1_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
172530. BIF_CFG_DEV1_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
172531. BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_CLOCK_MASK
172532. BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_CLOCK__SHIFT
172533. BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_SUPPORT_MASK
172534. BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_SUPPORT__SHIFT
172535. BIF_CFG_DEV1_EPF1_2_PMI_CAP__VERSION_MASK
172536. BIF_CFG_DEV1_EPF1_2_PMI_CAP__VERSION__SHIFT
172537. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
172538. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
172539. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
172540. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
172541. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
172542. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
172543. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
172544. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
172545. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
172546. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
172547. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_EN_MASK
172548. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_EN__SHIFT
172549. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_STATUS_MASK
172550. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
172551. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PMI_DATA_MASK
172552. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
172553. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__POWER_STATE_MASK
172554. BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
172555. BIF_CFG_DEV1_EPF1_2_PROG_INTERFACE__PROG_INTERFACE_MASK
172556. BIF_CFG_DEV1_EPF1_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
172557. BIF_CFG_DEV1_EPF1_2_REVISION_ID__MAJOR_REV_ID_MASK
172558. BIF_CFG_DEV1_EPF1_2_REVISION_ID__MAJOR_REV_ID__SHIFT
172559. BIF_CFG_DEV1_EPF1_2_REVISION_ID__MINOR_REV_ID_MASK
172560. BIF_CFG_DEV1_EPF1_2_REVISION_ID__MINOR_REV_ID__SHIFT
172561. BIF_CFG_DEV1_EPF1_2_ROM_BASE_ADDR__BASE_ADDR_MASK
172562. BIF_CFG_DEV1_EPF1_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT
172563. BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__CAP_ID_MASK
172564. BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__CAP_ID__SHIFT
172565. BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__NEXT_PTR_MASK
172566. BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__NEXT_PTR__SHIFT
172567. BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
172568. BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
172569. BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
172570. BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
172571. BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
172572. BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
172573. BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
172574. BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
172575. BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
172576. BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
172577. BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
172578. BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
172579. BIF_CFG_DEV1_EPF1_2_SATA_IDP_DATA__IDP_DATA_MASK
172580. BIF_CFG_DEV1_EPF1_2_SATA_IDP_DATA__IDP_DATA__SHIFT
172581. BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_INDEX_MASK
172582. BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT
172583. BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK
172584. BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
172585. BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK
172586. BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
172587. BIF_CFG_DEV1_EPF1_2_SBRN__SBRN_MASK
172588. BIF_CFG_DEV1_EPF1_2_SBRN__SBRN__SHIFT
172589. BIF_CFG_DEV1_EPF1_2_SLOT_CAP2__RESERVED_MASK
172590. BIF_CFG_DEV1_EPF1_2_SLOT_CAP2__RESERVED__SHIFT
172591. BIF_CFG_DEV1_EPF1_2_SLOT_CNTL2__RESERVED_MASK
172592. BIF_CFG_DEV1_EPF1_2_SLOT_CNTL2__RESERVED__SHIFT
172593. BIF_CFG_DEV1_EPF1_2_SLOT_STATUS2__RESERVED_MASK
172594. BIF_CFG_DEV1_EPF1_2_SLOT_STATUS2__RESERVED__SHIFT
172595. BIF_CFG_DEV1_EPF1_2_STATUS__CAP_LIST_MASK
172596. BIF_CFG_DEV1_EPF1_2_STATUS__CAP_LIST__SHIFT
172597. BIF_CFG_DEV1_EPF1_2_STATUS__DEVSEL_TIMING_MASK
172598. BIF_CFG_DEV1_EPF1_2_STATUS__DEVSEL_TIMING__SHIFT
172599. BIF_CFG_DEV1_EPF1_2_STATUS__FAST_BACK_CAPABLE_MASK
172600. BIF_CFG_DEV1_EPF1_2_STATUS__FAST_BACK_CAPABLE__SHIFT
172601. BIF_CFG_DEV1_EPF1_2_STATUS__INT_STATUS_MASK
172602. BIF_CFG_DEV1_EPF1_2_STATUS__INT_STATUS__SHIFT
172603. BIF_CFG_DEV1_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
172604. BIF_CFG_DEV1_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
172605. BIF_CFG_DEV1_EPF1_2_STATUS__PARITY_ERROR_DETECTED_MASK
172606. BIF_CFG_DEV1_EPF1_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
172607. BIF_CFG_DEV1_EPF1_2_STATUS__PCI_66_EN_MASK
172608. BIF_CFG_DEV1_EPF1_2_STATUS__PCI_66_EN__SHIFT
172609. BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_MASTER_ABORT_MASK
172610. BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
172611. BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_TARGET_ABORT_MASK
172612. BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
172613. BIF_CFG_DEV1_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
172614. BIF_CFG_DEV1_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
172615. BIF_CFG_DEV1_EPF1_2_STATUS__SIGNAL_TARGET_ABORT_MASK
172616. BIF_CFG_DEV1_EPF1_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
172617. BIF_CFG_DEV1_EPF1_2_SUB_CLASS__SUB_CLASS_MASK
172618. BIF_CFG_DEV1_EPF1_2_SUB_CLASS__SUB_CLASS__SHIFT
172619. BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__CAP_ID_MASK
172620. BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__CAP_ID__SHIFT
172621. BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__LENGTH_MASK
172622. BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__LENGTH__SHIFT
172623. BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR_MASK
172624. BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
172625. BIF_CFG_DEV1_EPF1_2_VENDOR_ID__VENDOR_ID_MASK
172626. BIF_CFG_DEV1_EPF1_2_VENDOR_ID__VENDOR_ID__SHIFT
172627. BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
172628. BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
172629. BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
172630. BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
172631. BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK
172632. BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
172633. BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
172634. BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
172635. BIF_CFG_DEV1_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK
172636. BIF_CFG_DEV1_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT
172637. BIF_CFG_DEV1_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK
172638. BIF_CFG_DEV1_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT
172639. BIF_CFG_DEV1_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK
172640. BIF_CFG_DEV1_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT
172641. BIF_CFG_DEV1_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK
172642. BIF_CFG_DEV1_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT
172643. BIF_CFG_DEV1_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK
172644. BIF_CFG_DEV1_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT
172645. BIF_CFG_DEV1_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK
172646. BIF_CFG_DEV1_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT
172647. BIF_CFG_DEV1_EPF2_0_BASE_CLASS__BASE_CLASS_MASK
172648. BIF_CFG_DEV1_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT
172649. BIF_CFG_DEV1_EPF2_0_BIST__BIST_CAP_MASK
172650. BIF_CFG_DEV1_EPF2_0_BIST__BIST_CAP__SHIFT
172651. BIF_CFG_DEV1_EPF2_0_BIST__BIST_COMP_MASK
172652. BIF_CFG_DEV1_EPF2_0_BIST__BIST_COMP__SHIFT
172653. BIF_CFG_DEV1_EPF2_0_BIST__BIST_STRT_MASK
172654. BIF_CFG_DEV1_EPF2_0_BIST__BIST_STRT__SHIFT
172655. BIF_CFG_DEV1_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
172656. BIF_CFG_DEV1_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
172657. BIF_CFG_DEV1_EPF2_0_CAP_PTR__CAP_PTR_MASK
172658. BIF_CFG_DEV1_EPF2_0_CAP_PTR__CAP_PTR__SHIFT
172659. BIF_CFG_DEV1_EPF2_0_COMMAND__AD_STEPPING_MASK
172660. BIF_CFG_DEV1_EPF2_0_COMMAND__AD_STEPPING__SHIFT
172661. BIF_CFG_DEV1_EPF2_0_COMMAND__BUS_MASTER_EN_MASK
172662. BIF_CFG_DEV1_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT
172663. BIF_CFG_DEV1_EPF2_0_COMMAND__FAST_B2B_EN_MASK
172664. BIF_CFG_DEV1_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT
172665. BIF_CFG_DEV1_EPF2_0_COMMAND__INT_DIS_MASK
172666. BIF_CFG_DEV1_EPF2_0_COMMAND__INT_DIS__SHIFT
172667. BIF_CFG_DEV1_EPF2_0_COMMAND__IO_ACCESS_EN_MASK
172668. BIF_CFG_DEV1_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT
172669. BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK
172670. BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT
172671. BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
172672. BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
172673. BIF_CFG_DEV1_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK
172674. BIF_CFG_DEV1_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT
172675. BIF_CFG_DEV1_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
172676. BIF_CFG_DEV1_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
172677. BIF_CFG_DEV1_EPF2_0_COMMAND__SERR_EN_MASK
172678. BIF_CFG_DEV1_EPF2_0_COMMAND__SERR_EN__SHIFT
172679. BIF_CFG_DEV1_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK
172680. BIF_CFG_DEV1_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
172681. BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESLD_MASK
172682. BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT
172683. BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESL_MASK
172684. BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESL__SHIFT
172685. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
172686. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
172687. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
172688. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
172689. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
172690. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
172691. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
172692. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
172693. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
172694. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
172695. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
172696. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
172697. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
172698. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
172699. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
172700. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
172701. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
172702. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
172703. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
172704. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
172705. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
172706. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
172707. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
172708. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
172709. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
172710. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
172711. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
172712. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
172713. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
172714. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
172715. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
172716. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
172717. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK
172718. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
172719. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK
172720. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
172721. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
172722. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
172723. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
172724. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
172725. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
172726. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
172727. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK
172728. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
172729. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
172730. BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
172731. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
172732. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
172733. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
172734. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
172735. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
172736. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
172737. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
172738. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
172739. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
172740. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
172741. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
172742. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
172743. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
172744. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
172745. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
172746. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
172747. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK
172748. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT
172749. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK
172750. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT
172751. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
172752. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
172753. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK
172754. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
172755. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
172756. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
172757. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
172758. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
172759. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK
172760. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT
172761. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
172762. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
172763. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
172764. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
172765. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
172766. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
172767. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
172768. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
172769. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
172770. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
172771. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
172772. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
172773. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK
172774. BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
172775. BIF_CFG_DEV1_EPF2_0_DEVICE_ID__DEVICE_ID_MASK
172776. BIF_CFG_DEV1_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT
172777. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2__RESERVED_MASK
172778. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT
172779. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK
172780. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT
172781. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK
172782. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT
172783. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK
172784. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT
172785. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
172786. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
172787. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
172788. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
172789. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK
172790. BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT
172791. BIF_CFG_DEV1_EPF2_0_FLADJ__FLADJ_MASK
172792. BIF_CFG_DEV1_EPF2_0_FLADJ__FLADJ__SHIFT
172793. BIF_CFG_DEV1_EPF2_0_HEADER__DEVICE_TYPE_MASK
172794. BIF_CFG_DEV1_EPF2_0_HEADER__DEVICE_TYPE__SHIFT
172795. BIF_CFG_DEV1_EPF2_0_HEADER__HEADER_TYPE_MASK
172796. BIF_CFG_DEV1_EPF2_0_HEADER__HEADER_TYPE__SHIFT
172797. BIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
172798. BIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
172799. BIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
172800. BIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
172801. BIF_CFG_DEV1_EPF2_0_LATENCY__LATENCY_TIMER_MASK
172802. BIF_CFG_DEV1_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT
172803. BIF_CFG_DEV1_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
172804. BIF_CFG_DEV1_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
172805. BIF_CFG_DEV1_EPF2_0_LINK_CAP2__RESERVED_MASK
172806. BIF_CFG_DEV1_EPF2_0_LINK_CAP2__RESERVED__SHIFT
172807. BIF_CFG_DEV1_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
172808. BIF_CFG_DEV1_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
172809. BIF_CFG_DEV1_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
172810. BIF_CFG_DEV1_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
172811. BIF_CFG_DEV1_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
172812. BIF_CFG_DEV1_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
172813. BIF_CFG_DEV1_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
172814. BIF_CFG_DEV1_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
172815. BIF_CFG_DEV1_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
172816. BIF_CFG_DEV1_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
172817. BIF_CFG_DEV1_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK
172818. BIF_CFG_DEV1_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
172819. BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
172820. BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
172821. BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_SPEED_MASK
172822. BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT
172823. BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_WIDTH_MASK
172824. BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT
172825. BIF_CFG_DEV1_EPF2_0_LINK_CAP__PM_SUPPORT_MASK
172826. BIF_CFG_DEV1_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT
172827. BIF_CFG_DEV1_EPF2_0_LINK_CAP__PORT_NUMBER_MASK
172828. BIF_CFG_DEV1_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT
172829. BIF_CFG_DEV1_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
172830. BIF_CFG_DEV1_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
172831. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
172832. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
172833. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
172834. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
172835. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
172836. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
172837. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
172838. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
172839. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
172840. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
172841. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
172842. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
172843. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
172844. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
172845. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK
172846. BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
172847. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
172848. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
172849. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
172850. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
172851. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK
172852. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
172853. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
172854. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
172855. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
172856. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
172857. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
172858. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
172859. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_DIS_MASK
172860. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT
172861. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__PM_CONTROL_MASK
172862. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT
172863. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
172864. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
172865. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK
172866. BIF_CFG_DEV1_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT
172867. BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
172868. BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
172869. BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
172870. BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
172871. BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
172872. BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
172873. BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
172874. BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
172875. BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
172876. BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
172877. BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
172878. BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
172879. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
172880. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
172881. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK
172882. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT
172883. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
172884. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
172885. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
172886. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
172887. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK
172888. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT
172889. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
172890. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
172891. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
172892. BIF_CFG_DEV1_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
172893. BIF_CFG_DEV1_EPF2_0_MAX_LATENCY__MAX_LAT_MASK
172894. BIF_CFG_DEV1_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT
172895. BIF_CFG_DEV1_EPF2_0_MIN_GRANT__MIN_GNT_MASK
172896. BIF_CFG_DEV1_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT
172897. BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK
172898. BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT
172899. BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK
172900. BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT
172901. BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK
172902. BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT
172903. BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
172904. BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
172905. BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
172906. BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
172907. BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK
172908. BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT
172909. BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK
172910. BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
172911. BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK
172912. BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
172913. BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
172914. BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
172915. BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK
172916. BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT
172917. BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK
172918. BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
172919. BIF_CFG_DEV1_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK
172920. BIF_CFG_DEV1_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT
172921. BIF_CFG_DEV1_EPF2_0_MSI_MASK__MSI_MASK_MASK
172922. BIF_CFG_DEV1_EPF2_0_MSI_MASK__MSI_MASK__SHIFT
172923. BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
172924. BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
172925. BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
172926. BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
172927. BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK
172928. BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
172929. BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK
172930. BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT
172931. BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
172932. BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
172933. BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
172934. BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
172935. BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
172936. BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
172937. BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
172938. BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
172939. BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK
172940. BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT
172941. BIF_CFG_DEV1_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK
172942. BIF_CFG_DEV1_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT
172943. BIF_CFG_DEV1_EPF2_0_MSI_PENDING__MSI_PENDING_MASK
172944. BIF_CFG_DEV1_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT
172945. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
172946. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
172947. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
172948. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
172949. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
172950. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
172951. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
172952. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
172953. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
172954. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
172955. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
172956. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
172957. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
172958. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
172959. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
172960. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
172961. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
172962. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
172963. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
172964. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
172965. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
172966. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
172967. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
172968. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
172969. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
172970. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
172971. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
172972. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
172973. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
172974. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
172975. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
172976. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
172977. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
172978. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
172979. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
172980. BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
172981. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
172982. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
172983. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
172984. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
172985. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
172986. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
172987. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
172988. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
172989. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
172990. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
172991. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
172992. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
172993. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
172994. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
172995. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
172996. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
172997. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
172998. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
172999. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
173000. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
173001. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
173002. BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
173003. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
173004. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
173005. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
173006. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
173007. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
173008. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
173009. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
173010. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
173011. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
173012. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
173013. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
173014. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
173015. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
173016. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
173017. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
173018. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
173019. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
173020. BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
173021. BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
173022. BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
173023. BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK
173024. BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
173025. BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK
173026. BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
173027. BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
173028. BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
173029. BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
173030. BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
173031. BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK
173032. BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
173033. BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK
173034. BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
173035. BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
173036. BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
173037. BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
173038. BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
173039. BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK
173040. BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
173041. BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK
173042. BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
173043. BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
173044. BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
173045. BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
173046. BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
173047. BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK
173048. BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
173049. BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK
173050. BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
173051. BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
173052. BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
173053. BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
173054. BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
173055. BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK
173056. BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
173057. BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK
173058. BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
173059. BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
173060. BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
173061. BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
173062. BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
173063. BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK
173064. BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
173065. BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK
173066. BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
173067. BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
173068. BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
173069. BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
173070. BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
173071. BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
173072. BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
173073. BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
173074. BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
173075. BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK
173076. BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT
173077. BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK
173078. BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
173079. BIF_CFG_DEV1_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK
173080. BIF_CFG_DEV1_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT
173081. BIF_CFG_DEV1_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
173082. BIF_CFG_DEV1_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
173083. BIF_CFG_DEV1_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
173084. BIF_CFG_DEV1_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
173085. BIF_CFG_DEV1_EPF2_0_PCIE_CAP__VERSION_MASK
173086. BIF_CFG_DEV1_EPF2_0_PCIE_CAP__VERSION__SHIFT
173087. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
173088. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
173089. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
173090. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
173091. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
173092. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
173093. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
173094. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
173095. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
173096. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
173097. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
173098. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
173099. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
173100. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
173101. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
173102. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
173103. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
173104. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
173105. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
173106. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
173107. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
173108. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
173109. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
173110. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
173111. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
173112. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
173113. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
173114. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
173115. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
173116. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
173117. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
173118. BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
173119. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
173120. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
173121. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
173122. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
173123. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
173124. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
173125. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
173126. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
173127. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
173128. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
173129. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
173130. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
173131. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
173132. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
173133. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
173134. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
173135. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
173136. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
173137. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
173138. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
173139. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
173140. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
173141. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
173142. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
173143. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
173144. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
173145. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
173146. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
173147. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
173148. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
173149. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
173150. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
173151. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
173152. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
173153. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
173154. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
173155. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
173156. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
173157. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
173158. BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
173159. BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK
173160. BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
173161. BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK
173162. BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
173163. BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK
173164. BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
173165. BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK
173166. BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
173167. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
173168. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
173169. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
173170. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
173171. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
173172. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
173173. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
173174. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
173175. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
173176. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
173177. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
173178. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
173179. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
173180. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
173181. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK
173182. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
173183. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
173184. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
173185. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
173186. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
173187. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
173188. BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
173189. BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
173190. BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
173191. BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
173192. BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
173193. BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
173194. BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
173195. BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
173196. BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
173197. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
173198. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
173199. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
173200. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
173201. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
173202. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
173203. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
173204. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
173205. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
173206. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
173207. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
173208. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
173209. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
173210. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
173211. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
173212. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
173213. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
173214. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
173215. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
173216. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
173217. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
173218. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
173219. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
173220. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
173221. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
173222. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
173223. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
173224. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
173225. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
173226. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
173227. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
173228. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
173229. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
173230. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
173231. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
173232. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
173233. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
173234. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
173235. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
173236. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
173237. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
173238. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
173239. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
173240. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
173241. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
173242. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
173243. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
173244. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
173245. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
173246. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
173247. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
173248. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
173249. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
173250. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
173251. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
173252. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
173253. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
173254. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
173255. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
173256. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
173257. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
173258. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
173259. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
173260. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
173261. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
173262. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
173263. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
173264. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
173265. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
173266. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
173267. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
173268. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
173269. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
173270. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
173271. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
173272. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
173273. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
173274. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
173275. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
173276. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
173277. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
173278. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
173279. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
173280. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
173281. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
173282. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
173283. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
173284. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
173285. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
173286. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
173287. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
173288. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
173289. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
173290. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
173291. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
173292. BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
173293. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
173294. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
173295. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
173296. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
173297. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
173298. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
173299. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
173300. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
173301. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
173302. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
173303. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
173304. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
173305. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
173306. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
173307. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
173308. BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
173309. BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK
173310. BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT
173311. BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK
173312. BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
173313. BIF_CFG_DEV1_EPF2_0_PMI_CAP__AUX_CURRENT_MASK
173314. BIF_CFG_DEV1_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT
173315. BIF_CFG_DEV1_EPF2_0_PMI_CAP__D1_SUPPORT_MASK
173316. BIF_CFG_DEV1_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT
173317. BIF_CFG_DEV1_EPF2_0_PMI_CAP__D2_SUPPORT_MASK
173318. BIF_CFG_DEV1_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT
173319. BIF_CFG_DEV1_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
173320. BIF_CFG_DEV1_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
173321. BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_CLOCK_MASK
173322. BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT
173323. BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_SUPPORT_MASK
173324. BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT
173325. BIF_CFG_DEV1_EPF2_0_PMI_CAP__VERSION_MASK
173326. BIF_CFG_DEV1_EPF2_0_PMI_CAP__VERSION__SHIFT
173327. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
173328. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
173329. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
173330. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
173331. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
173332. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
173333. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
173334. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
173335. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
173336. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
173337. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK
173338. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT
173339. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK
173340. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
173341. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK
173342. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
173343. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK
173344. BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
173345. BIF_CFG_DEV1_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK
173346. BIF_CFG_DEV1_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
173347. BIF_CFG_DEV1_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK
173348. BIF_CFG_DEV1_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT
173349. BIF_CFG_DEV1_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK
173350. BIF_CFG_DEV1_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT
173351. BIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK
173352. BIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
173353. BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__CAP_ID_MASK
173354. BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT
173355. BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK
173356. BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT
173357. BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
173358. BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
173359. BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
173360. BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
173361. BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
173362. BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
173363. BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
173364. BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
173365. BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
173366. BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
173367. BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
173368. BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
173369. BIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK
173370. BIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT
173371. BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK
173372. BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT
173373. BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK
173374. BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
173375. BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK
173376. BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
173377. BIF_CFG_DEV1_EPF2_0_SBRN__SBRN_MASK
173378. BIF_CFG_DEV1_EPF2_0_SBRN__SBRN__SHIFT
173379. BIF_CFG_DEV1_EPF2_0_SLOT_CAP2__RESERVED_MASK
173380. BIF_CFG_DEV1_EPF2_0_SLOT_CAP2__RESERVED__SHIFT
173381. BIF_CFG_DEV1_EPF2_0_SLOT_CNTL2__RESERVED_MASK
173382. BIF_CFG_DEV1_EPF2_0_SLOT_CNTL2__RESERVED__SHIFT
173383. BIF_CFG_DEV1_EPF2_0_SLOT_STATUS2__RESERVED_MASK
173384. BIF_CFG_DEV1_EPF2_0_SLOT_STATUS2__RESERVED__SHIFT
173385. BIF_CFG_DEV1_EPF2_0_STATUS__CAP_LIST_MASK
173386. BIF_CFG_DEV1_EPF2_0_STATUS__CAP_LIST__SHIFT
173387. BIF_CFG_DEV1_EPF2_0_STATUS__DEVSEL_TIMING_MASK
173388. BIF_CFG_DEV1_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT
173389. BIF_CFG_DEV1_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK
173390. BIF_CFG_DEV1_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT
173391. BIF_CFG_DEV1_EPF2_0_STATUS__INT_STATUS_MASK
173392. BIF_CFG_DEV1_EPF2_0_STATUS__INT_STATUS__SHIFT
173393. BIF_CFG_DEV1_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
173394. BIF_CFG_DEV1_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
173395. BIF_CFG_DEV1_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK
173396. BIF_CFG_DEV1_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
173397. BIF_CFG_DEV1_EPF2_0_STATUS__PCI_66_EN_MASK
173398. BIF_CFG_DEV1_EPF2_0_STATUS__PCI_66_EN__SHIFT
173399. BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK
173400. BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
173401. BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK
173402. BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
173403. BIF_CFG_DEV1_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
173404. BIF_CFG_DEV1_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
173405. BIF_CFG_DEV1_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK
173406. BIF_CFG_DEV1_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
173407. BIF_CFG_DEV1_EPF2_0_SUB_CLASS__SUB_CLASS_MASK
173408. BIF_CFG_DEV1_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT
173409. BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK
173410. BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT
173411. BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK
173412. BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT
173413. BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK
173414. BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
173415. BIF_CFG_DEV1_EPF2_0_VENDOR_ID__VENDOR_ID_MASK
173416. BIF_CFG_DEV1_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT
173417. BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
173418. BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
173419. BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
173420. BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
173421. BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK
173422. BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
173423. BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
173424. BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
173425. BIF_CFG_DEV1_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK
173426. BIF_CFG_DEV1_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT
173427. BIF_CFG_DEV1_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK
173428. BIF_CFG_DEV1_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT
173429. BIF_CFG_DEV1_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK
173430. BIF_CFG_DEV1_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT
173431. BIF_CFG_DEV1_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK
173432. BIF_CFG_DEV1_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT
173433. BIF_CFG_DEV1_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK
173434. BIF_CFG_DEV1_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT
173435. BIF_CFG_DEV1_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK
173436. BIF_CFG_DEV1_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT
173437. BIF_CFG_DEV1_EPF2_1_BASE_CLASS__BASE_CLASS_MASK
173438. BIF_CFG_DEV1_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT
173439. BIF_CFG_DEV1_EPF2_1_BIST__BIST_CAP_MASK
173440. BIF_CFG_DEV1_EPF2_1_BIST__BIST_CAP__SHIFT
173441. BIF_CFG_DEV1_EPF2_1_BIST__BIST_COMP_MASK
173442. BIF_CFG_DEV1_EPF2_1_BIST__BIST_COMP__SHIFT
173443. BIF_CFG_DEV1_EPF2_1_BIST__BIST_STRT_MASK
173444. BIF_CFG_DEV1_EPF2_1_BIST__BIST_STRT__SHIFT
173445. BIF_CFG_DEV1_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
173446. BIF_CFG_DEV1_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
173447. BIF_CFG_DEV1_EPF2_1_CAP_PTR__CAP_PTR_MASK
173448. BIF_CFG_DEV1_EPF2_1_CAP_PTR__CAP_PTR__SHIFT
173449. BIF_CFG_DEV1_EPF2_1_COMMAND__AD_STEPPING_MASK
173450. BIF_CFG_DEV1_EPF2_1_COMMAND__AD_STEPPING__SHIFT
173451. BIF_CFG_DEV1_EPF2_1_COMMAND__BUS_MASTER_EN_MASK
173452. BIF_CFG_DEV1_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT
173453. BIF_CFG_DEV1_EPF2_1_COMMAND__FAST_B2B_EN_MASK
173454. BIF_CFG_DEV1_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT
173455. BIF_CFG_DEV1_EPF2_1_COMMAND__INT_DIS_MASK
173456. BIF_CFG_DEV1_EPF2_1_COMMAND__INT_DIS__SHIFT
173457. BIF_CFG_DEV1_EPF2_1_COMMAND__IO_ACCESS_EN_MASK
173458. BIF_CFG_DEV1_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT
173459. BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK
173460. BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT
173461. BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
173462. BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
173463. BIF_CFG_DEV1_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK
173464. BIF_CFG_DEV1_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT
173465. BIF_CFG_DEV1_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
173466. BIF_CFG_DEV1_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
173467. BIF_CFG_DEV1_EPF2_1_COMMAND__SERR_EN_MASK
173468. BIF_CFG_DEV1_EPF2_1_COMMAND__SERR_EN__SHIFT
173469. BIF_CFG_DEV1_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK
173470. BIF_CFG_DEV1_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
173471. BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESLD_MASK
173472. BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT
173473. BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESL_MASK
173474. BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESL__SHIFT
173475. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
173476. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
173477. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
173478. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
173479. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
173480. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
173481. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
173482. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
173483. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
173484. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
173485. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
173486. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
173487. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
173488. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
173489. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
173490. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
173491. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
173492. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
173493. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
173494. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
173495. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
173496. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
173497. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
173498. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
173499. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
173500. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
173501. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
173502. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
173503. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
173504. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
173505. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
173506. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
173507. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK
173508. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
173509. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK
173510. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
173511. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
173512. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
173513. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
173514. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
173515. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
173516. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
173517. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK
173518. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
173519. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
173520. BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
173521. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
173522. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
173523. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
173524. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
173525. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
173526. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
173527. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
173528. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
173529. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
173530. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
173531. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
173532. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
173533. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
173534. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
173535. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
173536. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
173537. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK
173538. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT
173539. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK
173540. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT
173541. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
173542. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
173543. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK
173544. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
173545. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
173546. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
173547. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
173548. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
173549. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK
173550. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT
173551. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
173552. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
173553. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
173554. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
173555. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
173556. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
173557. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
173558. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
173559. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
173560. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
173561. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
173562. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
173563. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK
173564. BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
173565. BIF_CFG_DEV1_EPF2_1_DEVICE_ID__DEVICE_ID_MASK
173566. BIF_CFG_DEV1_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT
173567. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS2__RESERVED_MASK
173568. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT
173569. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK
173570. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT
173571. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK
173572. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT
173573. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK
173574. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT
173575. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
173576. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
173577. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
173578. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
173579. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK
173580. BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT
173581. BIF_CFG_DEV1_EPF2_1_FLADJ__FLADJ_MASK
173582. BIF_CFG_DEV1_EPF2_1_FLADJ__FLADJ__SHIFT
173583. BIF_CFG_DEV1_EPF2_1_HEADER__DEVICE_TYPE_MASK
173584. BIF_CFG_DEV1_EPF2_1_HEADER__DEVICE_TYPE__SHIFT
173585. BIF_CFG_DEV1_EPF2_1_HEADER__HEADER_TYPE_MASK
173586. BIF_CFG_DEV1_EPF2_1_HEADER__HEADER_TYPE__SHIFT
173587. BIF_CFG_DEV1_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
173588. BIF_CFG_DEV1_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
173589. BIF_CFG_DEV1_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
173590. BIF_CFG_DEV1_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
173591. BIF_CFG_DEV1_EPF2_1_LATENCY__LATENCY_TIMER_MASK
173592. BIF_CFG_DEV1_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT
173593. BIF_CFG_DEV1_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
173594. BIF_CFG_DEV1_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
173595. BIF_CFG_DEV1_EPF2_1_LINK_CAP2__RESERVED_MASK
173596. BIF_CFG_DEV1_EPF2_1_LINK_CAP2__RESERVED__SHIFT
173597. BIF_CFG_DEV1_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
173598. BIF_CFG_DEV1_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
173599. BIF_CFG_DEV1_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
173600. BIF_CFG_DEV1_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
173601. BIF_CFG_DEV1_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
173602. BIF_CFG_DEV1_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
173603. BIF_CFG_DEV1_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
173604. BIF_CFG_DEV1_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
173605. BIF_CFG_DEV1_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
173606. BIF_CFG_DEV1_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
173607. BIF_CFG_DEV1_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK
173608. BIF_CFG_DEV1_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
173609. BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
173610. BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
173611. BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_SPEED_MASK
173612. BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT
173613. BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_WIDTH_MASK
173614. BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT
173615. BIF_CFG_DEV1_EPF2_1_LINK_CAP__PM_SUPPORT_MASK
173616. BIF_CFG_DEV1_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT
173617. BIF_CFG_DEV1_EPF2_1_LINK_CAP__PORT_NUMBER_MASK
173618. BIF_CFG_DEV1_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT
173619. BIF_CFG_DEV1_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
173620. BIF_CFG_DEV1_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
173621. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
173622. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
173623. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
173624. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
173625. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
173626. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
173627. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
173628. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
173629. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
173630. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
173631. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
173632. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
173633. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
173634. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
173635. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK
173636. BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
173637. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
173638. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
173639. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
173640. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
173641. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK
173642. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
173643. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
173644. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
173645. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
173646. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
173647. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
173648. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
173649. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_DIS_MASK
173650. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT
173651. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__PM_CONTROL_MASK
173652. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT
173653. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
173654. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
173655. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK
173656. BIF_CFG_DEV1_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT
173657. BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
173658. BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
173659. BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
173660. BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
173661. BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
173662. BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
173663. BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
173664. BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
173665. BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
173666. BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
173667. BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
173668. BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
173669. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
173670. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
173671. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK
173672. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT
173673. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
173674. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
173675. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
173676. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
173677. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK
173678. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT
173679. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
173680. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
173681. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
173682. BIF_CFG_DEV1_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
173683. BIF_CFG_DEV1_EPF2_1_MAX_LATENCY__MAX_LAT_MASK
173684. BIF_CFG_DEV1_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT
173685. BIF_CFG_DEV1_EPF2_1_MIN_GRANT__MIN_GNT_MASK
173686. BIF_CFG_DEV1_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT
173687. BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK
173688. BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT
173689. BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK
173690. BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT
173691. BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK
173692. BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT
173693. BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
173694. BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
173695. BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
173696. BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
173697. BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK
173698. BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT
173699. BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK
173700. BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
173701. BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK
173702. BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
173703. BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
173704. BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
173705. BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK
173706. BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT
173707. BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK
173708. BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
173709. BIF_CFG_DEV1_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK
173710. BIF_CFG_DEV1_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT
173711. BIF_CFG_DEV1_EPF2_1_MSI_MASK__MSI_MASK_MASK
173712. BIF_CFG_DEV1_EPF2_1_MSI_MASK__MSI_MASK__SHIFT
173713. BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
173714. BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
173715. BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
173716. BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
173717. BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK
173718. BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
173719. BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK
173720. BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT
173721. BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
173722. BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
173723. BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
173724. BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
173725. BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
173726. BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
173727. BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
173728. BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
173729. BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK
173730. BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT
173731. BIF_CFG_DEV1_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK
173732. BIF_CFG_DEV1_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT
173733. BIF_CFG_DEV1_EPF2_1_MSI_PENDING__MSI_PENDING_MASK
173734. BIF_CFG_DEV1_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT
173735. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
173736. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
173737. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
173738. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
173739. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
173740. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
173741. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
173742. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
173743. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
173744. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
173745. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
173746. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
173747. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
173748. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
173749. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
173750. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
173751. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
173752. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
173753. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
173754. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
173755. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
173756. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
173757. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
173758. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
173759. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
173760. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
173761. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
173762. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
173763. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
173764. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
173765. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
173766. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
173767. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
173768. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
173769. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
173770. BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
173771. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
173772. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
173773. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
173774. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
173775. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
173776. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
173777. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
173778. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
173779. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
173780. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
173781. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
173782. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
173783. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
173784. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
173785. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
173786. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
173787. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
173788. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
173789. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
173790. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
173791. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
173792. BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
173793. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
173794. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
173795. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
173796. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
173797. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
173798. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
173799. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
173800. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
173801. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
173802. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
173803. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
173804. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
173805. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
173806. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
173807. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
173808. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
173809. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
173810. BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
173811. BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
173812. BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
173813. BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK
173814. BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
173815. BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK
173816. BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
173817. BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
173818. BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
173819. BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
173820. BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
173821. BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK
173822. BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
173823. BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK
173824. BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
173825. BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
173826. BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
173827. BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
173828. BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
173829. BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK
173830. BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
173831. BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK
173832. BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
173833. BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
173834. BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
173835. BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
173836. BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
173837. BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK
173838. BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
173839. BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK
173840. BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
173841. BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
173842. BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
173843. BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
173844. BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
173845. BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK
173846. BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
173847. BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK
173848. BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
173849. BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
173850. BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
173851. BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
173852. BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
173853. BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK
173854. BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
173855. BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK
173856. BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
173857. BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
173858. BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
173859. BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
173860. BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
173861. BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
173862. BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
173863. BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
173864. BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
173865. BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK
173866. BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT
173867. BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK
173868. BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
173869. BIF_CFG_DEV1_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK
173870. BIF_CFG_DEV1_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT
173871. BIF_CFG_DEV1_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
173872. BIF_CFG_DEV1_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
173873. BIF_CFG_DEV1_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
173874. BIF_CFG_DEV1_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
173875. BIF_CFG_DEV1_EPF2_1_PCIE_CAP__VERSION_MASK
173876. BIF_CFG_DEV1_EPF2_1_PCIE_CAP__VERSION__SHIFT
173877. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
173878. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
173879. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
173880. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
173881. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
173882. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
173883. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
173884. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
173885. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
173886. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
173887. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
173888. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
173889. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
173890. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
173891. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
173892. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
173893. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
173894. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
173895. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
173896. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
173897. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
173898. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
173899. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
173900. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
173901. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
173902. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
173903. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
173904. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
173905. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
173906. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
173907. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
173908. BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
173909. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
173910. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
173911. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
173912. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
173913. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
173914. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
173915. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
173916. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
173917. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
173918. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
173919. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
173920. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
173921. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
173922. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
173923. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
173924. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
173925. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
173926. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
173927. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
173928. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
173929. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
173930. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
173931. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
173932. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
173933. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
173934. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
173935. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
173936. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
173937. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
173938. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
173939. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
173940. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
173941. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
173942. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
173943. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
173944. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
173945. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
173946. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
173947. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
173948. BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
173949. BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK
173950. BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
173951. BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK
173952. BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
173953. BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK
173954. BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
173955. BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK
173956. BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
173957. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
173958. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
173959. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
173960. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
173961. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
173962. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
173963. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
173964. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
173965. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
173966. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
173967. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
173968. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
173969. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
173970. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
173971. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK
173972. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
173973. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
173974. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
173975. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
173976. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
173977. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
173978. BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
173979. BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
173980. BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
173981. BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
173982. BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
173983. BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
173984. BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
173985. BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
173986. BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
173987. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
173988. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
173989. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
173990. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
173991. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
173992. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
173993. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
173994. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
173995. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
173996. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
173997. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
173998. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
173999. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
174000. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
174001. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
174002. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
174003. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
174004. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
174005. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
174006. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
174007. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
174008. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
174009. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
174010. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
174011. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
174012. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
174013. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
174014. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
174015. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
174016. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
174017. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
174018. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
174019. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
174020. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
174021. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
174022. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
174023. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
174024. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
174025. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
174026. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
174027. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
174028. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
174029. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
174030. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
174031. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
174032. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
174033. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
174034. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
174035. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
174036. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
174037. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
174038. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
174039. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
174040. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
174041. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
174042. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
174043. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
174044. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
174045. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
174046. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
174047. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
174048. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
174049. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
174050. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
174051. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
174052. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
174053. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
174054. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
174055. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
174056. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
174057. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
174058. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
174059. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
174060. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
174061. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
174062. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
174063. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
174064. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
174065. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
174066. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
174067. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
174068. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
174069. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
174070. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
174071. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
174072. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
174073. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
174074. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
174075. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
174076. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
174077. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
174078. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
174079. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
174080. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
174081. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
174082. BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
174083. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
174084. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
174085. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
174086. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
174087. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
174088. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
174089. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
174090. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
174091. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
174092. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
174093. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
174094. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
174095. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
174096. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
174097. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
174098. BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
174099. BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK
174100. BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT
174101. BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK
174102. BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
174103. BIF_CFG_DEV1_EPF2_1_PMI_CAP__AUX_CURRENT_MASK
174104. BIF_CFG_DEV1_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT
174105. BIF_CFG_DEV1_EPF2_1_PMI_CAP__D1_SUPPORT_MASK
174106. BIF_CFG_DEV1_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT
174107. BIF_CFG_DEV1_EPF2_1_PMI_CAP__D2_SUPPORT_MASK
174108. BIF_CFG_DEV1_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT
174109. BIF_CFG_DEV1_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
174110. BIF_CFG_DEV1_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
174111. BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_CLOCK_MASK
174112. BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT
174113. BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_SUPPORT_MASK
174114. BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT
174115. BIF_CFG_DEV1_EPF2_1_PMI_CAP__VERSION_MASK
174116. BIF_CFG_DEV1_EPF2_1_PMI_CAP__VERSION__SHIFT
174117. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
174118. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
174119. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
174120. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
174121. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
174122. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
174123. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
174124. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
174125. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
174126. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
174127. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK
174128. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT
174129. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK
174130. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
174131. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK
174132. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
174133. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK
174134. BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
174135. BIF_CFG_DEV1_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK
174136. BIF_CFG_DEV1_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
174137. BIF_CFG_DEV1_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK
174138. BIF_CFG_DEV1_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT
174139. BIF_CFG_DEV1_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK
174140. BIF_CFG_DEV1_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT
174141. BIF_CFG_DEV1_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK
174142. BIF_CFG_DEV1_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
174143. BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__CAP_ID_MASK
174144. BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__CAP_ID__SHIFT
174145. BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__NEXT_PTR_MASK
174146. BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__NEXT_PTR__SHIFT
174147. BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
174148. BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
174149. BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
174150. BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
174151. BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
174152. BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
174153. BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
174154. BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
174155. BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
174156. BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
174157. BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
174158. BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
174159. BIF_CFG_DEV1_EPF2_1_SATA_IDP_DATA__IDP_DATA_MASK
174160. BIF_CFG_DEV1_EPF2_1_SATA_IDP_DATA__IDP_DATA__SHIFT
174161. BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_INDEX_MASK
174162. BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT
174163. BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK
174164. BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
174165. BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK
174166. BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
174167. BIF_CFG_DEV1_EPF2_1_SBRN__SBRN_MASK
174168. BIF_CFG_DEV1_EPF2_1_SBRN__SBRN__SHIFT
174169. BIF_CFG_DEV1_EPF2_1_SLOT_CAP2__RESERVED_MASK
174170. BIF_CFG_DEV1_EPF2_1_SLOT_CAP2__RESERVED__SHIFT
174171. BIF_CFG_DEV1_EPF2_1_SLOT_CNTL2__RESERVED_MASK
174172. BIF_CFG_DEV1_EPF2_1_SLOT_CNTL2__RESERVED__SHIFT
174173. BIF_CFG_DEV1_EPF2_1_SLOT_STATUS2__RESERVED_MASK
174174. BIF_CFG_DEV1_EPF2_1_SLOT_STATUS2__RESERVED__SHIFT
174175. BIF_CFG_DEV1_EPF2_1_STATUS__CAP_LIST_MASK
174176. BIF_CFG_DEV1_EPF2_1_STATUS__CAP_LIST__SHIFT
174177. BIF_CFG_DEV1_EPF2_1_STATUS__DEVSEL_TIMING_MASK
174178. BIF_CFG_DEV1_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT
174179. BIF_CFG_DEV1_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK
174180. BIF_CFG_DEV1_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT
174181. BIF_CFG_DEV1_EPF2_1_STATUS__INT_STATUS_MASK
174182. BIF_CFG_DEV1_EPF2_1_STATUS__INT_STATUS__SHIFT
174183. BIF_CFG_DEV1_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
174184. BIF_CFG_DEV1_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
174185. BIF_CFG_DEV1_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK
174186. BIF_CFG_DEV1_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
174187. BIF_CFG_DEV1_EPF2_1_STATUS__PCI_66_EN_MASK
174188. BIF_CFG_DEV1_EPF2_1_STATUS__PCI_66_EN__SHIFT
174189. BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK
174190. BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
174191. BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK
174192. BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
174193. BIF_CFG_DEV1_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
174194. BIF_CFG_DEV1_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
174195. BIF_CFG_DEV1_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK
174196. BIF_CFG_DEV1_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
174197. BIF_CFG_DEV1_EPF2_1_SUB_CLASS__SUB_CLASS_MASK
174198. BIF_CFG_DEV1_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT
174199. BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK
174200. BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT
174201. BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK
174202. BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT
174203. BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK
174204. BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
174205. BIF_CFG_DEV1_EPF2_1_VENDOR_ID__VENDOR_ID_MASK
174206. BIF_CFG_DEV1_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT
174207. BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
174208. BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
174209. BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
174210. BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
174211. BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID_MASK
174212. BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
174213. BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
174214. BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
174215. BIF_CFG_DEV1_EPF2_2_BASE_ADDR_1__BASE_ADDR_MASK
174216. BIF_CFG_DEV1_EPF2_2_BASE_ADDR_1__BASE_ADDR__SHIFT
174217. BIF_CFG_DEV1_EPF2_2_BASE_ADDR_2__BASE_ADDR_MASK
174218. BIF_CFG_DEV1_EPF2_2_BASE_ADDR_2__BASE_ADDR__SHIFT
174219. BIF_CFG_DEV1_EPF2_2_BASE_ADDR_3__BASE_ADDR_MASK
174220. BIF_CFG_DEV1_EPF2_2_BASE_ADDR_3__BASE_ADDR__SHIFT
174221. BIF_CFG_DEV1_EPF2_2_BASE_ADDR_4__BASE_ADDR_MASK
174222. BIF_CFG_DEV1_EPF2_2_BASE_ADDR_4__BASE_ADDR__SHIFT
174223. BIF_CFG_DEV1_EPF2_2_BASE_ADDR_5__BASE_ADDR_MASK
174224. BIF_CFG_DEV1_EPF2_2_BASE_ADDR_5__BASE_ADDR__SHIFT
174225. BIF_CFG_DEV1_EPF2_2_BASE_ADDR_6__BASE_ADDR_MASK
174226. BIF_CFG_DEV1_EPF2_2_BASE_ADDR_6__BASE_ADDR__SHIFT
174227. BIF_CFG_DEV1_EPF2_2_BASE_CLASS__BASE_CLASS_MASK
174228. BIF_CFG_DEV1_EPF2_2_BASE_CLASS__BASE_CLASS__SHIFT
174229. BIF_CFG_DEV1_EPF2_2_BIST__BIST_CAP_MASK
174230. BIF_CFG_DEV1_EPF2_2_BIST__BIST_CAP__SHIFT
174231. BIF_CFG_DEV1_EPF2_2_BIST__BIST_COMP_MASK
174232. BIF_CFG_DEV1_EPF2_2_BIST__BIST_COMP__SHIFT
174233. BIF_CFG_DEV1_EPF2_2_BIST__BIST_STRT_MASK
174234. BIF_CFG_DEV1_EPF2_2_BIST__BIST_STRT__SHIFT
174235. BIF_CFG_DEV1_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE_MASK
174236. BIF_CFG_DEV1_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
174237. BIF_CFG_DEV1_EPF2_2_CAP_PTR__CAP_PTR_MASK
174238. BIF_CFG_DEV1_EPF2_2_CAP_PTR__CAP_PTR__SHIFT
174239. BIF_CFG_DEV1_EPF2_2_COMMAND__AD_STEPPING_MASK
174240. BIF_CFG_DEV1_EPF2_2_COMMAND__AD_STEPPING__SHIFT
174241. BIF_CFG_DEV1_EPF2_2_COMMAND__BUS_MASTER_EN_MASK
174242. BIF_CFG_DEV1_EPF2_2_COMMAND__BUS_MASTER_EN__SHIFT
174243. BIF_CFG_DEV1_EPF2_2_COMMAND__FAST_B2B_EN_MASK
174244. BIF_CFG_DEV1_EPF2_2_COMMAND__FAST_B2B_EN__SHIFT
174245. BIF_CFG_DEV1_EPF2_2_COMMAND__INT_DIS_MASK
174246. BIF_CFG_DEV1_EPF2_2_COMMAND__INT_DIS__SHIFT
174247. BIF_CFG_DEV1_EPF2_2_COMMAND__IO_ACCESS_EN_MASK
174248. BIF_CFG_DEV1_EPF2_2_COMMAND__IO_ACCESS_EN__SHIFT
174249. BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_ACCESS_EN_MASK
174250. BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_ACCESS_EN__SHIFT
174251. BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
174252. BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
174253. BIF_CFG_DEV1_EPF2_2_COMMAND__PAL_SNOOP_EN_MASK
174254. BIF_CFG_DEV1_EPF2_2_COMMAND__PAL_SNOOP_EN__SHIFT
174255. BIF_CFG_DEV1_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE_MASK
174256. BIF_CFG_DEV1_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
174257. BIF_CFG_DEV1_EPF2_2_COMMAND__SERR_EN_MASK
174258. BIF_CFG_DEV1_EPF2_2_COMMAND__SERR_EN__SHIFT
174259. BIF_CFG_DEV1_EPF2_2_COMMAND__SPECIAL_CYCLE_EN_MASK
174260. BIF_CFG_DEV1_EPF2_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
174261. BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESLD_MASK
174262. BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESLD__SHIFT
174263. BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESL_MASK
174264. BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESL__SHIFT
174265. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
174266. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
174267. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
174268. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
174269. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
174270. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
174271. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
174272. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
174273. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
174274. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
174275. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
174276. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
174277. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
174278. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
174279. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
174280. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
174281. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
174282. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
174283. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED_MASK
174284. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
174285. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
174286. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
174287. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
174288. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
174289. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
174290. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
174291. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
174292. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
174293. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
174294. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
174295. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
174296. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
174297. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__EXTENDED_TAG_MASK
174298. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__EXTENDED_TAG__SHIFT
174299. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__FLR_CAPABLE_MASK
174300. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__FLR_CAPABLE__SHIFT
174301. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
174302. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
174303. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
174304. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
174305. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
174306. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
174307. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__PHANTOM_FUNC_MASK
174308. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
174309. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
174310. BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
174311. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
174312. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
174313. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
174314. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
174315. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
174316. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
174317. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
174318. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
174319. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
174320. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
174321. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
174322. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
174323. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
174324. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
174325. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
174326. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
174327. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__LTR_EN_MASK
174328. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__LTR_EN__SHIFT
174329. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__OBFF_EN_MASK
174330. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__OBFF_EN__SHIFT
174331. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
174332. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
174333. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__CORR_ERR_EN_MASK
174334. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
174335. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
174336. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
174337. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN_MASK
174338. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
174339. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__INITIATE_FLR_MASK
174340. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__INITIATE_FLR__SHIFT
174341. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
174342. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
174343. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
174344. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
174345. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
174346. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
174347. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN_MASK
174348. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
174349. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
174350. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
174351. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
174352. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
174353. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__USR_REPORT_EN_MASK
174354. BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
174355. BIF_CFG_DEV1_EPF2_2_DEVICE_ID__DEVICE_ID_MASK
174356. BIF_CFG_DEV1_EPF2_2_DEVICE_ID__DEVICE_ID__SHIFT
174357. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS2__RESERVED_MASK
174358. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS2__RESERVED__SHIFT
174359. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__AUX_PWR_MASK
174360. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__AUX_PWR__SHIFT
174361. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__CORR_ERR_MASK
174362. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__CORR_ERR__SHIFT
174363. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__FATAL_ERR_MASK
174364. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__FATAL_ERR__SHIFT
174365. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR_MASK
174366. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
174367. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
174368. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
174369. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__USR_DETECTED_MASK
174370. BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__USR_DETECTED__SHIFT
174371. BIF_CFG_DEV1_EPF2_2_FLADJ__FLADJ_MASK
174372. BIF_CFG_DEV1_EPF2_2_FLADJ__FLADJ__SHIFT
174373. BIF_CFG_DEV1_EPF2_2_HEADER__DEVICE_TYPE_MASK
174374. BIF_CFG_DEV1_EPF2_2_HEADER__DEVICE_TYPE__SHIFT
174375. BIF_CFG_DEV1_EPF2_2_HEADER__HEADER_TYPE_MASK
174376. BIF_CFG_DEV1_EPF2_2_HEADER__HEADER_TYPE__SHIFT
174377. BIF_CFG_DEV1_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
174378. BIF_CFG_DEV1_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
174379. BIF_CFG_DEV1_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
174380. BIF_CFG_DEV1_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
174381. BIF_CFG_DEV1_EPF2_2_LATENCY__LATENCY_TIMER_MASK
174382. BIF_CFG_DEV1_EPF2_2_LATENCY__LATENCY_TIMER__SHIFT
174383. BIF_CFG_DEV1_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
174384. BIF_CFG_DEV1_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
174385. BIF_CFG_DEV1_EPF2_2_LINK_CAP2__RESERVED_MASK
174386. BIF_CFG_DEV1_EPF2_2_LINK_CAP2__RESERVED__SHIFT
174387. BIF_CFG_DEV1_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
174388. BIF_CFG_DEV1_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
174389. BIF_CFG_DEV1_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
174390. BIF_CFG_DEV1_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
174391. BIF_CFG_DEV1_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
174392. BIF_CFG_DEV1_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
174393. BIF_CFG_DEV1_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
174394. BIF_CFG_DEV1_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
174395. BIF_CFG_DEV1_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY_MASK
174396. BIF_CFG_DEV1_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
174397. BIF_CFG_DEV1_EPF2_2_LINK_CAP__L1_EXIT_LATENCY_MASK
174398. BIF_CFG_DEV1_EPF2_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
174399. BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
174400. BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
174401. BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_SPEED_MASK
174402. BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_SPEED__SHIFT
174403. BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_WIDTH_MASK
174404. BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_WIDTH__SHIFT
174405. BIF_CFG_DEV1_EPF2_2_LINK_CAP__PM_SUPPORT_MASK
174406. BIF_CFG_DEV1_EPF2_2_LINK_CAP__PM_SUPPORT__SHIFT
174407. BIF_CFG_DEV1_EPF2_2_LINK_CAP__PORT_NUMBER_MASK
174408. BIF_CFG_DEV1_EPF2_2_LINK_CAP__PORT_NUMBER__SHIFT
174409. BIF_CFG_DEV1_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
174410. BIF_CFG_DEV1_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
174411. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
174412. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
174413. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS_MASK
174414. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
174415. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
174416. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
174417. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
174418. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
174419. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
174420. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
174421. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
174422. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
174423. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
174424. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
174425. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__XMIT_MARGIN_MASK
174426. BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__XMIT_MARGIN__SHIFT
174427. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
174428. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
174429. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
174430. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
174431. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__EXTENDED_SYNC_MASK
174432. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__EXTENDED_SYNC__SHIFT
174433. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
174434. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
174435. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
174436. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
174437. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
174438. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
174439. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_DIS_MASK
174440. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_DIS__SHIFT
174441. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__PM_CONTROL_MASK
174442. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__PM_CONTROL__SHIFT
174443. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
174444. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
174445. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__RETRAIN_LINK_MASK
174446. BIF_CFG_DEV1_EPF2_2_LINK_CNTL__RETRAIN_LINK__SHIFT
174447. BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
174448. BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
174449. BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
174450. BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
174451. BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
174452. BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
174453. BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
174454. BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
174455. BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
174456. BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
174457. BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
174458. BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
174459. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
174460. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
174461. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__DL_ACTIVE_MASK
174462. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__DL_ACTIVE__SHIFT
174463. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
174464. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
174465. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
174466. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
174467. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_TRAINING_MASK
174468. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_TRAINING__SHIFT
174469. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
174470. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
174471. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
174472. BIF_CFG_DEV1_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
174473. BIF_CFG_DEV1_EPF2_2_MAX_LATENCY__MAX_LAT_MASK
174474. BIF_CFG_DEV1_EPF2_2_MAX_LATENCY__MAX_LAT__SHIFT
174475. BIF_CFG_DEV1_EPF2_2_MIN_GRANT__MIN_GNT_MASK
174476. BIF_CFG_DEV1_EPF2_2_MIN_GRANT__MIN_GNT__SHIFT
174477. BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__CAP_ID_MASK
174478. BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__CAP_ID__SHIFT
174479. BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__NEXT_PTR_MASK
174480. BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT
174481. BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_EN_MASK
174482. BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT
174483. BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK
174484. BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT
174485. BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK
174486. BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT
174487. BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_BIR_MASK
174488. BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT
174489. BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK
174490. BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT
174491. BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK
174492. BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT
174493. BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK
174494. BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT
174495. BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__CAP_ID_MASK
174496. BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__CAP_ID__SHIFT
174497. BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__NEXT_PTR_MASK
174498. BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__NEXT_PTR__SHIFT
174499. BIF_CFG_DEV1_EPF2_2_MSI_MASK_64__MSI_MASK_64_MASK
174500. BIF_CFG_DEV1_EPF2_2_MSI_MASK_64__MSI_MASK_64__SHIFT
174501. BIF_CFG_DEV1_EPF2_2_MSI_MASK__MSI_MASK_MASK
174502. BIF_CFG_DEV1_EPF2_2_MSI_MASK__MSI_MASK__SHIFT
174503. BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
174504. BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
174505. BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
174506. BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
174507. BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_64BIT_MASK
174508. BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
174509. BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_EN_MASK
174510. BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_EN__SHIFT
174511. BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
174512. BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
174513. BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
174514. BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
174515. BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
174516. BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
174517. BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
174518. BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
174519. BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA__MSI_DATA_MASK
174520. BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA__MSI_DATA__SHIFT
174521. BIF_CFG_DEV1_EPF2_2_MSI_PENDING_64__MSI_PENDING_64_MASK
174522. BIF_CFG_DEV1_EPF2_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT
174523. BIF_CFG_DEV1_EPF2_2_MSI_PENDING__MSI_PENDING_MASK
174524. BIF_CFG_DEV1_EPF2_2_MSI_PENDING__MSI_PENDING__SHIFT
174525. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
174526. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
174527. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
174528. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
174529. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
174530. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
174531. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
174532. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
174533. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
174534. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
174535. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
174536. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
174537. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
174538. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
174539. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
174540. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
174541. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
174542. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
174543. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
174544. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
174545. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
174546. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
174547. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
174548. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
174549. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
174550. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
174551. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
174552. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
174553. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
174554. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
174555. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
174556. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
174557. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
174558. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
174559. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
174560. BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
174561. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
174562. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
174563. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
174564. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
174565. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
174566. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
174567. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
174568. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
174569. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
174570. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
174571. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
174572. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
174573. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
174574. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
174575. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
174576. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
174577. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
174578. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
174579. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
174580. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
174581. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
174582. BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
174583. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
174584. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
174585. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
174586. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
174587. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
174588. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
174589. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
174590. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
174591. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
174592. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
174593. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
174594. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
174595. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
174596. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
174597. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
174598. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
174599. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
174600. BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
174601. BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
174602. BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
174603. BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK
174604. BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
174605. BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK
174606. BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
174607. BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
174608. BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
174609. BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
174610. BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
174611. BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK
174612. BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
174613. BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK
174614. BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
174615. BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
174616. BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
174617. BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
174618. BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
174619. BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK
174620. BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
174621. BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK
174622. BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
174623. BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
174624. BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
174625. BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
174626. BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
174627. BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK
174628. BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
174629. BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK
174630. BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
174631. BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
174632. BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
174633. BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
174634. BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
174635. BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK
174636. BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
174637. BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK
174638. BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
174639. BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
174640. BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
174641. BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
174642. BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
174643. BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK
174644. BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
174645. BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK
174646. BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
174647. BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
174648. BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
174649. BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
174650. BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
174651. BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
174652. BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
174653. BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
174654. BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
174655. BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__CAP_ID_MASK
174656. BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__CAP_ID__SHIFT
174657. BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__NEXT_PTR_MASK
174658. BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
174659. BIF_CFG_DEV1_EPF2_2_PCIE_CAP__DEVICE_TYPE_MASK
174660. BIF_CFG_DEV1_EPF2_2_PCIE_CAP__DEVICE_TYPE__SHIFT
174661. BIF_CFG_DEV1_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM_MASK
174662. BIF_CFG_DEV1_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
174663. BIF_CFG_DEV1_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
174664. BIF_CFG_DEV1_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
174665. BIF_CFG_DEV1_EPF2_2_PCIE_CAP__VERSION_MASK
174666. BIF_CFG_DEV1_EPF2_2_PCIE_CAP__VERSION__SHIFT
174667. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
174668. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
174669. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
174670. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
174671. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
174672. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
174673. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
174674. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
174675. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
174676. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
174677. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
174678. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
174679. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
174680. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
174681. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
174682. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
174683. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
174684. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
174685. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
174686. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
174687. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
174688. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
174689. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
174690. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
174691. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
174692. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
174693. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
174694. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
174695. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
174696. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
174697. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
174698. BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
174699. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
174700. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
174701. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK
174702. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
174703. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
174704. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
174705. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
174706. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
174707. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
174708. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
174709. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
174710. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
174711. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
174712. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
174713. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
174714. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
174715. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
174716. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
174717. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
174718. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
174719. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
174720. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
174721. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
174722. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
174723. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
174724. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
174725. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
174726. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
174727. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
174728. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
174729. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
174730. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
174731. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
174732. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
174733. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
174734. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
174735. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
174736. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
174737. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
174738. BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
174739. BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG0__TLP_HDR_MASK
174740. BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
174741. BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG1__TLP_HDR_MASK
174742. BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
174743. BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG2__TLP_HDR_MASK
174744. BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
174745. BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG3__TLP_HDR_MASK
174746. BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
174747. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
174748. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
174749. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
174750. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
174751. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
174752. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
174753. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
174754. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
174755. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
174756. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
174757. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
174758. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
174759. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
174760. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
174761. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK
174762. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
174763. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
174764. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
174765. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
174766. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
174767. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
174768. BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
174769. BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
174770. BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
174771. BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
174772. BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
174773. BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
174774. BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
174775. BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
174776. BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
174777. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
174778. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
174779. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
174780. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
174781. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
174782. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
174783. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
174784. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
174785. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
174786. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
174787. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
174788. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
174789. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
174790. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
174791. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
174792. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
174793. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
174794. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
174795. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
174796. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
174797. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
174798. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
174799. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
174800. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
174801. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
174802. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
174803. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
174804. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
174805. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
174806. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
174807. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
174808. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
174809. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
174810. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
174811. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
174812. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
174813. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
174814. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
174815. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
174816. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
174817. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
174818. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
174819. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
174820. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
174821. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
174822. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
174823. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
174824. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
174825. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
174826. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
174827. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
174828. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
174829. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
174830. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
174831. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
174832. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
174833. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
174834. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
174835. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
174836. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
174837. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
174838. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
174839. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
174840. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
174841. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
174842. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
174843. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
174844. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
174845. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
174846. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
174847. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
174848. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
174849. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
174850. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
174851. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
174852. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
174853. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
174854. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
174855. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
174856. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
174857. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
174858. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
174859. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
174860. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
174861. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
174862. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
174863. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
174864. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
174865. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
174866. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
174867. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
174868. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
174869. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
174870. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
174871. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
174872. BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
174873. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
174874. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
174875. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
174876. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
174877. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
174878. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
174879. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
174880. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
174881. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
174882. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
174883. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
174884. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
174885. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
174886. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
174887. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
174888. BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
174889. BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__CAP_ID_MASK
174890. BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__CAP_ID__SHIFT
174891. BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__NEXT_PTR_MASK
174892. BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__NEXT_PTR__SHIFT
174893. BIF_CFG_DEV1_EPF2_2_PMI_CAP__AUX_CURRENT_MASK
174894. BIF_CFG_DEV1_EPF2_2_PMI_CAP__AUX_CURRENT__SHIFT
174895. BIF_CFG_DEV1_EPF2_2_PMI_CAP__D1_SUPPORT_MASK
174896. BIF_CFG_DEV1_EPF2_2_PMI_CAP__D1_SUPPORT__SHIFT
174897. BIF_CFG_DEV1_EPF2_2_PMI_CAP__D2_SUPPORT_MASK
174898. BIF_CFG_DEV1_EPF2_2_PMI_CAP__D2_SUPPORT__SHIFT
174899. BIF_CFG_DEV1_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
174900. BIF_CFG_DEV1_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
174901. BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_CLOCK_MASK
174902. BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_CLOCK__SHIFT
174903. BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_SUPPORT_MASK
174904. BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_SUPPORT__SHIFT
174905. BIF_CFG_DEV1_EPF2_2_PMI_CAP__VERSION_MASK
174906. BIF_CFG_DEV1_EPF2_2_PMI_CAP__VERSION__SHIFT
174907. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
174908. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
174909. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
174910. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
174911. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE_MASK
174912. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
174913. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT_MASK
174914. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
174915. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
174916. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
174917. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_EN_MASK
174918. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_EN__SHIFT
174919. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_STATUS_MASK
174920. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
174921. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PMI_DATA_MASK
174922. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
174923. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__POWER_STATE_MASK
174924. BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
174925. BIF_CFG_DEV1_EPF2_2_PROG_INTERFACE__PROG_INTERFACE_MASK
174926. BIF_CFG_DEV1_EPF2_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
174927. BIF_CFG_DEV1_EPF2_2_REVISION_ID__MAJOR_REV_ID_MASK
174928. BIF_CFG_DEV1_EPF2_2_REVISION_ID__MAJOR_REV_ID__SHIFT
174929. BIF_CFG_DEV1_EPF2_2_REVISION_ID__MINOR_REV_ID_MASK
174930. BIF_CFG_DEV1_EPF2_2_REVISION_ID__MINOR_REV_ID__SHIFT
174931. BIF_CFG_DEV1_EPF2_2_ROM_BASE_ADDR__BASE_ADDR_MASK
174932. BIF_CFG_DEV1_EPF2_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT
174933. BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__CAP_ID_MASK
174934. BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__CAP_ID__SHIFT
174935. BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__NEXT_PTR_MASK
174936. BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__NEXT_PTR__SHIFT
174937. BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK
174938. BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT
174939. BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK
174940. BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT
174941. BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK
174942. BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT
174943. BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK
174944. BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT
174945. BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK
174946. BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT
174947. BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK
174948. BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT
174949. BIF_CFG_DEV1_EPF2_2_SATA_IDP_DATA__IDP_DATA_MASK
174950. BIF_CFG_DEV1_EPF2_2_SATA_IDP_DATA__IDP_DATA__SHIFT
174951. BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_INDEX_MASK
174952. BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT
174953. BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK
174954. BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT
174955. BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK
174956. BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT
174957. BIF_CFG_DEV1_EPF2_2_SBRN__SBRN_MASK
174958. BIF_CFG_DEV1_EPF2_2_SBRN__SBRN__SHIFT
174959. BIF_CFG_DEV1_EPF2_2_SLOT_CAP2__RESERVED_MASK
174960. BIF_CFG_DEV1_EPF2_2_SLOT_CAP2__RESERVED__SHIFT
174961. BIF_CFG_DEV1_EPF2_2_SLOT_CNTL2__RESERVED_MASK
174962. BIF_CFG_DEV1_EPF2_2_SLOT_CNTL2__RESERVED__SHIFT
174963. BIF_CFG_DEV1_EPF2_2_SLOT_STATUS2__RESERVED_MASK
174964. BIF_CFG_DEV1_EPF2_2_SLOT_STATUS2__RESERVED__SHIFT
174965. BIF_CFG_DEV1_EPF2_2_STATUS__CAP_LIST_MASK
174966. BIF_CFG_DEV1_EPF2_2_STATUS__CAP_LIST__SHIFT
174967. BIF_CFG_DEV1_EPF2_2_STATUS__DEVSEL_TIMING_MASK
174968. BIF_CFG_DEV1_EPF2_2_STATUS__DEVSEL_TIMING__SHIFT
174969. BIF_CFG_DEV1_EPF2_2_STATUS__FAST_BACK_CAPABLE_MASK
174970. BIF_CFG_DEV1_EPF2_2_STATUS__FAST_BACK_CAPABLE__SHIFT
174971. BIF_CFG_DEV1_EPF2_2_STATUS__INT_STATUS_MASK
174972. BIF_CFG_DEV1_EPF2_2_STATUS__INT_STATUS__SHIFT
174973. BIF_CFG_DEV1_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
174974. BIF_CFG_DEV1_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
174975. BIF_CFG_DEV1_EPF2_2_STATUS__PARITY_ERROR_DETECTED_MASK
174976. BIF_CFG_DEV1_EPF2_2_STATUS__PARITY_ERROR_DETECTED__SHIFT
174977. BIF_CFG_DEV1_EPF2_2_STATUS__PCI_66_EN_MASK
174978. BIF_CFG_DEV1_EPF2_2_STATUS__PCI_66_EN__SHIFT
174979. BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_MASTER_ABORT_MASK
174980. BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
174981. BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_TARGET_ABORT_MASK
174982. BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
174983. BIF_CFG_DEV1_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
174984. BIF_CFG_DEV1_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
174985. BIF_CFG_DEV1_EPF2_2_STATUS__SIGNAL_TARGET_ABORT_MASK
174986. BIF_CFG_DEV1_EPF2_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
174987. BIF_CFG_DEV1_EPF2_2_SUB_CLASS__SUB_CLASS_MASK
174988. BIF_CFG_DEV1_EPF2_2_SUB_CLASS__SUB_CLASS__SHIFT
174989. BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__CAP_ID_MASK
174990. BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__CAP_ID__SHIFT
174991. BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__LENGTH_MASK
174992. BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__LENGTH__SHIFT
174993. BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR_MASK
174994. BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
174995. BIF_CFG_DEV1_EPF2_2_VENDOR_ID__VENDOR_ID_MASK
174996. BIF_CFG_DEV1_EPF2_2_VENDOR_ID__VENDOR_ID__SHIFT
174997. BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR_MASK
174998. BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT
174999. BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS_MASK
175000. BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS__SHIFT
175001. BIF_CFG_DEV1_RC0_BIST__BIST_CAP_MASK
175002. BIF_CFG_DEV1_RC0_BIST__BIST_CAP__SHIFT
175003. BIF_CFG_DEV1_RC0_BIST__BIST_COMP_MASK
175004. BIF_CFG_DEV1_RC0_BIST__BIST_COMP__SHIFT
175005. BIF_CFG_DEV1_RC0_BIST__BIST_STRT_MASK
175006. BIF_CFG_DEV1_RC0_BIST__BIST_STRT__SHIFT
175007. BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK
175008. BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
175009. BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR_MASK
175010. BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR__SHIFT
175011. BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING_MASK
175012. BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING__SHIFT
175013. BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN_MASK
175014. BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN__SHIFT
175015. BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN_MASK
175016. BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN__SHIFT
175017. BIF_CFG_DEV1_RC0_COMMAND__INT_DIS_MASK
175018. BIF_CFG_DEV1_RC0_COMMAND__INT_DIS__SHIFT
175019. BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN_MASK
175020. BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN__SHIFT
175021. BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN_MASK
175022. BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN__SHIFT
175023. BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
175024. BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
175025. BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN_MASK
175026. BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN__SHIFT
175027. BIF_CFG_DEV1_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK
175028. BIF_CFG_DEV1_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
175029. BIF_CFG_DEV1_RC0_COMMAND__SERR_EN_MASK
175030. BIF_CFG_DEV1_RC0_COMMAND__SERR_EN__SHIFT
175031. BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK
175032. BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
175033. BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
175034. BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
175035. BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
175036. BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
175037. BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
175038. BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
175039. BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
175040. BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
175041. BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
175042. BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
175043. BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
175044. BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
175045. BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
175046. BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
175047. BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
175048. BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
175049. BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
175050. BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
175051. BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK
175052. BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
175053. BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
175054. BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
175055. BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
175056. BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
175057. BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
175058. BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
175059. BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
175060. BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
175061. BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
175062. BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
175063. BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
175064. BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
175065. BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG_MASK
175066. BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT
175067. BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE_MASK
175068. BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT
175069. BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
175070. BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
175071. BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
175072. BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
175073. BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
175074. BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
175075. BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK
175076. BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
175077. BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
175078. BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
175079. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
175080. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
175081. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
175082. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
175083. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
175084. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
175085. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
175086. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
175087. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
175088. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
175089. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
175090. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
175091. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
175092. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
175093. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
175094. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
175095. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN_MASK
175096. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN__SHIFT
175097. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN_MASK
175098. BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT
175099. BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
175100. BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
175101. BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
175102. BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
175103. BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK
175104. BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
175105. BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
175106. BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
175107. BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK
175108. BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
175109. BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
175110. BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
175111. BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
175112. BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
175113. BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
175114. BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
175115. BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK
175116. BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
175117. BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
175118. BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
175119. BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
175120. BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
175121. BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK
175122. BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
175123. BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID_MASK
175124. BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID__SHIFT
175125. BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED_MASK
175126. BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED__SHIFT
175127. BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR_MASK
175128. BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR__SHIFT
175129. BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR_MASK
175130. BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR__SHIFT
175131. BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR_MASK
175132. BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT
175133. BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK
175134. BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
175135. BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
175136. BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
175137. BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED_MASK
175138. BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT
175139. BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
175140. BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
175141. BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE_MASK
175142. BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE__SHIFT
175143. BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE_MASK
175144. BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE__SHIFT
175145. BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
175146. BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
175147. BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
175148. BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
175149. BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
175150. BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
175151. BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
175152. BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
175153. BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_MASK
175154. BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
175155. BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
175156. BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT
175157. BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK
175158. BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
175159. BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
175160. BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT
175161. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
175162. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
175163. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK
175164. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
175165. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
175166. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
175167. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
175168. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
175169. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
175170. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
175171. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK
175172. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
175173. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
175174. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
175175. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK
175176. BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
175177. BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER_MASK
175178. BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER__SHIFT
175179. BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
175180. BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
175181. BIF_CFG_DEV1_RC0_LINK_CAP2__RESERVED_MASK
175182. BIF_CFG_DEV1_RC0_LINK_CAP2__RESERVED__SHIFT
175183. BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
175184. BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
175185. BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
175186. BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
175187. BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
175188. BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
175189. BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
175190. BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
175191. BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK
175192. BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
175193. BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK
175194. BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
175195. BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
175196. BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
175197. BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED_MASK
175198. BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED__SHIFT
175199. BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH_MASK
175200. BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH__SHIFT
175201. BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT_MASK
175202. BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT__SHIFT
175203. BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER_MASK
175204. BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER__SHIFT
175205. BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
175206. BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
175207. BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
175208. BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
175209. BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK
175210. BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
175211. BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
175212. BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
175213. BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
175214. BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
175215. BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
175216. BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
175217. BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
175218. BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
175219. BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
175220. BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
175221. BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN_MASK
175222. BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT
175223. BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
175224. BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
175225. BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
175226. BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
175227. BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC_MASK
175228. BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT
175229. BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
175230. BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
175231. BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
175232. BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
175233. BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
175234. BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
175235. BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS_MASK
175236. BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS__SHIFT
175237. BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL_MASK
175238. BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL__SHIFT
175239. BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
175240. BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
175241. BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK_MASK
175242. BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT
175243. BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
175244. BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
175245. BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
175246. BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
175247. BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
175248. BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
175249. BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
175250. BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
175251. BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
175252. BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
175253. BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
175254. BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
175255. BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
175256. BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
175257. BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE_MASK
175258. BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE__SHIFT
175259. BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
175260. BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
175261. BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
175262. BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
175263. BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING_MASK
175264. BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING__SHIFT
175265. BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
175266. BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
175267. BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
175268. BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
175269. BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
175270. BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
175271. BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
175272. BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
175273. BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
175274. BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
175275. BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
175276. BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
175277. BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID_MASK
175278. BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID__SHIFT
175279. BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR_MASK
175280. BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT
175281. BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
175282. BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
175283. BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
175284. BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
175285. BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK
175286. BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
175287. BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
175288. BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
175289. BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE_MASK
175290. BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT
175291. BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN_MASK
175292. BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN__SHIFT
175293. BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD_MASK
175294. BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD__SHIFT
175295. BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
175296. BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
175297. BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
175298. BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
175299. BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK
175300. BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
175301. BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN_MASK
175302. BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT
175303. BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
175304. BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
175305. BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
175306. BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
175307. BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
175308. BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
175309. BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
175310. BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
175311. BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA_MASK
175312. BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT
175313. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
175314. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
175315. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
175316. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
175317. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
175318. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
175319. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
175320. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
175321. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
175322. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
175323. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
175324. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
175325. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
175326. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
175327. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
175328. BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
175329. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
175330. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
175331. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
175332. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
175333. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
175334. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
175335. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
175336. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
175337. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
175338. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
175339. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
175340. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
175341. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
175342. BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
175343. BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
175344. BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
175345. BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
175346. BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
175347. BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
175348. BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
175349. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
175350. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
175351. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
175352. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
175353. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
175354. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
175355. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
175356. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
175357. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
175358. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
175359. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
175360. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
175361. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
175362. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
175363. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
175364. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
175365. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
175366. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
175367. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
175368. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
175369. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
175370. BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
175371. BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID_MASK
175372. BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT
175373. BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK
175374. BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
175375. BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE_MASK
175376. BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT
175377. BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK
175378. BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
175379. BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
175380. BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
175381. BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION_MASK
175382. BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION__SHIFT
175383. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
175384. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
175385. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
175386. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
175387. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
175388. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
175389. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
175390. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
175391. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
175392. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
175393. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
175394. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
175395. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
175396. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
175397. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
175398. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
175399. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
175400. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
175401. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
175402. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
175403. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
175404. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
175405. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
175406. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
175407. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
175408. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
175409. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
175410. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
175411. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
175412. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
175413. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
175414. BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
175415. BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
175416. BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
175417. BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
175418. BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
175419. BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
175420. BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
175421. BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
175422. BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
175423. BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
175424. BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
175425. BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
175426. BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
175427. BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
175428. BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
175429. BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK
175430. BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
175431. BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK
175432. BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
175433. BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK
175434. BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
175435. BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK
175436. BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
175437. BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175438. BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175439. BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175440. BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175441. BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
175442. BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
175443. BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175444. BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175445. BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175446. BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175447. BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175448. BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175449. BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175450. BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175451. BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
175452. BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
175453. BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175454. BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175455. BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175456. BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175457. BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175458. BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175459. BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175460. BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175461. BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
175462. BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
175463. BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175464. BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175465. BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175466. BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175467. BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175468. BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175469. BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175470. BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175471. BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
175472. BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
175473. BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175474. BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175475. BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175476. BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175477. BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175478. BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175479. BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175480. BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175481. BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
175482. BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
175483. BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175484. BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175485. BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175486. BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175487. BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175488. BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175489. BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175490. BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175491. BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
175492. BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
175493. BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175494. BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175495. BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175496. BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175497. BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175498. BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175499. BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175500. BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175501. BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
175502. BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
175503. BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175504. BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175505. BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175506. BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175507. BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175508. BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175509. BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175510. BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175511. BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
175512. BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
175513. BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175514. BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175515. BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175516. BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175517. BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175518. BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175519. BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175520. BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175521. BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
175522. BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
175523. BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175524. BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175525. BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175526. BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175527. BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175528. BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175529. BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175530. BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175531. BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
175532. BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
175533. BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175534. BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175535. BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175536. BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175537. BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175538. BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175539. BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175540. BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175541. BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
175542. BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
175543. BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175544. BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175545. BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175546. BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175547. BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175548. BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175549. BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175550. BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175551. BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
175552. BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
175553. BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175554. BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175555. BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175556. BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175557. BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175558. BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175559. BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175560. BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175561. BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
175562. BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
175563. BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175564. BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175565. BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175566. BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175567. BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175568. BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175569. BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175570. BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175571. BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
175572. BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
175573. BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175574. BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175575. BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175576. BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175577. BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175578. BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175579. BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175580. BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175581. BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
175582. BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
175583. BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175584. BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175585. BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175586. BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175587. BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
175588. BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
175589. BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
175590. BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
175591. BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
175592. BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
175593. BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
175594. BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
175595. BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
175596. BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
175597. BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
175598. BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
175599. BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
175600. BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
175601. BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
175602. BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
175603. BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
175604. BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
175605. BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__RESERVED_MASK
175606. BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__RESERVED__SHIFT
175607. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
175608. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
175609. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
175610. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
175611. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
175612. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
175613. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
175614. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
175615. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
175616. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
175617. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
175618. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
175619. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
175620. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
175621. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
175622. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
175623. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
175624. BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
175625. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
175626. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
175627. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
175628. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
175629. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
175630. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
175631. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
175632. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
175633. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
175634. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
175635. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
175636. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
175637. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
175638. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
175639. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
175640. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
175641. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
175642. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
175643. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
175644. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
175645. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
175646. BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
175647. BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
175648. BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
175649. BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
175650. BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
175651. BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
175652. BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
175653. BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
175654. BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
175655. BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
175656. BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
175657. BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
175658. BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
175659. BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
175660. BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
175661. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
175662. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
175663. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
175664. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
175665. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
175666. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
175667. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
175668. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
175669. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
175670. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
175671. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
175672. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
175673. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
175674. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
175675. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
175676. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
175677. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
175678. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
175679. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
175680. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
175681. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
175682. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
175683. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
175684. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
175685. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
175686. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
175687. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
175688. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
175689. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
175690. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
175691. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
175692. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
175693. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
175694. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
175695. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
175696. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
175697. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
175698. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
175699. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
175700. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
175701. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
175702. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
175703. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
175704. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
175705. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
175706. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
175707. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
175708. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
175709. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
175710. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
175711. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
175712. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
175713. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
175714. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
175715. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
175716. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
175717. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
175718. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
175719. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
175720. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
175721. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
175722. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
175723. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
175724. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
175725. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
175726. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
175727. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
175728. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
175729. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
175730. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
175731. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
175732. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
175733. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
175734. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
175735. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
175736. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
175737. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
175738. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
175739. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
175740. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
175741. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
175742. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
175743. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
175744. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
175745. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
175746. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
175747. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
175748. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
175749. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
175750. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
175751. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
175752. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
175753. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
175754. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
175755. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
175756. BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
175757. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
175758. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
175759. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
175760. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
175761. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
175762. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
175763. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
175764. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
175765. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
175766. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
175767. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
175768. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
175769. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
175770. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
175771. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
175772. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
175773. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
175774. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
175775. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
175776. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
175777. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
175778. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
175779. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
175780. BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
175781. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
175782. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
175783. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
175784. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
175785. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
175786. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
175787. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
175788. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
175789. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
175790. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
175791. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
175792. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
175793. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
175794. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
175795. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
175796. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
175797. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
175798. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
175799. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
175800. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
175801. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
175802. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
175803. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
175804. BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
175805. BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
175806. BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
175807. BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
175808. BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
175809. BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
175810. BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
175811. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
175812. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
175813. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
175814. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
175815. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
175816. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
175817. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
175818. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
175819. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
175820. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
175821. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
175822. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
175823. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
175824. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
175825. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
175826. BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
175827. BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID_MASK
175828. BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID__SHIFT
175829. BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR_MASK
175830. BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT
175831. BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT_MASK
175832. BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT__SHIFT
175833. BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT_MASK
175834. BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT__SHIFT
175835. BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT_MASK
175836. BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT__SHIFT
175837. BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
175838. BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
175839. BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK_MASK
175840. BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK__SHIFT
175841. BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT_MASK
175842. BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT__SHIFT
175843. BIF_CFG_DEV1_RC0_PMI_CAP__VERSION_MASK
175844. BIF_CFG_DEV1_RC0_PMI_CAP__VERSION__SHIFT
175845. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
175846. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
175847. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
175848. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
175849. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK
175850. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
175851. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK
175852. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
175853. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
175854. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
175855. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN_MASK
175856. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT
175857. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK
175858. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
175859. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK
175860. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
175861. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK
175862. BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
175863. BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
175864. BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
175865. BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
175866. BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
175867. BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
175868. BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
175869. BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
175870. BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
175871. BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
175872. BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
175873. BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
175874. BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
175875. BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK
175876. BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
175877. BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID_MASK
175878. BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT
175879. BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID_MASK
175880. BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID__SHIFT
175881. BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
175882. BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
175883. BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
175884. BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
175885. BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK
175886. BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
175887. BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
175888. BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
175889. BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
175890. BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
175891. BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
175892. BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
175893. BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING_MASK
175894. BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING__SHIFT
175895. BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK
175896. BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
175897. BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS_MASK
175898. BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS__SHIFT
175899. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__CAP_LIST_MASK
175900. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__CAP_LIST__SHIFT
175901. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK
175902. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
175903. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
175904. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
175905. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
175906. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
175907. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
175908. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
175909. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_EN_MASK
175910. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_EN__SHIFT
175911. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
175912. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
175913. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
175914. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
175915. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
175916. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
175917. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
175918. BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
175919. BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED_MASK
175920. BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED__SHIFT
175921. BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
175922. BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
175923. BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
175924. BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
175925. BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
175926. BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
175927. BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK
175928. BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
175929. BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK
175930. BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
175931. BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
175932. BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
175933. BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
175934. BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
175935. BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
175936. BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
175937. BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
175938. BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
175939. BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
175940. BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
175941. BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
175942. BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
175943. BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
175944. BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
175945. BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED_MASK
175946. BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED__SHIFT
175947. BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
175948. BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
175949. BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
175950. BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
175951. BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
175952. BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
175953. BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
175954. BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
175955. BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
175956. BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
175957. BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
175958. BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
175959. BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
175960. BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
175961. BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
175962. BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
175963. BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
175964. BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
175965. BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
175966. BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
175967. BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
175968. BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
175969. BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED_MASK
175970. BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED__SHIFT
175971. BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
175972. BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
175973. BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK
175974. BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
175975. BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK
175976. BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
175977. BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
175978. BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
175979. BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
175980. BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
175981. BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK
175982. BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
175983. BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
175984. BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
175985. BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
175986. BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
175987. BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
175988. BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
175989. BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID_MASK
175990. BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID__SHIFT
175991. BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR_MASK
175992. BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT
175993. BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID_MASK
175994. BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT
175995. BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
175996. BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
175997. BIF_CFG_DEV1_RC0_STATUS__CAP_LIST_MASK
175998. BIF_CFG_DEV1_RC0_STATUS__CAP_LIST__SHIFT
175999. BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING_MASK
176000. BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING__SHIFT
176001. BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE_MASK
176002. BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT
176003. BIF_CFG_DEV1_RC0_STATUS__INT_STATUS_MASK
176004. BIF_CFG_DEV1_RC0_STATUS__INT_STATUS__SHIFT
176005. BIF_CFG_DEV1_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
176006. BIF_CFG_DEV1_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
176007. BIF_CFG_DEV1_RC0_STATUS__PARITY_ERROR_DETECTED_MASK
176008. BIF_CFG_DEV1_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT
176009. BIF_CFG_DEV1_RC0_STATUS__PCI_66_EN_MASK
176010. BIF_CFG_DEV1_RC0_STATUS__PCI_66_EN__SHIFT
176011. BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK
176012. BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
176013. BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK
176014. BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
176015. BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
176016. BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
176017. BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK
176018. BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
176019. BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
176020. BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
176021. BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
176022. BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
176023. BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
176024. BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
176025. BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
176026. BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
176027. BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS_MASK
176028. BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS__SHIFT
176029. BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID_MASK
176030. BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID__SHIFT
176031. BIF_CFG_DEV1_RC1_BASE_ADDR_1__BASE_ADDR_MASK
176032. BIF_CFG_DEV1_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT
176033. BIF_CFG_DEV1_RC1_BASE_CLASS__BASE_CLASS_MASK
176034. BIF_CFG_DEV1_RC1_BASE_CLASS__BASE_CLASS__SHIFT
176035. BIF_CFG_DEV1_RC1_BIST__BIST_CAP_MASK
176036. BIF_CFG_DEV1_RC1_BIST__BIST_CAP__SHIFT
176037. BIF_CFG_DEV1_RC1_BIST__BIST_COMP_MASK
176038. BIF_CFG_DEV1_RC1_BIST__BIST_COMP__SHIFT
176039. BIF_CFG_DEV1_RC1_BIST__BIST_STRT_MASK
176040. BIF_CFG_DEV1_RC1_BIST__BIST_STRT__SHIFT
176041. BIF_CFG_DEV1_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK
176042. BIF_CFG_DEV1_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
176043. BIF_CFG_DEV1_RC1_CAP_PTR__CAP_PTR_MASK
176044. BIF_CFG_DEV1_RC1_CAP_PTR__CAP_PTR__SHIFT
176045. BIF_CFG_DEV1_RC1_COMMAND__AD_STEPPING_MASK
176046. BIF_CFG_DEV1_RC1_COMMAND__AD_STEPPING__SHIFT
176047. BIF_CFG_DEV1_RC1_COMMAND__BUS_MASTER_EN_MASK
176048. BIF_CFG_DEV1_RC1_COMMAND__BUS_MASTER_EN__SHIFT
176049. BIF_CFG_DEV1_RC1_COMMAND__FAST_B2B_EN_MASK
176050. BIF_CFG_DEV1_RC1_COMMAND__FAST_B2B_EN__SHIFT
176051. BIF_CFG_DEV1_RC1_COMMAND__INT_DIS_MASK
176052. BIF_CFG_DEV1_RC1_COMMAND__INT_DIS__SHIFT
176053. BIF_CFG_DEV1_RC1_COMMAND__IOEN_DN_MASK
176054. BIF_CFG_DEV1_RC1_COMMAND__IOEN_DN__SHIFT
176055. BIF_CFG_DEV1_RC1_COMMAND__MEMEN_DN_MASK
176056. BIF_CFG_DEV1_RC1_COMMAND__MEMEN_DN__SHIFT
176057. BIF_CFG_DEV1_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
176058. BIF_CFG_DEV1_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
176059. BIF_CFG_DEV1_RC1_COMMAND__PAL_SNOOP_EN_MASK
176060. BIF_CFG_DEV1_RC1_COMMAND__PAL_SNOOP_EN__SHIFT
176061. BIF_CFG_DEV1_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK
176062. BIF_CFG_DEV1_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
176063. BIF_CFG_DEV1_RC1_COMMAND__SERR_EN_MASK
176064. BIF_CFG_DEV1_RC1_COMMAND__SERR_EN__SHIFT
176065. BIF_CFG_DEV1_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK
176066. BIF_CFG_DEV1_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
176067. BIF_CFG_DEV1_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
176068. BIF_CFG_DEV1_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
176069. BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
176070. BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
176071. BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
176072. BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
176073. BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
176074. BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
176075. BIF_CFG_DEV1_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
176076. BIF_CFG_DEV1_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
176077. BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
176078. BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
176079. BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
176080. BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
176081. BIF_CFG_DEV1_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
176082. BIF_CFG_DEV1_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
176083. BIF_CFG_DEV1_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
176084. BIF_CFG_DEV1_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
176085. BIF_CFG_DEV1_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK
176086. BIF_CFG_DEV1_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
176087. BIF_CFG_DEV1_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
176088. BIF_CFG_DEV1_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
176089. BIF_CFG_DEV1_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
176090. BIF_CFG_DEV1_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
176091. BIF_CFG_DEV1_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
176092. BIF_CFG_DEV1_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
176093. BIF_CFG_DEV1_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
176094. BIF_CFG_DEV1_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
176095. BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
176096. BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
176097. BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
176098. BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
176099. BIF_CFG_DEV1_RC1_DEVICE_CAP__EXTENDED_TAG_MASK
176100. BIF_CFG_DEV1_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT
176101. BIF_CFG_DEV1_RC1_DEVICE_CAP__FLR_CAPABLE_MASK
176102. BIF_CFG_DEV1_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT
176103. BIF_CFG_DEV1_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
176104. BIF_CFG_DEV1_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
176105. BIF_CFG_DEV1_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
176106. BIF_CFG_DEV1_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
176107. BIF_CFG_DEV1_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
176108. BIF_CFG_DEV1_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
176109. BIF_CFG_DEV1_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK
176110. BIF_CFG_DEV1_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
176111. BIF_CFG_DEV1_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
176112. BIF_CFG_DEV1_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
176113. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
176114. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
176115. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
176116. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
176117. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
176118. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
176119. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
176120. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
176121. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
176122. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
176123. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
176124. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
176125. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
176126. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
176127. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
176128. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
176129. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__LTR_EN_MASK
176130. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__LTR_EN__SHIFT
176131. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__OBFF_EN_MASK
176132. BIF_CFG_DEV1_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT
176133. BIF_CFG_DEV1_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
176134. BIF_CFG_DEV1_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
176135. BIF_CFG_DEV1_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
176136. BIF_CFG_DEV1_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
176137. BIF_CFG_DEV1_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK
176138. BIF_CFG_DEV1_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
176139. BIF_CFG_DEV1_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
176140. BIF_CFG_DEV1_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
176141. BIF_CFG_DEV1_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK
176142. BIF_CFG_DEV1_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
176143. BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
176144. BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
176145. BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
176146. BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
176147. BIF_CFG_DEV1_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
176148. BIF_CFG_DEV1_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
176149. BIF_CFG_DEV1_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK
176150. BIF_CFG_DEV1_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
176151. BIF_CFG_DEV1_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
176152. BIF_CFG_DEV1_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
176153. BIF_CFG_DEV1_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
176154. BIF_CFG_DEV1_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
176155. BIF_CFG_DEV1_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK
176156. BIF_CFG_DEV1_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
176157. BIF_CFG_DEV1_RC1_DEVICE_ID__DEVICE_ID_MASK
176158. BIF_CFG_DEV1_RC1_DEVICE_ID__DEVICE_ID__SHIFT
176159. BIF_CFG_DEV1_RC1_DEVICE_STATUS2__RESERVED_MASK
176160. BIF_CFG_DEV1_RC1_DEVICE_STATUS2__RESERVED__SHIFT
176161. BIF_CFG_DEV1_RC1_DEVICE_STATUS__AUX_PWR_MASK
176162. BIF_CFG_DEV1_RC1_DEVICE_STATUS__AUX_PWR__SHIFT
176163. BIF_CFG_DEV1_RC1_DEVICE_STATUS__CORR_ERR_MASK
176164. BIF_CFG_DEV1_RC1_DEVICE_STATUS__CORR_ERR__SHIFT
176165. BIF_CFG_DEV1_RC1_DEVICE_STATUS__FATAL_ERR_MASK
176166. BIF_CFG_DEV1_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT
176167. BIF_CFG_DEV1_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK
176168. BIF_CFG_DEV1_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
176169. BIF_CFG_DEV1_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
176170. BIF_CFG_DEV1_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
176171. BIF_CFG_DEV1_RC1_DEVICE_STATUS__USR_DETECTED_MASK
176172. BIF_CFG_DEV1_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT
176173. BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
176174. BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
176175. BIF_CFG_DEV1_RC1_HEADER__DEVICE_TYPE_MASK
176176. BIF_CFG_DEV1_RC1_HEADER__DEVICE_TYPE__SHIFT
176177. BIF_CFG_DEV1_RC1_HEADER__HEADER_TYPE_MASK
176178. BIF_CFG_DEV1_RC1_HEADER__HEADER_TYPE__SHIFT
176179. BIF_CFG_DEV1_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
176180. BIF_CFG_DEV1_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
176181. BIF_CFG_DEV1_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
176182. BIF_CFG_DEV1_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
176183. BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
176184. BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
176185. BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
176186. BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
176187. BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_MASK
176188. BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
176189. BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
176190. BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT
176191. BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK
176192. BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
176193. BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
176194. BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT
176195. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
176196. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
176197. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK
176198. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
176199. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
176200. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
176201. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
176202. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
176203. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
176204. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
176205. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK
176206. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
176207. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
176208. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
176209. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK
176210. BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
176211. BIF_CFG_DEV1_RC1_LATENCY__LATENCY_TIMER_MASK
176212. BIF_CFG_DEV1_RC1_LATENCY__LATENCY_TIMER__SHIFT
176213. BIF_CFG_DEV1_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
176214. BIF_CFG_DEV1_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
176215. BIF_CFG_DEV1_RC1_LINK_CAP2__RESERVED_MASK
176216. BIF_CFG_DEV1_RC1_LINK_CAP2__RESERVED__SHIFT
176217. BIF_CFG_DEV1_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
176218. BIF_CFG_DEV1_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
176219. BIF_CFG_DEV1_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
176220. BIF_CFG_DEV1_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
176221. BIF_CFG_DEV1_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
176222. BIF_CFG_DEV1_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
176223. BIF_CFG_DEV1_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
176224. BIF_CFG_DEV1_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
176225. BIF_CFG_DEV1_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK
176226. BIF_CFG_DEV1_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
176227. BIF_CFG_DEV1_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK
176228. BIF_CFG_DEV1_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
176229. BIF_CFG_DEV1_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
176230. BIF_CFG_DEV1_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
176231. BIF_CFG_DEV1_RC1_LINK_CAP__LINK_SPEED_MASK
176232. BIF_CFG_DEV1_RC1_LINK_CAP__LINK_SPEED__SHIFT
176233. BIF_CFG_DEV1_RC1_LINK_CAP__LINK_WIDTH_MASK
176234. BIF_CFG_DEV1_RC1_LINK_CAP__LINK_WIDTH__SHIFT
176235. BIF_CFG_DEV1_RC1_LINK_CAP__PM_SUPPORT_MASK
176236. BIF_CFG_DEV1_RC1_LINK_CAP__PM_SUPPORT__SHIFT
176237. BIF_CFG_DEV1_RC1_LINK_CAP__PORT_NUMBER_MASK
176238. BIF_CFG_DEV1_RC1_LINK_CAP__PORT_NUMBER__SHIFT
176239. BIF_CFG_DEV1_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
176240. BIF_CFG_DEV1_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
176241. BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
176242. BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
176243. BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK
176244. BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
176245. BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
176246. BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
176247. BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
176248. BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
176249. BIF_CFG_DEV1_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
176250. BIF_CFG_DEV1_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
176251. BIF_CFG_DEV1_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
176252. BIF_CFG_DEV1_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
176253. BIF_CFG_DEV1_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
176254. BIF_CFG_DEV1_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
176255. BIF_CFG_DEV1_RC1_LINK_CNTL2__XMIT_MARGIN_MASK
176256. BIF_CFG_DEV1_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT
176257. BIF_CFG_DEV1_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
176258. BIF_CFG_DEV1_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
176259. BIF_CFG_DEV1_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
176260. BIF_CFG_DEV1_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
176261. BIF_CFG_DEV1_RC1_LINK_CNTL__EXTENDED_SYNC_MASK
176262. BIF_CFG_DEV1_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT
176263. BIF_CFG_DEV1_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
176264. BIF_CFG_DEV1_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
176265. BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
176266. BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
176267. BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
176268. BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
176269. BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_DIS_MASK
176270. BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_DIS__SHIFT
176271. BIF_CFG_DEV1_RC1_LINK_CNTL__PM_CONTROL_MASK
176272. BIF_CFG_DEV1_RC1_LINK_CNTL__PM_CONTROL__SHIFT
176273. BIF_CFG_DEV1_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
176274. BIF_CFG_DEV1_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
176275. BIF_CFG_DEV1_RC1_LINK_CNTL__RETRAIN_LINK_MASK
176276. BIF_CFG_DEV1_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT
176277. BIF_CFG_DEV1_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
176278. BIF_CFG_DEV1_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
176279. BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
176280. BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
176281. BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
176282. BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
176283. BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
176284. BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
176285. BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
176286. BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
176287. BIF_CFG_DEV1_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
176288. BIF_CFG_DEV1_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
176289. BIF_CFG_DEV1_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
176290. BIF_CFG_DEV1_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
176291. BIF_CFG_DEV1_RC1_LINK_STATUS__DL_ACTIVE_MASK
176292. BIF_CFG_DEV1_RC1_LINK_STATUS__DL_ACTIVE__SHIFT
176293. BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
176294. BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
176295. BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
176296. BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
176297. BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_TRAINING_MASK
176298. BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_TRAINING__SHIFT
176299. BIF_CFG_DEV1_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
176300. BIF_CFG_DEV1_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
176301. BIF_CFG_DEV1_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
176302. BIF_CFG_DEV1_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
176303. BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
176304. BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
176305. BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
176306. BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
176307. BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
176308. BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
176309. BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
176310. BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
176311. BIF_CFG_DEV1_RC1_MSI_CAP_LIST__CAP_ID_MASK
176312. BIF_CFG_DEV1_RC1_MSI_CAP_LIST__CAP_ID__SHIFT
176313. BIF_CFG_DEV1_RC1_MSI_CAP_LIST__NEXT_PTR_MASK
176314. BIF_CFG_DEV1_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT
176315. BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
176316. BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
176317. BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
176318. BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
176319. BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK
176320. BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
176321. BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
176322. BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
176323. BIF_CFG_DEV1_RC1_MSI_MAP_CAP__CAP_TYPE_MASK
176324. BIF_CFG_DEV1_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT
176325. BIF_CFG_DEV1_RC1_MSI_MAP_CAP__EN_MASK
176326. BIF_CFG_DEV1_RC1_MSI_MAP_CAP__EN__SHIFT
176327. BIF_CFG_DEV1_RC1_MSI_MAP_CAP__FIXD_MASK
176328. BIF_CFG_DEV1_RC1_MSI_MAP_CAP__FIXD__SHIFT
176329. BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
176330. BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
176331. BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
176332. BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
176333. BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK
176334. BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
176335. BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EN_MASK
176336. BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT
176337. BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
176338. BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
176339. BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
176340. BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
176341. BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
176342. BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
176343. BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
176344. BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
176345. BIF_CFG_DEV1_RC1_MSI_MSG_DATA__MSI_DATA_MASK
176346. BIF_CFG_DEV1_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT
176347. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
176348. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
176349. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
176350. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
176351. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
176352. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
176353. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
176354. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
176355. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
176356. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
176357. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
176358. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
176359. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
176360. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
176361. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
176362. BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
176363. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
176364. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
176365. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
176366. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
176367. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
176368. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
176369. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
176370. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
176371. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
176372. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
176373. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
176374. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
176375. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
176376. BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
176377. BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
176378. BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
176379. BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
176380. BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
176381. BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
176382. BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
176383. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
176384. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
176385. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
176386. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
176387. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
176388. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
176389. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
176390. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
176391. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
176392. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
176393. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
176394. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
176395. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
176396. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
176397. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
176398. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
176399. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
176400. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
176401. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
176402. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
176403. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
176404. BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
176405. BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__CAP_ID_MASK
176406. BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT
176407. BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK
176408. BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
176409. BIF_CFG_DEV1_RC1_PCIE_CAP__DEVICE_TYPE_MASK
176410. BIF_CFG_DEV1_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT
176411. BIF_CFG_DEV1_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK
176412. BIF_CFG_DEV1_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
176413. BIF_CFG_DEV1_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
176414. BIF_CFG_DEV1_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
176415. BIF_CFG_DEV1_RC1_PCIE_CAP__VERSION_MASK
176416. BIF_CFG_DEV1_RC1_PCIE_CAP__VERSION__SHIFT
176417. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
176418. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
176419. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
176420. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
176421. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
176422. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
176423. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
176424. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
176425. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
176426. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
176427. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
176428. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
176429. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
176430. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
176431. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
176432. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
176433. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
176434. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
176435. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
176436. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
176437. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
176438. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
176439. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
176440. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
176441. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
176442. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
176443. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
176444. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
176445. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
176446. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
176447. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
176448. BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
176449. BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
176450. BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
176451. BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
176452. BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
176453. BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
176454. BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
176455. BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
176456. BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
176457. BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
176458. BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
176459. BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
176460. BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
176461. BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
176462. BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
176463. BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK
176464. BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
176465. BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK
176466. BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
176467. BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK
176468. BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
176469. BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK
176470. BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
176471. BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176472. BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176473. BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176474. BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176475. BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
176476. BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
176477. BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176478. BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176479. BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176480. BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176481. BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176482. BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176483. BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176484. BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176485. BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
176486. BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
176487. BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176488. BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176489. BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176490. BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176491. BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176492. BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176493. BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176494. BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176495. BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
176496. BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
176497. BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176498. BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176499. BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176500. BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176501. BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176502. BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176503. BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176504. BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176505. BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
176506. BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
176507. BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176508. BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176509. BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176510. BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176511. BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176512. BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176513. BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176514. BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176515. BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
176516. BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
176517. BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176518. BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176519. BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176520. BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176521. BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176522. BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176523. BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176524. BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176525. BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
176526. BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
176527. BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176528. BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176529. BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176530. BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176531. BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176532. BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176533. BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176534. BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176535. BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
176536. BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
176537. BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176538. BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176539. BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176540. BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176541. BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176542. BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176543. BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176544. BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176545. BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
176546. BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
176547. BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176548. BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176549. BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176550. BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176551. BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176552. BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176553. BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176554. BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176555. BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
176556. BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
176557. BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176558. BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176559. BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176560. BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176561. BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176562. BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176563. BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176564. BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176565. BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
176566. BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
176567. BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176568. BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176569. BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176570. BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176571. BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176572. BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176573. BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176574. BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176575. BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
176576. BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
176577. BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176578. BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176579. BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176580. BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176581. BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176582. BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176583. BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176584. BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176585. BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
176586. BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
176587. BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176588. BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176589. BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176590. BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176591. BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176592. BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176593. BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176594. BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176595. BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
176596. BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
176597. BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176598. BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176599. BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176600. BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176601. BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176602. BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176603. BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176604. BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176605. BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
176606. BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
176607. BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176608. BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176609. BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176610. BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176611. BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176612. BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176613. BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176614. BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176615. BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
176616. BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
176617. BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176618. BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176619. BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176620. BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176621. BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
176622. BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
176623. BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
176624. BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
176625. BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
176626. BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
176627. BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
176628. BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
176629. BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
176630. BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
176631. BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
176632. BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
176633. BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
176634. BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
176635. BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
176636. BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
176637. BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
176638. BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
176639. BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__RESERVED_MASK
176640. BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__RESERVED__SHIFT
176641. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
176642. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
176643. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
176644. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
176645. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
176646. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
176647. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
176648. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
176649. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
176650. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
176651. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
176652. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
176653. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
176654. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
176655. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
176656. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
176657. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
176658. BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
176659. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
176660. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
176661. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
176662. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
176663. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
176664. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
176665. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
176666. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
176667. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
176668. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
176669. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
176670. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
176671. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
176672. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
176673. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
176674. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
176675. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
176676. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
176677. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
176678. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
176679. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
176680. BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
176681. BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
176682. BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
176683. BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
176684. BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
176685. BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
176686. BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
176687. BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
176688. BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
176689. BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
176690. BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
176691. BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
176692. BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
176693. BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
176694. BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
176695. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
176696. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
176697. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
176698. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
176699. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
176700. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
176701. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
176702. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
176703. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
176704. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
176705. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
176706. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
176707. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
176708. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
176709. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
176710. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
176711. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
176712. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
176713. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
176714. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
176715. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
176716. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
176717. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
176718. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
176719. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
176720. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
176721. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
176722. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
176723. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
176724. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
176725. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
176726. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
176727. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
176728. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
176729. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
176730. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
176731. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
176732. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
176733. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
176734. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
176735. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
176736. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
176737. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
176738. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
176739. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
176740. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
176741. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
176742. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
176743. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
176744. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
176745. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
176746. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
176747. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
176748. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
176749. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
176750. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
176751. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
176752. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
176753. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
176754. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
176755. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
176756. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
176757. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
176758. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
176759. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
176760. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
176761. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
176762. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
176763. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
176764. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
176765. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
176766. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
176767. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
176768. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
176769. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
176770. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
176771. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
176772. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
176773. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
176774. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
176775. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
176776. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
176777. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
176778. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
176779. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
176780. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
176781. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
176782. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
176783. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
176784. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
176785. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
176786. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
176787. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
176788. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
176789. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
176790. BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
176791. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
176792. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
176793. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
176794. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
176795. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
176796. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
176797. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
176798. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
176799. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
176800. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
176801. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
176802. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
176803. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
176804. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
176805. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
176806. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
176807. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
176808. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
176809. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
176810. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
176811. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
176812. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
176813. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
176814. BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
176815. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
176816. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
176817. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
176818. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
176819. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
176820. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
176821. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
176822. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
176823. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
176824. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
176825. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
176826. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
176827. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
176828. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
176829. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
176830. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
176831. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
176832. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
176833. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
176834. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
176835. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
176836. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
176837. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
176838. BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
176839. BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
176840. BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
176841. BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
176842. BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
176843. BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
176844. BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
176845. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
176846. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
176847. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
176848. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
176849. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
176850. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
176851. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
176852. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
176853. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
176854. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
176855. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
176856. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
176857. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
176858. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
176859. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
176860. BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
176861. BIF_CFG_DEV1_RC1_PMI_CAP_LIST__CAP_ID_MASK
176862. BIF_CFG_DEV1_RC1_PMI_CAP_LIST__CAP_ID__SHIFT
176863. BIF_CFG_DEV1_RC1_PMI_CAP_LIST__NEXT_PTR_MASK
176864. BIF_CFG_DEV1_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT
176865. BIF_CFG_DEV1_RC1_PMI_CAP__AUX_CURRENT_MASK
176866. BIF_CFG_DEV1_RC1_PMI_CAP__AUX_CURRENT__SHIFT
176867. BIF_CFG_DEV1_RC1_PMI_CAP__D1_SUPPORT_MASK
176868. BIF_CFG_DEV1_RC1_PMI_CAP__D1_SUPPORT__SHIFT
176869. BIF_CFG_DEV1_RC1_PMI_CAP__D2_SUPPORT_MASK
176870. BIF_CFG_DEV1_RC1_PMI_CAP__D2_SUPPORT__SHIFT
176871. BIF_CFG_DEV1_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
176872. BIF_CFG_DEV1_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
176873. BIF_CFG_DEV1_RC1_PMI_CAP__PME_CLOCK_MASK
176874. BIF_CFG_DEV1_RC1_PMI_CAP__PME_CLOCK__SHIFT
176875. BIF_CFG_DEV1_RC1_PMI_CAP__PME_SUPPORT_MASK
176876. BIF_CFG_DEV1_RC1_PMI_CAP__PME_SUPPORT__SHIFT
176877. BIF_CFG_DEV1_RC1_PMI_CAP__VERSION_MASK
176878. BIF_CFG_DEV1_RC1_PMI_CAP__VERSION__SHIFT
176879. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
176880. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
176881. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
176882. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
176883. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK
176884. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
176885. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK
176886. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
176887. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
176888. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
176889. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_EN_MASK
176890. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT
176891. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK
176892. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
176893. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK
176894. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
176895. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK
176896. BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
176897. BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
176898. BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
176899. BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
176900. BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
176901. BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
176902. BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
176903. BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
176904. BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
176905. BIF_CFG_DEV1_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
176906. BIF_CFG_DEV1_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
176907. BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
176908. BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
176909. BIF_CFG_DEV1_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK
176910. BIF_CFG_DEV1_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
176911. BIF_CFG_DEV1_RC1_REVISION_ID__MAJOR_REV_ID_MASK
176912. BIF_CFG_DEV1_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT
176913. BIF_CFG_DEV1_RC1_REVISION_ID__MINOR_REV_ID_MASK
176914. BIF_CFG_DEV1_RC1_REVISION_ID__MINOR_REV_ID__SHIFT
176915. BIF_CFG_DEV1_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
176916. BIF_CFG_DEV1_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
176917. BIF_CFG_DEV1_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
176918. BIF_CFG_DEV1_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
176919. BIF_CFG_DEV1_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK
176920. BIF_CFG_DEV1_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
176921. BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
176922. BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
176923. BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
176924. BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
176925. BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
176926. BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
176927. BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_PENDING_MASK
176928. BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_PENDING__SHIFT
176929. BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK
176930. BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
176931. BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_STATUS_MASK
176932. BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_STATUS__SHIFT
176933. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__CAP_LIST_MASK
176934. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__CAP_LIST__SHIFT
176935. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK
176936. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
176937. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
176938. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
176939. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
176940. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
176941. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
176942. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
176943. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PCI_66_EN_MASK
176944. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PCI_66_EN__SHIFT
176945. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
176946. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
176947. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
176948. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
176949. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
176950. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
176951. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
176952. BIF_CFG_DEV1_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
176953. BIF_CFG_DEV1_RC1_SLOT_CAP2__RESERVED_MASK
176954. BIF_CFG_DEV1_RC1_SLOT_CAP2__RESERVED__SHIFT
176955. BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
176956. BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
176957. BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
176958. BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
176959. BIF_CFG_DEV1_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
176960. BIF_CFG_DEV1_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
176961. BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK
176962. BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
176963. BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK
176964. BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
176965. BIF_CFG_DEV1_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
176966. BIF_CFG_DEV1_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
176967. BIF_CFG_DEV1_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
176968. BIF_CFG_DEV1_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
176969. BIF_CFG_DEV1_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
176970. BIF_CFG_DEV1_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
176971. BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
176972. BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
176973. BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
176974. BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
176975. BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
176976. BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
176977. BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
176978. BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
176979. BIF_CFG_DEV1_RC1_SLOT_CNTL2__RESERVED_MASK
176980. BIF_CFG_DEV1_RC1_SLOT_CNTL2__RESERVED__SHIFT
176981. BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
176982. BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
176983. BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
176984. BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
176985. BIF_CFG_DEV1_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
176986. BIF_CFG_DEV1_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
176987. BIF_CFG_DEV1_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
176988. BIF_CFG_DEV1_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
176989. BIF_CFG_DEV1_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
176990. BIF_CFG_DEV1_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
176991. BIF_CFG_DEV1_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
176992. BIF_CFG_DEV1_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
176993. BIF_CFG_DEV1_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
176994. BIF_CFG_DEV1_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
176995. BIF_CFG_DEV1_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
176996. BIF_CFG_DEV1_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
176997. BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
176998. BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
176999. BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
177000. BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
177001. BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
177002. BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
177003. BIF_CFG_DEV1_RC1_SLOT_STATUS2__RESERVED_MASK
177004. BIF_CFG_DEV1_RC1_SLOT_STATUS2__RESERVED__SHIFT
177005. BIF_CFG_DEV1_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
177006. BIF_CFG_DEV1_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
177007. BIF_CFG_DEV1_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK
177008. BIF_CFG_DEV1_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
177009. BIF_CFG_DEV1_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK
177010. BIF_CFG_DEV1_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
177011. BIF_CFG_DEV1_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
177012. BIF_CFG_DEV1_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
177013. BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
177014. BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
177015. BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK
177016. BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
177017. BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
177018. BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
177019. BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
177020. BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
177021. BIF_CFG_DEV1_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
177022. BIF_CFG_DEV1_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
177023. BIF_CFG_DEV1_RC1_SSID_CAP_LIST__CAP_ID_MASK
177024. BIF_CFG_DEV1_RC1_SSID_CAP_LIST__CAP_ID__SHIFT
177025. BIF_CFG_DEV1_RC1_SSID_CAP_LIST__NEXT_PTR_MASK
177026. BIF_CFG_DEV1_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT
177027. BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_ID_MASK
177028. BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT
177029. BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
177030. BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
177031. BIF_CFG_DEV1_RC1_STATUS__CAP_LIST_MASK
177032. BIF_CFG_DEV1_RC1_STATUS__CAP_LIST__SHIFT
177033. BIF_CFG_DEV1_RC1_STATUS__DEVSEL_TIMING_MASK
177034. BIF_CFG_DEV1_RC1_STATUS__DEVSEL_TIMING__SHIFT
177035. BIF_CFG_DEV1_RC1_STATUS__FAST_BACK_CAPABLE_MASK
177036. BIF_CFG_DEV1_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT
177037. BIF_CFG_DEV1_RC1_STATUS__INT_STATUS_MASK
177038. BIF_CFG_DEV1_RC1_STATUS__INT_STATUS__SHIFT
177039. BIF_CFG_DEV1_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
177040. BIF_CFG_DEV1_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
177041. BIF_CFG_DEV1_RC1_STATUS__PARITY_ERROR_DETECTED_MASK
177042. BIF_CFG_DEV1_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT
177043. BIF_CFG_DEV1_RC1_STATUS__PCI_66_EN_MASK
177044. BIF_CFG_DEV1_RC1_STATUS__PCI_66_EN__SHIFT
177045. BIF_CFG_DEV1_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK
177046. BIF_CFG_DEV1_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
177047. BIF_CFG_DEV1_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK
177048. BIF_CFG_DEV1_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
177049. BIF_CFG_DEV1_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
177050. BIF_CFG_DEV1_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
177051. BIF_CFG_DEV1_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK
177052. BIF_CFG_DEV1_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
177053. BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
177054. BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
177055. BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
177056. BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
177057. BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
177058. BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
177059. BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
177060. BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
177061. BIF_CFG_DEV1_RC1_SUB_CLASS__SUB_CLASS_MASK
177062. BIF_CFG_DEV1_RC1_SUB_CLASS__SUB_CLASS__SHIFT
177063. BIF_CFG_DEV1_RC1_VENDOR_ID__VENDOR_ID_MASK
177064. BIF_CFG_DEV1_RC1_VENDOR_ID__VENDOR_ID__SHIFT
177065. BIF_CFG_DEV1_RC2_BASE_ADDR_1__BASE_ADDR_MASK
177066. BIF_CFG_DEV1_RC2_BASE_ADDR_1__BASE_ADDR__SHIFT
177067. BIF_CFG_DEV1_RC2_BASE_CLASS__BASE_CLASS_MASK
177068. BIF_CFG_DEV1_RC2_BASE_CLASS__BASE_CLASS__SHIFT
177069. BIF_CFG_DEV1_RC2_BIST__BIST_CAP_MASK
177070. BIF_CFG_DEV1_RC2_BIST__BIST_CAP__SHIFT
177071. BIF_CFG_DEV1_RC2_BIST__BIST_COMP_MASK
177072. BIF_CFG_DEV1_RC2_BIST__BIST_COMP__SHIFT
177073. BIF_CFG_DEV1_RC2_BIST__BIST_STRT_MASK
177074. BIF_CFG_DEV1_RC2_BIST__BIST_STRT__SHIFT
177075. BIF_CFG_DEV1_RC2_CACHE_LINE__CACHE_LINE_SIZE_MASK
177076. BIF_CFG_DEV1_RC2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
177077. BIF_CFG_DEV1_RC2_CAP_PTR__CAP_PTR_MASK
177078. BIF_CFG_DEV1_RC2_CAP_PTR__CAP_PTR__SHIFT
177079. BIF_CFG_DEV1_RC2_COMMAND__AD_STEPPING_MASK
177080. BIF_CFG_DEV1_RC2_COMMAND__AD_STEPPING__SHIFT
177081. BIF_CFG_DEV1_RC2_COMMAND__BUS_MASTER_EN_MASK
177082. BIF_CFG_DEV1_RC2_COMMAND__BUS_MASTER_EN__SHIFT
177083. BIF_CFG_DEV1_RC2_COMMAND__FAST_B2B_EN_MASK
177084. BIF_CFG_DEV1_RC2_COMMAND__FAST_B2B_EN__SHIFT
177085. BIF_CFG_DEV1_RC2_COMMAND__INT_DIS_MASK
177086. BIF_CFG_DEV1_RC2_COMMAND__INT_DIS__SHIFT
177087. BIF_CFG_DEV1_RC2_COMMAND__IOEN_DN_MASK
177088. BIF_CFG_DEV1_RC2_COMMAND__IOEN_DN__SHIFT
177089. BIF_CFG_DEV1_RC2_COMMAND__MEMEN_DN_MASK
177090. BIF_CFG_DEV1_RC2_COMMAND__MEMEN_DN__SHIFT
177091. BIF_CFG_DEV1_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
177092. BIF_CFG_DEV1_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
177093. BIF_CFG_DEV1_RC2_COMMAND__PAL_SNOOP_EN_MASK
177094. BIF_CFG_DEV1_RC2_COMMAND__PAL_SNOOP_EN__SHIFT
177095. BIF_CFG_DEV1_RC2_COMMAND__PARITY_ERROR_RESPONSE_MASK
177096. BIF_CFG_DEV1_RC2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
177097. BIF_CFG_DEV1_RC2_COMMAND__SERR_EN_MASK
177098. BIF_CFG_DEV1_RC2_COMMAND__SERR_EN__SHIFT
177099. BIF_CFG_DEV1_RC2_COMMAND__SPECIAL_CYCLE_EN_MASK
177100. BIF_CFG_DEV1_RC2_COMMAND__SPECIAL_CYCLE_EN__SHIFT
177101. BIF_CFG_DEV1_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
177102. BIF_CFG_DEV1_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
177103. BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
177104. BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
177105. BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
177106. BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
177107. BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
177108. BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
177109. BIF_CFG_DEV1_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
177110. BIF_CFG_DEV1_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
177111. BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
177112. BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
177113. BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
177114. BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
177115. BIF_CFG_DEV1_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
177116. BIF_CFG_DEV1_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
177117. BIF_CFG_DEV1_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
177118. BIF_CFG_DEV1_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
177119. BIF_CFG_DEV1_RC2_DEVICE_CAP2__LTR_SUPPORTED_MASK
177120. BIF_CFG_DEV1_RC2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
177121. BIF_CFG_DEV1_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
177122. BIF_CFG_DEV1_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
177123. BIF_CFG_DEV1_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
177124. BIF_CFG_DEV1_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
177125. BIF_CFG_DEV1_RC2_DEVICE_CAP2__OBFF_SUPPORTED_MASK
177126. BIF_CFG_DEV1_RC2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
177127. BIF_CFG_DEV1_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
177128. BIF_CFG_DEV1_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
177129. BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
177130. BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
177131. BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
177132. BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
177133. BIF_CFG_DEV1_RC2_DEVICE_CAP__EXTENDED_TAG_MASK
177134. BIF_CFG_DEV1_RC2_DEVICE_CAP__EXTENDED_TAG__SHIFT
177135. BIF_CFG_DEV1_RC2_DEVICE_CAP__FLR_CAPABLE_MASK
177136. BIF_CFG_DEV1_RC2_DEVICE_CAP__FLR_CAPABLE__SHIFT
177137. BIF_CFG_DEV1_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
177138. BIF_CFG_DEV1_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
177139. BIF_CFG_DEV1_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
177140. BIF_CFG_DEV1_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
177141. BIF_CFG_DEV1_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
177142. BIF_CFG_DEV1_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
177143. BIF_CFG_DEV1_RC2_DEVICE_CAP__PHANTOM_FUNC_MASK
177144. BIF_CFG_DEV1_RC2_DEVICE_CAP__PHANTOM_FUNC__SHIFT
177145. BIF_CFG_DEV1_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
177146. BIF_CFG_DEV1_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
177147. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
177148. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
177149. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
177150. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
177151. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
177152. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
177153. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
177154. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
177155. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
177156. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
177157. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
177158. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
177159. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
177160. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
177161. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
177162. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
177163. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__LTR_EN_MASK
177164. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__LTR_EN__SHIFT
177165. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__OBFF_EN_MASK
177166. BIF_CFG_DEV1_RC2_DEVICE_CNTL2__OBFF_EN__SHIFT
177167. BIF_CFG_DEV1_RC2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
177168. BIF_CFG_DEV1_RC2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
177169. BIF_CFG_DEV1_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
177170. BIF_CFG_DEV1_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
177171. BIF_CFG_DEV1_RC2_DEVICE_CNTL__CORR_ERR_EN_MASK
177172. BIF_CFG_DEV1_RC2_DEVICE_CNTL__CORR_ERR_EN__SHIFT
177173. BIF_CFG_DEV1_RC2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
177174. BIF_CFG_DEV1_RC2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
177175. BIF_CFG_DEV1_RC2_DEVICE_CNTL__FATAL_ERR_EN_MASK
177176. BIF_CFG_DEV1_RC2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
177177. BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
177178. BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
177179. BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
177180. BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
177181. BIF_CFG_DEV1_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
177182. BIF_CFG_DEV1_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
177183. BIF_CFG_DEV1_RC2_DEVICE_CNTL__NO_SNOOP_EN_MASK
177184. BIF_CFG_DEV1_RC2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
177185. BIF_CFG_DEV1_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
177186. BIF_CFG_DEV1_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
177187. BIF_CFG_DEV1_RC2_DEVICE_CNTL__RELAXED_ORD_EN_MASK
177188. BIF_CFG_DEV1_RC2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
177189. BIF_CFG_DEV1_RC2_DEVICE_CNTL__USR_REPORT_EN_MASK
177190. BIF_CFG_DEV1_RC2_DEVICE_CNTL__USR_REPORT_EN__SHIFT
177191. BIF_CFG_DEV1_RC2_DEVICE_ID__DEVICE_ID_MASK
177192. BIF_CFG_DEV1_RC2_DEVICE_ID__DEVICE_ID__SHIFT
177193. BIF_CFG_DEV1_RC2_DEVICE_STATUS2__RESERVED_MASK
177194. BIF_CFG_DEV1_RC2_DEVICE_STATUS2__RESERVED__SHIFT
177195. BIF_CFG_DEV1_RC2_DEVICE_STATUS__AUX_PWR_MASK
177196. BIF_CFG_DEV1_RC2_DEVICE_STATUS__AUX_PWR__SHIFT
177197. BIF_CFG_DEV1_RC2_DEVICE_STATUS__CORR_ERR_MASK
177198. BIF_CFG_DEV1_RC2_DEVICE_STATUS__CORR_ERR__SHIFT
177199. BIF_CFG_DEV1_RC2_DEVICE_STATUS__FATAL_ERR_MASK
177200. BIF_CFG_DEV1_RC2_DEVICE_STATUS__FATAL_ERR__SHIFT
177201. BIF_CFG_DEV1_RC2_DEVICE_STATUS__NON_FATAL_ERR_MASK
177202. BIF_CFG_DEV1_RC2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
177203. BIF_CFG_DEV1_RC2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
177204. BIF_CFG_DEV1_RC2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
177205. BIF_CFG_DEV1_RC2_DEVICE_STATUS__USR_DETECTED_MASK
177206. BIF_CFG_DEV1_RC2_DEVICE_STATUS__USR_DETECTED__SHIFT
177207. BIF_CFG_DEV1_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
177208. BIF_CFG_DEV1_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
177209. BIF_CFG_DEV1_RC2_HEADER__DEVICE_TYPE_MASK
177210. BIF_CFG_DEV1_RC2_HEADER__DEVICE_TYPE__SHIFT
177211. BIF_CFG_DEV1_RC2_HEADER__HEADER_TYPE_MASK
177212. BIF_CFG_DEV1_RC2_HEADER__HEADER_TYPE__SHIFT
177213. BIF_CFG_DEV1_RC2_INTERRUPT_LINE__INTERRUPT_LINE_MASK
177214. BIF_CFG_DEV1_RC2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
177215. BIF_CFG_DEV1_RC2_INTERRUPT_PIN__INTERRUPT_PIN_MASK
177216. BIF_CFG_DEV1_RC2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
177217. BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
177218. BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
177219. BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
177220. BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
177221. BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE_MASK
177222. BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
177223. BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
177224. BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE__SHIFT
177225. BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT_MASK
177226. BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
177227. BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
177228. BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT__SHIFT
177229. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
177230. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
177231. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__ISA_EN_MASK
177232. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
177233. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
177234. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
177235. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
177236. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
177237. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
177238. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
177239. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SERR_EN_MASK
177240. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
177241. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
177242. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
177243. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_EN_MASK
177244. BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
177245. BIF_CFG_DEV1_RC2_LATENCY__LATENCY_TIMER_MASK
177246. BIF_CFG_DEV1_RC2_LATENCY__LATENCY_TIMER__SHIFT
177247. BIF_CFG_DEV1_RC2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
177248. BIF_CFG_DEV1_RC2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
177249. BIF_CFG_DEV1_RC2_LINK_CAP2__RESERVED_MASK
177250. BIF_CFG_DEV1_RC2_LINK_CAP2__RESERVED__SHIFT
177251. BIF_CFG_DEV1_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
177252. BIF_CFG_DEV1_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
177253. BIF_CFG_DEV1_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
177254. BIF_CFG_DEV1_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
177255. BIF_CFG_DEV1_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
177256. BIF_CFG_DEV1_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
177257. BIF_CFG_DEV1_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
177258. BIF_CFG_DEV1_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
177259. BIF_CFG_DEV1_RC2_LINK_CAP__L0S_EXIT_LATENCY_MASK
177260. BIF_CFG_DEV1_RC2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
177261. BIF_CFG_DEV1_RC2_LINK_CAP__L1_EXIT_LATENCY_MASK
177262. BIF_CFG_DEV1_RC2_LINK_CAP__L1_EXIT_LATENCY__SHIFT
177263. BIF_CFG_DEV1_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
177264. BIF_CFG_DEV1_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
177265. BIF_CFG_DEV1_RC2_LINK_CAP__LINK_SPEED_MASK
177266. BIF_CFG_DEV1_RC2_LINK_CAP__LINK_SPEED__SHIFT
177267. BIF_CFG_DEV1_RC2_LINK_CAP__LINK_WIDTH_MASK
177268. BIF_CFG_DEV1_RC2_LINK_CAP__LINK_WIDTH__SHIFT
177269. BIF_CFG_DEV1_RC2_LINK_CAP__PM_SUPPORT_MASK
177270. BIF_CFG_DEV1_RC2_LINK_CAP__PM_SUPPORT__SHIFT
177271. BIF_CFG_DEV1_RC2_LINK_CAP__PORT_NUMBER_MASK
177272. BIF_CFG_DEV1_RC2_LINK_CAP__PORT_NUMBER__SHIFT
177273. BIF_CFG_DEV1_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
177274. BIF_CFG_DEV1_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
177275. BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
177276. BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
177277. BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_SOS_MASK
177278. BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
177279. BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_COMPLIANCE_MASK
177280. BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
177281. BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
177282. BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
177283. BIF_CFG_DEV1_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
177284. BIF_CFG_DEV1_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
177285. BIF_CFG_DEV1_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
177286. BIF_CFG_DEV1_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
177287. BIF_CFG_DEV1_RC2_LINK_CNTL2__TARGET_LINK_SPEED_MASK
177288. BIF_CFG_DEV1_RC2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
177289. BIF_CFG_DEV1_RC2_LINK_CNTL2__XMIT_MARGIN_MASK
177290. BIF_CFG_DEV1_RC2_LINK_CNTL2__XMIT_MARGIN__SHIFT
177291. BIF_CFG_DEV1_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
177292. BIF_CFG_DEV1_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
177293. BIF_CFG_DEV1_RC2_LINK_CNTL__COMMON_CLOCK_CFG_MASK
177294. BIF_CFG_DEV1_RC2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
177295. BIF_CFG_DEV1_RC2_LINK_CNTL__EXTENDED_SYNC_MASK
177296. BIF_CFG_DEV1_RC2_LINK_CNTL__EXTENDED_SYNC__SHIFT
177297. BIF_CFG_DEV1_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
177298. BIF_CFG_DEV1_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
177299. BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
177300. BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
177301. BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
177302. BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
177303. BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_DIS_MASK
177304. BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_DIS__SHIFT
177305. BIF_CFG_DEV1_RC2_LINK_CNTL__PM_CONTROL_MASK
177306. BIF_CFG_DEV1_RC2_LINK_CNTL__PM_CONTROL__SHIFT
177307. BIF_CFG_DEV1_RC2_LINK_CNTL__READ_CPL_BOUNDARY_MASK
177308. BIF_CFG_DEV1_RC2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
177309. BIF_CFG_DEV1_RC2_LINK_CNTL__RETRAIN_LINK_MASK
177310. BIF_CFG_DEV1_RC2_LINK_CNTL__RETRAIN_LINK__SHIFT
177311. BIF_CFG_DEV1_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
177312. BIF_CFG_DEV1_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
177313. BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
177314. BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
177315. BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
177316. BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
177317. BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
177318. BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
177319. BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
177320. BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
177321. BIF_CFG_DEV1_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
177322. BIF_CFG_DEV1_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
177323. BIF_CFG_DEV1_RC2_LINK_STATUS__CURRENT_LINK_SPEED_MASK
177324. BIF_CFG_DEV1_RC2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
177325. BIF_CFG_DEV1_RC2_LINK_STATUS__DL_ACTIVE_MASK
177326. BIF_CFG_DEV1_RC2_LINK_STATUS__DL_ACTIVE__SHIFT
177327. BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
177328. BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
177329. BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
177330. BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
177331. BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_TRAINING_MASK
177332. BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_TRAINING__SHIFT
177333. BIF_CFG_DEV1_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
177334. BIF_CFG_DEV1_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
177335. BIF_CFG_DEV1_RC2_LINK_STATUS__SLOT_CLOCK_CFG_MASK
177336. BIF_CFG_DEV1_RC2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
177337. BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
177338. BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
177339. BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
177340. BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
177341. BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
177342. BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
177343. BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
177344. BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
177345. BIF_CFG_DEV1_RC2_MSI_CAP_LIST__CAP_ID_MASK
177346. BIF_CFG_DEV1_RC2_MSI_CAP_LIST__CAP_ID__SHIFT
177347. BIF_CFG_DEV1_RC2_MSI_CAP_LIST__NEXT_PTR_MASK
177348. BIF_CFG_DEV1_RC2_MSI_CAP_LIST__NEXT_PTR__SHIFT
177349. BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK
177350. BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT
177351. BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK
177352. BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT
177353. BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__CAP_ID_MASK
177354. BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
177355. BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
177356. BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
177357. BIF_CFG_DEV1_RC2_MSI_MAP_CAP__CAP_TYPE_MASK
177358. BIF_CFG_DEV1_RC2_MSI_MAP_CAP__CAP_TYPE__SHIFT
177359. BIF_CFG_DEV1_RC2_MSI_MAP_CAP__EN_MASK
177360. BIF_CFG_DEV1_RC2_MSI_MAP_CAP__EN__SHIFT
177361. BIF_CFG_DEV1_RC2_MSI_MAP_CAP__FIXD_MASK
177362. BIF_CFG_DEV1_RC2_MSI_MAP_CAP__FIXD__SHIFT
177363. BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
177364. BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
177365. BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
177366. BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
177367. BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_64BIT_MASK
177368. BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_64BIT__SHIFT
177369. BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_EN_MASK
177370. BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_EN__SHIFT
177371. BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
177372. BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
177373. BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
177374. BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
177375. BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
177376. BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
177377. BIF_CFG_DEV1_RC2_MSI_MSG_DATA_64__MSI_DATA_64_MASK
177378. BIF_CFG_DEV1_RC2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
177379. BIF_CFG_DEV1_RC2_MSI_MSG_DATA__MSI_DATA_MASK
177380. BIF_CFG_DEV1_RC2_MSI_MSG_DATA__MSI_DATA__SHIFT
177381. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
177382. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
177383. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
177384. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
177385. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
177386. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
177387. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
177388. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
177389. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
177390. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
177391. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
177392. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
177393. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
177394. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
177395. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
177396. BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
177397. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
177398. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
177399. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
177400. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
177401. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
177402. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
177403. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
177404. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
177405. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
177406. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
177407. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
177408. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
177409. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
177410. BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
177411. BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
177412. BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
177413. BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
177414. BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
177415. BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
177416. BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
177417. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
177418. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
177419. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
177420. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
177421. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
177422. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
177423. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
177424. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
177425. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
177426. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
177427. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
177428. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
177429. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
177430. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
177431. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
177432. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
177433. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
177434. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
177435. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
177436. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
177437. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
177438. BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
177439. BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__CAP_ID_MASK
177440. BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__CAP_ID__SHIFT
177441. BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__NEXT_PTR_MASK
177442. BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__NEXT_PTR__SHIFT
177443. BIF_CFG_DEV1_RC2_PCIE_CAP__DEVICE_TYPE_MASK
177444. BIF_CFG_DEV1_RC2_PCIE_CAP__DEVICE_TYPE__SHIFT
177445. BIF_CFG_DEV1_RC2_PCIE_CAP__INT_MESSAGE_NUM_MASK
177446. BIF_CFG_DEV1_RC2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
177447. BIF_CFG_DEV1_RC2_PCIE_CAP__SLOT_IMPLEMENTED_MASK
177448. BIF_CFG_DEV1_RC2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
177449. BIF_CFG_DEV1_RC2_PCIE_CAP__VERSION_MASK
177450. BIF_CFG_DEV1_RC2_PCIE_CAP__VERSION__SHIFT
177451. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
177452. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
177453. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
177454. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
177455. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
177456. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
177457. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
177458. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
177459. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
177460. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
177461. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
177462. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
177463. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
177464. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
177465. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
177466. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
177467. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
177468. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
177469. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
177470. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
177471. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
177472. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
177473. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
177474. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
177475. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
177476. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
177477. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
177478. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
177479. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
177480. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
177481. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
177482. BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
177483. BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
177484. BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
177485. BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
177486. BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
177487. BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
177488. BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
177489. BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
177490. BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
177491. BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
177492. BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
177493. BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK
177494. BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
177495. BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK
177496. BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
177497. BIF_CFG_DEV1_RC2_PCIE_HDR_LOG0__TLP_HDR_MASK
177498. BIF_CFG_DEV1_RC2_PCIE_HDR_LOG0__TLP_HDR__SHIFT
177499. BIF_CFG_DEV1_RC2_PCIE_HDR_LOG1__TLP_HDR_MASK
177500. BIF_CFG_DEV1_RC2_PCIE_HDR_LOG1__TLP_HDR__SHIFT
177501. BIF_CFG_DEV1_RC2_PCIE_HDR_LOG2__TLP_HDR_MASK
177502. BIF_CFG_DEV1_RC2_PCIE_HDR_LOG2__TLP_HDR__SHIFT
177503. BIF_CFG_DEV1_RC2_PCIE_HDR_LOG3__TLP_HDR_MASK
177504. BIF_CFG_DEV1_RC2_PCIE_HDR_LOG3__TLP_HDR__SHIFT
177505. BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177506. BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177507. BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177508. BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177509. BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
177510. BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
177511. BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177512. BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177513. BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177514. BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177515. BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177516. BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177517. BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177518. BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177519. BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
177520. BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
177521. BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177522. BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177523. BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177524. BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177525. BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177526. BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177527. BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177528. BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177529. BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
177530. BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
177531. BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177532. BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177533. BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177534. BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177535. BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177536. BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177537. BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177538. BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177539. BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
177540. BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
177541. BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177542. BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177543. BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177544. BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177545. BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177546. BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177547. BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177548. BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177549. BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
177550. BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
177551. BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177552. BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177553. BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177554. BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177555. BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177556. BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177557. BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177558. BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177559. BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
177560. BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
177561. BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177562. BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177563. BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177564. BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177565. BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177566. BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177567. BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177568. BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177569. BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
177570. BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
177571. BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177572. BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177573. BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177574. BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177575. BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177576. BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177577. BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177578. BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177579. BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
177580. BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
177581. BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177582. BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177583. BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177584. BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177585. BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177586. BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177587. BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177588. BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177589. BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
177590. BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
177591. BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177592. BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177593. BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177594. BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177595. BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177596. BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177597. BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177598. BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177599. BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
177600. BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
177601. BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177602. BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177603. BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177604. BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177605. BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177606. BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177607. BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177608. BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177609. BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
177610. BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
177611. BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177612. BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177613. BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177614. BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177615. BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177616. BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177617. BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177618. BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177619. BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
177620. BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
177621. BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177622. BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177623. BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177624. BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177625. BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177626. BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177627. BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177628. BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177629. BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
177630. BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
177631. BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177632. BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177633. BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177634. BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177635. BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177636. BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177637. BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177638. BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177639. BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
177640. BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
177641. BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177642. BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177643. BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177644. BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177645. BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177646. BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177647. BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177648. BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177649. BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
177650. BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
177651. BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177652. BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177653. BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177654. BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177655. BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
177656. BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
177657. BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
177658. BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
177659. BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
177660. BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
177661. BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
177662. BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
177663. BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
177664. BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
177665. BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
177666. BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
177667. BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
177668. BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
177669. BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
177670. BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
177671. BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
177672. BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
177673. BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__RESERVED_MASK
177674. BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__RESERVED__SHIFT
177675. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
177676. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
177677. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
177678. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
177679. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
177680. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
177681. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
177682. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
177683. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
177684. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
177685. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
177686. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
177687. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
177688. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
177689. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
177690. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
177691. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
177692. BIF_CFG_DEV1_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
177693. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK
177694. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
177695. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK
177696. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
177697. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK
177698. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
177699. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK
177700. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
177701. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK
177702. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
177703. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK
177704. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
177705. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK
177706. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
177707. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK
177708. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
177709. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK
177710. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
177711. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK
177712. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
177713. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK
177714. BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
177715. BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
177716. BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
177717. BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
177718. BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
177719. BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
177720. BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
177721. BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
177722. BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
177723. BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
177724. BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
177725. BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
177726. BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
177727. BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
177728. BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
177729. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
177730. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
177731. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
177732. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
177733. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
177734. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
177735. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
177736. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
177737. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
177738. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
177739. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
177740. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
177741. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
177742. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
177743. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
177744. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
177745. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
177746. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
177747. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
177748. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
177749. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
177750. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
177751. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
177752. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
177753. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
177754. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
177755. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
177756. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
177757. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
177758. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
177759. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
177760. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
177761. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
177762. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
177763. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
177764. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
177765. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
177766. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
177767. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
177768. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
177769. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
177770. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
177771. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
177772. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
177773. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
177774. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
177775. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
177776. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
177777. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
177778. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
177779. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
177780. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
177781. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
177782. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
177783. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
177784. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
177785. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
177786. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
177787. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
177788. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
177789. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
177790. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
177791. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
177792. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
177793. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
177794. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
177795. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
177796. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
177797. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
177798. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
177799. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
177800. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
177801. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
177802. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
177803. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
177804. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
177805. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
177806. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
177807. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
177808. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
177809. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
177810. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
177811. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
177812. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
177813. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
177814. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
177815. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
177816. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
177817. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
177818. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
177819. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
177820. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
177821. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
177822. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
177823. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
177824. BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
177825. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
177826. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
177827. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
177828. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
177829. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
177830. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
177831. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
177832. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
177833. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
177834. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
177835. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
177836. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
177837. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
177838. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
177839. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
177840. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
177841. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
177842. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
177843. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
177844. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
177845. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
177846. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
177847. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
177848. BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
177849. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
177850. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
177851. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
177852. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
177853. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
177854. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
177855. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
177856. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
177857. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
177858. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
177859. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
177860. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
177861. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
177862. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
177863. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
177864. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
177865. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
177866. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
177867. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
177868. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
177869. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
177870. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
177871. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
177872. BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
177873. BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
177874. BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
177875. BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
177876. BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
177877. BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
177878. BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
177879. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
177880. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
177881. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
177882. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
177883. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
177884. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
177885. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
177886. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
177887. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
177888. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
177889. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
177890. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
177891. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
177892. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
177893. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
177894. BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
177895. BIF_CFG_DEV1_RC2_PMI_CAP_LIST__CAP_ID_MASK
177896. BIF_CFG_DEV1_RC2_PMI_CAP_LIST__CAP_ID__SHIFT
177897. BIF_CFG_DEV1_RC2_PMI_CAP_LIST__NEXT_PTR_MASK
177898. BIF_CFG_DEV1_RC2_PMI_CAP_LIST__NEXT_PTR__SHIFT
177899. BIF_CFG_DEV1_RC2_PMI_CAP__AUX_CURRENT_MASK
177900. BIF_CFG_DEV1_RC2_PMI_CAP__AUX_CURRENT__SHIFT
177901. BIF_CFG_DEV1_RC2_PMI_CAP__D1_SUPPORT_MASK
177902. BIF_CFG_DEV1_RC2_PMI_CAP__D1_SUPPORT__SHIFT
177903. BIF_CFG_DEV1_RC2_PMI_CAP__D2_SUPPORT_MASK
177904. BIF_CFG_DEV1_RC2_PMI_CAP__D2_SUPPORT__SHIFT
177905. BIF_CFG_DEV1_RC2_PMI_CAP__DEV_SPECIFIC_INIT_MASK
177906. BIF_CFG_DEV1_RC2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
177907. BIF_CFG_DEV1_RC2_PMI_CAP__PME_CLOCK_MASK
177908. BIF_CFG_DEV1_RC2_PMI_CAP__PME_CLOCK__SHIFT
177909. BIF_CFG_DEV1_RC2_PMI_CAP__PME_SUPPORT_MASK
177910. BIF_CFG_DEV1_RC2_PMI_CAP__PME_SUPPORT__SHIFT
177911. BIF_CFG_DEV1_RC2_PMI_CAP__VERSION_MASK
177912. BIF_CFG_DEV1_RC2_PMI_CAP__VERSION__SHIFT
177913. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
177914. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
177915. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
177916. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
177917. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SCALE_MASK
177918. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
177919. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SELECT_MASK
177920. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
177921. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
177922. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
177923. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_EN_MASK
177924. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_EN__SHIFT
177925. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_STATUS_MASK
177926. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_STATUS__SHIFT
177927. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PMI_DATA_MASK
177928. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PMI_DATA__SHIFT
177929. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__POWER_STATE_MASK
177930. BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__POWER_STATE__SHIFT
177931. BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
177932. BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
177933. BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
177934. BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
177935. BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
177936. BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
177937. BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
177938. BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
177939. BIF_CFG_DEV1_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
177940. BIF_CFG_DEV1_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
177941. BIF_CFG_DEV1_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
177942. BIF_CFG_DEV1_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
177943. BIF_CFG_DEV1_RC2_PROG_INTERFACE__PROG_INTERFACE_MASK
177944. BIF_CFG_DEV1_RC2_PROG_INTERFACE__PROG_INTERFACE__SHIFT
177945. BIF_CFG_DEV1_RC2_REVISION_ID__MAJOR_REV_ID_MASK
177946. BIF_CFG_DEV1_RC2_REVISION_ID__MAJOR_REV_ID__SHIFT
177947. BIF_CFG_DEV1_RC2_REVISION_ID__MINOR_REV_ID_MASK
177948. BIF_CFG_DEV1_RC2_REVISION_ID__MINOR_REV_ID__SHIFT
177949. BIF_CFG_DEV1_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK
177950. BIF_CFG_DEV1_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT
177951. BIF_CFG_DEV1_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK
177952. BIF_CFG_DEV1_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT
177953. BIF_CFG_DEV1_RC2_ROOT_CNTL__PM_INTERRUPT_EN_MASK
177954. BIF_CFG_DEV1_RC2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT
177955. BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK
177956. BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT
177957. BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK
177958. BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT
177959. BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK
177960. BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT
177961. BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_PENDING_MASK
177962. BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_PENDING__SHIFT
177963. BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_REQUESTOR_ID_MASK
177964. BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT
177965. BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_STATUS_MASK
177966. BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_STATUS__SHIFT
177967. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__CAP_LIST_MASK
177968. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__CAP_LIST__SHIFT
177969. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__DEVSEL_TIMING_MASK
177970. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
177971. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
177972. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
177973. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
177974. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
177975. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
177976. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
177977. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PCI_66_EN_MASK
177978. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PCI_66_EN__SHIFT
177979. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
177980. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
177981. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
177982. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
177983. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
177984. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
177985. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
177986. BIF_CFG_DEV1_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
177987. BIF_CFG_DEV1_RC2_SLOT_CAP2__RESERVED_MASK
177988. BIF_CFG_DEV1_RC2_SLOT_CAP2__RESERVED__SHIFT
177989. BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK
177990. BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT
177991. BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK
177992. BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT
177993. BIF_CFG_DEV1_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK
177994. BIF_CFG_DEV1_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT
177995. BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_CAPABLE_MASK
177996. BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT
177997. BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_SURPRISE_MASK
177998. BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT
177999. BIF_CFG_DEV1_RC2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK
178000. BIF_CFG_DEV1_RC2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT
178001. BIF_CFG_DEV1_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK
178002. BIF_CFG_DEV1_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT
178003. BIF_CFG_DEV1_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK
178004. BIF_CFG_DEV1_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT
178005. BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK
178006. BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT
178007. BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK
178008. BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT
178009. BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK
178010. BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT
178011. BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK
178012. BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT
178013. BIF_CFG_DEV1_RC2_SLOT_CNTL2__RESERVED_MASK
178014. BIF_CFG_DEV1_RC2_SLOT_CNTL2__RESERVED__SHIFT
178015. BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK
178016. BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT
178017. BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK
178018. BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT
178019. BIF_CFG_DEV1_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK
178020. BIF_CFG_DEV1_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT
178021. BIF_CFG_DEV1_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK
178022. BIF_CFG_DEV1_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT
178023. BIF_CFG_DEV1_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK
178024. BIF_CFG_DEV1_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT
178025. BIF_CFG_DEV1_RC2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK
178026. BIF_CFG_DEV1_RC2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT
178027. BIF_CFG_DEV1_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK
178028. BIF_CFG_DEV1_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT
178029. BIF_CFG_DEV1_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK
178030. BIF_CFG_DEV1_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT
178031. BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK
178032. BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT
178033. BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK
178034. BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT
178035. BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK
178036. BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT
178037. BIF_CFG_DEV1_RC2_SLOT_STATUS2__RESERVED_MASK
178038. BIF_CFG_DEV1_RC2_SLOT_STATUS2__RESERVED__SHIFT
178039. BIF_CFG_DEV1_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK
178040. BIF_CFG_DEV1_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT
178041. BIF_CFG_DEV1_RC2_SLOT_STATUS__COMMAND_COMPLETED_MASK
178042. BIF_CFG_DEV1_RC2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT
178043. BIF_CFG_DEV1_RC2_SLOT_STATUS__DL_STATE_CHANGED_MASK
178044. BIF_CFG_DEV1_RC2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT
178045. BIF_CFG_DEV1_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK
178046. BIF_CFG_DEV1_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT
178047. BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK
178048. BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT
178049. BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_STATE_MASK
178050. BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT
178051. BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK
178052. BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT
178053. BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK
178054. BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT
178055. BIF_CFG_DEV1_RC2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK
178056. BIF_CFG_DEV1_RC2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT
178057. BIF_CFG_DEV1_RC2_SSID_CAP_LIST__CAP_ID_MASK
178058. BIF_CFG_DEV1_RC2_SSID_CAP_LIST__CAP_ID__SHIFT
178059. BIF_CFG_DEV1_RC2_SSID_CAP_LIST__NEXT_PTR_MASK
178060. BIF_CFG_DEV1_RC2_SSID_CAP_LIST__NEXT_PTR__SHIFT
178061. BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_ID_MASK
178062. BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_ID__SHIFT
178063. BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
178064. BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
178065. BIF_CFG_DEV1_RC2_STATUS__CAP_LIST_MASK
178066. BIF_CFG_DEV1_RC2_STATUS__CAP_LIST__SHIFT
178067. BIF_CFG_DEV1_RC2_STATUS__DEVSEL_TIMING_MASK
178068. BIF_CFG_DEV1_RC2_STATUS__DEVSEL_TIMING__SHIFT
178069. BIF_CFG_DEV1_RC2_STATUS__FAST_BACK_CAPABLE_MASK
178070. BIF_CFG_DEV1_RC2_STATUS__FAST_BACK_CAPABLE__SHIFT
178071. BIF_CFG_DEV1_RC2_STATUS__INT_STATUS_MASK
178072. BIF_CFG_DEV1_RC2_STATUS__INT_STATUS__SHIFT
178073. BIF_CFG_DEV1_RC2_STATUS__MASTER_DATA_PARITY_ERROR_MASK
178074. BIF_CFG_DEV1_RC2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
178075. BIF_CFG_DEV1_RC2_STATUS__PARITY_ERROR_DETECTED_MASK
178076. BIF_CFG_DEV1_RC2_STATUS__PARITY_ERROR_DETECTED__SHIFT
178077. BIF_CFG_DEV1_RC2_STATUS__PCI_66_EN_MASK
178078. BIF_CFG_DEV1_RC2_STATUS__PCI_66_EN__SHIFT
178079. BIF_CFG_DEV1_RC2_STATUS__RECEIVED_MASTER_ABORT_MASK
178080. BIF_CFG_DEV1_RC2_STATUS__RECEIVED_MASTER_ABORT__SHIFT
178081. BIF_CFG_DEV1_RC2_STATUS__RECEIVED_TARGET_ABORT_MASK
178082. BIF_CFG_DEV1_RC2_STATUS__RECEIVED_TARGET_ABORT__SHIFT
178083. BIF_CFG_DEV1_RC2_STATUS__SIGNALED_SYSTEM_ERROR_MASK
178084. BIF_CFG_DEV1_RC2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
178085. BIF_CFG_DEV1_RC2_STATUS__SIGNAL_TARGET_ABORT_MASK
178086. BIF_CFG_DEV1_RC2_STATUS__SIGNAL_TARGET_ABORT__SHIFT
178087. BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
178088. BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
178089. BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
178090. BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
178091. BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
178092. BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
178093. BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
178094. BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
178095. BIF_CFG_DEV1_RC2_SUB_CLASS__SUB_CLASS_MASK
178096. BIF_CFG_DEV1_RC2_SUB_CLASS__SUB_CLASS__SHIFT
178097. BIF_CFG_DEV1_RC2_VENDOR_ID__VENDOR_ID_MASK
178098. BIF_CFG_DEV1_RC2_VENDOR_ID__VENDOR_ID__SHIFT
178099. BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK
178100. BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__MASK
178101. BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT
178102. BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS_MASK
178103. BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__MASK
178104. BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT
178105. BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK
178106. BIF_CLK_CTRL__BIF_XSTCLK_READY__MASK
178107. BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT
178108. BIF_CLK_PDWN_DELAY_TIMER_IND__TIMER_MASK
178109. BIF_CLK_PDWN_DELAY_TIMER_IND__TIMER__SHIFT
178110. BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK
178111. BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT
178112. BIF_CLOCKS_BITS_IND__OBFF_XSL_FORCE_REFCLK_MASK
178113. BIF_CLOCKS_BITS_IND__OBFF_XSL_FORCE_REFCLK__SHIFT
178114. BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK_MASK
178115. BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK__SHIFT
178116. BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK
178117. BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__MASK
178118. BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT
178119. BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK
178120. BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__MASK
178121. BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT
178122. BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK
178123. BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__MASK
178124. BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT
178125. BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK
178126. BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__MASK
178127. BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT
178128. BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK
178129. BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__MASK
178130. BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT
178131. BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK
178132. BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__MASK
178133. BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT
178134. BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK
178135. BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__MASK
178136. BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT
178137. BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK_MASK
178138. BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__MASK
178139. BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT
178140. BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK_MASK
178141. BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK__SHIFT
178142. BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK_MASK
178143. BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK__SHIFT
178144. BIF_D3HOTD0_INTR_MASK__DEV1_PF2_D3HOTD0_INTR_MASK_MASK
178145. BIF_D3HOTD0_INTR_MASK__DEV1_PF2_D3HOTD0_INTR_MASK__SHIFT
178146. BIF_D3HOTD0_INTR_MASK__DEV1_PF3_D3HOTD0_INTR_MASK_MASK
178147. BIF_D3HOTD0_INTR_MASK__DEV1_PF3_D3HOTD0_INTR_MASK__SHIFT
178148. BIF_D3HOTD0_INTR_MASK__DEV1_PF4_D3HOTD0_INTR_MASK_MASK
178149. BIF_D3HOTD0_INTR_MASK__DEV1_PF4_D3HOTD0_INTR_MASK__SHIFT
178150. BIF_D3HOTD0_INTR_MASK__DEV1_PF5_D3HOTD0_INTR_MASK_MASK
178151. BIF_D3HOTD0_INTR_MASK__DEV1_PF5_D3HOTD0_INTR_MASK__SHIFT
178152. BIF_D3HOTD0_INTR_MASK__DEV1_PF6_D3HOTD0_INTR_MASK_MASK
178153. BIF_D3HOTD0_INTR_MASK__DEV1_PF6_D3HOTD0_INTR_MASK__SHIFT
178154. BIF_D3HOTD0_INTR_MASK__DEV1_PF7_D3HOTD0_INTR_MASK_MASK
178155. BIF_D3HOTD0_INTR_MASK__DEV1_PF7_D3HOTD0_INTR_MASK__SHIFT
178156. BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK
178157. BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__MASK
178158. BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT
178159. BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK
178160. BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__MASK
178161. BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT
178162. BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK
178163. BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__MASK
178164. BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT
178165. BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK
178166. BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__MASK
178167. BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT
178168. BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK
178169. BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__MASK
178170. BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT
178171. BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK
178172. BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__MASK
178173. BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT
178174. BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK
178175. BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__MASK
178176. BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT
178177. BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS_MASK
178178. BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__MASK
178179. BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT
178180. BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS_MASK
178181. BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS__SHIFT
178182. BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS_MASK
178183. BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS__SHIFT
178184. BIF_D3HOTD0_INTR_STS__DEV1_PF2_D3HOTD0_INTR_STS_MASK
178185. BIF_D3HOTD0_INTR_STS__DEV1_PF2_D3HOTD0_INTR_STS__SHIFT
178186. BIF_D3HOTD0_INTR_STS__DEV1_PF3_D3HOTD0_INTR_STS_MASK
178187. BIF_D3HOTD0_INTR_STS__DEV1_PF3_D3HOTD0_INTR_STS__SHIFT
178188. BIF_D3HOTD0_INTR_STS__DEV1_PF4_D3HOTD0_INTR_STS_MASK
178189. BIF_D3HOTD0_INTR_STS__DEV1_PF4_D3HOTD0_INTR_STS__SHIFT
178190. BIF_D3HOTD0_INTR_STS__DEV1_PF5_D3HOTD0_INTR_STS_MASK
178191. BIF_D3HOTD0_INTR_STS__DEV1_PF5_D3HOTD0_INTR_STS__SHIFT
178192. BIF_D3HOTD0_INTR_STS__DEV1_PF6_D3HOTD0_INTR_STS_MASK
178193. BIF_D3HOTD0_INTR_STS__DEV1_PF6_D3HOTD0_INTR_STS__SHIFT
178194. BIF_D3HOTD0_INTR_STS__DEV1_PF7_D3HOTD0_INTR_STS_MASK
178195. BIF_D3HOTD0_INTR_STS__DEV1_PF7_D3HOTD0_INTR_STS__SHIFT
178196. BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK1_MASK
178197. BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK1__SHIFT
178198. BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK2_MASK
178199. BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK2__SHIFT
178200. BIF_DEBUG_CNTL_IND__DEBUG_EN_MASK
178201. BIF_DEBUG_CNTL_IND__DEBUG_EN__SHIFT
178202. BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK1_MASK
178203. BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK1__SHIFT
178204. BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK2_MASK
178205. BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK2__SHIFT
178206. BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_XSP_MASK
178207. BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_XSP__SHIFT
178208. BIF_DEBUG_CNTL_IND__DEBUG_MULTIBLOCKEN_MASK
178209. BIF_DEBUG_CNTL_IND__DEBUG_MULTIBLOCKEN__SHIFT
178210. BIF_DEBUG_CNTL_IND__DEBUG_OUT_EN_MASK
178211. BIF_DEBUG_CNTL_IND__DEBUG_OUT_EN__SHIFT
178212. BIF_DEBUG_CNTL_IND__DEBUG_PAD_SEL_MASK
178213. BIF_DEBUG_CNTL_IND__DEBUG_PAD_SEL__SHIFT
178214. BIF_DEBUG_CNTL_IND__DEBUG_SWAP_MASK
178215. BIF_DEBUG_CNTL_IND__DEBUG_SWAP__SHIFT
178216. BIF_DEBUG_CNTL_IND__DEBUG_SYNC_CLKSEL_MASK
178217. BIF_DEBUG_CNTL_IND__DEBUG_SYNC_CLKSEL__SHIFT
178218. BIF_DEBUG_CNTL_IND__DEBUG_SYNC_EN_MASK
178219. BIF_DEBUG_CNTL_IND__DEBUG_SYNC_EN__SHIFT
178220. BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK
178221. BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT
178222. BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK
178223. BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT
178224. BIF_DEBUG_CNTL__DEBUG_EN_MASK
178225. BIF_DEBUG_CNTL__DEBUG_EN__SHIFT
178226. BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK
178227. BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT
178228. BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK
178229. BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT
178230. BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK
178231. BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT
178232. BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK
178233. BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT
178234. BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK
178235. BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT
178236. BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK
178237. BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT
178238. BIF_DEBUG_CNTL__DEBUG_SWAP_MASK
178239. BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT
178240. BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK
178241. BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT
178242. BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK
178243. BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT
178244. BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK1_MASK
178245. BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK1__SHIFT
178246. BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK2_MASK
178247. BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK2__SHIFT
178248. BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK
178249. BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT
178250. BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK
178251. BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT
178252. BIF_DEBUG_OUT_IND__DEBUG_OUTPUT_MASK
178253. BIF_DEBUG_OUT_IND__DEBUG_OUTPUT__SHIFT
178254. BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK
178255. BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT
178256. BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK
178257. BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__MASK
178258. BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT
178259. BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK
178260. BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__MASK
178261. BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT
178262. BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK
178263. BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__MASK
178264. BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT
178265. BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK
178266. BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__MASK
178267. BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT
178268. BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK
178269. BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__MASK
178270. BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT
178271. BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK
178272. BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__MASK
178273. BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT
178274. BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK
178275. BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__MASK
178276. BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT
178277. BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK
178278. BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__MASK
178279. BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT
178280. BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK
178281. BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__MASK
178282. BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT
178283. BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK
178284. BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__MASK
178285. BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT
178286. BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK
178287. BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__MASK
178288. BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT
178289. BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK
178290. BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__MASK
178291. BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT
178292. BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK
178293. BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__MASK
178294. BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT
178295. BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK
178296. BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__MASK
178297. BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT
178298. BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK
178299. BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__MASK
178300. BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT
178301. BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK
178302. BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__MASK
178303. BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT
178304. BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK
178305. BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__MASK
178306. BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT
178307. BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK
178308. BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__MASK
178309. BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT
178310. BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK
178311. BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__MASK
178312. BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT
178313. BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK
178314. BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__MASK
178315. BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT
178316. BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK
178317. BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__MASK
178318. BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT
178319. BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE_MASK
178320. BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__MASK
178321. BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT
178322. BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_MASK
178323. BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__MASK
178324. BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT
178325. BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE_MASK
178326. BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__MASK
178327. BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT
178328. BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE_MASK
178329. BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE__SHIFT
178330. BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET_MASK
178331. BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT
178332. BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE_MASK
178333. BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE__SHIFT
178334. BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE_MASK
178335. BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE__SHIFT
178336. BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET_MASK
178337. BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT
178338. BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE_MASK
178339. BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE__SHIFT
178340. BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_ACK_VALUE_MASK
178341. BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_ACK_VALUE__SHIFT
178342. BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_NEED_D3TOD0_RESET_MASK
178343. BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT
178344. BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_TGT_VALUE_MASK
178345. BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_TGT_VALUE__SHIFT
178346. BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_ACK_VALUE_MASK
178347. BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_ACK_VALUE__SHIFT
178348. BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_NEED_D3TOD0_RESET_MASK
178349. BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT
178350. BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_TGT_VALUE_MASK
178351. BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_TGT_VALUE__SHIFT
178352. BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_ACK_VALUE_MASK
178353. BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_ACK_VALUE__SHIFT
178354. BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_NEED_D3TOD0_RESET_MASK
178355. BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT
178356. BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_TGT_VALUE_MASK
178357. BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_TGT_VALUE__SHIFT
178358. BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_ACK_VALUE_MASK
178359. BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_ACK_VALUE__SHIFT
178360. BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_NEED_D3TOD0_RESET_MASK
178361. BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT
178362. BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_TGT_VALUE_MASK
178363. BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_TGT_VALUE__SHIFT
178364. BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_ACK_VALUE_MASK
178365. BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_ACK_VALUE__SHIFT
178366. BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_NEED_D3TOD0_RESET_MASK
178367. BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT
178368. BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_TGT_VALUE_MASK
178369. BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_TGT_VALUE__SHIFT
178370. BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_ACK_VALUE_MASK
178371. BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_ACK_VALUE__SHIFT
178372. BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_NEED_D3TOD0_RESET_MASK
178373. BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT
178374. BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_TGT_VALUE_MASK
178375. BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_TGT_VALUE__SHIFT
178376. BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID0_MASK
178377. BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID0__SHIFT
178378. BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID1_MASK
178379. BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID1__SHIFT
178380. BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID2_MASK
178381. BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID2__SHIFT
178382. BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID3_MASK
178383. BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID3__SHIFT
178384. BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK
178385. BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT
178386. BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK
178387. BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT
178388. BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK
178389. BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT
178390. BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK
178391. BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT
178392. BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID4_MASK
178393. BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID4__SHIFT
178394. BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID5_MASK
178395. BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID5__SHIFT
178396. BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID6_MASK
178397. BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID6__SHIFT
178398. BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID7_MASK
178399. BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID7__SHIFT
178400. BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK
178401. BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT
178402. BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK
178403. BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT
178404. BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK
178405. BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT
178406. BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK
178407. BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT
178408. BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK
178409. BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT
178410. BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK
178411. BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT
178412. BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK
178413. BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT
178414. BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK
178415. BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT
178416. BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
178417. BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
178418. BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_CLEAR_MASK
178419. BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_CLEAR__SHIFT
178420. BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_STATUS_MASK
178421. BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_STATUS__SHIFT
178422. BIF_DOORBELL_CNTL_IND__DOORBELL_MONITOR_EN_MASK
178423. BIF_DOORBELL_CNTL_IND__DOORBELL_MONITOR_EN__SHIFT
178424. BIF_DOORBELL_CNTL_IND__NON_CONSECUTIVE_BE_ZERO_DIS_MASK
178425. BIF_DOORBELL_CNTL_IND__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT
178426. BIF_DOORBELL_CNTL_IND__SELF_RING_DIS_MASK
178427. BIF_DOORBELL_CNTL_IND__SELF_RING_DIS__SHIFT
178428. BIF_DOORBELL_CNTL_IND__TRANS_CHECK_DIS_MASK
178429. BIF_DOORBELL_CNTL_IND__TRANS_CHECK_DIS__SHIFT
178430. BIF_DOORBELL_CNTL_IND__UNTRANS_LBACK_EN_MASK
178431. BIF_DOORBELL_CNTL_IND__UNTRANS_LBACK_EN__SHIFT
178432. BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK
178433. BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__MASK
178434. BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT
178435. BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK
178436. BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__MASK
178437. BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT
178438. BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK
178439. BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__MASK
178440. BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT
178441. BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK
178442. BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__MASK
178443. BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT
178444. BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK
178445. BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT
178446. BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS_MASK
178447. BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT
178448. BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK
178449. BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__MASK
178450. BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT
178451. BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK
178452. BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__MASK
178453. BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT
178454. BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK
178455. BIF_DOORBELL_CNTL__SELF_RING_DIS__MASK
178456. BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT
178457. BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK
178458. BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__MASK
178459. BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT
178460. BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK
178461. BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__MASK
178462. BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT
178463. BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ACV_ENABLE_MASK
178464. BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ACV_ENABLE__SHIFT
178465. BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK
178466. BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT
178467. BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK
178468. BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__MASK
178469. BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT
178470. BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK
178471. BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT
178472. BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK
178473. BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT
178474. BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK
178475. BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT
178476. BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_EN_MASK
178477. BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_EN__SHIFT
178478. BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_LOWER_MASK
178479. BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_LOWER__SHIFT
178480. BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK
178481. BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__MASK
178482. BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT
178483. BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK
178484. BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__MASK
178485. BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT
178486. BIF_DOORBELL_GBLAPER1_UPPER_IND__DOORBELL_GBLAPER1_UPPER_MASK
178487. BIF_DOORBELL_GBLAPER1_UPPER_IND__DOORBELL_GBLAPER1_UPPER__SHIFT
178488. BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK
178489. BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__MASK
178490. BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT
178491. BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_EN_MASK
178492. BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_EN__SHIFT
178493. BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_LOWER_MASK
178494. BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_LOWER__SHIFT
178495. BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK
178496. BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__MASK
178497. BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT
178498. BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK
178499. BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__MASK
178500. BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT
178501. BIF_DOORBELL_GBLAPER2_UPPER_IND__DOORBELL_GBLAPER2_UPPER_MASK
178502. BIF_DOORBELL_GBLAPER2_UPPER_IND__DOORBELL_GBLAPER2_UPPER__SHIFT
178503. BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK
178504. BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__MASK
178505. BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT
178506. BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK
178507. BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__MASK
178508. BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT
178509. BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK
178510. BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT
178511. BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK
178512. BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__MASK
178513. BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT
178514. BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK
178515. BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__MASK
178516. BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT
178517. BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK
178518. BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__MASK
178519. BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT
178520. BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK
178521. BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT
178522. BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK
178523. BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT
178524. BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK
178525. BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT
178526. BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK
178527. BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT
178528. BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK
178529. BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT
178530. BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK
178531. BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT
178532. BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK
178533. BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT
178534. BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK
178535. BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT
178536. BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK
178537. BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT
178538. BIF_FB_EN
178539. BIF_FB_EN_IND__FB_READ_EN_MASK
178540. BIF_FB_EN_IND__FB_READ_EN__SHIFT
178541. BIF_FB_EN_IND__FB_WRITE_EN_MASK
178542. BIF_FB_EN_IND__FB_WRITE_EN__SHIFT
178543. BIF_FB_EN__FB_READ_EN_MASK
178544. BIF_FB_EN__FB_READ_EN__MASK
178545. BIF_FB_EN__FB_READ_EN__SHIFT
178546. BIF_FB_EN__FB_WRITE_EN_MASK
178547. BIF_FB_EN__FB_WRITE_EN__MASK
178548. BIF_FB_EN__FB_WRITE_EN__SHIFT
178549. BIF_FEATURES_CONTROL_MISC_IND__ATC_PRG_RESP_PASID_UR_EN_MASK
178550. BIF_FEATURES_CONTROL_MISC_IND__ATC_PRG_RESP_PASID_UR_EN__SHIFT
178551. BIF_FEATURES_CONTROL_MISC_IND__AZ_BIF_REQ_ID_ROUTING_DIS_MASK
178552. BIF_FEATURES_CONTROL_MISC_IND__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT
178553. BIF_FEATURES_CONTROL_MISC_IND__BIF_MST_CPL_EP_DIS_MASK
178554. BIF_FEATURES_CONTROL_MISC_IND__BIF_MST_CPL_EP_DIS__SHIFT
178555. BIF_FEATURES_CONTROL_MISC_IND__BIF_RB_SET_OVERFLOW_EN_MASK
178556. BIF_FEATURES_CONTROL_MISC_IND__BIF_RB_SET_OVERFLOW_EN__SHIFT
178557. BIF_FEATURES_CONTROL_MISC_IND__BIF_SLV_REQ_EP_DIS_MASK
178558. BIF_FEATURES_CONTROL_MISC_IND__BIF_SLV_REQ_EP_DIS__SHIFT
178559. BIF_FEATURES_CONTROL_MISC_IND__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK
178560. BIF_FEATURES_CONTROL_MISC_IND__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT
178561. BIF_FEATURES_CONTROL_MISC_IND__MC_BIF_REQ_ID_ROUTING_DIS_MASK
178562. BIF_FEATURES_CONTROL_MISC_IND__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT
178563. BIF_FEATURES_CONTROL_MISC_IND__MST_BIF_REQ_EP_DIS_MASK
178564. BIF_FEATURES_CONTROL_MISC_IND__MST_BIF_REQ_EP_DIS__SHIFT
178565. BIF_FEATURES_CONTROL_MISC_IND__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK
178566. BIF_FEATURES_CONTROL_MISC_IND__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT
178567. BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK
178568. BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT
178569. BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK
178570. BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT
178571. BIF_FEATURES_CONTROL_MISC_IND__SLV_BIF_CPL_EP_DIS_MASK
178572. BIF_FEATURES_CONTROL_MISC_IND__SLV_BIF_CPL_EP_DIS__SHIFT
178573. BIF_FEATURES_CONTROL_MISC_IND__UR_PSN_PKT_REPORT_POISON_DIS_MASK
178574. BIF_FEATURES_CONTROL_MISC_IND__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT
178575. BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK
178576. BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK
178577. BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT
178578. BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK
178579. BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__MASK
178580. BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT
178581. BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK
178582. BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT
178583. BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK
178584. BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__MASK
178585. BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT
178586. BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK
178587. BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__MASK
178588. BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT
178589. BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK
178590. BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT
178591. BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK
178592. BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__MASK
178593. BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT
178594. BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK
178595. BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__MASK
178596. BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT
178597. BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK
178598. BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__MASK
178599. BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT
178600. BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK
178601. BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__MASK
178602. BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT
178603. BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS_MASK
178604. BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS__SHIFT
178605. BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS_MASK
178606. BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS__SHIFT
178607. BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK
178608. BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__MASK
178609. BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT
178610. BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS_MASK
178611. BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS__SHIFT
178612. BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS_MASK
178613. BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS__SHIFT
178614. BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS_MASK
178615. BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS__SHIFT
178616. BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK
178617. BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__MASK
178618. BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT
178619. BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK
178620. BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT
178621. BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK
178622. BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT
178623. BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK
178624. BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT
178625. BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK
178626. BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__MASK
178627. BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT
178628. BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK
178629. BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__MASK
178630. BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT
178631. BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK
178632. BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT
178633. BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK
178634. BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT
178635. BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK
178636. BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT
178637. BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK
178638. BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__MASK
178639. BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT
178640. BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN_MASK
178641. BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN__SHIFT
178642. BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK
178643. BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT
178644. BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK
178645. BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT
178646. BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK
178647. BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT
178648. BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK
178649. BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT
178650. BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK
178651. BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT
178652. BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK
178653. BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT
178654. BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK
178655. BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT
178656. BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK
178657. BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT
178658. BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK
178659. BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT
178660. BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK
178661. BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__MASK
178662. BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT
178663. BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC0_RSV_MASK
178664. BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC0_RSV__SHIFT
178665. BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC1_RSV_MASK
178666. BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC1_RSV__SHIFT
178667. BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC3_RSV_MASK
178668. BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC3_RSV__SHIFT
178669. BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC7_RSV_MASK
178670. BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC7_RSV__SHIFT
178671. BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC0_RSV_MASK
178672. BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC0_RSV__SHIFT
178673. BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC1_RSV_MASK
178674. BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC1_RSV__SHIFT
178675. BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC3_RSV_MASK
178676. BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC3_RSV__SHIFT
178677. BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC7_RSV_MASK
178678. BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC7_RSV__SHIFT
178679. BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK
178680. BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT
178681. BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK
178682. BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT
178683. BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK
178684. BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT
178685. BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK
178686. BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT
178687. BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK
178688. BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT
178689. BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK
178690. BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT
178691. BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK
178692. BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT
178693. BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK
178694. BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT
178695. BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT_MASK
178696. BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__MASK
178697. BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__SHIFT
178698. BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT_MASK
178699. BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__MASK
178700. BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__SHIFT
178701. BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT_MASK
178702. BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__MASK
178703. BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__SHIFT
178704. BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE_MASK
178705. BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE__SHIFT
178706. BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE_MASK
178707. BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE__SHIFT
178708. BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED_MASK
178709. BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED__SHIFT
178710. BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK
178711. BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT
178712. BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK
178713. BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT
178714. BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK
178715. BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT
178716. BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK
178717. BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT
178718. BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK
178719. BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT
178720. BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK
178721. BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT
178722. BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK
178723. BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT
178724. BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK
178725. BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT
178726. BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK
178727. BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT
178728. BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK
178729. BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT
178730. BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK
178731. BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT
178732. BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK
178733. BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT
178734. BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK
178735. BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT
178736. BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK
178737. BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__MASK
178738. BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT
178739. BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK
178740. BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT
178741. BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK
178742. BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT
178743. BIF_IH_DOORBELL_RANGE__OFFSET_MASK
178744. BIF_IH_DOORBELL_RANGE__OFFSET__MASK
178745. BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT
178746. BIF_IH_DOORBELL_RANGE__SIZE_MASK
178747. BIF_IH_DOORBELL_RANGE__SIZE__MASK
178748. BIF_IH_DOORBELL_RANGE__SIZE__SHIFT
178749. BIF_IH_SRC_ID_START
178750. BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD_MASK
178751. BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD__SHIFT
178752. BIF_IMPCTL_RXCNTL__CAL_DONE_MASK
178753. BIF_IMPCTL_RXCNTL__CAL_DONE__SHIFT
178754. BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT_MASK
178755. BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT__SHIFT
178756. BIF_IMPCTL_RXCNTL__FORCE_RST_MASK
178757. BIF_IMPCTL_RXCNTL__FORCE_RST__SHIFT
178758. BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_MASK
178759. BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH_MASK
178760. BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH__SHIFT
178761. BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ__SHIFT
178762. BIF_IMPCTL_RXCNTL__RX_ADJUST_MASK
178763. BIF_IMPCTL_RXCNTL__RX_ADJUST__SHIFT
178764. BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH_MASK
178765. BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH__SHIFT
178766. BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG_MASK
178767. BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG__SHIFT
178768. BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED_MASK
178769. BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED__SHIFT
178770. BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_MASK
178771. BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL_MASK
178772. BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL__SHIFT
178773. BIF_IMPCTL_RXCNTL__RX_IMP_READBACK__SHIFT
178774. BIF_IMPCTL_RXCNTL__SUSPEND_MASK
178775. BIF_IMPCTL_RXCNTL__SUSPEND__SHIFT
178776. BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_MASK
178777. BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH_MASK
178778. BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH__SHIFT
178779. BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ__SHIFT
178780. BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES_MASK
178781. BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES__SHIFT
178782. BIF_IMPCTL_SMPLCNTL__FORCE_DONE_MASK
178783. BIF_IMPCTL_SMPLCNTL__FORCE_DONE__SHIFT
178784. BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE_MASK
178785. BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE__SHIFT
178786. BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH_MASK
178787. BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH__SHIFT
178788. BIF_IMPCTL_SMPLCNTL__RxPDNB_MASK
178789. BIF_IMPCTL_SMPLCNTL__RxPDNB__SHIFT
178790. BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD_MASK
178791. BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD__SHIFT
178792. BIF_IMPCTL_SMPLCNTL__SETUP_TIME_MASK
178793. BIF_IMPCTL_SMPLCNTL__SETUP_TIME__SHIFT
178794. BIF_IMPCTL_SMPLCNTL__TxPDNB_pd_MASK
178795. BIF_IMPCTL_SMPLCNTL__TxPDNB_pd__SHIFT
178796. BIF_IMPCTL_SMPLCNTL__TxPDNB_pu_MASK
178797. BIF_IMPCTL_SMPLCNTL__TxPDNB_pu__SHIFT
178798. BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH_MASK
178799. BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH__SHIFT
178800. BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd_MASK
178801. BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd__SHIFT
178802. BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd_MASK
178803. BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd__SHIFT
178804. BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd_MASK
178805. BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd__SHIFT
178806. BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd_MASK
178807. BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd__SHIFT
178808. BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd_MASK
178809. BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd__SHIFT
178810. BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd_MASK
178811. BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd__SHIFT
178812. BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd_MASK
178813. BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd__SHIFT
178814. BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd_MASK
178815. BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd__SHIFT
178816. BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd_MASK
178817. BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd__SHIFT
178818. BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd_MASK
178819. BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd__SHIFT
178820. BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu_MASK
178821. BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu__SHIFT
178822. BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu_MASK
178823. BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu__SHIFT
178824. BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu_MASK
178825. BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu__SHIFT
178826. BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu_MASK
178827. BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu__SHIFT
178828. BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu_MASK
178829. BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu__SHIFT
178830. BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu_MASK
178831. BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu__SHIFT
178832. BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu_MASK
178833. BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu__SHIFT
178834. BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu_MASK
178835. BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu__SHIFT
178836. BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu_MASK
178837. BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu__SHIFT
178838. BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu_MASK
178839. BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu__SHIFT
178840. BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK
178841. BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__MASK
178842. BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT
178843. BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK
178844. BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__MASK
178845. BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT
178846. BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK
178847. BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__MASK
178848. BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT
178849. BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK
178850. BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__MASK
178851. BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT
178852. BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK
178853. BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__MASK
178854. BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT
178855. BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK_MASK
178856. BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT
178857. BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK_MASK
178858. BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK__SHIFT
178859. BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK
178860. BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__MASK
178861. BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT
178862. BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK
178863. BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__MASK
178864. BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT
178865. BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK
178866. BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__MASK
178867. BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT
178868. BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK
178869. BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__MASK
178870. BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT
178871. BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK
178872. BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__MASK
178873. BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT
178874. BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS_MASK
178875. BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT
178876. BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS_MASK
178877. BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS__SHIFT
178878. BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK
178879. BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT
178880. BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN_MASK
178881. BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__MASK
178882. BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__SHIFT
178883. BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
178884. BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
178885. BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
178886. BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
178887. BIF_LNCNT_RESET
178888. BIF_LNCNT_RESET_IND__RESET_LNCNT_EN_MASK
178889. BIF_LNCNT_RESET_IND__RESET_LNCNT_EN__SHIFT
178890. BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK
178891. BIF_LNCNT_RESET__RESET_LNCNT_EN__SHIFT
178892. BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_EN_MASK
178893. BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_EN__SHIFT
178894. BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_TIMER_MASK
178895. BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_TIMER__SHIFT
178896. BIF_MEM_PG_CNTL__BIF_MEM_SD_EN_MASK
178897. BIF_MEM_PG_CNTL__BIF_MEM_SD_EN__SHIFT
178898. BIF_MEM_PG_CNTL__BIF_MEM_SD_TIMER_MASK
178899. BIF_MEM_PG_CNTL__BIF_MEM_SD_TIMER__SHIFT
178900. BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK
178901. BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT
178902. BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK
178903. BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT
178904. BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK
178905. BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT
178906. BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK
178907. BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT
178908. BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK
178909. BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT
178910. BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK
178911. BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT
178912. BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK
178913. BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT
178914. BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK
178915. BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT
178916. BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK
178917. BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT
178918. BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK
178919. BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT
178920. BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK
178921. BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT
178922. BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK
178923. BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT
178924. BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK
178925. BIF_MMSCH0_DOORBELL_RANGE__OFFSET__MASK
178926. BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT
178927. BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK
178928. BIF_MMSCH0_DOORBELL_RANGE__SIZE__MASK
178929. BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT
178930. BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK
178931. BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT
178932. BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK
178933. BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT
178934. BIF_MM_INDACCESS_CNTL_IND__MM_INDACCESS_DIS_MASK
178935. BIF_MM_INDACCESS_CNTL_IND__MM_INDACCESS_DIS__SHIFT
178936. BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK
178937. BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__MASK
178938. BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT
178939. BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK
178940. BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT
178941. BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK
178942. BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT
178943. BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK
178944. BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__MASK
178945. BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT
178946. BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
178947. BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
178948. BIF_NB
178949. BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK
178950. BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT
178951. BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK
178952. BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT
178953. BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2_MASK
178954. BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2__SHIFT
178955. BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3_MASK
178956. BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3__SHIFT
178957. BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK
178958. BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT
178959. BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK
178960. BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT
178961. BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2_MASK
178962. BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2__SHIFT
178963. BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3_MASK
178964. BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3__SHIFT
178965. BIF_PERFCOUNTER0_RESULT_IND__PERFCOUNTER_RESULT_MASK
178966. BIF_PERFCOUNTER0_RESULT_IND__PERFCOUNTER_RESULT__SHIFT
178967. BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK
178968. BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__MASK
178969. BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT
178970. BIF_PERFCOUNTER1_RESULT_IND__PERFCOUNTER_RESULT_MASK
178971. BIF_PERFCOUNTER1_RESULT_IND__PERFCOUNTER_RESULT__SHIFT
178972. BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK
178973. BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__MASK
178974. BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT
178975. BIF_PERFMON_CNTL_IND__PERFCOUNTER_EN_MASK
178976. BIF_PERFMON_CNTL_IND__PERFCOUNTER_EN__SHIFT
178977. BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET0_MASK
178978. BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET0__SHIFT
178979. BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET1_MASK
178980. BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET1__SHIFT
178981. BIF_PERFMON_CNTL_IND__PERF_SEL0_MASK
178982. BIF_PERFMON_CNTL_IND__PERF_SEL0__SHIFT
178983. BIF_PERFMON_CNTL_IND__PERF_SEL1_MASK
178984. BIF_PERFMON_CNTL_IND__PERF_SEL1__SHIFT
178985. BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK
178986. BIF_PERFMON_CNTL__PERFCOUNTER_EN__MASK
178987. BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT
178988. BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK
178989. BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__MASK
178990. BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT
178991. BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK
178992. BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__MASK
178993. BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT
178994. BIF_PERFMON_CNTL__PERF_SEL0_MASK
178995. BIF_PERFMON_CNTL__PERF_SEL0__MASK
178996. BIF_PERFMON_CNTL__PERF_SEL0__SHIFT
178997. BIF_PERFMON_CNTL__PERF_SEL1_MASK
178998. BIF_PERFMON_CNTL__PERF_SEL1__MASK
178999. BIF_PERFMON_CNTL__PERF_SEL1__SHIFT
179000. BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK
179001. BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__MASK
179002. BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT
179003. BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK_MASK
179004. BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__MASK
179005. BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__SHIFT
179006. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK_MASK
179007. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__MASK
179008. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__SHIFT
179009. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK_MASK
179010. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__MASK
179011. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__SHIFT
179012. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK_MASK
179013. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__MASK
179014. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__SHIFT
179015. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK_MASK
179016. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__MASK
179017. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__SHIFT
179018. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK_MASK
179019. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__MASK
179020. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__SHIFT
179021. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK_MASK
179022. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__MASK
179023. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__SHIFT
179024. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK_MASK
179025. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__MASK
179026. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__SHIFT
179027. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF16_FLR_INTR_MASK_MASK
179028. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF16_FLR_INTR_MASK__SHIFT
179029. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF17_FLR_INTR_MASK_MASK
179030. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF17_FLR_INTR_MASK__SHIFT
179031. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF18_FLR_INTR_MASK_MASK
179032. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF18_FLR_INTR_MASK__SHIFT
179033. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF19_FLR_INTR_MASK_MASK
179034. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF19_FLR_INTR_MASK__SHIFT
179035. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK_MASK
179036. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__MASK
179037. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT
179038. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF20_FLR_INTR_MASK_MASK
179039. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF20_FLR_INTR_MASK__SHIFT
179040. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF21_FLR_INTR_MASK_MASK
179041. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF21_FLR_INTR_MASK__SHIFT
179042. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF22_FLR_INTR_MASK_MASK
179043. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF22_FLR_INTR_MASK__SHIFT
179044. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF23_FLR_INTR_MASK_MASK
179045. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF23_FLR_INTR_MASK__SHIFT
179046. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF24_FLR_INTR_MASK_MASK
179047. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF24_FLR_INTR_MASK__SHIFT
179048. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF25_FLR_INTR_MASK_MASK
179049. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF25_FLR_INTR_MASK__SHIFT
179050. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF26_FLR_INTR_MASK_MASK
179051. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF26_FLR_INTR_MASK__SHIFT
179052. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF27_FLR_INTR_MASK_MASK
179053. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF27_FLR_INTR_MASK__SHIFT
179054. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF28_FLR_INTR_MASK_MASK
179055. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF28_FLR_INTR_MASK__SHIFT
179056. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF29_FLR_INTR_MASK_MASK
179057. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF29_FLR_INTR_MASK__SHIFT
179058. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK_MASK
179059. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__MASK
179060. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__SHIFT
179061. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF30_FLR_INTR_MASK_MASK
179062. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF30_FLR_INTR_MASK__SHIFT
179063. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK_MASK
179064. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__MASK
179065. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__SHIFT
179066. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK_MASK
179067. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__MASK
179068. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__SHIFT
179069. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK_MASK
179070. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__MASK
179071. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__SHIFT
179072. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK_MASK
179073. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__MASK
179074. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__SHIFT
179075. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK_MASK
179076. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__MASK
179077. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__SHIFT
179078. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK_MASK
179079. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__MASK
179080. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__SHIFT
179081. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK_MASK
179082. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__MASK
179083. BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__SHIFT
179084. BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS_MASK
179085. BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__MASK
179086. BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__SHIFT
179087. BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS_MASK
179088. BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__MASK
179089. BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__SHIFT
179090. BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS_MASK
179091. BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__MASK
179092. BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__SHIFT
179093. BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS_MASK
179094. BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__MASK
179095. BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__SHIFT
179096. BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS_MASK
179097. BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__MASK
179098. BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__SHIFT
179099. BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS_MASK
179100. BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__MASK
179101. BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__SHIFT
179102. BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS_MASK
179103. BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__MASK
179104. BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__SHIFT
179105. BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS_MASK
179106. BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__MASK
179107. BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__SHIFT
179108. BIF_PF0_VF_FLR_INTR_STS__PF0_VF16_FLR_INTR_STS_MASK
179109. BIF_PF0_VF_FLR_INTR_STS__PF0_VF16_FLR_INTR_STS__SHIFT
179110. BIF_PF0_VF_FLR_INTR_STS__PF0_VF17_FLR_INTR_STS_MASK
179111. BIF_PF0_VF_FLR_INTR_STS__PF0_VF17_FLR_INTR_STS__SHIFT
179112. BIF_PF0_VF_FLR_INTR_STS__PF0_VF18_FLR_INTR_STS_MASK
179113. BIF_PF0_VF_FLR_INTR_STS__PF0_VF18_FLR_INTR_STS__SHIFT
179114. BIF_PF0_VF_FLR_INTR_STS__PF0_VF19_FLR_INTR_STS_MASK
179115. BIF_PF0_VF_FLR_INTR_STS__PF0_VF19_FLR_INTR_STS__SHIFT
179116. BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS_MASK
179117. BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__MASK
179118. BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__SHIFT
179119. BIF_PF0_VF_FLR_INTR_STS__PF0_VF20_FLR_INTR_STS_MASK
179120. BIF_PF0_VF_FLR_INTR_STS__PF0_VF20_FLR_INTR_STS__SHIFT
179121. BIF_PF0_VF_FLR_INTR_STS__PF0_VF21_FLR_INTR_STS_MASK
179122. BIF_PF0_VF_FLR_INTR_STS__PF0_VF21_FLR_INTR_STS__SHIFT
179123. BIF_PF0_VF_FLR_INTR_STS__PF0_VF22_FLR_INTR_STS_MASK
179124. BIF_PF0_VF_FLR_INTR_STS__PF0_VF22_FLR_INTR_STS__SHIFT
179125. BIF_PF0_VF_FLR_INTR_STS__PF0_VF23_FLR_INTR_STS_MASK
179126. BIF_PF0_VF_FLR_INTR_STS__PF0_VF23_FLR_INTR_STS__SHIFT
179127. BIF_PF0_VF_FLR_INTR_STS__PF0_VF24_FLR_INTR_STS_MASK
179128. BIF_PF0_VF_FLR_INTR_STS__PF0_VF24_FLR_INTR_STS__SHIFT
179129. BIF_PF0_VF_FLR_INTR_STS__PF0_VF25_FLR_INTR_STS_MASK
179130. BIF_PF0_VF_FLR_INTR_STS__PF0_VF25_FLR_INTR_STS__SHIFT
179131. BIF_PF0_VF_FLR_INTR_STS__PF0_VF26_FLR_INTR_STS_MASK
179132. BIF_PF0_VF_FLR_INTR_STS__PF0_VF26_FLR_INTR_STS__SHIFT
179133. BIF_PF0_VF_FLR_INTR_STS__PF0_VF27_FLR_INTR_STS_MASK
179134. BIF_PF0_VF_FLR_INTR_STS__PF0_VF27_FLR_INTR_STS__SHIFT
179135. BIF_PF0_VF_FLR_INTR_STS__PF0_VF28_FLR_INTR_STS_MASK
179136. BIF_PF0_VF_FLR_INTR_STS__PF0_VF28_FLR_INTR_STS__SHIFT
179137. BIF_PF0_VF_FLR_INTR_STS__PF0_VF29_FLR_INTR_STS_MASK
179138. BIF_PF0_VF_FLR_INTR_STS__PF0_VF29_FLR_INTR_STS__SHIFT
179139. BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS_MASK
179140. BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__MASK
179141. BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__SHIFT
179142. BIF_PF0_VF_FLR_INTR_STS__PF0_VF30_FLR_INTR_STS_MASK
179143. BIF_PF0_VF_FLR_INTR_STS__PF0_VF30_FLR_INTR_STS__SHIFT
179144. BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS_MASK
179145. BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__MASK
179146. BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__SHIFT
179147. BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS_MASK
179148. BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__MASK
179149. BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__SHIFT
179150. BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS_MASK
179151. BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__MASK
179152. BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__SHIFT
179153. BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS_MASK
179154. BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__MASK
179155. BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__SHIFT
179156. BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS_MASK
179157. BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__MASK
179158. BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__SHIFT
179159. BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS_MASK
179160. BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__MASK
179161. BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__SHIFT
179162. BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS_MASK
179163. BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__MASK
179164. BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__SHIFT
179165. BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK
179166. BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__MASK
179167. BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT
179168. BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK
179169. BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__MASK
179170. BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT
179171. BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK
179172. BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__MASK
179173. BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT
179174. BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK
179175. BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__MASK
179176. BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT
179177. BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK
179178. BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__MASK
179179. BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT
179180. BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK
179181. BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__MASK
179182. BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT
179183. BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK
179184. BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__MASK
179185. BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT
179186. BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK
179187. BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__MASK
179188. BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT
179189. BIF_PF0_VF_FLR_RST__PF0_VF16_FLR_RST_MASK
179190. BIF_PF0_VF_FLR_RST__PF0_VF16_FLR_RST__SHIFT
179191. BIF_PF0_VF_FLR_RST__PF0_VF17_FLR_RST_MASK
179192. BIF_PF0_VF_FLR_RST__PF0_VF17_FLR_RST__SHIFT
179193. BIF_PF0_VF_FLR_RST__PF0_VF18_FLR_RST_MASK
179194. BIF_PF0_VF_FLR_RST__PF0_VF18_FLR_RST__SHIFT
179195. BIF_PF0_VF_FLR_RST__PF0_VF19_FLR_RST_MASK
179196. BIF_PF0_VF_FLR_RST__PF0_VF19_FLR_RST__SHIFT
179197. BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK
179198. BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__MASK
179199. BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT
179200. BIF_PF0_VF_FLR_RST__PF0_VF20_FLR_RST_MASK
179201. BIF_PF0_VF_FLR_RST__PF0_VF20_FLR_RST__SHIFT
179202. BIF_PF0_VF_FLR_RST__PF0_VF21_FLR_RST_MASK
179203. BIF_PF0_VF_FLR_RST__PF0_VF21_FLR_RST__SHIFT
179204. BIF_PF0_VF_FLR_RST__PF0_VF22_FLR_RST_MASK
179205. BIF_PF0_VF_FLR_RST__PF0_VF22_FLR_RST__SHIFT
179206. BIF_PF0_VF_FLR_RST__PF0_VF23_FLR_RST_MASK
179207. BIF_PF0_VF_FLR_RST__PF0_VF23_FLR_RST__SHIFT
179208. BIF_PF0_VF_FLR_RST__PF0_VF24_FLR_RST_MASK
179209. BIF_PF0_VF_FLR_RST__PF0_VF24_FLR_RST__SHIFT
179210. BIF_PF0_VF_FLR_RST__PF0_VF25_FLR_RST_MASK
179211. BIF_PF0_VF_FLR_RST__PF0_VF25_FLR_RST__SHIFT
179212. BIF_PF0_VF_FLR_RST__PF0_VF26_FLR_RST_MASK
179213. BIF_PF0_VF_FLR_RST__PF0_VF26_FLR_RST__SHIFT
179214. BIF_PF0_VF_FLR_RST__PF0_VF27_FLR_RST_MASK
179215. BIF_PF0_VF_FLR_RST__PF0_VF27_FLR_RST__SHIFT
179216. BIF_PF0_VF_FLR_RST__PF0_VF28_FLR_RST_MASK
179217. BIF_PF0_VF_FLR_RST__PF0_VF28_FLR_RST__SHIFT
179218. BIF_PF0_VF_FLR_RST__PF0_VF29_FLR_RST_MASK
179219. BIF_PF0_VF_FLR_RST__PF0_VF29_FLR_RST__SHIFT
179220. BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK
179221. BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__MASK
179222. BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT
179223. BIF_PF0_VF_FLR_RST__PF0_VF30_FLR_RST_MASK
179224. BIF_PF0_VF_FLR_RST__PF0_VF30_FLR_RST__SHIFT
179225. BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK
179226. BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__MASK
179227. BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT
179228. BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK
179229. BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__MASK
179230. BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT
179231. BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK
179232. BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__MASK
179233. BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT
179234. BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK
179235. BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__MASK
179236. BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT
179237. BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK
179238. BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__MASK
179239. BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT
179240. BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK
179241. BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__MASK
179242. BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT
179243. BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK
179244. BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__MASK
179245. BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT
179246. BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK
179247. BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__MASK
179248. BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT
179249. BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK
179250. BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__MASK
179251. BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT
179252. BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK
179253. BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__MASK
179254. BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT
179255. BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK
179256. BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__MASK
179257. BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT
179258. BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK
179259. BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__MASK
179260. BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT
179261. BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK
179262. BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__MASK
179263. BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT
179264. BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK
179265. BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__MASK
179266. BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT
179267. BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK
179268. BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__MASK
179269. BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT
179270. BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK_MASK
179271. BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK__SHIFT
179272. BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK_MASK
179273. BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK__SHIFT
179274. BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK_MASK
179275. BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK__SHIFT
179276. BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK_MASK
179277. BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK__SHIFT
179278. BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK_MASK
179279. BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK__SHIFT
179280. BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK_MASK
179281. BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK__SHIFT
179282. BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK_MASK
179283. BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK__SHIFT
179284. BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK_MASK
179285. BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK__SHIFT
179286. BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK
179287. BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__MASK
179288. BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT
179289. BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK
179290. BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__MASK
179291. BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT
179292. BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK
179293. BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__MASK
179294. BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT
179295. BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK
179296. BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__MASK
179297. BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT
179298. BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK
179299. BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__MASK
179300. BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT
179301. BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK
179302. BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__MASK
179303. BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT
179304. BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK
179305. BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__MASK
179306. BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT
179307. BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK
179308. BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__MASK
179309. BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT
179310. BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS_MASK
179311. BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS__SHIFT
179312. BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS_MASK
179313. BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS__SHIFT
179314. BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS_MASK
179315. BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS__SHIFT
179316. BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS_MASK
179317. BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS__SHIFT
179318. BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS_MASK
179319. BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS__SHIFT
179320. BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS_MASK
179321. BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS__SHIFT
179322. BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS_MASK
179323. BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS__SHIFT
179324. BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS_MASK
179325. BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS__SHIFT
179326. BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK
179327. BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__MASK
179328. BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT
179329. BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK
179330. BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__MASK
179331. BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT
179332. BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK
179333. BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__MASK
179334. BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT
179335. BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK
179336. BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__MASK
179337. BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT
179338. BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK
179339. BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__MASK
179340. BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT
179341. BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK
179342. BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__MASK
179343. BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT
179344. BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK
179345. BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__MASK
179346. BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT
179347. BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK_MASK
179348. BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__MASK
179349. BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT
179350. BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK_MASK
179351. BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK__SHIFT
179352. BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK_MASK
179353. BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK__SHIFT
179354. BIF_PF_FLR_INTR_MASK__DEV1_PF2_FLR_INTR_MASK_MASK
179355. BIF_PF_FLR_INTR_MASK__DEV1_PF2_FLR_INTR_MASK__SHIFT
179356. BIF_PF_FLR_INTR_MASK__DEV1_PF3_FLR_INTR_MASK_MASK
179357. BIF_PF_FLR_INTR_MASK__DEV1_PF3_FLR_INTR_MASK__SHIFT
179358. BIF_PF_FLR_INTR_MASK__DEV1_PF4_FLR_INTR_MASK_MASK
179359. BIF_PF_FLR_INTR_MASK__DEV1_PF4_FLR_INTR_MASK__SHIFT
179360. BIF_PF_FLR_INTR_MASK__DEV1_PF5_FLR_INTR_MASK_MASK
179361. BIF_PF_FLR_INTR_MASK__DEV1_PF5_FLR_INTR_MASK__SHIFT
179362. BIF_PF_FLR_INTR_MASK__DEV1_PF6_FLR_INTR_MASK_MASK
179363. BIF_PF_FLR_INTR_MASK__DEV1_PF6_FLR_INTR_MASK__SHIFT
179364. BIF_PF_FLR_INTR_MASK__DEV1_PF7_FLR_INTR_MASK_MASK
179365. BIF_PF_FLR_INTR_MASK__DEV1_PF7_FLR_INTR_MASK__SHIFT
179366. BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK
179367. BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__MASK
179368. BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT
179369. BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK
179370. BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__MASK
179371. BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT
179372. BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK
179373. BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__MASK
179374. BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT
179375. BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK
179376. BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__MASK
179377. BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT
179378. BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK
179379. BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__MASK
179380. BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT
179381. BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK
179382. BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__MASK
179383. BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT
179384. BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK
179385. BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__MASK
179386. BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT
179387. BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS_MASK
179388. BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__MASK
179389. BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT
179390. BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS_MASK
179391. BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS__SHIFT
179392. BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS_MASK
179393. BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS__SHIFT
179394. BIF_PF_FLR_INTR_STS__DEV1_PF2_FLR_INTR_STS_MASK
179395. BIF_PF_FLR_INTR_STS__DEV1_PF2_FLR_INTR_STS__SHIFT
179396. BIF_PF_FLR_INTR_STS__DEV1_PF3_FLR_INTR_STS_MASK
179397. BIF_PF_FLR_INTR_STS__DEV1_PF3_FLR_INTR_STS__SHIFT
179398. BIF_PF_FLR_INTR_STS__DEV1_PF4_FLR_INTR_STS_MASK
179399. BIF_PF_FLR_INTR_STS__DEV1_PF4_FLR_INTR_STS__SHIFT
179400. BIF_PF_FLR_INTR_STS__DEV1_PF5_FLR_INTR_STS_MASK
179401. BIF_PF_FLR_INTR_STS__DEV1_PF5_FLR_INTR_STS__SHIFT
179402. BIF_PF_FLR_INTR_STS__DEV1_PF6_FLR_INTR_STS_MASK
179403. BIF_PF_FLR_INTR_STS__DEV1_PF6_FLR_INTR_STS__SHIFT
179404. BIF_PF_FLR_INTR_STS__DEV1_PF7_FLR_INTR_STS_MASK
179405. BIF_PF_FLR_INTR_STS__DEV1_PF7_FLR_INTR_STS__SHIFT
179406. BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK
179407. BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__MASK
179408. BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT
179409. BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK
179410. BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__MASK
179411. BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT
179412. BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK
179413. BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__MASK
179414. BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT
179415. BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK
179416. BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__MASK
179417. BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT
179418. BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK
179419. BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__MASK
179420. BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT
179421. BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK
179422. BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__MASK
179423. BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT
179424. BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK
179425. BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__MASK
179426. BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT
179427. BIF_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK
179428. BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__MASK
179429. BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT
179430. BIF_PF_FLR_RST__DEV1_PF0_FLR_RST_MASK
179431. BIF_PF_FLR_RST__DEV1_PF0_FLR_RST__SHIFT
179432. BIF_PF_FLR_RST__DEV1_PF1_FLR_RST_MASK
179433. BIF_PF_FLR_RST__DEV1_PF1_FLR_RST__SHIFT
179434. BIF_PF_FLR_RST__DEV1_PF2_FLR_RST_MASK
179435. BIF_PF_FLR_RST__DEV1_PF2_FLR_RST__SHIFT
179436. BIF_PF_FLR_RST__DEV1_PF3_FLR_RST_MASK
179437. BIF_PF_FLR_RST__DEV1_PF3_FLR_RST__SHIFT
179438. BIF_PF_FLR_RST__DEV1_PF4_FLR_RST_MASK
179439. BIF_PF_FLR_RST__DEV1_PF4_FLR_RST__SHIFT
179440. BIF_PF_FLR_RST__DEV1_PF5_FLR_RST_MASK
179441. BIF_PF_FLR_RST__DEV1_PF5_FLR_RST__SHIFT
179442. BIF_PF_FLR_RST__DEV1_PF6_FLR_RST_MASK
179443. BIF_PF_FLR_RST__DEV1_PF6_FLR_RST__SHIFT
179444. BIF_PF_FLR_RST__DEV1_PF7_FLR_RST_MASK
179445. BIF_PF_FLR_RST__DEV1_PF7_FLR_RST__SHIFT
179446. BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL0_ACK_TIMER_MASK
179447. BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL0_ACK_TIMER__SHIFT
179448. BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL1_ACK_TIMER_MASK
179449. BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL1_ACK_TIMER__SHIFT
179450. BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL_SWITCH_TIMER_MASK
179451. BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL_SWITCH_TIMER__SHIFT
179452. BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK
179453. BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT
179454. BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK
179455. BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT
179456. BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK
179457. BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT
179458. BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK
179459. BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__MASK
179460. BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT
179461. BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK
179462. BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__MASK
179463. BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT
179464. BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE_MASK
179465. BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE__SHIFT
179466. BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE_MASK
179467. BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE__SHIFT
179468. BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK
179469. BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__MASK
179470. BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT
179471. BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK_MASK
179472. BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK__SHIFT
179473. BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK
179474. BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__MASK
179475. BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT
179476. BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK_MASK
179477. BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK__SHIFT
179478. BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK
179479. BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__MASK
179480. BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT
179481. BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS_MASK
179482. BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS__SHIFT
179483. BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK
179484. BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__MASK
179485. BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT
179486. BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS_MASK
179487. BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS__SHIFT
179488. BIF_PWDN_COMMAND__REG_BU_pw_cmd_MASK
179489. BIF_PWDN_COMMAND__REG_BU_pw_cmd__SHIFT
179490. BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK
179491. BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT
179492. BIF_PWDN_COMMAND__REG_FBU_pw_cmd_MASK
179493. BIF_PWDN_COMMAND__REG_FBU_pw_cmd__SHIFT
179494. BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd_MASK
179495. BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd__SHIFT
179496. BIF_PWDN_COMMAND__REG_RWREG_RFEWGBIF_pw_cmd_MASK
179497. BIF_PWDN_COMMAND__REG_RWREG_RFEWGBIF_pw_cmd__SHIFT
179498. BIF_PWDN_COMMAND__REG_SMBUS_pw_cmd_MASK
179499. BIF_PWDN_COMMAND__REG_SMBUS_pw_cmd__SHIFT
179500. BIF_PWDN_STATUS__BU_REG_pw_status_MASK
179501. BIF_PWDN_STATUS__BU_REG_pw_status__SHIFT
179502. BIF_PWDN_STATUS__BX_REG_pw_status_MASK
179503. BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT
179504. BIF_PWDN_STATUS__FBU_REG_pw_status_MASK
179505. BIF_PWDN_STATUS__FBU_REG_pw_status__SHIFT
179506. BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status_MASK
179507. BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status__SHIFT
179508. BIF_PWDN_STATUS__RWREG_RFEWGBIF_REG_pw_status_MASK
179509. BIF_PWDN_STATUS__RWREG_RFEWGBIF_REG_pw_status__SHIFT
179510. BIF_PWDN_STATUS__SMBUS_REG_pw_status_MASK
179511. BIF_PWDN_STATUS__SMBUS_REG_pw_status__SHIFT
179512. BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK
179513. BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT
179514. BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK
179515. BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__MASK
179516. BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT
179517. BIF_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK
179518. BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK
179519. BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT
179520. BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK
179521. BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK
179522. BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT
179523. BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK
179524. BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK
179525. BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT
179526. BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK
179527. BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK
179528. BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT
179529. BIF_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN_MASK
179530. BIF_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN__SHIFT
179531. BIF_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK
179532. BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK
179533. BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT
179534. BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK
179535. BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK
179536. BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT
179537. BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK
179538. BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK
179539. BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT
179540. BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK
179541. BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK
179542. BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT
179543. BIF_RAS_LEAF0_CTRL__POISON_DET_EN_MASK
179544. BIF_RAS_LEAF0_CTRL__POISON_DET_EN__MASK
179545. BIF_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT
179546. BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK
179547. BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK
179548. BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT
179549. BIF_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK
179550. BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK
179551. BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT
179552. BIF_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK
179553. BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK
179554. BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT
179555. BIF_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK
179556. BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK
179557. BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT
179558. BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK
179559. BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK
179560. BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT
179561. BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK
179562. BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK
179563. BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT
179564. BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK
179565. BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK
179566. BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT
179567. BIF_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN_MASK
179568. BIF_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN__SHIFT
179569. BIF_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK
179570. BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK
179571. BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT
179572. BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK
179573. BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK
179574. BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT
179575. BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK
179576. BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK
179577. BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT
179578. BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK
179579. BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK
179580. BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT
179581. BIF_RAS_LEAF1_CTRL__POISON_DET_EN_MASK
179582. BIF_RAS_LEAF1_CTRL__POISON_DET_EN__MASK
179583. BIF_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT
179584. BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK
179585. BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK
179586. BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT
179587. BIF_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK
179588. BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK
179589. BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT
179590. BIF_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK
179591. BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK
179592. BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT
179593. BIF_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK
179594. BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK
179595. BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT
179596. BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK
179597. BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK
179598. BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT
179599. BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK
179600. BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK
179601. BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT
179602. BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK
179603. BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK
179604. BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT
179605. BIF_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN_MASK
179606. BIF_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN__SHIFT
179607. BIF_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK
179608. BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK
179609. BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT
179610. BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK
179611. BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK
179612. BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT
179613. BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK
179614. BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK
179615. BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT
179616. BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK
179617. BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK
179618. BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT
179619. BIF_RAS_LEAF2_CTRL__POISON_DET_EN_MASK
179620. BIF_RAS_LEAF2_CTRL__POISON_DET_EN__MASK
179621. BIF_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT
179622. BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK
179623. BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK
179624. BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT
179625. BIF_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK
179626. BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK
179627. BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT
179628. BIF_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK
179629. BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK
179630. BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT
179631. BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN_MASK
179632. BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__MASK
179633. BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__SHIFT
179634. BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG_MASK
179635. BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__MASK
179636. BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__SHIFT
179637. BIF_RB_BASE_IND__ADDR_MASK
179638. BIF_RB_BASE_IND__ADDR__SHIFT
179639. BIF_RB_BASE__ADDR_MASK
179640. BIF_RB_BASE__ADDR__MASK
179641. BIF_RB_BASE__ADDR__SHIFT
179642. BIF_RB_CNTL_IND__BIF_RB_TRAN_MASK
179643. BIF_RB_CNTL_IND__BIF_RB_TRAN__SHIFT
179644. BIF_RB_CNTL_IND__RB_ENABLE_MASK
179645. BIF_RB_CNTL_IND__RB_ENABLE__SHIFT
179646. BIF_RB_CNTL_IND__RB_SIZE_MASK
179647. BIF_RB_CNTL_IND__RB_SIZE__SHIFT
179648. BIF_RB_CNTL_IND__WPTR_OVERFLOW_CLEAR_MASK
179649. BIF_RB_CNTL_IND__WPTR_OVERFLOW_CLEAR__SHIFT
179650. BIF_RB_CNTL_IND__WPTR_WRITEBACK_ENABLE_MASK
179651. BIF_RB_CNTL_IND__WPTR_WRITEBACK_ENABLE__SHIFT
179652. BIF_RB_CNTL_IND__WPTR_WRITEBACK_TIMER_MASK
179653. BIF_RB_CNTL_IND__WPTR_WRITEBACK_TIMER__SHIFT
179654. BIF_RB_CNTL__BIF_RB_TRAN_MASK
179655. BIF_RB_CNTL__BIF_RB_TRAN__MASK
179656. BIF_RB_CNTL__BIF_RB_TRAN__SHIFT
179657. BIF_RB_CNTL__RB_ENABLE_MASK
179658. BIF_RB_CNTL__RB_ENABLE__MASK
179659. BIF_RB_CNTL__RB_ENABLE__SHIFT
179660. BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK
179661. BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT
179662. BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK
179663. BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT
179664. BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK
179665. BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT
179666. BIF_RB_CNTL__RB_SIZE_MASK
179667. BIF_RB_CNTL__RB_SIZE__MASK
179668. BIF_RB_CNTL__RB_SIZE__SHIFT
179669. BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK
179670. BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__MASK
179671. BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT
179672. BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK
179673. BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__MASK
179674. BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT
179675. BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK
179676. BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__MASK
179677. BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT
179678. BIF_RB_RPTR_IND__OFFSET_MASK
179679. BIF_RB_RPTR_IND__OFFSET__SHIFT
179680. BIF_RB_RPTR__OFFSET_MASK
179681. BIF_RB_RPTR__OFFSET__MASK
179682. BIF_RB_RPTR__OFFSET__SHIFT
179683. BIF_RB_WPTR_ADDR_HI_IND__ADDR_MASK
179684. BIF_RB_WPTR_ADDR_HI_IND__ADDR__SHIFT
179685. BIF_RB_WPTR_ADDR_HI__ADDR_MASK
179686. BIF_RB_WPTR_ADDR_HI__ADDR__MASK
179687. BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT
179688. BIF_RB_WPTR_ADDR_LO_IND__ADDR_MASK
179689. BIF_RB_WPTR_ADDR_LO_IND__ADDR__SHIFT
179690. BIF_RB_WPTR_ADDR_LO__ADDR_MASK
179691. BIF_RB_WPTR_ADDR_LO__ADDR__MASK
179692. BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT
179693. BIF_RB_WPTR_IND__BIF_RB_OVERFLOW_MASK
179694. BIF_RB_WPTR_IND__BIF_RB_OVERFLOW__SHIFT
179695. BIF_RB_WPTR_IND__OFFSET_MASK
179696. BIF_RB_WPTR_IND__OFFSET__SHIFT
179697. BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK
179698. BIF_RB_WPTR__BIF_RB_OVERFLOW__MASK
179699. BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT
179700. BIF_RB_WPTR__OFFSET_MASK
179701. BIF_RB_WPTR__OFFSET__MASK
179702. BIF_RB_WPTR__OFFSET__SHIFT
179703. BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK
179704. BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__MASK
179705. BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT
179706. BIF_RESET_CNTL_IND__HOLD_LKTRN_WARMRST_DIS_MASK
179707. BIF_RESET_CNTL_IND__HOLD_LKTRN_WARMRST_DIS__SHIFT
179708. BIF_RESET_CNTL_IND__LINK_TRAIN_EN_MASK
179709. BIF_RESET_CNTL_IND__LINK_TRAIN_EN__SHIFT
179710. BIF_RESET_CNTL_IND__RECAP_STRAP_WARMRST_MASK
179711. BIF_RESET_CNTL_IND__RECAP_STRAP_WARMRST__SHIFT
179712. BIF_RESET_CNTL_IND__RST_DONE_MASK
179713. BIF_RESET_CNTL_IND__RST_DONE__SHIFT
179714. BIF_RESET_CNTL_IND__STRAP_ALL_VALID_MASK
179715. BIF_RESET_CNTL_IND__STRAP_ALL_VALID__SHIFT
179716. BIF_RESET_CNTL_IND__STRAP_EN_MASK
179717. BIF_RESET_CNTL_IND__STRAP_EN__SHIFT
179718. BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS_MASK
179719. BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS__SHIFT
179720. BIF_RESET_CNTL__LINK_TRAIN_EN_MASK
179721. BIF_RESET_CNTL__LINK_TRAIN_EN__SHIFT
179722. BIF_RESET_CNTL__RECAP_STRAP_WARMRST_MASK
179723. BIF_RESET_CNTL__RECAP_STRAP_WARMRST__SHIFT
179724. BIF_RESET_CNTL__RST_DONE_MASK
179725. BIF_RESET_CNTL__RST_DONE__SHIFT
179726. BIF_RESET_CNTL__STRAP_ALL_VALID_MASK
179727. BIF_RESET_CNTL__STRAP_ALL_VALID__SHIFT
179728. BIF_RESET_CNTL__STRAP_EN_MASK
179729. BIF_RESET_CNTL__STRAP_EN__SHIFT
179730. BIF_RESET_EN_IND__BIF_COR_RESET_EN_MASK
179731. BIF_RESET_EN_IND__BIF_COR_RESET_EN__SHIFT
179732. BIF_RESET_EN_IND__CFG_RESET_EN_MASK
179733. BIF_RESET_EN_IND__CFG_RESET_EN__SHIFT
179734. BIF_RESET_EN_IND__CFG_RESET_PULSE_WIDTH_MASK
179735. BIF_RESET_EN_IND__CFG_RESET_PULSE_WIDTH__SHIFT
179736. BIF_RESET_EN_IND__COR_RESET_EN_MASK
179737. BIF_RESET_EN_IND__COR_RESET_EN__SHIFT
179738. BIF_RESET_EN_IND__DRV_RESET_DELAY_SEL_MASK
179739. BIF_RESET_EN_IND__DRV_RESET_DELAY_SEL__SHIFT
179740. BIF_RESET_EN_IND__DRV_RESET_EN_MASK
179741. BIF_RESET_EN_IND__DRV_RESET_EN__SHIFT
179742. BIF_RESET_EN_IND__FUNC0_FLR_EN_MASK
179743. BIF_RESET_EN_IND__FUNC0_FLR_EN__SHIFT
179744. BIF_RESET_EN_IND__FUNC0_RESET_DELAY_SEL_MASK
179745. BIF_RESET_EN_IND__FUNC0_RESET_DELAY_SEL__SHIFT
179746. BIF_RESET_EN_IND__FUNC1_FLR_EN_MASK
179747. BIF_RESET_EN_IND__FUNC1_FLR_EN__SHIFT
179748. BIF_RESET_EN_IND__FUNC1_RESET_DELAY_SEL_MASK
179749. BIF_RESET_EN_IND__FUNC1_RESET_DELAY_SEL__SHIFT
179750. BIF_RESET_EN_IND__FUNC2_FLR_EN_MASK
179751. BIF_RESET_EN_IND__FUNC2_FLR_EN__SHIFT
179752. BIF_RESET_EN_IND__FUNC2_RESET_DELAY_SEL_MASK
179753. BIF_RESET_EN_IND__FUNC2_RESET_DELAY_SEL__SHIFT
179754. BIF_RESET_EN_IND__HOT_RESET_EN_MASK
179755. BIF_RESET_EN_IND__HOT_RESET_EN__SHIFT
179756. BIF_RESET_EN_IND__LINK_DISABLE_RESET_EN_MASK
179757. BIF_RESET_EN_IND__LINK_DISABLE_RESET_EN__SHIFT
179758. BIF_RESET_EN_IND__LINK_DOWN_RESET_EN_MASK
179759. BIF_RESET_EN_IND__LINK_DOWN_RESET_EN__SHIFT
179760. BIF_RESET_EN_IND__PHY_RESET_EN_MASK
179761. BIF_RESET_EN_IND__PHY_RESET_EN__SHIFT
179762. BIF_RESET_EN_IND__PIF_RSTB_EN_MASK
179763. BIF_RESET_EN_IND__PIF_RSTB_EN__SHIFT
179764. BIF_RESET_EN_IND__PIF_STRAP_ALLVALID_EN_MASK
179765. BIF_RESET_EN_IND__PIF_STRAP_ALLVALID_EN__SHIFT
179766. BIF_RESET_EN_IND__REG_RESET_EN_MASK
179767. BIF_RESET_EN_IND__REG_RESET_EN__SHIFT
179768. BIF_RESET_EN_IND__RESET_CFGREG_ONLY_EN_MASK
179769. BIF_RESET_EN_IND__RESET_CFGREG_ONLY_EN__SHIFT
179770. BIF_RESET_EN_IND__SOFT_RST_MODE_MASK
179771. BIF_RESET_EN_IND__SOFT_RST_MODE__SHIFT
179772. BIF_RESET_EN_IND__STY_RESET_EN_MASK
179773. BIF_RESET_EN_IND__STY_RESET_EN__SHIFT
179774. BIF_RESET_EN__BIF_COR_RESET_EN_MASK
179775. BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT
179776. BIF_RESET_EN__CFG_RESET_EN_MASK
179777. BIF_RESET_EN__CFG_RESET_EN__SHIFT
179778. BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK
179779. BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT
179780. BIF_RESET_EN__COR_RESET_EN_MASK
179781. BIF_RESET_EN__COR_RESET_EN__SHIFT
179782. BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK
179783. BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT
179784. BIF_RESET_EN__DRV_RESET_EN_MASK
179785. BIF_RESET_EN__DRV_RESET_EN__SHIFT
179786. BIF_RESET_EN__FUNC0_FLR_EN_MASK
179787. BIF_RESET_EN__FUNC0_FLR_EN__SHIFT
179788. BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK
179789. BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT
179790. BIF_RESET_EN__FUNC1_FLR_EN_MASK
179791. BIF_RESET_EN__FUNC1_FLR_EN__SHIFT
179792. BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK
179793. BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT
179794. BIF_RESET_EN__FUNC2_FLR_EN_MASK
179795. BIF_RESET_EN__FUNC2_FLR_EN__SHIFT
179796. BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK
179797. BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT
179798. BIF_RESET_EN__HOT_RESET_EN_MASK
179799. BIF_RESET_EN__HOT_RESET_EN__SHIFT
179800. BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK
179801. BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT
179802. BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK
179803. BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT
179804. BIF_RESET_EN__PHY_RESET_EN_MASK
179805. BIF_RESET_EN__PHY_RESET_EN__SHIFT
179806. BIF_RESET_EN__PIF_RSTB_EN_MASK
179807. BIF_RESET_EN__PIF_RSTB_EN__SHIFT
179808. BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK
179809. BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT
179810. BIF_RESET_EN__REG_RESET_EN_MASK
179811. BIF_RESET_EN__REG_RESET_EN__SHIFT
179812. BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK
179813. BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT
179814. BIF_RESET_EN__SOFT_RST_MODE_MASK
179815. BIF_RESET_EN__SOFT_RST_MODE__SHIFT
179816. BIF_RESET_EN__STY_RESET_EN_MASK
179817. BIF_RESET_EN__STY_RESET_EN__SHIFT
179818. BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst_MASK
179819. BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst__SHIFT
179820. BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWGBIF_rst_MASK
179821. BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWGBIF_rst__SHIFT
179822. BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst_MASK
179823. BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst__SHIFT
179824. BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWGBIF_rst_MASK
179825. BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWGBIF_rst__SHIFT
179826. BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWGBIF_rst_MASK
179827. BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWGBIF_rst__SHIFT
179828. BIF_RFE_CNTL_MISC_IND__ADAPT_pciecore0_bu_reg_accessMode_MASK
179829. BIF_RFE_CNTL_MISC_IND__ADAPT_pciecore0_bu_reg_accessMode__SHIFT
179830. BIF_RFE_CNTL_MISC_IND__ADAPT_pif0_bu_reg_accessMode_MASK
179831. BIF_RFE_CNTL_MISC_IND__ADAPT_pif0_bu_reg_accessMode__SHIFT
179832. BIF_RFE_CNTL_MISC_IND__ADAPT_pif1_bu_reg_accessMode_MASK
179833. BIF_RFE_CNTL_MISC_IND__ADAPT_pif1_bu_reg_accessMode__SHIFT
179834. BIF_RFE_CNTL_MISC_IND__ADAPT_pwreg_bu_reg_accessMode_MASK
179835. BIF_RFE_CNTL_MISC_IND__ADAPT_pwreg_bu_reg_accessMode__SHIFT
179836. BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode_MASK
179837. BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode__SHIFT
179838. BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode_MASK
179839. BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode__SHIFT
179840. BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode_MASK
179841. BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode__SHIFT
179842. BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode_MASK
179843. BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode__SHIFT
179844. BIF_RFE_IMPRST_CNTL__REG_RST_impEn_MASK
179845. BIF_RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT
179846. BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst_MASK
179847. BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst__SHIFT
179848. BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK
179849. BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT
179850. BIF_RFE_MASTER_SOFTRST_TRIGGER__FBU_rst_MASK
179851. BIF_RFE_MASTER_SOFTRST_TRIGGER__FBU_rst__SHIFT
179852. BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst_MASK
179853. BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst__SHIFT
179854. BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWGBIF_rst_MASK
179855. BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWGBIF_rst__SHIFT
179856. BIF_RFE_MASTER_SOFTRST_TRIGGER__SMBUS_rst_MASK
179857. BIF_RFE_MASTER_SOFTRST_TRIGGER__SMBUS_rst__SHIFT
179858. BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK
179859. BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT
179860. BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK
179861. BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT
179862. BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK
179863. BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT
179864. BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK
179865. BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT
179866. BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_CFG_FUNC_SEL_MASK
179867. BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_CFG_FUNC_SEL__SHIFT
179868. BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_WR_TO_CFG_EN_MASK
179869. BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_WR_TO_CFG_EN__SHIFT
179870. BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_CFG_FUNC_SEL_MASK
179871. BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_CFG_FUNC_SEL__SHIFT
179872. BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_WR_TO_CFG_EN_MASK
179873. BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_WR_TO_CFG_EN__SHIFT
179874. BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout_MASK
179875. BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout__SHIFT
179876. BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer_MASK
179877. BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer__SHIFT
179878. BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer_MASK
179879. BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer__SHIFT
179880. BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer_MASK
179881. BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer__SHIFT
179882. BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK
179883. BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT
179884. BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK
179885. BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT
179886. BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK
179887. BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT
179888. BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK
179889. BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT
179890. BIF_RFE_MST_FBU_CMDSTATUS__FBU_RFE_mstTimeout_MASK
179891. BIF_RFE_MST_FBU_CMDSTATUS__FBU_RFE_mstTimeout__SHIFT
179892. BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkGate_timer_MASK
179893. BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkGate_timer__SHIFT
179894. BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkSetup_timer_MASK
179895. BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkSetup_timer__SHIFT
179896. BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_timeout_timer_MASK
179897. BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_timeout_timer__SHIFT
179898. BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer_MASK
179899. BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer__SHIFT
179900. BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer_MASK
179901. BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer__SHIFT
179902. BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer_MASK
179903. BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer__SHIFT
179904. BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout_MASK
179905. BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout__SHIFT
179906. BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkGate_timer_MASK
179907. BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkGate_timer__SHIFT
179908. BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkSetup_timer_MASK
179909. BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkSetup_timer__SHIFT
179910. BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_timeout_timer_MASK
179911. BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_timeout_timer__SHIFT
179912. BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__RWREG_RFEWGBIF_RFE_mstTimeout_MASK
179913. BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__RWREG_RFEWGBIF_RFE_mstTimeout__SHIFT
179914. BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkGate_timer_MASK
179915. BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkGate_timer__SHIFT
179916. BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkSetup_timer_MASK
179917. BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkSetup_timer__SHIFT
179918. BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_timeout_timer_MASK
179919. BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_timeout_timer__SHIFT
179920. BIF_RFE_MST_SMBUS_CMDSTATUS__SMBUS_RFE_mstTimeout_MASK
179921. BIF_RFE_MST_SMBUS_CMDSTATUS__SMBUS_RFE_mstTimeout__SHIFT
179922. BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK
179923. BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT
179924. BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK
179925. BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT
179926. BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK
179927. BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT
179928. BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK
179929. BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT
179930. BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK
179931. BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT
179932. BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK
179933. BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT
179934. BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK
179935. BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT
179936. BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK
179937. BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT
179938. BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK
179939. BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__MASK
179940. BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT
179941. BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK
179942. BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__MASK
179943. BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT
179944. BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK
179945. BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__MASK
179946. BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT
179947. BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT_MASK
179948. BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT__SHIFT
179949. BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK
179950. BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__MASK
179951. BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT
179952. BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT_MASK
179953. BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT__SHIFT
179954. BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE_MASK
179955. BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__MASK
179956. BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT
179957. BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE_MASK
179958. BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__MASK
179959. BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__SHIFT
179960. BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE_MASK
179961. BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__MASK
179962. BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__SHIFT
179963. BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE_MASK
179964. BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__MASK
179965. BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__SHIFT
179966. BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE_MASK
179967. BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__MASK
179968. BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__SHIFT
179969. BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE_MASK
179970. BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__MASK
179971. BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__SHIFT
179972. BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE_MASK
179973. BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__MASK
179974. BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__SHIFT
179975. BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE_MASK
179976. BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__MASK
179977. BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__SHIFT
179978. BIF_RST_GFXVF_FLR_IDLE__VF16_TRANS_IDLE_MASK
179979. BIF_RST_GFXVF_FLR_IDLE__VF16_TRANS_IDLE__SHIFT
179980. BIF_RST_GFXVF_FLR_IDLE__VF17_TRANS_IDLE_MASK
179981. BIF_RST_GFXVF_FLR_IDLE__VF17_TRANS_IDLE__SHIFT
179982. BIF_RST_GFXVF_FLR_IDLE__VF18_TRANS_IDLE_MASK
179983. BIF_RST_GFXVF_FLR_IDLE__VF18_TRANS_IDLE__SHIFT
179984. BIF_RST_GFXVF_FLR_IDLE__VF19_TRANS_IDLE_MASK
179985. BIF_RST_GFXVF_FLR_IDLE__VF19_TRANS_IDLE__SHIFT
179986. BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE_MASK
179987. BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__MASK
179988. BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__SHIFT
179989. BIF_RST_GFXVF_FLR_IDLE__VF20_TRANS_IDLE_MASK
179990. BIF_RST_GFXVF_FLR_IDLE__VF20_TRANS_IDLE__SHIFT
179991. BIF_RST_GFXVF_FLR_IDLE__VF21_TRANS_IDLE_MASK
179992. BIF_RST_GFXVF_FLR_IDLE__VF21_TRANS_IDLE__SHIFT
179993. BIF_RST_GFXVF_FLR_IDLE__VF22_TRANS_IDLE_MASK
179994. BIF_RST_GFXVF_FLR_IDLE__VF22_TRANS_IDLE__SHIFT
179995. BIF_RST_GFXVF_FLR_IDLE__VF23_TRANS_IDLE_MASK
179996. BIF_RST_GFXVF_FLR_IDLE__VF23_TRANS_IDLE__SHIFT
179997. BIF_RST_GFXVF_FLR_IDLE__VF24_TRANS_IDLE_MASK
179998. BIF_RST_GFXVF_FLR_IDLE__VF24_TRANS_IDLE__SHIFT
179999. BIF_RST_GFXVF_FLR_IDLE__VF25_TRANS_IDLE_MASK
180000. BIF_RST_GFXVF_FLR_IDLE__VF25_TRANS_IDLE__SHIFT
180001. BIF_RST_GFXVF_FLR_IDLE__VF26_TRANS_IDLE_MASK
180002. BIF_RST_GFXVF_FLR_IDLE__VF26_TRANS_IDLE__SHIFT
180003. BIF_RST_GFXVF_FLR_IDLE__VF27_TRANS_IDLE_MASK
180004. BIF_RST_GFXVF_FLR_IDLE__VF27_TRANS_IDLE__SHIFT
180005. BIF_RST_GFXVF_FLR_IDLE__VF28_TRANS_IDLE_MASK
180006. BIF_RST_GFXVF_FLR_IDLE__VF28_TRANS_IDLE__SHIFT
180007. BIF_RST_GFXVF_FLR_IDLE__VF29_TRANS_IDLE_MASK
180008. BIF_RST_GFXVF_FLR_IDLE__VF29_TRANS_IDLE__SHIFT
180009. BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE_MASK
180010. BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__MASK
180011. BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__SHIFT
180012. BIF_RST_GFXVF_FLR_IDLE__VF30_TRANS_IDLE_MASK
180013. BIF_RST_GFXVF_FLR_IDLE__VF30_TRANS_IDLE__SHIFT
180014. BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE_MASK
180015. BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__MASK
180016. BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__SHIFT
180017. BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE_MASK
180018. BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__MASK
180019. BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__SHIFT
180020. BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE_MASK
180021. BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__MASK
180022. BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__SHIFT
180023. BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE_MASK
180024. BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__MASK
180025. BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__SHIFT
180026. BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE_MASK
180027. BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__MASK
180028. BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__SHIFT
180029. BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE_MASK
180030. BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__MASK
180031. BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__SHIFT
180032. BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE_MASK
180033. BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__MASK
180034. BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__SHIFT
180035. BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK
180036. BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__MASK
180037. BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT
180038. BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK
180039. BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__MASK
180040. BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT
180041. BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE_MASK
180042. BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE__SHIFT
180043. BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK
180044. BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__MASK
180045. BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT
180046. BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK
180047. BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__MASK
180048. BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT
180049. BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK
180050. BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__MASK
180051. BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT
180052. BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK
180053. BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__MASK
180054. BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT
180055. BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK
180056. BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__MASK
180057. BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT
180058. BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK
180059. BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__MASK
180060. BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT
180061. BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK
180062. BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__MASK
180063. BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT
180064. BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE_MASK
180065. BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE__SHIFT
180066. BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK
180067. BIF_RST_MISC_CTRL3__TIMER_SCALE__MASK
180068. BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT
180069. BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK
180070. BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__MASK
180071. BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT
180072. BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK
180073. BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__MASK
180074. BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT
180075. BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK
180076. BIF_RST_MISC_CTRL__DRV_RST_MODE__MASK
180077. BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT
180078. BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK
180079. BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__MASK
180080. BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT
180081. BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK
180082. BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__MASK
180083. BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT
180084. BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK
180085. BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__MASK
180086. BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT
180087. BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK
180088. BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__MASK
180089. BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT
180090. BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK
180091. BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__MASK
180092. BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT
180093. BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK
180094. BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__MASK
180095. BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT
180096. BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK
180097. BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__MASK
180098. BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT
180099. BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK
180100. BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__MASK
180101. BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT
180102. BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK
180103. BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__MASK
180104. BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT
180105. BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK
180106. BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__MASK
180107. BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT
180108. BIF_SCRATCH0
180109. BIF_SCRATCH0_IND__BIF_SCRATCH0_MASK
180110. BIF_SCRATCH0_IND__BIF_SCRATCH0__SHIFT
180111. BIF_SCRATCH0__BIF_SCRATCH0_MASK
180112. BIF_SCRATCH0__BIF_SCRATCH0__MASK
180113. BIF_SCRATCH0__BIF_SCRATCH0__SHIFT
180114. BIF_SCRATCH1_IND__BIF_SCRATCH1_MASK
180115. BIF_SCRATCH1_IND__BIF_SCRATCH1__SHIFT
180116. BIF_SCRATCH1__BIF_SCRATCH1_MASK
180117. BIF_SCRATCH1__BIF_SCRATCH1__MASK
180118. BIF_SCRATCH1__BIF_SCRATCH1__SHIFT
180119. BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK
180120. BIF_SDMA0_DOORBELL_RANGE__OFFSET__MASK
180121. BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT
180122. BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK
180123. BIF_SDMA0_DOORBELL_RANGE__SIZE__MASK
180124. BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT
180125. BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK
180126. BIF_SDMA1_DOORBELL_RANGE__OFFSET__MASK
180127. BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT
180128. BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK
180129. BIF_SDMA1_DOORBELL_RANGE__SIZE__MASK
180130. BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT
180131. BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK
180132. BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__MASK
180133. BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT
180134. BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID_MASK
180135. BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__MASK
180136. BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__SHIFT
180137. BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK
180138. BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT
180139. BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK
180140. BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT
180141. BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK
180142. BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT
180143. BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK
180144. BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__MASK
180145. BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT
180146. BIF_SLVARB_MODE_IND__SLVARB_MODE_MASK
180147. BIF_SLVARB_MODE_IND__SLVARB_MODE__SHIFT
180148. BIF_SLVARB_MODE__SLVARB_MODE_MASK
180149. BIF_SLVARB_MODE__SLVARB_MODE__MASK
180150. BIF_SLVARB_MODE__SLVARB_MODE__SHIFT
180151. BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK
180152. BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__MASK
180153. BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT
180154. BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
180155. BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
180156. BIF_SMU_DATA_IND__BIF_SMU_DATA_MASK
180157. BIF_SMU_DATA_IND__BIF_SMU_DATA__SHIFT
180158. BIF_SMU_DATA__BIF_SMU_DATA_MASK
180159. BIF_SMU_DATA__BIF_SMU_DATA__SHIFT
180160. BIF_SMU_INDEX_IND__BIF_SMU_INDEX_MASK
180161. BIF_SMU_INDEX_IND__BIF_SMU_INDEX__SHIFT
180162. BIF_SMU_INDEX__BIF_SMU_INDEX_MASK
180163. BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT
180164. BIF_SSA_DISP_LOWER__SSA_DISP_LOWER_MASK
180165. BIF_SSA_DISP_LOWER__SSA_DISP_LOWER__SHIFT
180166. BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN_MASK
180167. BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN__SHIFT
180168. BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN_MASK
180169. BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN__SHIFT
180170. BIF_SSA_DISP_UPPER__SSA_DISP_UPPER_MASK
180171. BIF_SSA_DISP_UPPER__SSA_DISP_UPPER__SHIFT
180172. BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER_MASK
180173. BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER__SHIFT
180174. BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN_MASK
180175. BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN__SHIFT
180176. BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN_MASK
180177. BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN__SHIFT
180178. BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER_MASK
180179. BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER__SHIFT
180180. BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER_MASK
180181. BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER__SHIFT
180182. BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN_MASK
180183. BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN__SHIFT
180184. BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN_MASK
180185. BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN__SHIFT
180186. BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER_MASK
180187. BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER__SHIFT
180188. BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER_MASK
180189. BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER__SHIFT
180190. BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN_MASK
180191. BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN__SHIFT
180192. BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN_MASK
180193. BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN__SHIFT
180194. BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER_MASK
180195. BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER__SHIFT
180196. BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER_MASK
180197. BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER__SHIFT
180198. BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN_MASK
180199. BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN__SHIFT
180200. BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN_MASK
180201. BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN__SHIFT
180202. BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER_MASK
180203. BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER__SHIFT
180204. BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN_MASK
180205. BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN__SHIFT
180206. BIF_SSA_MC_LOWER__SSA_MC_LOWER_MASK
180207. BIF_SSA_MC_LOWER__SSA_MC_LOWER__SHIFT
180208. BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN_MASK
180209. BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN__SHIFT
180210. BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN_MASK
180211. BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN__SHIFT
180212. BIF_SSA_MC_UPPER__SSA_MC_UPPER_MASK
180213. BIF_SSA_MC_UPPER__SSA_MC_UPPER__SHIFT
180214. BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS_MASK
180215. BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS__SHIFT
180216. BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS_MASK
180217. BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS__SHIFT
180218. BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS_MASK
180219. BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS__SHIFT
180220. BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK
180221. BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__MASK
180222. BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT
180223. BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK
180224. BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__MASK
180225. BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT
180226. BIF_USB_SHUB_RS_RESET_CNTL__FLR_ON_RS_RESET_EN_MASK
180227. BIF_USB_SHUB_RS_RESET_CNTL__FLR_ON_RS_RESET_EN__SHIFT
180228. BIF_USB_SHUB_RS_RESET_CNTL__LKRST_ON_RS_RESET_EN_MASK
180229. BIF_USB_SHUB_RS_RESET_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
180230. BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK
180231. BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__MASK
180232. BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT
180233. BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK
180234. BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__MASK
180235. BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT
180236. BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK
180237. BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__MASK
180238. BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT
180239. BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK
180240. BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__MASK
180241. BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT
180242. BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK
180243. BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT
180244. BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK
180245. BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__MASK
180246. BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT
180247. BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK
180248. BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT
180249. BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK
180250. BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT
180251. BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK
180252. BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT
180253. BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK
180254. BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT
180255. BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK
180256. BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT
180257. BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK
180258. BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT
180259. BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK
180260. BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__MASK
180261. BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT
180262. BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK
180263. BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__MASK
180264. BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT
180265. BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK
180266. BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__MASK
180267. BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT
180268. BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK
180269. BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__MASK
180270. BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT
180271. BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK
180272. BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__MASK
180273. BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT
180274. BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_CMP_EN_MASK
180275. BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_CMP_EN__SHIFT
180276. BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_STALL_EN_MASK
180277. BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_STALL_EN__SHIFT
180278. BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_CMP_EN_MASK
180279. BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_CMP_EN__SHIFT
180280. BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_STALL_EN_MASK
180281. BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_STALL_EN__SHIFT
180282. BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_CMP_EN_MASK
180283. BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_CMP_EN__SHIFT
180284. BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_STALL_EN_MASK
180285. BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_STALL_EN__SHIFT
180286. BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK
180287. BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__MASK
180288. BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT
180289. BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK
180290. BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__MASK
180291. BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT
180292. BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK
180293. BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__MASK
180294. BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT
180295. BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK
180296. BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__MASK
180297. BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT
180298. BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK
180299. BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__MASK
180300. BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT
180301. BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK
180302. BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__MASK
180303. BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT
180304. BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_CMP_EN_MASK
180305. BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_CMP_EN__SHIFT
180306. BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_LOWER_MASK
180307. BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_LOWER__SHIFT
180308. BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_STALL_EN_MASK
180309. BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_STALL_EN__SHIFT
180310. BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK
180311. BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__MASK
180312. BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT
180313. BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK
180314. BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__MASK
180315. BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT
180316. BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK
180317. BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__MASK
180318. BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT
180319. BIF_VDDGFX_GFX0_UPPER_IND__VDDGFX_GFX0_REG_UPPER_MASK
180320. BIF_VDDGFX_GFX0_UPPER_IND__VDDGFX_GFX0_REG_UPPER__SHIFT
180321. BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK
180322. BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__MASK
180323. BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT
180324. BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_CMP_EN_MASK
180325. BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_CMP_EN__SHIFT
180326. BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_LOWER_MASK
180327. BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_LOWER__SHIFT
180328. BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_STALL_EN_MASK
180329. BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_STALL_EN__SHIFT
180330. BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK
180331. BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__MASK
180332. BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT
180333. BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK
180334. BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__MASK
180335. BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT
180336. BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK
180337. BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__MASK
180338. BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT
180339. BIF_VDDGFX_GFX1_UPPER_IND__VDDGFX_GFX1_REG_UPPER_MASK
180340. BIF_VDDGFX_GFX1_UPPER_IND__VDDGFX_GFX1_REG_UPPER__SHIFT
180341. BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK
180342. BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__MASK
180343. BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT
180344. BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_CMP_EN_MASK
180345. BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_CMP_EN__SHIFT
180346. BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_LOWER_MASK
180347. BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_LOWER__SHIFT
180348. BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_STALL_EN_MASK
180349. BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_STALL_EN__SHIFT
180350. BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK
180351. BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__MASK
180352. BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT
180353. BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK
180354. BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__MASK
180355. BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT
180356. BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK
180357. BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__MASK
180358. BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT
180359. BIF_VDDGFX_GFX2_UPPER_IND__VDDGFX_GFX2_REG_UPPER_MASK
180360. BIF_VDDGFX_GFX2_UPPER_IND__VDDGFX_GFX2_REG_UPPER__SHIFT
180361. BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK
180362. BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__MASK
180363. BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT
180364. BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_CMP_EN_MASK
180365. BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_CMP_EN__SHIFT
180366. BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_LOWER_MASK
180367. BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_LOWER__SHIFT
180368. BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_STALL_EN_MASK
180369. BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_STALL_EN__SHIFT
180370. BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK
180371. BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__MASK
180372. BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT
180373. BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK
180374. BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__MASK
180375. BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT
180376. BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK
180377. BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__MASK
180378. BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT
180379. BIF_VDDGFX_GFX3_UPPER_IND__VDDGFX_GFX3_REG_UPPER_MASK
180380. BIF_VDDGFX_GFX3_UPPER_IND__VDDGFX_GFX3_REG_UPPER__SHIFT
180381. BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK
180382. BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__MASK
180383. BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT
180384. BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_CMP_EN_MASK
180385. BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_CMP_EN__SHIFT
180386. BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_LOWER_MASK
180387. BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_LOWER__SHIFT
180388. BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_STALL_EN_MASK
180389. BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_STALL_EN__SHIFT
180390. BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK
180391. BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__MASK
180392. BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT
180393. BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK
180394. BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__MASK
180395. BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT
180396. BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK
180397. BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__MASK
180398. BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT
180399. BIF_VDDGFX_GFX4_UPPER_IND__VDDGFX_GFX4_REG_UPPER_MASK
180400. BIF_VDDGFX_GFX4_UPPER_IND__VDDGFX_GFX4_REG_UPPER__SHIFT
180401. BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK
180402. BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__MASK
180403. BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT
180404. BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_CMP_EN_MASK
180405. BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_CMP_EN__SHIFT
180406. BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_LOWER_MASK
180407. BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_LOWER__SHIFT
180408. BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_STALL_EN_MASK
180409. BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_STALL_EN__SHIFT
180410. BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK
180411. BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__MASK
180412. BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT
180413. BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK
180414. BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__MASK
180415. BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT
180416. BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK
180417. BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__MASK
180418. BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT
180419. BIF_VDDGFX_GFX5_UPPER_IND__VDDGFX_GFX5_REG_UPPER_MASK
180420. BIF_VDDGFX_GFX5_UPPER_IND__VDDGFX_GFX5_REG_UPPER__SHIFT
180421. BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK
180422. BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__MASK
180423. BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT
180424. BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_CMP_EN_MASK
180425. BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_CMP_EN__SHIFT
180426. BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_LOWER_MASK
180427. BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_LOWER__SHIFT
180428. BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_STALL_EN_MASK
180429. BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_STALL_EN__SHIFT
180430. BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK
180431. BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__MASK
180432. BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT
180433. BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK
180434. BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__MASK
180435. BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT
180436. BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK
180437. BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__MASK
180438. BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT
180439. BIF_VDDGFX_RSV1_UPPER_IND__VDDGFX_RSV1_REG_UPPER_MASK
180440. BIF_VDDGFX_RSV1_UPPER_IND__VDDGFX_RSV1_REG_UPPER__SHIFT
180441. BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK
180442. BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__MASK
180443. BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT
180444. BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_CMP_EN_MASK
180445. BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_CMP_EN__SHIFT
180446. BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_LOWER_MASK
180447. BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_LOWER__SHIFT
180448. BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_STALL_EN_MASK
180449. BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_STALL_EN__SHIFT
180450. BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK
180451. BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__MASK
180452. BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT
180453. BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK
180454. BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__MASK
180455. BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT
180456. BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK
180457. BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__MASK
180458. BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT
180459. BIF_VDDGFX_RSV2_UPPER_IND__VDDGFX_RSV2_REG_UPPER_MASK
180460. BIF_VDDGFX_RSV2_UPPER_IND__VDDGFX_RSV2_REG_UPPER__SHIFT
180461. BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK
180462. BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__MASK
180463. BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT
180464. BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_CMP_EN_MASK
180465. BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_CMP_EN__SHIFT
180466. BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_LOWER_MASK
180467. BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_LOWER__SHIFT
180468. BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_STALL_EN_MASK
180469. BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_STALL_EN__SHIFT
180470. BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK
180471. BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__MASK
180472. BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT
180473. BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK
180474. BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__MASK
180475. BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT
180476. BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK
180477. BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__MASK
180478. BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT
180479. BIF_VDDGFX_RSV3_UPPER_IND__VDDGFX_RSV3_REG_UPPER_MASK
180480. BIF_VDDGFX_RSV3_UPPER_IND__VDDGFX_RSV3_REG_UPPER__SHIFT
180481. BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK
180482. BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__MASK
180483. BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT
180484. BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_CMP_EN_MASK
180485. BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_CMP_EN__SHIFT
180486. BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_LOWER_MASK
180487. BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_LOWER__SHIFT
180488. BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_STALL_EN_MASK
180489. BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_STALL_EN__SHIFT
180490. BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK
180491. BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__MASK
180492. BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT
180493. BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK
180494. BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__MASK
180495. BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT
180496. BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK
180497. BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__MASK
180498. BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT
180499. BIF_VDDGFX_RSV4_UPPER_IND__VDDGFX_RSV4_REG_UPPER_MASK
180500. BIF_VDDGFX_RSV4_UPPER_IND__VDDGFX_RSV4_REG_UPPER__SHIFT
180501. BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK
180502. BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__MASK
180503. BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT
180504. BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF_MASK
180505. BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF__SHIFT
180506. BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF_MASK
180507. BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF__SHIFT
180508. BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK
180509. BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__MASK
180510. BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT
180511. BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK
180512. BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__MASK
180513. BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT
180514. BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK
180515. BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__MASK
180516. BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT
180517. BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK
180518. BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__MASK
180519. BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT
180520. BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK
180521. BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__MASK
180522. BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT
180523. BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK
180524. BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__MASK
180525. BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT
180526. BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK
180527. BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__MASK
180528. BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT
180529. BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK
180530. BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__MASK
180531. BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT
180532. BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK
180533. BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT
180534. BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK
180535. BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT
180536. BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK
180537. BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT
180538. BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK
180539. BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT
180540. BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK
180541. BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT
180542. BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK
180543. BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT
180544. BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK
180545. BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT
180546. BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK
180547. BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT
180548. BIF_XDMA_HI_IND__BIF_XDMA_UPPER_BOUND_MASK
180549. BIF_XDMA_HI_IND__BIF_XDMA_UPPER_BOUND__SHIFT
180550. BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK
180551. BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT
180552. BIF_XDMA_LO_IND__BIF_XDMA_APER_EN_MASK
180553. BIF_XDMA_LO_IND__BIF_XDMA_APER_EN__SHIFT
180554. BIF_XDMA_LO_IND__BIF_XDMA_LOWER_BOUND_MASK
180555. BIF_XDMA_LO_IND__BIF_XDMA_LOWER_BOUND__SHIFT
180556. BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK
180557. BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT
180558. BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK
180559. BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT
180560. BIG
180561. BIGDIRENDNAME
180562. BIGDIRSTARTNAME
180563. BIGEND
180564. BIGENDIAN_CPU
180565. BIGFROMCCK
180566. BIGHEADS
180567. BIGMAC2_REGISTER_BMAC_CONTROL
180568. BIGMAC2_REGISTER_BMAC_XGXS_CONTROL
180569. BIGMAC2_REGISTER_CNT_MAX_SIZE
180570. BIGMAC2_REGISTER_PFC_CONTROL
180571. BIGMAC2_REGISTER_RX_CONTROL
180572. BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS
180573. BIGMAC2_REGISTER_RX_LSS_STAT
180574. BIGMAC2_REGISTER_RX_MAX_SIZE
180575. BIGMAC2_REGISTER_RX_STAT_GR64
180576. BIGMAC2_REGISTER_RX_STAT_GRIPJ
180577. BIGMAC2_REGISTER_RX_STAT_GRPP
180578. BIGMAC2_REGISTER_TX_CONTROL
180579. BIGMAC2_REGISTER_TX_MAX_SIZE
180580. BIGMAC2_REGISTER_TX_PAUSE_CONTROL
180581. BIGMAC2_REGISTER_TX_SOURCE_ADDR
180582. BIGMAC2_REGISTER_TX_STAT_GTBYT
180583. BIGMAC2_REGISTER_TX_STAT_GTPOK
180584. BIGMAC2_REGISTER_TX_STAT_GTPP
180585. BIGMAC_IMASK_ACNTEXP
180586. BIGMAC_IMASK_CCNTEXP
180587. BIGMAC_IMASK_CVCNTEXP
180588. BIGMAC_IMASK_DTIMEXP
180589. BIGMAC_IMASK_ECNTEXP
180590. BIGMAC_IMASK_FCNTEXP
180591. BIGMAC_IMASK_GOTFRAME
180592. BIGMAC_IMASK_LCCNTEXP
180593. BIGMAC_IMASK_LCNTEXP
180594. BIGMAC_IMASK_MAXPKTERR
180595. BIGMAC_IMASK_NCNTEXP
180596. BIGMAC_IMASK_RCNTEXP
180597. BIGMAC_IMASK_RFIFOVF
180598. BIGMAC_IMASK_SENTFRAME
180599. BIGMAC_IMASK_TFIFO_UND
180600. BIGMAC_PHY_EXTERNAL
180601. BIGMAC_PHY_INTERNAL
180602. BIGMAC_REGISTER_BMAC_CONTROL
180603. BIGMAC_REGISTER_BMAC_XGXS_CONTROL
180604. BIGMAC_REGISTER_CNT_MAX_SIZE
180605. BIGMAC_REGISTER_RX_CONTROL
180606. BIGMAC_REGISTER_RX_LLFC_MSG_FLDS
180607. BIGMAC_REGISTER_RX_LSS_STATUS
180608. BIGMAC_REGISTER_RX_MAX_SIZE
180609. BIGMAC_REGISTER_RX_STAT_GR64
180610. BIGMAC_REGISTER_RX_STAT_GRIPJ
180611. BIGMAC_REGISTER_TX_CONTROL
180612. BIGMAC_REGISTER_TX_MAX_SIZE
180613. BIGMAC_REGISTER_TX_PAUSE_THRESHOLD
180614. BIGMAC_REGISTER_TX_SOURCE_ADDR
180615. BIGMAC_REGISTER_TX_STAT_GTBYT
180616. BIGMAC_REGISTER_TX_STAT_GTPKT
180617. BIGMAC_RXCFG_AENABLE
180618. BIGMAC_RXCFG_DCRCS
180619. BIGMAC_RXCFG_DERR
180620. BIGMAC_RXCFG_ENABLE
180621. BIGMAC_RXCFG_FIFO
180622. BIGMAC_RXCFG_HENABLE
180623. BIGMAC_RXCFG_ME
180624. BIGMAC_RXCFG_PGRP
180625. BIGMAC_RXCFG_PMISC
180626. BIGMAC_RXCFG_PSTRIP
180627. BIGMAC_RXCFG_REJME
180628. BIGMAC_STAT_ACNTEXP
180629. BIGMAC_STAT_CCNTEXP
180630. BIGMAC_STAT_CVCNTEXP
180631. BIGMAC_STAT_DTIMEXP
180632. BIGMAC_STAT_ECNTEXP
180633. BIGMAC_STAT_FCNTEXP
180634. BIGMAC_STAT_GOTFRAME
180635. BIGMAC_STAT_LCCNTEXP
180636. BIGMAC_STAT_LCNTEXP
180637. BIGMAC_STAT_MAXPKTERR
180638. BIGMAC_STAT_NCNTEXP
180639. BIGMAC_STAT_RCNTEXP
180640. BIGMAC_STAT_RFIFOVF
180641. BIGMAC_STAT_SENTFRAME
180642. BIGMAC_STAT_TFIFO_UND
180643. BIGMAC_TXCFG_CIGN
180644. BIGMAC_TXCFG_DBACKOFF
180645. BIGMAC_TXCFG_DGIVEUP
180646. BIGMAC_TXCFG_ENABLE
180647. BIGMAC_TXCFG_FCSOFF
180648. BIGMAC_TXCFG_FIFO
180649. BIGMAC_TXCFG_FULLDPLX
180650. BIGMAC_TXCFG_SMODE
180651. BIGMAC_XCFG_LANCE
180652. BIGMAC_XCFG_LIPG0
180653. BIGMAC_XCFG_MIIDISAB
180654. BIGMAC_XCFG_MLBACK
180655. BIGMAC_XCFG_ODENABLE
180656. BIGMAC_XCFG_RESV
180657. BIGMAC_XCFG_SMODE
180658. BIGMAC_XCFG_SQENABLE
180659. BIGMAC_XCFG_SQETWIN
180660. BIGMAC_XCFG_XLBACK
180661. BIGNOTLITTLE
180662. BIGSECS
180663. BIG_BUFFER_SIZE
180664. BIG_CHUNK_GAP
180665. BIG_CPI
180666. BIG_ENDIAN
180667. BIG_ENDIAN_HOST
180668. BIG_ENDIAN_MODE
180669. BIG_IOCTL32_Command_struct
180670. BIG_IOCTL_Command_struct
180671. BIG_JOINER_ENABLE
180672. BIG_KERNEL_PAGE_SHIFT
180673. BIG_KERNEL_PAGE_SIZE
180674. BIG_KEY_DEC
180675. BIG_KEY_ENC
180676. BIG_KEY_FILE_THRESHOLD
180677. BIG_KEY_IV_SIZE
180678. BIG_LS
180679. BIG_RAM_NAME_LEN
180680. BILINEAR_PRECISION_6_BIT
180681. BILINEAR_PRECISION_8_BIT
180682. BILLION
180683. BIMC_CLK_SRC
180684. BIMC_DDR_CLK_SRC
180685. BIMC_DDR_CPLL0_ROOT_CLK_SRC
180686. BIMC_DDR_CPLL1_ROOT_CLK_SRC
180687. BIMC_GDSC
180688. BIMC_GPU_CLK_SRC
180689. BIMC_HMSS_AXI_CLK_SRC
180690. BIMC_PLL
180691. BIMC_PLL_VOTE
180692. BIMM
180693. BIM_BUFFER_ADDR_MASK
180694. BIM_BUFFER_WR_SELECT
180695. BIM_CFG_32BIT
180696. BIM_CFG_64BIT_DISABLE
180697. BIM_CFG_66MHZ
180698. BIM_CFG_BIM_DISABLE
180699. BIM_CFG_BIM_STATUS
180700. BIM_CFG_DPAR_INTR_ENABLE
180701. BIM_CFG_PERROR_BLOCK
180702. BIM_CFG_RESERVED0
180703. BIM_CFG_RESERVED1
180704. BIM_CFG_RESERVED2
180705. BIM_CFG_RMA_INTR_ENABLE
180706. BIM_CFG_RTA_INTR_ENABLE
180707. BIM_DIAG_BRST_SM_MASK
180708. BIM_DIAG_MSTR_SM_MASK
180709. BIM_LOCAL_DEV_EXT
180710. BIM_LOCAL_DEV_HW_RESET
180711. BIM_LOCAL_DEV_PAD
180712. BIM_LOCAL_DEV_PROM
180713. BIM_LOCAL_DEV_SOFT_0
180714. BIM_LOCAL_DEV_SOFT_1
180715. BIM_RAM_BIST_RD_HI_PASS
180716. BIM_RAM_BIST_RD_LOW_PASS
180717. BIM_RAM_BIST_RD_PASS
180718. BIM_RAM_BIST_RD_START
180719. BIM_RAM_BIST_WR_HI_PASS
180720. BIM_RAM_BIST_WR_LOW_PASS
180721. BIM_RAM_BIST_WR_PASS
180722. BIM_RAM_BIST_WR_START
180723. BIN0_PULSE
180724. BIN1_PULSE
180725. BINARY_PRINT_ADDR
180726. BINARY_PRINT_CHAR_DATA
180727. BINARY_PRINT_CHAR_PAD
180728. BINARY_PRINT_DATA_BEGIN
180729. BINARY_PRINT_DATA_END
180730. BINARY_PRINT_LINE_BEGIN
180731. BINARY_PRINT_LINE_END
180732. BINARY_PRINT_NUM_DATA
180733. BINARY_PRINT_NUM_PAD
180734. BINARY_PRINT_SEP
180735. BINARY_SIGNATURE
180736. BINDERFS_I
180737. BINDERFS_MAX_MINOR
180738. BINDERFS_MAX_MINOR_CAPPED
180739. BINDERFS_MAX_NAME
180740. BINDERFS_SUPER_MAGIC
180741. BINDER_BUFFER_FLAG_HAS_PARENT
180742. BINDER_CTL_ADD
180743. BINDER_CURRENT_PROTOCOL_VERSION
180744. BINDER_DEBUG_BUFFER_ALLOC
180745. BINDER_DEBUG_BUFFER_ALLOC_ASYNC
180746. BINDER_DEBUG_DEAD_BINDER
180747. BINDER_DEBUG_DEAD_TRANSACTION
180748. BINDER_DEBUG_DEATH_NOTIFICATION
180749. BINDER_DEBUG_FAILED_TRANSACTION
180750. BINDER_DEBUG_FREE_BUFFER
180751. BINDER_DEBUG_INTERNAL_REFS
180752. BINDER_DEBUG_OPEN_CLOSE
180753. BINDER_DEBUG_PRIORITY_CAP
180754. BINDER_DEBUG_READ_WRITE
180755. BINDER_DEBUG_SPINLOCKS
180756. BINDER_DEBUG_THREADS
180757. BINDER_DEBUG_TRANSACTION
180758. BINDER_DEBUG_TRANSACTION_COMPLETE
180759. BINDER_DEBUG_USER_ERROR
180760. BINDER_DEBUG_USER_REFS
180761. BINDER_DEFERRED_FLUSH
180762. BINDER_DEFERRED_RELEASE
180763. BINDER_GET_NODE_DEBUG_INFO
180764. BINDER_GET_NODE_INFO_FOR_REF
180765. BINDER_LOOPER_STATE_ENTERED
180766. BINDER_LOOPER_STATE_EXITED
180767. BINDER_LOOPER_STATE_INVALID
180768. BINDER_LOOPER_STATE_POLL
180769. BINDER_LOOPER_STATE_REGISTERED
180770. BINDER_LOOPER_STATE_WAITING
180771. BINDER_SET_CONTEXT_MGR
180772. BINDER_SET_CONTEXT_MGR_EXT
180773. BINDER_SET_IDLE_PRIORITY
180774. BINDER_SET_IDLE_TIMEOUT
180775. BINDER_SET_MAX_THREADS
180776. BINDER_STAT_COUNT
180777. BINDER_STAT_DEATH
180778. BINDER_STAT_NODE
180779. BINDER_STAT_PROC
180780. BINDER_STAT_REF
180781. BINDER_STAT_THREAD
180782. BINDER_STAT_TRANSACTION
180783. BINDER_STAT_TRANSACTION_COMPLETE
180784. BINDER_THREAD_EXIT
180785. BINDER_TYPE_BINDER
180786. BINDER_TYPE_FD
180787. BINDER_TYPE_FDA
180788. BINDER_TYPE_HANDLE
180789. BINDER_TYPE_PTR
180790. BINDER_TYPE_WEAK_BINDER
180791. BINDER_TYPE_WEAK_HANDLE
180792. BINDER_VERSION
180793. BINDER_WORK_CLEAR_DEATH_NOTIFICATION
180794. BINDER_WORK_DEAD_BINDER
180795. BINDER_WORK_DEAD_BINDER_AND_CLEAR
180796. BINDER_WORK_NODE
180797. BINDER_WORK_RETURN_ERROR
180798. BINDER_WORK_TRANSACTION
180799. BINDER_WORK_TRANSACTION_COMPLETE
180800. BINDER_WRITE_READ
180801. BINDEX
180802. BINDING_CONTEXT_CMD
180803. BIND_ANY_ADDR
180804. BIND_FN_ALL
180805. BIND_PIRQ__WILL_SHARE
180806. BIND_REJECT
180807. BINFMTFS_MAGIC
180808. BINNER_BREAK_BATCH
180809. BINNER_DROP
180810. BINNER_DROP_ASSERT
180811. BINNER_PIPELINE
180812. BINNING
180813. BINNING_ALLOWED
180814. BINPRM_BUF_SIZE
180815. BINPRM_FLAGS_ENFORCE_NONDUMP
180816. BINPRM_FLAGS_ENFORCE_NONDUMP_BIT
180817. BINPRM_FLAGS_EXECFD
180818. BINPRM_FLAGS_EXECFD_BIT
180819. BINPRM_FLAGS_PATH_INACCESSIBLE
180820. BINPRM_FLAGS_PATH_INACCESSIBLE_BIT
180821. BINTDIFCLKENABLE
180822. BINTEN
180823. BINTF_WIN_LEN_CFG
180824. BIN_ATTR
180825. BIN_ATTR_RO
180826. BIN_ATTR_RW
180827. BIN_ATTR_WO
180828. BIN_AUDIO_OUT
180829. BIN_BUF_DBG_ATTN_BLOCKS
180830. BIN_BUF_DBG_ATTN_INDEXES
180831. BIN_BUF_DBG_ATTN_NAME_OFFSETS
180832. BIN_BUF_DBG_ATTN_REGS
180833. BIN_BUF_DBG_BUS_BLOCKS
180834. BIN_BUF_DBG_BUS_BLOCKS_USER_DATA
180835. BIN_BUF_DBG_BUS_LINES
180836. BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS
180837. BIN_BUF_DBG_DUMP_MEM
180838. BIN_BUF_DBG_DUMP_REG
180839. BIN_BUF_DBG_IDLE_CHK_IMMS
180840. BIN_BUF_DBG_IDLE_CHK_PARSING_DATA
180841. BIN_BUF_DBG_IDLE_CHK_REGS
180842. BIN_BUF_DBG_IDLE_CHK_RULES
180843. BIN_BUF_DBG_MODE_TREE
180844. BIN_BUF_DBG_PARSING_STRINGS
180845. BIN_BUF_INIT_CMD
180846. BIN_BUF_INIT_FW_VER_INFO
180847. BIN_BUF_INIT_IRO
180848. BIN_BUF_INIT_MODE_TREE
180849. BIN_BUF_INIT_VAL
180850. BIN_CONF_OVERRIDE_CHECK
180851. BIN_MAP_MODE_NONE
180852. BIN_MAP_MODE_POPS
180853. BIN_MAP_MODE_RTA_INDEX
180854. BIN_SAMPLE
180855. BIN_SIZE_128_PIXELS
180856. BIN_SIZE_256_PIXELS
180857. BIN_SIZE_32_PIXELS
180858. BIN_SIZE_512_PIXELS
180859. BIN_SIZE_64_PIXELS
180860. BINapp0F8
180861. BINapp0I
180862. BINapp1I
180863. BINattr
180864. BINovly
180865. BIODASDABORTIO
180866. BIODASDALLOWIO
180867. BIODASDCHECKFMT
180868. BIODASDCMFDISABLE
180869. BIODASDCMFENABLE
180870. BIODASDDISABLE
180871. BIODASDENABLE
180872. BIODASDFMT
180873. BIODASDGATTR
180874. BIODASDINFO
180875. BIODASDINFO2
180876. BIODASDPRRD
180877. BIODASDPRRST
180878. BIODASDPSRD
180879. BIODASDQUIESCE
180880. BIODASDRAS
180881. BIODASDREADALLCMB
180882. BIODASDRESUME
180883. BIODASDRLSE
180884. BIODASDRSRV
180885. BIODASDSATTR
180886. BIODASDSLCK
180887. BIODASDSNID
180888. BIODASDSYMMIO
180889. BIOS
180890. BIOS32_SIGNATURE
180891. BIOSADR
180892. BIOSET_NEED_BVECS
180893. BIOSET_NEED_RESCUER
180894. BIOSFibPath
180895. BIOSIDCodeAddr
180896. BIOSLOG
180897. BIOSOFFSET
180898. BIOSPage1_t
180899. BIOSPage2_t
180900. BIOSPage4_t
180901. BIOSSEG
180902. BIOS_0_SCRATCH
180903. BIOS_1_SCRATCH
180904. BIOS_2_SCRATCH
180905. BIOS_3_SCRATCH
180906. BIOS_4_SCRATCH
180907. BIOS_5_SCRATCH
180908. BIOS_6_SCRATCH
180909. BIOS_7_SCRATCH
180910. BIOS_ADDR
180911. BIOS_BASE
180912. BIOS_BEGIN
180913. BIOS_BSIZE
180914. BIOS_BUG_MSG
180915. BIOS_CALL_CONSOLE_WRITE
180916. BIOS_CALL_ETH_NODE_ADDR
180917. BIOS_CALL_GDB_DETACH
180918. BIOS_CALL_SHUTDOWN
180919. BIOS_CLIENT
180920. BIOS_CLKID
180921. BIOS_CMD_TABLE_PARA_REVISION
180922. BIOS_CMD_TABLE_REVISION
180923. BIOS_CNTL
180924. BIOS_CNTL_LOCK_ENABLE_MASK
180925. BIOS_CNTL_REG_NEW
180926. BIOS_CNTL_REG_OLD
180927. BIOS_CNTL_WRITE_ENABLE_MASK
180928. BIOS_CODELEN
180929. BIOS_CODESEG
180930. BIOS_CONFIG
180931. BIOS_CTRL_AIPP_DIS
180932. BIOS_CTRL_BIOS
180933. BIOS_CTRL_BIOS_REMOVABLE
180934. BIOS_CTRL_BOOTABLE_CD
180935. BIOS_CTRL_DISPLAY_MSG
180936. BIOS_CTRL_EXTENDED_XLAT
180937. BIOS_CTRL_GT_2_DISK
180938. BIOS_CTRL_INIT_VERBOSE
180939. BIOS_CTRL_MULTIPLE_LUN
180940. BIOS_CTRL_NO_SCAM
180941. BIOS_CTRL_RESET_SCSI_BUS
180942. BIOS_CTRL_SCSI_PARITY
180943. BIOS_DATA_OFFSET
180944. BIOS_EN
180945. BIOS_ENABLE
180946. BIOS_ENABLED
180947. BIOS_END
180948. BIOS_FREQ_BASE_INTERVAL_TIMER
180949. BIOS_FREQ_BASE_PLATFORM
180950. BIOS_FREQ_BASE_REALTIME_CLOCK
180951. BIOS_ID_OFFS
180952. BIOS_IMAGE_SIZE_OFFSET
180953. BIOS_IMAGE_SIZE_UNIT
180954. BIOS_IN16
180955. BIOS_IN32
180956. BIOS_IN8
180957. BIOS_IN_USE
180958. BIOS_IPC
180959. BIOS_LAST_OFFSET
180960. BIOS_LOCK_ENABLE
180961. BIOS_MEMCONSOLE_V1_MAGIC
180962. BIOS_MEMCONSOLE_V2_MAGIC
180963. BIOS_MSG_CODE_LIC_CHALLENGE
180964. BIOS_MSG_CODE_LIC_RESPONSE
180965. BIOS_MSG_CODE_VIRT_MAC_ISCSI
180966. BIOS_MSG_CODE_VIRT_MAC_PRIM
180967. BIOS_OFFSET_INC
180968. BIOS_OFFSET_LIMIT
180969. BIOS_PARAMETER_BLOCK
180970. BIOS_PFN
180971. BIOS_PFN_END
180972. BIOS_PVT_DATA
180973. BIOS_RAM_SIZE_KB_PTR
180974. BIOS_REGION_BASE
180975. BIOS_REGION_SIZE
180976. BIOS_RELATIVE_CARD
180977. BIOS_ROM
180978. BIOS_ROM_BASE
180979. BIOS_ROM_DIS
180980. BIOS_ROM_END
180981. BIOS_SCAN_LIMIT
180982. BIOS_SCRATCH_0_IND__BIOS_SCRATCH_0_MASK
180983. BIOS_SCRATCH_0_IND__BIOS_SCRATCH_0__SHIFT
180984. BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK
180985. BIOS_SCRATCH_0__BIOS_SCRATCH_0__MASK
180986. BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT
180987. BIOS_SCRATCH_10_IND__BIOS_SCRATCH_10_MASK
180988. BIOS_SCRATCH_10_IND__BIOS_SCRATCH_10__SHIFT
180989. BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK
180990. BIOS_SCRATCH_10__BIOS_SCRATCH_10__MASK
180991. BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT
180992. BIOS_SCRATCH_11_IND__BIOS_SCRATCH_11_MASK
180993. BIOS_SCRATCH_11_IND__BIOS_SCRATCH_11__SHIFT
180994. BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK
180995. BIOS_SCRATCH_11__BIOS_SCRATCH_11__MASK
180996. BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT
180997. BIOS_SCRATCH_12_IND__BIOS_SCRATCH_12_MASK
180998. BIOS_SCRATCH_12_IND__BIOS_SCRATCH_12__SHIFT
180999. BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK
181000. BIOS_SCRATCH_12__BIOS_SCRATCH_12__MASK
181001. BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT
181002. BIOS_SCRATCH_13_IND__BIOS_SCRATCH_13_MASK
181003. BIOS_SCRATCH_13_IND__BIOS_SCRATCH_13__SHIFT
181004. BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK
181005. BIOS_SCRATCH_13__BIOS_SCRATCH_13__MASK
181006. BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT
181007. BIOS_SCRATCH_14_IND__BIOS_SCRATCH_14_MASK
181008. BIOS_SCRATCH_14_IND__BIOS_SCRATCH_14__SHIFT
181009. BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK
181010. BIOS_SCRATCH_14__BIOS_SCRATCH_14__MASK
181011. BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT
181012. BIOS_SCRATCH_15_IND__BIOS_SCRATCH_15_MASK
181013. BIOS_SCRATCH_15_IND__BIOS_SCRATCH_15__SHIFT
181014. BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK
181015. BIOS_SCRATCH_15__BIOS_SCRATCH_15__MASK
181016. BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT
181017. BIOS_SCRATCH_1_IND__BIOS_SCRATCH_1_MASK
181018. BIOS_SCRATCH_1_IND__BIOS_SCRATCH_1__SHIFT
181019. BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK
181020. BIOS_SCRATCH_1__BIOS_SCRATCH_1__MASK
181021. BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT
181022. BIOS_SCRATCH_2_IND__BIOS_SCRATCH_2_MASK
181023. BIOS_SCRATCH_2_IND__BIOS_SCRATCH_2__SHIFT
181024. BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK
181025. BIOS_SCRATCH_2__BIOS_SCRATCH_2__MASK
181026. BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT
181027. BIOS_SCRATCH_3_IND__BIOS_SCRATCH_3_MASK
181028. BIOS_SCRATCH_3_IND__BIOS_SCRATCH_3__SHIFT
181029. BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK
181030. BIOS_SCRATCH_3__BIOS_SCRATCH_3__MASK
181031. BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT
181032. BIOS_SCRATCH_4
181033. BIOS_SCRATCH_4_IND__BIOS_SCRATCH_4_MASK
181034. BIOS_SCRATCH_4_IND__BIOS_SCRATCH_4__SHIFT
181035. BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK
181036. BIOS_SCRATCH_4__BIOS_SCRATCH_4__MASK
181037. BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT
181038. BIOS_SCRATCH_5_IND__BIOS_SCRATCH_5_MASK
181039. BIOS_SCRATCH_5_IND__BIOS_SCRATCH_5__SHIFT
181040. BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK
181041. BIOS_SCRATCH_5__BIOS_SCRATCH_5__MASK
181042. BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT
181043. BIOS_SCRATCH_6_IND__BIOS_SCRATCH_6_MASK
181044. BIOS_SCRATCH_6_IND__BIOS_SCRATCH_6__SHIFT
181045. BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK
181046. BIOS_SCRATCH_6__BIOS_SCRATCH_6__MASK
181047. BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT
181048. BIOS_SCRATCH_7_IND__BIOS_SCRATCH_7_MASK
181049. BIOS_SCRATCH_7_IND__BIOS_SCRATCH_7__SHIFT
181050. BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK
181051. BIOS_SCRATCH_7__BIOS_SCRATCH_7__MASK
181052. BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT
181053. BIOS_SCRATCH_8_IND__BIOS_SCRATCH_8_MASK
181054. BIOS_SCRATCH_8_IND__BIOS_SCRATCH_8__SHIFT
181055. BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK
181056. BIOS_SCRATCH_8__BIOS_SCRATCH_8__MASK
181057. BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT
181058. BIOS_SCRATCH_9_IND__BIOS_SCRATCH_9_MASK
181059. BIOS_SCRATCH_9_IND__BIOS_SCRATCH_9__SHIFT
181060. BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK
181061. BIOS_SCRATCH_9__BIOS_SCRATCH_9__MASK
181062. BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT
181063. BIOS_SERVER
181064. BIOS_SIGNATURE
181065. BIOS_SIGNATURE_COREBOOT
181066. BIOS_SIGNATURE_TINYBIOS
181067. BIOS_START_MAX
181068. BIOS_START_MIN
181069. BIOS_START_SEG
181070. BIOS_STATUS_ABORT
181071. BIOS_STATUS_EINVAL
181072. BIOS_STATUS_MORE_PASSES
181073. BIOS_STATUS_SUCCESS
181074. BIOS_STATUS_UNAVAIL
181075. BIOS_STATUS_UNIMPLEMENTED
181076. BIOS_TRANSLATION_25563
181077. BIOS_TRANSLATION_6432
181078. BIOS_VERSION
181079. BIOS_WRITE_ENABLE
181080. BIO_BOUNCED
181081. BIO_BUG_ON
181082. BIO_CHAIN
181083. BIO_CLONED
181084. BIO_DEBUG
181085. BIO_EMPTY_LIST
181086. BIO_FLAG_LAST
181087. BIO_INLINE_VECS
181088. BIO_ISSUE_RES_BITS
181089. BIO_ISSUE_RES_MASK
181090. BIO_ISSUE_RES_SHIFT
181091. BIO_ISSUE_SIZE_BITS
181092. BIO_ISSUE_SIZE_MASK
181093. BIO_ISSUE_SIZE_SHIFT
181094. BIO_ISSUE_THROTL_SKIP_LATENCY
181095. BIO_ISSUE_TIME_MASK
181096. BIO_MAX_PAGES
181097. BIO_NO_PAGE_REF
181098. BIO_NULL_MAPPED
181099. BIO_POOL_SIZE
181100. BIO_QUEUE_ENTERED
181101. BIO_QUIET
181102. BIO_REFFED
181103. BIO_RESET_BITS
181104. BIO_RESET_BYTES
181105. BIO_SPECIAL
181106. BIO_SPLIT_ENTRIES
181107. BIO_THROTTLED
181108. BIO_TRACE_COMPLETION
181109. BIO_TRACKED
181110. BIO_USER_MAPPED
181111. BIO_WORKINGSET
181112. BIP_AAD_SIZE
181113. BIP_BLOCK_INTEGRITY
181114. BIP_CTRL_NOCHECK
181115. BIP_DISK_NOCHECK
181116. BIP_INLINE_VECS
181117. BIP_IP_CHECKSUM
181118. BIP_MAPPED_INTEGRITY
181119. BIP_MAX_KEYID
181120. BIP_RANGE
181121. BIQPATH_CONTROL
181122. BIQUAD_COEFF_COUNT
181123. BIQUAD_COEFS
181124. BIQUAD_SIZE
181125. BIR_G
181126. BIR_M
181127. BIR_S
181128. BIR_V
181129. BIST
181130. BIST0_FUSE_FLAG
181131. BIST0_NOW
181132. BIST0_SRAM_FAIL
181133. BIST1_FUSE_FLAG
181134. BIST1_NOW
181135. BIST1_SRAM_FAIL
181136. BISTCMD_TSTATRX
181137. BISTCMD_TSTATTX
181138. BISTCMD_TSTERR
181139. BISTCMD_TSTITTX
181140. BISTCMD_TSTMODE
181141. BISTCMD_TSTPAT0
181142. BISTCMD_TSTPAT5
181143. BISTCMD_TSTPATA
181144. BISTCMD_TSTPATF
181145. BISTCMD_TSTRX
181146. BISTCONF_REG
181147. BISTCSR
181148. BISTCTL0
181149. BISTCTL1
181150. BISTEN_AT
181151. BISTEN_ETM
181152. BISTEN_LSB
181153. BISTEN_PORT_SEL
181154. BISTSR0_BISTGO
181155. BISTSR1_TSTSR
181156. BISTSR2_CMDPRTEN
181157. BISTSR2_RAMTSTEN
181158. BIST_CMD_GAP_S
181159. BIST_CMD_GAP_V
181160. BIST_COMMAND
181161. BIST_ERR
181162. BIST_ERROR_STATE
181163. BIST_ERR_ADR0
181164. BIST_ERR_ADR1
181165. BIST_ERR_ADR2
181166. BIST_ERR_ADR3
181167. BIST_ERR_CNT_LSB
181168. BIST_ERR_CNT_MSB
181169. BIST_ERR_SEL_LSB
181170. BIST_ERR_SEL_MSB
181171. BIST_OPCODE_S
181172. BIST_OPCODE_V
181173. BIST_PORT_SELECT
181174. BIST_STAT
181175. BIST_STAT2
181176. BIST_STATUS
181177. BIST_VID_PLL_AB_STAT
181178. BIST_VID_PLL_CD_STAT
181179. BIST_VID_PLL_EF_STAT
181180. BIST_VID_PLL_GH_STAT
181181. BIST_WAIT_DELAY_COUNT
181182. BIST_WAIT_DELAY_MS
181183. BIST__BIST_CAP_MASK
181184. BIST__BIST_CAP__MASK
181185. BIST__BIST_CAP__SHIFT
181186. BIST__BIST_COMP_MASK
181187. BIST__BIST_COMP__MASK
181188. BIST__BIST_COMP__SHIFT
181189. BIST__BIST_STRT_MASK
181190. BIST__BIST_STRT__MASK
181191. BIST__BIST_STRT__SHIFT
181192. BISYNC
181193. BIS_CERT
181194. BIT
181195. BIT0
181196. BIT00
181197. BIT01
181198. BIT02
181199. BIT03
181200. BIT04
181201. BIT05
181202. BIT06
181203. BIT07
181204. BIT08
181205. BIT09
181206. BIT1
181207. BIT10
181208. BIT11
181209. BIT12
181210. BIT13
181211. BIT14
181212. BIT15
181213. BIT16
181214. BIT17
181215. BIT18
181216. BIT19
181217. BIT2
181218. BIT20
181219. BIT21
181220. BIT22
181221. BIT23
181222. BIT24
181223. BIT25
181224. BIT26
181225. BIT27
181226. BIT28
181227. BIT29
181228. BIT2BYTE
181229. BIT3
181230. BIT30
181231. BIT31
181232. BIT32
181233. BIT33
181234. BIT34
181235. BIT35
181236. BIT36
181237. BIT4
181238. BIT5
181239. BIT6
181240. BIT63
181241. BIT7
181242. BIT8
181243. BIT9
181244. BITBANG_CS_ACTIVE
181245. BITBANG_CS_INACTIVE
181246. BITBIT_NR
181247. BITBIT_SIZE
181248. BITBLT
181249. BITBLT_CNTL
181250. BITBLT_COMMAND_REG
181251. BITBLT_CONTROL
181252. BITBLT_START_REG
181253. BITBLT_STATUS
181254. BITBUCKET
181255. BITC
181256. BITCLR
181257. BITFIELD2
181258. BITFIELD3
181259. BITFIELD4
181260. BITFIELD5
181261. BITFIELD6
181262. BITFIELD_MASK
181263. BITLINE_INF
181264. BITMAP_ATTR
181265. BITMAP_AUTO_DS
181266. BITMAP_BLOCK_SHIFT
181267. BITMAP_BLOCK_SIZE
181268. BITMAP_CHUNK_BITS
181269. BITMAP_CHUNK_SIZE
181270. BITMAP_CSUM_XOR
181271. BITMAP_FIRST_BYTE_MASK
181272. BITMAP_FIRST_WORD_MASK
181273. BITMAP_FLUSH_INTERVAL
181274. BITMAP_FROM_U64
181275. BITMAP_GRANULARITY
181276. BITMAP_H
181277. BITMAP_HOSTENDIAN
181278. BITMAP_IO
181279. BITMAP_IO_QUEUED
181280. BITMAP_LAST_BYTE_MASK
181281. BITMAP_LAST_WORD_MASK
181282. BITMAP_LEN
181283. BITMAP_LOC
181284. BITMAP_MAGIC
181285. BITMAP_MAJOR_CLUSTERED
181286. BITMAP_MAJOR_HI
181287. BITMAP_MAJOR_HOSTENDIAN
181288. BITMAP_MAJOR_LO
181289. BITMAP_MEM_ALIGNMENT
181290. BITMAP_MEM_MASK
181291. BITMAP_NEEDS_SYNC
181292. BITMAP_NO_RR
181293. BITMAP_OP_CLEAR
181294. BITMAP_OP_SET
181295. BITMAP_OP_TEST_ALL_CLEAR
181296. BITMAP_OP_TEST_ALL_SET
181297. BITMAP_PAGE_DIRTY
181298. BITMAP_PAGE_NEEDWRITE
181299. BITMAP_PAGE_PENDING
181300. BITMAP_RESIZE
181301. BITMAP_RR
181302. BITMAP_SHIFT
181303. BITMAP_STALE
181304. BITMAP_STA_PS
181305. BITMAP_VERSION
181306. BITMAP_VERSION_MASK
181307. BITMAP_VERSION_SHIFT
181308. BITMAP_VERSION_SMASK
181309. BITMAP_WRITE_ERROR
181310. BITMASK
181311. BITMASK_BCN_RSSI_HIGH
181312. BITMASK_BCN_RSSI_LOW
181313. BITMASK_SIZE
181314. BITNUM
181315. BITOFF_CAL
181316. BITOP_BE32_SWIZZLE
181317. BITOP_LE_SWIZZLE
181318. BITRATE
181319. BITRATE_DEFAULT
181320. BITRATE_DEFAULT_PEAK
181321. BITRATE_MAX
181322. BITRATE_MIN
181323. BITRATE_STEP
181324. BITRATE_TABLE_SIZE
181325. BITRATE_TARGET
181326. BITS
181327. BITS64
181328. BITSET
181329. BITSET_BIT
181330. BITSET_CLR
181331. BITSET_IS_SET
181332. BITSET_SET
181333. BITSET_SIZE
181334. BITSET_T
181335. BITSET_WORD
181336. BITSFUNC
181337. BITSFUNC2
181338. BITSFUNC3
181339. BITSPERBYTE
181340. BITSPERPAGE
181341. BITSSET
181342. BITSTR
181343. BITSTREAM_H_MODULE
181344. BITSTREAM_OFFSET_MASK
181345. BITS_1
181346. BITS_2
181347. BITS_3
181348. BITS_31_0
181349. BITS_32_1
181350. BITS_33_2
181351. BITS_34_3
181352. BITS_35_4
181353. BITS_36_5
181354. BITS_37_6
181355. BITS_38_7
181356. BITS_4
181357. BITS_5
181358. BITS_6
181359. BITS_7
181360. BITS_8
181361. BITS_ACK
181362. BITS_ADR
181363. BITS_BADDEST
181364. BITS_BADOPC
181365. BITS_BN
181366. BITS_BOT_MB
181367. BITS_CCIE
181368. BITS_CFINT
181369. BITS_CHIP_VER
181370. BITS_CKE
181371. BITS_CMD
181372. BITS_COMPOUND
181373. BITS_CSADR
181374. BITS_C_VC
181375. BITS_DATA
181376. BITS_DATA_5
181377. BITS_DATA_6
181378. BITS_DATA_7
181379. BITS_DATA_8
181380. BITS_DATA_9
181381. BITS_DATA_MASK
181382. BITS_DN
181383. BITS_EF_ADDR
181384. BITS_ENBL
181385. BITS_EREGNO
181386. BITS_ERRRCV
181387. BITS_ERRSNT
181388. BITS_FN
181389. BITS_FOR_PGD
181390. BITS_FOR_PTE
181391. BITS_GET
181392. BITS_INTDL
181393. BITS_INTMAC
181394. BITS_INTPM
181395. BITS_INTTL
181396. BITS_INT_RX_CTRL
181397. BITS_INT_RX_ERP
181398. BITS_INT_RX_VC0_CPL
181399. BITS_INT_RX_VC0_NonPosted
181400. BITS_INT_RX_VC0_Posted
181401. BITS_INT_RX_VCX_CPL
181402. BITS_INT_RX_VCX_NonPosted
181403. BITS_INT_RX_VCX_Posted
181404. BITS_INT_TX_CTRL
181405. BITS_INT_TX_VC0_CPL
181406. BITS_INT_TX_VC0_NonPosted
181407. BITS_INT_TX_VC0_Posted
181408. BITS_INT_TX_VCX_CPL
181409. BITS_INT_TX_VCX_NonPosted
181410. BITS_INT_TX_VCX_Posted
181411. BITS_IN_COMMAND
181412. BITS_IN_DWORD
181413. BITS_LAMRn
181414. BITS_LANE
181415. BITS_LAREn
181416. BITS_LARn
181417. BITS_LOCK
181418. BITS_MASK
181419. BITS_MCODE
181420. BITS_MDATA
181421. BITS_MROUTE
181422. BITS_MSGADRH
181423. BITS_MSGADRL
181424. BITS_MSGIE
181425. BITS_M_VC
181426. BITS_PAH
181427. BITS_PAL
181428. BITS_PAM
181429. BITS_PARE
181430. BITS_PARITY_EVEN
181431. BITS_PARITY_MARK
181432. BITS_PARITY_MASK
181433. BITS_PARITY_NONE
181434. BITS_PARITY_ODD
181435. BITS_PARITY_SPACE
181436. BITS_PDR
181437. BITS_PER_ARRAY_ENTRY
181438. BITS_PER_BITMAP
181439. BITS_PER_BYTE
181440. BITS_PER_BYTE_MASK
181441. BITS_PER_BYTE_MASKED
181442. BITS_PER_COMPAT_LONG
181443. BITS_PER_EVTCHN_WORD
181444. BITS_PER_GPO
181445. BITS_PER_INDEX_STREAM
181446. BITS_PER_LONG
181447. BITS_PER_LONG_COMPAT
181448. BITS_PER_LONG_LONG
181449. BITS_PER_LONG_MASK
181450. BITS_PER_MPI_LIMB
181451. BITS_PER_OBJ
181452. BITS_PER_PAGE
181453. BITS_PER_PAGE_MASK
181454. BITS_PER_PGD
181455. BITS_PER_PGD_ENTRY
181456. BITS_PER_PIXEL
181457. BITS_PER_PMD
181458. BITS_PER_PMD_ENTRY
181459. BITS_PER_PTE
181460. BITS_PER_PTE_ENTRY
181461. BITS_PER_PTR
181462. BITS_PER_REG
181463. BITS_PER_REGISTER
181464. BITS_PER_SLOT
181465. BITS_PER_STEP_BCH
181466. BITS_PER_STEP_RS
181467. BITS_PER_TYPE
181468. BITS_PER_U128
181469. BITS_PER_U64
181470. BITS_PER_UNIT
181471. BITS_PER_WAKEREF
181472. BITS_PER_XA_VALUE
181473. BITS_RANGE
181474. BITS_REGNO
181475. BITS_RFC_DIRECT
181476. BITS_ROUNDDOWN_BYTES
181477. BITS_ROUNDUP_BYTES
181478. BITS_RRSR_RSC
181479. BITS_RXAGC_CCK
181480. BITS_RXAGC_OFDM
181481. BITS_RXGCK_CCK_FIFOTHR
181482. BITS_RXGCK_HT_FIFOTHR
181483. BITS_RXGCK_OFDM_FIFOTHR
181484. BITS_RXGCK_VHT_FIFOTHR
181485. BITS_RXPSF_ERRTHR
181486. BITS_RXPSF_PKTLENTHR
181487. BITS_RX_BQ_DEPTH_EN
181488. BITS_RX_BQ_START_ADDR_EN
181489. BITS_RX_BQ_WR_ADDR_EN
181490. BITS_RX_EN
181491. BITS_RX_FLUSH_CMD
181492. BITS_RX_FLUSH_FLAG_DOWN
181493. BITS_RX_FLUSH_FLAG_UP
181494. BITS_RX_FQ_DEPTH_EN
181495. BITS_RX_FQ_RD_ADDR_EN
181496. BITS_RX_FQ_START_ADDR_EN
181497. BITS_RX_IQ_WEIGHT
181498. BITS_RX_STOP
181499. BITS_SET
181500. BITS_SHIFT_CLEAR
181501. BITS_SHIFT_MASK
181502. BITS_SHIFT_NEXT_LEVEL
181503. BITS_SHIFT_VAL
181504. BITS_SHPRI
181505. BITS_SNPMD
181506. BITS_SPC
181507. BITS_STOP_1
181508. BITS_STOP_1_5
181509. BITS_STOP_2
181510. BITS_STOP_MASK
181511. BITS_SUBTUNE
181512. BITS_TC
181513. BITS_TOP_MB
181514. BITS_TO_32BIT
181515. BITS_TO_BYTES
181516. BITS_TO_COMPAT_LONGS
181517. BITS_TO_HIDX
181518. BITS_TO_LONGS
181519. BITS_TO_LONGS_COMPAT
181520. BITS_TO_U32
181521. BITS_TO_U64
181522. BITS_TX_BQ_DEPTH_EN
181523. BITS_TX_BQ_RD_ADDR_EN
181524. BITS_TX_BQ_START_ADDR_EN
181525. BITS_TX_EN
181526. BITS_TX_FLUSH_CMD
181527. BITS_TX_FLUSH_FLAG_DOWN
181528. BITS_TX_FLUSH_FLAG_UP
181529. BITS_TX_RQ_DEPTH_EN
181530. BITS_TX_RQ_START_ADDR_EN
181531. BITS_TX_RQ_WR_ADDR_EN
181532. BITS_TX_STOP
181533. BITS_TYPE
181534. BITS_T_VC
181535. BITS_UNSOLRESP
181536. BITS_VC_ID
181537. BITS_VENDOR_ID
181538. BIT_0
181539. BIT_1
181540. BIT_10
181541. BIT_11
181542. BIT_12
181543. BIT_13
181544. BIT_14
181545. BIT_15
181546. BIT_16
181547. BIT_17
181548. BIT_18
181549. BIT_19
181550. BIT_2
181551. BIT_20
181552. BIT_21
181553. BIT_22
181554. BIT_23
181555. BIT_24
181556. BIT_25
181557. BIT_26
181558. BIT_27
181559. BIT_28
181560. BIT_29
181561. BIT_3
181562. BIT_30
181563. BIT_31
181564. BIT_32K_CAL_TMR_EN
181565. BIT_3WIRE_PI_ON
181566. BIT_3WIRE_RX_EN
181567. BIT_3WIRE_TX_EN
181568. BIT_4
181569. BIT_5
181570. BIT_6
181571. BIT_64
181572. BIT_7
181573. BIT_8
181574. BIT_9
181575. BIT_AAP
181576. BIT_AB
181577. BIT_AC
181578. BIT_ACRC32
181579. BIT_ADD3
181580. BIT_ADDR_CH_ERR_INT
181581. BIT_AICV
181582. BIT_ALICE0_ZONE_CTRL_ICRST_N
181583. BIT_ALICE0_ZONE_CTRL_USE_INT_DIV20
181584. BIT_ALL_CNT_RST
181585. BIT_AM
181586. BIT_ANAPAR_BTPS
181587. BIT_ANA_PORT_EN
181588. BIT_APM
181589. BIT_APPEND
181590. BIT_APP_BASSN
181591. BIT_APP_FCS
181592. BIT_APP_ICV
181593. BIT_APP_MIC
181594. BIT_APP_PHYSTS
181595. BIT_APP_UPCHG
181596. BIT_APWRMGT
181597. BIT_ARG16
181598. BIT_ARG32
181599. BIT_ARG8
181600. BIT_AUTO_INIT_LLT
181601. BIT_AUTO_INIT_LLT_V1
181602. BIT_BACKLIGHT_OFF
181603. BIT_BACKLIGHT_ON
181604. BIT_BASEADDR_CHG_ERR_EN
181605. BIT_BASEADDR_SWITCH_EN
181606. BIT_BASEADDR_SWITCH_SEL
181607. BIT_BAT_CHARGE_STATUS_OVERTEMP
181608. BIT_BAT_CHARGE_STATUS_PRECHG
181609. BIT_BAT_POWER_ACIN
181610. BIT_BAT_POWER_ON
181611. BIT_BAT_POWER_S3
181612. BIT_BAT_STATE_CHARGING
181613. BIT_BAT_STATE_DISCHARGING
181614. BIT_BAT_STATUS_DESTROY
181615. BIT_BAT_STATUS_FULL
181616. BIT_BAT_STATUS_IN
181617. BIT_BAT_STATUS_LOW
181618. BIT_BA_PARSER_EN
181619. BIT_BB_CCK_CHECK_EN
181620. BIT_BCN_PORT_SEL
181621. BIT_BCN_VALID_V1
181622. BIT_BC_DROP_EN
181623. BIT_BC_MD_EN
181624. BIT_BGR_BIAS_BGR_EN
181625. BIT_BIST_ALWAYS_ON
181626. BIT_BIST_EN
181627. BIT_BIST_RESET
181628. BIT_BIST_START_BIT
181629. BIT_BIST_START_SEL
181630. BIT_BIST_TRANS
181631. BIT_BOOT_FROM_ROM
181632. BIT_BOOT_FSPI_EN
181633. BIT_BTCCA_CTRL
181634. BIT_BTGP_JTAG_EN
181635. BIT_BTGP_SPI_EN
181636. BIT_BT_AOD_GPIO3
181637. BIT_BT_DIG_CLK_EN
181638. BIT_BT_FUNC_EN
181639. BIT_BT_INT_EN
181640. BIT_BT_PTA_EN
181641. BIT_BW_RXBB
181642. BIT_BW_TXBB
181643. BIT_BYPASS_DPD
181644. BIT_BYTE
181645. BIT_CAF_OSC_DIG_XTAL_STABLE
181646. BIT_CAF_OSC_XTAL_EN
181647. BIT_CAMERA_CONTROL_OFF
181648. BIT_CAMERA_CONTROL_ON
181649. BIT_CAMERA_STATUS_OFF
181650. BIT_CAMERA_STATUS_ON
181651. BIT_CAM_BYPASS
181652. BIT_CAM_ERROR
181653. BIT_CAM_OVERCURR
181654. BIT_CAM_PRESENT
181655. BIT_CAM_READY
181656. BIT_CAM_RESET
181657. BIT_CAM_STCHG
181658. BIT_CANCELLED_COMMAND
181659. BIT_CAR_PERST_RST
181660. BIT_CBSSID_BCN
181661. BIT_CBSSID_DATA
181662. BIT_CBUS3_CNVT_CBUS3CNVT_EN
181663. BIT_CBUS3_CNVT_TEARCBUS_EN
181664. BIT_CBUS_CEC_ABORT
181665. BIT_CBUS_CMD_ABORT
181666. BIT_CBUS_CNX_CHG
181667. BIT_CBUS_DDC_ABORT
181668. BIT_CBUS_HPD_CHG
181669. BIT_CBUS_MHL12_DISCON_INT
181670. BIT_CBUS_MHL3_DISCON_INT
181671. BIT_CBUS_MSC_ABORT_RCVD
181672. BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_DDC_ON_CBUS
181673. BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_DDC_ERRORCODE
181674. BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_VS1_ERRORCODE
181675. BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_MSC_ON_CBUS
181676. BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN
181677. BIT_CBUS_MSC_MR_MSC_MSG
181678. BIT_CBUS_MSC_MR_SET_INT
181679. BIT_CBUS_MSC_MR_WRITE_BURST
181680. BIT_CBUS_MSC_MR_WRITE_STAT
181681. BIT_CBUS_MSC_MT_DONE
181682. BIT_CBUS_MSC_MT_DONE_NACK
181683. BIT_CBUS_RESET
181684. BIT_CBUS_STATUS_CBUS_CONNECTED
181685. BIT_CBUS_STATUS_CBUS_HPD
181686. BIT_CBUS_STATUS_MHL_CABLE_PRESENT
181687. BIT_CBUS_STATUS_MHL_MODE
181688. BIT_CBUS_STATUS_MSC_HB_SUCCESS
181689. BIT_CCIR_EN
181690. BIT_CCIR_MODE
181691. BIT_CCK_BLK_EN
181692. BIT_CCK_FA_RST
181693. BIT_CCK_OFDM_BLK_EN
181694. BIT_CEA_NEW_AVI
181695. BIT_CEA_NEW_VSI
181696. BIT_CH
181697. BIT_CHECK_CCK_EN
181698. BIT_CHECK_SUM_OK
181699. BIT_CHIP_VER
181700. BIT_CLEAR_CHIP_VER
181701. BIT_CLEAR_RXPSF_ERRTHR
181702. BIT_CLEAR_RXPSF_PKTLENTHR
181703. BIT_CLEAR_VENDOR_ID
181704. BIT_CLK_ALL_ON
181705. BIT_CLK_MASTER
181706. BIT_CLOSED_ON_HOST
181707. BIT_CLR
181708. BIT_CLR_H2CQ_HOST_IDX
181709. BIT_CLR_H2CQ_HW_IDX
181710. BIT_CLR_RXFIFO
181711. BIT_CLR_STATFIFO
181712. BIT_COC_CALIBRATION_DONE
181713. BIT_COC_CTL15_COC_CTRL15_7
181714. BIT_COC_CTL3_COC_CTRL3_7
181715. BIT_COC_CTL6_COC_CTRL6_6
181716. BIT_COC_CTL6_COC_CTRL6_7
181717. BIT_COC_CTL7_COC_CTRL7_5
181718. BIT_COC_CTL7_COC_CTRL7_6
181719. BIT_COC_CTL7_COC_CTRL7_7
181720. BIT_COC_CTLD_COC_CTRLD_7
181721. BIT_COC_CTLE_COC_CTRLE_7
181722. BIT_COC_MISC_CTL0_FSM_MON
181723. BIT_COC_PLL_LOCK_STATUS_CHANGE
181724. BIT_COC_STAT_0_PLL_LOCKED
181725. BIT_COF_INT
181726. BIT_COF_INT_EN
181727. BIT_COMMECNT_I2C_TO_EMSC_EN
181728. BIT_COM_RX_GCK_EN
181729. BIT_CONSTANT
181730. BIT_CONTROL_0
181731. BIT_CPU_CLK_EN
181732. BIT_CRC_ERR_PASS
181733. BIT_CRT_DETECT_PLUG
181734. BIT_CRT_DETECT_UNPLUG
181735. BIT_CSI_HW_ENABLE
181736. BIT_CStream_t
181737. BIT_CTRL1_GPIO_I_6
181738. BIT_CTRL1_GPIO_I_7
181739. BIT_CTRL1_GPIO_I_8
181740. BIT_CTRL1_GPIO_OEN_6
181741. BIT_CTRL1_GPIO_OEN_7
181742. BIT_CTRL1_GPIO_OEN_8
181743. BIT_CTRL_GPIO_I_2
181744. BIT_CTRL_GPIO_I_3
181745. BIT_CTRL_GPIO_I_4
181746. BIT_CTRL_GPIO_I_5
181747. BIT_CTRL_GPIO_OEN_2
181748. BIT_CTRL_GPIO_OEN_3
181749. BIT_CTRL_GPIO_OEN_4
181750. BIT_CTRL_GPIO_OEN_5
181751. BIT_DA
181752. BIT_DATA_FROM_MIPI
181753. BIT_DATA_MODE
181754. BIT_DBG_GNT_WL_BT
181755. BIT_DCB_MODE
181756. BIT_DCTL_CTS_TCK_PHASE
181757. BIT_DCTL_EXT_DDC_SEL
181758. BIT_DCTL_HSIC_CLK_PHASE
181759. BIT_DCTL_HSIC_RX_STROBE_PHASE
181760. BIT_DCTL_HSIC_TX_BIST_START_SEL
181761. BIT_DCTL_TCLKNX_PHASE
181762. BIT_DCTL_TDM_LCLK_PHASE
181763. BIT_DCTL_TRANSCODE
181764. BIT_DDC_CMD_DDC_FLT_EN
181765. BIT_DDC_CMD_DONE
181766. BIT_DDC_CMD_HDCP_DDC_EN
181767. BIT_DDC_CMD_SDA_DEL_EN
181768. BIT_DDC_DOUT_CNT_DDC_DELAY_CNT_8
181769. BIT_DDC_MANUAL_DDCM_ABORT_WP
181770. BIT_DDC_MANUAL_DSCL
181771. BIT_DDC_MANUAL_DSDA
181772. BIT_DDC_MANUAL_GCP_HW_CTL_EN
181773. BIT_DDC_MANUAL_IO_DSCL
181774. BIT_DDC_MANUAL_IO_DSDA
181775. BIT_DDC_MANUAL_MAN_DDC
181776. BIT_DDC_MANUAL_VP_SEL
181777. BIT_DDC_STATUS_DDC_BUS_LOW
181778. BIT_DDC_STATUS_DDC_FIFO_EMPTY
181779. BIT_DDC_STATUS_DDC_FIFO_FULL
181780. BIT_DDC_STATUS_DDC_FIFO_READ_IN_SUE
181781. BIT_DDC_STATUS_DDC_FIFO_WRITE_IN_USE
181782. BIT_DDC_STATUS_DDC_I2C_IN_PROG
181783. BIT_DDC_STATUS_DDC_NO_ACK
181784. BIT_DDMACH0_CHKSUM_CONT
181785. BIT_DDMACH0_CHKSUM_EN
181786. BIT_DDMACH0_CHKSUM_STS
181787. BIT_DDMACH0_OWN
181788. BIT_DDMACH0_RESET_CHKSUM_STS
181789. BIT_DDMA_EN
181790. BIT_DEINTERLACE_EN
181791. BIT_DEPTH_16
181792. BIT_DEPTH_20
181793. BIT_DEPTH_24
181794. BIT_DEPTH_32
181795. BIT_DEPTH_8
181796. BIT_DE_PWR_TRIM
181797. BIT_DE_TRXBW
181798. BIT_DE_TX_GAIN
181799. BIT_DFX
181800. BIT_DIFFERED_COMMAND
181801. BIT_DISCHKPPDLLEN
181802. BIT_DISC_CTRL1_CBUS_INTR_EN
181803. BIT_DISC_CTRL1_DISC_EN
181804. BIT_DISC_CTRL1_HB_ONLY
181805. BIT_DISC_CTRL5_DSM_OVRIDE
181806. BIT_DISC_CTRL8_DELAY_CBUS_INTR_EN
181807. BIT_DISC_CTRL8_NOMHLINT_CLR_BYPASS
181808. BIT_DISC_CTRL9_DISC_PULSE_PROCEED
181809. BIT_DISC_CTRL9_MHL3DISC_EN
181810. BIT_DISC_CTRL9_MHL3_RSEN_BYP
181811. BIT_DISC_CTRL9_NOMHL_EST
181812. BIT_DISC_CTRL9_VBUS_OUTPUT_CAPABILITY_SRC
181813. BIT_DISC_CTRL9_WAKE_DRVFLT
181814. BIT_DISC_CTRL9_WAKE_PULSE_BYPASS
181815. BIT_DISC_STAT1_PSM_OVRIDE
181816. BIT_DISC_STAT2_CBUS_OE_POL
181817. BIT_DISC_STAT2_CBUS_SATUS
181818. BIT_DISC_STAT2_RSEN
181819. BIT_DISDECMYPKT
181820. BIT_DISPLAY_LCD_OFF
181821. BIT_DISPLAY_LCD_ON
181822. BIT_DIS_LSIG_CFE
181823. BIT_DIS_SECOND_CCA
181824. BIT_DIS_STBC_CFE
181825. BIT_DIS_TSF_UDT
181826. BIT_DIS_TXOP_CFE
181827. BIT_DIVIDER_MIPS
181828. BIT_DMA_EP_MISC_ICR_FW_INT
181829. BIT_DMA_EP_MISC_ICR_HALP
181830. BIT_DMA_EP_MISC_ICR_RX_HTRSH
181831. BIT_DMA_EP_MISC_ICR_TX_NO_ACT
181832. BIT_DMA_EP_RX_ICR_RX_DONE
181833. BIT_DMA_EP_RX_ICR_RX_HTRSH
181834. BIT_DMA_EP_TX_ICR_TX_DONE
181835. BIT_DMA_EP_TX_ICR_TX_DONE_N
181836. BIT_DMA_ERROR
181837. BIT_DMA_IRQ
181838. BIT_DMA_ITR_CNT_CRL_CLR
181839. BIT_DMA_ITR_CNT_CRL_EN
181840. BIT_DMA_ITR_CNT_CRL_EXT_TICK
181841. BIT_DMA_ITR_CNT_CRL_FOREVER
181842. BIT_DMA_ITR_CNT_CRL_REACH_TRSH
181843. BIT_DMA_ITR_RX_CNT_CTL_CLR
181844. BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN
181845. BIT_DMA_ITR_RX_CNT_CTL_EN
181846. BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL
181847. BIT_DMA_ITR_RX_CNT_CTL_FOREVER
181848. BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG
181849. BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH
181850. BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR
181851. BIT_DMA_ITR_RX_IDL_CNT_CTL_EN
181852. BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL
181853. BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER
181854. BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH
181855. BIT_DMA_ITR_TX_CNT_CTL_CLR
181856. BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN
181857. BIT_DMA_ITR_TX_CNT_CTL_EN
181858. BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL
181859. BIT_DMA_ITR_TX_CNT_CTL_FOREVER
181860. BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG
181861. BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH
181862. BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR
181863. BIT_DMA_ITR_TX_IDL_CNT_CTL_EN
181864. BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL
181865. BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER
181866. BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH
181867. BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC
181868. BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN
181869. BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC
181870. BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN
181871. BIT_DMA_PSEUDO_CAUSE_MISC
181872. BIT_DMA_PSEUDO_CAUSE_RX
181873. BIT_DMA_PSEUDO_CAUSE_TX
181874. BIT_DMA_REFLASH_RFF
181875. BIT_DMA_REFLASH_SFF
181876. BIT_DMA_REQ_EN_RFF
181877. BIT_DMA_REQ_EN_SFF
181878. BIT_DMA_RUN
181879. BIT_DMA_TSF_DONE_FB1
181880. BIT_DMA_TSF_DONE_FB2
181881. BIT_DMA_TSF_DONE_SFF
181882. BIT_DMEM_CHKSUM_OK
181883. BIT_DMEM_DW_OK
181884. BIT_DOC_CTL6_DOC_CTRL6_6
181885. BIT_DOC_CTL6_DOC_CTRL6_7
181886. BIT_DOC_CTL7_DOC_CTRL7_5
181887. BIT_DOC_CTL7_DOC_CTRL7_6
181888. BIT_DOC_CTL7_DOC_CTRL7_7
181889. BIT_DOC_CTL8_DOC_CTRL8_7
181890. BIT_DOC_CTLE_DOC_CTRLE_6
181891. BIT_DOC_CTLE_DOC_CTRLE_7
181892. BIT_DPDT_SEL_EN
181893. BIT_DPDT_WL_SEL
181894. BIT_DPD_CLK
181895. BIT_DPD_EN
181896. BIT_DPD_OSC_EN
181897. BIT_DPD_PDIDCK_N
181898. BIT_DPD_PDNRX12
181899. BIT_DPD_PDNTX12
181900. BIT_DPD_PD_MHL_CLK_N
181901. BIT_DPD_PWRON_HSIC
181902. BIT_DPD_PWRON_PLL
181903. BIT_DRDY
181904. BIT_DStream_completed
181905. BIT_DStream_endOfBuffer
181906. BIT_DStream_overflow
181907. BIT_DStream_status
181908. BIT_DStream_t
181909. BIT_DStream_unfinished
181910. BIT_DUMMY_FCS_READY_MASK_EN
181911. BIT_DURATION
181912. BIT_DZC
181913. BIT_DZE
181914. BIT_ECC_AUTO_EN
181915. BIT_ECC_INT
181916. BIT_ECC_INT_EN
181917. BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP
181918. BIT_EDID_CTRL_EDID_FIFO_ACCESS_ALWAYS_EN
181919. BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
181920. BIT_EDID_CTRL_EDID_FIFO_BLOCK_SEL
181921. BIT_EDID_CTRL_EDID_MODE_EN
181922. BIT_EDID_CTRL_EDID_PRIME_VALID
181923. BIT_EDID_CTRL_INVALID_BKSV
181924. BIT_EDID_CTRL_XDEVCAP_EN
181925. BIT_EF_FLAG
181926. BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR
181927. BIT_EMSCINTRMASK1_EMSC_INTRMASK1_0
181928. BIT_EMSCINTR_EMSC_COMMA_CHAR_ERR
181929. BIT_EMSCINTR_EMSC_RFIFO_READ_ERR
181930. BIT_EMSCINTR_EMSC_XFIFO_EMPTY
181931. BIT_EMSCINTR_EMSC_XFIFO_WRITE_ERR
181932. BIT_EMSCINTR_EMSC_XMIT_ACK_TOUT
181933. BIT_EMSCINTR_EMSC_XMIT_DONE
181934. BIT_EMSCINTR_EMSC_XMIT_GNT_TOUT
181935. BIT_EMSCINTR_SPI_DVLD
181936. BIT_ENMBID
181937. BIT_ENSWBCN
181938. BIT_EN_BCNQ_DL
181939. BIT_EN_BCN_FUNCTION
181940. BIT_EN_EOF_V1
181941. BIT_EN_FREE_CNT
181942. BIT_EN_GNT_BT_AWAKE
181943. BIT_EN_PRECNT
181944. BIT_EN_WR_FREE_TAIL
181945. BIT_EO
181946. BIT_EOF_INT
181947. BIT_EOF_INT_EN
181948. BIT_EP
181949. BIT_ERRPKT
181950. BIT_EXT_TIA_BW
181951. BIT_EXT_VSYNC
181952. BIT_F1_INT
181953. BIT_F2_INT
181954. BIT_FAN_AUTO
181955. BIT_FAN_CONTROL_OFF
181956. BIT_FAN_CONTROL_ON
181957. BIT_FAN_MANUAL
181958. BIT_FAN_STATUS_OFF
181959. BIT_FAN_STATUS_ON
181960. BIT_FAST_INTR_STAT_BLOCK
181961. BIT_FAST_INTR_STAT_COC
181962. BIT_FAST_INTR_STAT_DDC
181963. BIT_FAST_INTR_STAT_DISC
181964. BIT_FAST_INTR_STAT_EDID
181965. BIT_FAST_INTR_STAT_G2WB
181966. BIT_FAST_INTR_STAT_G2WB_ERR
181967. BIT_FAST_INTR_STAT_HDCP
181968. BIT_FAST_INTR_STAT_HDCP2
181969. BIT_FAST_INTR_STAT_INFR
181970. BIT_FAST_INTR_STAT_INT2
181971. BIT_FAST_INTR_STAT_LTRN
181972. BIT_FAST_INTR_STAT_MERR
181973. BIT_FAST_INTR_STAT_MSC
181974. BIT_FAST_INTR_STAT_SCDT
181975. BIT_FAST_INTR_STAT_TDM
181976. BIT_FAST_INTR_STAT_TIMR
181977. BIT_FA_RESET
181978. BIT_FB1_DMA_DONE_INTEN
181979. BIT_FB2_DMA_DONE_INTEN
181980. BIT_FCC
181981. BIT_FCGC_HSIC_ENABLE
181982. BIT_FCGC_HSIC_HOSTMODE
181983. BIT_FD_DRAW_FACE_FRAME
181984. BIT_FD_DRAW_SMILE_LVL
181985. BIT_FD_EN
181986. BIT_FD_GMM
181987. BIT_FD_ISH
181988. BIT_FEN_BB_GLB_RST
181989. BIT_FEN_BB_RSTB
181990. BIT_FEN_CPUEN
181991. BIT_FIELD
181992. BIT_FIELD0_INT
181993. BIT_FIELD1_INT
181994. BIT_FIFO_EMPTY
181995. BIT_FIFO_FULL
181996. BIT_FMP_HEADER
181997. BIT_FMP_MULTICHANNEL
181998. BIT_FMP_SD
181999. BIT_FMT16
182000. BIT_FMT32
182001. BIT_FMT8
182002. BIT_FREECLK_EXIST
182003. BIT_FRMCNT
182004. BIT_FRMCNT_RST
182005. BIT_FSPI_EN
182006. BIT_FW_DW_RDY
182007. BIT_FW_INIT_RDY
182008. BIT_GAIN_TXBB
182009. BIT_GAP
182010. BIT_GBE
182011. BIT_GCLK_MODE
182012. BIT_GENCTL_CLR_EMSC_RFIFO
182013. BIT_GENCTL_CLR_EMSC_XFIFO
182014. BIT_GENCTL_DIS_XMIT_ERR_STATE
182015. BIT_GENCTL_EMSC_EN
182016. BIT_GENCTL_SPEC_TRANS_DIS
182017. BIT_GENCTL_SPI_MISO_EDGE
182018. BIT_GENCTL_SPI_MOSI_EDGE
182019. BIT_GENCTL_START_TRAIN_SEQ
182020. BIT_GET_CHIP_VER
182021. BIT_GET_RXPSF_ERRTHR
182022. BIT_GET_VENDOR_ID
182023. BIT_GLOSS_DB
182024. BIT_GNT_BT_POLARITY
182025. BIT_GPIO12
182026. BIT_GS_PWSF
182027. BIT_H2CQ_FULL
182028. BIT_HARDWARE
182029. BIT_HCI_RXDMA_EN
182030. BIT_HCI_TXDMA_EN
182031. BIT_HDA
182032. BIT_HDCP2X_CTRL_0_HDCP2X_EN
182033. BIT_HDCP2X_CTRL_0_HDCP2X_ENCRYPT_EN
182034. BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX
182035. BIT_HDCP2X_CTRL_0_HDCP2X_HDMIMODE
182036. BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_OVR
182037. BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_SEL
182038. BIT_HDCP2X_CTRL_0_HDCP2X_PRECOMPUTE
182039. BIT_HDCP2X_CTRL_0_HDCP2X_REPEATER
182040. BIT_HDCP2X_CTRL_1_HDCP2X_CTL3MSK
182041. BIT_HDCP2X_CTRL_1_HDCP2X_HPD_OVR
182042. BIT_HDCP2X_CTRL_1_HDCP2X_HPD_SW
182043. BIT_HDCP2X_CTRL_1_HDCP2X_REAUTH_SW
182044. BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD
182045. BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD_START
182046. BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR
182047. BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR_START
182048. BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_XFER_START
182049. BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_EN
182050. BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_GNT
182051. BIT_HDCP2X_POLL_CS_HDCP2X_MSG_SZ_CLR_OPTION
182052. BIT_HDCP2X_POLL_CS_HDCP2X_REAUTH_REQ_CLR_OPTION
182053. BIT_HDCP2X_POLL_CS_HDCP2X_RPT_READY_CLR_OPTION
182054. BIT_HPAL_PERST_FROM_PAD
182055. BIT_HPD_CTRL_GPIO_I_0
182056. BIT_HPD_CTRL_GPIO_I_1
182057. BIT_HPD_CTRL_GPIO_OEN_0
182058. BIT_HPD_CTRL_GPIO_OEN_1
182059. BIT_HPD_CTRL_HPD_DS_SIGNAL
182060. BIT_HPD_CTRL_HPD_HIGH
182061. BIT_HPD_CTRL_HPD_OUT_OD_EN
182062. BIT_HPD_CTRL_HPD_OUT_OVR_EN
182063. BIT_HRESP_ERR_EN
182064. BIT_HRESP_ERR_INT
182065. BIT_HRXCTRL3_HRX_OUT_EN
182066. BIT_HRXCTRL3_HRX_STAY_RESET
182067. BIT_HRXCTRL3_STATUS_EN
182068. BIT_HSYNC_POL
182069. BIT_HTC_LOC_CTRL
182070. BIT_HTXCTRL_HTX_ALLSBE_SOP
182071. BIT_HTXCTRL_HTX_DRVCONN1
182072. BIT_HTXCTRL_HTX_DRVRST1
182073. BIT_HTXCTRL_HTX_RGDINV_USB
182074. BIT_HTXCTRL_HTX_RSPTDM_BUSY
182075. BIT_IE
182076. BIT_ILLEGAL0
182077. BIT_ILLEGAL1
182078. BIT_ILLEGAL2
182079. BIT_ILLEGAL3
182080. BIT_ILLEGAL4
182081. BIT_ILLEGAL5
182082. BIT_ILLEGAL6
182083. BIT_ILLEGAL7
182084. BIT_IMEM_BOOT_LOAD_CHECKSUM_OK
182085. BIT_IMEM_CHKSUM_OK
182086. BIT_IMEM_DW_OK
182087. BIT_INNER_LB
182088. BIT_INQST_MASK_ALLIRQ
182089. BIT_INQST_MASK_EOF
182090. BIT_INQST_MASK_ERROR_BS
182091. BIT_INQST_MASK_OVERFLOW
182092. BIT_INQST_MASK_PAUSE
182093. BIT_INQST_MASK_UNDERFLOW
182094. BIT_INTEDGE
182095. BIT_INTR9_DEVCAP_DONE
182096. BIT_INTR9_EDID_DONE
182097. BIT_INTR9_EDID_ERROR
182098. BIT_INTR_SCDT_CHANGE
182099. BIT_INTR_STATE_INTR_STATE
182100. BIT_INT_CTRL_INTR_OD
182101. BIT_INT_CTRL_INTR_POLARITY
182102. BIT_INT_CTRL_SOFTWARE_WP
182103. BIT_INV_DATA
182104. BIT_INV_PCLK
182105. BIT_IOC
182106. BIT_IOE
182107. BIT_IQ_SWITCH
182108. BIT_IXC
182109. BIT_IXE
182110. BIT_LB_ATT
182111. BIT_LB_SW
182112. BIT_LDOE25_PON
182113. BIT_LD_RQPN
182114. BIT_LED1DIS
182115. BIT_LED_GREEN_CHARGE
182116. BIT_LED_NUMLOCK
182117. BIT_LED_ORANGE_POWER
182118. BIT_LED_RED_CHARGE
182119. BIT_LED_RED_POWER
182120. BIT_LED_TEST_IN
182121. BIT_LED_TEST_OUT
182122. BIT_LEN_MASK_16
182123. BIT_LEN_MASK_32
182124. BIT_LEN_MASK_8
182125. BIT_LID_DETECT_OFF
182126. BIT_LID_DETECT_ON
182127. BIT_LINKSPEED
182128. BIT_LM_DDC_DDC_GPU_REQUEST
182129. BIT_LM_DDC_DDC_GRANT
182130. BIT_LM_DDC_DDC_TPI_SW
182131. BIT_LM_DDC_SW_TPI_EN_DISABLED
182132. BIT_LM_DDC_VIDEO_MUTE_EN
182133. BIT_LNAON_SEL_EN
182134. BIT_LNAON_WLBT_SEL
182135. BIT_LOAD
182136. BIT_LPC_CLOCK_RUN
182137. BIT_LPE
182138. BIT_LPSS1_F0_DMA
182139. BIT_LPSS1_F1_PWM1
182140. BIT_LPSS1_F2_PWM2
182141. BIT_LPSS1_F3_HSUART1
182142. BIT_LPSS1_F4_HSUART2
182143. BIT_LPSS1_F5_SPI
182144. BIT_LPSS1_F6_XXX
182145. BIT_LPSS1_F7_XXX
182146. BIT_LPSS2_F0_DMA
182147. BIT_LPSS2_F1_I2C1
182148. BIT_LPSS2_F2_I2C2
182149. BIT_LPSS2_F3_I2C3
182150. BIT_LPSS2_F4_I2C4
182151. BIT_LPSS2_F5_I2C5
182152. BIT_LPSS2_F6_I2C6
182153. BIT_LPSS2_F7_I2C7
182154. BIT_LSIGEN
182155. BIT_LTE_COEX_EN
182156. BIT_LTE_MUX_CTRL_PATH
182157. BIT_M3_CTRL_ENC_TMDS
182158. BIT_M3_CTRL_H2M_SWRST
182159. BIT_M3_CTRL_M3AV_EN
182160. BIT_M3_CTRL_MHL3_MASTER_EN
182161. BIT_M3_CTRL_SW_MHL3_SEL
182162. BIT_M3_P0CTRL_MHL3_P0_HDCP_EN
182163. BIT_M3_P0CTRL_MHL3_P0_HDCP_ENC_EN
182164. BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED
182165. BIT_M3_P0CTRL_MHL3_P0_PORT_EN
182166. BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN
182167. BIT_M3_SCTRL_MHL3_SCRAMBLER_EN
182168. BIT_MACFLT_ENA
182169. BIT_MACFLT_FW2CPU
182170. BIT_MACRXEN
182171. BIT_MACTXEN
182172. BIT_MAC_CLK_SEL
182173. BIT_MAC_PORT_EN
182174. BIT_MAC_SEC_EN
182175. BIT_MASK
182176. BIT_MASK_BCN_HEAD_1_V1
182177. BIT_MASK_CHIP_VER
182178. BIT_MASK_DDMACH0_DLEN
182179. BIT_MASK_DESCR
182180. BIT_MASK_EFUSE_BANK_SEL
182181. BIT_MASK_EF_ADDR
182182. BIT_MASK_EF_DATA
182183. BIT_MASK_RFE_INV89
182184. BIT_MASK_RFE_SEL89
182185. BIT_MASK_RXGCK_CCK_FIFOTHR
182186. BIT_MASK_RXGCK_HT_FIFOTHR
182187. BIT_MASK_RXGCK_OFDM_FIFOTHR
182188. BIT_MASK_RXGCK_VHT_FIFOTHR
182189. BIT_MASK_RXPSF_ERRTHR
182190. BIT_MASK_RXPSF_PKTLENTHR
182191. BIT_MASK_TXDMA_BEQ_MAP
182192. BIT_MASK_TXDMA_BKQ_MAP
182193. BIT_MASK_TXDMA_HIQ_MAP
182194. BIT_MASK_TXDMA_MGQ_MAP
182195. BIT_MASK_TXDMA_VIQ_MAP
182196. BIT_MASK_TXDMA_VOQ_MAP
182197. BIT_MASK_TXPKTNUM
182198. BIT_MASK_TXSC_20M
182199. BIT_MASK_TXSC_40M
182200. BIT_MASK_Tx_OQT_free_space
182201. BIT_MASK_VENDOR_ID
182202. BIT_MCLKDIV
182203. BIT_MCLKEN
182204. BIT_MCUFWDL_EN
182205. BIT_MC_MATCH_EN
182206. BIT_MDIO_WFLAG_V1
182207. BIT_MDT_IDLE_AFTER_HAWB_DISABLE
182208. BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN
182209. BIT_MDT_RCV_CTRL_MDT_DISABLE
182210. BIT_MDT_RCV_CTRL_MDT_RCV_EN
182211. BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_ALL
182212. BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR
182213. BIT_MDT_RCV_CTRL_MDT_RFIFO_OVER_WR_EN
182214. BIT_MDT_RCV_CTRL_MDT_XFIFO_OVER_WR_EN
182215. BIT_MDT_RCV_SM_ABORT_PKT_RCVD
182216. BIT_MDT_RCV_SM_ERROR
182217. BIT_MDT_RCV_TIMEOUT
182218. BIT_MDT_RFIFO_DATA_RDY
182219. BIT_MDT_XFIFO_EMPTY
182220. BIT_MDT_XFIFO_STAT_MDT_XMIT_PRE_HS_EN
182221. BIT_MDT_XMIT_CTRL_CLR_ABORT_WAIT
182222. BIT_MDT_XMIT_CTRL_CMD_MERGE_EN
182223. BIT_MDT_XMIT_CTRL_EN
182224. BIT_MDT_XMIT_CTRL_FIXED_AID
182225. BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN
182226. BIT_MDT_XMIT_CTRL_SINGLE_RUN_EN
182227. BIT_MDT_XMIT_CTRL_XFIFO_CLR_ALL
182228. BIT_MDT_XMIT_CTRL_XFIFO_CLR_CUR
182229. BIT_MDT_XMIT_SM_ABORT_PKT_RCVD
182230. BIT_MDT_XMIT_SM_ERROR
182231. BIT_MDT_XMIT_TIMEOUT
182232. BIT_MFBEN
182233. BIT_MHL3_EST_INT
182234. BIT_MHL3_TX_ZONE_CTL_MHL2_INTPLT_ZONE_MANU_EN
182235. BIT_MHL_CBUS_CTL0_CBUS_RGND_TEST_MODE
182236. BIT_MHL_COC_CTL0_COC_BIAS_EN
182237. BIT_MHL_COC_CTL1_COC_EN
182238. BIT_MHL_COC_CTL3_COC_AECHO_EN
182239. BIT_MHL_DOC_CTL0_DOC_RXBIAS_EN
182240. BIT_MHL_DOC_CTL0_DOC_RXDATA_EN
182241. BIT_MHL_DP_CTL0_DP_OE
182242. BIT_MHL_DP_CTL0_TX_OE_OVR
182243. BIT_MHL_DP_CTL2_CLK_BYPASS_EN
182244. BIT_MHL_DP_CTL5_RSEN_EN
182245. BIT_MHL_DP_CTL5_RSEN_EN_OVR
182246. BIT_MHL_DP_CTL6_DP_PRE_POST_SEL
182247. BIT_MHL_DP_CTL6_DP_TAP1_EN
182248. BIT_MHL_DP_CTL6_DP_TAP1_SGN
182249. BIT_MHL_DP_CTL6_DP_TAP2_EN
182250. BIT_MHL_DP_CTL6_DP_TAP2_SGN
182251. BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN
182252. BIT_MHL_EST_INT
182253. BIT_MHL_PLL_CTL0_AUD_CLK_EN
182254. BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
182255. BIT_MHL_PLL_CTL0_ZONE_MASK_OE
182256. BIT_MHL_PLL_CTL2_CLKDETECT_EN
182257. BIT_MHL_PLL_CTL2_MEAS_FVCO
182258. BIT_MHL_PLL_CTL2_PLL_FAST_LOCK
182259. BIT_MHL_TOP_CTL_MHL3_DOC_SEL
182260. BIT_MHL_TOP_CTL_MHL_PP_SEL
182261. BIT_MIPI_DATA_FORMAT_MASK
182262. BIT_MIPI_DATA_FORMAT_OFFSET
182263. BIT_MIPI_DATA_FORMAT_RAW10
182264. BIT_MIPI_DATA_FORMAT_RAW12
182265. BIT_MIPI_DATA_FORMAT_RAW14
182266. BIT_MIPI_DATA_FORMAT_RAW8
182267. BIT_MIPI_DATA_FORMAT_YUV422_8B
182268. BIT_MIPI_DOUBLE_CMPNT
182269. BIT_MIPI_YU_SWAP
182270. BIT_MO
182271. BIT_MODE_CHANGE_EN
182272. BIT_MONADIC
182273. BIT_MSC_COMMAND_START_DEBUG
182274. BIT_MSC_COMMAND_START_MSC_MSG
182275. BIT_MSC_COMMAND_START_PEER
182276. BIT_MSC_COMMAND_START_READ_DEVCAP
182277. BIT_MSC_COMMAND_START_WRITE_BURST
182278. BIT_MSC_COMMAND_START_WRITE_STAT
182279. BIT_MSC_HEARTBEAT_CTRL_MSC_HB_EN
182280. BIT_MSK
182281. BIT_NAME
182282. BIT_NAME_
182283. BIT_NBI_EN
182284. BIT_ND
182285. BIT_NE
182286. BIT_NEEDS_SW_FIX
182287. BIT_NOACKRSP
182288. BIT_NOTIFIED_COMMAND
182289. BIT_NOT_MHL_EST_INT
182290. BIT_NO_FLASH_INDICATION
182291. BIT_NTSC_EN
182292. BIT_OFC
182293. BIT_OFDM_FA_RST
182294. BIT_OFE
182295. BIT_OFFSET
182296. BIT_OFFSET_LEN_MASK_16
182297. BIT_OFFSET_LEN_MASK_32
182298. BIT_OFFSET_LEN_MASK_8
182299. BIT_OFS
182300. BIT_OFUL34_RDY_VALID_BUG_FIX_EN
182301. BIT_OP
182302. BIT_OPS
182303. BIT_ORED_DEDICATED_IRQ_GPSC
182304. BIT_ORED_DEDICATED_IRQ_GPSS
182305. BIT_OTG
182306. BIT_OTG_SS_PHY
182307. BIT_OTP_HW_SECTION_DONE_TALYN_MB
182308. BIT_OTP_SIGNATURE_ERR_TALYN_MB
182309. BIT_PACK_DIR
182310. BIT_PANCOORD
182311. BIT_PAPE_SEL_EN
182312. BIT_PAPE_WLBT_SEL
182313. BIT_PARALLEL24_EN
182314. BIT_PAUSE_EN
182315. BIT_PAUSE_FRM_PASS
182316. BIT_PCIE_PORT0
182317. BIT_PCIE_PORT1
182318. BIT_PCIE_PORT2
182319. BIT_PCIE_PORT3
182320. BIT_PCI_BCNQ_FLAG
182321. BIT_PER_PIX
182322. BIT_PFC
182323. BIT_PG_RX
182324. BIT_PG_TX
182325. BIT_PHY_ADDR_OFFSET
182326. BIT_PIXEL_BIT
182327. BIT_PKTCTL_DLEN
182328. BIT_PKT_FILTER_0_DROP_AIF_PKT
182329. BIT_PKT_FILTER_0_DROP_AVI_PKT
182330. BIT_PKT_FILTER_0_DROP_CEA_CP_PKT
182331. BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT
182332. BIT_PKT_FILTER_0_DROP_CTS_PKT
182333. BIT_PKT_FILTER_0_DROP_GCP_PKT
182334. BIT_PKT_FILTER_0_DROP_MPEG_PKT
182335. BIT_PKT_FILTER_0_DROP_SPIF_PKT
182336. BIT_PKT_FILTER_1_AVI_OVERRIDE_DIS
182337. BIT_PKT_FILTER_1_DROP_AUDIO_PKT
182338. BIT_PKT_FILTER_1_DROP_GEN2_PKT
182339. BIT_PKT_FILTER_1_DROP_GEN_PKT
182340. BIT_PKT_FILTER_1_DROP_VSIF_PKT
182341. BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS
182342. BIT_PMU_DEVICE_RDY
182343. BIT_PREINDEX
182344. BIT_PRE_TX_CMD
182345. BIT_PROMI
182346. BIT_PROTOCOL_EN
182347. BIT_PRP_IF_EN
182348. BIT_PTA_EDCCA_EN
182349. BIT_PTA_WL_TX_EN
182350. BIT_PT_OPT
182351. BIT_PWD_SRST_CBUS_RST
182352. BIT_PWD_SRST_CBUS_RST_SW
182353. BIT_PWD_SRST_CBUS_RST_SW_EN
182354. BIT_PWD_SRST_COC_DOC_RST
182355. BIT_PWD_SRST_HDCP2X_SW_RST
182356. BIT_PWD_SRST_MHLFIFO_RST
182357. BIT_PWD_SRST_SW_RST
182358. BIT_PWD_SRST_SW_RST_AUTO
182359. BIT_RD_CMD_BUSY
182360. BIT_RE
182361. BIT_REDGE
182362. BIT_RESERVED
182363. BIT_RESET_ON
182364. BIT_RFE_BUF_EN
182365. BIT_RFF_OR_INT
182366. BIT_RFMOD
182367. BIT_RFMOD_40M
182368. BIT_RFMOD_80M
182369. BIT_RFRST
182370. BIT_RF_EN
182371. BIT_RF_OR_INTEN
182372. BIT_RF_RSTB
182373. BIT_RF_SDM_RSTB
182374. BIT_RF_TYPE_ID
182375. BIT_RGND_READY_INT
182376. BIT_RPFM_CAM_ENABLE
182377. BIT_RPT_DGAIN
182378. BIT_RPT_SEL
182379. BIT_RPWM_TOGGLE
182380. BIT_RST_TRXDMA_INTF
182381. BIT_RTC_CTRL_REG_AUTO_COMP_M
182382. BIT_RTC_CTRL_REG_GET_TIME_M
182383. BIT_RTC_CTRL_REG_MODE_12_24_M
182384. BIT_RTC_CTRL_REG_ROUND_30S_M
182385. BIT_RTC_CTRL_REG_RTC_GET_TIME
182386. BIT_RTC_CTRL_REG_RTC_READSEL_M
182387. BIT_RTC_CTRL_REG_RTC_V_OPT
182388. BIT_RTC_CTRL_REG_SET_32_COUNTER_M
182389. BIT_RTC_CTRL_REG_STOP_RTC_M
182390. BIT_RTC_CTRL_REG_TEST_MODE_M
182391. BIT_RTC_INTERRUPTS_REG_EVERY_M
182392. BIT_RTC_INTERRUPTS_REG_IT_ALARM_M
182393. BIT_RTC_INTERRUPTS_REG_IT_TIMER_M
182394. BIT_RTC_STATUS_REG_1D_EVENT_M
182395. BIT_RTC_STATUS_REG_1H_EVENT_M
182396. BIT_RTC_STATUS_REG_1M_EVENT_M
182397. BIT_RTC_STATUS_REG_1S_EVENT_M
182398. BIT_RTC_STATUS_REG_ALARM_M
182399. BIT_RTC_STATUS_REG_POWER_UP_M
182400. BIT_RTC_STATUS_REG_RUN_M
182401. BIT_RTL_ID
182402. BIT_RU
182403. BIT_RUNT_PKT_EN
182404. BIT_RXAGC
182405. BIT_RXA_MIX_GAIN
182406. BIT_RXBIST_VGB_EN
182407. BIT_RXDECINV
182408. BIT_RXDMA_EN
182409. BIT_RXFF_INT
182410. BIT_RXFF_INTEN
182411. BIT_RXFF_LEVEL
182412. BIT_RXGCK_CCK_FIFOTHR
182413. BIT_RXGCK_FIFOTHR_EN
182414. BIT_RXGCK_HT_FIFOTHR
182415. BIT_RXGCK_OFDMCCA_EN
182416. BIT_RXGCK_OFDM_FIFOTHR
182417. BIT_RXGCK_VHT_FIFOTHR
182418. BIT_RXG_GAIN
182419. BIT_RXIE
182420. BIT_RXIF
182421. BIT_RXPSF_ALL_ERRCHKEN
182422. BIT_RXPSF_CCKCHKEN
182423. BIT_RXPSF_CCKRST
182424. BIT_RXPSF_CONT_ERRCHKEN
182425. BIT_RXPSF_CTRLEN
182426. BIT_RXPSF_ERRTHR
182427. BIT_RXPSF_HTCHKEN
182428. BIT_RXPSF_MHCHKEN
182429. BIT_RXPSF_OFDMCHKEN
182430. BIT_RXPSF_OFDMRST
182431. BIT_RXPSF_PKTLENTHR
182432. BIT_RXPSF_VHTCHKEN
182433. BIT_RXSK_PERPKT
182434. BIT_RX_HDMI_CLR_BUFFER_AIF_CLR_EN
182435. BIT_RX_HDMI_CLR_BUFFER_SWAP_VSI_IEEE_ID
182436. BIT_RX_HDMI_CLR_BUFFER_USE_AIF4VSI
182437. BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN
182438. BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_W_AVI
182439. BIT_RX_HDMI_CLR_BUFFER_VSI_IEEE_ID_CHK_EN
182440. BIT_RX_HDMI_CTRL0_BYP_DVIFILT_SYNC
182441. BIT_RX_HDMI_CTRL0_HDMI_MODE_EN_ITSELF_CLR
182442. BIT_RX_HDMI_CTRL0_HDMI_MODE_OVERWRITE
182443. BIT_RX_HDMI_CTRL0_HDMI_MODE_SW_VALUE
182444. BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE
182445. BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE_EN
182446. BIT_RX_HDMI_CTRL2_USE_AV_MUTE
182447. BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI
182448. BIT_RX_PSEL_RST
182449. BIT_RX_READY
182450. BIT_RX_STATUS_IRQ
182451. BIT_RX_TAG_EN
182452. BIT_SATA
182453. BIT_SB
182454. BIT_SCC_EMMC
182455. BIT_SCC_MIPI
182456. BIT_SCC_SDCARD
182457. BIT_SCC_SDIO
182458. BIT_SCHEDULE_EN
182459. BIT_SEC
182460. BIT_SECIE
182461. BIT_SECIF
182462. BIT_SECIGNORE
182463. BIT_SEG7_A
182464. BIT_SEG7_B
182465. BIT_SEG7_C
182466. BIT_SEG7_D
182467. BIT_SEG7_E
182468. BIT_SEG7_F
182469. BIT_SEG7_G
182470. BIT_SEG7_RESERVED
182471. BIT_SET
182472. BIT_SET_RXPSF_ERRTHR
182473. BIT_SET_RXPSF_PKTLENTHR
182474. BIT_SFF_DMA_DONE_INTEN
182475. BIT_SFF_OR_INT
182476. BIT_SF_OR_INTEN
182477. BIT_SHARED_IRQ_GPSC
182478. BIT_SHARED_IRQ_GPSS
182479. BIT_SHIFT_CHIP_VER
182480. BIT_SHIFT_EF_ADDR
182481. BIT_SHIFT_MAC_CLK_SEL
182482. BIT_SHIFT_RXGCK_CCK_FIFOTHR
182483. BIT_SHIFT_RXGCK_HT_FIFOTHR
182484. BIT_SHIFT_RXGCK_OFDM_FIFOTHR
182485. BIT_SHIFT_RXGCK_VHT_FIFOTHR
182486. BIT_SHIFT_RXPSF_ERRTHR
182487. BIT_SHIFT_RXPSF_PKTLENTHR
182488. BIT_SHIFT_SIFS_CCK_TRX
182489. BIT_SHIFT_SIFS_OFDM_CTX
182490. BIT_SHIFT_SIFS_OFDM_TRX
182491. BIT_SHIFT_TBTT_HOLD_TIME_AP
182492. BIT_SHIFT_TXDMA_BEQ_MAP
182493. BIT_SHIFT_TXDMA_BKQ_MAP
182494. BIT_SHIFT_TXDMA_HIQ_MAP
182495. BIT_SHIFT_TXDMA_MGQ_MAP
182496. BIT_SHIFT_TXDMA_VIQ_MAP
182497. BIT_SHIFT_TXDMA_VOQ_MAP
182498. BIT_SHIFT_TXPKTNUM
182499. BIT_SHIFT_TXSC_20M
182500. BIT_SHIFT_TXSC_40M
182501. BIT_SHIFT_Tx_OQT_free_space
182502. BIT_SHIFT_VENDOR_ID
182503. BIT_SHUTDOWN_ON
182504. BIT_SIFS_BK_EN
182505. BIT_SKIP_SOUND
182506. BIT_SMB
182507. BIT_SO
182508. BIT_SOF_INT
182509. BIT_SOF_INTEN
182510. BIT_SOF_POL
182511. BIT_SPARROW_M_4_SEL_SLEEP_OR_REF
182512. BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE
182513. BIT_SPIBURSTSTAT_SPI_CBUSRST
182514. BIT_SPIBURSTSTAT_SPI_HDCPRST
182515. BIT_SPIBURSTSTAT_SPI_SRST
182516. BIT_STATES
182517. BIT_STATFF_INT
182518. BIT_STATFF_INTEN
182519. BIT_STATFF_LEVEL
182520. BIT_STREAM_TIME
182521. BIT_STRIP_PAD_EN
182522. BIT_STS_GMM
182523. BIT_STS_ISH
182524. BIT_SUBPAGE
182525. BIT_SWAP
182526. BIT_SWAP16_EN
182527. BIT_SW_DPDT_SEL_DATA
182528. BIT_SYSCTRL_LP_ISOL_EN
182529. BIT_SYSCTRL_LP_RESET_N
182530. BIT_SYSCTRL_PSW_CLK_EN
182531. BIT_SYSCTRL_PWR_READY
182532. BIT_SYSCTRL_REF_CLOCK_EN
182533. BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD
182534. BIT_SYS_CTRL1_OTP2XAOVR_EN
182535. BIT_SYS_CTRL1_OTP2XVOVR_EN
182536. BIT_SYS_CTRL1_OTPADROPOVR_SET
182537. BIT_SYS_CTRL1_OTPAMUTEOVR_SET
182538. BIT_SYS_CTRL1_OTPVMUTEOVR_SET
182539. BIT_SYS_CTRL1_TX_CTRL_HDMI
182540. BIT_SYS_CTRL1_VSYNCPIN
182541. BIT_TABLE
182542. BIT_TA_BCN
182543. BIT_TCPOFLD_EN
182544. BIT_TDE_DBG_SEL
182545. BIT_TDMLLCTL_TTX_LL_SEL_MODE
182546. BIT_TDMLLCTL_TTX_LL_TIE_LOW
182547. BIT_TDM_INTR_SYNC_DATA
182548. BIT_TDM_INTR_SYNC_WAIT
182549. BIT_TEST_TXCTRL_HDMI_MODE
182550. BIT_TEST_TXCTRL_PCLK_REF_SEL
182551. BIT_TEST_TXCTRL_RCLK_REF_SEL
182552. BIT_TEST_TXCTRL_TST_PLLCK
182553. BIT_TIME_RELATIVE_TO_BUFFER
182554. BIT_TIM_PARSER_EN
182555. BIT_TMDS_CCTRL_TMDS_OE
182556. BIT_TMDS_CH_EN_CH0_EN
182557. BIT_TMDS_CH_EN_CH12_EN
182558. BIT_TMDS_CLK_EN_CLK_EN
182559. BIT_TMDS_CSTAT_P3_CKDT
182560. BIT_TMDS_CSTAT_P3_CLR_AVI
182561. BIT_TMDS_CSTAT_P3_RX_HDMI_CP_CLR_MUTE
182562. BIT_TMDS_CSTAT_P3_RX_HDMI_CP_NEW_CP
182563. BIT_TMDS_CSTAT_P3_RX_HDMI_CP_SET_MUTE
182564. BIT_TMDS_CSTAT_P3_SCDT
182565. BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS
182566. BIT_TMDS_CTRL4_SCDT_CKDT_SEL
182567. BIT_TMDS_CTRL4_TX_EN_BY_SCDT
182568. BIT_TO_2G
182569. BIT_TO_8G
182570. BIT_TO_COL
182571. BIT_TO_MASK
182572. BIT_TO_ROW_SSRN
182573. BIT_TO_WORD_SHIFT
182574. BIT_TPI_BSTATUS1_DS_DEV_EXCEED
182575. BIT_TPI_BSTATUS2_DS_CASC_EXCEED
182576. BIT_TPI_BSTATUS2_DS_HDMI_MODE
182577. BIT_TPI_CBUS_START_GET_DEVCAP_START
182578. BIT_TPI_CBUS_START_GET_EDID_START_0
182579. BIT_TPI_CBUS_START_PUT_DCAPCHG_START
182580. BIT_TPI_CBUS_START_PUT_DCAPRDY_START
182581. BIT_TPI_CBUS_START_PUT_LINK_MODE_START
182582. BIT_TPI_CBUS_START_RCPE_REPLY_START
182583. BIT_TPI_CBUS_START_RCPK_REPLY_START
182584. BIT_TPI_CBUS_START_RCP_REQ_START
182585. BIT_TPI_COPP_DATA1_COPP_CONNTYPE_0
182586. BIT_TPI_COPP_DATA1_COPP_CONNTYPE_1
182587. BIT_TPI_COPP_DATA1_COPP_GPROT
182588. BIT_TPI_COPP_DATA1_COPP_HDCP_REP
182589. BIT_TPI_COPP_DATA1_COPP_LPROT
182590. BIT_TPI_COPP_DATA1_COPP_PROTYPE
182591. BIT_TPI_COPP_DATA2_COPP_PROTLEVEL
182592. BIT_TPI_COPP_DATA2_DDC_SHORT_RI_RD
182593. BIT_TPI_COPP_DATA2_DOUBLE_RI_CHECK
182594. BIT_TPI_COPP_DATA2_INTERM_RI_CHECK_EN
182595. BIT_TPI_COPP_DATA2_INTR_ENCRYPTION
182596. BIT_TPI_COPP_DATA2_KSV_FORWARD
182597. BIT_TPI_HW_OPT3_DDC_DEBUG
182598. BIT_TPI_HW_OPT3_RI_CHECK_SKIP
182599. BIT_TPI_HW_OPT3_TPI_DDC_BURST_MODE
182600. BIT_TPI_INFO_FSEL_EN
182601. BIT_TPI_INFO_FSEL_READ_FLAG
182602. BIT_TPI_INFO_FSEL_RPT
182603. BIT_TPI_INPUT_ENDITHER
182604. BIT_TPI_INPUT_EXTENDEDBITMODE
182605. BIT_TPI_INTR_ST0_KSV_FIFO_FIRST_STAT
182606. BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_DONE_STAT
182607. BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_ERR_STAT
182608. BIT_TPI_INTR_ST0_READ_BKSV_ERR_STAT
182609. BIT_TPI_INTR_ST0_TPI_AUTH_CHNGE_STAT
182610. BIT_TPI_INTR_ST0_TPI_COPP_CHNGE_STAT
182611. BIT_TPI_INTR_ST0_TPI_V_RDY_STAT
182612. BIT_TPI_OUTPUT_CSCMODE709
182613. BIT_TPI_SC_DDC_GPU_REQUEST
182614. BIT_TPI_SC_DDC_TPI_SW
182615. BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN
182616. BIT_TPI_SC_TPI_AV_MUTE
182617. BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI
182618. BIT_TPI_SC_TPI_OUTPUT_MODE_1
182619. BIT_TPI_SC_TPI_REAUTH_CTL
182620. BIT_TPI_SC_TPI_UPDATE_FLG
182621. BIT_TRXCTRL_TRX_CLR_WVALLOW
182622. BIT_TRXCTRL_TRX_FROM_SE_COC
182623. BIT_TSFT_SEL_TIMER0
182624. BIT_TTXINTH_TTX_INTR10
182625. BIT_TTXINTH_TTX_INTR11
182626. BIT_TTXINTH_TTX_INTR12
182627. BIT_TTXINTH_TTX_INTR13
182628. BIT_TTXINTH_TTX_INTR14
182629. BIT_TTXINTH_TTX_INTR15
182630. BIT_TTXINTH_TTX_INTR8
182631. BIT_TTXINTH_TTX_INTR9
182632. BIT_TTXINTL_TTX_INTR0
182633. BIT_TTXINTL_TTX_INTR1
182634. BIT_TTXINTL_TTX_INTR2
182635. BIT_TTXINTL_TTX_INTR3
182636. BIT_TTXINTL_TTX_INTR4
182637. BIT_TTXINTL_TTX_INTR5
182638. BIT_TTXINTL_TTX_INTR6
182639. BIT_TTXINTL_TTX_INTR7
182640. BIT_TTXNUMB_TTX_COM1_AT_SYNC_WAIT
182641. BIT_TVDECODER_IN_EN
182642. BIT_TWO_8BIT_SENSOR
182643. BIT_TXAGC
182644. BIT_TXA_LB_ATT
182645. BIT_TXBIST_VGB_EN
182646. BIT_TXDMA_BEQ_MAP
182647. BIT_TXDMA_BKQ_MAP
182648. BIT_TXDMA_EN
182649. BIT_TXDMA_HIQ_MAP
182650. BIT_TXDMA_MGQ_MAP
182651. BIT_TXDMA_VIQ_MAP
182652. BIT_TXDMA_VOQ_MAP
182653. BIT_TXNACKREQ
182654. BIT_TXNIE
182655. BIT_TXNIF
182656. BIT_TXNSECEN
182657. BIT_TXNTRIG
182658. BIT_TXPKTNUM
182659. BIT_TXSC_20M
182660. BIT_TXSC_40M
182661. BIT_TX_CFIR
182662. BIT_TX_CLOSING
182663. BIT_TX_IP_BIST_CNTLSTA_TXBIST_DONE
182664. BIT_TX_IP_BIST_CNTLSTA_TXBIST_EN
182665. BIT_TX_IP_BIST_CNTLSTA_TXBIST_ON
182666. BIT_TX_IP_BIST_CNTLSTA_TXBIST_QUARTER_CLK_SEL
182667. BIT_TX_IP_BIST_CNTLSTA_TXBIST_RUN
182668. BIT_TX_IP_BIST_CNTLSTA_TXBIST_SEL
182669. BIT_TX_IP_BIST_CNTLSTA_TXCLK_HALF_SEL
182670. BIT_TX_OFFSET_VAL
182671. BIT_TX_READY
182672. BIT_TX_SCHEDULED
182673. BIT_TX_STATUS_IRQ
182674. BIT_Tx_OQT_free_space
182675. BIT_UC_MATCH_EN
182676. BIT_UC_MD_EN
182677. BIT_UFC
182678. BIT_UFE
182679. BIT_UFS_DEVICE_RESET
182680. BIT_UFS_PHY_ISO_CTRL
182681. BIT_UFS_PSW_ISO_CTRL
182682. BIT_UFS_PSW_MTCMOS_EN
182683. BIT_UFS_REFCLK_ISO_EN
182684. BIT_UFS_REFCLK_SRC_SEl
182685. BIT_ULL
182686. BIT_ULL_MASK
182687. BIT_ULL_WORD
182688. BIT_UP
182689. BIT_UP_CLEAR
182690. BIT_UP_SET
182691. BIT_USB_EHCI
182692. BIT_USB_FLAG_OFF
182693. BIT_USB_FLAG_ON
182694. BIT_USB_RXDMA_AGG_EN
182695. BIT_USER_CLKS_CAR_AHB_SW_SEL
182696. BIT_USER_CLKS_RST_PWGD
182697. BIT_USER_EXT_CLK
182698. BIT_USER_MAC_CPU_MAN_RST
182699. BIT_USER_OOB_MODE
182700. BIT_USER_OOB_R2_MODE
182701. BIT_USER_PREVENT_DEEP_SLEEP
182702. BIT_USER_SUPPORT_T_POWER_ON_0
182703. BIT_USER_USER_CPU_MAN_RST
182704. BIT_USER_USER_ICR_SW_INT_2
182705. BIT_USH
182706. BIT_USH_SS_PHY
182707. BIT_UTMI_8_16
182708. BIT_UTMI_ULPI
182709. BIT_UTSRST_FC_SRST
182710. BIT_UTSRST_HRX_SRST
182711. BIT_UTSRST_HTX_SRST
182712. BIT_UTSRST_KEEPER_SRST
182713. BIT_UTSRST_TRX_SRST
182714. BIT_UTSRST_TTX_SRST
182715. BIT_UVC_CMD_QUI
182716. BIT_UVC_CMD_REMOVE_SHARED_ACCESS
182717. BIT_UVC_CMD_SET_SHARED_ACCESS
182718. BIT_VAL
182719. BIT_VEC64_CLEAR_BIT
182720. BIT_VEC64_ELEM_MASK
182721. BIT_VEC64_ELEM_ONE_MASK
182722. BIT_VEC64_ELEM_SHIFT
182723. BIT_VEC64_ELEM_SZ
182724. BIT_VEC64_ONES_MASK
182725. BIT_VEC64_SET_BIT
182726. BIT_VEC64_TEST_BIT
182727. BIT_VENDOR_ID
182728. BIT_VHT_DACK
182729. BIT_VID_MODE_M1080P
182730. BIT_VID_OVRRD_3DCONV_EN_FRAME_PACK
182731. BIT_VID_OVRRD_ENABLE_AUTO_PATH_EN
182732. BIT_VID_OVRRD_ENDOWNSAMPLE_OVRRD
182733. BIT_VID_OVRRD_ENRGB2YCBCR_OVRRD
182734. BIT_VID_OVRRD_M1080P_OVRRD
182735. BIT_VID_OVRRD_MINIVSYNC_ON
182736. BIT_VID_OVRRD_PP_AUTO_DISABLE
182737. BIT_VLAN_DROP_EN
182738. BIT_WAKE_ON_READ
182739. BIT_WAKE_ON_WRITE
182740. BIT_WDG_EN
182741. BIT_WDG_RST
182742. BIT_WDG_RUN
182743. BIT_WIDE
182744. BIT_WLAN_OFF
182745. BIT_WLAN_ON
182746. BIT_WLMCU_IOIF
182747. BIT_WLRF1_BBRF_EN
182748. BIT_WLRFE_4_5_EN
182749. BIT_WL_PLATFORM_RST
182750. BIT_WL_RFK
182751. BIT_WL_SECURITY_CLK
182752. BIT_WORD
182753. BIT_WRITEABLE_SHIFT
182754. BIT_WRITE_BACK
182755. BIT_WR_DATA_OFFSET
182756. BIT_ZERO_PACK_EN
182757. BIT_addBits
182758. BIT_addBitsFast
182759. BIT_closeCStream
182760. BIT_endOfDStream
182761. BIT_flushBits
182762. BIT_flushBitsFast
182763. BIT_getLowerBits
182764. BIT_getMiddleBits
182765. BIT_getUpperBits
182766. BIT_highbit32
182767. BIT_initCStream
182768. BIT_initDStream
182769. BIT_lookBits
182770. BIT_lookBitsFast
182771. BIT_readBits
182772. BIT_readBitsFast
182773. BIT_reloadDStream
182774. BIT_skipBits
182775. BIU_DIAG_VAR
182776. BI_AMIGA_AUTOCON
182777. BI_AMIGA_CHIPSET
182778. BI_AMIGA_CHIP_SIZE
182779. BI_AMIGA_ECLOCK
182780. BI_AMIGA_MODEL
182781. BI_AMIGA_PSFREQ
182782. BI_AMIGA_SERPER
182783. BI_AMIGA_VBLANK
182784. BI_APOLLO_MODEL
182785. BI_ATARI_MCH_COOKIE
182786. BI_ATARI_MCH_TYPE
182787. BI_COMMAND_LINE
182788. BI_CPUTYPE
182789. BI_FPUTYPE
182790. BI_HP300_MODEL
182791. BI_HP300_UART_ADDR
182792. BI_HP300_UART_SCODE
182793. BI_LAST
182794. BI_MACHTYPE
182795. BI_MAC_ADBTYPE
182796. BI_MAC_ASCBASE
182797. BI_MAC_BTIME
182798. BI_MAC_CPUID
182799. BI_MAC_ETHBASE
182800. BI_MAC_ETHTYPE
182801. BI_MAC_GMTBIAS
182802. BI_MAC_IDEBASE
182803. BI_MAC_IDETYPE
182804. BI_MAC_IOP_ADB
182805. BI_MAC_IOP_SWIM
182806. BI_MAC_MEMSIZE
182807. BI_MAC_MODEL
182808. BI_MAC_NUBUS
182809. BI_MAC_PMU
182810. BI_MAC_ROMBASE
182811. BI_MAC_SCCBASE
182812. BI_MAC_SCCTYPE
182813. BI_MAC_SCSI5380
182814. BI_MAC_SCSI5396
182815. BI_MAC_SCSIDMA
182816. BI_MAC_SLOTMASK
182817. BI_MAC_VADDR
182818. BI_MAC_VDEPTH
182819. BI_MAC_VDIM
182820. BI_MAC_VIA1BASE
182821. BI_MAC_VIA2BASE
182822. BI_MAC_VIA2TYPE
182823. BI_MAC_VLOGICAL
182824. BI_MAC_VROW
182825. BI_MASK
182826. BI_MEMCHUNK
182827. BI_MMUTYPE
182828. BI_RAMDISK
182829. BI_REV
182830. BI_SHIFT
182831. BI_VERSION_MAJOR
182832. BI_VERSION_MINOR
182833. BI_VME_BRDINFO
182834. BI_VME_TYPE
182835. BJAPANMODE
182836. BJ_Forget
182837. BJ_Metadata
182838. BJ_None
182839. BJ_Reserved
182840. BJ_Shadow
182841. BJ_Types
182842. BK
182843. BK3710_BMICP
182844. BK3710_BMIDTP
182845. BK3710_BMISP
182846. BK3710_CTL_OFFSET
182847. BK3710_DATRCVR
182848. BK3710_DATSTB
182849. BK3710_DMARCVR
182850. BK3710_DMASTB
182851. BK3710_IDESTATUS
182852. BK3710_IDETIMP
182853. BK3710_IORDYTMP
182854. BK3710_MISCCTL
182855. BK3710_REGRCVR
182856. BK3710_REGSTB
182857. BK3710_TF_OFFSET
182858. BK3710_UDMACTL
182859. BK3710_UDMAENV
182860. BK3710_UDMASTB
182861. BK3710_UDMATRP
182862. BK3_DIS_SDCARD_PWR
182863. BK3_EN_SDCARD_PHYS_BASE
182864. BK3_EN_SDCARD_PWR
182865. BKDONE
182866. BKEY_EXPONENT_BITS
182867. BKEY_MANTISSA_BITS
182868. BKEY_MANTISSA_MASK
182869. BKEY_MID_BITS
182870. BKEY_PAD
182871. BKEY_PADDED
182872. BKFEN
182873. BKGD_MIX_D
182874. BKGD_MIX_D_AND_NOT_S
182875. BKGD_MIX_D_AND_S
182876. BKGD_MIX_D_OR_NOT_S
182877. BKGD_MIX_D_OR_S
182878. BKGD_MIX_D_PLUS_S_DIV2
182879. BKGD_MIX_D_XOR_S
182880. BKGD_MIX_NOT_D
182881. BKGD_MIX_NOT_D_AND_NOT_S
182882. BKGD_MIX_NOT_D_AND_S
182883. BKGD_MIX_NOT_D_OR_NOT_S
182884. BKGD_MIX_NOT_D_OR_S
182885. BKGD_MIX_NOT_D_XOR_S
182886. BKGD_MIX_NOT_S
182887. BKGD_MIX_ONE
182888. BKGD_MIX_S
182889. BKGD_MIX_ZERO
182890. BKGD_SRC_BKGD_CLR
182891. BKGD_SRC_BLIT
182892. BKGD_SRC_FRGD_CLR
182893. BKGD_SRC_HOST
182894. BKGD_SRC_PATTERN
182895. BKL
182896. BKOFF_SLOT_CFG
182897. BKOFF_SLOT_CFG_CC_DELAY_TIME
182898. BKOFF_SLOT_CFG_SLOT_TIME
182899. BKOPS_STATUS_CRITICAL
182900. BKOPS_STATUS_MAX
182901. BKOPS_STATUS_NON_CRITICAL
182902. BKOPS_STATUS_NO_OP
182903. BKOPS_STATUS_PERF_IMPACT
182904. BKP
182905. BKPG_IO
182906. BKPRAM_CK
182907. BKPSRAM
182908. BKPT_OPCODE
182909. BKP_REDUN_SEL
182910. BKP_REDUN_SHIFT
182911. BKP_SEL
182912. BKQDA
182913. BKSV
182914. BKTID1_CTRL
182915. BKTID2_CTRL
182916. BKW_MMAP_DATA_PENDING
182917. BKW_MMAP_EMPTY
182918. BKW_MMAP_NOTREADY
182919. BKW_MMAP_RUNNING
182920. BK_BAT_V
182921. BK_PRIORITY
182922. BK_Q
182923. BK_QID_01
182924. BK_QID_02
182925. BK_QUEUE
182926. BK_QUEUE_INX
182927. BL
182928. BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK
182929. BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT
182930. BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK
182931. BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT
182932. BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK
182933. BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT
182934. BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK
182935. BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT
182936. BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK
182937. BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT
182938. BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK
182939. BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT
182940. BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK
182941. BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT
182942. BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK
182943. BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT
182944. BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK
182945. BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT
182946. BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK
182947. BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT
182948. BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK
182949. BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT
182950. BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK
182951. BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT
182952. BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK
182953. BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT
182954. BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK
182955. BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT
182956. BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK
182957. BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT
182958. BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK
182959. BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT
182960. BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK
182961. BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT
182962. BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK
182963. BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT
182964. BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK
182965. BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT
182966. BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK
182967. BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT
182968. BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK
182969. BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT
182970. BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK
182971. BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT
182972. BLACK
182973. BLACKBIRD_COPYRIGHT_OFF
182974. BLACKBIRD_COPYRIGHT_ON
182975. BLACKBIRD_CUSTOM_EXTENSION_USR_DATA
182976. BLACKBIRD_CUSTOM_PRIVATE_PACKET
182977. BLACKBIRD_DMA_BYTES
182978. BLACKBIRD_DMA_FRAMES
182979. BLACKBIRD_DMA_TRANSFER_BITS_DONE
182980. BLACKBIRD_DMA_TRANSFER_BITS_ERROR
182981. BLACKBIRD_DMA_TRANSFER_BITS_LL_ERROR
182982. BLACKBIRD_END_AT_GOP
182983. BLACKBIRD_END_NOW
182984. BLACKBIRD_FIELD1_MICRONAS
182985. BLACKBIRD_FIELD1_SAA7114
182986. BLACKBIRD_FIELD1_SAA7115
182987. BLACKBIRD_FIELD2_MICRONAS
182988. BLACKBIRD_FIELD2_SAA7114
182989. BLACKBIRD_FIELD2_SAA7115
182990. BLACKBIRD_FIRM_IMAGE_SIZE
182991. BLACKBIRD_FRAMERATE_NTSC_30
182992. BLACKBIRD_FRAMERATE_PAL_25
182993. BLACKBIRD_LAST_BUFFER
182994. BLACKBIRD_MORE_BUFFERS_FOLLOW
182995. BLACKBIRD_MPEG_CAPTURE
182996. BLACKBIRD_MUTE
182997. BLACKBIRD_MUTE_VIDEO_U_MASK
182998. BLACKBIRD_MUTE_VIDEO_U_SHIFT
182999. BLACKBIRD_MUTE_VIDEO_V_MASK
183000. BLACKBIRD_MUTE_VIDEO_V_SHIFT
183001. BLACKBIRD_MUTE_VIDEO_Y_MASK
183002. BLACKBIRD_MUTE_VIDEO_Y_SHIFT
183003. BLACKBIRD_NOTIFICATION_NO_MAILBOX
183004. BLACKBIRD_NOTIFICATION_OFF
183005. BLACKBIRD_NOTIFICATION_ON
183006. BLACKBIRD_NOTIFICATION_REFRESH
183007. BLACKBIRD_OUTPUT_PORT_MEMORY
183008. BLACKBIRD_OUTPUT_PORT_SERIAL
183009. BLACKBIRD_OUTPUT_PORT_STREAMING
183010. BLACKBIRD_PAUSE_ENCODING
183011. BLACKBIRD_PICTURE_MASK_ALL_FRAMES
183012. BLACKBIRD_PICTURE_MASK_I_FRAMES
183013. BLACKBIRD_PICTURE_MASK_I_P_FRAMES
183014. BLACKBIRD_PICTURE_MASK_NONE
183015. BLACKBIRD_RAW_BITS_NONE
183016. BLACKBIRD_RAW_BITS_PASSTHRU_CAPTURE
183017. BLACKBIRD_RAW_BITS_PCM_CAPTURE
183018. BLACKBIRD_RAW_BITS_TO_HOST_CAPTURE
183019. BLACKBIRD_RAW_BITS_VBI_CAPTURE
183020. BLACKBIRD_RAW_BITS_YUV_CAPTURE
183021. BLACKBIRD_RAW_CAPTURE
183022. BLACKBIRD_RAW_PASSTHRU_CAPTURE
183023. BLACKBIRD_RESUME_ENCODING
183024. BLACKBIRD_UNMUTE
183025. BLACKBIRD_VBI_BITS_INSERT_IN_PRIVATE_PACKETS
183026. BLACKBIRD_VBI_BITS_INSERT_IN_XTENSION_USR_DATA
183027. BLACKBIRD_VBI_BITS_RAW
183028. BLACKBIRD_VBI_BITS_SEPARATE_STREAM
183029. BLACKBIRD_VBI_BITS_SEPARATE_STREAM_PRV_DATA
183030. BLACKBIRD_VBI_BITS_SEPARATE_STREAM_USR_DATA
183031. BLACKBIRD_VBI_BITS_SLICED
183032. BLACKOUT_MODE_MASK
183033. BLACKOUT_RD
183034. BLACKOUT_WR
183035. BLACK_COLOR_FORMAT_COUNT
183036. BLACK_COLOR_FORMAT_DEBUG
183037. BLACK_COLOR_FORMAT_RGB_FULLRANGE
183038. BLACK_COLOR_FORMAT_RGB_LIMITED
183039. BLACK_COLOR_FORMAT_YUV_CV
183040. BLACK_COLOR_FORMAT_YUV_SUPER_AA
183041. BLACK_COLOR_FORMAT_YUV_TV
183042. BLACK_OFFSET_CBCR
183043. BLACK_OFFSET_RGB_Y
183044. BLADE3D
183045. BLAMBDA_ED
183046. BLANK
183047. BLANKING_EXTRA_HEIGHT
183048. BLANKING_EXTRA_WIDTH
183049. BLANKING_LEVEL
183050. BLANKING_MIN_HEIGHT
183051. BLANKING_PACKET_ENABLE
183052. BLANK_BIT
183053. BLANK_CHECK
183054. BLANK_CRTC_PARAMETERS
183055. BLANK_CRTC_PS_ALLOCATION
183056. BLANK_DISP
183057. BLANK_DISP_OVERLAY
183058. BLANK_HEAD_SIZE
183059. BLANK_IO
183060. BLANK_LEVEL
183061. BLANK_LOOP_END
183062. BLANK_LOOP_SIZE
183063. BLANK_LOOP_START
183064. BLANK_OFF
183065. BLANK_SLOT
183066. BLAST_BLOCK
183067. BLC_ADJUSTMENT_MAX
183068. BLC_HIST_CTL
183069. BLC_I2C_TYPE
183070. BLC_POLARITY_INVERSE
183071. BLC_POLARITY_NORMAL
183072. BLC_PWM_CPU_CTL
183073. BLC_PWM_CPU_CTL2
183074. BLC_PWM_CTL
183075. BLC_PWM_CTL2
183076. BLC_PWM_CTL2_C
183077. BLC_PWM_CTL_C
183078. BLC_PWM_FREQ_CALC_CONSTANT
183079. BLC_PWM_PCH_CTL1
183080. BLC_PWM_PCH_CTL2
183081. BLC_PWM_PRECISION_FACTOR
183082. BLC_PWM_TYPT
183083. BLD_STR_UFI_TYPE_BE2
183084. BLD_STR_UFI_TYPE_BE3
183085. BLD_STR_UFI_TYPE_SH
183086. BLE
183087. BLEEPS
183088. BLEEPS_DEC
183089. BLEEPS_INC
183090. BLEEP_TIME
183091. BLEN
183092. BLEND2_DST_MINUS_SRC
183093. BLEND2_DST_PLUS_SRC
183094. BLEND2_DST_PLUS_SRC_BIAS
183095. BLEND2_MAX_DST_SRC
183096. BLEND2_MIN_DST_SRC
183097. BLEND2_SRC_MINUS_DST
183098. BLENDCON
183099. BLENDCON_NEW_4BIT_ALPHA_VALUE
183100. BLENDCON_NEW_8BIT_ALPHA_VALUE
183101. BLENDCON_NEW_MASK
183102. BLENDE
183103. BLENDEQ_ALPHA0
183104. BLENDEQ_ALPHA_A
183105. BLENDEQ_A_FUNC_F
183106. BLENDEQ_B_FUNC_F
183107. BLENDEQ_ONE
183108. BLENDEQ_ONE_MINUS_ALPHA_A
183109. BLENDEQ_ZERO
183110. BLENDEQx
183111. BLENDERQ_ALPHA0
183112. BLENDERQ_ALPHA_A
183113. BLENDERQ_A_FUNC_F
183114. BLENDERQ_B_FUNC_F
183115. BLENDERQ_ONE
183116. BLENDERQ_ONE_MINUS_ALPHA_A
183117. BLENDERQ_P_FUNC_F
183118. BLENDERQ_Q_FUNC_F
183119. BLENDERQ_ZERO
183120. BLENDE_A_FUNC
183121. BLENDE_B_FUNC
183122. BLENDE_COEF_A
183123. BLENDE_COEF_ALPHA0
183124. BLENDE_COEF_ALPHA_A
183125. BLENDE_COEF_ALPHA_B
183126. BLENDE_COEF_B
183127. BLENDE_COEF_ONE
183128. BLENDE_COEF_ONE_MINUS_A
183129. BLENDE_COEF_ONE_MINUS_ALPHA_A
183130. BLENDE_COEF_ONE_MINUS_ALPHA_B
183131. BLENDE_COEF_ONE_MINUS_B
183132. BLENDE_COEF_ZERO
183133. BLENDE_P_FUNC
183134. BLENDE_Q_FUNC
183135. BLEND_3D_COL_INT
183136. BLEND_3D_FRAME_INT
183137. BLEND_3D_H_ROW_INT
183138. BLEND_3D_MAX
183139. BLEND_3D_NONE
183140. BLEND_3D_V_ROW_INT
183141. BLEND_BOTH_INV_SRC_ALPHA
183142. BLEND_BOTH_SRC_ALPHA
183143. BLEND_BYPASS
183144. BLEND_COLOR_KEY_0
183145. BLEND_COLOR_KEY_1
183146. BLEND_COLOR_KEY_BOTH
183147. BLEND_COLOR_KEY_NONE
183148. BLEND_CONSTANT_ALPHA
183149. BLEND_CONSTANT_COLOR
183150. BLEND_CONTROL_ALPHA
183151. BLEND_CONTROL_DEPENDENT
183152. BLEND_CONTROL_FIX
183153. BLEND_DST_ALPHA
183154. BLEND_DST_COLOR
183155. BLEND_DST_MINUS_SRC
183156. BLEND_DST_PLUS_SRC
183157. BLEND_FACTOR_DST_ALPHA_K2
183158. BLEND_FACTOR_DST_ALPHA_NEG_K1_TIMES_SRC
183159. BLEND_FACTOR_DST_ALPHA_ONE
183160. BLEND_FACTOR_DST_ALPHA_ZERO
183161. BLEND_FACTOR_DST_COLOR_K1
183162. BLEND_FACTOR_DST_COLOR_K1_TIMES_DST
183163. BLEND_FACTOR_DST_COLOR_K2
183164. BLEND_FACTOR_DST_COLOR_NEG_K1
183165. BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_DST
183166. BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC
183167. BLEND_FACTOR_DST_COLOR_ONE
183168. BLEND_FACTOR_DST_COLOR_ZERO
183169. BLEND_FACTOR_SRC_ALPHA_K1
183170. BLEND_FACTOR_SRC_ALPHA_K2
183171. BLEND_FACTOR_SRC_ALPHA_NEG_K1_TIMES_DST
183172. BLEND_FACTOR_SRC_ALPHA_ZERO
183173. BLEND_FACTOR_SRC_COLOR_K1
183174. BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST
183175. BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC
183176. BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST
183177. BLEND_FACTOR_SRC_COLOR_ONE
183178. BLEND_FACTOR_SRC_COLOR_ZERO
183179. BLEND_INV_SRC1_ALPHA
183180. BLEND_INV_SRC1_COLOR
183181. BLEND_MAX_DST_SRC
183182. BLEND_MIN_DST_SRC
183183. BLEND_NEW
183184. BLEND_ONE
183185. BLEND_ONE_MINUS_CONSTANT_ALPHA
183186. BLEND_ONE_MINUS_CONSTANT_COLOR
183187. BLEND_ONE_MINUS_DST_ALPHA
183188. BLEND_ONE_MINUS_DST_COLOR
183189. BLEND_ONE_MINUS_SRC_ALPHA
183190. BLEND_ONE_MINUS_SRC_COLOR
183191. BLEND_OP
183192. BLEND_OPT_PRESERVE_A0_IGNORE_A1
183193. BLEND_OPT_PRESERVE_A1_IGNORE_A0
183194. BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
183195. BLEND_OPT_PRESERVE_C0_IGNORE_C1
183196. BLEND_OPT_PRESERVE_C1_IGNORE_C0
183197. BLEND_OPT_PRESERVE_NONE_IGNORE_A0
183198. BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
183199. BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
183200. BLEND_SRC1_ALPHA
183201. BLEND_SRC1_COLOR
183202. BLEND_SRC_ALPHA
183203. BLEND_SRC_ALPHA_SATURATE
183204. BLEND_SRC_COLOR
183205. BLEND_SRC_MINUS_DST
183206. BLEND_WEIGHT0
183207. BLEND_WEIGHT1
183208. BLEND_ZERO
183209. BLEU
183210. BLIEND_MODE
183211. BLIMIT
183212. BLIND_SCAN_CTRL_REG
183213. BLINK
183214. BLINKINGOFF_STATE
183215. BLINKINGON_STATE
183216. BLINK_170MS
183217. BLINK_340MS
183218. BLINK_42MS
183219. BLINK_670MS
183220. BLINK_84MS
183221. BLINK_DELAY
183222. BLINK_EN
183223. BLINK_GREEN_LED
183224. BLINK_MS
183225. BLINK_OFF
183226. BLINK_ON
183227. BLINK_ORANGE_LED
183228. BLINK_RED_LED
183229. BLINK_X1
183230. BLINK_X2
183231. BLINK_X3
183232. BLINK_X4
183233. BLIST_BORKEN
183234. BLIST_FLAG_NAME
183235. BLIST_FORCELUN
183236. BLIST_INQUIRY_36
183237. BLIST_ISROM
183238. BLIST_KEY
183239. BLIST_LARGELUN
183240. BLIST_MAX5LUN
183241. BLIST_MAX_1024
183242. BLIST_MAX_512
183243. BLIST_NOLUN
183244. BLIST_NOREPORTLUN
183245. BLIST_NOSTARTONADD
183246. BLIST_NOTQ
183247. BLIST_NOT_LOCKABLE
183248. BLIST_NO_DIF
183249. BLIST_NO_RSOC
183250. BLIST_NO_ULD_ATTACH
183251. BLIST_REPORTLUN2
183252. BLIST_RETRY_ASC_C1
183253. BLIST_RETRY_HWERROR
183254. BLIST_RETRY_ITF
183255. BLIST_SELECT_NO_ATN
183256. BLIST_SINGLELUN
183257. BLIST_SKIP_VPD_PAGES
183258. BLIST_SPARSELUN
183259. BLIST_TRY_VPD_PAGES
183260. BLIST_UNMAP_LIMIT_WS
183261. BLIT
183262. BLIT2D
183263. BLIT2DSCALE
183264. BLITTER
183265. BLITTER_CLOCK_GATE_DISABLE
183266. BLIT_MRT0
183267. BLIT_MRT1
183268. BLIT_MRT2
183269. BLIT_MRT3
183270. BLIT_MRT4
183271. BLIT_MRT5
183272. BLIT_MRT6
183273. BLIT_MRT7
183274. BLIT_OP_COPY
183275. BLIT_OP_FILL
183276. BLIT_OP_SCALE
183277. BLIT_POINT_DST
183278. BLIT_POINT_DST_X
183279. BLIT_POINT_DST_Y
183280. BLIT_POINT_SRC
183281. BLIT_POINT_SRC_X
183282. BLIT_POINT_SRC_Y
183283. BLIT_S
183284. BLIT_SIZE
183285. BLIT_SIZE_HEIGHT
183286. BLIT_SIZE_WIDTH
183287. BLIT_ZS
183288. BLK64
183289. BLKADDR_CPT0
183290. BLKADDR_CPT1
183291. BLKADDR_LMT
183292. BLKADDR_MSIX
183293. BLKADDR_NDC0
183294. BLKADDR_NDC1
183295. BLKADDR_NDC2
183296. BLKADDR_NIX0
183297. BLKADDR_NIX1
183298. BLKADDR_NPA
183299. BLKADDR_NPC
183300. BLKADDR_RVUM
183301. BLKADDR_SSO
183302. BLKADDR_SSOW
183303. BLKADDR_TIM
183304. BLKALIGNOFF
183305. BLKBACK_INVALID_HANDLE
183306. BLKBSZGET
183307. BLKBSZGET_32
183308. BLKBSZSET
183309. BLKBSZSET_32
183310. BLKCG_MAX_POLS
183311. BLKCIPHER_WALK_COPY
183312. BLKCIPHER_WALK_DIFF
183313. BLKCIPHER_WALK_PHYS
183314. BLKCIPHER_WALK_SLOW
183315. BLKCMP0
183316. BLKCMP1
183317. BLKDEV_BB
183318. BLKDEV_DISCARD_SECURE
183319. BLKDEV_FALLOC_FL_SUPPORTED
183320. BLKDEV_IOSHIFT
183321. BLKDEV_IOSIZE
183322. BLKDEV_MAJOR_HASH_SIZE
183323. BLKDEV_MAJOR_MAX
183324. BLKDEV_MAX_RQ
183325. BLKDEV_MIN_RQ
183326. BLKDEV_ZERO_NOFALLBACK
183327. BLKDEV_ZERO_NOUNMAP
183328. BLKDISCARD
183329. BLKDISCARDZEROES
183330. BLKELVGET
183331. BLKELVSET
183332. BLKFLSBUF
183333. BLKFRAGET
183334. BLKFRASET
183335. BLKGETNRZONES
183336. BLKGETSIZE
183337. BLKGETSIZE64
183338. BLKGETSIZE64_32
183339. BLKGETZONESZ
183340. BLKG_RWSTAT_ASYNC
183341. BLKG_RWSTAT_DISCARD
183342. BLKG_RWSTAT_NR
183343. BLKG_RWSTAT_READ
183344. BLKG_RWSTAT_SYNC
183345. BLKG_RWSTAT_TOTAL
183346. BLKG_RWSTAT_WRITE
183347. BLKG_STAT_CPU_BATCH
183348. BLKH_SIZE
183349. BLKID_AVB_PARAMS
183350. BLKID_GENERAL_PARAMS
183351. BLKID_L2_FORWARDING
183352. BLKID_L2_FORWARDING_PARAMS
183353. BLKID_L2_LOOKUP
183354. BLKID_L2_LOOKUP_PARAMS
183355. BLKID_L2_POLICING
183356. BLKID_MAC_CONFIG
183357. BLKID_SCHEDULE
183358. BLKID_SCHEDULE_ENTRY_POINTS
183359. BLKID_SCHEDULE_ENTRY_POINTS_PARAMS
183360. BLKID_SCHEDULE_PARAMS
183361. BLKID_VLAN_LOOKUP
183362. BLKID_XMII_PARAMS
183363. BLKIF_DISCARD_SECURE
183364. BLKIF_MAJOR
183365. BLKIF_MAX_INDIRECT_PAGES_PER_REQUEST
183366. BLKIF_MAX_SEGMENTS_PER_REQUEST
183367. BLKIF_MINOR
183368. BLKIF_MINOR_EXT
183369. BLKIF_OP_DISCARD
183370. BLKIF_OP_FLUSH_DISKCACHE
183371. BLKIF_OP_INDIRECT
183372. BLKIF_OP_READ
183373. BLKIF_OP_WRITE
183374. BLKIF_OP_WRITE_BARRIER
183375. BLKIF_PROTOCOL_DEFAULT
183376. BLKIF_PROTOCOL_NATIVE
183377. BLKIF_PROTOCOL_X86_32
183378. BLKIF_PROTOCOL_X86_64
183379. BLKIF_RSP_EOPNOTSUPP
183380. BLKIF_RSP_ERROR
183381. BLKIF_RSP_OKAY
183382. BLKIF_STATE_CONNECTED
183383. BLKIF_STATE_DISCONNECTED
183384. BLKIF_STATE_SUSPENDED
183385. BLKIOLATENCY
183386. BLKIOLATENCY_EXP_BUCKET_SIZE
183387. BLKIOLATENCY_MAX_WIN_SIZE
183388. BLKIOLATENCY_MIN_ADJUST_TIME
183389. BLKIOLATENCY_MIN_GOOD_SAMPLES
183390. BLKIOLATENCY_MIN_WIN_SIZE
183391. BLKIOLATENCY_NR_EXP_FACTORS
183392. BLKIOMIN
183393. BLKIOOPT
183394. BLKL_CD_POL_HIGH
183395. BLKL_CRCERR_ABORT
183396. BLKL_DATA3_CD
183397. BLKL_GPI_CD
183398. BLKL_INT_ENABLE
183399. BLKPBSZGET
183400. BLKPG
183401. BLKPG_ADD_PARTITION
183402. BLKPG_DEL_PARTITION
183403. BLKPG_DEVNAMELTH
183404. BLKPG_RESIZE_PARTITION
183405. BLKPG_VOLNAMELTH
183406. BLKRAGET
183407. BLKRASET
183408. BLKRDBOOTINT_F
183409. BLKRDBOOTINT_S
183410. BLKRDBOOTINT_V
183411. BLKRDCTLINT_F
183412. BLKRDCTLINT_S
183413. BLKRDCTLINT_V
183414. BLKRDEEPROMINT_F
183415. BLKRDEEPROMINT_S
183416. BLKRDEEPROMINT_V
183417. BLKRDFLASHINT_F
183418. BLKRDFLASHINT_S
183419. BLKRDFLASHINT_V
183420. BLKRDPLINT_F
183421. BLKRDPLINT_S
183422. BLKRDPLINT_V
183423. BLKREPORTZONE
183424. BLKRESETZONE
183425. BLKROGET
183426. BLKROSET
183427. BLKROTATIONAL
183428. BLKRRPART
183429. BLKSECDISCARD
183430. BLKSECTGET
183431. BLKSECTSET
183432. BLKSSZGET
183433. BLKSTOL2
183434. BLKS_PER_BUF
183435. BLKS_PER_BUF_SHIFT
183436. BLKS_PER_SEC
183437. BLKTOAG
183438. BLKTOCTL
183439. BLKTOCTLLEAF
183440. BLKTODMAP
183441. BLKTODMAPN
183442. BLKTOL0
183443. BLKTOL1
183444. BLKTRACESETUP
183445. BLKTRACESETUP32
183446. BLKTRACESTART
183447. BLKTRACESTOP
183448. BLKTRACETEARDOWN
183449. BLKTRACE_BDEV_SIZE
183450. BLKTRACE_H
183451. BLKTYPE_CPT
183452. BLKTYPE_LMT
183453. BLKTYPE_MAX
183454. BLKTYPE_MSIX
183455. BLKTYPE_NDC
183456. BLKTYPE_NIX
183457. BLKTYPE_NPA
183458. BLKTYPE_NPC
183459. BLKTYPE_RVUM
183460. BLKTYPE_SSO
183461. BLKTYPE_SSOW
183462. BLKTYPE_TIM
183463. BLKWRBOOTINT_F
183464. BLKWRBOOTINT_S
183465. BLKWRBOOTINT_V
183466. BLKWRCTLINT_F
183467. BLKWRCTLINT_S
183468. BLKWRCTLINT_V
183469. BLKWREEPROMINT_F
183470. BLKWREEPROMINT_S
183471. BLKWREEPROMINT_V
183472. BLKWRFLASHINT_F
183473. BLKWRFLASHINT_S
183474. BLKWRFLASHINT_V
183475. BLKWRPLINT_F
183476. BLKWRPLINT_S
183477. BLKWRPLINT_V
183478. BLKZEROOUT
183479. BLK_AD
183480. BLK_ADDR_REG_OFFSET
183481. BLK_AVG
183482. BLK_BLOCK_INFO
183483. BLK_BOUNCE_ANY
183484. BLK_BOUNCE_HIGH
183485. BLK_BOUNCE_ISA
183486. BLK_CONTROL
183487. BLK_COUNT
183488. BLK_CTL
183489. BLK_CTRL_EN
183490. BLK_CURSOR
183491. BLK_DEFAULT_SG_TIMEOUT
183492. BLK_DEF_MAX_SECTORS
183493. BLK_DESC_NUM_MASK
183494. BLK_DESC_NUM_SHIFT
183495. BLK_DMA
183496. BLK_EH_DONE
183497. BLK_EH_RESET_TIMER
183498. BLK_EOL_DURATION
183499. BLK_EOL_PKT_LEN
183500. BLK_ERASE_1
183501. BLK_ERASE_2
183502. BLK_FUN_SWTCH
183503. BLK_HDR_LEN
183504. BLK_HEAD_BYTES
183505. BLK_IDX_AVB_PARAMS
183506. BLK_IDX_GENERAL_PARAMS
183507. BLK_IDX_INVAL
183508. BLK_IDX_L2_FORWARDING
183509. BLK_IDX_L2_FORWARDING_PARAMS
183510. BLK_IDX_L2_LOOKUP
183511. BLK_IDX_L2_LOOKUP_PARAMS
183512. BLK_IDX_L2_POLICING
183513. BLK_IDX_MAC_CONFIG
183514. BLK_IDX_MAX
183515. BLK_IDX_MAX_DYN
183516. BLK_IDX_MGMT_ROUTE
183517. BLK_IDX_SCHEDULE
183518. BLK_IDX_SCHEDULE_ENTRY_POINTS
183519. BLK_IDX_SCHEDULE_ENTRY_POINTS_PARAMS
183520. BLK_IDX_SCHEDULE_PARAMS
183521. BLK_IDX_VLAN_LOOKUP
183522. BLK_IDX_XMII_PARAMS
183523. BLK_INFO
183524. BLK_INPUT_ID0
183525. BLK_INTEGRITY_DEVICE_CAPABLE
183526. BLK_INTEGRITY_GENERATE
183527. BLK_INTEGRITY_IP_CHECKSUM
183528. BLK_INTEGRITY_VERIFY
183529. BLK_INTERNAL_H
183530. BLK_INTF
183531. BLK_IN_SIZE
183532. BLK_IO_TRACE_MAGIC
183533. BLK_IO_TRACE_VERSION
183534. BLK_IRQ_CLEAR
183535. BLK_IRQ_MASK
183536. BLK_IRQ_RAW_STATUS
183537. BLK_IRQ_STATUS
183538. BLK_LINE_EVENT_PKT_LEN
183539. BLK_LINE_PULSE_PKT_LEN
183540. BLK_LO2EXT
183541. BLK_LSEG2EXT
183542. BLK_MAX_CDB
183543. BLK_MAX_REQUEST_COUNT
183544. BLK_MAX_RING_SIZE
183545. BLK_MAX_SEGMENTS
183546. BLK_MAX_SEGMENT_SIZE
183547. BLK_MAX_TIMEOUT
183548. BLK_MAX_WRITE_HINTS
183549. BLK_MDP
183550. BLK_MIN_SG_TIMEOUT
183551. BLK_MIXER
183552. BLK_MQ_CPU_WORK_BATCH
183553. BLK_MQ_DISPATCH_BUSY_EWMA_FACTOR
183554. BLK_MQ_DISPATCH_BUSY_EWMA_WEIGHT
183555. BLK_MQ_F_ALLOC_POLICY_BITS
183556. BLK_MQ_F_ALLOC_POLICY_START_BIT
183557. BLK_MQ_F_BLOCKING
183558. BLK_MQ_F_NO_SCHED
183559. BLK_MQ_F_SHOULD_MERGE
183560. BLK_MQ_F_TAG_SHARED
183561. BLK_MQ_H
183562. BLK_MQ_MAX_DEPTH
183563. BLK_MQ_MAX_DISPATCH_ORDER
183564. BLK_MQ_POLL_CLASSIC
183565. BLK_MQ_POLL_STATS_BKTS
183566. BLK_MQ_RESOURCE_DELAY
183567. BLK_MQ_SCHED_H
183568. BLK_MQ_S_SCHED_RESTART
183569. BLK_MQ_S_STOPPED
183570. BLK_MQ_S_TAG_ACTIVE
183571. BLK_MQ_TAG_FAIL
183572. BLK_MQ_TAG_MAX
183573. BLK_MQ_TAG_MIN
183574. BLK_MQ_UNIQUE_TAG_BITS
183575. BLK_MQ_UNIQUE_TAG_MASK
183576. BLK_NOT_FOUND
183577. BLK_NOT_MIR
183578. BLK_OUTPUT_ID0
183579. BLK_P0_PTR_HIGH
183580. BLK_P0_PTR_LOW
183581. BLK_P0_STRIDE
183582. BLK_P1_PTR_HIGH
183583. BLK_P1_PTR_LOW
183584. BLK_P1_STRIDE
183585. BLK_P2_PTR_HIGH
183586. BLK_P2_PTR_LOW
183587. BLK_PINGPONG
183588. BLK_PIPELINE_INFO
183589. BLK_PLUG_FLUSH_SIZE
183590. BLK_PLUS_PRIV
183591. BLK_QC_T_EAGAIN
183592. BLK_QC_T_INTERNAL
183593. BLK_QC_T_NONE
183594. BLK_QC_T_SHIFT
183595. BLK_RGB
183596. BLK_RING_SIZE
183597. BLK_RW_ASYNC
183598. BLK_RW_CMP
183599. BLK_RW_SYNC
183600. BLK_SAFE_MAX_SECTORS
183601. BLK_SCSI_CMD_PER_LONG
183602. BLK_SCSI_MAX_CMDS
183603. BLK_SEG_BOUNDARY_MASK
183604. BLK_SIZE
183605. BLK_STATE_ALLDIRTY
183606. BLK_STATE_ALLFF
183607. BLK_STATE_BADBLOCK
183608. BLK_STATE_CLEAN
183609. BLK_STATE_CLEANMARKER
183610. BLK_STATE_PARTDIRTY
183611. BLK_STATUS
183612. BLK_STAT_H
183613. BLK_STS_AGAIN
183614. BLK_STS_DEV_RESOURCE
183615. BLK_STS_DM_REQUEUE
183616. BLK_STS_IOERR
183617. BLK_STS_MEDIUM
183618. BLK_STS_NEXUS
183619. BLK_STS_NOSPC
183620. BLK_STS_NOTSUPP
183621. BLK_STS_OK
183622. BLK_STS_PROTECTION
183623. BLK_STS_RESOURCE
183624. BLK_STS_TARGET
183625. BLK_STS_TIMEOUT
183626. BLK_STS_TRANSPORT
183627. BLK_TAG_ALLOC_FIFO
183628. BLK_TAG_ALLOC_NAME
183629. BLK_TAG_ALLOC_RR
183630. BLK_TA_ABORT
183631. BLK_TA_BACKMERGE
183632. BLK_TA_BOUNCE
183633. BLK_TA_COMPLETE
183634. BLK_TA_DRV_DATA
183635. BLK_TA_FRONTMERGE
183636. BLK_TA_GETRQ
183637. BLK_TA_INSERT
183638. BLK_TA_ISSUE
183639. BLK_TA_PLUG
183640. BLK_TA_QUEUE
183641. BLK_TA_REMAP
183642. BLK_TA_REQUEUE
183643. BLK_TA_SLEEPRQ
183644. BLK_TA_SPLIT
183645. BLK_TA_UNPLUG_IO
183646. BLK_TA_UNPLUG_TIMER
183647. BLK_TC_ACT
183648. BLK_TC_AHEAD
183649. BLK_TC_COMPLETE
183650. BLK_TC_DISCARD
183651. BLK_TC_DRV_DATA
183652. BLK_TC_END
183653. BLK_TC_FLUSH
183654. BLK_TC_FS
183655. BLK_TC_FUA
183656. BLK_TC_ISSUE
183657. BLK_TC_META
183658. BLK_TC_NOTIFY
183659. BLK_TC_PC
183660. BLK_TC_PREFLUSH
183661. BLK_TC_QUEUE
183662. BLK_TC_RAHEAD
183663. BLK_TC_READ
183664. BLK_TC_REQUEUE
183665. BLK_TC_SHIFT
183666. BLK_TC_SYNC
183667. BLK_TC_SYNCIO
183668. BLK_TC_WRITE
183669. BLK_TN_MAX_MSG
183670. BLK_TN_MESSAGE
183671. BLK_TN_PROCESS
183672. BLK_TN_TIMESTAMP
183673. BLK_TRACE_DEVICE_ATTR
183674. BLK_TYPE
183675. BLK_VALID_INPUT_ID0
183676. BLK_VIG
183677. BLK_ZONED_HA
183678. BLK_ZONED_HM
183679. BLK_ZONED_NONE
183680. BLK_ZONED_REPORT_MAX_ZONES
183681. BLK_ZONE_COND_CLOSED
183682. BLK_ZONE_COND_EMPTY
183683. BLK_ZONE_COND_EXP_OPEN
183684. BLK_ZONE_COND_FULL
183685. BLK_ZONE_COND_IMP_OPEN
183686. BLK_ZONE_COND_NOT_WP
183687. BLK_ZONE_COND_OFFLINE
183688. BLK_ZONE_COND_READONLY
183689. BLK_ZONE_TYPE_CONVENTIONAL
183690. BLK_ZONE_TYPE_SEQWRITE_PREF
183691. BLK_ZONE_TYPE_SEQWRITE_REQ
183692. BLMIN
183693. BLMOD_EN
183694. BLM_COMBINATION_MODE
183695. BLM_FADE_HSB
183696. BLM_FADE_RAND_HSB
183697. BLM_FADE_RAND_RGB
183698. BLM_FADE_RGB
183699. BLM_GET_ADDR
183700. BLM_GET_CUR_RGB
183701. BLM_GET_FW_VER
183702. BLM_GO_RGB
183703. BLM_HISTOGRAM_ENABLE
183704. BLM_LEGACY_MODE
183705. BLM_PCH_OVERRIDE_ENABLE
183706. BLM_PCH_POLARITY
183707. BLM_PCH_PWM_ENABLE
183708. BLM_PHASE_IN_COUNT_MASK
183709. BLM_PHASE_IN_COUNT_SHIFT
183710. BLM_PHASE_IN_ENABLE
183711. BLM_PHASE_IN_INCR_MASK
183712. BLM_PHASE_IN_INCR_SHIFT
183713. BLM_PHASE_IN_INTERUPT_ENABL
183714. BLM_PHASE_IN_INTERUPT_STATUS
183715. BLM_PHASE_IN_TIME_BASE_MASK
183716. BLM_PHASE_IN_TIME_BASE_SHIFT
183717. BLM_PIPE
183718. BLM_PIPE_A
183719. BLM_PIPE_B
183720. BLM_PIPE_C
183721. BLM_PIPE_SELECT
183722. BLM_PIPE_SELECT_IVB
183723. BLM_PLAY_SCRIPT
183724. BLM_POLARITY_I965
183725. BLM_POLARITY_PNV
183726. BLM_PWM_ENABLE
183727. BLM_READ_SCRIPT_LINE
183728. BLM_RX_NO_SWAP
183729. BLM_SET_ADDR
183730. BLM_SET_FADE_SPEED
183731. BLM_SET_SCRIPT_LR
183732. BLM_SET_STARTUP_PARAM
183733. BLM_SET_TIME_ADJ
183734. BLM_STOP_SCRIPT
183735. BLM_TRANSCODER_A
183736. BLM_TRANSCODER_B
183737. BLM_TRANSCODER_C
183738. BLM_TRANSCODER_EDP
183739. BLM_TX_NO_SWAP
183740. BLM_WRITE_SCRIPT_LINE
183741. BLNC_CHK
183742. BLND0_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK
183743. BLND0_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT
183744. BLND0_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK
183745. BLND0_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT
183746. BLND0_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK
183747. BLND0_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT
183748. BLND0_BLND_CONTROL2__PTI_ENABLE_MASK
183749. BLND0_BLND_CONTROL2__PTI_ENABLE__SHIFT
183750. BLND0_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK
183751. BLND0_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT
183752. BLND0_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK
183753. BLND0_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT
183754. BLND0_BLND_CONTROL__BLND_ALPHA_MODE_MASK
183755. BLND0_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT
183756. BLND0_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK
183757. BLND0_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT
183758. BLND0_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK
183759. BLND0_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT
183760. BLND0_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK
183761. BLND0_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT
183762. BLND0_BLND_CONTROL__BLND_MODE_MASK
183763. BLND0_BLND_CONTROL__BLND_MODE__SHIFT
183764. BLND0_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK
183765. BLND0_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT
183766. BLND0_BLND_CONTROL__BLND_STEREO_POLARITY_MASK
183767. BLND0_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT
183768. BLND0_BLND_CONTROL__BLND_STEREO_TYPE_MASK
183769. BLND0_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT
183770. BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK
183771. BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT
183772. BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK
183773. BLND0_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT
183774. BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK
183775. BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT
183776. BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK
183777. BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT
183778. BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK
183779. BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT
183780. BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK
183781. BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT
183782. BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK
183783. BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT
183784. BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK
183785. BLND0_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT
183786. BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK
183787. BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT
183788. BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK
183789. BLND0_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT
183790. BLND0_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK
183791. BLND0_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT
183792. BLND0_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK
183793. BLND0_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT
183794. BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK
183795. BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT
183796. BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK
183797. BLND0_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT
183798. BLND0_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK
183799. BLND0_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT
183800. BLND0_BLND_SM_CONTROL2__SM_MODE_MASK
183801. BLND0_BLND_SM_CONTROL2__SM_MODE__SHIFT
183802. BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK
183803. BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT
183804. BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK
183805. BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT
183806. BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK
183807. BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT
183808. BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK
183809. BLND0_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT
183810. BLND0_BLND_UPDATE__BLND_UPDATE_LOCK_MASK
183811. BLND0_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT
183812. BLND0_BLND_UPDATE__BLND_UPDATE_PENDING_MASK
183813. BLND0_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT
183814. BLND0_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK
183815. BLND0_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT
183816. BLND0_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK
183817. BLND0_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT
183818. BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK
183819. BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT
183820. BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK
183821. BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT
183822. BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK
183823. BLND0_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT
183824. BLND0_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK
183825. BLND0_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT
183826. BLND0_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK
183827. BLND0_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT
183828. BLND1_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK
183829. BLND1_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT
183830. BLND1_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK
183831. BLND1_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT
183832. BLND1_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK
183833. BLND1_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT
183834. BLND1_BLND_CONTROL2__PTI_ENABLE_MASK
183835. BLND1_BLND_CONTROL2__PTI_ENABLE__SHIFT
183836. BLND1_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK
183837. BLND1_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT
183838. BLND1_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK
183839. BLND1_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT
183840. BLND1_BLND_CONTROL__BLND_ALPHA_MODE_MASK
183841. BLND1_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT
183842. BLND1_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK
183843. BLND1_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT
183844. BLND1_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK
183845. BLND1_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT
183846. BLND1_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK
183847. BLND1_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT
183848. BLND1_BLND_CONTROL__BLND_MODE_MASK
183849. BLND1_BLND_CONTROL__BLND_MODE__SHIFT
183850. BLND1_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK
183851. BLND1_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT
183852. BLND1_BLND_CONTROL__BLND_STEREO_POLARITY_MASK
183853. BLND1_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT
183854. BLND1_BLND_CONTROL__BLND_STEREO_TYPE_MASK
183855. BLND1_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT
183856. BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK
183857. BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT
183858. BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK
183859. BLND1_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT
183860. BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK
183861. BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT
183862. BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK
183863. BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT
183864. BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK
183865. BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT
183866. BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK
183867. BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT
183868. BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK
183869. BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT
183870. BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK
183871. BLND1_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT
183872. BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK
183873. BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT
183874. BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK
183875. BLND1_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT
183876. BLND1_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK
183877. BLND1_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT
183878. BLND1_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK
183879. BLND1_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT
183880. BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK
183881. BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT
183882. BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK
183883. BLND1_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT
183884. BLND1_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK
183885. BLND1_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT
183886. BLND1_BLND_SM_CONTROL2__SM_MODE_MASK
183887. BLND1_BLND_SM_CONTROL2__SM_MODE__SHIFT
183888. BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK
183889. BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT
183890. BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK
183891. BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT
183892. BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK
183893. BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT
183894. BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK
183895. BLND1_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT
183896. BLND1_BLND_UPDATE__BLND_UPDATE_LOCK_MASK
183897. BLND1_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT
183898. BLND1_BLND_UPDATE__BLND_UPDATE_PENDING_MASK
183899. BLND1_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT
183900. BLND1_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK
183901. BLND1_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT
183902. BLND1_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK
183903. BLND1_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT
183904. BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK
183905. BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT
183906. BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK
183907. BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT
183908. BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK
183909. BLND1_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT
183910. BLND1_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK
183911. BLND1_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT
183912. BLND1_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK
183913. BLND1_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT
183914. BLND2_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK
183915. BLND2_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT
183916. BLND2_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK
183917. BLND2_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT
183918. BLND2_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK
183919. BLND2_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT
183920. BLND2_BLND_CONTROL2__PTI_ENABLE_MASK
183921. BLND2_BLND_CONTROL2__PTI_ENABLE__SHIFT
183922. BLND2_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK
183923. BLND2_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT
183924. BLND2_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK
183925. BLND2_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT
183926. BLND2_BLND_CONTROL__BLND_ALPHA_MODE_MASK
183927. BLND2_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT
183928. BLND2_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK
183929. BLND2_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT
183930. BLND2_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK
183931. BLND2_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT
183932. BLND2_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK
183933. BLND2_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT
183934. BLND2_BLND_CONTROL__BLND_MODE_MASK
183935. BLND2_BLND_CONTROL__BLND_MODE__SHIFT
183936. BLND2_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK
183937. BLND2_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT
183938. BLND2_BLND_CONTROL__BLND_STEREO_POLARITY_MASK
183939. BLND2_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT
183940. BLND2_BLND_CONTROL__BLND_STEREO_TYPE_MASK
183941. BLND2_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT
183942. BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK
183943. BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT
183944. BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK
183945. BLND2_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT
183946. BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK
183947. BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT
183948. BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK
183949. BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT
183950. BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK
183951. BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT
183952. BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK
183953. BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT
183954. BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK
183955. BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT
183956. BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK
183957. BLND2_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT
183958. BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK
183959. BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT
183960. BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK
183961. BLND2_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT
183962. BLND2_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK
183963. BLND2_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT
183964. BLND2_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK
183965. BLND2_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT
183966. BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK
183967. BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT
183968. BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK
183969. BLND2_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT
183970. BLND2_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK
183971. BLND2_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT
183972. BLND2_BLND_SM_CONTROL2__SM_MODE_MASK
183973. BLND2_BLND_SM_CONTROL2__SM_MODE__SHIFT
183974. BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK
183975. BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT
183976. BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK
183977. BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT
183978. BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK
183979. BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT
183980. BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK
183981. BLND2_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT
183982. BLND2_BLND_UPDATE__BLND_UPDATE_LOCK_MASK
183983. BLND2_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT
183984. BLND2_BLND_UPDATE__BLND_UPDATE_PENDING_MASK
183985. BLND2_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT
183986. BLND2_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK
183987. BLND2_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT
183988. BLND2_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK
183989. BLND2_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT
183990. BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK
183991. BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT
183992. BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK
183993. BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT
183994. BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK
183995. BLND2_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT
183996. BLND2_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK
183997. BLND2_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT
183998. BLND2_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK
183999. BLND2_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT
184000. BLND3_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK
184001. BLND3_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT
184002. BLND3_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK
184003. BLND3_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT
184004. BLND3_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK
184005. BLND3_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT
184006. BLND3_BLND_CONTROL2__PTI_ENABLE_MASK
184007. BLND3_BLND_CONTROL2__PTI_ENABLE__SHIFT
184008. BLND3_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK
184009. BLND3_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT
184010. BLND3_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK
184011. BLND3_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT
184012. BLND3_BLND_CONTROL__BLND_ALPHA_MODE_MASK
184013. BLND3_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT
184014. BLND3_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK
184015. BLND3_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT
184016. BLND3_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK
184017. BLND3_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT
184018. BLND3_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK
184019. BLND3_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT
184020. BLND3_BLND_CONTROL__BLND_MODE_MASK
184021. BLND3_BLND_CONTROL__BLND_MODE__SHIFT
184022. BLND3_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK
184023. BLND3_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT
184024. BLND3_BLND_CONTROL__BLND_STEREO_POLARITY_MASK
184025. BLND3_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT
184026. BLND3_BLND_CONTROL__BLND_STEREO_TYPE_MASK
184027. BLND3_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT
184028. BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK
184029. BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT
184030. BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK
184031. BLND3_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT
184032. BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK
184033. BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT
184034. BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK
184035. BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT
184036. BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK
184037. BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT
184038. BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK
184039. BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT
184040. BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK
184041. BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT
184042. BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK
184043. BLND3_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT
184044. BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK
184045. BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT
184046. BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK
184047. BLND3_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT
184048. BLND3_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK
184049. BLND3_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT
184050. BLND3_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK
184051. BLND3_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT
184052. BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK
184053. BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT
184054. BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK
184055. BLND3_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT
184056. BLND3_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK
184057. BLND3_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT
184058. BLND3_BLND_SM_CONTROL2__SM_MODE_MASK
184059. BLND3_BLND_SM_CONTROL2__SM_MODE__SHIFT
184060. BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK
184061. BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT
184062. BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK
184063. BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT
184064. BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK
184065. BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT
184066. BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK
184067. BLND3_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT
184068. BLND3_BLND_UPDATE__BLND_UPDATE_LOCK_MASK
184069. BLND3_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT
184070. BLND3_BLND_UPDATE__BLND_UPDATE_PENDING_MASK
184071. BLND3_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT
184072. BLND3_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK
184073. BLND3_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT
184074. BLND3_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK
184075. BLND3_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT
184076. BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK
184077. BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT
184078. BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK
184079. BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT
184080. BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK
184081. BLND3_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT
184082. BLND3_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK
184083. BLND3_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT
184084. BLND3_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK
184085. BLND3_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT
184086. BLND4_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK
184087. BLND4_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT
184088. BLND4_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK
184089. BLND4_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT
184090. BLND4_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK
184091. BLND4_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT
184092. BLND4_BLND_CONTROL2__PTI_ENABLE_MASK
184093. BLND4_BLND_CONTROL2__PTI_ENABLE__SHIFT
184094. BLND4_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK
184095. BLND4_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT
184096. BLND4_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK
184097. BLND4_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT
184098. BLND4_BLND_CONTROL__BLND_ALPHA_MODE_MASK
184099. BLND4_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT
184100. BLND4_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK
184101. BLND4_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT
184102. BLND4_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK
184103. BLND4_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT
184104. BLND4_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK
184105. BLND4_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT
184106. BLND4_BLND_CONTROL__BLND_MODE_MASK
184107. BLND4_BLND_CONTROL__BLND_MODE__SHIFT
184108. BLND4_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK
184109. BLND4_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT
184110. BLND4_BLND_CONTROL__BLND_STEREO_POLARITY_MASK
184111. BLND4_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT
184112. BLND4_BLND_CONTROL__BLND_STEREO_TYPE_MASK
184113. BLND4_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT
184114. BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK
184115. BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT
184116. BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK
184117. BLND4_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT
184118. BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK
184119. BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT
184120. BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK
184121. BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT
184122. BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK
184123. BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT
184124. BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK
184125. BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT
184126. BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK
184127. BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT
184128. BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK
184129. BLND4_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT
184130. BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK
184131. BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT
184132. BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK
184133. BLND4_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT
184134. BLND4_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK
184135. BLND4_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT
184136. BLND4_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK
184137. BLND4_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT
184138. BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK
184139. BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT
184140. BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK
184141. BLND4_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT
184142. BLND4_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK
184143. BLND4_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT
184144. BLND4_BLND_SM_CONTROL2__SM_MODE_MASK
184145. BLND4_BLND_SM_CONTROL2__SM_MODE__SHIFT
184146. BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK
184147. BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT
184148. BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK
184149. BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT
184150. BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK
184151. BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT
184152. BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK
184153. BLND4_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT
184154. BLND4_BLND_UPDATE__BLND_UPDATE_LOCK_MASK
184155. BLND4_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT
184156. BLND4_BLND_UPDATE__BLND_UPDATE_PENDING_MASK
184157. BLND4_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT
184158. BLND4_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK
184159. BLND4_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT
184160. BLND4_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK
184161. BLND4_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT
184162. BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK
184163. BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT
184164. BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK
184165. BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT
184166. BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK
184167. BLND4_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT
184168. BLND4_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK
184169. BLND4_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT
184170. BLND4_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK
184171. BLND4_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT
184172. BLND5_BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK
184173. BLND5_BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT
184174. BLND5_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK
184175. BLND5_BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT
184176. BLND5_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK
184177. BLND5_BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT
184178. BLND5_BLND_CONTROL2__PTI_ENABLE_MASK
184179. BLND5_BLND_CONTROL2__PTI_ENABLE__SHIFT
184180. BLND5_BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK
184181. BLND5_BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT
184182. BLND5_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK
184183. BLND5_BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT
184184. BLND5_BLND_CONTROL__BLND_ALPHA_MODE_MASK
184185. BLND5_BLND_CONTROL__BLND_ALPHA_MODE__SHIFT
184186. BLND5_BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK
184187. BLND5_BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT
184188. BLND5_BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK
184189. BLND5_BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT
184190. BLND5_BLND_CONTROL__BLND_GLOBAL_GAIN_MASK
184191. BLND5_BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT
184192. BLND5_BLND_CONTROL__BLND_MODE_MASK
184193. BLND5_BLND_CONTROL__BLND_MODE__SHIFT
184194. BLND5_BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK
184195. BLND5_BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT
184196. BLND5_BLND_CONTROL__BLND_STEREO_POLARITY_MASK
184197. BLND5_BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT
184198. BLND5_BLND_CONTROL__BLND_STEREO_TYPE_MASK
184199. BLND5_BLND_CONTROL__BLND_STEREO_TYPE__SHIFT
184200. BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK
184201. BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT
184202. BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK
184203. BLND5_BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT
184204. BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK
184205. BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT
184206. BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK
184207. BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT
184208. BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK
184209. BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT
184210. BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK
184211. BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT
184212. BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK
184213. BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT
184214. BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK
184215. BLND5_BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT
184216. BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK
184217. BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT
184218. BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK
184219. BLND5_BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT
184220. BLND5_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK
184221. BLND5_BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT
184222. BLND5_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK
184223. BLND5_BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT
184224. BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK
184225. BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT
184226. BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK
184227. BLND5_BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT
184228. BLND5_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK
184229. BLND5_BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT
184230. BLND5_BLND_SM_CONTROL2__SM_MODE_MASK
184231. BLND5_BLND_SM_CONTROL2__SM_MODE__SHIFT
184232. BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK
184233. BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT
184234. BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK
184235. BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT
184236. BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK
184237. BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT
184238. BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK
184239. BLND5_BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT
184240. BLND5_BLND_UPDATE__BLND_UPDATE_LOCK_MASK
184241. BLND5_BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT
184242. BLND5_BLND_UPDATE__BLND_UPDATE_PENDING_MASK
184243. BLND5_BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT
184244. BLND5_BLND_UPDATE__BLND_UPDATE_TAKEN_MASK
184245. BLND5_BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT
184246. BLND5_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK
184247. BLND5_BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT
184248. BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK
184249. BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT
184250. BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK
184251. BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT
184252. BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK
184253. BLND5_BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT
184254. BLND5_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK
184255. BLND5_BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT
184256. BLND5_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK
184257. BLND5_BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT
184258. BLNDV0_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK
184259. BLNDV0_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT
184260. BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK
184261. BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT
184262. BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK
184263. BLNDV0_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT
184264. BLNDV0_BLNDV_CONTROL2__PTI_ENABLE_MASK
184265. BLNDV0_BLNDV_CONTROL2__PTI_ENABLE__SHIFT
184266. BLNDV0_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK
184267. BLNDV0_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT
184268. BLNDV0_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK
184269. BLNDV0_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT
184270. BLNDV0_BLNDV_CONTROL__BLND_ALPHA_MODE_MASK
184271. BLNDV0_BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT
184272. BLNDV0_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK
184273. BLNDV0_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT
184274. BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK
184275. BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT
184276. BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK
184277. BLNDV0_BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT
184278. BLNDV0_BLNDV_CONTROL__BLND_MODE_MASK
184279. BLNDV0_BLNDV_CONTROL__BLND_MODE__SHIFT
184280. BLNDV0_BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK
184281. BLNDV0_BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT
184282. BLNDV0_BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK
184283. BLNDV0_BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT
184284. BLNDV0_BLNDV_CONTROL__BLND_STEREO_TYPE_MASK
184285. BLNDV0_BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT
184286. BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK
184287. BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT
184288. BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK
184289. BLNDV0_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT
184290. BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK
184291. BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT
184292. BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK
184293. BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT
184294. BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK
184295. BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT
184296. BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK
184297. BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT
184298. BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK
184299. BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT
184300. BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK
184301. BLNDV0_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT
184302. BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK
184303. BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT
184304. BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK
184305. BLNDV0_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT
184306. BLNDV0_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK
184307. BLNDV0_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT
184308. BLNDV0_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK
184309. BLNDV0_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT
184310. BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK
184311. BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT
184312. BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK
184313. BLNDV0_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT
184314. BLNDV0_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK
184315. BLNDV0_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT
184316. BLNDV0_BLNDV_SM_CONTROL2__SM_MODE_MASK
184317. BLNDV0_BLNDV_SM_CONTROL2__SM_MODE__SHIFT
184318. BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK
184319. BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT
184320. BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK
184321. BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT
184322. BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK
184323. BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT
184324. BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK
184325. BLNDV0_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT
184326. BLNDV0_BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK
184327. BLNDV0_BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT
184328. BLNDV0_BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK
184329. BLNDV0_BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT
184330. BLNDV0_BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK
184331. BLNDV0_BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT
184332. BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK
184333. BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT
184334. BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK
184335. BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT
184336. BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK
184337. BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT
184338. BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK
184339. BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT
184340. BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK
184341. BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT
184342. BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK
184343. BLNDV0_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT
184344. BLNDV1_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK
184345. BLNDV1_BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT
184346. BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK
184347. BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT
184348. BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK
184349. BLNDV1_BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT
184350. BLNDV1_BLNDV_CONTROL2__PTI_ENABLE_MASK
184351. BLNDV1_BLNDV_CONTROL2__PTI_ENABLE__SHIFT
184352. BLNDV1_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK
184353. BLNDV1_BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT
184354. BLNDV1_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK
184355. BLNDV1_BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT
184356. BLNDV1_BLNDV_CONTROL__BLND_ALPHA_MODE_MASK
184357. BLNDV1_BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT
184358. BLNDV1_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK
184359. BLNDV1_BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT
184360. BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK
184361. BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT
184362. BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK
184363. BLNDV1_BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT
184364. BLNDV1_BLNDV_CONTROL__BLND_MODE_MASK
184365. BLNDV1_BLNDV_CONTROL__BLND_MODE__SHIFT
184366. BLNDV1_BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK
184367. BLNDV1_BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT
184368. BLNDV1_BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK
184369. BLNDV1_BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT
184370. BLNDV1_BLNDV_CONTROL__BLND_STEREO_TYPE_MASK
184371. BLNDV1_BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT
184372. BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK
184373. BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT
184374. BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK
184375. BLNDV1_BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT
184376. BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK
184377. BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT
184378. BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK
184379. BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT
184380. BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK
184381. BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT
184382. BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK
184383. BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT
184384. BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK
184385. BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT
184386. BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK
184387. BLNDV1_BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT
184388. BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK
184389. BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT
184390. BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK
184391. BLNDV1_BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT
184392. BLNDV1_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK
184393. BLNDV1_BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT
184394. BLNDV1_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK
184395. BLNDV1_BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT
184396. BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK
184397. BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT
184398. BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK
184399. BLNDV1_BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT
184400. BLNDV1_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK
184401. BLNDV1_BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT
184402. BLNDV1_BLNDV_SM_CONTROL2__SM_MODE_MASK
184403. BLNDV1_BLNDV_SM_CONTROL2__SM_MODE__SHIFT
184404. BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK
184405. BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT
184406. BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK
184407. BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT
184408. BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK
184409. BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT
184410. BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK
184411. BLNDV1_BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT
184412. BLNDV1_BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK
184413. BLNDV1_BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT
184414. BLNDV1_BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK
184415. BLNDV1_BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT
184416. BLNDV1_BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK
184417. BLNDV1_BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT
184418. BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK
184419. BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT
184420. BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK
184421. BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT
184422. BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK
184423. BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT
184424. BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK
184425. BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT
184426. BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK
184427. BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT
184428. BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK
184429. BLNDV1_BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT
184430. BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN
184431. BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE
184432. BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE
184433. BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN
184434. BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE
184435. BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE
184436. BLNDV_CONTROL2_PTI_ENABLE
184437. BLNDV_CONTROL2_PTI_ENABLE_FALSE
184438. BLNDV_CONTROL2_PTI_ENABLE_TRUE
184439. BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK
184440. BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT
184441. BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK
184442. BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT
184443. BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK
184444. BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT
184445. BLNDV_CONTROL2__PTI_ENABLE_MASK
184446. BLNDV_CONTROL2__PTI_ENABLE__SHIFT
184447. BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK
184448. BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT
184449. BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY
184450. BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE
184451. BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE
184452. BLNDV_CONTROL_BLND_ALPHA_MODE
184453. BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA
184454. BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY
184455. BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN
184456. BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED
184457. BLNDV_CONTROL_BLND_FEEDTHROUGH_EN
184458. BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE
184459. BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE
184460. BLNDV_CONTROL_BLND_MODE
184461. BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE
184462. BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY
184463. BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY
184464. BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE
184465. BLNDV_CONTROL_BLND_MULTIPLIED_MODE
184466. BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE
184467. BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE
184468. BLNDV_CONTROL_BLND_STEREO_POLARITY
184469. BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH
184470. BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW
184471. BLNDV_CONTROL_BLND_STEREO_TYPE
184472. BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO
184473. BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO
184474. BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO
184475. BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED
184476. BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK
184477. BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT
184478. BLNDV_CONTROL__BLND_ALPHA_MODE_MASK
184479. BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT
184480. BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK
184481. BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT
184482. BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK
184483. BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT
184484. BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK
184485. BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT
184486. BLNDV_CONTROL__BLND_MODE_MASK
184487. BLNDV_CONTROL__BLND_MODE__SHIFT
184488. BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK
184489. BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT
184490. BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK
184491. BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT
184492. BLNDV_CONTROL__BLND_STEREO_TYPE_MASK
184493. BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT
184494. BLNDV_DEBUG_BLND_CNV_MUX_SELECT
184495. BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH
184496. BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW
184497. BLNDV_DEBUG__BLND_CNV_MUX_SELECT_MASK
184498. BLNDV_DEBUG__BLND_CNV_MUX_SELECT__SHIFT
184499. BLNDV_DEBUG__BLND_DEBUG_MASK
184500. BLNDV_DEBUG__BLND_DEBUG__SHIFT
184501. BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK
184502. BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT
184503. BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK
184504. BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT
184505. BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK
184506. BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT
184507. BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK
184508. BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT
184509. BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK
184510. BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT
184511. BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK
184512. BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT
184513. BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK
184514. BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT
184515. BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK
184516. BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT
184517. BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK
184518. BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT
184519. BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK
184520. BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT
184521. BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE
184522. BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE
184523. BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE
184524. BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL
184525. BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH
184526. BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW
184527. BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE
184528. BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED
184529. BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL
184530. BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH
184531. BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW
184532. BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE
184533. BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED
184534. BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE
184535. BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE
184536. BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE
184537. BLNDV_SM_CONTROL2_SM_MODE
184538. BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING
184539. BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING
184540. BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING
184541. BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE
184542. BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK
184543. BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT
184544. BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK
184545. BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT
184546. BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK
184547. BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT
184548. BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK
184549. BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT
184550. BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK
184551. BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT
184552. BLNDV_SM_CONTROL2__SM_MODE_MASK
184553. BLNDV_SM_CONTROL2__SM_MODE__SHIFT
184554. BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK
184555. BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT
184556. BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN
184557. BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE
184558. BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE
184559. BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK
184560. BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT
184561. BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK
184562. BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT
184563. BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK
184564. BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE
184565. BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE
184566. BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK
184567. BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE
184568. BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE
184569. BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK
184570. BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT
184571. BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK
184572. BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT
184573. BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK
184574. BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT
184575. BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK
184576. BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT
184577. BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK
184578. BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT
184579. BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK
184580. BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT
184581. BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK
184582. BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT
184583. BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK
184584. BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE
184585. BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE
184586. BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK
184587. BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE
184588. BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE
184589. BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK
184590. BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE
184591. BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE
184592. BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK
184593. BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE
184594. BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE
184595. BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK
184596. BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE
184597. BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE
184598. BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK
184599. BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE
184600. BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE
184601. BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE
184602. BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE
184603. BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE
184604. BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK
184605. BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT
184606. BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK
184607. BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT
184608. BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK
184609. BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT
184610. BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK
184611. BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT
184612. BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK
184613. BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT
184614. BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK
184615. BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT
184616. BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK
184617. BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT
184618. BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN
184619. BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE
184620. BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE
184621. BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN
184622. BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE
184623. BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE
184624. BLND_CONTROL2_PTI_ENABLE
184625. BLND_CONTROL2_PTI_ENABLE_FALSE
184626. BLND_CONTROL2_PTI_ENABLE_TRUE
184627. BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK
184628. BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT
184629. BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK
184630. BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT
184631. BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK
184632. BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT
184633. BLND_CONTROL2__PTI_ENABLE_MASK
184634. BLND_CONTROL2__PTI_ENABLE__SHIFT
184635. BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK
184636. BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT
184637. BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY
184638. BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE
184639. BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE
184640. BLND_CONTROL_BLND_ALPHA_MODE
184641. BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA
184642. BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY
184643. BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN
184644. BLND_CONTROL_BLND_ALPHA_MODE_UNUSED
184645. BLND_CONTROL_BLND_FEEDTHROUGH_EN
184646. BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE
184647. BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE
184648. BLND_CONTROL_BLND_MODE
184649. BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE
184650. BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY
184651. BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY
184652. BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE
184653. BLND_CONTROL_BLND_MULTIPLIED_MODE
184654. BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE
184655. BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE
184656. BLND_CONTROL_BLND_STEREO_POLARITY
184657. BLND_CONTROL_BLND_STEREO_POLARITY_HIGH
184658. BLND_CONTROL_BLND_STEREO_POLARITY_LOW
184659. BLND_CONTROL_BLND_STEREO_TYPE
184660. BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO
184661. BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO
184662. BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO
184663. BLND_CONTROL_BLND_STEREO_TYPE_UNUSED
184664. BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK
184665. BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT
184666. BLND_CONTROL__BLND_ALPHA_MODE_MASK
184667. BLND_CONTROL__BLND_ALPHA_MODE__SHIFT
184668. BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK
184669. BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT
184670. BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK
184671. BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT
184672. BLND_CONTROL__BLND_GLOBAL_GAIN_MASK
184673. BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT
184674. BLND_CONTROL__BLND_MODE_MASK
184675. BLND_CONTROL__BLND_MODE__SHIFT
184676. BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK
184677. BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT
184678. BLND_CONTROL__BLND_STEREO_POLARITY_MASK
184679. BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT
184680. BLND_CONTROL__BLND_STEREO_TYPE_MASK
184681. BLND_CONTROL__BLND_STEREO_TYPE__SHIFT
184682. BLND_DEBUG_BLND_CNV_MUX_SELECT
184683. BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH
184684. BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW
184685. BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK
184686. BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT
184687. BLND_DEBUG__BLND_DEBUG_MASK
184688. BLND_DEBUG__BLND_DEBUG__SHIFT
184689. BLND_MODE_BLENDING
184690. BLND_MODE_CURRENT_PIPE
184691. BLND_MODE_OTHER_PIPE
184692. BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK
184693. BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT
184694. BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK
184695. BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT
184696. BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK
184697. BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT
184698. BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK
184699. BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT
184700. BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK
184701. BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT
184702. BLND_REG_UPDATE_STATUS__DCP_BLNDC_OVL_UPDATE_PENDING_MASK
184703. BLND_REG_UPDATE_STATUS__DCP_BLNDC_OVL_UPDATE_PENDING__SHIFT
184704. BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK
184705. BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT
184706. BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK
184707. BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT
184708. BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK
184709. BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT
184710. BLND_REG_UPDATE_STATUS__DCP_BLNDO_OVL_UPDATE_PENDING_MASK
184711. BLND_REG_UPDATE_STATUS__DCP_BLNDO_OVL_UPDATE_PENDING__SHIFT
184712. BLND_REG_UPDATE_STATUS__DCP_BLNDc_CUR_UPDATE_PENDING_MASK
184713. BLND_REG_UPDATE_STATUS__DCP_BLNDc_CUR_UPDATE_PENDING__SHIFT
184714. BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_SURF_UPDATE_PENDING_MASK
184715. BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_SURF_UPDATE_PENDING__SHIFT
184716. BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_UPDATE_PENDING_MASK
184717. BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_UPDATE_PENDING__SHIFT
184718. BLND_REG_UPDATE_STATUS__DCP_BLNDc_OVL_UPDATE_PENDING_MASK
184719. BLND_REG_UPDATE_STATUS__DCP_BLNDc_OVL_UPDATE_PENDING__SHIFT
184720. BLND_REG_UPDATE_STATUS__DCP_BLNDo_CUR_UPDATE_PENDING_MASK
184721. BLND_REG_UPDATE_STATUS__DCP_BLNDo_CUR_UPDATE_PENDING__SHIFT
184722. BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_SURF_UPDATE_PENDING_MASK
184723. BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_SURF_UPDATE_PENDING__SHIFT
184724. BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_UPDATE_PENDING_MASK
184725. BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_UPDATE_PENDING__SHIFT
184726. BLND_REG_UPDATE_STATUS__DCP_BLNDo_OVL_UPDATE_PENDING_MASK
184727. BLND_REG_UPDATE_STATUS__DCP_BLNDo_OVL_UPDATE_PENDING__SHIFT
184728. BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK
184729. BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT
184730. BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK
184731. BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT
184732. BLND_REG_UPDATE_STATUS__SCL_BLNDc_UPDATE_PENDING_MASK
184733. BLND_REG_UPDATE_STATUS__SCL_BLNDc_UPDATE_PENDING__SHIFT
184734. BLND_REG_UPDATE_STATUS__SCL_BLNDo_UPDATE_PENDING_MASK
184735. BLND_REG_UPDATE_STATUS__SCL_BLNDo_UPDATE_PENDING__SHIFT
184736. BLND_SM_CONTROL2_SM_FIELD_ALTERNATE
184737. BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE
184738. BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE
184739. BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL
184740. BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH
184741. BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW
184742. BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE
184743. BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED
184744. BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL
184745. BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH
184746. BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW
184747. BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE
184748. BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED
184749. BLND_SM_CONTROL2_SM_FRAME_ALTERNATE
184750. BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE
184751. BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE
184752. BLND_SM_CONTROL2_SM_MODE
184753. BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING
184754. BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING
184755. BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING
184756. BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE
184757. BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK
184758. BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT
184759. BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK
184760. BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT
184761. BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK
184762. BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT
184763. BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK
184764. BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT
184765. BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK
184766. BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT
184767. BLND_SM_CONTROL2__SM_MODE_MASK
184768. BLND_SM_CONTROL2__SM_MODE__SHIFT
184769. BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK
184770. BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT
184771. BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN
184772. BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE
184773. BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE
184774. BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK
184775. BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT
184776. BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK
184777. BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT
184778. BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK
184779. BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE
184780. BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE
184781. BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK
184782. BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE
184783. BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE
184784. BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK
184785. BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT
184786. BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK
184787. BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT
184788. BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK
184789. BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT
184790. BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK
184791. BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT
184792. BLND_UPDATE__BLND_UPDATE_LOCK_MASK
184793. BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT
184794. BLND_UPDATE__BLND_UPDATE_PENDING_MASK
184795. BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT
184796. BLND_UPDATE__BLND_UPDATE_TAKEN_MASK
184797. BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT
184798. BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK
184799. BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE
184800. BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE
184801. BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK
184802. BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE
184803. BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE
184804. BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK
184805. BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE
184806. BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE
184807. BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK
184808. BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE
184809. BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE
184810. BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK
184811. BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE
184812. BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE
184813. BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK
184814. BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE
184815. BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE
184816. BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE
184817. BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE
184818. BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE
184819. BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK
184820. BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT
184821. BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK
184822. BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT
184823. BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK
184824. BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT
184825. BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK
184826. BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT
184827. BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK
184828. BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT
184829. BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK_MASK
184830. BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK__SHIFT
184831. BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK
184832. BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT
184833. BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK
184834. BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT
184835. BLOB_7220_IBCHG
184836. BLOB_7322_IBCHG
184837. BLOCK
184838. BLOCK0_FI
184839. BLOCK0_MC
184840. BLOCK0_MCS
184841. BLOCK0_REG_BANK
184842. BLOCK0_SPARE
184843. BLOCK0_SPARE_OOB_CLK_SEL_MASK
184844. BLOCK0_SPARE_OOB_CLK_SEL_REFBY2
184845. BLOCK0_XGXSSTATUS
184846. BLOCK0_XGXSSTATUS_PLL_LOCK
184847. BLOCK16
184848. BLOCK4
184849. BLOCKACK
184850. BLOCKACKPARAM_AMSDU_SUPP_MASK
184851. BLOCKACKPARAM_TID_POS
184852. BLOCKACKPARAM_WINSIZE_POS
184853. BLOCKCIPHER_BLOCK_SIZE
184854. BLOCKCIPHER_KEY_SIZE
184855. BLOCKED
184856. BLOCKED_HASH_BITS
184857. BLOCKING
184858. BLOCKING_INIT_NOTIFIER_HEAD
184859. BLOCKING_NAMED_PIPE
184860. BLOCKING_NOTIFIER_HEAD
184861. BLOCKING_NOTIFIER_INIT
184862. BLOCKMOVE
184863. BLOCKRST
184864. BLOCKS
184865. BLOCKSIZE
184866. BLOCKS_CTR
184867. BLOCKS_PER_COREGROUP
184868. BLOCKS_PER_PAGE
184869. BLOCK_1_NUM
184870. BLOCK_1_SIZE
184871. BLOCK_2_EXP_SIZE
184872. BLOCK_2_NUM
184873. BLOCK_2_SIZE
184874. BLOCK_3_NUM
184875. BLOCK_3_SIZE
184876. BLOCK_ACK
184877. BLOCK_ADDR1_H
184878. BLOCK_ADDR1_L
184879. BLOCK_ADDR2_H
184880. BLOCK_ADDR2_L
184881. BLOCK_ADDRESS
184882. BLOCK_ATC
184883. BLOCK_ATTR
184884. BLOCK_AVS_WRAP
184885. BLOCK_AXG_MAC_CSR_OFFSET
184886. BLOCK_AXG_MAC_OFFSET
184887. BLOCK_AXG_STATS_OFFSET
184888. BLOCK_BAD
184889. BLOCK_BAR0_MAP
184890. BLOCK_BITMAP
184891. BLOCK_BMB
184892. BLOCK_BMBN
184893. BLOCK_BOOT
184894. BLOCK_BRB
184895. BLOCK_BRB1
184896. BLOCK_BTB
184897. BLOCK_CAU
184898. BLOCK_CCFC
184899. BLOCK_CCM
184900. BLOCK_CDU
184901. BLOCK_CFC
184902. BLOCK_CNIG
184903. BLOCK_CONTEXT_DONE
184904. BLOCK_CONTROL
184905. BLOCK_COST
184906. BLOCK_COUNT_0
184907. BLOCK_COUNT_1
184908. BLOCK_COUNT_MASK
184909. BLOCK_CPMU
184910. BLOCK_CSDM
184911. BLOCK_CSEM
184912. BLOCK_DATA
184913. BLOCK_DBG
184914. BLOCK_DBU
184915. BLOCK_DELETED
184916. BLOCK_DIAG_CSR_OFFSET
184917. BLOCK_DIRTIED
184918. BLOCK_DMAE
184919. BLOCK_DMA_ALLOC_SZ
184920. BLOCK_DORQ
184921. BLOCK_DWORDS
184922. BLOCK_END
184923. BLOCK_ERASE
184924. BLOCK_ERASED
184925. BLOCK_ERASING
184926. BLOCK_ERROR
184927. BLOCK_ETH_CLE_CSR_OFFSET
184928. BLOCK_ETH_CLKRST_CSR_OFFSET
184929. BLOCK_ETH_CSR_OFFSET
184930. BLOCK_ETH_DIAG_CSR_OFFSET
184931. BLOCK_ETH_MAC_CSR_OFFSET
184932. BLOCK_ETH_MAC_OFFSET
184933. BLOCK_ETH_RING_IF_OFFSET
184934. BLOCK_ETH_STATS_OFFSET
184935. BLOCK_EXT_MAJOR
184936. BLOCK_FAILED
184937. BLOCK_FREE
184938. BLOCK_FREED
184939. BLOCK_FREED_HOLDER
184940. BLOCK_GRC
184941. BLOCK_HASH_SHIFT
184942. BLOCK_HC
184943. BLOCK_HW_QUEUE
184944. BLOCK_IGU
184945. BLOCK_INFO_BLK_ID
184946. BLOCK_INFO_BLK_TYPE
184947. BLOCK_INFO_INPUT_ID
184948. BLOCK_INFO_N_SUBBLKS
184949. BLOCK_INFO_TYPE_ID
184950. BLOCK_IPC
184951. BLOCK_IS_RESERVED
184952. BLOCK_LAYER_SECTOR
184953. BLOCK_LCD_SHIFT
184954. BLOCK_LDO1_SHIFT
184955. BLOCK_LDO2_SHIFT
184956. BLOCK_LED
184957. BLOCK_LEN
184958. BLOCK_LSN
184959. BLOCK_MASK
184960. BLOCK_MAX
184961. BLOCK_MCM
184962. BLOCK_MCP
184963. BLOCK_MCP2
184964. BLOCK_MEM_RDY
184965. BLOCK_MISC
184966. BLOCK_MISCS
184967. BLOCK_MISC_AEU
184968. BLOCK_MODE
184969. BLOCK_MS
184970. BLOCK_MSDM
184971. BLOCK_MSEM
184972. BLOCK_MULD
184973. BLOCK_NCSI
184974. BLOCK_NEEDS_FLUSH
184975. BLOCK_NIG
184976. BLOCK_NIL
184977. BLOCK_NOTEXPLORED
184978. BLOCK_NUMBER
184979. BLOCK_NUMBER_OFFSET
184980. BLOCK_NUM_PKTS
184981. BLOCK_NWM
184982. BLOCK_NWS
184983. BLOCK_O2FP
184984. BLOCK_O2PRIV
184985. BLOCK_OFFSET_VALUE_OFF
184986. BLOCK_OK
184987. BLOCK_OPS_IDX
184988. BLOCK_OPTE
184989. BLOCK_PBF
184990. BLOCK_PBF_PB1
184991. BLOCK_PBF_PB2
184992. BLOCK_PCIE
184993. BLOCK_PCM
184994. BLOCK_PCS_OFFSET
184995. BLOCK_PER_IMAGE_2_EXP_SIZE
184996. BLOCK_PGLCS
184997. BLOCK_PGLUE_B
184998. BLOCK_PHY_PCIE
184999. BLOCK_PRIV
185000. BLOCK_PRM
185001. BLOCK_PROTECT_BITS
185002. BLOCK_PRS
185003. BLOCK_PRTY_INFO
185004. BLOCK_PRTY_INFO_0
185005. BLOCK_PRTY_INFO_1
185006. BLOCK_PSDM
185007. BLOCK_PSEM
185008. BLOCK_PSWHST
185009. BLOCK_PSWHST2
185010. BLOCK_PSWRD
185011. BLOCK_PSWRD2
185012. BLOCK_PSWRQ
185013. BLOCK_PSWRQ2
185014. BLOCK_PSWWR
185015. BLOCK_PSWWR2
185016. BLOCK_PTLD
185017. BLOCK_PTU
185018. BLOCK_PXP
185019. BLOCK_PXP2
185020. BLOCK_PXPREQBUS
185021. BLOCK_QM
185022. BLOCK_RDIF
185023. BLOCK_READ
185024. BLOCK_REPLACEMENT
185025. BLOCK_RESERVED
185026. BLOCK_RGFS
185027. BLOCK_RGND_INT
185028. BLOCK_RGSRC
185029. BLOCK_RPB
185030. BLOCK_RSS
185031. BLOCK_SECTORS
185032. BLOCK_SECTOR_SHIFT
185033. BLOCK_SIZE
185034. BLOCK_SIZE_0
185035. BLOCK_SIZE_1
185036. BLOCK_SIZE_128
185037. BLOCK_SIZE_64
185038. BLOCK_SIZE_BITS
185039. BLOCK_SIZE_MASK
185040. BLOCK_SNUM
185041. BLOCK_SOFTIRQ
185042. BLOCK_SRC
185043. BLOCK_STATUS
185044. BLOCK_TCFC
185045. BLOCK_TCM
185046. BLOCK_TDIF
185047. BLOCK_TGFS
185048. BLOCK_TGSRC
185049. BLOCK_TM
185050. BLOCK_TMLD
185051. BLOCK_TSDM
185052. BLOCK_TSEM
185053. BLOCK_TXEN_MODE
185054. BLOCK_TYPE
185055. BLOCK_UCM
185056. BLOCK_UMAC
185057. BLOCK_UNDEF
185058. BLOCK_UNMASK_COMPLEMENT
185059. BLOCK_UNUSED
185060. BLOCK_UPB
185061. BLOCK_USB_SHIFT
185062. BLOCK_USDM
185063. BLOCK_USEM
185064. BLOCK_WOL
185065. BLOCK_WRITE
185066. BLOCK_WRITE_ENABLE
185067. BLOCK_XCM
185068. BLOCK_XG_MDIO_CSR_OFFSET
185069. BLOCK_XMAC
185070. BLOCK_XPB
185071. BLOCK_XSDM
185072. BLOCK_XSEM
185073. BLOCK_XYLD
185074. BLOCK_YCM
185075. BLOCK_YPLD
185076. BLOCK_YSDM
185077. BLOCK_YSEM
185078. BLOCK_YULD
185079. BLOGIC_ABRT_QUEUE
185080. BLOGIC_ADAPTER_DIAG
185081. BLOGIC_ADAPTER_SW_ERROR
185082. BLOGIC_AGGRESSIVE_RR
185083. BLOGIC_ANNOUNCE_LEVEL
185084. BLOGIC_AUTOREQSENSE_FAIL
185085. BLOGIC_AUTOSCSI_BASE
185086. BLOGIC_BAD_CMD_PARAM
185087. BLOGIC_BAD_MSG_RCVD
185088. BLOGIC_BAD_RECONNECT
185089. BLOGIC_BDR
185090. BLOGIC_BIOS_BASE
185091. BLOGIC_BIOS_DISK128x32
185092. BLOGIC_BIOS_DISK255x63
185093. BLOGIC_BIOS_DISK64x32
185094. BLOGIC_BIOS_DRVMAP
185095. BLOGIC_BIOS_NODISK
185096. BLOGIC_BUS_SETTLE_TIME
185097. BLOGIC_CCB_ACTIVE
185098. BLOGIC_CCB_COMPLETE
185099. BLOGIC_CCB_FREE
185100. BLOGIC_CCB_GRP_ALLOCSIZE
185101. BLOGIC_CCB_RESET
185102. BLOGIC_CDB_MAXLEN
185103. BLOGIC_CHECKCONDITION
185104. BLOGIC_CMD_ABORT_BY_HOST
185105. BLOGIC_CMD_CMPLT_NORMAL
185106. BLOGIC_CMD_COMPLETE_ERROR
185107. BLOGIC_CMD_COMPLETE_GOOD
185108. BLOGIC_CMD_NOTFOUND
185109. BLOGIC_CMD_PARM_REG
185110. BLOGIC_CNTRL_REG
185111. BLOGIC_DATAIN_CHECKED
185112. BLOGIC_DATAIN_REG
185113. BLOGIC_DATAOUT_CHECKED
185114. BLOGIC_DATA_OVERRUN
185115. BLOGIC_DATA_UNDERRUN
185116. BLOGIC_DEVBUSY
185117. BLOGIC_DISABLE_INT
185118. BLOGIC_ECHO_CMDDATA
185119. BLOGIC_EISA_BUS
185120. BLOGIC_ENABLE_OUTBOX_AVAIL_INT
185121. BLOGIC_ERR_LEVEL
185122. BLOGIC_EXEC_BIOS_CMD
185123. BLOGIC_EXEC_MBOX_CMD
185124. BLOGIC_EXEC_SCS_CMD
185125. BLOGIC_EXT_LUN_CCB
185126. BLOGIC_FETCH_LOCALRAM
185127. BLOGIC_FLASHPOINT
185128. BLOGIC_FLASHPOINT_ADDR_COUNT
185129. BLOGIC_FLASH_LOAD
185130. BLOGIC_GEOMETRY_REG
185131. BLOGIC_GET_BOARD_ID
185132. BLOGIC_HEADTAG
185133. BLOGIC_HW_BDR
185134. BLOGIC_HW_FAIL
185135. BLOGIC_HW_RESET
185136. BLOGIC_HW_TIMEOUT
185137. BLOGIC_INBOX_FREE
185138. BLOGIC_INFO_LEVEL
185139. BLOGIC_INITIATOR_CCB
185140. BLOGIC_INITIATOR_CCBB_RESIDUAL
185141. BLOGIC_INITIATOR_CCB_SG
185142. BLOGIC_INITIATOR_CCB_SG_RESIDUAL
185143. BLOGIC_INIT_EXT_MBOX
185144. BLOGIC_INIT_MBOX
185145. BLOGIC_INQ_CONFIG
185146. BLOGIC_INQ_DEV
185147. BLOGIC_INQ_DEV0TO7
185148. BLOGIC_INQ_DEV8TO15
185149. BLOGIC_INQ_EXTSETUP
185150. BLOGIC_INQ_FWVER_D3
185151. BLOGIC_INQ_FWVER_LETTER
185152. BLOGIC_INQ_MODELNO
185153. BLOGIC_INQ_PCI_INFO
185154. BLOGIC_INQ_SETUPINFO
185155. BLOGIC_INQ_SYNC_PERIOD
185156. BLOGIC_INT_REG
185157. BLOGIC_INVALID_BUSPHASE
185158. BLOGIC_INVALID_CCB
185159. BLOGIC_INVALID_CMD_CODE
185160. BLOGIC_INVALID_OUTBOX_CODE
185161. BLOGIC_IO_130
185162. BLOGIC_IO_134
185163. BLOGIC_IO_230
185164. BLOGIC_IO_234
185165. BLOGIC_IO_330
185166. BLOGIC_IO_334
185167. BLOGIC_IO_DISABLE
185168. BLOGIC_IO_DISABLE2
185169. BLOGIC_ISA_BUS
185170. BLOGIC_LEGACY_LUN_CCB
185171. BLOGIC_LINEBUF_SIZE
185172. BLOGIC_LINKCCB_BADLUN
185173. BLOGIC_LINK_CMD_CMPLT
185174. BLOGIC_LINK_CMD_CMPLT_FLAG
185175. BLOGIC_LOAD_AUTOSCSICODE
185176. BLOGIC_MAXDEV
185177. BLOGIC_MAX_ADAPTERS
185178. BLOGIC_MAX_AUTO_TAG_DEPTH
185179. BLOGIC_MAX_MAILBOX
185180. BLOGIC_MAX_TAG_DEPTH
185181. BLOGIC_MBOX_ABORT
185182. BLOGIC_MBOX_START
185183. BLOGIC_MCA_BUS
185184. BLOGIC_MIN_AUTO_TAG_DEPTH
185185. BLOGIC_MOD_IOADDR
185186. BLOGIC_MSGBUF_SIZE
185187. BLOGIC_MULTIMASTER
185188. BLOGIC_MULTIMASTER_ADDR_COUNT
185189. BLOGIC_NOEXPECT_BUSFREE
185190. BLOGIC_NORESPONSE_TO_ATN
185191. BLOGIC_NOTICE_LEVEL
185192. BLOGIC_NOTX
185193. BLOGIC_OP_GOOD
185194. BLOGIC_ORDEREDTAG
185195. BLOGIC_OUTBOX_FREE
185196. BLOGIC_PARITY_ERR
185197. BLOGIC_PCI_BUS
185198. BLOGIC_READ_BUSMASTER_FIFO
185199. BLOGIC_READ_INQBUF
185200. BLOGIC_READ_LOCALRAM
185201. BLOGIC_READ_SCAMDATA
185202. BLOGIC_RST_FROM_OTHERDEV
185203. BLOGIC_RSVDTAG
185204. BLOGIC_SELECT_TIMEOUT
185205. BLOGIC_SETCCB_FMT
185206. BLOGIC_SET_OPTIONS
185207. BLOGIC_SET_PREEMPT_TIME
185208. BLOGIC_SET_SELECT_TIMEOUT
185209. BLOGIC_SET_TIMEOFF_BUS
185210. BLOGIC_SET_TXRATE
185211. BLOGIC_SG_LIMIT
185212. BLOGIC_SIMPLETAG
185213. BLOGIC_STATUS_REG
185214. BLOGIC_STORE_LOCALRAM
185215. BLOGIC_STORE_TO_EEPROM
185216. BLOGIC_STRICT_RR
185217. BLOGIC_STRICT_RR_MODE
185218. BLOGIC_SZ_BUCKETS
185219. BLOGIC_TAGQUEUE_REJECT
185220. BLOGIC_TAG_DEPTH_BB
185221. BLOGIC_TEST_CMP_COMPLETE
185222. BLOGIC_TGT_CCB
185223. BLOGIC_TGT_MODE
185224. BLOGIC_UNCHECKED_TX
185225. BLOGIC_UNKNOWN_BUS
185226. BLOGIC_UNTAG_DEPTH
185227. BLOGIC_UNTAG_DEPTH_BB
185228. BLOGIC_VESA_BUS
185229. BLOGIC_WARN_LEVEL
185230. BLOGIC_WRITE_BUSMASTER_FIFO
185231. BLOGIC_WRITE_INQBUF
185232. BLOGIC_WRITE_LOCALRAM
185233. BLOGIC_WRITE_SCAMDATA
185234. BLOG_SKB_CB
185235. BLONGCFO
185236. BLONGCFOF_LENGTH
185237. BLONGCFOT_LENGTH
185238. BLOOP_FIT_TYPE
185239. BLPATH_LOOPBACK
185240. BLPF_CTL_REG
185241. BLPF_THR1_REG
185242. BLPF_THR2_REG
185243. BLSIG_LENGTH
185244. BLSIG_PARITY
185245. BLSIG_RATE
185246. BLSIG_RESERVED
185247. BLSP1_QUP1_I2C_APPS_CLK_SRC
185248. BLSP1_QUP1_SPI_APPS_CLK_SRC
185249. BLSP1_QUP2_I2C_APPS_CLK_SRC
185250. BLSP1_QUP2_SPI_APPS_CLK_SRC
185251. BLSP1_QUP3_I2C_APPS_CLK_SRC
185252. BLSP1_QUP3_SPI_APPS_CLK_SRC
185253. BLSP1_QUP4_I2C_APPS_CLK_SRC
185254. BLSP1_QUP4_SPI_APPS_CLK_SRC
185255. BLSP1_QUP5_I2C_APPS_CLK_SRC
185256. BLSP1_QUP5_SPI_APPS_CLK_SRC
185257. BLSP1_QUP6_I2C_APPS_CLK_SRC
185258. BLSP1_QUP6_SPI_APPS_CLK_SRC
185259. BLSP1_UART1_APPS_CLK_SRC
185260. BLSP1_UART2_APPS_CLK_SRC
185261. BLSP1_UART3_APPS_CLK_SRC
185262. BLSP1_UART4_APPS_CLK_SRC
185263. BLSP1_UART5_APPS_CLK_SRC
185264. BLSP1_UART6_APPS_CLK_SRC
185265. BLSP2_QUP1_I2C_APPS_CLK_SRC
185266. BLSP2_QUP1_SPI_APPS_CLK_SRC
185267. BLSP2_QUP2_I2C_APPS_CLK_SRC
185268. BLSP2_QUP2_SPI_APPS_CLK_SRC
185269. BLSP2_QUP3_I2C_APPS_CLK_SRC
185270. BLSP2_QUP3_SPI_APPS_CLK_SRC
185271. BLSP2_QUP4_I2C_APPS_CLK_SRC
185272. BLSP2_QUP4_SPI_APPS_CLK_SRC
185273. BLSP2_QUP5_I2C_APPS_CLK_SRC
185274. BLSP2_QUP5_SPI_APPS_CLK_SRC
185275. BLSP2_QUP6_I2C_APPS_CLK_SRC
185276. BLSP2_QUP6_SPI_APPS_CLK_SRC
185277. BLSP2_UART1_APPS_CLK_SRC
185278. BLSP2_UART2_APPS_CLK_SRC
185279. BLSP2_UART3_APPS_CLK_SRC
185280. BLSP2_UART4_APPS_CLK_SRC
185281. BLSP2_UART5_APPS_CLK_SRC
185282. BLSP2_UART6_APPS_CLK_SRC
185283. BLSP_UART_SIM_CLK_SRC
185284. BLSSIREADADDRESS
185285. BLSSIREADBACKDATA
185286. BLSSIREADEDGE
185287. BLSSIREADOKFLAG
185288. BLSSI_READADDRESS
185289. BLSSI_READBACK_DATA
185290. BLSSI_READEDGE
185291. BLS_TO_DPI_RDMA1_TO_DSI
185292. BLS_TO_DSI_RDMA1_TO_DPI1
185293. BLTCLIPX
185294. BLTCLIPY
185295. BLTCNTL
185296. BLTCOLOR
185297. BLTCOMMAND
185298. BLTCTL
185299. BLTDATA
185300. BLTDSTBASEADDR
185301. BLTDSTCHROMARANGE
185302. BLTDSTXY
185303. BLTIME_1024_CYCLES
185304. BLTIME_128_CYCLES
185305. BLTIME_2048_CYCLES
185306. BLTIME_256_CYCLES
185307. BLTIME_300_CYCLES
185308. BLTIME_384_CYCLES
185309. BLTIME_512_CYCLES
185310. BLTIME_64_CYCLES
185311. BLTROP
185312. BLTROP_COPY
185313. BLTROP_INVERT
185314. BLTROP_XOR
185315. BLTR_STATUS
185316. BLTSIZE
185317. BLTSRCBASEADDR
185318. BLTSRCCHROMARANGE
185319. BLTSRCXY
185320. BLTXYSTRIDES
185321. BLT_16BPP_FMT
185322. BLT_ACK
185323. BLT_ACK_BYPASS_S2S3
185324. BLT_AQ1_CTL
185325. BLT_AQ1_CTL_CFG
185326. BLT_AQ1_IP
185327. BLT_AQ1_LNA
185328. BLT_AQ1_STA
185329. BLT_BAS
185330. BLT_BOT_TO_TOP
185331. BLT_CIC
185332. BLT_CIC_ALL_GRP
185333. BLT_CPU2SCR_BITBLT
185334. BLT_CTL
185335. BLT_CTL_RESET
185336. BLT_DEI
185337. BLT_DEPTH_16_1555
185338. BLT_DEPTH_16_565
185339. BLT_DEPTH_32
185340. BLT_DEPTH_8
185341. BLT_DST_ADDR
185342. BLT_DST_HEIGHT
185343. BLT_DST_H_W
185344. BLT_DST_WIDTH
185345. BLT_FCTL
185346. BLT_FCTL_HV_SAMPLE
185347. BLT_FCTL_HV_SCALE
185348. BLT_FCTL_Y_HV_SAMPLE
185349. BLT_FCTL_Y_HV_SCALE
185350. BLT_HFC_N
185351. BLT_HFP
185352. BLT_HWS_PGA_GEN7
185353. BLT_INS
185354. BLT_INS_AQLOCK
185355. BLT_INS_CKEY
185356. BLT_INS_CLIP
185357. BLT_INS_CLUT
185358. BLT_INS_DEI
185359. BLT_INS_FLICK
185360. BLT_INS_GRAD
185361. BLT_INS_IRQ
185362. BLT_INS_IVMX
185363. BLT_INS_OVMX
185364. BLT_INS_PACE
185365. BLT_INS_PMASK
185366. BLT_INS_ROTATE
185367. BLT_INS_S1_CF
185368. BLT_INS_S1_COPY
185369. BLT_INS_S1_FILL
185370. BLT_INS_S1_MASK
185371. BLT_INS_S1_MEM
185372. BLT_INS_S1_OFF
185373. BLT_INS_S2_CF
185374. BLT_INS_S2_MASK
185375. BLT_INS_S2_MEM
185376. BLT_INS_S2_OFF
185377. BLT_INS_S3_MASK
185378. BLT_INS_S3_MEM
185379. BLT_INS_S3_OFF
185380. BLT_INS_SCALE
185381. BLT_INS_VC1R
185382. BLT_ITM0
185383. BLT_ITS
185384. BLT_ITS_AQ1_LNA
185385. BLT_IVMX0
185386. BLT_IVMX1
185387. BLT_IVMX2
185388. BLT_IVMX3
185389. BLT_LEFT_TO_RIGHT
185390. BLT_NB_H_COEF
185391. BLT_NB_V_COEF
185392. BLT_NIP
185393. BLT_OVMX0
185394. BLT_OVMX1
185395. BLT_OVMX2
185396. BLT_OVMX3
185397. BLT_PAT_ADDR
185398. BLT_PLUGS1_CHZ
185399. BLT_PLUGS1_MSZ
185400. BLT_PLUGS1_OP2
185401. BLT_PLUGS1_PGZ
185402. BLT_PLUGS2_CHZ
185403. BLT_PLUGS2_MSZ
185404. BLT_PLUGS2_OP2
185405. BLT_PLUGS2_PGZ
185406. BLT_PLUGS3_CHZ
185407. BLT_PLUGS3_MSZ
185408. BLT_PLUGS3_OP2
185409. BLT_PLUGS3_PGZ
185410. BLT_PLUGT_CHZ
185411. BLT_PLUGT_MSZ
185412. BLT_PLUGT_OP2
185413. BLT_PLUGT_PGZ
185414. BLT_RECFILL_BITBLT
185415. BLT_RIGHT_TO_LEFT
185416. BLT_RING_BASE
185417. BLT_ROP
185418. BLT_ROP_COLOR_COPY
185419. BLT_ROP_SRC_COPY
185420. BLT_RSF
185421. BLT_RZI
185422. BLT_RZI_DEFAULT
185423. BLT_S1BA
185424. BLT_S1TY
185425. BLT_S1TY_A1_SUBSET
185426. BLT_S1TY_CHROMA_EXT
185427. BLT_S1TY_RGB_EXP
185428. BLT_S1XY
185429. BLT_S2BA
185430. BLT_S2SZ
185431. BLT_S2TY
185432. BLT_S2TY_A1_SUBSET
185433. BLT_S2TY_CHROMA_EXT
185434. BLT_S2TY_RGB_EXP
185435. BLT_S2XY
185436. BLT_S3BA
185437. BLT_S3SZ
185438. BLT_S3TY
185439. BLT_S3TY_BLANK_ACC
185440. BLT_S3XY
185441. BLT_SCR2SCR_BITBLT
185442. BLT_SRC_ADDR
185443. BLT_STA1
185444. BLT_STA1_IDLE
185445. BLT_TBA
185446. BLT_TOP_TO_BOT
185447. BLT_TSZ
185448. BLT_TTY
185449. BLT_TTY_ALPHA_R
185450. BLT_TTY_BIG_END
185451. BLT_TTY_CHROMA
185452. BLT_TTY_COL_MASK
185453. BLT_TTY_COL_SHIFT
185454. BLT_TTY_CR_NOT_CB
185455. BLT_TTY_DITHER
185456. BLT_TTY_HSO
185457. BLT_TTY_MB
185458. BLT_TTY_VSO
185459. BLT_TXY
185460. BLT_VFC_N
185461. BLT_VFP
185462. BLT_WRITE_A
185463. BLT_WRITE_RGB
185464. BLT_WRITE_RGBA
185465. BLT_Y_HFC_N
185466. BLT_Y_HFP
185467. BLT_Y_RSF
185468. BLT_Y_RZI
185469. BLT_Y_VFC_N
185470. BLT_Y_VFP
185471. BLU
185472. BLUE
185473. BLUEFIELD_UHS_REG_EXT_DRIVE
185474. BLUEFIELD_UHS_REG_EXT_SAMPLE
185475. BLUETOOTH
185476. BLUETOOTH_VER_1_1
185477. BLUETOOTH_VER_1_2
185478. BLUETOOTH_VER_2_0
185479. BLUE_BALANCE_DEFAULT
185480. BLUE_GAIN_DEFAULT
185481. BLUE_IS_PULSE
185482. BLUE_LED
185483. BLUE_PULSE_LED
185484. BLUE_SHIFT
185485. BLUE_START
185486. BLUE_X_INC
185487. BLUE_Y_INC
185488. BLX
185489. BL_1
185490. BL_128K
185491. BL_128M
185492. BL_16M
185493. BL_1M
185494. BL_2
185495. BL_256K
185496. BL_256M
185497. BL_2M
185498. BL_32M
185499. BL_4M
185500. BL_512K
185501. BL_64M
185502. BL_8M
185503. BL_ALL_UNLOCKED
185504. BL_BURN_TIMEOUT
185505. BL_CFGR_VAL
185506. BL_CMD_TIMEOUT
185507. BL_CODES
185508. BL_CONFIG_CONTAINER
185509. BL_CONTAINER
185510. BL_CORE_FBBLANK
185511. BL_CORE_SUSPENDED
185512. BL_CORE_SUSPENDRESUME
185513. BL_CTL_SHFT
185514. BL_CTRL_VAL
185515. BL_DATA_OFFSET
185516. BL_DATA_STR
185517. BL_DEF_BRIGHT
185518. BL_DESC_BLK_SIZE
185519. BL_DEVICE_MOUNT
185520. BL_DEVICE_REQUEST_ERR
185521. BL_DEVICE_REQUEST_INIT
185522. BL_DEVICE_REQUEST_PROC
185523. BL_DEVICE_UMOUNT
185524. BL_ERROR_BOOTLOADING
185525. BL_ERROR_CMD_CSUM
185526. BL_ERROR_FLASH_CSUM
185527. BL_ERROR_FLASH_PROT
185528. BL_ERROR_INVALID
185529. BL_ERROR_INVALID_KEY
185530. BL_ERROR_NO_ERR_ACTIVE
185531. BL_ERROR_NO_ERR_IDLE
185532. BL_ERROR_RESERVED
185533. BL_FILE
185534. BL_HEADER
185535. BL_HEAD_OFFSET
185536. BL_IMAGE_CONTAINER
185537. BL_LOCKDOWN_INFO_CONTAINER
185538. BL_MAX_BRIGHT
185539. BL_NAME_SIZE
185540. BL_NOTIFY_POST_DISABLE
185541. BL_NOTIFY_POST_ENABLE
185542. BL_NOTIFY_PRE_DISABLE
185543. BL_NOTIFY_PRE_ENABLE
185544. BL_PAGE_STR
185545. BL_PKG_IDX
185546. BL_PROTOCOL_DESCRIPTOR_CONTAINER
185547. BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK
185548. BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT
185549. BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK
185550. BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT
185551. BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK
185552. BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT
185553. BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK
185554. BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT
185555. BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK
185556. BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT
185557. BL_PWM_CNTL__BL_PWM_EN_MASK
185558. BL_PWM_CNTL__BL_PWM_EN__SHIFT
185559. BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK
185560. BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT
185561. BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK
185562. BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT
185563. BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK
185564. BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT
185565. BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK
185566. BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT
185567. BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK
185568. BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT
185569. BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK
185570. BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT
185571. BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK
185572. BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT
185573. BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK
185574. BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT
185575. BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK
185576. BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT
185577. BL_READY
185578. BL_REG_LIST
185579. BL_SHUTDOWN_HS_GRTD
185580. BL_SHUTDOWN_HS_PROT_VER
185581. BL_SHUTDOWN_HS_RTD
185582. BL_STATUS_BUSY
185583. BL_STATUS_CSUM_VALID
185584. BL_STATUS_REV_3_2
185585. BL_STATUS_REV_6_5
185586. BL_STATUS_REV_MASK
185587. BL_STATUS_RUNNING
185588. BL_STATUS_SIZE
185589. BL_STATUS_WATCHDOG
185590. BM
185591. BM0_IRQ_STS
185592. BM1880_PINCONF
185593. BM1880_PINCONF_DAT
185594. BM1880_PINCONF_DRV
185595. BM1880_PINCONF_PULLCTRL
185596. BM1880_PINCONF_PULLDOWN
185597. BM1880_PINCONF_PULLUP
185598. BM1880_PINCONF_SCHMITT
185599. BM1880_PINCONF_SLEW
185600. BM1880_PINCTRL_GRP
185601. BM1880_PINMUX_FUNCTION
185602. BM1880_REG_MUX
185603. BM1880_RST_AHB_ROM
185604. BM1880_RST_AXI_SRAM
185605. BM1880_RST_DDR
185606. BM1880_RST_EFUSE
185607. BM1880_RST_EMMC
185608. BM1880_RST_ETH0
185609. BM1880_RST_ETH1
185610. BM1880_RST_GDMA
185611. BM1880_RST_GPIO0
185612. BM1880_RST_GPIO1
185613. BM1880_RST_GPIO2
185614. BM1880_RST_I2C0
185615. BM1880_RST_I2C1
185616. BM1880_RST_I2C2
185617. BM1880_RST_I2C3
185618. BM1880_RST_I2C4
185619. BM1880_RST_I2S0
185620. BM1880_RST_I2S1
185621. BM1880_RST_JPEG
185622. BM1880_RST_MAIN_AP
185623. BM1880_RST_MINER
185624. BM1880_RST_NAND
185625. BM1880_RST_PWM0
185626. BM1880_RST_PWM1
185627. BM1880_RST_PWM2
185628. BM1880_RST_PWM3
185629. BM1880_RST_SD
185630. BM1880_RST_SDMA
185631. BM1880_RST_SECOND_AP
185632. BM1880_RST_SPI
185633. BM1880_RST_SPIC
185634. BM1880_RST_TPU
185635. BM1880_RST_UART0_1_ACLK
185636. BM1880_RST_UART0_1_CLK
185637. BM1880_RST_UART2_3_ACLK
185638. BM1880_RST_UART2_3_CLK
185639. BM1880_RST_USB
185640. BM1880_RST_VIDEO
185641. BM1880_RST_VPP
185642. BM1880_RST_WDT
185643. BM1_IRQ_STS
185644. BM2835_MMAL_MODULE_NAME
185645. BM2835_MMAL_VERSION
185646. BM6880_REG_HUMIDITY_MSB
185647. BMA150_ACC_X_LSB_REG
185648. BMA150_ADV_INT_EN_MSK
185649. BMA150_ADV_INT_EN_POS
185650. BMA150_ADV_INT_EN_REG
185651. BMA150_ANY_MOTION_DUR_MSK
185652. BMA150_ANY_MOTION_DUR_POS
185653. BMA150_ANY_MOTION_DUR_REG
185654. BMA150_ANY_MOTION_EN_MSK
185655. BMA150_ANY_MOTION_EN_POS
185656. BMA150_ANY_MOTION_EN_REG
185657. BMA150_ANY_MOTION_THRES_REG
185658. BMA150_BANDWIDTH_MSK
185659. BMA150_BANDWIDTH_POS
185660. BMA150_BANDWIDTH_REG
185661. BMA150_BW_100HZ
185662. BMA150_BW_1500HZ
185663. BMA150_BW_190HZ
185664. BMA150_BW_25HZ
185665. BMA150_BW_375HZ
185666. BMA150_BW_50HZ
185667. BMA150_BW_750HZ
185668. BMA150_CFG_0_REG
185669. BMA150_CFG_1_REG
185670. BMA150_CFG_2_REG
185671. BMA150_CFG_3_REG
185672. BMA150_CFG_4_REG
185673. BMA150_CFG_5_REG
185674. BMA150_CHIP_ID
185675. BMA150_CHIP_ID_REG
185676. BMA150_CTRL_0_REG
185677. BMA150_CTRL_1_REG
185678. BMA150_CTRL_2_REG
185679. BMA150_CTRL_3_REG
185680. BMA150_DATA_0_REG
185681. BMA150_DATA_1_REG
185682. BMA150_DATA_2_REG
185683. BMA150_DRIVER
185684. BMA150_HIGH_G_DUR_REG
185685. BMA150_HIGH_G_EN_MSK
185686. BMA150_HIGH_G_EN_POS
185687. BMA150_HIGH_G_EN_REG
185688. BMA150_HIGH_G_HYST_MSK
185689. BMA150_HIGH_G_HYST_POS
185690. BMA150_HIGH_G_HYST_REG
185691. BMA150_HIGH_G_THRES_REG
185692. BMA150_LOW_G_DUR_REG
185693. BMA150_LOW_G_EN_MSK
185694. BMA150_LOW_G_EN_POS
185695. BMA150_LOW_G_EN_REG
185696. BMA150_LOW_G_HYST_MSK
185697. BMA150_LOW_G_HYST_POS
185698. BMA150_LOW_G_HYST_REG
185699. BMA150_LOW_G_THRES_REG
185700. BMA150_MODE_NORMAL
185701. BMA150_MODE_SLEEP
185702. BMA150_MODE_WAKE_UP
185703. BMA150_POLL_INTERVAL
185704. BMA150_POLL_MAX
185705. BMA150_POLL_MIN
185706. BMA150_RANGE_2G
185707. BMA150_RANGE_4G
185708. BMA150_RANGE_8G
185709. BMA150_RANGE_MSK
185710. BMA150_RANGE_POS
185711. BMA150_RANGE_REG
185712. BMA150_SLEEP_MSK
185713. BMA150_SLEEP_POS
185714. BMA150_SLEEP_REG
185715. BMA150_SW_RES_MSK
185716. BMA150_SW_RES_POS
185717. BMA150_SW_RES_REG
185718. BMA150_WAKE_UP_MSK
185719. BMA150_WAKE_UP_POS
185720. BMA150_WAKE_UP_REG
185721. BMA150_XYZ_DATA_SIZE
185722. BMA180
185723. BMA180_ACC_CHANNEL
185724. BMA180_ACC_X_LSB
185725. BMA180_BW
185726. BMA180_BW_TCS
185727. BMA180_CHIP_ID
185728. BMA180_CTRL_REG0
185729. BMA180_CTRL_REG3
185730. BMA180_DIS_WAKE_UP
185731. BMA180_DRV_NAME
185732. BMA180_EE_W
185733. BMA180_ID_REG_VAL
185734. BMA180_IRQ_NAME
185735. BMA180_LOW_POWER
185736. BMA180_MODE_CONFIG
185737. BMA180_NEW_DATA_INT
185738. BMA180_OFFSET_LSB1
185739. BMA180_PM_OPS
185740. BMA180_RANGE
185741. BMA180_RESET
185742. BMA180_RESET_INT
185743. BMA180_RESET_VAL
185744. BMA180_SLEEP
185745. BMA180_SMP_SKIP
185746. BMA180_TCO_Z
185747. BMA180_TEMP
185748. BMA180_TEMP_CHANNEL
185749. BMA220_ACCEL_CHANNEL
185750. BMA220_CHIP_ID
185751. BMA220_DATA_SHIFT
185752. BMA220_DEVICE_NAME
185753. BMA220_PM_OPS
185754. BMA220_RANGE_MASK
185755. BMA220_READ_MASK
185756. BMA220_REG_ACCEL_X
185757. BMA220_REG_ACCEL_Y
185758. BMA220_REG_ACCEL_Z
185759. BMA220_REG_ID
185760. BMA220_REG_RANGE
185761. BMA220_REG_SUSPEND
185762. BMA220_SCALE_AVAILABLE
185763. BMA220_SUSPEND_SLEEP
185764. BMA220_SUSPEND_WAKE
185765. BMA250
185766. BMA250_BW_MASK
185767. BMA250_BW_REG
185768. BMA250_DATA_INTEN_MASK
185769. BMA250_INT1_DATA_MASK
185770. BMA250_INT_ENABLE_REG
185771. BMA250_INT_MAP_REG
185772. BMA250_INT_RESET_MASK
185773. BMA250_INT_RESET_REG
185774. BMA250_LOWPOWER_MASK
185775. BMA250_POWER_REG
185776. BMA250_RANGE_MASK
185777. BMA250_RANGE_REG
185778. BMA250_RESET_REG
185779. BMA250_SUSPEND_MASK
185780. BMAC_ADDR0
185781. BMAC_ADDR0_ADDR0
185782. BMAC_ADDR1
185783. BMAC_ADDR1_ADDR1
185784. BMAC_ADDR2
185785. BMAC_ADDR2_ADDR2
185786. BMAC_ADDR_CMPEN
185787. BMAC_ADDR_CMPEN_EN0
185788. BMAC_ADDR_CMPEN_EN1
185789. BMAC_ADDR_CMPEN_EN10
185790. BMAC_ADDR_CMPEN_EN11
185791. BMAC_ADDR_CMPEN_EN12
185792. BMAC_ADDR_CMPEN_EN13
185793. BMAC_ADDR_CMPEN_EN14
185794. BMAC_ADDR_CMPEN_EN15
185795. BMAC_ADDR_CMPEN_EN2
185796. BMAC_ADDR_CMPEN_EN3
185797. BMAC_ADDR_CMPEN_EN4
185798. BMAC_ADDR_CMPEN_EN5
185799. BMAC_ADDR_CMPEN_EN6
185800. BMAC_ADDR_CMPEN_EN7
185801. BMAC_ADDR_CMPEN_EN8
185802. BMAC_ADDR_CMPEN_EN9
185803. BMAC_ADD_FILT0
185804. BMAC_ADD_FILT00_MASK
185805. BMAC_ADD_FILT00_MASK_VAL
185806. BMAC_ADD_FILT0_FILT0
185807. BMAC_ADD_FILT1
185808. BMAC_ADD_FILT12_MASK
185809. BMAC_ADD_FILT12_MASK_VAL
185810. BMAC_ADD_FILT1_FILT1
185811. BMAC_ADD_FILT2
185812. BMAC_ADD_FILT2_FILT2
185813. BMAC_AFILTER0
185814. BMAC_AFILTER1
185815. BMAC_AFILTER2
185816. BMAC_AFMASK
185817. BMAC_ALIMIT
185818. BMAC_ALT_ADDR0
185819. BMAC_ALT_ADDR0_ADDR0
185820. BMAC_ALT_ADDR1
185821. BMAC_ALT_ADDR1_ADDR1
185822. BMAC_ALT_ADDR2
185823. BMAC_ALT_ADDR2_ADDR2
185824. BMAC_CONTROL_RX_ENABLE
185825. BMAC_CTRL_CONFIG
185826. BMAC_CTRL_CONFIG_PASS_CTRL
185827. BMAC_CTRL_CONFIG_RX_PAUSE_EN
185828. BMAC_CTRL_CONFIG_TX_PAUSE_EN
185829. BMAC_CTRL_STATUS
185830. BMAC_CTRL_STATUS_MASK
185831. BMAC_CTRL_STATUS_NOPAUSE
185832. BMAC_CTRL_STATUS_PAUSE
185833. BMAC_CTRL_STATUS_PAUSE_RECV
185834. BMAC_CTRL_STATUS_TIME
185835. BMAC_CTRL_STATUS_TIME_SHIFT
185836. BMAC_CTRL_TYPE
185837. BMAC_DTCTR
185838. BMAC_EXCTR
185839. BMAC_FCCTR
185840. BMAC_FC_ADDR0
185841. BMAC_FC_ADDR0_ADDR0
185842. BMAC_FC_ADDR1
185843. BMAC_FC_ADDR1_ADDR1
185844. BMAC_FC_ADDR2
185845. BMAC_FC_ADDR2_ADDR2
185846. BMAC_FRCTR
185847. BMAC_GLECTR
185848. BMAC_HASH_TBL
185849. BMAC_HASH_TBL_VAL
185850. BMAC_HOST_INFO
185851. BMAC_HTABLE0
185852. BMAC_HTABLE1
185853. BMAC_HTABLE2
185854. BMAC_HTABLE3
185855. BMAC_IGAP1
185856. BMAC_IGAP2
185857. BMAC_IMASK
185858. BMAC_JSIZE
185859. BMAC_LTCTR
185860. BMAC_MACADDR0
185861. BMAC_MACADDR1
185862. BMAC_MACADDR2
185863. BMAC_MAX_FRAME
185864. BMAC_MAX_FRAME_MAX_BURST
185865. BMAC_MAX_FRAME_MAX_BURST_SHIFT
185866. BMAC_MAX_FRAME_MAX_FRAME
185867. BMAC_MAX_FRAME_MAX_FRAME_SHIFT
185868. BMAC_MIN_FRAME
185869. BMAC_MIN_FRAME_VAL
185870. BMAC_NCCTR
185871. BMAC_NUM_ALT_ADDR
185872. BMAC_NUM_HOST_INFO
185873. BMAC_PATTEMPT
185874. BMAC_PLEN
185875. BMAC_PORT2_OFF
185876. BMAC_PORT3_OFF
185877. BMAC_PPAT
185878. BMAC_PREAMBLE_SIZE
185879. BMAC_PREAMBLE_SIZE_VAL
185880. BMAC_RCRCECTR
185881. BMAC_REG_SIZE
185882. BMAC_RSEED
185883. BMAC_RXCFG
185884. BMAC_RXCVALID
185885. BMAC_RXMAX
185886. BMAC_RXMIN
185887. BMAC_RXPMAX
185888. BMAC_RXPMIN
185889. BMAC_RXSMACHINE
185890. BMAC_RXSWRESET
185891. BMAC_SEND_PAUSE
185892. BMAC_SEND_PAUSE_SEND
185893. BMAC_SEND_PAUSE_TIME
185894. BMAC_STATE_MACHINE
185895. BMAC_STATUS
185896. BMAC_STIME
185897. BMAC_TXCFG
185898. BMAC_TXDELIM
185899. BMAC_TXMAX
185900. BMAC_TXMIN
185901. BMAC_TXPMAX
185902. BMAC_TXPMIN
185903. BMAC_TXSDELIM
185904. BMAC_TXSMACHINE
185905. BMAC_TXSWRESET
185906. BMAC_UNALECTR
185907. BMAC_XIFCFG
185908. BMAC_XIF_CONFIG
185909. BMAC_XIF_CONFIG_25MHZ_CLOCK
185910. BMAC_XIF_CONFIG_GMII_MODE
185911. BMAC_XIF_CONFIG_LED_POLARITY
185912. BMAC_XIF_CONFIG_LINK_LED
185913. BMAC_XIF_CONFIG_MII_LOOPBACK
185914. BMAC_XIF_CONFIG_TX_OUTPUT_EN
185915. BMADR_UP
185916. BMAN_ERRS_TO_DISABLE
185917. BMAN_PAACE
185918. BMAN_REV10
185919. BMAN_REV20
185920. BMAN_REV21
185921. BMAN_TOKEN_MASK
185922. BMAPBLKNO
185923. BMAPPGTOLEV
185924. BMAPSZTOLEV
185925. BMAPVERSION
185926. BMAP_ATTRFORK
185927. BMAP_B
185928. BMAP_COWFORK
185929. BMAP_I
185930. BMAP_IOCTL
185931. BMAP_LEFT_CONTIG
185932. BMAP_LEFT_DELAY
185933. BMAP_LEFT_FILLING
185934. BMAP_LEFT_VALID
185935. BMAP_LOCK
185936. BMAP_LOCK_INIT
185937. BMAP_OFF
185938. BMAP_RIGHT_CONTIG
185939. BMAP_RIGHT_DELAY
185940. BMAP_RIGHT_FILLING
185941. BMAP_RIGHT_VALID
185942. BMAP_UNLOCK
185943. BMASK
185944. BMASK12BITS
185945. BMASKBYTE0
185946. BMASKBYTE1
185947. BMASKBYTE2
185948. BMASKBYTE3
185949. BMASKCCK
185950. BMASKDWORD
185951. BMASKH4BITS
185952. BMASKHWORD
185953. BMASKLWORD
185954. BMASKOFDM_D
185955. BMASKRFEINV
185956. BMASK_OPF
185957. BMAX
185958. BMBN_REG_DBG_DWORD_ENABLE_K2_E5
185959. BMBN_REG_DBG_FORCE_FRAME_K2_E5
185960. BMBN_REG_DBG_FORCE_VALID_K2_E5
185961. BMBN_REG_DBG_SELECT_K2_E5
185962. BMBN_REG_DBG_SHIFT_K2_E5
185963. BMBT_BLOCKCOUNT_BITLEN
185964. BMBT_EXNTFLAG_BITLEN
185965. BMBT_STARTBLOCK_BITLEN
185966. BMBT_STARTOFF_BITLEN
185967. BMBT_STARTOFF_MASK
185968. BMB_REG_BIG_RAM_ADDRESS
185969. BMB_REG_BIG_RAM_DATA
185970. BMB_REG_DBG_DWORD_ENABLE
185971. BMB_REG_DBG_FORCE_FRAME
185972. BMB_REG_DBG_FORCE_VALID
185973. BMB_REG_DBG_SELECT
185974. BMB_REG_DBG_SHIFT
185975. BMC
185976. BMC0_BLANKEN
185977. BMC0_CSCBEN
185978. BMC0_CSYTRUE
185979. BMC0_DUAL
185980. BMC0_HARDDIS
185981. BMC0_HSYTRUE
185982. BMC0_LOLDIS
185983. BMC0_LPENDIS
185984. BMC0_PAL
185985. BMC0_VARBEAMEN
185986. BMC0_VARCSYEN
185987. BMC0_VARHSYEN
185988. BMC0_VARVBEN
185989. BMC0_VARVSYEN
185990. BMC0_VSYTRUE
185991. BMC150_ACCEL_ANY_MOTION_BIT_SIGN
185992. BMC150_ACCEL_ANY_MOTION_BIT_X
185993. BMC150_ACCEL_ANY_MOTION_BIT_Y
185994. BMC150_ACCEL_ANY_MOTION_BIT_Z
185995. BMC150_ACCEL_ANY_MOTION_MASK
185996. BMC150_ACCEL_AXIS_TO_REG
185997. BMC150_ACCEL_CHANNEL
185998. BMC150_ACCEL_CHANNELS
185999. BMC150_ACCEL_DEF_BW
186000. BMC150_ACCEL_DEF_RANGE_16G
186001. BMC150_ACCEL_DEF_RANGE_2G
186002. BMC150_ACCEL_DEF_RANGE_4G
186003. BMC150_ACCEL_DEF_RANGE_8G
186004. BMC150_ACCEL_DEF_SLOPE_DURATION
186005. BMC150_ACCEL_DEF_SLOPE_THRESHOLD
186006. BMC150_ACCEL_DRV_NAME
186007. BMC150_ACCEL_FIFO_LENGTH
186008. BMC150_ACCEL_FIFO_MODE_BYPASS
186009. BMC150_ACCEL_FIFO_MODE_FIFO
186010. BMC150_ACCEL_FIFO_MODE_STREAM
186011. BMC150_ACCEL_INTERRUPTS
186012. BMC150_ACCEL_INT_ANY_MOTION
186013. BMC150_ACCEL_INT_DATA_READY
186014. BMC150_ACCEL_INT_EN_BIT_DATA_EN
186015. BMC150_ACCEL_INT_EN_BIT_FFULL_EN
186016. BMC150_ACCEL_INT_EN_BIT_FWM_EN
186017. BMC150_ACCEL_INT_EN_BIT_SLP_X
186018. BMC150_ACCEL_INT_EN_BIT_SLP_Y
186019. BMC150_ACCEL_INT_EN_BIT_SLP_Z
186020. BMC150_ACCEL_INT_MAP_0_BIT_SLOPE
186021. BMC150_ACCEL_INT_MAP_1_BIT_DATA
186022. BMC150_ACCEL_INT_MAP_1_BIT_FFULL
186023. BMC150_ACCEL_INT_MAP_1_BIT_FWM
186024. BMC150_ACCEL_INT_MODE_LATCH_INT
186025. BMC150_ACCEL_INT_MODE_LATCH_RESET
186026. BMC150_ACCEL_INT_MODE_NON_LATCH_INT
186027. BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL
186028. BMC150_ACCEL_INT_WATERMARK
186029. BMC150_ACCEL_IRQ_NAME
186030. BMC150_ACCEL_MAX_STARTUP_TIME_MS
186031. BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK
186032. BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT
186033. BMC150_ACCEL_PMU_MODE_MASK
186034. BMC150_ACCEL_PMU_MODE_SHIFT
186035. BMC150_ACCEL_REG_CHIP_ID
186036. BMC150_ACCEL_REG_FIFO_CONFIG0
186037. BMC150_ACCEL_REG_FIFO_CONFIG1
186038. BMC150_ACCEL_REG_FIFO_DATA
186039. BMC150_ACCEL_REG_FIFO_STATUS
186040. BMC150_ACCEL_REG_INT_5
186041. BMC150_ACCEL_REG_INT_6
186042. BMC150_ACCEL_REG_INT_EN_0
186043. BMC150_ACCEL_REG_INT_EN_1
186044. BMC150_ACCEL_REG_INT_MAP_0
186045. BMC150_ACCEL_REG_INT_MAP_1
186046. BMC150_ACCEL_REG_INT_OUT_CTRL
186047. BMC150_ACCEL_REG_INT_RST_LATCH
186048. BMC150_ACCEL_REG_INT_STATUS_2
186049. BMC150_ACCEL_REG_PMU_BW
186050. BMC150_ACCEL_REG_PMU_LPW
186051. BMC150_ACCEL_REG_PMU_RANGE
186052. BMC150_ACCEL_REG_RESET
186053. BMC150_ACCEL_REG_TEMP
186054. BMC150_ACCEL_REG_XOUT_L
186055. BMC150_ACCEL_RESET_VAL
186056. BMC150_ACCEL_SLEEP_100_MS
186057. BMC150_ACCEL_SLEEP_10_MS
186058. BMC150_ACCEL_SLEEP_1_MS
186059. BMC150_ACCEL_SLEEP_1_SEC
186060. BMC150_ACCEL_SLEEP_25_MS
186061. BMC150_ACCEL_SLEEP_2_MS
186062. BMC150_ACCEL_SLEEP_4_MS
186063. BMC150_ACCEL_SLEEP_500_MICRO
186064. BMC150_ACCEL_SLEEP_500_MS
186065. BMC150_ACCEL_SLEEP_50_MS
186066. BMC150_ACCEL_SLEEP_6_MS
186067. BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND
186068. BMC150_ACCEL_SLEEP_MODE_LPM
186069. BMC150_ACCEL_SLEEP_MODE_NORMAL
186070. BMC150_ACCEL_SLEEP_MODE_SUSPEND
186071. BMC150_ACCEL_SLOPE_DUR_MASK
186072. BMC150_ACCEL_SLOPE_THRES_MASK
186073. BMC150_ACCEL_TEMP_CENTER_VAL
186074. BMC150_ACCEL_TRIGGERS
186075. BMC150_ACCEL_TRIGGER_ANY_MOTION
186076. BMC150_ACCEL_TRIGGER_DATA_READY
186077. BMC150_AUTO_SUSPEND_DELAY_MS
186078. BMC150_MAGN_AUTO_SUSPEND_DELAY_MS
186079. BMC150_MAGN_CHANNEL
186080. BMC150_MAGN_CHIP_ID_VAL
186081. BMC150_MAGN_DEFAULT_PRESET
186082. BMC150_MAGN_DRV_NAME
186083. BMC150_MAGN_IRQ_NAME
186084. BMC150_MAGN_MASK_DRDY_DR_POLARITY
186085. BMC150_MAGN_MASK_DRDY_EN
186086. BMC150_MAGN_MASK_DRDY_INT3
186087. BMC150_MAGN_MASK_DRDY_INT3_POLARITY
186088. BMC150_MAGN_MASK_DRDY_LATCHING
186089. BMC150_MAGN_MASK_DRDY_X_EN
186090. BMC150_MAGN_MASK_DRDY_Y_EN
186091. BMC150_MAGN_MASK_DRDY_Z_EN
186092. BMC150_MAGN_MASK_ODR
186093. BMC150_MAGN_MASK_OPMODE
186094. BMC150_MAGN_MASK_POWER_CTL
186095. BMC150_MAGN_MODE_FORCED
186096. BMC150_MAGN_MODE_NORMAL
186097. BMC150_MAGN_MODE_SLEEP
186098. BMC150_MAGN_POWER_MODE_NORMAL
186099. BMC150_MAGN_POWER_MODE_SLEEP
186100. BMC150_MAGN_POWER_MODE_SUSPEND
186101. BMC150_MAGN_REGVAL_TO_REPXY
186102. BMC150_MAGN_REGVAL_TO_REPZ
186103. BMC150_MAGN_REG_CHIP_ID
186104. BMC150_MAGN_REG_HIGH_THRESH
186105. BMC150_MAGN_REG_INT
186106. BMC150_MAGN_REG_INT_DRDY
186107. BMC150_MAGN_REG_INT_STATUS
186108. BMC150_MAGN_REG_LOW_THRESH
186109. BMC150_MAGN_REG_OPMODE_ODR
186110. BMC150_MAGN_REG_POWER
186111. BMC150_MAGN_REG_REP_DATAMASK
186112. BMC150_MAGN_REG_REP_XY
186113. BMC150_MAGN_REG_REP_Z
186114. BMC150_MAGN_REG_RHALL_L
186115. BMC150_MAGN_REG_RHALL_M
186116. BMC150_MAGN_REG_TRIM_END
186117. BMC150_MAGN_REG_TRIM_START
186118. BMC150_MAGN_REG_X_L
186119. BMC150_MAGN_REG_X_M
186120. BMC150_MAGN_REG_Y_L
186121. BMC150_MAGN_REG_Y_M
186122. BMC150_MAGN_REG_Z_L
186123. BMC150_MAGN_REG_Z_M
186124. BMC150_MAGN_REPXY_TO_REGVAL
186125. BMC150_MAGN_REPZ_TO_REGVAL
186126. BMC150_MAGN_SHIFT_DRDY_EN
186127. BMC150_MAGN_SHIFT_ODR
186128. BMC150_MAGN_SHIFT_OPMODE
186129. BMC150_MAGN_SHIFT_RHALL_L
186130. BMC150_MAGN_SHIFT_XY_L
186131. BMC150_MAGN_SHIFT_Z_L
186132. BMC150_MAGN_START_UP_TIME_MS
186133. BMC150_MAGN_XY_OVERFLOW_VAL
186134. BMC150_MAGN_Z_OVERFLOW_VAL
186135. BMC2HOST
186136. BMCIP_MASK
186137. BMCIP_V4
186138. BMCIP_V6
186139. BMCMD_CONSERVATION_OFF
186140. BMCMD_CONSERVATION_ON
186141. BMCNT_UP
186142. BMCR
186143. BMCRSR
186144. BMCR_ANENABLE
186145. BMCR_ANRESTART
186146. BMCR_CTST
186147. BMCR_FULLDPLX
186148. BMCR_ISOLATE
186149. BMCR_LOOPBACK
186150. BMCR_PDOWN
186151. BMCR_RESET
186152. BMCR_RESV
186153. BMCR_SPD2
186154. BMCR_SPEED10
186155. BMCR_SPEED100
186156. BMCR_SPEED1000
186157. BMCTRL_DEFAULT
186158. BMC_BIT_LED_HOTSWAP
186159. BMC_BIT_LED_STATUS
186160. BMC_BIT_LED_USER1
186161. BMC_BIT_LED_USER2
186162. BMC_CMD_LED_GET_SET
186163. BMC_CMD_REV_MAIN
186164. BMC_CMD_REV_MAJOR
186165. BMC_CMD_REV_MINOR
186166. BMC_CMD_RST_RSN
186167. BMC_CMD_WDT_EXIT_PROD
186168. BMC_CMD_WDT_PROD_STAT
186169. BMC_CMD_WD_OFF
186170. BMC_CMD_WD_ON
186171. BMC_CMD_WD_STATE
186172. BMC_CMD_WD_TIME
186173. BMC_CMD_WD_TRIG
186174. BMC_FILT_BROADCAST
186175. BMC_FILT_BROADCAST_ARP
186176. BMC_FILT_BROADCAST_DHCP_CLIENT
186177. BMC_FILT_BROADCAST_DHCP_SERVER
186178. BMC_FILT_BROADCAST_NET_BIOS
186179. BMC_FILT_MULTICAST
186180. BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER
186181. BMC_FILT_MULTICAST_IPV6_RA
186182. BMC_FILT_MULTICAST_IPV6_RAS
186183. BMC_QUEUE_INX
186184. BMC_VOLT_COUNT
186185. BMC_WD_OFF_VAL
186186. BMC_WD_TIMEOUT_MAX
186187. BMC_WD_TIMEOUT_MIN
186188. BMDE
186189. BMDMA_CMD
186190. BMDMA_PRD_HIGH
186191. BMDMA_PRD_LOW
186192. BMDMA_STATUS
186193. BME1000_E_PHY_ID
186194. BME1000_E_PHY_ID_R2
186195. BME1000_PSCR_ENABLE_DOWNSHIFT
186196. BME280_CHIP_ID
186197. BME680_ADC_GAS_RES_SHIFT
186198. BME680_AMB_TEMP
186199. BME680_BIT_H1_DATA_MASK
186200. BME680_CHIP_ID_VAL
186201. BME680_CMD_SOFTRESET
186202. BME680_FILTER_COEFF_VAL
186203. BME680_FILTER_MASK
186204. BME680_GAS_MEAS_BIT
186205. BME680_GAS_RANGE_MASK
186206. BME680_GAS_STAB_BIT
186207. BME680_GH1_REG
186208. BME680_GH2_LSB_REG
186209. BME680_GH3_REG
186210. BME680_H1_LSB_REG
186211. BME680_H1_MSB_REG
186212. BME680_H2_LSB_REG
186213. BME680_H2_MSB_REG
186214. BME680_H3_REG
186215. BME680_H4_REG
186216. BME680_H5_REG
186217. BME680_H6_REG
186218. BME680_H7_REG
186219. BME680_HUM_REG_SHIFT_VAL
186220. BME680_H_
186221. BME680_MAX_OVERFLOW_VAL
186222. BME680_MEAS_SKIPPED
186223. BME680_MODE_FORCED
186224. BME680_MODE_MASK
186225. BME680_MODE_SLEEP
186226. BME680_NB_CONV_MASK
186227. BME680_OSRS_HUMIDITY_MASK
186228. BME680_OSRS_PRESS_MASK
186229. BME680_OSRS_TEMP_MASK
186230. BME680_P10_REG
186231. BME680_P1_LSB_REG
186232. BME680_P2_LSB_REG
186233. BME680_P3_REG
186234. BME680_P4_LSB_REG
186235. BME680_P5_LSB_REG
186236. BME680_P6_REG
186237. BME680_P7_REG
186238. BME680_P8_LSB_REG
186239. BME680_P9_LSB_REG
186240. BME680_REG_CHIP_ID
186241. BME680_REG_CONFIG
186242. BME680_REG_CTRL_GAS_1
186243. BME680_REG_CTRL_HUMIDITY
186244. BME680_REG_CTRL_MEAS
186245. BME680_REG_GAS_MSB
186246. BME680_REG_GAS_R_LSB
186247. BME680_REG_GAS_WAIT_0
186248. BME680_REG_MEAS_STAT_0
186249. BME680_REG_PRESS_MSB
186250. BME680_REG_RANGE_SW_ERR
186251. BME680_REG_RES_HEAT_0
186252. BME680_REG_RES_HEAT_RANGE
186253. BME680_REG_RES_HEAT_VAL
186254. BME680_REG_SOFT_RESET
186255. BME680_REG_STATUS
186256. BME680_REG_TEMP_MSB
186257. BME680_RHRANGE_MASK
186258. BME680_RSERROR_MASK
186259. BME680_RUN_GAS_MASK
186260. BME680_SPI_MEM_PAGE_1_VAL
186261. BME680_SPI_MEM_PAGE_BIT
186262. BME680_T1_LSB_REG
186263. BME680_T2_LSB_REG
186264. BME680_T3_REG
186265. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK
186266. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__MASK
186267. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT
186268. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK
186269. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__MASK
186270. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT
186271. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK
186272. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__MASK
186273. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT
186274. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK
186275. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__MASK
186276. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT
186277. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK
186278. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__MASK
186279. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT
186280. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK
186281. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__MASK
186282. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT
186283. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK
186284. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__MASK
186285. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT
186286. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK
186287. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__MASK
186288. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT
186289. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0_MASK
186290. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0__SHIFT
186291. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1_MASK
186292. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1__SHIFT
186293. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2_MASK
186294. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2__SHIFT
186295. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3_MASK
186296. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3__SHIFT
186297. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4_MASK
186298. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4__SHIFT
186299. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5_MASK
186300. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5__SHIFT
186301. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6_MASK
186302. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6__SHIFT
186303. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7_MASK
186304. BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7__SHIFT
186305. BME_LOCKED
186306. BME_NO_WRITES
186307. BME_PRIORITY
186308. BMF_WEIGHT_SUM
186309. BMF_WIN_L
186310. BMG160_ANY_DUR_MASK
186311. BMG160_ANY_DUR_SHIFT
186312. BMG160_ANY_MOTION_BIT_X
186313. BMG160_ANY_MOTION_BIT_Y
186314. BMG160_ANY_MOTION_BIT_Z
186315. BMG160_ANY_MOTION_MASK
186316. BMG160_AUTO_SUSPEND_DELAY_MS
186317. BMG160_AXIS_TO_REG
186318. BMG160_CHANNEL
186319. BMG160_CHIP_ID_VAL
186320. BMG160_DATA_ENABLE_INT
186321. BMG160_DEF_BW
186322. BMG160_GYRO_REG_RESET
186323. BMG160_GYRO_RESET_VAL
186324. BMG160_H_
186325. BMG160_INT1_BIT_OD
186326. BMG160_INT_MAP_0_BIT_ANY
186327. BMG160_INT_MAP_1_BIT_NEW_DATA
186328. BMG160_INT_MODE_LATCH_INT
186329. BMG160_INT_MODE_LATCH_RESET
186330. BMG160_INT_MODE_NON_LATCH_INT
186331. BMG160_INT_MOTION_X
186332. BMG160_INT_MOTION_Y
186333. BMG160_INT_MOTION_Z
186334. BMG160_IRQ_NAME
186335. BMG160_MAX_STARTUP_TIME_MS
186336. BMG160_MODE_DEEP_SUSPEND
186337. BMG160_MODE_NORMAL
186338. BMG160_MODE_SUSPEND
186339. BMG160_NO_FILTER
186340. BMG160_RANGE_1000DPS
186341. BMG160_RANGE_125DPS
186342. BMG160_RANGE_2000DPS
186343. BMG160_RANGE_250DPS
186344. BMG160_RANGE_500DPS
186345. BMG160_REG_CHIP_ID
186346. BMG160_REG_INT_EN_0
186347. BMG160_REG_INT_EN_1
186348. BMG160_REG_INT_MAP_0
186349. BMG160_REG_INT_MAP_1
186350. BMG160_REG_INT_RST_LATCH
186351. BMG160_REG_INT_STATUS_2
186352. BMG160_REG_MOTION_INTR
186353. BMG160_REG_PMU_BW
186354. BMG160_REG_PMU_BW_RES
186355. BMG160_REG_PMU_LPW
186356. BMG160_REG_RANGE
186357. BMG160_REG_SLOPE_THRES
186358. BMG160_REG_TEMP
186359. BMG160_REG_XOUT_L
186360. BMG160_SLOPE_THRES_MASK
186361. BMG160_TEMP_CENTER_VAL
186362. BMGGAIN
186363. BMI160_ACCEL
186364. BMI160_ACCEL_CONFIG_BWP_MASK
186365. BMI160_ACCEL_CONFIG_ODR_MASK
186366. BMI160_ACCEL_PMU_MIN_USLEEP
186367. BMI160_ACCEL_RANGE_16G
186368. BMI160_ACCEL_RANGE_2G
186369. BMI160_ACCEL_RANGE_4G
186370. BMI160_ACCEL_RANGE_8G
186371. BMI160_ACTIVE_HIGH
186372. BMI160_CHANNEL
186373. BMI160_CHIP_ID_VAL
186374. BMI160_CMD_ACCEL_PM_LOW_POWER
186375. BMI160_CMD_ACCEL_PM_NORMAL
186376. BMI160_CMD_ACCEL_PM_SUSPEND
186377. BMI160_CMD_GYRO_PM_FAST_STARTUP
186378. BMI160_CMD_GYRO_PM_NORMAL
186379. BMI160_CMD_GYRO_PM_SUSPEND
186380. BMI160_CMD_SOFTRESET
186381. BMI160_DRDY_INT_EN
186382. BMI160_EDGE_TRIGGERED
186383. BMI160_EXT_MAGN
186384. BMI160_GYRO
186385. BMI160_GYRO_CONFIG_BWP_MASK
186386. BMI160_GYRO_CONFIG_ODR_MASK
186387. BMI160_GYRO_PMU_MIN_USLEEP
186388. BMI160_GYRO_RANGE_1000DPS
186389. BMI160_GYRO_RANGE_125DPS
186390. BMI160_GYRO_RANGE_2000DPS
186391. BMI160_GYRO_RANGE_250DPS
186392. BMI160_GYRO_RANGE_500DPS
186393. BMI160_H_
186394. BMI160_INT1_LATCH_MASK
186395. BMI160_INT1_MAP_DRDY_EN
186396. BMI160_INT1_OUT_CTRL_SHIFT
186397. BMI160_INT2_LATCH_MASK
186398. BMI160_INT2_MAP_DRDY_EN
186399. BMI160_INT2_OUT_CTRL_SHIFT
186400. BMI160_INT_OUT_CTRL_MASK
186401. BMI160_NORMAL_WRITE_USLEEP
186402. BMI160_NUM_SENSORS
186403. BMI160_OPEN_DRAIN
186404. BMI160_OUTPUT_EN
186405. BMI160_PIN_INT1
186406. BMI160_PIN_INT2
186407. BMI160_REG_ACCEL_CONFIG
186408. BMI160_REG_ACCEL_RANGE
186409. BMI160_REG_CHIP_ID
186410. BMI160_REG_CMD
186411. BMI160_REG_DATA_ACCEL_XOUT_L
186412. BMI160_REG_DATA_GYRO_XOUT_L
186413. BMI160_REG_DATA_MAGN_XOUT_L
186414. BMI160_REG_DUMMY
186415. BMI160_REG_GYRO_CONFIG
186416. BMI160_REG_GYRO_RANGE
186417. BMI160_REG_INT_EN
186418. BMI160_REG_INT_LATCH
186419. BMI160_REG_INT_MAP
186420. BMI160_REG_INT_OUT_CTRL
186421. BMI160_REG_PMU_STATUS
186422. BMI160_SCAN_ACCEL_X
186423. BMI160_SCAN_ACCEL_Y
186424. BMI160_SCAN_ACCEL_Z
186425. BMI160_SCAN_EXT_MAGN_X
186426. BMI160_SCAN_EXT_MAGN_Y
186427. BMI160_SCAN_EXT_MAGN_Z
186428. BMI160_SCAN_GYRO_X
186429. BMI160_SCAN_GYRO_Y
186430. BMI160_SCAN_GYRO_Z
186431. BMI160_SCAN_RHALL
186432. BMI160_SCAN_TIMESTAMP
186433. BMI160_SOFTRESET_USLEEP
186434. BMI160_SUSPENDED_WRITE_USLEEP
186435. BMIC_CACHE_FLUSH
186436. BMIC_CSMI_PASSTHRU
186437. BMIC_DEVICE_TYPE_CONTROLLER
186438. BMIC_DEVICE_TYPE_ENCLOSURE
186439. BMIC_FLASH_FIRMWARE
186440. BMIC_FLUSH_CACHE
186441. BMIC_IDENTIFY_CONTROLLER
186442. BMIC_IDENTIFY_PHYSICAL_DEVICE
186443. BMIC_IN
186444. BMIC_LAST_FAILURE_ABORTED_COMMAND
186445. BMIC_LAST_FAILURE_AUTOSENSE_FAILED
186446. BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED
186447. BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR
186448. BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE
186449. BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG
186450. BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG
186451. BMIC_LAST_FAILURE_ERROR_ERASING_RIS
186452. BMIC_LAST_FAILURE_ERROR_SAVING_RIS
186453. BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND
186454. BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY
186455. BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED
186456. BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY
186457. BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED
186458. BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED
186459. BMIC_LAST_FAILURE_HARDWARE_ERROR
186460. BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED
186461. BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED
186462. BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED
186463. BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED
186464. BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED
186465. BMIC_LAST_FAILURE_INQUIRY_FAILED
186466. BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE
186467. BMIC_LAST_FAILURE_KC_VOLUME_FAILED
186468. BMIC_LAST_FAILURE_MARK_BAD_FAILED
186469. BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP
186470. BMIC_LAST_FAILURE_MEDIUM_ERROR_1
186471. BMIC_LAST_FAILURE_MEDIUM_ERROR_2
186472. BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS
186473. BMIC_LAST_FAILURE_NON_DISK_DEVICE
186474. BMIC_LAST_FAILURE_NOT_READY
186475. BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE
186476. BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX
186477. BMIC_LAST_FAILURE_OFFLINE_ERASE
186478. BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE
186479. BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL
186480. BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE
186481. BMIC_LAST_FAILURE_PHY_RESET_FAILED
186482. BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED
186483. BMIC_LAST_FAILURE_READ_CAPACITY_FAILED
186484. BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR
186485. BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG
186486. BMIC_LAST_FAILURE_SMART_ERROR_REPORTED
186487. BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER
186488. BMIC_LAST_FAILURE_TIMEOUT
186489. BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG
186490. BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG
186491. BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT
186492. BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP
186493. BMIC_LAST_FAILURE_WRITE_PROTECTED
186494. BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED
186495. BMIC_LAST_FAILURE_WRONG_REPLACE
186496. BMIC_OUT
186497. BMIC_PHYS_DRIVE_AUTHENTICATED
186498. BMIC_PHYS_DRIVE_SSD_WEAROUT
186499. BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE
186500. BMIC_READ
186501. BMIC_SENSE_CONTROLLER_PARAMETERS
186502. BMIC_SENSE_DIAG_OPTIONS
186503. BMIC_SENSE_STORAGE_BOX_PARAMS
186504. BMIC_SENSE_SUBSYSTEM_INFORMATION
186505. BMIC_SET_DIAG_OPTIONS
186506. BMIC_SMART_CARRIER_AUTHENTICATED
186507. BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED
186508. BMIC_WRITE
186509. BMIC_WRITE_HOST_WELLNESS
186510. BMIDECR0
186511. BMIDECR1
186512. BMIDECSR
186513. BMIDESR0
186514. BMINIDX_TH
186515. BMIPS
186516. BMIPS5000
186517. BMIPS5200
186518. BMIPS5_CLK_DIV_MASK
186519. BMIPS5_CLK_DIV_SET_SHIFT
186520. BMIPS5_CLK_DIV_SHIFT
186521. BMIPS_CPUFREQ_NAME
186522. BMIPS_CPUFREQ_PREFIX
186523. BMIPS_GET_CBR
186524. BMIPS_L2_CONFIG
186525. BMIPS_LMB_CONTROL
186526. BMIPS_NMI_RESET_VEC
186527. BMIPS_PERF_CONTROL_0
186528. BMIPS_PERF_CONTROL_1
186529. BMIPS_PERF_COUNTER_0
186530. BMIPS_PERF_COUNTER_1
186531. BMIPS_PERF_COUNTER_2
186532. BMIPS_PERF_COUNTER_3
186533. BMIPS_PERF_GLOBAL_CONTROL
186534. BMIPS_RAC_ADDRESS_RANGE
186535. BMIPS_RAC_CONFIG
186536. BMIPS_RAC_CONFIG_1
186537. BMIPS_RELO_VECTOR_CONTROL_0
186538. BMIPS_RELO_VECTOR_CONTROL_1
186539. BMIPS_SYSTEM_BASE
186540. BMIPS_WARM_RESTART_VEC
186541. BMI_BIST_REG
186542. BMI_CE_NUM_TO_HOST
186543. BMI_CE_NUM_TO_TARG
186544. BMI_CFG1_FIFO_SIZE_SHIFT
186545. BMI_CFG2_DMAS_MASK
186546. BMI_CFG2_DMAS_SHIFT
186547. BMI_CFG2_TASKS_MASK
186548. BMI_CFG2_TASKS_SHIFT
186549. BMI_CMD_ATTR_COLOR_SHIFT
186550. BMI_CMD_ATTR_ORDER
186551. BMI_CMD_ATTR_SYNC
186552. BMI_CMD_MR_DEAS
186553. BMI_CMD_MR_LEAC
186554. BMI_CMD_MR_MA
186555. BMI_CMD_MR_SLEAC
186556. BMI_CMD_RX_MR_DEF
186557. BMI_CMD_TX_MR_DEF
186558. BMI_COMMUNICATION_TIMEOUT
186559. BMI_COMMUNICATION_TIMEOUT_HZ
186560. BMI_CTL
186561. BMI_DEQUEUE_PIPELINE_DEPTH
186562. BMI_DMA_ATTR_SWP_SHIFT
186563. BMI_DMA_ATTR_WRITE_OPTIMIZE
186564. BMI_DONE
186565. BMI_EBD_EN
186566. BMI_ERR_INTR_EN_DISPATCH_RAM_ECC
186567. BMI_ERR_INTR_EN_LIST_RAM_ECC
186568. BMI_ERR_INTR_EN_STATISTICS_RAM_ECC
186569. BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC
186570. BMI_EXECUTE
186571. BMI_EXTRA_FIFO_SIZE_MASK
186572. BMI_EXTRA_FIFO_SIZE_SHIFT
186573. BMI_EXTRA_NUM_OF_DMAS_SHIFT
186574. BMI_EXTRA_NUM_OF_TASKS_SHIFT
186575. BMI_EXT_BUF_MARG_END_MASK
186576. BMI_EXT_BUF_MARG_START_MASK
186577. BMI_EXT_BUF_MARG_START_SHIFT
186578. BMI_EXT_BUF_POOL_BACKUP
186579. BMI_EXT_BUF_POOL_EN_COUNTER
186580. BMI_EXT_BUF_POOL_ID_MASK
186581. BMI_EXT_BUF_POOL_ID_SHIFT
186582. BMI_EXT_BUF_POOL_VALID
186583. BMI_FIFO_ALIGN
186584. BMI_FIFO_PIPELINE_DEPTH_MASK
186585. BMI_FIFO_PIPELINE_DEPTH_SHIFT
186586. BMI_FIFO_SIZE_MASK
186587. BMI_FIFO_THRESHOLD
186588. BMI_FRAME_END_CS_IGNORE_MASK
186589. BMI_FRAME_END_CS_IGNORE_SHIFT
186590. BMI_GET_TARGET_ID
186591. BMI_GET_TARGET_INFO
186592. BMI_H
186593. BMI_IC_FROM_INT_MASK
186594. BMI_IC_FROM_INT_SHIFT
186595. BMI_IC_SIZE_MASK
186596. BMI_IC_TO_EXT_MASK
186597. BMI_IC_TO_EXT_SHIFT
186598. BMI_INIT_START
186599. BMI_INT
186600. BMI_INT_BUF_MARG_MASK
186601. BMI_INT_BUF_MARG_SHIFT
186602. BMI_INT_ENA_W1S
186603. BMI_LZ_DATA
186604. BMI_LZ_STREAM_START
186605. BMI_MAX_CMDBUF_SIZE
186606. BMI_MAX_DATA_SIZE
186607. BMI_NEXT_ENG_FD_BITS_SHIFT
186608. BMI_NO_COMMAND
186609. BMI_NPS_PKT_CNT
186610. BMI_NUM_OF_DMAS_MASK
186611. BMI_NUM_OF_DMAS_SHIFT
186612. BMI_NUM_OF_EXTRA_DMAS_MASK
186613. BMI_NUM_OF_EXTRA_TASKS_MASK
186614. BMI_NUM_OF_TASKS_MASK
186615. BMI_NUM_OF_TASKS_SHIFT
186616. BMI_NVRAM_PROCESS
186617. BMI_NVRAM_SEG_NAME_SZ
186618. BMI_OFFSET
186619. BMI_PARAM_FLASH_SECTION_ALL
186620. BMI_PARAM_GET_EEPROM_BOARD_ID
186621. BMI_PARAM_GET_EXT_BOARD_ID
186622. BMI_PARAM_GET_FLASH_BOARD_ID
186623. BMI_POOL_DEP_NUM_OF_POOLS_SHIFT
186624. BMI_PORT_CFG_EN
186625. BMI_PORT_REGS_OFFSET
186626. BMI_PORT_STATUS_BSY
186627. BMI_PRIORITY_ELEVATION_LEVEL
186628. BMI_READ_MEMORY
186629. BMI_READ_SOC_REGISTER
186630. BMI_READ_SOC_WORD
186631. BMI_ROMPATCH_ACTIVATE
186632. BMI_ROMPATCH_DEACTIVATE
186633. BMI_ROMPATCH_INSTALL
186634. BMI_ROMPATCH_UNINSTALL
186635. BMI_RX_FIFO_PRI_ELEVATION_SHIFT
186636. BMI_RX_FIFO_THRESHOLD_ETHE
186637. BMI_RX_FRAME_END_CUT_MASK
186638. BMI_RX_FRAME_END_CUT_SHIFT
186639. BMI_SET_APP_START
186640. BMI_SGMTFILE_BDDATA
186641. BMI_SGMTFILE_BEGINADDR
186642. BMI_SGMTFILE_DONE
186643. BMI_SGMTFILE_EXEC
186644. BMI_SGMTFILE_FLAG_COMPRESS
186645. BMI_SGMTFILE_MAGIC_NUM
186646. BMI_TX_FIFO_MIN_FILL_SHIFT
186647. BMI_WRITE_MEMORY
186648. BMI_WRITE_SOC_REGISTER
186649. BMI_WRITE_SOC_WORD
186650. BMODE_LAST_ADDR_OFFS
186651. BMODE_RELOCATE
186652. BMOISE_PWDB
186653. BMO_BIST_REG
186654. BMO_CTL2
186655. BMO_NPS_SLC_PKT_CNT
186656. BMP180_CHIP_ID
186657. BMP180_MEAS_PRESS_1X
186658. BMP180_MEAS_PRESS_2X
186659. BMP180_MEAS_PRESS_4X
186660. BMP180_MEAS_PRESS_8X
186661. BMP180_MEAS_PRESS_X
186662. BMP180_MEAS_SCO
186663. BMP180_MEAS_TEMP
186664. BMP180_REG_CALIB_COUNT
186665. BMP180_REG_CALIB_START
186666. BMP180_REG_OUT_LSB
186667. BMP180_REG_OUT_MSB
186668. BMP180_REG_OUT_XLSB
186669. BMP280_CHIP_ID
186670. BMP280_COMP_PRESS_REG_COUNT
186671. BMP280_COMP_TEMP_REG_COUNT
186672. BMP280_FILTER_16X
186673. BMP280_FILTER_2X
186674. BMP280_FILTER_4X
186675. BMP280_FILTER_8X
186676. BMP280_FILTER_MASK
186677. BMP280_FILTER_OFF
186678. BMP280_HUMIDITY_SKIPPED
186679. BMP280_MODE_FORCED
186680. BMP280_MODE_MASK
186681. BMP280_MODE_NORMAL
186682. BMP280_MODE_SLEEP
186683. BMP280_OSRS_HUMIDITIY_X
186684. BMP280_OSRS_HUMIDITY_16X
186685. BMP280_OSRS_HUMIDITY_1X
186686. BMP280_OSRS_HUMIDITY_2X
186687. BMP280_OSRS_HUMIDITY_4X
186688. BMP280_OSRS_HUMIDITY_8X
186689. BMP280_OSRS_HUMIDITY_MASK
186690. BMP280_OSRS_HUMIDITY_SKIP
186691. BMP280_OSRS_PRESS_16X
186692. BMP280_OSRS_PRESS_1X
186693. BMP280_OSRS_PRESS_2X
186694. BMP280_OSRS_PRESS_4X
186695. BMP280_OSRS_PRESS_8X
186696. BMP280_OSRS_PRESS_MASK
186697. BMP280_OSRS_PRESS_SKIP
186698. BMP280_OSRS_PRESS_X
186699. BMP280_OSRS_TEMP_16X
186700. BMP280_OSRS_TEMP_1X
186701. BMP280_OSRS_TEMP_2X
186702. BMP280_OSRS_TEMP_4X
186703. BMP280_OSRS_TEMP_8X
186704. BMP280_OSRS_TEMP_MASK
186705. BMP280_OSRS_TEMP_SKIP
186706. BMP280_OSRS_TEMP_X
186707. BMP280_PRESS_SKIPPED
186708. BMP280_REG_COMP_H1
186709. BMP280_REG_COMP_H2
186710. BMP280_REG_COMP_H3
186711. BMP280_REG_COMP_H4
186712. BMP280_REG_COMP_H5
186713. BMP280_REG_COMP_H6
186714. BMP280_REG_COMP_PRESS_START
186715. BMP280_REG_COMP_TEMP_START
186716. BMP280_REG_CONFIG
186717. BMP280_REG_CTRL_HUMIDITY
186718. BMP280_REG_CTRL_MEAS
186719. BMP280_REG_HUMIDITY_LSB
186720. BMP280_REG_HUMIDITY_MSB
186721. BMP280_REG_ID
186722. BMP280_REG_PRESS_LSB
186723. BMP280_REG_PRESS_MSB
186724. BMP280_REG_PRESS_XLSB
186725. BMP280_REG_RESET
186726. BMP280_REG_STATUS
186727. BMP280_REG_TEMP_LSB
186728. BMP280_REG_TEMP_MSB
186729. BMP280_REG_TEMP_XLSB
186730. BMP280_SOFT_RESET_VAL
186731. BMP280_TEMP_SKIPPED
186732. BMPLEN
186733. BMPR12
186734. BMPR13
186735. BMPSTR
186736. BMP_LOADED
186737. BMP_LOADING
186738. BMP_NONE
186739. BMRCMODE
186740. BMREQ_NEGATE_TIMING_SEL
186741. BMR_BAR
186742. BMR_BIG_ENDIAN
186743. BMR_BLE
186744. BMR_CAL
186745. BMR_DAS
186746. BMR_DBO
186747. BMR_DSL
186748. BMR_GBL
186749. BMR_OFFSET
186750. BMR_PBL
186751. BMR_RML
186752. BMR_SWR
186753. BMR_TAP
186754. BMSR
186755. BMSR_100BASE4
186756. BMSR_100FULL
186757. BMSR_100FULL2
186758. BMSR_100HALF
186759. BMSR_100HALF2
186760. BMSR_10FULL
186761. BMSR_10HALF
186762. BMSR_ANCOMP
186763. BMSR_ANEGCAPABLE
186764. BMSR_ANEGCOMPLETE
186765. BMSR_ERCAP
186766. BMSR_ESTATEN
186767. BMSR_JCD
186768. BMSR_LSTATUS
186769. BMSR_MEDIA
186770. BMSR_RESV
186771. BMSR_RFAULT
186772. BMSTOP_CHANGE2_NONDATA_PHASE
186773. BMU_BBC
186774. BMU_CHECK
186775. BMU_CLR_IRQ_CHK
186776. BMU_CLR_IRQ_PAR
186777. BMU_CLR_IRQ_TCP
186778. BMU_CLR_RESET
186779. BMU_DEV_0
186780. BMU_DIS_RX_CHKSUM
186781. BMU_DIS_RX_RSS_HASH
186782. BMU_ENA_RX_CHKSUM
186783. BMU_ENA_RX_RSS_HASH
186784. BMU_EN_IRQ_EOB
186785. BMU_EN_IRQ_EOF
186786. BMU_EOF
186787. BMU_ERROR_GENERIC_RECOVERY
186788. BMU_FIFO_ENA
186789. BMU_FIFO_OP_OFF
186790. BMU_FIFO_OP_ON
186791. BMU_FIFO_RST
186792. BMU_IDLE
186793. BMU_INTR
186794. BMU_IRQ_EOB
186795. BMU_IRQ_EOF
186796. BMU_NO_FCS
186797. BMU_OPER_INIT
186798. BMU_OP_OFF
186799. BMU_OP_ON
186800. BMU_OWN
186801. BMU_RESET_EP_IN
186802. BMU_RESET_EP_OUT
186803. BMU_RST_CLR
186804. BMU_RST_SET
186805. BMU_RX_IP_PKT
186806. BMU_RX_TCP_PKT
186807. BMU_SMT_TX
186808. BMU_START
186809. BMU_STAT_VAL
186810. BMU_STF
186811. BMU_STFWD
186812. BMU_STOP
186813. BMU_ST_BUF
186814. BMU_SW
186815. BMU_TCP_CHECK
186816. BMU_TIST_VAL
186817. BMU_TX_CLR_IRQ_TCP
186818. BMU_TX_IPIDINCR_OFF
186819. BMU_TX_IPIDINCR_ON
186820. BMU_UDP_CHECK
186821. BMU_UNUSED
186822. BMU_WM_DEFAULT
186823. BMU_WM_PEX
186824. BMVAL
186825. BMV_IF_ATTRFORK
186826. BMV_IF_COWFORK
186827. BMV_IF_DELALLOC
186828. BMV_IF_NO_DMAPI_READ
186829. BMV_IF_NO_HOLES
186830. BMV_IF_PREALLOC
186831. BMV_IF_VALID
186832. BMV_OF_DELALLOC
186833. BMV_OF_LAST
186834. BMV_OF_PREALLOC
186835. BMV_OF_SHARED
186836. BM_ADDR
186837. BM_ADDRESS_HIGH
186838. BM_ADDRESS_LOW
186839. BM_AIO_COPY_PAGES
186840. BM_AIO_READ
186841. BM_AIO_WRITE_ALL_PAGES
186842. BM_AIO_WRITE_HINTED
186843. BM_AMR_IMDOM
186844. BM_AMR_IMDOW
186845. BM_AMR_IMDOY
186846. BM_AMR_IMHOUR
186847. BM_AMR_IMMIN
186848. BM_AMR_IMMON
186849. BM_AMR_IMSEC
186850. BM_AMR_IMYEAR
186851. BM_AMR_OFF
186852. BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS
186853. BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG
186854. BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL
186855. BM_ANADIG_REG_2P5_ENABLE_PULLDOWN
186856. BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG
186857. BM_ANADIG_REG_CORE_FET_ODRIVE
186858. BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN
186859. BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1
186860. BM_ANADIG_USB1_MISC_RX_VMIN_FS
186861. BM_ANADIG_USB1_MISC_RX_VPIN_FS
186862. BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID
186863. BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN
186864. BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1
186865. BM_ANADIG_USB2_MISC_RX_VMIN_FS
186866. BM_ANADIG_USB2_MISC_RX_VPIN_FS
186867. BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID
186868. BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B
186869. BM_ANADIG_USB_CHRG_DETECT_EN_B
186870. BM_APBH_CTRL0_APB_BURST8_EN
186871. BM_APBH_CTRL0_APB_BURST_EN
186872. BM_BCH_CTRL_COMPLETE_IRQ
186873. BM_BCH_CTRL_COMPLETE_IRQ_EN
186874. BM_BCH_FLASH0LAYOUT0_DATA0_SIZE
186875. BM_BCH_FLASH0LAYOUT0_ECC0
186876. BM_BCH_FLASH0LAYOUT0_META_SIZE
186877. BM_BCH_FLASH0LAYOUT0_NBLOCKS
186878. BM_BCH_FLASH0LAYOUT1_DATAN_SIZE
186879. BM_BCH_FLASH0LAYOUT1_ECCN
186880. BM_BCH_FLASH0LAYOUT1_PAGE_SIZE
186881. BM_BITS_PER_BLOCK
186882. BM_BITS_PER_EXT
186883. BM_BIT_TO_EXT
186884. BM_BIT_TO_SECT
186885. BM_BLOCKS_PER_BM_EXT_MASK
186886. BM_BLOCK_MASK
186887. BM_BLOCK_SHIFT
186888. BM_BLOCK_SIZE
186889. BM_C0_EN
186890. BM_C0_RST
186891. BM_C1_EN
186892. BM_C1_RST
186893. BM_C2_EN
186894. BM_C2_RST
186895. BM_C3_EN
186896. BM_C3_RST
186897. BM_CALDIR_BACK
186898. BM_CALVAL_M
186899. BM_CCALOFF
186900. BM_CCR_RBC_BYPASS_COUNT
186901. BM_CCR_RBC_EN
186902. BM_CCR_WB_COUNT
186903. BM_CCSR_PLL1_SW_CLK_SEL
186904. BM_CCW_COMMAND
186905. BM_CCW_PIO_NUM
186906. BM_CDHIPR_ARM_PODF_BUSY
186907. BM_CGPR_INT_MEM_CLK_LPM
186908. BM_CIIR_IMDOM
186909. BM_CIIR_IMDOW
186910. BM_CIIR_IMDOY
186911. BM_CIIR_IMHOUR
186912. BM_CIIR_IMMIN
186913. BM_CIIR_IMMON
186914. BM_CIIR_IMSEC
186915. BM_CIIR_IMYEAR
186916. BM_CLKEN
186917. BM_CLPCR_ARM_CLK_DIS_ON_LPM
186918. BM_CLPCR_BYPASS_PMIC_READY
186919. BM_CLPCR_BYP_MMDC_CH0_LPM_HS
186920. BM_CLPCR_BYP_MMDC_CH1_LPM_HS
186921. BM_CLPCR_COSC_PWRDOWN
186922. BM_CLPCR_DIS_REF_OSC
186923. BM_CLPCR_LPM
186924. BM_CLPCR_MASK_CORE0_WFI
186925. BM_CLPCR_MASK_CORE1_WFI
186926. BM_CLPCR_MASK_CORE2_WFI
186927. BM_CLPCR_MASK_CORE3_WFI
186928. BM_CLPCR_MASK_L2CC_IDLE
186929. BM_CLPCR_MASK_SCU_IDLE
186930. BM_CLPCR_SBYOS
186931. BM_CLPCR_STBY_COUNT
186932. BM_CLPCR_VSTBY
186933. BM_CLPCR_WB_CORE_AT_LPM
186934. BM_CLPCR_WB_PER_AT_LPM
186935. BM_CL_CR
186936. BM_CL_RCR
186937. BM_CL_RCR_CI_CENA
186938. BM_CL_RCR_PI_CENA
186939. BM_CL_RR0
186940. BM_CL_RR1
186941. BM_CMD_BUSY
186942. BM_CNT
186943. BM_COMMAND
186944. BM_CONSERVATION_BIT
186945. BM_CONTROL
186946. BM_CONTROL_ENABLE
186947. BM_CONTROL_INIT
186948. BM_CONTROL_IRQEN
186949. BM_COUNT
186950. BM_COUNTER_CLR
186951. BM_COUNT_MASK
186952. BM_CS_CTRL1
186953. BM_CS_STATUS
186954. BM_CS_STATUS_LINK_UP
186955. BM_CS_STATUS_RESOLVED
186956. BM_CS_STATUS_SPEED_1000
186957. BM_CS_STATUS_SPEED_MASK
186958. BM_CTCR0_SHIFT
186959. BM_CTCR1_SHIFT
186960. BM_CTCR2_SHIFT
186961. BM_CTCR3_SHIFT
186962. BM_CTCRST
186963. BM_CTCR_DEFAULT
186964. BM_CTCR_TM
186965. BM_CTIME0_DOW_M
186966. BM_CTIME0_DOW_S
186967. BM_CTIME0_HOUR_M
186968. BM_CTIME0_HOUR_S
186969. BM_CTIME0_MIN_M
186970. BM_CTIME0_MIN_S
186971. BM_CTIME0_SEC_M
186972. BM_CTIME0_SEC_S
186973. BM_CTIME1_DOM_M
186974. BM_CTIME1_DOM_S
186975. BM_CTIME1_MON_M
186976. BM_CTIME1_MON_S
186977. BM_CTIME1_YEAR_M
186978. BM_CTIME1_YEAR_S
186979. BM_CTIME2_DOY_M
186980. BM_CTIME2_DOY_S
186981. BM_CTL_BYTE_ORD_BE
186982. BM_CTL_BYTE_ORD_LE
186983. BM_CTL_DIS
186984. BM_CTL_EN
186985. BM_CTL_PAUSE
186986. BM_CTRL0
186987. BM_CTRL1
186988. BM_CYCLE
186989. BM_CYCLE0
186990. BM_CYCLE1
186991. BM_DATA
186992. BM_DATA_EN
186993. BM_DESCRIPTOR_ENTRY
186994. BM_DIR0_SHIFT
186995. BM_DIR1_SHIFT
186996. BM_DIR2_SHIFT
186997. BM_DIR3_SHIFT
186998. BM_DIR_COUNT_DOWN
186999. BM_DIR_COUNT_UP
187000. BM_DIR_DEFAULT
187001. BM_DONT_CLEAR
187002. BM_DONT_SET
187003. BM_DONT_TEST
187004. BM_EIGHTBIT_MODE
187005. BM_EIRQ_BSCN
187006. BM_EIRQ_FLWI
187007. BM_EIRQ_IVCI
187008. BM_EIRQ_MBEI
187009. BM_EIRQ_SBEI
187010. BM_END_OF_MAP
187011. BM_ENTRIES_PER_LEVEL
187012. BM_EOP_ERR
187013. BM_EXT_SHIFT
187014. BM_EXT_SIZE
187015. BM_EXT_TO_SECT
187016. BM_FORCE_OFF
187017. BM_FOURBIT_MODE
187018. BM_FRAME_ASSERT_TIMING
187019. BM_FRAME_BUF_OFFSET
187020. BM_GPMI_CTRL0_ADDRESS
187021. BM_GPMI_CTRL0_ADDRESS_INCREMENT
187022. BM_GPMI_CTRL0_COMMAND_MODE
187023. BM_GPMI_CTRL0_WORD_LENGTH
187024. BM_GPMI_CTRL0_XFER_COUNT
187025. BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY
187026. BM_GPMI_CTRL1_BCH_MODE
187027. BM_GPMI_CTRL1_CAMERA_MODE
187028. BM_GPMI_CTRL1_CLEAR_MASK
187029. BM_GPMI_CTRL1_DECOUPLE_CS
187030. BM_GPMI_CTRL1_DEV_RESET
187031. BM_GPMI_CTRL1_DLL_ENABLE
187032. BM_GPMI_CTRL1_GPMI_MODE
187033. BM_GPMI_CTRL1_HALF_PERIOD
187034. BM_GPMI_CTRL1_RDN_DELAY
187035. BM_GPMI_CTRL1_WRN_DLY_SEL
187036. BM_GPMI_ECCCTRL_BUFFER_MASK
187037. BM_GPMI_ECCCTRL_ECC_CMD
187038. BM_GPMI_ECCCTRL_ENABLE_ECC
187039. BM_GPMI_TIMING0_ADDRESS_SETUP
187040. BM_GPMI_TIMING0_DATA_HOLD
187041. BM_GPMI_TIMING0_DATA_SETUP
187042. BM_GPMI_TIMING1_BUSY_TIMEOUT
187043. BM_GUI_TABLE
187044. BM_GUI_TABLE_CMD
187045. BM_HOSTDATA
187046. BM_IBE_ENABLED
187047. BM_ICOLL_INTR_ENABLE
187048. BM_IRDY_ASSERT_TIMING
187049. BM_IR_CR0
187050. BM_IR_MR0
187051. BM_IR_MR1
187052. BM_IR_MR2
187053. BM_IR_MR3
187054. BM_IS_LOCKED
187055. BM_LENGTH
187056. BM_LOCKED_CHANGE_ALLOWED
187057. BM_LOCKED_MASK
187058. BM_LOCKED_SET_ALLOWED
187059. BM_LOCKED_TEST_ALLOWED
187060. BM_MAX_NUM_OF_POOLS
187061. BM_MCC_VERB_ACQUIRE_BUFCOUNT
187062. BM_MCC_VERB_CMD_ACQUIRE
187063. BM_MCC_VERB_CMD_MASK
187064. BM_MCC_VERB_CMD_QUERY
187065. BM_MCC_VERB_VBIT
187066. BM_MCR_INT_EN
187067. BM_MCR_RES_EN
187068. BM_MCR_STOP_EN
187069. BM_MCR_TIMEOUT
187070. BM_MCR_VERB_ACQUIRE_BUFCOUNT
187071. BM_MCR_VERB_CMD_ACQUIRE
187072. BM_MCR_VERB_CMD_ERR_ECC
187073. BM_MCR_VERB_CMD_ERR_INVALID
187074. BM_MCR_VERB_CMD_MASK
187075. BM_MCR_VERB_CMD_QUERY
187076. BM_MCR_VERB_VBIT
187077. BM_MIIGSK_CFGR_FRCONT_10M
187078. BM_MIIGSK_CFGR_MII
187079. BM_MIIGSK_CFGR_RMII
187080. BM_MMDC_MDMISC_DDR_TYPE
187081. BM_MOD_WDEN
187082. BM_MOD_WDINT
187083. BM_MOD_WDRESET
187084. BM_MOD_WDTOF
187085. BM_MTA
187086. BM_MUX_MODE
187087. BM_OBE_ENABLED
187088. BM_OCOTP_CTRL_BUSY
187089. BM_OCOTP_CTRL_ERROR
187090. BM_OCOTP_CTRL_RD_BANK_OPEN
187091. BM_PAD_CTL_GP_ENABLE
187092. BM_PAD_CTL_IFMUX_ENABLE
187093. BM_PAGE_HINT_WRITEOUT
187094. BM_PAGE_IDX_MASK
187095. BM_PAGE_IO_ERROR
187096. BM_PAGE_IO_LOCK
187097. BM_PAGE_LAZY_WRITEOUT
187098. BM_PAGE_NEED_WRITEOUT
187099. BM_PARITY_ERR
187100. BM_PHY_PAGE_SELECT
187101. BM_PHY_REG
187102. BM_PHY_REG_NUM
187103. BM_PHY_REG_PAGE
187104. BM_PIRQ_RCRI
187105. BM_PIRQ_VISIBLE
187106. BM_PLL_ARM_DIV_SELECT
187107. BM_PLL_ARM_ENABLE
187108. BM_PLL_ARM_LOCK
187109. BM_PLL_ARM_POWERDOWN
187110. BM_PLL_LOCK
187111. BM_PLL_MULT
187112. BM_PLL_POWER
187113. BM_PMCTRL_PSTOPO
187114. BM_PMCTRL_RUNM
187115. BM_PMCTRL_STOPM
187116. BM_POOL_MAX
187117. BM_PORT_CTRL_PAGE
187118. BM_PORT_GEN_CFG
187119. BM_PR_DISABLE
187120. BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE
187121. BM_PXP_ALPHA_A_CTRL_RSVD0
187122. BM_PXP_ALPHA_A_CTRL_RSVD1
187123. BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE
187124. BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE
187125. BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA
187126. BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE
187127. BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE
187128. BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE
187129. BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE
187130. BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA
187131. BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE
187132. BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE
187133. BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE
187134. BM_PXP_ALPHA_B_CTRL_1_ROP
187135. BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE
187136. BM_PXP_ALPHA_B_CTRL_1_RSVD0
187137. BM_PXP_ALPHA_B_CTRL_1_RSVD1
187138. BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE
187139. BM_PXP_ALPHA_B_CTRL_RSVD0
187140. BM_PXP_ALPHA_B_CTRL_RSVD1
187141. BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE
187142. BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE
187143. BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA
187144. BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE
187145. BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE
187146. BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE
187147. BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE
187148. BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA
187149. BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE
187150. BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE
187151. BM_PXP_AS_BUF_ADDR
187152. BM_PXP_AS_CLRKEYHIGH_0_PIXEL
187153. BM_PXP_AS_CLRKEYHIGH_0_RSVD1
187154. BM_PXP_AS_CLRKEYHIGH_1_PIXEL
187155. BM_PXP_AS_CLRKEYHIGH_1_RSVD1
187156. BM_PXP_AS_CLRKEYLOW_0_PIXEL
187157. BM_PXP_AS_CLRKEYLOW_0_RSVD1
187158. BM_PXP_AS_CLRKEYLOW_1_PIXEL
187159. BM_PXP_AS_CLRKEYLOW_1_RSVD1
187160. BM_PXP_AS_CTRL_ALPHA
187161. BM_PXP_AS_CTRL_ALPHA0_INVERT
187162. BM_PXP_AS_CTRL_ALPHA1_INVERT
187163. BM_PXP_AS_CTRL_ALPHA_CTRL
187164. BM_PXP_AS_CTRL_ENABLE_COLORKEY
187165. BM_PXP_AS_CTRL_FORMAT
187166. BM_PXP_AS_CTRL_ROP
187167. BM_PXP_AS_CTRL_RSVD0
187168. BM_PXP_AS_CTRL_RSVD1
187169. BM_PXP_AS_PITCH_PITCH
187170. BM_PXP_AS_PITCH_RSVD
187171. BM_PXP_CFA_DATA
187172. BM_PXP_CSC1_COEF0_BYPASS
187173. BM_PXP_CSC1_COEF0_C0
187174. BM_PXP_CSC1_COEF0_RSVD1
187175. BM_PXP_CSC1_COEF0_UV_OFFSET
187176. BM_PXP_CSC1_COEF0_YCBCR_MODE
187177. BM_PXP_CSC1_COEF0_Y_OFFSET
187178. BM_PXP_CSC1_COEF1_C1
187179. BM_PXP_CSC1_COEF1_C4
187180. BM_PXP_CSC1_COEF1_RSVD0
187181. BM_PXP_CSC1_COEF1_RSVD1
187182. BM_PXP_CSC1_COEF2_C2
187183. BM_PXP_CSC1_COEF2_C3
187184. BM_PXP_CSC1_COEF2_RSVD0
187185. BM_PXP_CSC1_COEF2_RSVD1
187186. BM_PXP_CSC2_COEF0_A1
187187. BM_PXP_CSC2_COEF0_A2
187188. BM_PXP_CSC2_COEF0_RSVD0
187189. BM_PXP_CSC2_COEF0_RSVD1
187190. BM_PXP_CSC2_COEF1_A3
187191. BM_PXP_CSC2_COEF1_B1
187192. BM_PXP_CSC2_COEF1_RSVD0
187193. BM_PXP_CSC2_COEF1_RSVD1
187194. BM_PXP_CSC2_COEF2_B2
187195. BM_PXP_CSC2_COEF2_B3
187196. BM_PXP_CSC2_COEF2_RSVD0
187197. BM_PXP_CSC2_COEF2_RSVD1
187198. BM_PXP_CSC2_COEF3_C1
187199. BM_PXP_CSC2_COEF3_C2
187200. BM_PXP_CSC2_COEF3_RSVD0
187201. BM_PXP_CSC2_COEF3_RSVD1
187202. BM_PXP_CSC2_COEF4_C3
187203. BM_PXP_CSC2_COEF4_D1
187204. BM_PXP_CSC2_COEF4_RSVD0
187205. BM_PXP_CSC2_COEF4_RSVD1
187206. BM_PXP_CSC2_COEF5_D2
187207. BM_PXP_CSC2_COEF5_D3
187208. BM_PXP_CSC2_COEF5_RSVD0
187209. BM_PXP_CSC2_COEF5_RSVD1
187210. BM_PXP_CSC2_CTRL_BYPASS
187211. BM_PXP_CSC2_CTRL_CSC_MODE
187212. BM_PXP_CSC2_CTRL_RSVD
187213. BM_PXP_CTRL2_BLOCK_SIZE
187214. BM_PXP_CTRL2_ENABLE
187215. BM_PXP_CTRL2_ENABLE_ALPHA_B
187216. BM_PXP_CTRL2_ENABLE_CSC2
187217. BM_PXP_CTRL2_ENABLE_DITHER
187218. BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE
187219. BM_PXP_CTRL2_ENABLE_LUT
187220. BM_PXP_CTRL2_ENABLE_ROTATE0
187221. BM_PXP_CTRL2_ENABLE_ROTATE1
187222. BM_PXP_CTRL2_ENABLE_WFE_A
187223. BM_PXP_CTRL2_ENABLE_WFE_B
187224. BM_PXP_CTRL2_HFLIP0
187225. BM_PXP_CTRL2_HFLIP1
187226. BM_PXP_CTRL2_ROTATE0
187227. BM_PXP_CTRL2_ROTATE1
187228. BM_PXP_CTRL2_RSVD0
187229. BM_PXP_CTRL2_RSVD1
187230. BM_PXP_CTRL2_RSVD2
187231. BM_PXP_CTRL2_RSVD3
187232. BM_PXP_CTRL2_VFLIP0
187233. BM_PXP_CTRL2_VFLIP1
187234. BM_PXP_CTRL_BLOCK_SIZE
187235. BM_PXP_CTRL_CLKGATE
187236. BM_PXP_CTRL_ENABLE
187237. BM_PXP_CTRL_ENABLE_ALPHA_B
187238. BM_PXP_CTRL_ENABLE_CSC2
187239. BM_PXP_CTRL_ENABLE_DITHER
187240. BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE
187241. BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE
187242. BM_PXP_CTRL_ENABLE_LUT
187243. BM_PXP_CTRL_ENABLE_PS_AS_OUT
187244. BM_PXP_CTRL_ENABLE_ROTATE0
187245. BM_PXP_CTRL_ENABLE_ROTATE1
187246. BM_PXP_CTRL_ENABLE_WFE_A
187247. BM_PXP_CTRL_ENABLE_WFE_B
187248. BM_PXP_CTRL_EN_REPEAT
187249. BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP
187250. BM_PXP_CTRL_HFLIP0
187251. BM_PXP_CTRL_HFLIP1
187252. BM_PXP_CTRL_IRQ_ENABLE
187253. BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE
187254. BM_PXP_CTRL_NEXT_IRQ_ENABLE
187255. BM_PXP_CTRL_ROTATE0
187256. BM_PXP_CTRL_ROTATE1
187257. BM_PXP_CTRL_RSVD0
187258. BM_PXP_CTRL_RSVD1
187259. BM_PXP_CTRL_RSVD4
187260. BM_PXP_CTRL_SFTRST
187261. BM_PXP_CTRL_VFLIP0
187262. BM_PXP_CTRL_VFLIP1
187263. BM_PXP_DATA_PATH_CTRL0_MUX0_SEL
187264. BM_PXP_DATA_PATH_CTRL0_MUX10_SEL
187265. BM_PXP_DATA_PATH_CTRL0_MUX11_SEL
187266. BM_PXP_DATA_PATH_CTRL0_MUX12_SEL
187267. BM_PXP_DATA_PATH_CTRL0_MUX13_SEL
187268. BM_PXP_DATA_PATH_CTRL0_MUX14_SEL
187269. BM_PXP_DATA_PATH_CTRL0_MUX15_SEL
187270. BM_PXP_DATA_PATH_CTRL0_MUX1_SEL
187271. BM_PXP_DATA_PATH_CTRL0_MUX2_SEL
187272. BM_PXP_DATA_PATH_CTRL0_MUX3_SEL
187273. BM_PXP_DATA_PATH_CTRL0_MUX4_SEL
187274. BM_PXP_DATA_PATH_CTRL0_MUX5_SEL
187275. BM_PXP_DATA_PATH_CTRL0_MUX6_SEL
187276. BM_PXP_DATA_PATH_CTRL0_MUX7_SEL
187277. BM_PXP_DATA_PATH_CTRL0_MUX8_SEL
187278. BM_PXP_DATA_PATH_CTRL0_MUX9_SEL
187279. BM_PXP_DATA_PATH_CTRL1_MUX16_SEL
187280. BM_PXP_DATA_PATH_CTRL1_MUX17_SEL
187281. BM_PXP_DATA_PATH_CTRL1_RSVD0
187282. BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT
187283. BM_PXP_DEBUGCTRL_RSVD
187284. BM_PXP_DEBUGCTRL_SELECT
187285. BM_PXP_DEBUG_DATA
187286. BM_PXP_INIT_MEM_CTRL_ADDR
187287. BM_PXP_INIT_MEM_CTRL_RSVD0
187288. BM_PXP_INIT_MEM_CTRL_SELECT
187289. BM_PXP_INIT_MEM_CTRL_START
187290. BM_PXP_INIT_MEM_DATA_DATA
187291. BM_PXP_INIT_MEM_DATA_HIGH_DATA
187292. BM_PXP_IRQ_COMPRESS_DONE_IRQ
187293. BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ
187294. BM_PXP_IRQ_DITHER_CH0_STORE_IRQ
187295. BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ
187296. BM_PXP_IRQ_DITHER_CH1_STORE_IRQ
187297. BM_PXP_IRQ_DITHER_STORE_IRQ
187298. BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ
187299. BM_PXP_IRQ_FIRST_CH0_STORE_IRQ
187300. BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ
187301. BM_PXP_IRQ_FIRST_CH1_STORE_IRQ
187302. BM_PXP_IRQ_FIRST_STORE_IRQ
187303. BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN
187304. BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN
187305. BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN
187306. BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN
187307. BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN
187308. BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN
187309. BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN
187310. BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN
187311. BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN
187312. BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN
187313. BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN
187314. BM_PXP_IRQ_MASK_RSVD1
187315. BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN
187316. BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN
187317. BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN
187318. BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN
187319. BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN
187320. BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN
187321. BM_PXP_IRQ_RSVD1
187322. BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ
187323. BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ
187324. BM_PXP_IRQ_WFE_A_STORE_IRQ
187325. BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ
187326. BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ
187327. BM_PXP_IRQ_WFE_B_STORE_IRQ
187328. BM_PXP_LUT_ADDR_ADDR
187329. BM_PXP_LUT_ADDR_NUM_BYTES
187330. BM_PXP_LUT_ADDR_RSVD1
187331. BM_PXP_LUT_ADDR_RSVD2
187332. BM_PXP_LUT_CTRL_BYPASS
187333. BM_PXP_LUT_CTRL_DMA_START
187334. BM_PXP_LUT_CTRL_INVALID
187335. BM_PXP_LUT_CTRL_LOOKUP_MODE
187336. BM_PXP_LUT_CTRL_LRU_UPD
187337. BM_PXP_LUT_CTRL_OUT_MODE
187338. BM_PXP_LUT_CTRL_RSVD0
187339. BM_PXP_LUT_CTRL_RSVD1
187340. BM_PXP_LUT_CTRL_RSVD2
187341. BM_PXP_LUT_CTRL_RSVD3
187342. BM_PXP_LUT_CTRL_SEL_8KB
187343. BM_PXP_LUT_DATA_DATA
187344. BM_PXP_LUT_EXTMEM_ADDR
187345. BM_PXP_NEXT_ENABLED
187346. BM_PXP_NEXT_POINTER
187347. BM_PXP_NEXT_RSVD
187348. BM_PXP_OUT_AS_LRC_RSVD0
187349. BM_PXP_OUT_AS_LRC_RSVD1
187350. BM_PXP_OUT_AS_LRC_X
187351. BM_PXP_OUT_AS_LRC_Y
187352. BM_PXP_OUT_AS_ULC_RSVD0
187353. BM_PXP_OUT_AS_ULC_RSVD1
187354. BM_PXP_OUT_AS_ULC_X
187355. BM_PXP_OUT_AS_ULC_Y
187356. BM_PXP_OUT_BUF2_ADDR
187357. BM_PXP_OUT_BUF_ADDR
187358. BM_PXP_OUT_CTRL_ALPHA
187359. BM_PXP_OUT_CTRL_ALPHA_OUTPUT
187360. BM_PXP_OUT_CTRL_FORMAT
187361. BM_PXP_OUT_CTRL_INTERLACED_OUTPUT
187362. BM_PXP_OUT_CTRL_RSVD0
187363. BM_PXP_OUT_CTRL_RSVD1
187364. BM_PXP_OUT_LRC_RSVD0
187365. BM_PXP_OUT_LRC_RSVD1
187366. BM_PXP_OUT_LRC_X
187367. BM_PXP_OUT_LRC_Y
187368. BM_PXP_OUT_PITCH_PITCH
187369. BM_PXP_OUT_PITCH_RSVD
187370. BM_PXP_OUT_PS_LRC_RSVD0
187371. BM_PXP_OUT_PS_LRC_RSVD1
187372. BM_PXP_OUT_PS_LRC_X
187373. BM_PXP_OUT_PS_LRC_Y
187374. BM_PXP_OUT_PS_ULC_RSVD0
187375. BM_PXP_OUT_PS_ULC_RSVD1
187376. BM_PXP_OUT_PS_ULC_X
187377. BM_PXP_OUT_PS_ULC_Y
187378. BM_PXP_POWER_REG0_CTRL
187379. BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0
187380. BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN
187381. BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN
187382. BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE
187383. BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE
187384. BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE
187385. BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE
187386. BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE
187387. BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE
187388. BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE
187389. BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE
187390. BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE
187391. BM_PXP_POWER_REG1_RSVD0
187392. BM_PXP_PS_BACKGROUND_0_COLOR
187393. BM_PXP_PS_BACKGROUND_0_RSVD
187394. BM_PXP_PS_BACKGROUND_1_COLOR
187395. BM_PXP_PS_BACKGROUND_1_RSVD
187396. BM_PXP_PS_BUF_ADDR
187397. BM_PXP_PS_CLRKEYHIGH_0_PIXEL
187398. BM_PXP_PS_CLRKEYHIGH_0_RSVD1
187399. BM_PXP_PS_CLRKEYHIGH_1_PIXEL
187400. BM_PXP_PS_CLRKEYHIGH_1_RSVD1
187401. BM_PXP_PS_CLRKEYLOW_0_PIXEL
187402. BM_PXP_PS_CLRKEYLOW_0_RSVD1
187403. BM_PXP_PS_CLRKEYLOW_1_PIXEL
187404. BM_PXP_PS_CLRKEYLOW_1_RSVD1
187405. BM_PXP_PS_CTRL_DECX
187406. BM_PXP_PS_CTRL_DECY
187407. BM_PXP_PS_CTRL_FORMAT
187408. BM_PXP_PS_CTRL_RSVD0
187409. BM_PXP_PS_CTRL_RSVD1
187410. BM_PXP_PS_CTRL_WB_SWAP
187411. BM_PXP_PS_OFFSET_RSVD1
187412. BM_PXP_PS_OFFSET_RSVD2
187413. BM_PXP_PS_OFFSET_XOFFSET
187414. BM_PXP_PS_OFFSET_YOFFSET
187415. BM_PXP_PS_PITCH_PITCH
187416. BM_PXP_PS_PITCH_RSVD
187417. BM_PXP_PS_SCALE_RSVD1
187418. BM_PXP_PS_SCALE_RSVD2
187419. BM_PXP_PS_SCALE_XSCALE
187420. BM_PXP_PS_SCALE_YSCALE
187421. BM_PXP_PS_UBUF_ADDR
187422. BM_PXP_PS_VBUF_ADDR
187423. BM_PXP_STAT_AXI_ERROR_ID_0
187424. BM_PXP_STAT_AXI_ERROR_ID_1
187425. BM_PXP_STAT_AXI_READ_ERROR_0
187426. BM_PXP_STAT_AXI_READ_ERROR_1
187427. BM_PXP_STAT_AXI_WRITE_ERROR_0
187428. BM_PXP_STAT_AXI_WRITE_ERROR_1
187429. BM_PXP_STAT_BLOCKX
187430. BM_PXP_STAT_BLOCKY
187431. BM_PXP_STAT_IRQ0
187432. BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ
187433. BM_PXP_STAT_NEXT_IRQ
187434. BM_PXP_STAT_RSVD2
187435. BM_PXP_VERSION_MAJOR
187436. BM_PXP_VERSION_MINOR
187437. BM_PXP_VERSION_STEP
187438. BM_RAR_CTRL
187439. BM_RAR_H
187440. BM_RAR_L
187441. BM_RAR_M
187442. BM_RCR_SIZE
187443. BM_RCR_VERB_BUFCOUNT_MASK
187444. BM_RCR_VERB_CMD_BPID_MULTI
187445. BM_RCR_VERB_CMD_BPID_SINGLE
187446. BM_RCR_VERB_CMD_MASK
187447. BM_RCR_VERB_VBIT
187448. BM_RCTL
187449. BM_RCTL_BAM
187450. BM_RCTL_MO_MASK
187451. BM_RCTL_MO_SHIFT
187452. BM_RCTL_MPE
187453. BM_RCTL_PMCF
187454. BM_RCTL_RFCE
187455. BM_RCTL_UPE
187456. BM_REG_CFG
187457. BM_REG_IER
187458. BM_REG_IIR
187459. BM_REG_ISDR
187460. BM_REG_ISR
187461. BM_REG_RCR_CI_CINH
187462. BM_REG_RCR_ITR
187463. BM_REG_RCR_PI_CINH
187464. BM_REG_SCN
187465. BM_REQUEST_TYPE
187466. BM_RTCALF
187467. BM_RTCCIF
187468. BM_RTREE_LEVEL_MASK
187469. BM_RTREE_LEVEL_SHIFT
187470. BM_SAIF_CTRL_BITCLK_48XFS_ENABLE
187471. BM_SAIF_CTRL_BITCLK_BASE_RATE
187472. BM_SAIF_CTRL_BITCLK_EDGE
187473. BM_SAIF_CTRL_BITCLK_MULT_RATE
187474. BM_SAIF_CTRL_BIT_ORDER
187475. BM_SAIF_CTRL_CHANNEL_NUM_SELECT
187476. BM_SAIF_CTRL_CLKGATE
187477. BM_SAIF_CTRL_DELAY
187478. BM_SAIF_CTRL_DMAWAIT_COUNT
187479. BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN
187480. BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN
187481. BM_SAIF_CTRL_JUSTIFY
187482. BM_SAIF_CTRL_LRCLK_POLARITY
187483. BM_SAIF_CTRL_LRCLK_PULSE
187484. BM_SAIF_CTRL_READ_MODE
187485. BM_SAIF_CTRL_RSRVD2
187486. BM_SAIF_CTRL_RUN
187487. BM_SAIF_CTRL_SFTRST
187488. BM_SAIF_CTRL_SLAVE_MODE
187489. BM_SAIF_CTRL_WORD_LENGTH
187490. BM_SAIF_DATA_PCM_LEFT
187491. BM_SAIF_DATA_PCM_RIGHT
187492. BM_SAIF_STAT_BUSY
187493. BM_SAIF_STAT_DMA_PREQ
187494. BM_SAIF_STAT_FIFO_OVERFLOW_IRQ
187495. BM_SAIF_STAT_FIFO_SERVICE_IRQ
187496. BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ
187497. BM_SAIF_STAT_PRESENT
187498. BM_SAIF_STAT_RSRVD0
187499. BM_SAIF_STAT_RSRVD1
187500. BM_SAIF_STAT_RSRVD2
187501. BM_SAIF_VERSION_MAJOR
187502. BM_SAIF_VERSION_MINOR
187503. BM_SAIF_VERSION_STEP
187504. BM_SCLC
187505. BM_SCLS
187506. BM_SDAC
187507. BM_SDAS
187508. BM_SD_OFF
187509. BM_SD_POWER
187510. BM_SECT_PER_BIT
187511. BM_SECT_PER_EXT
187512. BM_SECT_TO_BIT
187513. BM_SECT_TO_EXT
187514. BM_SINGLE_BUS_MASTER
187515. BM_SINGLE_MODE
187516. BM_SIZE
187517. BM_SOFT_RESET
187518. BM_SPI_CS
187519. BM_SPI_MODE
187520. BM_SSP_BLOCK_SIZE_BLOCK_COUNT
187521. BM_SSP_BLOCK_SIZE_BLOCK_SIZE
187522. BM_SSP_CMD0_APPEND_8CYC
187523. BM_SSP_CMD0_BLOCK_COUNT
187524. BM_SSP_CMD0_BLOCK_SIZE
187525. BM_SSP_CMD0_CMD
187526. BM_SSP_CMD0_CONT_CLKING_EN
187527. BM_SSP_CMD0_DBL_DATA_RATE_EN
187528. BM_SSP_CMD0_SLOW_CLKING_EN
187529. BM_SSP_CTRL0_BUS_WIDTH
187530. BM_SSP_CTRL0_DATA_XFER
187531. BM_SSP_CTRL0_ENABLE
187532. BM_SSP_CTRL0_GET_RESP
187533. BM_SSP_CTRL0_IGNORE_CRC
187534. BM_SSP_CTRL0_LOCK_CS
187535. BM_SSP_CTRL0_LONG_RESP
187536. BM_SSP_CTRL0_READ
187537. BM_SSP_CTRL0_RUN
187538. BM_SSP_CTRL0_SDIO_IRQ_CHECK
187539. BM_SSP_CTRL0_WAIT_FOR_CMD
187540. BM_SSP_CTRL0_WAIT_FOR_IRQ
187541. BM_SSP_CTRL0_XFER_COUNT
187542. BM_SSP_CTRL1_DATA_CRC_IRQ
187543. BM_SSP_CTRL1_DATA_CRC_IRQ_EN
187544. BM_SSP_CTRL1_DATA_TIMEOUT_IRQ
187545. BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
187546. BM_SSP_CTRL1_DMA_ENABLE
187547. BM_SSP_CTRL1_FIFO_OVERRUN_IRQ
187548. BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN
187549. BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ
187550. BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN
187551. BM_SSP_CTRL1_PHASE
187552. BM_SSP_CTRL1_POLARITY
187553. BM_SSP_CTRL1_RECV_TIMEOUT_IRQ
187554. BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
187555. BM_SSP_CTRL1_RESP_ERR_IRQ
187556. BM_SSP_CTRL1_RESP_ERR_IRQ_EN
187557. BM_SSP_CTRL1_RESP_TIMEOUT_IRQ
187558. BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
187559. BM_SSP_CTRL1_SDIO_IRQ
187560. BM_SSP_CTRL1_SDIO_IRQ_EN
187561. BM_SSP_CTRL1_SSP_MODE
187562. BM_SSP_CTRL1_WORD_LENGTH
187563. BM_SSP_STATUS_CARD_DETECT
187564. BM_SSP_STATUS_FIFO_EMPTY
187565. BM_SSP_STATUS_SDIO_IRQ
187566. BM_SSP_TIMING_CLOCK_DIVIDE
187567. BM_SSP_TIMING_CLOCK_RATE
187568. BM_SSP_TIMING_TIMEOUT
187569. BM_START
187570. BM_START_ADR
187571. BM_STATUS
187572. BM_STR_OFF
187573. BM_SYSTEM_MEM_ADDR
187574. BM_SYSTEM_TABLE
187575. BM_TEST
187576. BM_TEST_DIR
187577. BM_THRESHOLD
187578. BM_TIMROT_TIMCTRLn_IRQ
187579. BM_TIMROT_TIMCTRLn_IRQ_EN
187580. BM_TIMROT_TIMCTRLn_RELOAD
187581. BM_TIMROT_TIMCTRLn_UPDATE
187582. BM_USBPHY_CTRL_CLKGATE
187583. BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE
187584. BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD
187585. BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE
187586. BM_USBPHY_CTRL_ENAUTOSET_USBCLKS
187587. BM_USBPHY_CTRL_ENAUTO_PWRON_PLL
187588. BM_USBPHY_CTRL_ENDPDMCHG_WKUP
187589. BM_USBPHY_CTRL_ENHOSTDISCONDETECT
187590. BM_USBPHY_CTRL_ENIDCHG_WKUP
187591. BM_USBPHY_CTRL_ENUTMILEVEL2
187592. BM_USBPHY_CTRL_ENUTMILEVEL3
187593. BM_USBPHY_CTRL_ENVBUSCHG_WKUP
187594. BM_USBPHY_CTRL_OTG_ID_VALUE
187595. BM_USBPHY_CTRL_SFTRST
187596. BM_USBPHY_DEBUG_CLKGATE
187597. BM_USBPHY_IP_FIX
187598. BM_USBPHY_PLL_BYPASS
187599. BM_USBPHY_PLL_EN_USB_CLKS
187600. BM_USBPHY_PLL_LOCK
187601. BM_USBPHY_PLL_POWER
187602. BM_USBPHY_PLL_REG_ENABLE
187603. BM_VID_ADDR_HIGH
187604. BM_VID_ADDR_LOW
187605. BM_VME_CONTROL_ABLE
187606. BM_VME_CONTROL_BERRI
187607. BM_VME_CONTROL_BERRST
187608. BM_VME_CONTROL_BPENA
187609. BM_VME_CONTROL_MASTER_ENDIAN
187610. BM_VME_CONTROL_SLAVE_ENDIAN
187611. BM_VME_CONTROL_VBENA
187612. BM_WDTC_MAX
187613. BM_WUC
187614. BM_WUC_ADDRESS_OPCODE
187615. BM_WUC_DATA_OPCODE
187616. BM_WUC_ENABLE_BIT
187617. BM_WUC_ENABLE_PAGE
187618. BM_WUC_ENABLE_REG
187619. BM_WUC_HOST_WU_BIT
187620. BM_WUC_ME_WU_BIT
187621. BM_WUC_PAGE
187622. BM_WUFC
187623. BM_WUS
187624. BNAD_CF_ALLMULTI
187625. BNAD_CF_DEFAULT
187626. BNAD_CF_DIM_ENABLED
187627. BNAD_CF_MSIX
187628. BNAD_CF_PROMISC
187629. BNAD_DIM_TIMER_FREQ
187630. BNAD_ETHTOOL_STATS_NUM
187631. BNAD_FILL_UNMAPQ_MEM_REQ
187632. BNAD_FRAME_SIZE
187633. BNAD_GET_CTR
187634. BNAD_GET_MBOX_IRQ
187635. BNAD_INTR_RX
187636. BNAD_INTR_TX
187637. BNAD_INTX_RX_IB_BITMASK
187638. BNAD_INTX_TX_IB_BITMASK
187639. BNAD_IOCETH_TIMEOUT
187640. BNAD_JUMBO_MTU
187641. BNAD_LS_DOWN
187642. BNAD_LS_UP
187643. BNAD_MAILBOX_MSIX_INDEX
187644. BNAD_MAILBOX_MSIX_VECTORS
187645. BNAD_MAX_RX
187646. BNAD_MAX_RXP_PER_RX
187647. BNAD_MAX_RXQ_DEPTH
187648. BNAD_MAX_RXQ_PER_RXP
187649. BNAD_MAX_TX
187650. BNAD_MAX_TXQ_DEPTH
187651. BNAD_MAX_TXQ_PER_TX
187652. BNAD_MIN_Q_DEPTH
187653. BNAD_NAME
187654. BNAD_NAME_LEN
187655. BNAD_NAPI_POLL_QUOTA
187656. BNAD_NETIF_WAKE_THRESHOLD
187657. BNAD_NUM_CQ_COUNTERS
187658. BNAD_NUM_RXF_COUNTERS
187659. BNAD_NUM_RXP
187660. BNAD_NUM_RXQ_COUNTERS
187661. BNAD_NUM_TXF_COUNTERS
187662. BNAD_NUM_TXQ
187663. BNAD_NUM_TXQ_COUNTERS
187664. BNAD_PCI_DEV_IS_CAT2
187665. BNAD_RF_CEE_RUNNING
187666. BNAD_RF_DIM_TIMER_RUNNING
187667. BNAD_RF_MBOX_IRQ_DISABLED
187668. BNAD_RF_MTU_SET
187669. BNAD_RF_NETDEV_REGISTERED
187670. BNAD_RF_STATS_TIMER_RUNNING
187671. BNAD_RF_TX_PRIO_SET
187672. BNAD_RXBUF_IS_MULTI_BUFF
187673. BNAD_RXBUF_IS_SK_BUFF
187674. BNAD_RXBUF_MULTI_BUFF
187675. BNAD_RXBUF_NONE
187676. BNAD_RXBUF_PAGE
187677. BNAD_RXBUF_SK_BUFF
187678. BNAD_RXMODE_PROMISC_DEFAULT
187679. BNAD_RXQ_DEPTH
187680. BNAD_RXQ_POST_OK
187681. BNAD_RXQ_REFILL_THRESHOLD_SHIFT
187682. BNAD_RXQ_STARTED
187683. BNAD_STATS_TIMER_FREQ
187684. BNAD_TXQ_DEPTH
187685. BNAD_TXQ_FREE_SENT
187686. BNAD_TXQ_NUM
187687. BNAD_TXQ_TX_STARTED
187688. BNAD_UPDATE_CTR
187689. BNAD_VERSION
187690. BNA_BIAS_T_LARGE
187691. BNA_BIAS_T_MAX
187692. BNA_BIAS_T_SMALL
187693. BNA_CB_BUSY
187694. BNA_CB_FAIL
187695. BNA_CB_INTERRUPT
187696. BNA_CB_INVALID_MAC
187697. BNA_CB_MCAST_LIST_FULL
187698. BNA_CB_NOT_EXEC
187699. BNA_CB_SUCCESS
187700. BNA_CB_UCAST_CAM_FULL
187701. BNA_CB_WAITING
187702. BNA_CEE_UP
187703. BNA_CQ_EF_BCAST
187704. BNA_CQ_EF_EOP
187705. BNA_CQ_EF_FCS_ERROR
187706. BNA_CQ_EF_FC_CRC_OK
187707. BNA_CQ_EF_HDS_HEADER
187708. BNA_CQ_EF_IPV4
187709. BNA_CQ_EF_IPV6
187710. BNA_CQ_EF_IP_OPTIONS
187711. BNA_CQ_EF_L3_CKSUM_OK
187712. BNA_CQ_EF_L4_CKSUM_OK
187713. BNA_CQ_EF_LOCAL
187714. BNA_CQ_EF_MAC_ERROR
187715. BNA_CQ_EF_MCAST
187716. BNA_CQ_EF_MCAST_MATCH
187717. BNA_CQ_EF_REMOTE
187718. BNA_CQ_EF_RSS
187719. BNA_CQ_EF_RSVD1
187720. BNA_CQ_EF_RSVD2
187721. BNA_CQ_EF_TCP
187722. BNA_CQ_EF_TOO_LONG
187723. BNA_CQ_EF_UDP
187724. BNA_CQ_EF_VLAN
187725. BNA_DBG_FWTRC_LEN
187726. BNA_DOORBELL_IB_INT_ACK
187727. BNA_DOORBELL_IB_INT_DISABLE
187728. BNA_DOORBELL_Q_PRD_IDX
187729. BNA_DOORBELL_Q_STOP
187730. BNA_ENET_F_ENABLED
187731. BNA_ENET_F_IOCETH_READY
187732. BNA_ENET_F_MTU_CHANGED
187733. BNA_ENET_F_PAUSE_CHANGED
187734. BNA_ENET_T_LOOPBACK_EXTERNAL
187735. BNA_ENET_T_LOOPBACK_INTERNAL
187736. BNA_ENET_T_REGULAR
187737. BNA_ETHPORT_F_ADMIN_UP
187738. BNA_ETHPORT_F_PORT_ENABLED
187739. BNA_ETHPORT_F_RX_STARTED
187740. BNA_GET_DMA_ADDR
187741. BNA_GET_RXQS
187742. BNA_HARD_CLEANUP
187743. BNA_IB_MAX_ACK_EVENTS
187744. BNA_INTR_T_INTX
187745. BNA_INTR_T_MSIX
187746. BNA_IS_ERR_INTR
187747. BNA_IS_HALT_INTR
187748. BNA_IS_INTX_DATA_INTR
187749. BNA_IS_MBOX_ERR_INTR
187750. BNA_IS_MBOX_INTR
187751. BNA_LARGE_PKT_SIZE
187752. BNA_LINK_DOWN
187753. BNA_LINK_UP
187754. BNA_LOAD_T_HIGH_1
187755. BNA_LOAD_T_HIGH_2
187756. BNA_LOAD_T_HIGH_3
187757. BNA_LOAD_T_HIGH_4
187758. BNA_LOAD_T_LOW_1
187759. BNA_LOAD_T_LOW_2
187760. BNA_LOAD_T_LOW_3
187761. BNA_LOAD_T_LOW_4
187762. BNA_LOAD_T_MAX
187763. BNA_MAX_NAME_SIZE
187764. BNA_MEM_T_DMA
187765. BNA_MEM_T_KVA
187766. BNA_MOD_F_INIT_DONE
187767. BNA_MOD_RES_MEM_T_MCHANDLE_ARRAY
187768. BNA_MOD_RES_MEM_T_MCMAC_ARRAY
187769. BNA_MOD_RES_MEM_T_RXP_ARRAY
187770. BNA_MOD_RES_MEM_T_RXQ_ARRAY
187771. BNA_MOD_RES_MEM_T_RX_ARRAY
187772. BNA_MOD_RES_MEM_T_TXQ_ARRAY
187773. BNA_MOD_RES_MEM_T_TX_ARRAY
187774. BNA_MOD_RES_MEM_T_UCMAC_ARRAY
187775. BNA_MOD_RES_T_MAX
187776. BNA_PCI_REG_CT_ADDRSZ
187777. BNA_PKT_RATE_10K
187778. BNA_PKT_RATE_20K
187779. BNA_PKT_RATE_30K
187780. BNA_PKT_RATE_40K
187781. BNA_PKT_RATE_50K
187782. BNA_PKT_RATE_60K
187783. BNA_PKT_RATE_70K
187784. BNA_PKT_RATE_80K
187785. BNA_QE_FREE_CNT
187786. BNA_QE_INDX_ADD
187787. BNA_QE_INDX_INC
187788. BNA_QE_IN_USE_CNT
187789. BNA_Q_INDEX_CHANGE
187790. BNA_Q_NAME_SIZE
187791. BNA_RES_MEM_T_ATTR
187792. BNA_RES_MEM_T_COM
187793. BNA_RES_MEM_T_FWTRC
187794. BNA_RES_MEM_T_STATS
187795. BNA_RES_T_INTR
187796. BNA_RES_T_MAX
187797. BNA_RES_T_MEM
187798. BNA_RSS_F_CFG_PENDING
187799. BNA_RSS_F_RIT_PENDING
187800. BNA_RSS_F_STATUS_PENDING
187801. BNA_RXMODE_ALLMULTI
187802. BNA_RXMODE_DEFAULT
187803. BNA_RXMODE_PROMISC
187804. BNA_RXP_HDS
187805. BNA_RXP_SINGLE
187806. BNA_RXP_SLR
187807. BNA_RX_F_ENABLED
187808. BNA_RX_F_ENET_STARTED
187809. BNA_RX_MOD_F_ENET_LOOPBACK
187810. BNA_RX_MOD_F_ENET_STARTED
187811. BNA_RX_RES_MEM_T_CCB
187812. BNA_RX_RES_MEM_T_CQPT
187813. BNA_RX_RES_MEM_T_CQPT_PAGE
187814. BNA_RX_RES_MEM_T_CSWQPT
187815. BNA_RX_RES_MEM_T_DPAGE
187816. BNA_RX_RES_MEM_T_DQPT
187817. BNA_RX_RES_MEM_T_DSWQPT
187818. BNA_RX_RES_MEM_T_HPAGE
187819. BNA_RX_RES_MEM_T_HQPT
187820. BNA_RX_RES_MEM_T_HSWQPT
187821. BNA_RX_RES_MEM_T_IBIDX
187822. BNA_RX_RES_MEM_T_RCB
187823. BNA_RX_RES_MEM_T_RIT
187824. BNA_RX_RES_MEM_T_UNMAPDQ
187825. BNA_RX_RES_MEM_T_UNMAPHQ
187826. BNA_RX_RES_T_INTR
187827. BNA_RX_RES_T_MAX
187828. BNA_RX_T_LOOPBACK
187829. BNA_RX_T_REGULAR
187830. BNA_SET_DMA_ADDR
187831. BNA_SOFT_CLEANUP
187832. BNA_STATUS_T_DISABLED
187833. BNA_STATUS_T_ENABLED
187834. BNA_TXQ_WI_CF_FCOE_CRC
187835. BNA_TXQ_WI_CF_INS_PRIO
187836. BNA_TXQ_WI_CF_INS_VLAN
187837. BNA_TXQ_WI_CF_IPID_MODE
187838. BNA_TXQ_WI_CF_IP_CKSUM
187839. BNA_TXQ_WI_CF_TCP_CKSUM
187840. BNA_TXQ_WI_CF_UDP_CKSUM
187841. BNA_TXQ_WI_EXTENSION
187842. BNA_TXQ_WI_L4_HDR_N_OFFSET
187843. BNA_TXQ_WI_NEEDED
187844. BNA_TXQ_WI_SEND
187845. BNA_TXQ_WI_SEND_LSO
187846. BNA_TX_F_BW_UPDATED
187847. BNA_TX_F_ENABLED
187848. BNA_TX_F_ENET_STARTED
187849. BNA_TX_MOD_F_ENET_LOOPBACK
187850. BNA_TX_MOD_F_ENET_STARTED
187851. BNA_TX_RES_INTR_T_TXCMPL
187852. BNA_TX_RES_MEM_T_IBIDX
187853. BNA_TX_RES_MEM_T_PAGE
187854. BNA_TX_RES_MEM_T_QPT
187855. BNA_TX_RES_MEM_T_SWQPT
187856. BNA_TX_RES_MEM_T_TCB
187857. BNA_TX_RES_MEM_T_UNMAPQ
187858. BNA_TX_RES_T_MAX
187859. BNA_TX_T_LOOPBACK
187860. BNA_TX_T_REGULAR
187861. BNA_UPDATE_PKT_CNT
187862. BNB_INTF_DET_ON
187863. BNB_INTF_TH_CFG
187864. BNC
187865. BNC_AUI
187866. BNC_AUI_SUSPECT
187867. BNC_CLOCK_4020_BITS
187868. BNC_SUSPECT
187869. BNC_TRIG_THRESHOLD_0V_BIT
187870. BNDF_ON_OFF
187871. BND_HSYNC2VSYNC
187872. BND_MASK
187873. BNE
187874. BNEPCONNADD
187875. BNEPCONNDEL
187876. BNEPGETCONNINFO
187877. BNEPGETCONNLIST
187878. BNEPGETSUPPFEAT
187879. BNEP_BASE_UUID
187880. BNEP_CMD_NOT_UNDERSTOOD
187881. BNEP_COMPRESSED
187882. BNEP_COMPRESSED_DST_ONLY
187883. BNEP_COMPRESSED_SRC_ONLY
187884. BNEP_CONNECT_TO
187885. BNEP_CONN_INVALID_DST
187886. BNEP_CONN_INVALID_SRC
187887. BNEP_CONN_INVALID_SVC
187888. BNEP_CONN_NOT_ALLOWED
187889. BNEP_CONTROL
187890. BNEP_EXT_CONTROL
187891. BNEP_EXT_HEADER
187892. BNEP_FILTER_DENIED_SECURITY
187893. BNEP_FILTER_INVALID_MCADDR
187894. BNEP_FILTER_INVALID_RANGE
187895. BNEP_FILTER_LIMIT_REACHED
187896. BNEP_FILTER_MULTI_ADDR_RSP
187897. BNEP_FILTER_MULTI_ADDR_SET
187898. BNEP_FILTER_NET_TYPE_RSP
187899. BNEP_FILTER_NET_TYPE_SET
187900. BNEP_FILTER_TO
187901. BNEP_FILTER_UNSUPPORTED_REQ
187902. BNEP_FLUSH_TO
187903. BNEP_GENERAL
187904. BNEP_MAX_MULTICAST_FILTERS
187905. BNEP_MAX_PROTO_FILTERS
187906. BNEP_MTU
187907. BNEP_PSM
187908. BNEP_SETUP_CONN_REQ
187909. BNEP_SETUP_CONN_RSP
187910. BNEP_SETUP_RESPONSE
187911. BNEP_SETUP_RSP_SENT
187912. BNEP_SUCCESS
187913. BNEP_SVC_GN
187914. BNEP_SVC_NAP
187915. BNEP_SVC_PANU
187916. BNEP_TX_QUEUE_LEN
187917. BNEP_TYPE_MASK
187918. BNEP_UUID128
187919. BNEP_UUID16
187920. BNEP_UUID32
187921. BNEZAD
187922. BNOISE_EN_PWDB
187923. BNOISE_LVL_TOP_SET
187924. BNSS
187925. BNUMOFCCKTX
187926. BNUMOFOFDMTX
187927. BNUM_OFSTF
187928. BNX2FC_ABTS
187929. BNX2FC_BD_SPLIT_SZ
187930. BNX2FC_CLEANUP
187931. BNX2FC_CNIC_REGISTERED
187932. BNX2FC_CONFQ_WQE_SIZE
187933. BNX2FC_CQ_WQES_MAX
187934. BNX2FC_CQ_WQE_SIZE
187935. BNX2FC_CREATE_LINK_DOWN
187936. BNX2FC_CREATE_LINK_UP
187937. BNX2FC_CTLR_INIT_DONE
187938. BNX2FC_ELS
187939. BNX2FC_ELS_DBG
187940. BNX2FC_ELS_MAX_SQES
187941. BNX2FC_FCOE_MAC_METHOD_FCF_MAP
187942. BNX2FC_FCOE_MAC_METHOD_FCOE_SET_MAC
187943. BNX2FC_FCOE_MAC_METHOD_GRANGED_MAC
187944. BNX2FC_FLAG_ABTS_DONE
187945. BNX2FC_FLAG_CMD_LOST
187946. BNX2FC_FLAG_CTX_ALLOC_FAILURE
187947. BNX2FC_FLAG_DESTROYED
187948. BNX2FC_FLAG_DESTROY_CMPL
187949. BNX2FC_FLAG_DISABLED
187950. BNX2FC_FLAG_DISABLE_FAILED
187951. BNX2FC_FLAG_EH_ABORT
187952. BNX2FC_FLAG_ELS_DONE
187953. BNX2FC_FLAG_ELS_TIMEOUT
187954. BNX2FC_FLAG_ENABLED
187955. BNX2FC_FLAG_FW_INIT_DONE
187956. BNX2FC_FLAG_IO_CLEANUP
187957. BNX2FC_FLAG_IO_COMPL
187958. BNX2FC_FLAG_ISSUE_ABTS
187959. BNX2FC_FLAG_ISSUE_CLEANUP_REQ
187960. BNX2FC_FLAG_ISSUE_RRQ
187961. BNX2FC_FLAG_OFFLOADED
187962. BNX2FC_FLAG_OFLD_REQ_CMPL
187963. BNX2FC_FLAG_RETIRE_OXID
187964. BNX2FC_FLAG_SESSION_READY
187965. BNX2FC_FLAG_SRR_SENT
187966. BNX2FC_FLAG_TM_COMPL
187967. BNX2FC_FLAG_TM_TIMEOUT
187968. BNX2FC_FLAG_UPLD_REQ_COMPL
187969. BNX2FC_FW_MAX_BDS_PER_CMD
187970. BNX2FC_FW_TIMEOUT
187971. BNX2FC_HASH_TBL_CHUNK_SIZE
187972. BNX2FC_HBA_DBG
187973. BNX2FC_INIT_POLL_TIME
187974. BNX2FC_IO_DBG
187975. BNX2FC_IO_TIMEOUT
187976. BNX2FC_MAX_BDS_PER_CMD
187977. BNX2FC_MAX_BD_LEN
187978. BNX2FC_MAX_CMD_LEN
187979. BNX2FC_MAX_FCP_TGT
187980. BNX2FC_MAX_LUN
187981. BNX2FC_MAX_NPIV
187982. BNX2FC_MAX_PAYLOAD
187983. BNX2FC_MAX_QUEUE_DEPTH
187984. BNX2FC_MAX_RETRY_CNT
187985. BNX2FC_MAX_ROWS_IN_HASH_TBL
187986. BNX2FC_MAX_RPORT_RETRY_CNT
187987. BNX2FC_MAX_SEQS
187988. BNX2FC_MFS
187989. BNX2FC_MINI_JUMBO_MTU
187990. BNX2FC_MIN_PAYLOAD
187991. BNX2FC_MIN_QUEUE_DEPTH
187992. BNX2FC_MIN_XID
187993. BNX2FC_MISC_DBG
187994. BNX2FC_NAME
187995. BNX2FC_NUM_ERR_BITS
187996. BNX2FC_NUM_MAX_SESS
187997. BNX2FC_NUM_MAX_SESS_LOG
187998. BNX2FC_READ
187999. BNX2FC_RELOGIN_WAIT_CNT
188000. BNX2FC_RELOGIN_WAIT_TIME
188001. BNX2FC_RNID_HBA
188002. BNX2FC_RQ_BUF_LOG_SZ
188003. BNX2FC_RQ_BUF_SZ
188004. BNX2FC_RQ_WQES_MAX
188005. BNX2FC_RQ_WQE_SIZE
188006. BNX2FC_SCSI_CMD
188007. BNX2FC_SCSI_MAX_SQES
188008. BNX2FC_SEQ_CLEANUP
188009. BNX2FC_SQ_WQES_MAX
188010. BNX2FC_SQ_WQE_SIZE
188011. BNX2FC_STATS
188012. BNX2FC_TASKS_PER_PAGE
188013. BNX2FC_TASK_MGMT_CMD
188014. BNX2FC_TASK_SIZE
188015. BNX2FC_TGT_DBG
188016. BNX2FC_TM_MAX_SQES
188017. BNX2FC_TM_TIMEOUT
188018. BNX2FC_VERSION
188019. BNX2FC_WAIT_CNT
188020. BNX2FC_WRITE
188021. BNX2FC_XFERQ_WQE_SIZE
188022. BNX2I_570X_CQ_WQES_MAX
188023. BNX2I_570X_PAGE_SIZE_DEFAULT
188024. BNX2I_570X_SQ_WQES_DEFAULT
188025. BNX2I_570X_SQ_WQES_MAX
188026. BNX2I_570x_QUE_DB_SIZE
188027. BNX2I_5770X_CQ_WQES_MAX
188028. BNX2I_5770X_SQ_WQES_DEFAULT
188029. BNX2I_5770X_SQ_WQES_MAX
188030. BNX2I_5771x_QUE_DB_SIZE
188031. BNX2I_CCELLS_DEFAULT
188032. BNX2I_CCELLS_MAX
188033. BNX2I_CCELLS_MIN
188034. BNX2I_CID_RESERVED
188035. BNX2I_CNIC_REGISTERED
188036. BNX2I_CONN_CTX_BUF_SIZE
188037. BNX2I_CQE_SIZE
188038. BNX2I_ERR_DATA_SEG_LEN_NOT_ZERO
188039. BNX2I_ERR_DESIRED_DATA_TRNS_LEN_0
188040. BNX2I_ERR_DESIRED_DATA_TRNS_LEN_1
188041. BNX2I_INIT_POLL_TIME
188042. BNX2I_MAX_ADAPTERS
188043. BNX2I_MAX_MTU_SUPPORTED
188044. BNX2I_MQ_BIN_MODE
188045. BNX2I_MQ_KERNEL_BYPASS_MODE
188046. BNX2I_MQ_KERNEL_MODE
188047. BNX2I_NX2_DEV_5706
188048. BNX2I_NX2_DEV_5708
188049. BNX2I_NX2_DEV_5709
188050. BNX2I_NX2_DEV_57710
188051. BNX2I_RESERVED_SLOW_PATH_CMD_SLOTS
188052. BNX2I_RQ_WQES_DEFAULT
188053. BNX2I_RQ_WQES_MAX
188054. BNX2I_RQ_WQES_MIN
188055. BNX2I_RQ_WQE_SIZE
188056. BNX2I_SQ_WQES_MIN
188057. BNX2I_SQ_WQE_SIZE
188058. BNX2X_1st_NON_L2_ETH_CID
188059. BNX2X_57711_SET_MC_FILTER
188060. BNX2X_ACCEPT_ALL_MULTICAST
188061. BNX2X_ACCEPT_ALL_UNICAST
188062. BNX2X_ACCEPT_ANY_VLAN
188063. BNX2X_ACCEPT_BROADCAST
188064. BNX2X_ACCEPT_MULTICAST
188065. BNX2X_ACCEPT_UNICAST
188066. BNX2X_ACCEPT_UNMATCHED
188067. BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
188068. BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
188069. BNX2X_ALLOC_AND_SET
188070. BNX2X_BC_VER
188071. BNX2X_BTR
188072. BNX2X_CAM_SIZE_EMUL
188073. BNX2X_CHIP_E1H_OFST
188074. BNX2X_CHIP_E1_OFST
188075. BNX2X_CHIP_E2_OFST
188076. BNX2X_CHIP_E3B0_OFST
188077. BNX2X_CHIP_E3_OFST
188078. BNX2X_CHIP_IS_E2_PLUS
188079. BNX2X_CHIP_MASK_ALL
188080. BNX2X_CHIP_MASK_E1
188081. BNX2X_CHIP_MASK_E1H
188082. BNX2X_CHIP_MASK_E1X
188083. BNX2X_CHIP_MASK_E2
188084. BNX2X_CHIP_MASK_E3
188085. BNX2X_CHIP_MASK_E3B0
188086. BNX2X_CHIP_MAX_OFST
188087. BNX2X_CIDS_PER_VF
188088. BNX2X_CL_QZONE_ID
188089. BNX2X_CMN_H
188090. BNX2X_CNIC_START_ETH_CID
188091. BNX2X_CONTEXT_MEM_SIZE
188092. BNX2X_DBG_ERR
188093. BNX2X_DB_MIN_SHIFT
188094. BNX2X_DB_SHIFT
188095. BNX2X_DCBX_CAPS
188096. BNX2X_DCBX_CONFIG_INV_VALUE
188097. BNX2X_DCBX_ENABLED_INVALID
188098. BNX2X_DCBX_ENABLED_OFF
188099. BNX2X_DCBX_ENABLED_ON_NEG_OFF
188100. BNX2X_DCBX_ENABLED_ON_NEG_ON
188101. BNX2X_DCBX_OVERWRITE_SETTINGS_DISABLE
188102. BNX2X_DCBX_OVERWRITE_SETTINGS_ENABLE
188103. BNX2X_DCBX_OVERWRITE_SETTINGS_INVALID
188104. BNX2X_DCBX_STATE_NEG_RECEIVED
188105. BNX2X_DCBX_STATE_TX_PAUSED
188106. BNX2X_DCBX_STATE_TX_RELEASED
188107. BNX2X_DCBX_STRICT_COS_HIGHEST
188108. BNX2X_DCBX_STRICT_COS_NEXT_LOWER_PRI
188109. BNX2X_DCBX_STRICT_INVALID
188110. BNX2X_DCB_H
188111. BNX2X_DCB_STATE_OFF
188112. BNX2X_DCB_STATE_ON
188113. BNX2X_DEF_SB_ATT_IDX
188114. BNX2X_DEF_SB_ID
188115. BNX2X_DEF_SB_IDX
188116. BNX2X_DEV_INFO
188117. BNX2X_DONT_CONSUME_CAM_CREDIT
188118. BNX2X_DONT_CONSUME_CAM_CREDIT_DEST
188119. BNX2X_DOORBELL_PCI_BAR
188120. BNX2X_DUMP_H
188121. BNX2X_DUMP_VERSION
188122. BNX2X_E3B0_PORT1_COS_OFFSET
188123. BNX2X_EQ_INDEX
188124. BNX2X_ERR
188125. BNX2X_ERROR
188126. BNX2X_ETH_MAC
188127. BNX2X_ETH_Q
188128. BNX2X_EXT_LOOPBACK
188129. BNX2X_EXT_LOOPBACK_FAILED
188130. BNX2X_FCOE_CID
188131. BNX2X_FCOE_ETH_CID
188132. BNX2X_FCOE_ETH_CL_ID_IDX
188133. BNX2X_FCOE_L2_RX_INDEX
188134. BNX2X_FCOE_L2_TX_INDEX
188135. BNX2X_FCOE_L5_CID_BASE
188136. BNX2X_FCOE_MINI_JUMBO_MTU
188137. BNX2X_FCOE_NUM_CONNECTIONS
188138. BNX2X_FCOE_Q
188139. BNX2X_FCOE_QUERY_IDX
188140. BNX2X_FILTER_FCOE_ETH_START_SCHED
188141. BNX2X_FILTER_FCOE_ETH_STOP_SCHED
188142. BNX2X_FILTER_ISCSI_ETH_START_SCHED
188143. BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
188144. BNX2X_FILTER_MAC_PENDING
188145. BNX2X_FILTER_MCAST_PENDING
188146. BNX2X_FILTER_MCAST_SCHED
188147. BNX2X_FILTER_RSS_CONF_PENDING
188148. BNX2X_FILTER_RX_MODE_PENDING
188149. BNX2X_FILTER_RX_MODE_SCHED
188150. BNX2X_FILTER_VLAN_MAC_PENDING
188151. BNX2X_FILTER_VLAN_PENDING
188152. BNX2X_FIRST_QUEUE_QUERY_IDX
188153. BNX2X_FIRST_VF_CID
188154. BNX2X_FLOW_CTRL_AUTO
188155. BNX2X_FLOW_CTRL_BOTH
188156. BNX2X_FLOW_CTRL_NONE
188157. BNX2X_FLOW_CTRL_RX
188158. BNX2X_FLOW_CTRL_TX
188159. BNX2X_FREE
188160. BNX2X_FW_DEFS_H
188161. BNX2X_FW_DMAE_C
188162. BNX2X_FW_RX_ALIGN_END
188163. BNX2X_FW_RX_ALIGN_START
188164. BNX2X_F_CMD_AFEX_UPDATE
188165. BNX2X_F_CMD_AFEX_VIFLISTS
188166. BNX2X_F_CMD_HW_INIT
188167. BNX2X_F_CMD_HW_RESET
188168. BNX2X_F_CMD_MAX
188169. BNX2X_F_CMD_SET_TIMESYNC
188170. BNX2X_F_CMD_START
188171. BNX2X_F_CMD_STOP
188172. BNX2X_F_CMD_SWITCH_UPDATE
188173. BNX2X_F_CMD_TX_START
188174. BNX2X_F_CMD_TX_STOP
188175. BNX2X_F_STATE_INITIALIZED
188176. BNX2X_F_STATE_MAX
188177. BNX2X_F_STATE_RESET
188178. BNX2X_F_STATE_STARTED
188179. BNX2X_F_STATE_TX_STOPPED
188180. BNX2X_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG
188181. BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG
188182. BNX2X_F_UPDATE_TUNNEL_CFG_CHNG
188183. BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE
188184. BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE
188185. BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN
188186. BNX2X_F_UPDATE_TUNNEL_INNER_RSS
188187. BNX2X_F_UPDATE_TX_SWITCH_SUSPEND
188188. BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG
188189. BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG
188190. BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG
188191. BNX2X_GLOBAL_RESET_BIT
188192. BNX2X_GRC_RSV
188193. BNX2X_GRC_TIMEOUT
188194. BNX2X_H
188195. BNX2X_HAS_MF_EXT_PROTOCOL_FCOE
188196. BNX2X_HAS_SECOND_PBD
188197. BNX2X_HSI_H
188198. BNX2X_HW_CID
188199. BNX2X_IGU_STAS_MSG_PF_CNT
188200. BNX2X_IGU_STAS_MSG_VF_CNT
188201. BNX2X_ILT_FREE
188202. BNX2X_ILT_ZALLOC
188203. BNX2X_INIT_FILE_HDR_H
188204. BNX2X_INIT_H
188205. BNX2X_INIT_OPS_H
188206. BNX2X_INT_MODE_INTX
188207. BNX2X_INT_MODE_MSI
188208. BNX2X_INT_MODE_MSIX
188209. BNX2X_IOV_HANDLE_FLR
188210. BNX2X_IOV_HANDLE_VF_MSG
188211. BNX2X_ISCSI_ACK_Q
188212. BNX2X_ISCSI_ETH_CID
188213. BNX2X_ISCSI_ETH_CL_ID_IDX
188214. BNX2X_ISCSI_ETH_MAC
188215. BNX2X_ISCSI_GLB_BUF_SIZE
188216. BNX2X_ISCSI_HQ_BD_SIZE
188217. BNX2X_ISCSI_MAX_PENDING_R2TS
188218. BNX2X_ISCSI_NUM_CONNECTIONS
188219. BNX2X_ISCSI_PBL_NOT_CACHED
188220. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED
188221. BNX2X_ISCSI_Q
188222. BNX2X_ISCSI_R2TQE_SIZE
188223. BNX2X_ISCSI_START_CID
188224. BNX2X_ISCSI_TASK_CONTEXT_SIZE
188225. BNX2X_IS_CQE_COMPLETED
188226. BNX2X_IS_ETS_ENABLED
188227. BNX2X_IS_MF_EXT_PROTOCOL_FCOE
188228. BNX2X_IS_MF_EXT_PROTOCOL_ISCSI
188229. BNX2X_IS_MF_SD_PROTOCOL_FCOE
188230. BNX2X_IS_MF_SD_PROTOCOL_ISCSI
188231. BNX2X_KWQ_DATA
188232. BNX2X_KWQ_DATA_IDX
188233. BNX2X_KWQ_DATA_PG
188234. BNX2X_L2_CID_COUNT
188235. BNX2X_L2_MAX_CID
188236. BNX2X_LINK_H
188237. BNX2X_LINK_REPORT_FD
188238. BNX2X_LINK_REPORT_LINK_DOWN
188239. BNX2X_LINK_REPORT_RX_FC_ON
188240. BNX2X_LINK_REPORT_TX_FC_ON
188241. BNX2X_LLH_CAM_ETH_LINE
188242. BNX2X_LLH_CAM_ISCSI_ETH_LINE
188243. BNX2X_LLH_CAM_MAX_PF_LINE
188244. BNX2X_LOOPBACK_FAILED
188245. BNX2X_MAC_LOOPBACK
188246. BNX2X_MAC_LOOPBACK_FAILED
188247. BNX2X_MAX_CNIC_ETH_CL_ID_IDX
188248. BNX2X_MAX_COALESCE_TOUT
188249. BNX2X_MAX_COS_SUPPORT
188250. BNX2X_MAX_CQS
188251. BNX2X_MAX_EMUL_MULTI
188252. BNX2X_MAX_FCOE_INIT_CONN_MASK
188253. BNX2X_MAX_FCOE_INIT_CONN_SHIFT
188254. BNX2X_MAX_FCOE_TRGT_CONN_MASK
188255. BNX2X_MAX_FCOE_TRGT_CONN_SHIFT
188256. BNX2X_MAX_ISCSI_INIT_CONN_MASK
188257. BNX2X_MAX_ISCSI_INIT_CONN_SHIFT
188258. BNX2X_MAX_ISCSI_TRGT_CONN_MASK
188259. BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT
188260. BNX2X_MAX_MULTICAST
188261. BNX2X_MAX_NUM_OF_VFS
188262. BNX2X_MAX_NUM_VF_QUEUES
188263. BNX2X_MAX_PHC_DRIFT
188264. BNX2X_MAX_PRIORITY
188265. BNX2X_MAX_QUEUES
188266. BNX2X_MAX_RCQ_DESC_CNT
188267. BNX2X_MAX_RSS_COUNT
188268. BNX2X_MAX_RX_DESC_CNT
188269. BNX2X_MCAST_BINS_NUM
188270. BNX2X_MCAST_CMD_ADD
188271. BNX2X_MCAST_CMD_CONT
188272. BNX2X_MCAST_CMD_DEL
188273. BNX2X_MCAST_CMD_RESTORE
188274. BNX2X_MCAST_CMD_SET
188275. BNX2X_MCAST_CMD_SET_ADD
188276. BNX2X_MCAST_CMD_SET_DEL
188277. BNX2X_MCAST_VEC_SZ
188278. BNX2X_MCP_ASSERT
188279. BNX2X_MC_ASSERT_BITS
188280. BNX2X_MFW_REQ_H
188281. BNX2X_MF_CFG_ADDR
188282. BNX2X_MF_EXT_PROT
188283. BNX2X_MF_EXT_PROTOCOL_MASK
188284. BNX2X_MF_SD_PROTOCOL
188285. BNX2X_MIN_MSIX_VEC_CNT
188286. BNX2X_MSG_DCB
188287. BNX2X_MSG_DMAE
188288. BNX2X_MSG_ETHTOOL
188289. BNX2X_MSG_FP
188290. BNX2X_MSG_IDLE
188291. BNX2X_MSG_IOV
188292. BNX2X_MSG_MCP
188293. BNX2X_MSG_NVM
188294. BNX2X_MSG_OFF
188295. BNX2X_MSG_PTP
188296. BNX2X_MSG_SP
188297. BNX2X_MSG_STATS
188298. BNX2X_MULTI_TX_COS
188299. BNX2X_MULTI_TX_COS_E1X
188300. BNX2X_MULTI_TX_COS_E2_E3A0
188301. BNX2X_MULTI_TX_COS_E3B0
188302. BNX2X_NETQ_ETH_MAC
188303. BNX2X_NEXT_KCQE
188304. BNX2X_NEXT_RCQE
188305. BNX2X_NR_VIRTFN
188306. BNX2X_NUM_ETH_QUEUES
188307. BNX2X_NUM_NON_CNIC_QUEUES
188308. BNX2X_NUM_QUEUES
188309. BNX2X_NUM_Q_STATS
188310. BNX2X_NUM_RX_QUEUES
188311. BNX2X_NUM_STATS
188312. BNX2X_NUM_TESTS
188313. BNX2X_NUM_TESTS_MF
188314. BNX2X_NUM_TESTS_SF
188315. BNX2X_NUM_TSO_WIN_SUB_BDS
188316. BNX2X_NUM_VXLAN_TSO_WIN_SUB_BDS
188317. BNX2X_NVRAM_1MB_SIZE
188318. BNX2X_NVRAM_PAGE_SIZE
188319. BNX2X_NVRAM_TIMEOUT_COUNT
188320. BNX2X_OBJ_TYPE_RX
188321. BNX2X_OBJ_TYPE_RX_TX
188322. BNX2X_OBJ_TYPE_TX
188323. BNX2X_P2P_DETECT_PARAM_MASK
188324. BNX2X_P2P_DETECT_RULE_MASK
188325. BNX2X_PATH0_LOAD_CNT_MASK
188326. BNX2X_PATH0_LOAD_CNT_SHIFT
188327. BNX2X_PATH0_RST_IN_PROG_BIT
188328. BNX2X_PATH1_LOAD_CNT_MASK
188329. BNX2X_PATH1_LOAD_CNT_SHIFT
188330. BNX2X_PATH1_RST_IN_PROG_BIT
188331. BNX2X_PCI_ALLOC
188332. BNX2X_PCI_FALLOC
188333. BNX2X_PCI_FREE
188334. BNX2X_PF_QUERY_IDX
188335. BNX2X_PF_Q_NUM
188336. BNX2X_PHY_LOOPBACK
188337. BNX2X_PHY_LOOPBACK_FAILED
188338. BNX2X_PMF_LINK_ASSERT
188339. BNX2X_POOL_VEC_SIZE
188340. BNX2X_PORT2_MODE_NUM_VNICS
188341. BNX2X_PORT4_MODE_NUM_VNICS
188342. BNX2X_PORT_QUERY_IDX
188343. BNX2X_PREV_UNDI_BD
188344. BNX2X_PREV_UNDI_PROD
188345. BNX2X_PREV_UNDI_PROD_ADDR
188346. BNX2X_PREV_UNDI_PROD_ADDR_H
188347. BNX2X_PREV_UNDI_RCQ
188348. BNX2X_PREV_WAIT_NEEDED
188349. BNX2X_PRIMARY_CID_INDEX
188350. BNX2X_PRI_FLAG_FCOE
188351. BNX2X_PRI_FLAG_ISCSI
188352. BNX2X_PRI_FLAG_LEN
188353. BNX2X_PRI_FLAG_STORAGE
188354. BNX2X_PRS_FLAG_OVERETH_IPV4
188355. BNX2X_PTP_TX_ON_PARAM_MASK
188356. BNX2X_PTP_TX_ON_RULE_MASK
188357. BNX2X_PTP_TX_TIMEOUT
188358. BNX2X_PTP_V1_L4_PARAM_MASK
188359. BNX2X_PTP_V1_L4_RULE_MASK
188360. BNX2X_PTP_V2_L2_PARAM_MASK
188361. BNX2X_PTP_V2_L2_RULE_MASK
188362. BNX2X_PTP_V2_L4_PARAM_MASK
188363. BNX2X_PTP_V2_L4_RULE_MASK
188364. BNX2X_PTP_V2_PARAM_MASK
188365. BNX2X_PTP_V2_RULE_MASK
188366. BNX2X_PXP_DRAM_ALIGN
188367. BNX2X_Q_CMDQ_REG_ADDR
188368. BNX2X_Q_CMD_ACTIVATE
188369. BNX2X_Q_CMD_CFC_DEL
188370. BNX2X_Q_CMD_DEACTIVATE
188371. BNX2X_Q_CMD_EMPTY
188372. BNX2X_Q_CMD_HALT
188373. BNX2X_Q_CMD_INIT
188374. BNX2X_Q_CMD_MAX
188375. BNX2X_Q_CMD_SETUP
188376. BNX2X_Q_CMD_SETUP_TX_ONLY
188377. BNX2X_Q_CMD_TERMINATE
188378. BNX2X_Q_CMD_UPDATE
188379. BNX2X_Q_CMD_UPDATE_TPA
188380. BNX2X_Q_FLG_ACTIVE
188381. BNX2X_Q_FLG_ANTI_SPOOF
188382. BNX2X_Q_FLG_COS
188383. BNX2X_Q_FLG_DEF_VLAN
188384. BNX2X_Q_FLG_DHC
188385. BNX2X_Q_FLG_FCOE
188386. BNX2X_Q_FLG_FORCE_DEFAULT_PRI
188387. BNX2X_Q_FLG_HC
188388. BNX2X_Q_FLG_HC_EN
188389. BNX2X_Q_FLG_LEADING_RSS
188390. BNX2X_Q_FLG_MCAST
188391. BNX2X_Q_FLG_OV
188392. BNX2X_Q_FLG_PCSUM_ON_PKT
188393. BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN
188394. BNX2X_Q_FLG_SILENT_VLAN_REM
188395. BNX2X_Q_FLG_STATS
188396. BNX2X_Q_FLG_TPA
188397. BNX2X_Q_FLG_TPA_GRO
188398. BNX2X_Q_FLG_TPA_IPV6
188399. BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
188400. BNX2X_Q_FLG_TX_SEC
188401. BNX2X_Q_FLG_TX_SWITCH
188402. BNX2X_Q_FLG_VLAN
188403. BNX2X_Q_FLG_ZERO_STATS
188404. BNX2X_Q_LOGICAL_STATE_ACTIVE
188405. BNX2X_Q_LOGICAL_STATE_STOPPED
188406. BNX2X_Q_STATE_ACTIVE
188407. BNX2X_Q_STATE_FLRED
188408. BNX2X_Q_STATE_INACTIVE
188409. BNX2X_Q_STATE_INITIALIZED
188410. BNX2X_Q_STATE_MAX
188411. BNX2X_Q_STATE_MCOS_TERMINATED
188412. BNX2X_Q_STATE_MULTI_COS
188413. BNX2X_Q_STATE_RESET
188414. BNX2X_Q_STATE_STOPPED
188415. BNX2X_Q_STATE_TERMINATED
188416. BNX2X_Q_TYPE_HAS_RX
188417. BNX2X_Q_TYPE_HAS_TX
188418. BNX2X_Q_UPDATE_ACTIVATE
188419. BNX2X_Q_UPDATE_ACTIVATE_CHNG
188420. BNX2X_Q_UPDATE_ANTI_SPOOF
188421. BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG
188422. BNX2X_Q_UPDATE_DEF_VLAN_EN
188423. BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG
188424. BNX2X_Q_UPDATE_IN_VLAN_REM
188425. BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG
188426. BNX2X_Q_UPDATE_OUT_VLAN_REM
188427. BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG
188428. BNX2X_Q_UPDATE_PTP_PKTS
188429. BNX2X_Q_UPDATE_PTP_PKTS_CHNG
188430. BNX2X_Q_UPDATE_SILENT_VLAN_REM
188431. BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG
188432. BNX2X_Q_UPDATE_TX_SWITCHING
188433. BNX2X_Q_UPDATE_TX_SWITCHING_CHNG
188434. BNX2X_Q_VOQ_REG_ADDR
188435. BNX2X_RCQ_DESC_CNT
188436. BNX2X_RECOVERY_DONE
188437. BNX2X_RECOVERY_FAILED
188438. BNX2X_RECOVERY_GLOB_REG
188439. BNX2X_RECOVERY_INIT
188440. BNX2X_RECOVERY_NIC_LOADING
188441. BNX2X_RECOVERY_WAIT
188442. BNX2X_REG_H
188443. BNX2X_RSS_IPV4
188444. BNX2X_RSS_IPV4_TCP
188445. BNX2X_RSS_IPV4_UDP
188446. BNX2X_RSS_IPV4_VXLAN
188447. BNX2X_RSS_IPV6
188448. BNX2X_RSS_IPV6_TCP
188449. BNX2X_RSS_IPV6_UDP
188450. BNX2X_RSS_IPV6_VXLAN
188451. BNX2X_RSS_MODE_DISABLED
188452. BNX2X_RSS_MODE_REGULAR
188453. BNX2X_RSS_SET_SRCH
188454. BNX2X_RSS_TUNN_INNER_HDRS
188455. BNX2X_RX_ALIGN_SHIFT
188456. BNX2X_RX_DESC_CNT
188457. BNX2X_RX_MODE_ALLMULTI
188458. BNX2X_RX_MODE_FCOE_ETH
188459. BNX2X_RX_MODE_ISCSI_ETH
188460. BNX2X_RX_MODE_NONE
188461. BNX2X_RX_MODE_NORMAL
188462. BNX2X_RX_MODE_PROMISC
188463. BNX2X_RX_SB_INDEX
188464. BNX2X_RX_SUM_FIX
188465. BNX2X_SEED_CQE
188466. BNX2X_SHMEM2_ADDR
188467. BNX2X_SHMEM2_HAS
188468. BNX2X_SHMEM_ADDR
188469. BNX2X_SHMEM_MF_BLK_OFFSET
188470. BNX2X_SP_DSB_INDEX
188471. BNX2X_SP_RTNL_AFEX_F_UPDATE
188472. BNX2X_SP_RTNL_CHANGE_UDP_PORT
188473. BNX2X_SP_RTNL_ENABLE_SRIOV
188474. BNX2X_SP_RTNL_FAN_FAILURE
188475. BNX2X_SP_RTNL_GET_DRV_VERSION
188476. BNX2X_SP_RTNL_HYPERVISOR_VLAN
188477. BNX2X_SP_RTNL_RX_MODE
188478. BNX2X_SP_RTNL_SETUP_TC
188479. BNX2X_SP_RTNL_TX_STOP
188480. BNX2X_SP_RTNL_TX_TIMEOUT
188481. BNX2X_SP_RTNL_UPDATE_SVID
188482. BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN
188483. BNX2X_SP_RTNL_VFPF_MCAST
188484. BNX2X_SP_VERBS
188485. BNX2X_SRIOV_H
188486. BNX2X_STATE_CLOSED
188487. BNX2X_STATE_CLOSING_WAIT4_DELETE
188488. BNX2X_STATE_CLOSING_WAIT4_HALT
188489. BNX2X_STATE_DIAG
188490. BNX2X_STATE_ERROR
188491. BNX2X_STATE_OPEN
188492. BNX2X_STATE_OPENING_WAIT4_LOAD
188493. BNX2X_STATE_OPENING_WAIT4_PORT
188494. BNX2X_STATS_H
188495. BNX2X_SWCID_MASK
188496. BNX2X_SWCID_SHIFT
188497. BNX2X_SW_CID
188498. BNX2X_TOE_ACK_Q
188499. BNX2X_TOE_Q
188500. BNX2X_TPA_ERROR
188501. BNX2X_TPA_START
188502. BNX2X_TPA_STOP
188503. BNX2X_TSO_SPLIT_BD
188504. BNX2X_TX_SB_INDEX_BASE
188505. BNX2X_TX_SB_INDEX_COS0
188506. BNX2X_UC_LIST_MAC
188507. BNX2X_UDP_PORT_GENEVE
188508. BNX2X_UDP_PORT_MAX
188509. BNX2X_UDP_PORT_VXLAN
188510. BNX2X_UPDATE_DRV_INFO_IND_COUNT
188511. BNX2X_UPDATE_DRV_INFO_IND_LENGTH
188512. BNX2X_VF_BAR_SIZE
188513. BNX2X_VF_CIDS
188514. BNX2X_VF_CID_WND
188515. BNX2X_VF_FILTER_MAC
188516. BNX2X_VF_FILTER_VLAN
188517. BNX2X_VF_FILTER_VLAN_MAC
188518. BNX2X_VF_ID_INVALID
188519. BNX2X_VF_MAX_QUEUES
188520. BNX2X_VF_MAX_TPA_AGG_QUEUES
188521. BNX2X_VLAN
188522. BNX2X_VLAN_MAC_ADD
188523. BNX2X_VLAN_MAC_CMP_FLAGS
188524. BNX2X_VLAN_MAC_CMP_MASK
188525. BNX2X_VLAN_MAC_DEL
188526. BNX2X_VLAN_MAC_MOVE
188527. BNX2X_VOQ_Q_REG_ADDR
188528. BNX2X_VPD_LEN
188529. BNX2_BC_RESET_TYPE
188530. BNX2_BC_STATE
188531. BNX2_BC_STATE_APPLY_WKARND
188532. BNX2_BC_STATE_BC1_START
188533. BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK
188534. BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE
188535. BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE
188536. BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK
188537. BNX2_BC_STATE_CONDITION
188538. BNX2_BC_STATE_DEBUG_CMD
188539. BNX2_BC_STATE_ERR_BAD_BC2_CRC
188540. BNX2_BC_STATE_ERR_BAD_VERSION
188541. BNX2_BC_STATE_ERR_BC1_LOOP
188542. BNX2_BC_STATE_ERR_DRV_DEAD
188543. BNX2_BC_STATE_ERR_MASK
188544. BNX2_BC_STATE_ERR_NO_RXP
188545. BNX2_BC_STATE_ERR_TOO_MANY_RBUF
188546. BNX2_BC_STATE_ERR_UNKNOWN_CMD
188547. BNX2_BC_STATE_GET_NVM_CFG1
188548. BNX2_BC_STATE_GET_NVM_CFG2
188549. BNX2_BC_STATE_GOING_BC2
188550. BNX2_BC_STATE_GOING_DIAG
188551. BNX2_BC_STATE_INIT_VID
188552. BNX2_BC_STATE_LOAD_BC2
188553. BNX2_BC_STATE_PROG_BAR
188554. BNX2_BC_STATE_RESET_TYPE
188555. BNX2_BC_STATE_RESET_TYPE_DRV_DIAG
188556. BNX2_BC_STATE_RESET_TYPE_DRV_MASK
188557. BNX2_BC_STATE_RESET_TYPE_DRV_RESET
188558. BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN
188559. BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD
188560. BNX2_BC_STATE_RESET_TYPE_DRV_WOL
188561. BNX2_BC_STATE_RESET_TYPE_NONE
188562. BNX2_BC_STATE_RESET_TYPE_PCI
188563. BNX2_BC_STATE_RESET_TYPE_SIG
188564. BNX2_BC_STATE_RESET_TYPE_SIG_MASK
188565. BNX2_BC_STATE_RESET_TYPE_VALUE
188566. BNX2_BC_STATE_RESET_TYPE_VAUX
188567. BNX2_BC_STATE_RT_DRV_CMD
188568. BNX2_BC_STATE_RT_DRV_PULSE
188569. BNX2_BC_STATE_RT_FINAL_INIT
188570. BNX2_BC_STATE_RT_FIOEVTS
188571. BNX2_BC_STATE_RT_GOING_D3
188572. BNX2_BC_STATE_RT_LOW_POWER
188573. BNX2_BC_STATE_RT_OTHER_FW
188574. BNX2_BC_STATE_RT_SET_WOL
188575. BNX2_BC_STATE_RT_WKARND
188576. BNX2_BC_STATE_SIGN
188577. BNX2_BC_STATE_SIGN_MASK
188578. BNX2_CAPABILITY_SIGNATURE_MASK
188579. BNX2_CHIP
188580. BNX2_CHIP_5706
188581. BNX2_CHIP_5708
188582. BNX2_CHIP_5709
188583. BNX2_CHIP_BOND
188584. BNX2_CHIP_BOND_SERDES_BIT
188585. BNX2_CHIP_ID
188586. BNX2_CHIP_ID_5706_A0
188587. BNX2_CHIP_ID_5706_A1
188588. BNX2_CHIP_ID_5706_A2
188589. BNX2_CHIP_ID_5708_A0
188590. BNX2_CHIP_ID_5708_B0
188591. BNX2_CHIP_ID_5708_B1
188592. BNX2_CHIP_ID_5709_A0
188593. BNX2_CHIP_ID_5709_A1
188594. BNX2_CHIP_METAL
188595. BNX2_CHIP_REV
188596. BNX2_CHIP_REV_Ax
188597. BNX2_CHIP_REV_Bx
188598. BNX2_CHIP_REV_Cx
188599. BNX2_COM_CKSUM_ERROR_STATUS
188600. BNX2_COM_CKSUM_ERROR_STATUS_CALCULATED
188601. BNX2_COM_CKSUM_ERROR_STATUS_EXPECTED
188602. BNX2_COM_COMQ
188603. BNX2_COM_COMQ_FTQ_CMD
188604. BNX2_COM_COMQ_FTQ_CMD_ADD_DATA
188605. BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN
188606. BNX2_COM_COMQ_FTQ_CMD_BUSY
188607. BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR
188608. BNX2_COM_COMQ_FTQ_CMD_OFFSET
188609. BNX2_COM_COMQ_FTQ_CMD_POP
188610. BNX2_COM_COMQ_FTQ_CMD_RD_DATA
188611. BNX2_COM_COMQ_FTQ_CMD_SFT_RESET
188612. BNX2_COM_COMQ_FTQ_CMD_WR_TOP
188613. BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0
188614. BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1
188615. BNX2_COM_COMQ_FTQ_CTL
188616. BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH
188617. BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE
188618. BNX2_COM_COMQ_FTQ_CTL_INTERVENE
188619. BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH
188620. BNX2_COM_COMQ_FTQ_CTL_OVERFLOW
188621. BNX2_COM_COMTQ
188622. BNX2_COM_COMTQ_FTQ_CMD
188623. BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA
188624. BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN
188625. BNX2_COM_COMTQ_FTQ_CMD_BUSY
188626. BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR
188627. BNX2_COM_COMTQ_FTQ_CMD_OFFSET
188628. BNX2_COM_COMTQ_FTQ_CMD_POP
188629. BNX2_COM_COMTQ_FTQ_CMD_RD_DATA
188630. BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET
188631. BNX2_COM_COMTQ_FTQ_CMD_WR_TOP
188632. BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0
188633. BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1
188634. BNX2_COM_COMTQ_FTQ_CTL
188635. BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH
188636. BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE
188637. BNX2_COM_COMTQ_FTQ_CTL_INTERVENE
188638. BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH
188639. BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW
188640. BNX2_COM_COMTQ_PFE_PFE_CTL
188641. BNX2_COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT
188642. BNX2_COM_COMTQ_PFE_PFE_CTL_OFFSET
188643. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_COUNT
188644. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE
188645. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0
188646. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_1
188647. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_10
188648. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_11
188649. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_12
188650. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_13
188651. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_14
188652. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_15
188653. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_2
188654. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_3
188655. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_4
188656. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_5
188657. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_6
188658. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_7
188659. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_8
188660. BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_9
188661. BNX2_COM_COMXQ
188662. BNX2_COM_COMXQ_FTQ_CMD
188663. BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA
188664. BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN
188665. BNX2_COM_COMXQ_FTQ_CMD_BUSY
188666. BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR
188667. BNX2_COM_COMXQ_FTQ_CMD_OFFSET
188668. BNX2_COM_COMXQ_FTQ_CMD_POP
188669. BNX2_COM_COMXQ_FTQ_CMD_RD_DATA
188670. BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET
188671. BNX2_COM_COMXQ_FTQ_CMD_WR_TOP
188672. BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0
188673. BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1
188674. BNX2_COM_COMXQ_FTQ_CTL
188675. BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH
188676. BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE
188677. BNX2_COM_COMXQ_FTQ_CTL_INTERVENE
188678. BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH
188679. BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW
188680. BNX2_COM_CPU_DATA_ACCESS
188681. BNX2_COM_CPU_DEBUG_VECT_PEEK
188682. BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN
188683. BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL
188684. BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE
188685. BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN
188686. BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL
188687. BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE
188688. BNX2_COM_CPU_EVENT_MASK
188689. BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK
188690. BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK
188691. BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK
188692. BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK
188693. BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK
188694. BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK
188695. BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK
188696. BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK
188697. BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK
188698. BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK
188699. BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK
188700. BNX2_COM_CPU_HW_BREAKPOINT
188701. BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS
188702. BNX2_COM_CPU_HW_BREAKPOINT_DISABLE
188703. BNX2_COM_CPU_INSTRUCTION
188704. BNX2_COM_CPU_INTERRUPT_ENABLE
188705. BNX2_COM_CPU_INTERRUPT_SAVED_PC
188706. BNX2_COM_CPU_INTERRUPT_VECTOR
188707. BNX2_COM_CPU_LAST_BRANCH_ADDR
188708. BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA
188709. BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE
188710. BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH
188711. BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP
188712. BNX2_COM_CPU_MODE
188713. BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA
188714. BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA
188715. BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA
188716. BNX2_COM_CPU_MODE_INTERRUPT_ENA
188717. BNX2_COM_CPU_MODE_LOCAL_RST
188718. BNX2_COM_CPU_MODE_MSG_BIT1
188719. BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA
188720. BNX2_COM_CPU_MODE_PAGE_0_INST_ENA
188721. BNX2_COM_CPU_MODE_SOFT_HALT
188722. BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA
188723. BNX2_COM_CPU_MODE_STEP_ENA
188724. BNX2_COM_CPU_PROGRAM_COUNTER
188725. BNX2_COM_CPU_REG_FILE
188726. BNX2_COM_CPU_STATE
188727. BNX2_COM_CPU_STATE_ALIGN_HALTED
188728. BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED
188729. BNX2_COM_CPU_STATE_BAD_INST_HALTED
188730. BNX2_COM_CPU_STATE_BAD_PC_HALTED
188731. BNX2_COM_CPU_STATE_BLOCKED_READ
188732. BNX2_COM_CPU_STATE_BREAKPOINT
188733. BNX2_COM_CPU_STATE_DATA_ACCESS_STALL
188734. BNX2_COM_CPU_STATE_FIO_ABORT_HALTED
188735. BNX2_COM_CPU_STATE_INST_FETCH_STALL
188736. BNX2_COM_CPU_STATE_INTERRUPT
188737. BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED
188738. BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED
188739. BNX2_COM_CPU_STATE_SOFT_HALTED
188740. BNX2_COM_CPU_STATE_SPAD_UNDERFLOW
188741. BNX2_COM_SCRATCH
188742. BNX2_CONDITION_MFW_RUN_IPMI
188743. BNX2_CONDITION_MFW_RUN_MASK
188744. BNX2_CONDITION_MFW_RUN_NCSI
188745. BNX2_CONDITION_MFW_RUN_NONE
188746. BNX2_CONDITION_MFW_RUN_UMP
188747. BNX2_CONDITION_MFW_RUN_UNKNOWN
188748. BNX2_CONDITION_PM_STATE_FULL
188749. BNX2_CONDITION_PM_STATE_MASK
188750. BNX2_CONDITION_PM_STATE_PREP
188751. BNX2_CONDITION_PM_STATE_UNPREP
188752. BNX2_CP_CKSUM_ERROR_STATUS
188753. BNX2_CP_CKSUM_ERROR_STATUS_CALCULATED
188754. BNX2_CP_CKSUM_ERROR_STATUS_EXPECTED
188755. BNX2_CP_CPQ
188756. BNX2_CP_CPQ_FTQ_CMD
188757. BNX2_CP_CPQ_FTQ_CMD_ADD_DATA
188758. BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN
188759. BNX2_CP_CPQ_FTQ_CMD_BUSY
188760. BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR
188761. BNX2_CP_CPQ_FTQ_CMD_OFFSET
188762. BNX2_CP_CPQ_FTQ_CMD_POP
188763. BNX2_CP_CPQ_FTQ_CMD_RD_DATA
188764. BNX2_CP_CPQ_FTQ_CMD_SFT_RESET
188765. BNX2_CP_CPQ_FTQ_CMD_WR_TOP
188766. BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0
188767. BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1
188768. BNX2_CP_CPQ_FTQ_CTL
188769. BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH
188770. BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE
188771. BNX2_CP_CPQ_FTQ_CTL_INTERVENE
188772. BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH
188773. BNX2_CP_CPQ_FTQ_CTL_OVERFLOW
188774. BNX2_CP_CPQ_PFE_PFE_CTL
188775. BNX2_CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT
188776. BNX2_CP_CPQ_PFE_PFE_CTL_OFFSET
188777. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_COUNT
188778. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE
188779. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0
188780. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_1
188781. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_10
188782. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_11
188783. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_12
188784. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_13
188785. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_14
188786. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_15
188787. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_2
188788. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_3
188789. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_4
188790. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_5
188791. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_6
188792. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_7
188793. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_8
188794. BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_9
188795. BNX2_CP_CPU_DATA_ACCESS
188796. BNX2_CP_CPU_DEBUG_VECT_PEEK
188797. BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN
188798. BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL
188799. BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE
188800. BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN
188801. BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL
188802. BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE
188803. BNX2_CP_CPU_EVENT_MASK
188804. BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK
188805. BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK
188806. BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK
188807. BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK
188808. BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK
188809. BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK
188810. BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK
188811. BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK
188812. BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK
188813. BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK
188814. BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK
188815. BNX2_CP_CPU_HW_BREAKPOINT
188816. BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS
188817. BNX2_CP_CPU_HW_BREAKPOINT_DISABLE
188818. BNX2_CP_CPU_INSTRUCTION
188819. BNX2_CP_CPU_INTERRUPT_ENABLE
188820. BNX2_CP_CPU_INTERRUPT_SAVED_PC
188821. BNX2_CP_CPU_INTERRUPT_VECTOR
188822. BNX2_CP_CPU_LAST_BRANCH_ADDR
188823. BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA
188824. BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE
188825. BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH
188826. BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP
188827. BNX2_CP_CPU_MODE
188828. BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA
188829. BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA
188830. BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA
188831. BNX2_CP_CPU_MODE_INTERRUPT_ENA
188832. BNX2_CP_CPU_MODE_LOCAL_RST
188833. BNX2_CP_CPU_MODE_MSG_BIT1
188834. BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA
188835. BNX2_CP_CPU_MODE_PAGE_0_INST_ENA
188836. BNX2_CP_CPU_MODE_SOFT_HALT
188837. BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA
188838. BNX2_CP_CPU_MODE_STEP_ENA
188839. BNX2_CP_CPU_PROGRAM_COUNTER
188840. BNX2_CP_CPU_REG_FILE
188841. BNX2_CP_CPU_STATE
188842. BNX2_CP_CPU_STATE_ALIGN_HALTED
188843. BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED
188844. BNX2_CP_CPU_STATE_BAD_INST_HALTED
188845. BNX2_CP_CPU_STATE_BAD_PC_HALTED
188846. BNX2_CP_CPU_STATE_BLOCKED_READ
188847. BNX2_CP_CPU_STATE_BREAKPOINT
188848. BNX2_CP_CPU_STATE_DATA_ACCESS_STALL
188849. BNX2_CP_CPU_STATE_FIO_ABORT_HALTED
188850. BNX2_CP_CPU_STATE_INST_FETCH_STALL
188851. BNX2_CP_CPU_STATE_INTERRUPT
188852. BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED
188853. BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED
188854. BNX2_CP_CPU_STATE_SOFT_HALTED
188855. BNX2_CP_CPU_STATE_SPAD_UNDERFLOW
188856. BNX2_CP_SCRATCH
188857. BNX2_CTX_ACCESS_STATUS
188858. BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM
188859. BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM
188860. BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI
188861. BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI
188862. BNX2_CTX_ACCESS_STATUS_MASTERENCODED
188863. BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM
188864. BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST
188865. BNX2_CTX_ACCESS_STATUS_REQUEST_XI
188866. BNX2_CTX_CACHE_CTRL_SM_STATUS
188867. BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC
188868. BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC
188869. BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC
188870. BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC
188871. BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR
188872. BNX2_CTX_CACHE_CTRL_STATUS
188873. BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED
188874. BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START
188875. BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT
188876. BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP
188877. BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE
188878. BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE
188879. BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE
188880. BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE
188881. BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE
188882. BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE
188883. BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE
188884. BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE
188885. BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE
188886. BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE
188887. BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE
188888. BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW
188889. BNX2_CTX_CACHE_DATA
188890. BNX2_CTX_CACHE_STATUS
188891. BNX2_CTX_CACHE_STATUS_HELD_ENTRIES
188892. BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES
188893. BNX2_CTX_CAM_CTRL
188894. BNX2_CTX_CAM_CTRL_CAM_ADDR
188895. BNX2_CTX_CAM_CTRL_INVALIDATE
188896. BNX2_CTX_CAM_CTRL_READ_REQ
188897. BNX2_CTX_CAM_CTRL_RESET
188898. BNX2_CTX_CAM_CTRL_SEARCH
188899. BNX2_CTX_CAM_CTRL_WRITE_REQ
188900. BNX2_CTX_CHNL_LOCK_STATUS_0
188901. BNX2_CTX_CHNL_LOCK_STATUS_0_CID
188902. BNX2_CTX_CHNL_LOCK_STATUS_0_MODE
188903. BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI
188904. BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE
188905. BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI
188906. BNX2_CTX_CHNL_LOCK_STATUS_1
188907. BNX2_CTX_CHNL_LOCK_STATUS_2
188908. BNX2_CTX_CHNL_LOCK_STATUS_3
188909. BNX2_CTX_CHNL_LOCK_STATUS_4
188910. BNX2_CTX_CHNL_LOCK_STATUS_5
188911. BNX2_CTX_CHNL_LOCK_STATUS_6
188912. BNX2_CTX_CHNL_LOCK_STATUS_7
188913. BNX2_CTX_CHNL_LOCK_STATUS_8
188914. BNX2_CTX_CHNL_LOCK_STATUS_9
188915. BNX2_CTX_CKSUM_ERROR_STATUS
188916. BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED
188917. BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED
188918. BNX2_CTX_COMMAND
188919. BNX2_CTX_COMMAND_DISABLE_COMBINE_READ
188920. BNX2_CTX_COMMAND_DISABLE_PLRU
188921. BNX2_CTX_COMMAND_DISABLE_USAGE_CNT
188922. BNX2_CTX_COMMAND_ENABLED
188923. BNX2_CTX_COMMAND_FLUSH_AHEAD
188924. BNX2_CTX_COMMAND_MEM_INIT
188925. BNX2_CTX_COMMAND_PAGE_SIZE
188926. BNX2_CTX_COMMAND_PAGE_SIZE_128K
188927. BNX2_CTX_COMMAND_PAGE_SIZE_16K
188928. BNX2_CTX_COMMAND_PAGE_SIZE_1K
188929. BNX2_CTX_COMMAND_PAGE_SIZE_1M
188930. BNX2_CTX_COMMAND_PAGE_SIZE_256
188931. BNX2_CTX_COMMAND_PAGE_SIZE_256K
188932. BNX2_CTX_COMMAND_PAGE_SIZE_2K
188933. BNX2_CTX_COMMAND_PAGE_SIZE_32K
188934. BNX2_CTX_COMMAND_PAGE_SIZE_4K
188935. BNX2_CTX_COMMAND_PAGE_SIZE_512
188936. BNX2_CTX_COMMAND_PAGE_SIZE_512K
188937. BNX2_CTX_COMMAND_PAGE_SIZE_64K
188938. BNX2_CTX_COMMAND_PAGE_SIZE_8K
188939. BNX2_CTX_CTX_CTRL
188940. BNX2_CTX_CTX_CTRL_ATTR
188941. BNX2_CTX_CTX_CTRL_CTX_ADDR
188942. BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT
188943. BNX2_CTX_CTX_CTRL_NO_RAM_ACC
188944. BNX2_CTX_CTX_CTRL_PREFETCH_SIZE
188945. BNX2_CTX_CTX_CTRL_READ_REQ
188946. BNX2_CTX_CTX_CTRL_WRITE_REQ
188947. BNX2_CTX_CTX_DATA
188948. BNX2_CTX_DATA
188949. BNX2_CTX_DATA_ADR
188950. BNX2_CTX_DATA_ADR_DATA_ADR
188951. BNX2_CTX_DBG_LOCK_STATUS
188952. BNX2_CTX_DBG_LOCK_STATUS_MATCH
188953. BNX2_CTX_DBG_LOCK_STATUS_SM
188954. BNX2_CTX_DMA_STATUS
188955. BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS
188956. BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS
188957. BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS
188958. BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS
188959. BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS
188960. BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS
188961. BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS
188962. BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS
188963. BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS
188964. BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS
188965. BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS
188966. BNX2_CTX_HOST_PAGE_TBL_CTRL
188967. BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR
188968. BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ
188969. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ
188970. BNX2_CTX_HOST_PAGE_TBL_DATA0
188971. BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID
188972. BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE
188973. BNX2_CTX_HOST_PAGE_TBL_DATA1
188974. BNX2_CTX_LOCK
188975. BNX2_CTX_LOCK_CID_VALUE
188976. BNX2_CTX_LOCK_GRANTED
188977. BNX2_CTX_LOCK_MODE
188978. BNX2_CTX_LOCK_MODE_IMMEDIATE
188979. BNX2_CTX_LOCK_MODE_SURE
188980. BNX2_CTX_LOCK_MODE_UNLOCK
188981. BNX2_CTX_LOCK_REQ
188982. BNX2_CTX_LOCK_STATUS
188983. BNX2_CTX_LOCK_TYPE
188984. BNX2_CTX_LOCK_TYPE_COMPLETE_XI
188985. BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE
188986. BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL
188987. BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER
188988. BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX
188989. BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID
188990. BNX2_CTX_LOCK_TYPE_PROTOCOL_XI
188991. BNX2_CTX_LOCK_TYPE_TIMER_XI
188992. BNX2_CTX_LOCK_TYPE_TX_XI
188993. BNX2_CTX_LOCK_TYPE_VOID_XI
188994. BNX2_CTX_PAGE_TBL
188995. BNX2_CTX_PAGE_TBL_PAGE_TBL
188996. BNX2_CTX_REP_STATUS
188997. BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID
188998. BNX2_CTX_REP_STATUS_ERROR_ENTRY
188999. BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR
189000. BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR
189001. BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR
189002. BNX2_CTX_STATUS
189003. BNX2_CTX_STATUS_ACC_STALL_STAT
189004. BNX2_CTX_STATUS_DEAD_LOCK
189005. BNX2_CTX_STATUS_EXT_READ_STAT
189006. BNX2_CTX_STATUS_EXT_WRITE_STAT
189007. BNX2_CTX_STATUS_HIT_STAT
189008. BNX2_CTX_STATUS_INVALID_PAGE
189009. BNX2_CTX_STATUS_LOCK_STALL_STAT
189010. BNX2_CTX_STATUS_LOCK_WAIT
189011. BNX2_CTX_STATUS_MISS_STAT
189012. BNX2_CTX_STATUS_READ_STAT
189013. BNX2_CTX_STATUS_USAGE_CNT_ERR
189014. BNX2_CTX_STATUS_WRITE_STAT
189015. BNX2_CTX_VIRT_ADDR
189016. BNX2_CTX_VIRT_ADDR_VIRT_ADDR
189017. BNX2_DEV_INFO_BC_REV
189018. BNX2_DEV_INFO_DRV_ALWAYS_ALIVE
189019. BNX2_DEV_INFO_FEATURE_CFG_VALID
189020. BNX2_DEV_INFO_FORMAT_REV
189021. BNX2_DEV_INFO_FORMAT_REV_ID
189022. BNX2_DEV_INFO_FORMAT_REV_MASK
189023. BNX2_DEV_INFO_PER_PORT_HW_CONFIG2
189024. BNX2_DEV_INFO_SECONDARY_PORT
189025. BNX2_DEV_INFO_SIGNATURE
189026. BNX2_DEV_INFO_SIGNATURE_MAGIC
189027. BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK
189028. BNX2_DMA_ARBITER
189029. BNX2_DMA_ARBITER_ALT_MODE_EN
189030. BNX2_DMA_ARBITER_NUM_READS
189031. BNX2_DMA_ARBITER_OUSTD_READ_REQ
189032. BNX2_DMA_ARBITER_RD_ARB_MODE
189033. BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN
189034. BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT
189035. BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN
189036. BNX2_DMA_ARBITER_RR_MODE
189037. BNX2_DMA_ARBITER_TIMER_MODE
189038. BNX2_DMA_ARBITER_WR_ARB_MODE
189039. BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN
189040. BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT
189041. BNX2_DMA_ARB_STAT_00
189042. BNX2_DMA_ARB_STAT_00_CUR_BINMSTR
189043. BNX2_DMA_ARB_STAT_00_MASTER
189044. BNX2_DMA_ARB_STAT_00_MASTER_ENC
189045. BNX2_DMA_ARB_STAT_01
189046. BNX2_DMA_ARB_STAT_01_HPB_RPTR
189047. BNX2_DMA_ARB_STAT_01_HPB_WPTR
189048. BNX2_DMA_ARB_STAT_01_HPR_RPTR
189049. BNX2_DMA_ARB_STAT_01_HPR_WPTR
189050. BNX2_DMA_ARB_STAT_01_LPB_RPTR
189051. BNX2_DMA_ARB_STAT_01_LPB_WPTR
189052. BNX2_DMA_ARB_STAT_01_LPR_RPTR
189053. BNX2_DMA_ARB_STAT_01_LPR_WPTR
189054. BNX2_DMA_ARB_TIMERS
189055. BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME
189056. BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT
189057. BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT
189058. BNX2_DMA_BLACKOUT
189059. BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT
189060. BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT
189061. BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT
189062. BNX2_DMA_COMMAND
189063. BNX2_DMA_COMMAND_ENABLE
189064. BNX2_DMA_CONFIG
189065. BNX2_DMA_CONFIG_BIG_SIZE
189066. BNX2_DMA_CONFIG_BIG_SIZE_128
189067. BNX2_DMA_CONFIG_BIG_SIZE_256
189068. BNX2_DMA_CONFIG_BIG_SIZE_512
189069. BNX2_DMA_CONFIG_BIG_SIZE_64
189070. BNX2_DMA_CONFIG_BIG_SIZE_NONE
189071. BNX2_DMA_CONFIG_CNTL_BYTE_SWAP
189072. BNX2_DMA_CONFIG_CNTL_FPGA_MODE
189073. BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY
189074. BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA
189075. BNX2_DMA_CONFIG_CNTL_TWO_DMA
189076. BNX2_DMA_CONFIG_CNTL_WORD_SWAP
189077. BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI
189078. BNX2_DMA_CONFIG_DATA_BYTE_SWAP
189079. BNX2_DMA_CONFIG_DATA_WORD_SWAP
189080. BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI
189081. BNX2_DMA_CONFIG_MAX_PL_128B_XI
189082. BNX2_DMA_CONFIG_MAX_PL_256B_XI
189083. BNX2_DMA_CONFIG_MAX_PL_512B_XI
189084. BNX2_DMA_CONFIG_MAX_PL_EN_XI
189085. BNX2_DMA_CONFIG_MAX_PL_XI
189086. BNX2_DMA_CONFIG_MAX_RRS_1024B_XI
189087. BNX2_DMA_CONFIG_MAX_RRS_128B_XI
189088. BNX2_DMA_CONFIG_MAX_RRS_2048B_XI
189089. BNX2_DMA_CONFIG_MAX_RRS_256B_XI
189090. BNX2_DMA_CONFIG_MAX_RRS_4096B_XI
189091. BNX2_DMA_CONFIG_MAX_RRS_512B_XI
189092. BNX2_DMA_CONFIG_MAX_RRS_EN_XI
189093. BNX2_DMA_CONFIG_MAX_RRS_XI
189094. BNX2_DMA_CONFIG_NO_64SWAP_EN_XI
189095. BNX2_DMA_CONFIG_NO_RCHANS_IN_USE
189096. BNX2_DMA_CONFIG_NO_WCHANS_IN_USE
189097. BNX2_DMA_CONFIG_ONE_DMA
189098. BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS
189099. BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP
189100. BNX2_DMA_DEBUG_VECT_PEEK
189101. BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN
189102. BNX2_DMA_DEBUG_VECT_PEEK_1_SEL
189103. BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE
189104. BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN
189105. BNX2_DMA_DEBUG_VECT_PEEK_2_SEL
189106. BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE
189107. BNX2_DMA_FUSE_CTRL0_CMD
189108. BNX2_DMA_FUSE_CTRL0_CMD_LOAD
189109. BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE
189110. BNX2_DMA_FUSE_CTRL0_CMD_SEL
189111. BNX2_DMA_FUSE_CTRL0_CMD_SHIFT
189112. BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE
189113. BNX2_DMA_FUSE_CTRL0_DATA
189114. BNX2_DMA_FUSE_CTRL1_CMD
189115. BNX2_DMA_FUSE_CTRL1_CMD_LOAD
189116. BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE
189117. BNX2_DMA_FUSE_CTRL1_CMD_SEL
189118. BNX2_DMA_FUSE_CTRL1_CMD_SHIFT
189119. BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE
189120. BNX2_DMA_FUSE_CTRL1_DATA
189121. BNX2_DMA_FUSE_CTRL2_CMD
189122. BNX2_DMA_FUSE_CTRL2_CMD_LOAD
189123. BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE
189124. BNX2_DMA_FUSE_CTRL2_CMD_SEL
189125. BNX2_DMA_FUSE_CTRL2_CMD_SHIFT
189126. BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE
189127. BNX2_DMA_FUSE_CTRL2_DATA
189128. BNX2_DMA_RCHAN_STAT_22
189129. BNX2_DMA_RCHAN_STAT_30
189130. BNX2_DMA_RCHAN_STAT_31
189131. BNX2_DMA_RCHAN_STAT_32
189132. BNX2_DMA_RCHAN_STAT_40
189133. BNX2_DMA_RCHAN_STAT_41
189134. BNX2_DMA_RCHAN_STAT_42
189135. BNX2_DMA_RCHAN_STAT_50
189136. BNX2_DMA_RCHAN_STAT_51
189137. BNX2_DMA_RCHAN_STAT_52
189138. BNX2_DMA_RCHAN_STAT_60
189139. BNX2_DMA_RCHAN_STAT_61
189140. BNX2_DMA_RCHAN_STAT_62
189141. BNX2_DMA_RCHAN_STAT_70
189142. BNX2_DMA_RCHAN_STAT_71
189143. BNX2_DMA_RCHAN_STAT_72
189144. BNX2_DMA_READ_MASTER_SETTING_0
189145. BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP
189146. BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN
189147. BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY
189148. BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER
189149. BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS
189150. BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP
189151. BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN
189152. BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY
189153. BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER
189154. BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS
189155. BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP
189156. BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN
189157. BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY
189158. BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER
189159. BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS
189160. BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP
189161. BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN
189162. BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY
189163. BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER
189164. BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS
189165. BNX2_DMA_READ_MASTER_SETTING_1
189166. BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP
189167. BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN
189168. BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY
189169. BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER
189170. BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS
189171. BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP
189172. BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN
189173. BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY
189174. BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER
189175. BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS
189176. BNX2_DMA_STATUS
189177. BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT
189178. BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT
189179. BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT
189180. BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT
189181. BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT
189182. BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT
189183. BNX2_DMA_STATUS_BME_XI
189184. BNX2_DMA_STATUS_GLOBAL_ERR_XI
189185. BNX2_DMA_STATUS_PAR_ERROR_STATE
189186. BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT
189187. BNX2_DMA_STATUS_READ_TRANSFERS_STAT
189188. BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT
189189. BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT
189190. BNX2_DMA_TAG_RAM_00
189191. BNX2_DMA_TAG_RAM_00_CHANNEL
189192. BNX2_DMA_TAG_RAM_00_FUNCTION
189193. BNX2_DMA_TAG_RAM_00_MASTER
189194. BNX2_DMA_TAG_RAM_00_MASTER_COM
189195. BNX2_DMA_TAG_RAM_00_MASTER_CP
189196. BNX2_DMA_TAG_RAM_00_MASTER_CTX
189197. BNX2_DMA_TAG_RAM_00_MASTER_RBDC
189198. BNX2_DMA_TAG_RAM_00_MASTER_TBDC
189199. BNX2_DMA_TAG_RAM_00_MASTER_TDMA
189200. BNX2_DMA_TAG_RAM_00_SWAP
189201. BNX2_DMA_TAG_RAM_00_SWAP_CONFIG
189202. BNX2_DMA_TAG_RAM_00_SWAP_CONTROL
189203. BNX2_DMA_TAG_RAM_00_SWAP_DATA
189204. BNX2_DMA_TAG_RAM_00_VALID
189205. BNX2_DMA_TAG_RAM_01
189206. BNX2_DMA_TAG_RAM_01_CHANNEL
189207. BNX2_DMA_TAG_RAM_01_FUNCTION
189208. BNX2_DMA_TAG_RAM_01_MASTER
189209. BNX2_DMA_TAG_RAM_01_MASTER_COM
189210. BNX2_DMA_TAG_RAM_01_MASTER_CP
189211. BNX2_DMA_TAG_RAM_01_MASTER_CTX
189212. BNX2_DMA_TAG_RAM_01_MASTER_RBDC
189213. BNX2_DMA_TAG_RAM_01_MASTER_TBDC
189214. BNX2_DMA_TAG_RAM_01_MASTER_TDMA
189215. BNX2_DMA_TAG_RAM_01_SWAP
189216. BNX2_DMA_TAG_RAM_01_SWAP_CONFIG
189217. BNX2_DMA_TAG_RAM_01_SWAP_CONTROL
189218. BNX2_DMA_TAG_RAM_01_SWAP_DATA
189219. BNX2_DMA_TAG_RAM_01_VALID
189220. BNX2_DMA_TAG_RAM_02
189221. BNX2_DMA_TAG_RAM_02_CHANNEL
189222. BNX2_DMA_TAG_RAM_02_FUNCTION
189223. BNX2_DMA_TAG_RAM_02_MASTER
189224. BNX2_DMA_TAG_RAM_02_MASTER_COM
189225. BNX2_DMA_TAG_RAM_02_MASTER_CP
189226. BNX2_DMA_TAG_RAM_02_MASTER_CTX
189227. BNX2_DMA_TAG_RAM_02_MASTER_RBDC
189228. BNX2_DMA_TAG_RAM_02_MASTER_TBDC
189229. BNX2_DMA_TAG_RAM_02_MASTER_TDMA
189230. BNX2_DMA_TAG_RAM_02_SWAP
189231. BNX2_DMA_TAG_RAM_02_SWAP_CONFIG
189232. BNX2_DMA_TAG_RAM_02_SWAP_CONTROL
189233. BNX2_DMA_TAG_RAM_02_SWAP_DATA
189234. BNX2_DMA_TAG_RAM_02_VALID
189235. BNX2_DMA_TAG_RAM_03
189236. BNX2_DMA_TAG_RAM_03_CHANNEL
189237. BNX2_DMA_TAG_RAM_03_FUNCTION
189238. BNX2_DMA_TAG_RAM_03_MASTER
189239. BNX2_DMA_TAG_RAM_03_MASTER_COM
189240. BNX2_DMA_TAG_RAM_03_MASTER_CP
189241. BNX2_DMA_TAG_RAM_03_MASTER_CTX
189242. BNX2_DMA_TAG_RAM_03_MASTER_RBDC
189243. BNX2_DMA_TAG_RAM_03_MASTER_TBDC
189244. BNX2_DMA_TAG_RAM_03_MASTER_TDMA
189245. BNX2_DMA_TAG_RAM_03_SWAP
189246. BNX2_DMA_TAG_RAM_03_SWAP_CONFIG
189247. BNX2_DMA_TAG_RAM_03_SWAP_CONTROL
189248. BNX2_DMA_TAG_RAM_03_SWAP_DATA
189249. BNX2_DMA_TAG_RAM_03_VALID
189250. BNX2_DMA_TAG_RAM_04
189251. BNX2_DMA_TAG_RAM_04_CHANNEL
189252. BNX2_DMA_TAG_RAM_04_FUNCTION
189253. BNX2_DMA_TAG_RAM_04_MASTER
189254. BNX2_DMA_TAG_RAM_04_MASTER_COM
189255. BNX2_DMA_TAG_RAM_04_MASTER_CP
189256. BNX2_DMA_TAG_RAM_04_MASTER_CTX
189257. BNX2_DMA_TAG_RAM_04_MASTER_RBDC
189258. BNX2_DMA_TAG_RAM_04_MASTER_TBDC
189259. BNX2_DMA_TAG_RAM_04_MASTER_TDMA
189260. BNX2_DMA_TAG_RAM_04_SWAP
189261. BNX2_DMA_TAG_RAM_04_SWAP_CONFIG
189262. BNX2_DMA_TAG_RAM_04_SWAP_CONTROL
189263. BNX2_DMA_TAG_RAM_04_SWAP_DATA
189264. BNX2_DMA_TAG_RAM_04_VALID
189265. BNX2_DMA_TAG_RAM_05
189266. BNX2_DMA_TAG_RAM_05_CHANNEL
189267. BNX2_DMA_TAG_RAM_05_FUNCTION
189268. BNX2_DMA_TAG_RAM_05_MASTER
189269. BNX2_DMA_TAG_RAM_05_MASTER_COM
189270. BNX2_DMA_TAG_RAM_05_MASTER_CP
189271. BNX2_DMA_TAG_RAM_05_MASTER_CTX
189272. BNX2_DMA_TAG_RAM_05_MASTER_RBDC
189273. BNX2_DMA_TAG_RAM_05_MASTER_TBDC
189274. BNX2_DMA_TAG_RAM_05_MASTER_TDMA
189275. BNX2_DMA_TAG_RAM_05_SWAP
189276. BNX2_DMA_TAG_RAM_05_SWAP_CONFIG
189277. BNX2_DMA_TAG_RAM_05_SWAP_CONTROL
189278. BNX2_DMA_TAG_RAM_05_SWAP_DATA
189279. BNX2_DMA_TAG_RAM_05_VALID
189280. BNX2_DMA_TAG_RAM_06
189281. BNX2_DMA_TAG_RAM_06_CHANNEL
189282. BNX2_DMA_TAG_RAM_06_FUNCTION
189283. BNX2_DMA_TAG_RAM_06_MASTER
189284. BNX2_DMA_TAG_RAM_06_MASTER_COM
189285. BNX2_DMA_TAG_RAM_06_MASTER_CP
189286. BNX2_DMA_TAG_RAM_06_MASTER_CTX
189287. BNX2_DMA_TAG_RAM_06_MASTER_RBDC
189288. BNX2_DMA_TAG_RAM_06_MASTER_TBDC
189289. BNX2_DMA_TAG_RAM_06_MASTER_TDMA
189290. BNX2_DMA_TAG_RAM_06_SWAP
189291. BNX2_DMA_TAG_RAM_06_SWAP_CONFIG
189292. BNX2_DMA_TAG_RAM_06_SWAP_CONTROL
189293. BNX2_DMA_TAG_RAM_06_SWAP_DATA
189294. BNX2_DMA_TAG_RAM_06_VALID
189295. BNX2_DMA_TAG_RAM_07
189296. BNX2_DMA_TAG_RAM_07_CHANNEL
189297. BNX2_DMA_TAG_RAM_07_FUNCTION
189298. BNX2_DMA_TAG_RAM_07_MASTER
189299. BNX2_DMA_TAG_RAM_07_MASTER_COM
189300. BNX2_DMA_TAG_RAM_07_MASTER_CP
189301. BNX2_DMA_TAG_RAM_07_MASTER_CTX
189302. BNX2_DMA_TAG_RAM_07_MASTER_RBDC
189303. BNX2_DMA_TAG_RAM_07_MASTER_TBDC
189304. BNX2_DMA_TAG_RAM_07_MASTER_TDMA
189305. BNX2_DMA_TAG_RAM_07_SWAP
189306. BNX2_DMA_TAG_RAM_07_SWAP_CONFIG
189307. BNX2_DMA_TAG_RAM_07_SWAP_CONTROL
189308. BNX2_DMA_TAG_RAM_07_SWAP_DATA
189309. BNX2_DMA_TAG_RAM_07_VALID
189310. BNX2_DMA_TAG_RAM_08
189311. BNX2_DMA_TAG_RAM_08_CHANNEL
189312. BNX2_DMA_TAG_RAM_08_FUNCTION
189313. BNX2_DMA_TAG_RAM_08_MASTER
189314. BNX2_DMA_TAG_RAM_08_MASTER_COM
189315. BNX2_DMA_TAG_RAM_08_MASTER_CP
189316. BNX2_DMA_TAG_RAM_08_MASTER_CTX
189317. BNX2_DMA_TAG_RAM_08_MASTER_RBDC
189318. BNX2_DMA_TAG_RAM_08_MASTER_TBDC
189319. BNX2_DMA_TAG_RAM_08_MASTER_TDMA
189320. BNX2_DMA_TAG_RAM_08_SWAP
189321. BNX2_DMA_TAG_RAM_08_SWAP_CONFIG
189322. BNX2_DMA_TAG_RAM_08_SWAP_CONTROL
189323. BNX2_DMA_TAG_RAM_08_SWAP_DATA
189324. BNX2_DMA_TAG_RAM_08_VALID
189325. BNX2_DMA_TAG_RAM_09
189326. BNX2_DMA_TAG_RAM_09_CHANNEL
189327. BNX2_DMA_TAG_RAM_09_FUNCTION
189328. BNX2_DMA_TAG_RAM_09_MASTER
189329. BNX2_DMA_TAG_RAM_09_MASTER_COM
189330. BNX2_DMA_TAG_RAM_09_MASTER_CP
189331. BNX2_DMA_TAG_RAM_09_MASTER_CTX
189332. BNX2_DMA_TAG_RAM_09_MASTER_RBDC
189333. BNX2_DMA_TAG_RAM_09_MASTER_TBDC
189334. BNX2_DMA_TAG_RAM_09_MASTER_TDMA
189335. BNX2_DMA_TAG_RAM_09_SWAP
189336. BNX2_DMA_TAG_RAM_09_SWAP_CONFIG
189337. BNX2_DMA_TAG_RAM_09_SWAP_CONTROL
189338. BNX2_DMA_TAG_RAM_09_SWAP_DATA
189339. BNX2_DMA_TAG_RAM_09_VALID
189340. BNX2_DMA_TAG_RAM_10
189341. BNX2_DMA_TAG_RAM_10_CHANNEL
189342. BNX2_DMA_TAG_RAM_10_FUNCTION
189343. BNX2_DMA_TAG_RAM_10_MASTER
189344. BNX2_DMA_TAG_RAM_10_MASTER_COM
189345. BNX2_DMA_TAG_RAM_10_MASTER_CP
189346. BNX2_DMA_TAG_RAM_10_MASTER_CTX
189347. BNX2_DMA_TAG_RAM_10_MASTER_RBDC
189348. BNX2_DMA_TAG_RAM_10_MASTER_TBDC
189349. BNX2_DMA_TAG_RAM_10_MASTER_TDMA
189350. BNX2_DMA_TAG_RAM_10_SWAP
189351. BNX2_DMA_TAG_RAM_10_SWAP_CONFIG
189352. BNX2_DMA_TAG_RAM_10_SWAP_CONTROL
189353. BNX2_DMA_TAG_RAM_10_SWAP_DATA
189354. BNX2_DMA_TAG_RAM_10_VALID
189355. BNX2_DMA_TAG_RAM_11
189356. BNX2_DMA_TAG_RAM_11_CHANNEL
189357. BNX2_DMA_TAG_RAM_11_FUNCTION
189358. BNX2_DMA_TAG_RAM_11_MASTER
189359. BNX2_DMA_TAG_RAM_11_MASTER_COM
189360. BNX2_DMA_TAG_RAM_11_MASTER_CP
189361. BNX2_DMA_TAG_RAM_11_MASTER_CTX
189362. BNX2_DMA_TAG_RAM_11_MASTER_RBDC
189363. BNX2_DMA_TAG_RAM_11_MASTER_TBDC
189364. BNX2_DMA_TAG_RAM_11_MASTER_TDMA
189365. BNX2_DMA_TAG_RAM_11_SWAP
189366. BNX2_DMA_TAG_RAM_11_SWAP_CONFIG
189367. BNX2_DMA_TAG_RAM_11_SWAP_CONTROL
189368. BNX2_DMA_TAG_RAM_11_SWAP_DATA
189369. BNX2_DMA_TAG_RAM_11_VALID
189370. BNX2_DMA_WCHAN_STAT_00
189371. BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW
189372. BNX2_DMA_WCHAN_STAT_01
189373. BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH
189374. BNX2_DMA_WCHAN_STAT_02
189375. BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP
189376. BNX2_DMA_WCHAN_STAT_02_LENGTH
189377. BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL
189378. BNX2_DMA_WCHAN_STAT_02_WORD_SWAP
189379. BNX2_DMA_WCHAN_STAT_10
189380. BNX2_DMA_WCHAN_STAT_11
189381. BNX2_DMA_WCHAN_STAT_12
189382. BNX2_DMA_WCHAN_STAT_20
189383. BNX2_DMA_WCHAN_STAT_21
189384. BNX2_DMA_WCHAN_STAT_22
189385. BNX2_DMA_WCHAN_STAT_30
189386. BNX2_DMA_WCHAN_STAT_31
189387. BNX2_DMA_WCHAN_STAT_32
189388. BNX2_DMA_WCHAN_STAT_40
189389. BNX2_DMA_WCHAN_STAT_41
189390. BNX2_DMA_WCHAN_STAT_42
189391. BNX2_DMA_WCHAN_STAT_50
189392. BNX2_DMA_WCHAN_STAT_51
189393. BNX2_DMA_WCHAN_STAT_52
189394. BNX2_DMA_WCHAN_STAT_60
189395. BNX2_DMA_WCHAN_STAT_61
189396. BNX2_DMA_WCHAN_STAT_62
189397. BNX2_DMA_WCHAN_STAT_70
189398. BNX2_DMA_WCHAN_STAT_71
189399. BNX2_DMA_WCHAN_STAT_72
189400. BNX2_DMA_WRITE_MASTER_SETTING_0
189401. BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD
189402. BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP
189403. BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN
189404. BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY
189405. BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER
189406. BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS
189407. BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD
189408. BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP
189409. BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN
189410. BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY
189411. BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER
189412. BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS
189413. BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD
189414. BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP
189415. BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN
189416. BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY
189417. BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER
189418. BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS
189419. BNX2_DMA_WRITE_MASTER_SETTING_1
189420. BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD
189421. BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP
189422. BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN
189423. BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY
189424. BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER
189425. BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS
189426. BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD
189427. BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP
189428. BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN
189429. BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY
189430. BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER
189431. BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS
189432. BNX2_DRV_ACK_CAP_MB
189433. BNX2_DRV_ACK_CAP_SIGNATURE
189434. BNX2_DRV_MB
189435. BNX2_DRV_MB_ARG0
189436. BNX2_DRV_MSG_CODE
189437. BNX2_DRV_MSG_CODE_CMD_SET_LINK
189438. BNX2_DRV_MSG_CODE_DIAG
189439. BNX2_DRV_MSG_CODE_FW_TIMEOUT
189440. BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE
189441. BNX2_DRV_MSG_CODE_PULSE
189442. BNX2_DRV_MSG_CODE_RESET
189443. BNX2_DRV_MSG_CODE_SHUTDOWN
189444. BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL
189445. BNX2_DRV_MSG_CODE_SUSPEND_WOL
189446. BNX2_DRV_MSG_CODE_UNLOAD
189447. BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN
189448. BNX2_DRV_MSG_DATA
189449. BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE
189450. BNX2_DRV_MSG_DATA_WAIT0
189451. BNX2_DRV_MSG_DATA_WAIT1
189452. BNX2_DRV_MSG_DATA_WAIT2
189453. BNX2_DRV_MSG_DATA_WAIT3
189454. BNX2_DRV_MSG_SEQ
189455. BNX2_DRV_PULSE_MB
189456. BNX2_DRV_PULSE_PERIOD_MS
189457. BNX2_DRV_PULSE_SEQ_MASK
189458. BNX2_DRV_RESET_SIGNATURE
189459. BNX2_DRV_RESET_SIGNATURE_MAGIC
189460. BNX2_EMAC_ATTENTION_ENA
189461. BNX2_EMAC_ATTENTION_ENA_AP_ERROR
189462. BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE
189463. BNX2_EMAC_ATTENTION_ENA_LINK
189464. BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE
189465. BNX2_EMAC_ATTENTION_ENA_MI_INT
189466. BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE
189467. BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE
189468. BNX2_EMAC_BACKOFF_SEED
189469. BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED
189470. BNX2_EMAC_CKSUM_ERROR_STATUS
189471. BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED
189472. BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED
189473. BNX2_EMAC_LED
189474. BNX2_EMAC_LED_1000MB
189475. BNX2_EMAC_LED_1000MB_OVERRIDE
189476. BNX2_EMAC_LED_100MB
189477. BNX2_EMAC_LED_100MB_OVERRIDE
189478. BNX2_EMAC_LED_10MB
189479. BNX2_EMAC_LED_10MB_OVERRIDE
189480. BNX2_EMAC_LED_2500MB
189481. BNX2_EMAC_LED_2500MB_OVERRIDE
189482. BNX2_EMAC_LED_ACTIVITY_SEL
189483. BNX2_EMAC_LED_ACTIVITY_SEL_0
189484. BNX2_EMAC_LED_ACTIVITY_SEL_1
189485. BNX2_EMAC_LED_ACTIVITY_SEL_2
189486. BNX2_EMAC_LED_ACTIVITY_SEL_3
189487. BNX2_EMAC_LED_BLNK_RATE
189488. BNX2_EMAC_LED_BLNK_RATE_ENA
189489. BNX2_EMAC_LED_BLNK_TRAFFIC
189490. BNX2_EMAC_LED_OVERRIDE
189491. BNX2_EMAC_LED_TRAFFIC
189492. BNX2_EMAC_LED_TRAFFIC_OVERRIDE
189493. BNX2_EMAC_LED_TRAFFIC_STAT
189494. BNX2_EMAC_MAC_MATCH0
189495. BNX2_EMAC_MAC_MATCH1
189496. BNX2_EMAC_MAC_MATCH10
189497. BNX2_EMAC_MAC_MATCH11
189498. BNX2_EMAC_MAC_MATCH12
189499. BNX2_EMAC_MAC_MATCH13
189500. BNX2_EMAC_MAC_MATCH14
189501. BNX2_EMAC_MAC_MATCH15
189502. BNX2_EMAC_MAC_MATCH16
189503. BNX2_EMAC_MAC_MATCH17
189504. BNX2_EMAC_MAC_MATCH18
189505. BNX2_EMAC_MAC_MATCH19
189506. BNX2_EMAC_MAC_MATCH2
189507. BNX2_EMAC_MAC_MATCH20
189508. BNX2_EMAC_MAC_MATCH21
189509. BNX2_EMAC_MAC_MATCH22
189510. BNX2_EMAC_MAC_MATCH23
189511. BNX2_EMAC_MAC_MATCH24
189512. BNX2_EMAC_MAC_MATCH25
189513. BNX2_EMAC_MAC_MATCH26
189514. BNX2_EMAC_MAC_MATCH27
189515. BNX2_EMAC_MAC_MATCH28
189516. BNX2_EMAC_MAC_MATCH29
189517. BNX2_EMAC_MAC_MATCH3
189518. BNX2_EMAC_MAC_MATCH30
189519. BNX2_EMAC_MAC_MATCH31
189520. BNX2_EMAC_MAC_MATCH4
189521. BNX2_EMAC_MAC_MATCH5
189522. BNX2_EMAC_MAC_MATCH6
189523. BNX2_EMAC_MAC_MATCH7
189524. BNX2_EMAC_MAC_MATCH8
189525. BNX2_EMAC_MAC_MATCH9
189526. BNX2_EMAC_MDIO_AUTO_STATUS
189527. BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR
189528. BNX2_EMAC_MDIO_COMM
189529. BNX2_EMAC_MDIO_COMM_COMMAND
189530. BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS
189531. BNX2_EMAC_MDIO_COMM_COMMAND_READ
189532. BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI
189533. BNX2_EMAC_MDIO_COMM_COMMAND_READ_45
189534. BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI
189535. BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0
189536. BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3
189537. BNX2_EMAC_MDIO_COMM_COMMAND_WRITE
189538. BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI
189539. BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI
189540. BNX2_EMAC_MDIO_COMM_DATA
189541. BNX2_EMAC_MDIO_COMM_DISEXT
189542. BNX2_EMAC_MDIO_COMM_FAIL
189543. BNX2_EMAC_MDIO_COMM_PHY_ADDR
189544. BNX2_EMAC_MDIO_COMM_REG_ADDR
189545. BNX2_EMAC_MDIO_COMM_START_BUSY
189546. BNX2_EMAC_MDIO_MODE
189547. BNX2_EMAC_MDIO_MODE_AUTO_POLL
189548. BNX2_EMAC_MDIO_MODE_BIT_BANG
189549. BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI
189550. BNX2_EMAC_MDIO_MODE_CLOCK_CNT
189551. BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI
189552. BNX2_EMAC_MDIO_MODE_EXT_MDINT
189553. BNX2_EMAC_MDIO_MODE_MDC
189554. BNX2_EMAC_MDIO_MODE_MDINT
189555. BNX2_EMAC_MDIO_MODE_MDIO
189556. BNX2_EMAC_MDIO_MODE_MDIO_OE
189557. BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE
189558. BNX2_EMAC_MDIO_STATUS
189559. BNX2_EMAC_MDIO_STATUS_10MB
189560. BNX2_EMAC_MDIO_STATUS_LINK
189561. BNX2_EMAC_MODE
189562. BNX2_EMAC_MODE_25G_MODE
189563. BNX2_EMAC_MODE_ACPI_RCVD
189564. BNX2_EMAC_MODE_BOND_OVRD
189565. BNX2_EMAC_MODE_EXT_LINK_POL
189566. BNX2_EMAC_MODE_FORCE_LINK
189567. BNX2_EMAC_MODE_HALF_DUPLEX
189568. BNX2_EMAC_MODE_MAC_LOOP
189569. BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA
189570. BNX2_EMAC_MODE_MPKT
189571. BNX2_EMAC_MODE_MPKT_RCVD
189572. BNX2_EMAC_MODE_PORT
189573. BNX2_EMAC_MODE_PORT_GMII
189574. BNX2_EMAC_MODE_PORT_MII
189575. BNX2_EMAC_MODE_PORT_MII_10M
189576. BNX2_EMAC_MODE_PORT_NONE
189577. BNX2_EMAC_MODE_RESET
189578. BNX2_EMAC_MODE_SERDES_MODE
189579. BNX2_EMAC_MODE_TAGGED_MAC_CTL
189580. BNX2_EMAC_MODE_TX_BURST
189581. BNX2_EMAC_MULTICAST_HASH0
189582. BNX2_EMAC_MULTICAST_HASH1
189583. BNX2_EMAC_MULTICAST_HASH2
189584. BNX2_EMAC_MULTICAST_HASH3
189585. BNX2_EMAC_MULTICAST_HASH4
189586. BNX2_EMAC_MULTICAST_HASH5
189587. BNX2_EMAC_MULTICAST_HASH6
189588. BNX2_EMAC_MULTICAST_HASH7
189589. BNX2_EMAC_RXMAC_DEBUG0
189590. BNX2_EMAC_RXMAC_DEBUG1
189591. BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR
189592. BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC
189593. BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT
189594. BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA
189595. BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT
189596. BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE
189597. BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START
189598. BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR
189599. BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME
189600. BNX2_EMAC_RXMAC_DEBUG2
189601. BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN
189602. BNX2_EMAC_RXMAC_DEBUG2_FALSEC
189603. BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE
189604. BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT
189605. BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0
189606. BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1
189607. BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2
189608. BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3
189609. BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE
189610. BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST
189611. BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS
189612. BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT
189613. BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE
189614. BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE
189615. BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED
189616. BNX2_EMAC_RXMAC_DEBUG2_QUANTA
189617. BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER
189618. BNX2_EMAC_RXMAC_DEBUG2_SM_STATE
189619. BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA
189620. BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP
189621. BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT
189622. BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC
189623. BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE
189624. BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP
189625. BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD
189626. BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP
189627. BNX2_EMAC_RXMAC_DEBUG2_TAGGED
189628. BNX2_EMAC_RXMAC_DEBUG3
189629. BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR
189630. BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR
189631. BNX2_EMAC_RXMAC_DEBUG4
189632. BNX2_EMAC_RXMAC_DEBUG4_ADVANCE
189633. BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT
189634. BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER
189635. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE
189636. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC
189637. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2
189638. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3
189639. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1
189640. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2
189641. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3
189642. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE
189643. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD
189644. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP
189645. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE
189646. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH
189647. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC
189648. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC
189649. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2
189650. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3
189651. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK
189652. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2
189653. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3
189654. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE
189655. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1
189656. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2
189657. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED
189658. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED
189659. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1
189660. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2
189661. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3
189662. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE
189663. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE
189664. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL
189665. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2
189666. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3
189667. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI
189668. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1
189669. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2
189670. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3
189671. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE
189672. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL
189673. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE
189674. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF
189675. BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON
189676. BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA
189677. BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND
189678. BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED
189679. BNX2_EMAC_RXMAC_DEBUG4_START
189680. BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD
189681. BNX2_EMAC_RXMAC_DEBUG5
189682. BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0
189683. BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1
189684. BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF
189685. BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF
189686. BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF
189687. BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF
189688. BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF
189689. BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT
189690. BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW
189691. BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT
189692. BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED
189693. BNX2_EMAC_RXMAC_DEBUG5_FMLEN
189694. BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT
189695. BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE
189696. BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE
189697. BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA
189698. BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT
189699. BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM
189700. BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT
189701. BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE
189702. BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL
189703. BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC
189704. BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE
189705. BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF
189706. BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT
189707. BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL
189708. BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC
189709. BNX2_EMAC_RX_MODE
189710. BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE
189711. BNX2_EMAC_RX_MODE_ACCEPT_RUNTS
189712. BNX2_EMAC_RX_MODE_FILT_BROADCAST
189713. BNX2_EMAC_RX_MODE_FLOW_EN
189714. BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL
189715. BNX2_EMAC_RX_MODE_KEEP_PAUSE
189716. BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG
189717. BNX2_EMAC_RX_MODE_LLC_CHK
189718. BNX2_EMAC_RX_MODE_NO_CRC_CHK
189719. BNX2_EMAC_RX_MODE_PROMISCUOUS
189720. BNX2_EMAC_RX_MODE_RESET
189721. BNX2_EMAC_RX_MODE_SORT_MODE
189722. BNX2_EMAC_RX_MTU_SIZE
189723. BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA
189724. BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE
189725. BNX2_EMAC_RX_STATUS
189726. BNX2_EMAC_RX_STATUS_FFED
189727. BNX2_EMAC_RX_STATUS_FF_RECEIVED
189728. BNX2_EMAC_RX_STATUS_N_RECEIVED
189729. BNX2_EMAC_RX_STAT_AC0
189730. BNX2_EMAC_RX_STAT_AC1
189731. BNX2_EMAC_RX_STAT_AC10
189732. BNX2_EMAC_RX_STAT_AC11
189733. BNX2_EMAC_RX_STAT_AC12
189734. BNX2_EMAC_RX_STAT_AC13
189735. BNX2_EMAC_RX_STAT_AC14
189736. BNX2_EMAC_RX_STAT_AC15
189737. BNX2_EMAC_RX_STAT_AC16
189738. BNX2_EMAC_RX_STAT_AC17
189739. BNX2_EMAC_RX_STAT_AC18
189740. BNX2_EMAC_RX_STAT_AC19
189741. BNX2_EMAC_RX_STAT_AC2
189742. BNX2_EMAC_RX_STAT_AC20
189743. BNX2_EMAC_RX_STAT_AC21
189744. BNX2_EMAC_RX_STAT_AC22
189745. BNX2_EMAC_RX_STAT_AC3
189746. BNX2_EMAC_RX_STAT_AC4
189747. BNX2_EMAC_RX_STAT_AC5
189748. BNX2_EMAC_RX_STAT_AC6
189749. BNX2_EMAC_RX_STAT_AC7
189750. BNX2_EMAC_RX_STAT_AC8
189751. BNX2_EMAC_RX_STAT_AC9
189752. BNX2_EMAC_RX_STAT_AC_28
189753. BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS
189754. BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS
189755. BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS
189756. BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG
189757. BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS
189758. BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS
189759. BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS
189760. BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS
189761. BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS
189762. BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS
189763. BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS
189764. BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS
189765. BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS
189766. BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS
189767. BNX2_EMAC_RX_STAT_FALSECARRIERERRORS
189768. BNX2_EMAC_RX_STAT_IFHCINBADOCTETS
189769. BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS
189770. BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS
189771. BNX2_EMAC_RX_STAT_IFHCINOCTETS
189772. BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS
189773. BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED
189774. BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED
189775. BNX2_EMAC_RX_STAT_XOFFSTATEENTERED
189776. BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED
189777. BNX2_EMAC_SERDES_CNTL
189778. BNX2_EMAC_SERDES_CNTL_BGMAX
189779. BNX2_EMAC_SERDES_CNTL_BGMIN
189780. BNX2_EMAC_SERDES_CNTL_CDET_EN
189781. BNX2_EMAC_SERDES_CNTL_PLLTEST
189782. BNX2_EMAC_SERDES_CNTL_REGCTL12
189783. BNX2_EMAC_SERDES_CNTL_REGCTL25
189784. BNX2_EMAC_SERDES_CNTL_REMOTE_LBK
189785. BNX2_EMAC_SERDES_CNTL_REV_PHASE
189786. BNX2_EMAC_SERDES_CNTL_RXCKSEL
189787. BNX2_EMAC_SERDES_CNTL_RXG
189788. BNX2_EMAC_SERDES_CNTL_RXR
189789. BNX2_EMAC_SERDES_CNTL_SERDES_MODE
189790. BNX2_EMAC_SERDES_CNTL_TBI_LBK
189791. BNX2_EMAC_SERDES_CNTL_TXBIAS
189792. BNX2_EMAC_SERDES_CNTL_TXEDGE
189793. BNX2_EMAC_SERDES_CNTL_TXMODE
189794. BNX2_EMAC_SERDES_STATUS
189795. BNX2_EMAC_SERDES_STATUS_COMMA_DET
189796. BNX2_EMAC_SERDES_STATUS_RX_STAT
189797. BNX2_EMAC_STATUS
189798. BNX2_EMAC_STATUS_AP_ERROR
189799. BNX2_EMAC_STATUS_LINK
189800. BNX2_EMAC_STATUS_LINK_CHANGE
189801. BNX2_EMAC_STATUS_MI_COMPLETE
189802. BNX2_EMAC_STATUS_MI_INT
189803. BNX2_EMAC_STATUS_PARITY_ERROR_STATE
189804. BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE
189805. BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE
189806. BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE
189807. BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0
189808. BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE
189809. BNX2_EMAC_TXMAC_DEBUG0
189810. BNX2_EMAC_TXMAC_DEBUG1
189811. BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC
189812. BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE
189813. BNX2_EMAC_TXMAC_DEBUG1_DEFERRED
189814. BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME
189815. BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION
189816. BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER
189817. BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE
189818. BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0
189819. BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1
189820. BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2
189821. BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3
189822. BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE
189823. BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0
189824. BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0
189825. BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1
189826. BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE
189827. BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE
189828. BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER
189829. BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME
189830. BNX2_EMAC_TXMAC_DEBUG2
189831. BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF
189832. BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT
189833. BNX2_EMAC_TXMAC_DEBUG2_COL_BIT
189834. BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT
189835. BNX2_EMAC_TXMAC_DEBUG3
189836. BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE
189837. BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE
189838. BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC
189839. BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2
189840. BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3
189841. BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE
189842. BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC
189843. BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI
189844. BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT
189845. BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER
189846. BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER
189847. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE
189848. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF
189849. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM
189850. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1
189851. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2
189852. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA
189853. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM
189854. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT
189855. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE
189856. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM
189857. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1
189858. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2
189859. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD
189860. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB
189861. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG
189862. BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT
189863. BNX2_EMAC_TXMAC_DEBUG3_XOFF
189864. BNX2_EMAC_TXMAC_DEBUG4
189865. BNX2_EMAC_TXMAC_DEBUG4_ADVANCE
189866. BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC
189867. BNX2_EMAC_TXMAC_DEBUG4_BURSTING
189868. BNX2_EMAC_TXMAC_DEBUG4_COLLIDING
189869. BNX2_EMAC_TXMAC_DEBUG4_COL_IN
189870. BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC
189871. BNX2_EMAC_TXMAC_DEBUG4_GO
189872. BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER
189873. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER
189874. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE
189875. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD
189876. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1
189877. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2
189878. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE
189879. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1
189880. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2
189881. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3
189882. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1
189883. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2
189884. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3
189885. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME
189886. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE
189887. BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT
189888. BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND
189889. BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING
189890. BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED
189891. BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID
189892. BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC
189893. BNX2_EMAC_TX_LENGTHS
189894. BNX2_EMAC_TX_LENGTHS_IPG
189895. BNX2_EMAC_TX_LENGTHS_IPG_CRS
189896. BNX2_EMAC_TX_LENGTHS_SLOT
189897. BNX2_EMAC_TX_MODE
189898. BNX2_EMAC_TX_MODE_BIG_BACKOFF
189899. BNX2_EMAC_TX_MODE_CS16_TEST
189900. BNX2_EMAC_TX_MODE_EXT_PAUSE_EN
189901. BNX2_EMAC_TX_MODE_FLOW_EN
189902. BNX2_EMAC_TX_MODE_LINK_AWARE
189903. BNX2_EMAC_TX_MODE_LONG_PAUSE
189904. BNX2_EMAC_TX_MODE_RESET
189905. BNX2_EMAC_TX_RATE_LIMIT_CTRL
189906. BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN
189907. BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC
189908. BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM
189909. BNX2_EMAC_TX_STATUS
189910. BNX2_EMAC_TX_STATUS_CS16_ERROR
189911. BNX2_EMAC_TX_STATUS_LINK_UP
189912. BNX2_EMAC_TX_STATUS_UNDERRUN
189913. BNX2_EMAC_TX_STATUS_XOFFED
189914. BNX2_EMAC_TX_STATUS_XOFF_SENT
189915. BNX2_EMAC_TX_STATUS_XON_SENT
189916. BNX2_EMAC_TX_STAT_AC0
189917. BNX2_EMAC_TX_STAT_AC1
189918. BNX2_EMAC_TX_STAT_AC10
189919. BNX2_EMAC_TX_STAT_AC11
189920. BNX2_EMAC_TX_STAT_AC12
189921. BNX2_EMAC_TX_STAT_AC13
189922. BNX2_EMAC_TX_STAT_AC14
189923. BNX2_EMAC_TX_STAT_AC15
189924. BNX2_EMAC_TX_STAT_AC16
189925. BNX2_EMAC_TX_STAT_AC17
189926. BNX2_EMAC_TX_STAT_AC18
189927. BNX2_EMAC_TX_STAT_AC19
189928. BNX2_EMAC_TX_STAT_AC2
189929. BNX2_EMAC_TX_STAT_AC20
189930. BNX2_EMAC_TX_STAT_AC3
189931. BNX2_EMAC_TX_STAT_AC4
189932. BNX2_EMAC_TX_STAT_AC5
189933. BNX2_EMAC_TX_STAT_AC6
189934. BNX2_EMAC_TX_STAT_AC7
189935. BNX2_EMAC_TX_STAT_AC8
189936. BNX2_EMAC_TX_STAT_AC9
189937. BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS
189938. BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS
189939. BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS
189940. BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS
189941. BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES
189942. BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES
189943. BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS
189944. BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS
189945. BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS
189946. BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS
189947. BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS
189948. BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS
189949. BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS
189950. BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS
189951. BNX2_EMAC_TX_STAT_FLOWCONTROLDONE
189952. BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS
189953. BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS
189954. BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS
189955. BNX2_EMAC_TX_STAT_IFHCOUTOCTETS
189956. BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS
189957. BNX2_EMAC_TX_STAT_OUTXOFFSENT
189958. BNX2_EMAC_TX_STAT_OUTXONSENT
189959. BNX2_END_UNICAST_ADDRESS_INDEX
189960. BNX2_ERR_PEND_R2T_IN_CLEANUP
189961. BNX2_FLAG_AER_ENABLED
189962. BNX2_FLAG_ASF_ENABLE
189963. BNX2_FLAG_BROKEN_STATS
189964. BNX2_FLAG_CAN_KEEP_VLAN
189965. BNX2_FLAG_JUMBO_BROKEN
189966. BNX2_FLAG_MSIX_CAP
189967. BNX2_FLAG_MSI_CAP
189968. BNX2_FLAG_NO_WOL
189969. BNX2_FLAG_ONE_SHOT_MSI
189970. BNX2_FLAG_PCIE
189971. BNX2_FLAG_PCIX
189972. BNX2_FLAG_PCI_32BIT
189973. BNX2_FLAG_USING_MSI
189974. BNX2_FLAG_USING_MSIX
189975. BNX2_FLAG_USING_MSI_OR_MSIX
189976. BNX2_FL_NOT_5709
189977. BNX2_FTQ_ENTRY
189978. BNX2_FW_ACK_DRV_SIGNATURE
189979. BNX2_FW_ACK_TIME_OUT_MS
189980. BNX2_FW_CAP_BC_CAN_KEEP_VLAN
189981. BNX2_FW_CAP_CAN_KEEP_VLAN
189982. BNX2_FW_CAP_MB
189983. BNX2_FW_CAP_MFW_CAN_KEEP_VLAN
189984. BNX2_FW_CAP_REMOTE_PHY_CAPABLE
189985. BNX2_FW_CAP_REMOTE_PHY_PRESENT
189986. BNX2_FW_CAP_SIGNATURE
189987. BNX2_FW_CAP_SIGNATURE_MASK
189988. BNX2_FW_EVT_CODE_LINK_EVENT
189989. BNX2_FW_EVT_CODE_MB
189990. BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT
189991. BNX2_FW_MAX_ISCSI_CONN
189992. BNX2_FW_MB
189993. BNX2_FW_MSG_ACK
189994. BNX2_FW_MSG_STATUS_FAILURE
189995. BNX2_FW_MSG_STATUS_MASK
189996. BNX2_FW_MSG_STATUS_OK
189997. BNX2_FW_RX_DROP_COUNT
189998. BNX2_FW_RX_LOW_LATENCY
189999. BNX2_H
190000. BNX2_HC_ATTN_BITS_ENABLE
190001. BNX2_HC_CMD_TICKS
190002. BNX2_HC_CMD_TICKS_1
190003. BNX2_HC_CMD_TICKS_1_INT
190004. BNX2_HC_CMD_TICKS_1_VALUE
190005. BNX2_HC_CMD_TICKS_2
190006. BNX2_HC_CMD_TICKS_2_INT
190007. BNX2_HC_CMD_TICKS_2_VALUE
190008. BNX2_HC_CMD_TICKS_3
190009. BNX2_HC_CMD_TICKS_3_INT
190010. BNX2_HC_CMD_TICKS_3_VALUE
190011. BNX2_HC_CMD_TICKS_4
190012. BNX2_HC_CMD_TICKS_4_INT
190013. BNX2_HC_CMD_TICKS_4_VALUE
190014. BNX2_HC_CMD_TICKS_5
190015. BNX2_HC_CMD_TICKS_5_INT
190016. BNX2_HC_CMD_TICKS_5_VALUE
190017. BNX2_HC_CMD_TICKS_6
190018. BNX2_HC_CMD_TICKS_6_INT
190019. BNX2_HC_CMD_TICKS_6_VALUE
190020. BNX2_HC_CMD_TICKS_7
190021. BNX2_HC_CMD_TICKS_7_INT
190022. BNX2_HC_CMD_TICKS_7_VALUE
190023. BNX2_HC_CMD_TICKS_8
190024. BNX2_HC_CMD_TICKS_8_INT
190025. BNX2_HC_CMD_TICKS_8_VALUE
190026. BNX2_HC_CMD_TICKS_INT
190027. BNX2_HC_CMD_TICKS_OFF
190028. BNX2_HC_CMD_TICKS_VALUE
190029. BNX2_HC_COALESCE_NOW
190030. BNX2_HC_COALESCE_NOW_COAL_NOW
190031. BNX2_HC_COALESCE_NOW_COAL_NOW_WO_INT
190032. BNX2_HC_COALESCE_NOW_COAL_ON_NXT_EVENT
190033. BNX2_HC_COMMAND
190034. BNX2_HC_COMMAND_CLR_STAT_NOW
190035. BNX2_HC_COMMAND_COAL_NOW
190036. BNX2_HC_COMMAND_COAL_NOW_WO_INT
190037. BNX2_HC_COMMAND_COAL_ON_NEXT_EVENT
190038. BNX2_HC_COMMAND_ENABLE
190039. BNX2_HC_COMMAND_FORCE_INT
190040. BNX2_HC_COMMAND_FORCE_INT_FREE
190041. BNX2_HC_COMMAND_FORCE_INT_HIGH
190042. BNX2_HC_COMMAND_FORCE_INT_LOW
190043. BNX2_HC_COMMAND_FORCE_INT_NULL
190044. BNX2_HC_COMMAND_MAIN_PWR_INT
190045. BNX2_HC_COMMAND_SKIP_ABORT
190046. BNX2_HC_COMMAND_STATS_NOW
190047. BNX2_HC_COMP_PROD_TRIP
190048. BNX2_HC_COMP_PROD_TRIP_1
190049. BNX2_HC_COMP_PROD_TRIP_1_INT
190050. BNX2_HC_COMP_PROD_TRIP_1_VALUE
190051. BNX2_HC_COMP_PROD_TRIP_2
190052. BNX2_HC_COMP_PROD_TRIP_2_INT
190053. BNX2_HC_COMP_PROD_TRIP_2_VALUE
190054. BNX2_HC_COMP_PROD_TRIP_3
190055. BNX2_HC_COMP_PROD_TRIP_3_INT
190056. BNX2_HC_COMP_PROD_TRIP_3_VALUE
190057. BNX2_HC_COMP_PROD_TRIP_4
190058. BNX2_HC_COMP_PROD_TRIP_4_INT
190059. BNX2_HC_COMP_PROD_TRIP_4_VALUE
190060. BNX2_HC_COMP_PROD_TRIP_5
190061. BNX2_HC_COMP_PROD_TRIP_5_INT
190062. BNX2_HC_COMP_PROD_TRIP_5_VALUE
190063. BNX2_HC_COMP_PROD_TRIP_6
190064. BNX2_HC_COMP_PROD_TRIP_6_INT
190065. BNX2_HC_COMP_PROD_TRIP_6_VALUE
190066. BNX2_HC_COMP_PROD_TRIP_7
190067. BNX2_HC_COMP_PROD_TRIP_7_INT
190068. BNX2_HC_COMP_PROD_TRIP_7_VALUE
190069. BNX2_HC_COMP_PROD_TRIP_8
190070. BNX2_HC_COMP_PROD_TRIP_8_INT
190071. BNX2_HC_COMP_PROD_TRIP_8_VALUE
190072. BNX2_HC_COMP_PROD_TRIP_INT
190073. BNX2_HC_COMP_PROD_TRIP_OFF
190074. BNX2_HC_COMP_PROD_TRIP_VALUE
190075. BNX2_HC_COM_TICKS
190076. BNX2_HC_COM_TICKS_1
190077. BNX2_HC_COM_TICKS_1_INT
190078. BNX2_HC_COM_TICKS_1_VALUE
190079. BNX2_HC_COM_TICKS_2
190080. BNX2_HC_COM_TICKS_2_INT
190081. BNX2_HC_COM_TICKS_2_VALUE
190082. BNX2_HC_COM_TICKS_3
190083. BNX2_HC_COM_TICKS_3_INT
190084. BNX2_HC_COM_TICKS_3_VALUE
190085. BNX2_HC_COM_TICKS_4
190086. BNX2_HC_COM_TICKS_4_INT
190087. BNX2_HC_COM_TICKS_4_VALUE
190088. BNX2_HC_COM_TICKS_5
190089. BNX2_HC_COM_TICKS_5_INT
190090. BNX2_HC_COM_TICKS_5_VALUE
190091. BNX2_HC_COM_TICKS_6
190092. BNX2_HC_COM_TICKS_6_INT
190093. BNX2_HC_COM_TICKS_6_VALUE
190094. BNX2_HC_COM_TICKS_7
190095. BNX2_HC_COM_TICKS_7_INT
190096. BNX2_HC_COM_TICKS_7_VALUE
190097. BNX2_HC_COM_TICKS_8
190098. BNX2_HC_COM_TICKS_8_INT
190099. BNX2_HC_COM_TICKS_8_VALUE
190100. BNX2_HC_COM_TICKS_INT
190101. BNX2_HC_COM_TICKS_OFF
190102. BNX2_HC_COM_TICKS_VALUE
190103. BNX2_HC_CONFIG
190104. BNX2_HC_CONFIG_CMD_TMR_MODE
190105. BNX2_HC_CONFIG_COLLECT_STATS
190106. BNX2_HC_CONFIG_COM_TMR_MODE
190107. BNX2_HC_CONFIG_GEN_STAT_AVG_INTR
190108. BNX2_HC_CONFIG_ONE_SHOT
190109. BNX2_HC_CONFIG_PER_COLLECT_LIMIT
190110. BNX2_HC_CONFIG_PER_MODE
190111. BNX2_HC_CONFIG_RX_TMR_MODE
190112. BNX2_HC_CONFIG_SB_ADDR_INC
190113. BNX2_HC_CONFIG_SB_ADDR_INC_1024B
190114. BNX2_HC_CONFIG_SB_ADDR_INC_128B
190115. BNX2_HC_CONFIG_SB_ADDR_INC_2048B
190116. BNX2_HC_CONFIG_SB_ADDR_INC_256B
190117. BNX2_HC_CONFIG_SB_ADDR_INC_4096B
190118. BNX2_HC_CONFIG_SB_ADDR_INC_512B
190119. BNX2_HC_CONFIG_SB_ADDR_INC_64B
190120. BNX2_HC_CONFIG_SB_ADDR_INC_8192B
190121. BNX2_HC_CONFIG_SET_MASK_AT_RD
190122. BNX2_HC_CONFIG_STATISTIC_PRIORITY
190123. BNX2_HC_CONFIG_STATUS_PRIORITY
190124. BNX2_HC_CONFIG_STAT_MEM_ADDR
190125. BNX2_HC_CONFIG_TX_SEL
190126. BNX2_HC_CONFIG_TX_TMR_MODE
190127. BNX2_HC_CONFIG_UNMASK_ALL
190128. BNX2_HC_CONFIG_USE_INT_PARAM
190129. BNX2_HC_DEBUG_VECT_PEEK
190130. BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN
190131. BNX2_HC_DEBUG_VECT_PEEK_1_SEL
190132. BNX2_HC_DEBUG_VECT_PEEK_1_VALUE
190133. BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN
190134. BNX2_HC_DEBUG_VECT_PEEK_2_SEL
190135. BNX2_HC_DEBUG_VECT_PEEK_2_VALUE
190136. BNX2_HC_MSIX_BIT_VECTOR
190137. BNX2_HC_MSIX_BIT_VECTOR_VAL
190138. BNX2_HC_PERIODIC_TICKS
190139. BNX2_HC_PERIODIC_TICKS_1
190140. BNX2_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS
190141. BNX2_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS
190142. BNX2_HC_PERIODIC_TICKS_2
190143. BNX2_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS
190144. BNX2_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS
190145. BNX2_HC_PERIODIC_TICKS_3
190146. BNX2_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS
190147. BNX2_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS
190148. BNX2_HC_PERIODIC_TICKS_4
190149. BNX2_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS
190150. BNX2_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS
190151. BNX2_HC_PERIODIC_TICKS_5
190152. BNX2_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS
190153. BNX2_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS
190154. BNX2_HC_PERIODIC_TICKS_6
190155. BNX2_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS
190156. BNX2_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS
190157. BNX2_HC_PERIODIC_TICKS_7
190158. BNX2_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS
190159. BNX2_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS
190160. BNX2_HC_PERIODIC_TICKS_8
190161. BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS
190162. BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS
190163. BNX2_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS
190164. BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS
190165. BNX2_HC_RX_QUICK_CONS_TRIP
190166. BNX2_HC_RX_QUICK_CONS_TRIP_1
190167. BNX2_HC_RX_QUICK_CONS_TRIP_1_INT
190168. BNX2_HC_RX_QUICK_CONS_TRIP_1_VALUE
190169. BNX2_HC_RX_QUICK_CONS_TRIP_2
190170. BNX2_HC_RX_QUICK_CONS_TRIP_2_INT
190171. BNX2_HC_RX_QUICK_CONS_TRIP_2_VALUE
190172. BNX2_HC_RX_QUICK_CONS_TRIP_3
190173. BNX2_HC_RX_QUICK_CONS_TRIP_3_INT
190174. BNX2_HC_RX_QUICK_CONS_TRIP_3_VALUE
190175. BNX2_HC_RX_QUICK_CONS_TRIP_4
190176. BNX2_HC_RX_QUICK_CONS_TRIP_4_INT
190177. BNX2_HC_RX_QUICK_CONS_TRIP_4_VALUE
190178. BNX2_HC_RX_QUICK_CONS_TRIP_5
190179. BNX2_HC_RX_QUICK_CONS_TRIP_5_INT
190180. BNX2_HC_RX_QUICK_CONS_TRIP_5_VALUE
190181. BNX2_HC_RX_QUICK_CONS_TRIP_6
190182. BNX2_HC_RX_QUICK_CONS_TRIP_6_INT
190183. BNX2_HC_RX_QUICK_CONS_TRIP_6_VALUE
190184. BNX2_HC_RX_QUICK_CONS_TRIP_7
190185. BNX2_HC_RX_QUICK_CONS_TRIP_7_INT
190186. BNX2_HC_RX_QUICK_CONS_TRIP_7_VALUE
190187. BNX2_HC_RX_QUICK_CONS_TRIP_8
190188. BNX2_HC_RX_QUICK_CONS_TRIP_8_INT
190189. BNX2_HC_RX_QUICK_CONS_TRIP_8_VALUE
190190. BNX2_HC_RX_QUICK_CONS_TRIP_INT
190191. BNX2_HC_RX_QUICK_CONS_TRIP_OFF
190192. BNX2_HC_RX_QUICK_CONS_TRIP_VALUE
190193. BNX2_HC_RX_TICKS
190194. BNX2_HC_RX_TICKS_1
190195. BNX2_HC_RX_TICKS_1_INT
190196. BNX2_HC_RX_TICKS_1_VALUE
190197. BNX2_HC_RX_TICKS_2
190198. BNX2_HC_RX_TICKS_2_INT
190199. BNX2_HC_RX_TICKS_2_VALUE
190200. BNX2_HC_RX_TICKS_3
190201. BNX2_HC_RX_TICKS_3_INT
190202. BNX2_HC_RX_TICKS_3_VALUE
190203. BNX2_HC_RX_TICKS_4
190204. BNX2_HC_RX_TICKS_4_INT
190205. BNX2_HC_RX_TICKS_4_VALUE
190206. BNX2_HC_RX_TICKS_5
190207. BNX2_HC_RX_TICKS_5_INT
190208. BNX2_HC_RX_TICKS_5_VALUE
190209. BNX2_HC_RX_TICKS_6
190210. BNX2_HC_RX_TICKS_6_INT
190211. BNX2_HC_RX_TICKS_6_VALUE
190212. BNX2_HC_RX_TICKS_7
190213. BNX2_HC_RX_TICKS_7_INT
190214. BNX2_HC_RX_TICKS_7_VALUE
190215. BNX2_HC_RX_TICKS_8
190216. BNX2_HC_RX_TICKS_8_INT
190217. BNX2_HC_RX_TICKS_8_VALUE
190218. BNX2_HC_RX_TICKS_INT
190219. BNX2_HC_RX_TICKS_OFF
190220. BNX2_HC_RX_TICKS_VALUE
190221. BNX2_HC_SB_CONFIG_1
190222. BNX2_HC_SB_CONFIG_1_CMD_TMR_MODE
190223. BNX2_HC_SB_CONFIG_1_COM_TMR_MODE
190224. BNX2_HC_SB_CONFIG_1_ONE_SHOT
190225. BNX2_HC_SB_CONFIG_1_PER_COLLECT_LIMIT
190226. BNX2_HC_SB_CONFIG_1_PER_MODE
190227. BNX2_HC_SB_CONFIG_1_RX_TMR_MODE
190228. BNX2_HC_SB_CONFIG_1_TX_TMR_MODE
190229. BNX2_HC_SB_CONFIG_1_USE_INT_PARAM
190230. BNX2_HC_SB_CONFIG_2
190231. BNX2_HC_SB_CONFIG_2_CMD_TMR_MODE
190232. BNX2_HC_SB_CONFIG_2_COM_TMR_MODE
190233. BNX2_HC_SB_CONFIG_2_ONE_SHOT
190234. BNX2_HC_SB_CONFIG_2_PER_COLLECT_LIMIT
190235. BNX2_HC_SB_CONFIG_2_PER_MODE
190236. BNX2_HC_SB_CONFIG_2_RX_TMR_MODE
190237. BNX2_HC_SB_CONFIG_2_TX_TMR_MODE
190238. BNX2_HC_SB_CONFIG_2_USE_INT_PARAM
190239. BNX2_HC_SB_CONFIG_3
190240. BNX2_HC_SB_CONFIG_3_CMD_TMR_MODE
190241. BNX2_HC_SB_CONFIG_3_COM_TMR_MODE
190242. BNX2_HC_SB_CONFIG_3_ONE_SHOT
190243. BNX2_HC_SB_CONFIG_3_PER_COLLECT_LIMIT
190244. BNX2_HC_SB_CONFIG_3_PER_MODE
190245. BNX2_HC_SB_CONFIG_3_RX_TMR_MODE
190246. BNX2_HC_SB_CONFIG_3_TX_TMR_MODE
190247. BNX2_HC_SB_CONFIG_3_USE_INT_PARAM
190248. BNX2_HC_SB_CONFIG_4
190249. BNX2_HC_SB_CONFIG_4_CMD_TMR_MODE
190250. BNX2_HC_SB_CONFIG_4_COM_TMR_MODE
190251. BNX2_HC_SB_CONFIG_4_ONE_SHOT
190252. BNX2_HC_SB_CONFIG_4_PER_COLLECT_LIMIT
190253. BNX2_HC_SB_CONFIG_4_PER_MODE
190254. BNX2_HC_SB_CONFIG_4_RX_TMR_MODE
190255. BNX2_HC_SB_CONFIG_4_TX_TMR_MODE
190256. BNX2_HC_SB_CONFIG_4_USE_INT_PARAM
190257. BNX2_HC_SB_CONFIG_5
190258. BNX2_HC_SB_CONFIG_5_CMD_TMR_MODE
190259. BNX2_HC_SB_CONFIG_5_COM_TMR_MODE
190260. BNX2_HC_SB_CONFIG_5_ONE_SHOT
190261. BNX2_HC_SB_CONFIG_5_PER_COLLECT_LIMIT
190262. BNX2_HC_SB_CONFIG_5_PER_MODE
190263. BNX2_HC_SB_CONFIG_5_RX_TMR_MODE
190264. BNX2_HC_SB_CONFIG_5_TX_TMR_MODE
190265. BNX2_HC_SB_CONFIG_5_USE_INT_PARAM
190266. BNX2_HC_SB_CONFIG_6
190267. BNX2_HC_SB_CONFIG_6_CMD_TMR_MODE
190268. BNX2_HC_SB_CONFIG_6_COM_TMR_MODE
190269. BNX2_HC_SB_CONFIG_6_ONE_SHOT
190270. BNX2_HC_SB_CONFIG_6_PER_COLLECT_LIMIT
190271. BNX2_HC_SB_CONFIG_6_PER_MODE
190272. BNX2_HC_SB_CONFIG_6_RX_TMR_MODE
190273. BNX2_HC_SB_CONFIG_6_TX_TMR_MODE
190274. BNX2_HC_SB_CONFIG_6_USE_INT_PARAM
190275. BNX2_HC_SB_CONFIG_7
190276. BNX2_HC_SB_CONFIG_7_CMD_TMR_MODE
190277. BNX2_HC_SB_CONFIG_7_COM_TMR_MODE
190278. BNX2_HC_SB_CONFIG_7_ONE_SHOT
190279. BNX2_HC_SB_CONFIG_7_PER_COLLECT_LIMIT
190280. BNX2_HC_SB_CONFIG_7_PER_MODE
190281. BNX2_HC_SB_CONFIG_7_RX_TMR_MODE
190282. BNX2_HC_SB_CONFIG_7_TX_TMR_MODE
190283. BNX2_HC_SB_CONFIG_7_USE_INT_PARAM
190284. BNX2_HC_SB_CONFIG_8
190285. BNX2_HC_SB_CONFIG_8_CMD_TMR_MODE
190286. BNX2_HC_SB_CONFIG_8_COM_TMR_MODE
190287. BNX2_HC_SB_CONFIG_8_ONE_SHOT
190288. BNX2_HC_SB_CONFIG_8_PER_COLLECT_LIMIT
190289. BNX2_HC_SB_CONFIG_8_PER_MODE
190290. BNX2_HC_SB_CONFIG_8_RX_TMR_MODE
190291. BNX2_HC_SB_CONFIG_8_TX_TMR_MODE
190292. BNX2_HC_SB_CONFIG_8_USE_INT_PARAM
190293. BNX2_HC_SB_CONFIG_SIZE
190294. BNX2_HC_STATISTICS_ADDR_H
190295. BNX2_HC_STATISTICS_ADDR_L
190296. BNX2_HC_STATS_INTERRUPT_STATUS
190297. BNX2_HC_STATS_INTERRUPT_STATUS_INT_STATUS
190298. BNX2_HC_STATS_INTERRUPT_STATUS_SB_STATUS
190299. BNX2_HC_STATS_TICKS
190300. BNX2_HC_STATS_TICKS_HC_STAT_TICKS
190301. BNX2_HC_STATUS
190302. BNX2_HC_STATUS_ADDR_H
190303. BNX2_HC_STATUS_ADDR_L
190304. BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT
190305. BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT
190306. BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT
190307. BNX2_HC_STATUS_CORE_CLK_CNT_STAT
190308. BNX2_HC_STATUS_MASTER_ABORT
190309. BNX2_HC_STATUS_NUM_INT_GEN_STAT
190310. BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT
190311. BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT
190312. BNX2_HC_STATUS_PARITY_ERROR_STATE
190313. BNX2_HC_STATUS_PCI_CLK_CNT_STAT
190314. BNX2_HC_STAT_COLLECT_TICKS
190315. BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS
190316. BNX2_HC_STAT_GEN_SEL_0
190317. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0
190318. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT
190319. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT
190320. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT
190321. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0
190322. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1
190323. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10
190324. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11
190325. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2
190326. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3
190327. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4
190328. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5
190329. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6
190330. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7
190331. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8
190332. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9
190333. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT
190334. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT
190335. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0
190336. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1
190337. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2
190338. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3
190339. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4
190340. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5
190341. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6
190342. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7
190343. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT
190344. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT
190345. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT
190346. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS
190347. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI
190348. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI
190349. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI
190350. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS
190351. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI
190352. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64
190353. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64
190354. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT
190355. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT
190356. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT
190357. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT
190358. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT
190359. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT
190360. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT
190361. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT
190362. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT
190363. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT
190364. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK
190365. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI
190366. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI
190367. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI
190368. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI
190369. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI
190370. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI
190371. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI
190372. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI
190373. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK
190374. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI
190375. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI
190376. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI
190377. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI
190378. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI
190379. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI
190380. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI
190381. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI
190382. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK
190383. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI
190384. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI
190385. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI
190386. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI
190387. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI
190388. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI
190389. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI
190390. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI
190391. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN
190392. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI
190393. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI
190394. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI
190395. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI
190396. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI
190397. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI
190398. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI
190399. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI
190400. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR
190401. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI
190402. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI
190403. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI
190404. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI
190405. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI
190406. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI
190407. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI
190408. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI
190409. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS
190410. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI
190411. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI
190412. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI
190413. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI
190414. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI
190415. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI
190416. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI
190417. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI
190418. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT
190419. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT
190420. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT
190421. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0
190422. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1
190423. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2
190424. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3
190425. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4
190426. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5
190427. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6
190428. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7
190429. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT
190430. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI
190431. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT
190432. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT
190433. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS
190434. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS
190435. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT
190436. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT
190437. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT
190438. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT
190439. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT
190440. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI
190441. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI
190442. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI
190443. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT
190444. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT
190445. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT
190446. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0
190447. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1
190448. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2
190449. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3
190450. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4
190451. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5
190452. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT
190453. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT
190454. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0
190455. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1
190456. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10
190457. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11
190458. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2
190459. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3
190460. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4
190461. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5
190462. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6
190463. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7
190464. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8
190465. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9
190466. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT
190467. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT
190468. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT
190469. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT
190470. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT
190471. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT
190472. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT
190473. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT
190474. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT
190475. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT
190476. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT
190477. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT
190478. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT
190479. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT
190480. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0
190481. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1
190482. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2
190483. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3
190484. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT
190485. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT
190486. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT
190487. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT
190488. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0
190489. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1
190490. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2
190491. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3
190492. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4
190493. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5
190494. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6
190495. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7
190496. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI
190497. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI
190498. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI
190499. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI
190500. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI
190501. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI
190502. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI
190503. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI
190504. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI
190505. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI
190506. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI
190507. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI
190508. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI
190509. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1
190510. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI
190511. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2
190512. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI
190513. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3
190514. BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI
190515. BNX2_HC_STAT_GEN_SEL_1
190516. BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4
190517. BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI
190518. BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5
190519. BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI
190520. BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6
190521. BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI
190522. BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7
190523. BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI
190524. BNX2_HC_STAT_GEN_SEL_2
190525. BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10
190526. BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI
190527. BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11
190528. BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI
190529. BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8
190530. BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI
190531. BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9
190532. BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI
190533. BNX2_HC_STAT_GEN_SEL_3
190534. BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12
190535. BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI
190536. BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13
190537. BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI
190538. BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14
190539. BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI
190540. BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15
190541. BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI
190542. BNX2_HC_STAT_GEN_STAT0
190543. BNX2_HC_STAT_GEN_STAT1
190544. BNX2_HC_STAT_GEN_STAT10
190545. BNX2_HC_STAT_GEN_STAT11
190546. BNX2_HC_STAT_GEN_STAT12
190547. BNX2_HC_STAT_GEN_STAT13
190548. BNX2_HC_STAT_GEN_STAT14
190549. BNX2_HC_STAT_GEN_STAT15
190550. BNX2_HC_STAT_GEN_STAT2
190551. BNX2_HC_STAT_GEN_STAT3
190552. BNX2_HC_STAT_GEN_STAT4
190553. BNX2_HC_STAT_GEN_STAT5
190554. BNX2_HC_STAT_GEN_STAT6
190555. BNX2_HC_STAT_GEN_STAT7
190556. BNX2_HC_STAT_GEN_STAT8
190557. BNX2_HC_STAT_GEN_STAT9
190558. BNX2_HC_STAT_GEN_STAT_AC
190559. BNX2_HC_STAT_GEN_STAT_AC0
190560. BNX2_HC_STAT_GEN_STAT_AC1
190561. BNX2_HC_STAT_GEN_STAT_AC10
190562. BNX2_HC_STAT_GEN_STAT_AC11
190563. BNX2_HC_STAT_GEN_STAT_AC12
190564. BNX2_HC_STAT_GEN_STAT_AC13
190565. BNX2_HC_STAT_GEN_STAT_AC14
190566. BNX2_HC_STAT_GEN_STAT_AC15
190567. BNX2_HC_STAT_GEN_STAT_AC2
190568. BNX2_HC_STAT_GEN_STAT_AC3
190569. BNX2_HC_STAT_GEN_STAT_AC4
190570. BNX2_HC_STAT_GEN_STAT_AC5
190571. BNX2_HC_STAT_GEN_STAT_AC6
190572. BNX2_HC_STAT_GEN_STAT_AC7
190573. BNX2_HC_STAT_GEN_STAT_AC8
190574. BNX2_HC_STAT_GEN_STAT_AC9
190575. BNX2_HC_STAT_MEM_DATA
190576. BNX2_HC_TX_QUICK_CONS_TRIP
190577. BNX2_HC_TX_QUICK_CONS_TRIP_1
190578. BNX2_HC_TX_QUICK_CONS_TRIP_1_INT
190579. BNX2_HC_TX_QUICK_CONS_TRIP_1_VALUE
190580. BNX2_HC_TX_QUICK_CONS_TRIP_2
190581. BNX2_HC_TX_QUICK_CONS_TRIP_2_INT
190582. BNX2_HC_TX_QUICK_CONS_TRIP_2_VALUE
190583. BNX2_HC_TX_QUICK_CONS_TRIP_3
190584. BNX2_HC_TX_QUICK_CONS_TRIP_3_INT
190585. BNX2_HC_TX_QUICK_CONS_TRIP_3_VALUE
190586. BNX2_HC_TX_QUICK_CONS_TRIP_4
190587. BNX2_HC_TX_QUICK_CONS_TRIP_4_INT
190588. BNX2_HC_TX_QUICK_CONS_TRIP_4_VALUE
190589. BNX2_HC_TX_QUICK_CONS_TRIP_5
190590. BNX2_HC_TX_QUICK_CONS_TRIP_5_INT
190591. BNX2_HC_TX_QUICK_CONS_TRIP_5_VALUE
190592. BNX2_HC_TX_QUICK_CONS_TRIP_6
190593. BNX2_HC_TX_QUICK_CONS_TRIP_6_INT
190594. BNX2_HC_TX_QUICK_CONS_TRIP_6_VALUE
190595. BNX2_HC_TX_QUICK_CONS_TRIP_7
190596. BNX2_HC_TX_QUICK_CONS_TRIP_7_INT
190597. BNX2_HC_TX_QUICK_CONS_TRIP_7_VALUE
190598. BNX2_HC_TX_QUICK_CONS_TRIP_8
190599. BNX2_HC_TX_QUICK_CONS_TRIP_8_INT
190600. BNX2_HC_TX_QUICK_CONS_TRIP_8_VALUE
190601. BNX2_HC_TX_QUICK_CONS_TRIP_INT
190602. BNX2_HC_TX_QUICK_CONS_TRIP_OFF
190603. BNX2_HC_TX_QUICK_CONS_TRIP_VALUE
190604. BNX2_HC_TX_TICKS
190605. BNX2_HC_TX_TICKS_1
190606. BNX2_HC_TX_TICKS_1_INT
190607. BNX2_HC_TX_TICKS_1_VALUE
190608. BNX2_HC_TX_TICKS_2
190609. BNX2_HC_TX_TICKS_2_INT
190610. BNX2_HC_TX_TICKS_2_VALUE
190611. BNX2_HC_TX_TICKS_3
190612. BNX2_HC_TX_TICKS_3_INT
190613. BNX2_HC_TX_TICKS_3_VALUE
190614. BNX2_HC_TX_TICKS_4
190615. BNX2_HC_TX_TICKS_4_INT
190616. BNX2_HC_TX_TICKS_4_VALUE
190617. BNX2_HC_TX_TICKS_5
190618. BNX2_HC_TX_TICKS_5_INT
190619. BNX2_HC_TX_TICKS_5_VALUE
190620. BNX2_HC_TX_TICKS_6
190621. BNX2_HC_TX_TICKS_6_INT
190622. BNX2_HC_TX_TICKS_6_VALUE
190623. BNX2_HC_TX_TICKS_7
190624. BNX2_HC_TX_TICKS_7_INT
190625. BNX2_HC_TX_TICKS_7_VALUE
190626. BNX2_HC_TX_TICKS_8
190627. BNX2_HC_TX_TICKS_8_INT
190628. BNX2_HC_TX_TICKS_8_VALUE
190629. BNX2_HC_TX_TICKS_INT
190630. BNX2_HC_TX_TICKS_OFF
190631. BNX2_HC_TX_TICKS_VALUE
190632. BNX2_HC_VIS
190633. BNX2_HC_VIS_1
190634. BNX2_HC_VIS_1_DURING_SW_INTACK_STATE
190635. BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT
190636. BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE
190637. BNX2_HC_VIS_1_HW_INTACK_STATE
190638. BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT
190639. BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE
190640. BNX2_HC_VIS_1_INT_B
190641. BNX2_HC_VIS_1_INT_GEN_STATE
190642. BNX2_HC_VIS_1_INT_GEN_STATE_DLE
190643. BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT
190644. BNX2_HC_VIS_1_MAILBOX_COUNT_STATE
190645. BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT
190646. BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE
190647. BNX2_HC_VIS_1_RAM_RD_ARB_STATE
190648. BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN
190649. BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA
190650. BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE
190651. BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN
190652. BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE
190653. BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT
190654. BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE
190655. BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT
190656. BNX2_HC_VIS_1_RAM_WR_ARB_STATE
190657. BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR
190658. BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL
190659. BNX2_HC_VIS_1_STAT_CHAN_ID
190660. BNX2_HC_VIS_1_SW_INTACK_STATE
190661. BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT
190662. BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE
190663. BNX2_HC_VIS_DMA_MSI_STATE
190664. BNX2_HC_VIS_DMA_STAT_STATE
190665. BNX2_HC_VIS_DMA_STAT_STATE_ABORT
190666. BNX2_HC_VIS_DMA_STAT_STATE_COMP
190667. BNX2_HC_VIS_DMA_STAT_STATE_IDLE
190668. BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA
190669. BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM
190670. BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA
190671. BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM
190672. BNX2_HC_VIS_DMA_STAT_STATE_WAIT
190673. BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP
190674. BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1
190675. BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2
190676. BNX2_HC_VIS_STATISTIC_DMA_EN_STATE
190677. BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT
190678. BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE
190679. BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START
190680. BNX2_HC_VIS_STAT_BUILD_STATE
190681. BNX2_HC_VIS_STAT_BUILD_STATE_DMA
190682. BNX2_HC_VIS_STAT_BUILD_STATE_IDLE
190683. BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL
190684. BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA
190685. BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH
190686. BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW
190687. BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST
190688. BNX2_HC_VIS_STAT_BUILD_STATE_START
190689. BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32
190690. BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64
190691. BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE
190692. BNX2_ISCSI_CTX_MAP
190693. BNX2_ISCSI_DRIVER_NAME
190694. BNX2_ISCSI_INITIATOR
190695. BNX2_ISCSI_INITIATOR_EN
190696. BNX2_ISCSI_MAX_CONN
190697. BNX2_ISCSI_MAX_CONN_MASK
190698. BNX2_ISCSI_MAX_CONN_SHIFT
190699. BNX2_L2CTX_BD_PRE_READ
190700. BNX2_L2CTX_CMD_TYPE
190701. BNX2_L2CTX_CMD_TYPE_TYPE
190702. BNX2_L2CTX_CMD_TYPE_TYPE_L2
190703. BNX2_L2CTX_CMD_TYPE_TYPE_TCP
190704. BNX2_L2CTX_CMD_TYPE_XI
190705. BNX2_L2CTX_CTX_SIZE
190706. BNX2_L2CTX_CTX_TYPE
190707. BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE
190708. BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED
190709. BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE
190710. BNX2_L2CTX_CTX_TYPE_SIZE_L2
190711. BNX2_L2CTX_EST_NBD
190712. BNX2_L2CTX_FLOW_CTRL_ENABLE
190713. BNX2_L2CTX_HOST_BDIDX
190714. BNX2_L2CTX_HOST_BSEQ
190715. BNX2_L2CTX_HOST_PG_BDIDX
190716. BNX2_L2CTX_L2_STATUSB_NUM
190717. BNX2_L2CTX_L2_STATUSB_NUM_SHIFT
190718. BNX2_L2CTX_L5_STATUSB_NUM
190719. BNX2_L2CTX_L5_STATUSB_NUM_SHIFT
190720. BNX2_L2CTX_NX_BDHADDR_HI
190721. BNX2_L2CTX_NX_BDHADDR_LO
190722. BNX2_L2CTX_NX_BDIDX
190723. BNX2_L2CTX_NX_BSEQ
190724. BNX2_L2CTX_NX_PG_BDHADDR_HI
190725. BNX2_L2CTX_NX_PG_BDHADDR_LO
190726. BNX2_L2CTX_PG_BUF_SIZE
190727. BNX2_L2CTX_RBDC_JUMBO_KEY
190728. BNX2_L2CTX_RBDC_KEY
190729. BNX2_L2CTX_TBDR_BHADDR_HI
190730. BNX2_L2CTX_TBDR_BHADDR_HI_XI
190731. BNX2_L2CTX_TBDR_BHADDR_LO
190732. BNX2_L2CTX_TBDR_BHADDR_LO_XI
190733. BNX2_L2CTX_TBDR_BIDX
190734. BNX2_L2CTX_TBDR_BOFF
190735. BNX2_L2CTX_TBDR_BSEQ
190736. BNX2_L2CTX_TSCH_BSEQ
190737. BNX2_L2CTX_TXP_BIDX
190738. BNX2_L2CTX_TXP_BOFF
190739. BNX2_L2CTX_TXP_BSEQ
190740. BNX2_L2CTX_TX_HOST_BIDX
190741. BNX2_L2CTX_TX_HOST_BSEQ
190742. BNX2_L2CTX_TYPE
190743. BNX2_L2CTX_TYPE_SIZE_L2
190744. BNX2_L2CTX_TYPE_TYPE
190745. BNX2_L2CTX_TYPE_TYPE_EMPTY
190746. BNX2_L2CTX_TYPE_TYPE_L2
190747. BNX2_L2CTX_TYPE_XI
190748. BNX2_LINK_STATUS
190749. BNX2_LINK_STATUS_1000FULL
190750. BNX2_LINK_STATUS_1000HALF
190751. BNX2_LINK_STATUS_100BASE_T4
190752. BNX2_LINK_STATUS_100FULL
190753. BNX2_LINK_STATUS_100HALF
190754. BNX2_LINK_STATUS_10FULL
190755. BNX2_LINK_STATUS_10HALF
190756. BNX2_LINK_STATUS_2500FULL
190757. BNX2_LINK_STATUS_2500HALF
190758. BNX2_LINK_STATUS_AN_COMPLETE
190759. BNX2_LINK_STATUS_AN_ENABLED
190760. BNX2_LINK_STATUS_AN_INCOMPLETE
190761. BNX2_LINK_STATUS_HEART_BEAT_EXPIRED
190762. BNX2_LINK_STATUS_INIT_VALUE
190763. BNX2_LINK_STATUS_LINK_DOWN
190764. BNX2_LINK_STATUS_LINK_UP
190765. BNX2_LINK_STATUS_PARALLEL_DET
190766. BNX2_LINK_STATUS_PARTNER_AD_1000FULL
190767. BNX2_LINK_STATUS_PARTNER_AD_1000HALF
190768. BNX2_LINK_STATUS_PARTNER_AD_100BT4
190769. BNX2_LINK_STATUS_PARTNER_AD_100FULL
190770. BNX2_LINK_STATUS_PARTNER_AD_100HALF
190771. BNX2_LINK_STATUS_PARTNER_AD_10FULL
190772. BNX2_LINK_STATUS_PARTNER_AD_10HALF
190773. BNX2_LINK_STATUS_PARTNER_AD_2500FULL
190774. BNX2_LINK_STATUS_PARTNER_AD_2500HALF
190775. BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP
190776. BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP
190777. BNX2_LINK_STATUS_RESERVED
190778. BNX2_LINK_STATUS_RX_FC_ENABLED
190779. BNX2_LINK_STATUS_SERDES_LINK
190780. BNX2_LINK_STATUS_SPEED_MASK
190781. BNX2_LINK_STATUS_TX_FC_ENABLED
190782. BNX2_LOOPBACK_FAILED
190783. BNX2_MAC_LOOPBACK
190784. BNX2_MAC_LOOPBACK_FAILED
190785. BNX2_MAX_CID
190786. BNX2_MAX_MSIX_HW_VEC
190787. BNX2_MAX_MSIX_VEC
190788. BNX2_MAX_RX_DESC_CNT
190789. BNX2_MAX_RX_PG_RINGS
190790. BNX2_MAX_RX_RINGS
190791. BNX2_MAX_TOTAL_RX_DESC_CNT
190792. BNX2_MAX_TOTAL_RX_PG_DESC_CNT
190793. BNX2_MAX_TX_DESC_CNT
190794. BNX2_MAX_UNICAST_ADDRESSES
190795. BNX2_MAX_VER_SLEN
190796. BNX2_MCP_ACCESS_LOCK
190797. BNX2_MCP_ACCESS_LOCK_LOCK
190798. BNX2_MCP_CPU_DATA_ACCESS
190799. BNX2_MCP_CPU_DEBUG_VECT_PEEK
190800. BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN
190801. BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL
190802. BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE
190803. BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN
190804. BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL
190805. BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE
190806. BNX2_MCP_CPU_EVENT_MASK
190807. BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK
190808. BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK
190809. BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK
190810. BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK
190811. BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK
190812. BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK
190813. BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK
190814. BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK
190815. BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK
190816. BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK
190817. BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK
190818. BNX2_MCP_CPU_HW_BREAKPOINT
190819. BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS
190820. BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE
190821. BNX2_MCP_CPU_INSTRUCTION
190822. BNX2_MCP_CPU_INTERRUPT_ENABLE
190823. BNX2_MCP_CPU_INTERRUPT_SAVED_PC
190824. BNX2_MCP_CPU_INTERRUPT_VECTOR
190825. BNX2_MCP_CPU_LAST_BRANCH_ADDR
190826. BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA
190827. BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE
190828. BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH
190829. BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP
190830. BNX2_MCP_CPU_MODE
190831. BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA
190832. BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA
190833. BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA
190834. BNX2_MCP_CPU_MODE_INTERRUPT_ENA
190835. BNX2_MCP_CPU_MODE_LOCAL_RST
190836. BNX2_MCP_CPU_MODE_MSG_BIT1
190837. BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA
190838. BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA
190839. BNX2_MCP_CPU_MODE_SOFT_HALT
190840. BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA
190841. BNX2_MCP_CPU_MODE_STEP_ENA
190842. BNX2_MCP_CPU_PROGRAM_COUNTER
190843. BNX2_MCP_CPU_REG_FILE
190844. BNX2_MCP_CPU_STATE
190845. BNX2_MCP_CPU_STATE_ALIGN_HALTED
190846. BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED
190847. BNX2_MCP_CPU_STATE_BAD_INST_HALTED
190848. BNX2_MCP_CPU_STATE_BAD_PC_HALTED
190849. BNX2_MCP_CPU_STATE_BLOCKED_READ
190850. BNX2_MCP_CPU_STATE_BREAKPOINT
190851. BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL
190852. BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED
190853. BNX2_MCP_CPU_STATE_INST_FETCH_STALL
190854. BNX2_MCP_CPU_STATE_INTERRUPT
190855. BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED
190856. BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED
190857. BNX2_MCP_CPU_STATE_SOFT_HALTED
190858. BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW
190859. BNX2_MCP_DRIVER_DOORBELL
190860. BNX2_MCP_DRIVER_DOORBELL_DRIVER_DOORBELL
190861. BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC
190862. BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL
190863. BNX2_MCP_MAILBOX_CFG
190864. BNX2_MCP_MAILBOX_CFG_MAILBOX_OFFSET
190865. BNX2_MCP_MAILBOX_CFG_MAILBOX_SIZE
190866. BNX2_MCP_MAILBOX_CFG_OTHER_FUNC
190867. BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET
190868. BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE
190869. BNX2_MCP_MCPQ
190870. BNX2_MCP_MCPQ_FTQ_CMD
190871. BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA
190872. BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN
190873. BNX2_MCP_MCPQ_FTQ_CMD_BUSY
190874. BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR
190875. BNX2_MCP_MCPQ_FTQ_CMD_OFFSET
190876. BNX2_MCP_MCPQ_FTQ_CMD_POP
190877. BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA
190878. BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET
190879. BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP
190880. BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0
190881. BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1
190882. BNX2_MCP_MCPQ_FTQ_CTL
190883. BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH
190884. BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE
190885. BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE
190886. BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH
190887. BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW
190888. BNX2_MCP_MCP_ATTENTION_STATUS
190889. BNX2_MCP_MCP_ATTENTION_STATUS_CPU_EVENT
190890. BNX2_MCP_MCP_ATTENTION_STATUS_DRV_DOORBELL
190891. BNX2_MCP_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT
190892. BNX2_MCP_MCP_CONTROL
190893. BNX2_MCP_MCP_CONTROL_MCP_ISOLATE
190894. BNX2_MCP_MCP_CONTROL_SMBUS_SEL
190895. BNX2_MCP_MCP_DOORBELL
190896. BNX2_MCP_MCP_DOORBELL_MCP_DOORBELL
190897. BNX2_MCP_MCP_HEARTBEAT
190898. BNX2_MCP_MCP_HEARTBEAT_CONTROL
190899. BNX2_MCP_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE
190900. BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT
190901. BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_INC
190902. BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET
190903. BNX2_MCP_MCP_HEARTBEAT_STATUS
190904. BNX2_MCP_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD
190905. BNX2_MCP_MCP_HEARTBEAT_STATUS_VALID
190906. BNX2_MCP_ROM
190907. BNX2_MCP_SCRATCH
190908. BNX2_MCP_STATE_P0
190909. BNX2_MCP_STATE_P0_5708
190910. BNX2_MCP_STATE_P1
190911. BNX2_MCP_STATE_P1_5708
190912. BNX2_MCP_TOE_ID
190913. BNX2_MCP_TOE_ID_FUNCTION_ID
190914. BNX2_MCP_WATCHDOG_CONTROL
190915. BNX2_MCP_WATCHDOG_CONTROL_MCP_RST_ENABLE
190916. BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ATTN
190917. BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ENABLE
190918. BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT
190919. BNX2_MCP_WATCHDOG_RESET
190920. BNX2_MCP_WATCHDOG_RESET_WATCHDOG_RESET
190921. BNX2_MFW_VER_PTR
190922. BNX2_MIN_MSIX_VEC
190923. BNX2_MISC_ARB_FREE0
190924. BNX2_MISC_ARB_FREE1
190925. BNX2_MISC_ARB_FREE2
190926. BNX2_MISC_ARB_FREE3
190927. BNX2_MISC_ARB_FREE4
190928. BNX2_MISC_ARB_GNT0
190929. BNX2_MISC_ARB_GNT0_0
190930. BNX2_MISC_ARB_GNT0_1
190931. BNX2_MISC_ARB_GNT0_2
190932. BNX2_MISC_ARB_GNT0_3
190933. BNX2_MISC_ARB_GNT0_4
190934. BNX2_MISC_ARB_GNT0_5
190935. BNX2_MISC_ARB_GNT0_6
190936. BNX2_MISC_ARB_GNT0_7
190937. BNX2_MISC_ARB_GNT1
190938. BNX2_MISC_ARB_GNT1_10
190939. BNX2_MISC_ARB_GNT1_11
190940. BNX2_MISC_ARB_GNT1_12
190941. BNX2_MISC_ARB_GNT1_13
190942. BNX2_MISC_ARB_GNT1_14
190943. BNX2_MISC_ARB_GNT1_15
190944. BNX2_MISC_ARB_GNT1_8
190945. BNX2_MISC_ARB_GNT1_9
190946. BNX2_MISC_ARB_GNT2
190947. BNX2_MISC_ARB_GNT2_16
190948. BNX2_MISC_ARB_GNT2_17
190949. BNX2_MISC_ARB_GNT2_18
190950. BNX2_MISC_ARB_GNT2_19
190951. BNX2_MISC_ARB_GNT2_20
190952. BNX2_MISC_ARB_GNT2_21
190953. BNX2_MISC_ARB_GNT2_22
190954. BNX2_MISC_ARB_GNT2_23
190955. BNX2_MISC_ARB_GNT3
190956. BNX2_MISC_ARB_GNT3_24
190957. BNX2_MISC_ARB_GNT3_25
190958. BNX2_MISC_ARB_GNT3_26
190959. BNX2_MISC_ARB_GNT3_27
190960. BNX2_MISC_ARB_GNT3_28
190961. BNX2_MISC_ARB_GNT3_29
190962. BNX2_MISC_ARB_GNT3_30
190963. BNX2_MISC_ARB_GNT3_31
190964. BNX2_MISC_ARB_REQ0
190965. BNX2_MISC_ARB_REQ1
190966. BNX2_MISC_ARB_REQ2
190967. BNX2_MISC_ARB_REQ3
190968. BNX2_MISC_ARB_REQ4
190969. BNX2_MISC_ARB_REQ_STATUS0
190970. BNX2_MISC_ARB_REQ_STATUS1
190971. BNX2_MISC_ARB_REQ_STATUS2
190972. BNX2_MISC_ARB_REQ_STATUS3
190973. BNX2_MISC_ARB_REQ_STATUS4
190974. BNX2_MISC_BIST_CS0
190975. BNX2_MISC_BIST_CS0_BIST_OVERRIDE
190976. BNX2_MISC_BIST_CS0_BIST_SETUP
190977. BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET
190978. BNX2_MISC_BIST_CS0_MBIST_DONE
190979. BNX2_MISC_BIST_CS0_MBIST_EN
190980. BNX2_MISC_BIST_CS0_MBIST_GO
190981. BNX2_MISC_BIST_CS1
190982. BNX2_MISC_BIST_CS1_BIST_SETUP
190983. BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET
190984. BNX2_MISC_BIST_CS1_MBIST_DONE
190985. BNX2_MISC_BIST_CS1_MBIST_EN
190986. BNX2_MISC_BIST_CS1_MBIST_GO
190987. BNX2_MISC_BIST_CS2
190988. BNX2_MISC_BIST_CS2_BIST_SETUP
190989. BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET
190990. BNX2_MISC_BIST_CS2_MBIST_DONE
190991. BNX2_MISC_BIST_CS2_MBIST_EN
190992. BNX2_MISC_BIST_CS2_MBIST_GO
190993. BNX2_MISC_BIST_CS3
190994. BNX2_MISC_BIST_CS3_BIST_SETUP
190995. BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET
190996. BNX2_MISC_BIST_CS3_MBIST_DONE
190997. BNX2_MISC_BIST_CS3_MBIST_EN
190998. BNX2_MISC_BIST_CS3_MBIST_GO
190999. BNX2_MISC_BIST_CS4
191000. BNX2_MISC_BIST_CS4_BIST_SETUP
191001. BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET
191002. BNX2_MISC_BIST_CS4_MBIST_DONE
191003. BNX2_MISC_BIST_CS4_MBIST_EN
191004. BNX2_MISC_BIST_CS4_MBIST_GO
191005. BNX2_MISC_BIST_CS5
191006. BNX2_MISC_BIST_CS5_BIST_SETUP
191007. BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET
191008. BNX2_MISC_BIST_CS5_MBIST_DONE
191009. BNX2_MISC_BIST_CS5_MBIST_EN
191010. BNX2_MISC_BIST_CS5_MBIST_GO
191011. BNX2_MISC_BIST_MEMSTATUS0
191012. BNX2_MISC_BIST_MEMSTATUS1
191013. BNX2_MISC_BIST_MEMSTATUS2
191014. BNX2_MISC_BIST_MEMSTATUS3
191015. BNX2_MISC_BIST_MEMSTATUS4
191016. BNX2_MISC_BIST_MEMSTATUS5
191017. BNX2_MISC_CFG
191018. BNX2_MISC_CFG_BIST_EN
191019. BNX2_MISC_CFG_CK25_OUT_ALT_SRC
191020. BNX2_MISC_CFG_CLK_CTL_OVERRIDE
191021. BNX2_MISC_CFG_DBU_GRC_TMOUT_TE
191022. BNX2_MISC_CFG_GRC_TMOUT
191023. BNX2_MISC_CFG_LEDMODE
191024. BNX2_MISC_CFG_LEDMODE_MAC
191025. BNX2_MISC_CFG_LEDMODE_MAC2_XI
191026. BNX2_MISC_CFG_LEDMODE_MAC3_XI
191027. BNX2_MISC_CFG_LEDMODE_MAC4_XI
191028. BNX2_MISC_CFG_LEDMODE_MAC_XI
191029. BNX2_MISC_CFG_LEDMODE_PHY10_XI
191030. BNX2_MISC_CFG_LEDMODE_PHY11_XI
191031. BNX2_MISC_CFG_LEDMODE_PHY1_TE
191032. BNX2_MISC_CFG_LEDMODE_PHY1_XI
191033. BNX2_MISC_CFG_LEDMODE_PHY2_TE
191034. BNX2_MISC_CFG_LEDMODE_PHY2_XI
191035. BNX2_MISC_CFG_LEDMODE_PHY3_TE
191036. BNX2_MISC_CFG_LEDMODE_PHY3_XI
191037. BNX2_MISC_CFG_LEDMODE_PHY4_TE
191038. BNX2_MISC_CFG_LEDMODE_PHY4_XI
191039. BNX2_MISC_CFG_LEDMODE_PHY5_TE
191040. BNX2_MISC_CFG_LEDMODE_PHY5_XI
191041. BNX2_MISC_CFG_LEDMODE_PHY6_TE
191042. BNX2_MISC_CFG_LEDMODE_PHY6_XI
191043. BNX2_MISC_CFG_LEDMODE_PHY7_TE
191044. BNX2_MISC_CFG_LEDMODE_PHY7_XI
191045. BNX2_MISC_CFG_LEDMODE_PHY8_XI
191046. BNX2_MISC_CFG_LEDMODE_PHY9_XI
191047. BNX2_MISC_CFG_LEDMODE_UNUSED_XI
191048. BNX2_MISC_CFG_LEDMODE_XI
191049. BNX2_MISC_CFG_MCP_GRC_TMOUT_TE
191050. BNX2_MISC_CFG_NVM_WR_EN
191051. BNX2_MISC_CFG_NVM_WR_EN_ALLOW
191052. BNX2_MISC_CFG_NVM_WR_EN_ALLOW2
191053. BNX2_MISC_CFG_NVM_WR_EN_PCI
191054. BNX2_MISC_CFG_NVM_WR_EN_PROTECT
191055. BNX2_MISC_CFG_PARITY_MODE_XI
191056. BNX2_MISC_CFG_PORT_SELECT_XI
191057. BNX2_MISC_CFG_RESERVED5_TE
191058. BNX2_MISC_CFG_RESERVED6_TE
191059. BNX2_MISC_CLOCK_CONTROL_BITS
191060. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT
191061. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI
191062. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC
191063. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12
191064. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6
191065. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62
191066. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF
191067. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE
191068. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED
191069. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100
191070. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25
191071. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40
191072. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50
191073. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80
191074. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI
191075. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP
191076. BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI
191077. BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER
191078. BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET
191079. BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ
191080. BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ
191081. BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ
191082. BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ
191083. BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ
191084. BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ
191085. BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ
191086. BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ
191087. BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW
191088. BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI
191089. BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI
191090. BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI
191091. BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI
191092. BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE
191093. BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE
191094. BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE
191095. BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE
191096. BNX2_MISC_COMMAND
191097. BNX2_MISC_COMMAND_CMN_SW_RESET
191098. BNX2_MISC_COMMAND_CS16_ERR
191099. BNX2_MISC_COMMAND_CS16_ERR_LOC
191100. BNX2_MISC_COMMAND_DINTEG_ATTN_EN
191101. BNX2_MISC_COMMAND_DISABLE_ALL
191102. BNX2_MISC_COMMAND_ENABLE_ALL
191103. BNX2_MISC_COMMAND_HD_RESET
191104. BNX2_MISC_COMMAND_PAR_ERROR
191105. BNX2_MISC_COMMAND_PAR_ERR_RAM
191106. BNX2_MISC_COMMAND_PCIE_DIS
191107. BNX2_MISC_COMMAND_PCIE_LINK_IN_L23
191108. BNX2_MISC_COMMAND_POR_RESET
191109. BNX2_MISC_COMMAND_POWERDOWN_EVENT
191110. BNX2_MISC_COMMAND_SHUTDOWN_EN
191111. BNX2_MISC_COMMAND_SW_RESET
191112. BNX2_MISC_COMMAND_SW_SHUTDOWN
191113. BNX2_MISC_CONFIG_LFSR
191114. BNX2_MISC_CONFIG_LFSR_DIV
191115. BNX2_MISC_CS16_ERR
191116. BNX2_MISC_CS16_ERR_ENA_COM
191117. BNX2_MISC_CS16_ERR_ENA_CP
191118. BNX2_MISC_CS16_ERR_ENA_CTX
191119. BNX2_MISC_CS16_ERR_ENA_EMAC
191120. BNX2_MISC_CS16_ERR_ENA_PCI
191121. BNX2_MISC_CS16_ERR_ENA_RBDC
191122. BNX2_MISC_CS16_ERR_ENA_RDMA
191123. BNX2_MISC_CS16_ERR_ENA_TBDR
191124. BNX2_MISC_CS16_ERR_ENA_TDMA
191125. BNX2_MISC_CS16_ERR_STA_COM
191126. BNX2_MISC_CS16_ERR_STA_CP
191127. BNX2_MISC_CS16_ERR_STA_CTX
191128. BNX2_MISC_CS16_ERR_STA_EMAC
191129. BNX2_MISC_CS16_ERR_STA_PCI
191130. BNX2_MISC_CS16_ERR_STA_RBDC
191131. BNX2_MISC_CS16_ERR_STA_RDMA
191132. BNX2_MISC_CS16_ERR_STA_TBDR
191133. BNX2_MISC_CS16_ERR_STA_TDMA
191134. BNX2_MISC_DEBUG_VECTOR_SEL
191135. BNX2_MISC_DEBUG_VECTOR_SEL_0
191136. BNX2_MISC_DEBUG_VECTOR_SEL_1
191137. BNX2_MISC_DEBUG_VECTOR_SEL_1_XI
191138. BNX2_MISC_DUAL_MEDIA_CTRL
191139. BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID
191140. BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C
191141. BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S
191142. BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X
191143. BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST
191144. BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST
191145. BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET
191146. BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST
191147. BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET
191148. BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL
191149. BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP
191150. BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ
191151. BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ
191152. BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ
191153. BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ
191154. BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ
191155. BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP
191156. BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN
191157. BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST
191158. BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET
191159. BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST
191160. BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET
191161. BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE
191162. BNX2_MISC_ECO_CORE_CTL
191163. BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD
191164. BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT
191165. BNX2_MISC_ECO_HW_CTL
191166. BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN
191167. BNX2_MISC_ECO_HW_CTL_RESERVED_HARD
191168. BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT
191169. BNX2_MISC_ENABLE_CLR_BITS
191170. BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE
191171. BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE
191172. BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE
191173. BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE
191174. BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE
191175. BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE
191176. BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE
191177. BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE
191178. BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE
191179. BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE
191180. BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE
191181. BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE
191182. BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE
191183. BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE
191184. BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE
191185. BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE
191186. BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE
191187. BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE
191188. BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE
191189. BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE
191190. BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE
191191. BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE
191192. BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE
191193. BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE
191194. BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE
191195. BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE
191196. BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE
191197. BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE
191198. BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE
191199. BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE
191200. BNX2_MISC_ENABLE_DEFAULT
191201. BNX2_MISC_ENABLE_SET_BITS
191202. BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE
191203. BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE
191204. BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE
191205. BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE
191206. BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE
191207. BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE
191208. BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE
191209. BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE
191210. BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE
191211. BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE
191212. BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE
191213. BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE
191214. BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE
191215. BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE
191216. BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE
191217. BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE
191218. BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE
191219. BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE
191220. BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE
191221. BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE
191222. BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE
191223. BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE
191224. BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE
191225. BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE
191226. BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE
191227. BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE
191228. BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE
191229. BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE
191230. BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE
191231. BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE
191232. BNX2_MISC_ENABLE_STATUS_BITS
191233. BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE
191234. BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE
191235. BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE
191236. BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE
191237. BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE
191238. BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE
191239. BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE
191240. BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE
191241. BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE
191242. BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE
191243. BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE
191244. BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE
191245. BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE
191246. BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE
191247. BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE
191248. BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE
191249. BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE
191250. BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE
191251. BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE
191252. BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE
191253. BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE
191254. BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE
191255. BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE
191256. BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE
191257. BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE
191258. BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE
191259. BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE
191260. BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE
191261. BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE
191262. BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE
191263. BNX2_MISC_FINAL_CLK_CTL_VAL
191264. BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL
191265. BNX2_MISC_GP_HW_CTL0
191266. BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF
191267. BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY
191268. BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE
191269. BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF
191270. BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE
191271. BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF
191272. BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE
191273. BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE
191274. BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE
191275. BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE
191276. BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT
191277. BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P
191278. BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P
191279. BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P
191280. BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P
191281. BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI
191282. BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA
191283. BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA
191284. BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA
191285. BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA
191286. BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA
191287. BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN
191288. BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ
191289. BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA
191290. BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA
191291. BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA
191292. BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA
191293. BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ
191294. BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA
191295. BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA
191296. BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA
191297. BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA
191298. BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS
191299. BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS
191300. BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT
191301. BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P
191302. BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P
191303. BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P
191304. BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P
191305. BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ
191306. BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45
191307. BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57
191308. BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62
191309. BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66
191310. BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF
191311. BNX2_MISC_GP_HW_CTL0_RESERVED1_XI
191312. BNX2_MISC_GP_HW_CTL0_RESERVED2_XI
191313. BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL
191314. BNX2_MISC_GP_HW_CTL0_RMII_MODE
191315. BNX2_MISC_GP_HW_CTL0_RVMII_MODE
191316. BNX2_MISC_GP_HW_CTL0_TX_DRIVE
191317. BNX2_MISC_GP_HW_CTL0_UP1_DEF0
191318. BNX2_MISC_GP_HW_CTL1
191319. BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE
191320. BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE
191321. BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE
191322. BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE
191323. BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI
191324. BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI
191325. BNX2_MISC_ID
191326. BNX2_MISC_ID_BOND_ID
191327. BNX2_MISC_ID_BOND_ID_C
191328. BNX2_MISC_ID_BOND_ID_S
191329. BNX2_MISC_ID_BOND_ID_X
191330. BNX2_MISC_ID_CHIP_METAL
191331. BNX2_MISC_ID_CHIP_NUM
191332. BNX2_MISC_ID_CHIP_REV
191333. BNX2_MISC_LCPLL_CTRL0
191334. BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL
191335. BNX2_MISC_LCPLL_CTRL0_CAPRESTART
191336. BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN
191337. BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN
191338. BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN
191339. BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN
191340. BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN
191341. BNX2_MISC_LCPLL_CTRL0_ICP_CTRL
191342. BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360
191343. BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480
191344. BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600
191345. BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720
191346. BNX2_MISC_LCPLL_CTRL0_OAC
191347. BNX2_MISC_LCPLL_CTRL0_OAC_FORTY
191348. BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY
191349. BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY
191350. BNX2_MISC_LCPLL_CTRL0_OAC_ZERO
191351. BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE
191352. BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN
191353. BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS
191354. BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN
191355. BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE
191356. BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN
191357. BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS
191358. BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART
191359. BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE
191360. BNX2_MISC_LCPLL_CTRL0_RESERVED
191361. BNX2_MISC_LCPLL_CTRL0_VTH_CTRL
191362. BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0
191363. BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1
191364. BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2
191365. BNX2_MISC_LCPLL_CTRL1
191366. BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN
191367. BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN
191368. BNX2_MISC_LCPLL_CTRL1_CAPSELECTM
191369. BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR
191370. BNX2_MISC_LCPLL_STATUS
191371. BNX2_MISC_LCPLL_STATUS_CAPSELECT
191372. BNX2_MISC_LCPLL_STATUS_CAPSTATE
191373. BNX2_MISC_LCPLL_STATUS_FREQDONE_SM
191374. BNX2_MISC_LCPLL_STATUS_FREQPASS_SM
191375. BNX2_MISC_LCPLL_STATUS_PLLSEQDONE
191376. BNX2_MISC_LCPLL_STATUS_PLLSEQPASS
191377. BNX2_MISC_LCPLL_STATUS_PLLSTATE
191378. BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR
191379. BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0
191380. BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1
191381. BNX2_MISC_LFSR_MASK_BITS
191382. BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE
191383. BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE
191384. BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE
191385. BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE
191386. BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE
191387. BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE
191388. BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE
191389. BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE
191390. BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE
191391. BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE
191392. BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE
191393. BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE
191394. BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE
191395. BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE
191396. BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE
191397. BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE
191398. BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE
191399. BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE
191400. BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE
191401. BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE
191402. BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE
191403. BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE
191404. BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE
191405. BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE
191406. BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE
191407. BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE
191408. BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE
191409. BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE
191410. BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE
191411. BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE
191412. BNX2_MISC_MEM_TM0
191413. BNX2_MISC_MEM_TM0_HB_MEM_TM
191414. BNX2_MISC_MEM_TM0_MCP_SCPAD
191415. BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM
191416. BNX2_MISC_MEM_TM0_UMP_TM
191417. BNX2_MISC_NEW_CORE_CTL
191418. BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE
191419. BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ
191420. BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS
191421. BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN
191422. BNX2_MISC_NEW_CORE_CTL_RESERVED_TC
191423. BNX2_MISC_NEW_HW_CTL
191424. BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS
191425. BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED
191426. BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT
191427. BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE
191428. BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0
191429. BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1
191430. BNX2_MISC_OSCFUNDS_CTRL
191431. BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON
191432. BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF
191433. BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON
191434. BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ
191435. BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0
191436. BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1
191437. BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2
191438. BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3
191439. BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ
191440. BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0
191441. BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1
191442. BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2
191443. BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3
191444. BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM
191445. BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0
191446. BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1
191447. BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2
191448. BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3
191449. BNX2_MISC_OTP_CMD1
191450. BNX2_MISC_OTP_CMD1_DEBUG
191451. BNX2_MISC_OTP_CMD1_FMODE
191452. BNX2_MISC_OTP_CMD1_FMODE_IDLE
191453. BNX2_MISC_OTP_CMD1_FMODE_INIT
191454. BNX2_MISC_OTP_CMD1_FMODE_RESERVED0
191455. BNX2_MISC_OTP_CMD1_FMODE_RESERVED1
191456. BNX2_MISC_OTP_CMD1_FMODE_RST
191457. BNX2_MISC_OTP_CMD1_FMODE_SET
191458. BNX2_MISC_OTP_CMD1_FMODE_VERIFY
191459. BNX2_MISC_OTP_CMD1_FMODE_WRITE
191460. BNX2_MISC_OTP_CMD1_PBYP
191461. BNX2_MISC_OTP_CMD1_PCOUNT
191462. BNX2_MISC_OTP_CMD1_PROGSEL
191463. BNX2_MISC_OTP_CMD1_PROGSTART
191464. BNX2_MISC_OTP_CMD1_SADBYP
191465. BNX2_MISC_OTP_CMD1_TM
191466. BNX2_MISC_OTP_CMD1_USEPINS
191467. BNX2_MISC_OTP_CMD1_VSEL
191468. BNX2_MISC_OTP_CMD2
191469. BNX2_MISC_OTP_CMD2_DOSEL
191470. BNX2_MISC_OTP_CMD2_DOSEL_0
191471. BNX2_MISC_OTP_CMD2_DOSEL_1
191472. BNX2_MISC_OTP_CMD2_DOSEL_127
191473. BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR
191474. BNX2_MISC_OTP_SHIFT1_CMD
191475. BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA
191476. BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N
191477. BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE
191478. BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT
191479. BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START
191480. BNX2_MISC_OTP_SHIFT1_DATA
191481. BNX2_MISC_OTP_SHIFT2_CMD
191482. BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA
191483. BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N
191484. BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE
191485. BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT
191486. BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START
191487. BNX2_MISC_OTP_SHIFT2_DATA
191488. BNX2_MISC_OTP_STATUS
191489. BNX2_MISC_OTP_STATUS_BUSY
191490. BNX2_MISC_OTP_STATUS_BUSYSM
191491. BNX2_MISC_OTP_STATUS_DATA
191492. BNX2_MISC_OTP_STATUS_DONE
191493. BNX2_MISC_OTP_STATUS_VALID
191494. BNX2_MISC_PERR_ENA0
191495. BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI
191496. BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI
191497. BNX2_MISC_PERR_ENA0_COM_MISC_CTXC
191498. BNX2_MISC_PERR_ENA0_COM_MISC_REGF
191499. BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD
191500. BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI
191501. BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI
191502. BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI
191503. BNX2_MISC_PERR_ENA0_CP_MISC_CTXC
191504. BNX2_MISC_PERR_ENA0_CP_MISC_REGF
191505. BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD
191506. BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI
191507. BNX2_MISC_PERR_ENA0_CS_MISC_TMEM
191508. BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI
191509. BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI
191510. BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI
191511. BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0
191512. BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1
191513. BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2
191514. BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3
191515. BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4
191516. BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5
191517. BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL
191518. BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI
191519. BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI
191520. BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0
191521. BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1
191522. BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2
191523. BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3
191524. BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4
191525. BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0
191526. BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1
191527. BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2
191528. BNX2_MISC_PERR_ENA0_HC_MISC_DMA
191529. BNX2_MISC_PERR_ENA0_MCP_MISC_REGF
191530. BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD
191531. BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI
191532. BNX2_MISC_PERR_ENA0_MQ_MISC_CTX
191533. BNX2_MISC_PERR_ENA0_RBDC_MISC
191534. BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI
191535. BNX2_MISC_PERR_ENA0_RBUF_MISC_MB
191536. BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR
191537. BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI
191538. BNX2_MISC_PERR_ENA0_RDE_MISC_RPC
191539. BNX2_MISC_PERR_ENA0_RDE_MISC_RPM
191540. BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI
191541. BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI
191542. BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI
191543. BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI
191544. BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI
191545. BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS
191546. BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI
191547. BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI
191548. BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI
191549. BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI
191550. BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI
191551. BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI
191552. BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI
191553. BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI
191554. BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI
191555. BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI
191556. BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI
191557. BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI
191558. BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI
191559. BNX2_MISC_PERR_ENA1
191560. BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI
191561. BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI
191562. BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI
191563. BNX2_MISC_PERR_ENA1_CPQ_MISC
191564. BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI
191565. BNX2_MISC_PERR_ENA1_CSQ_MISC
191566. BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI
191567. BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI
191568. BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI
191569. BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI
191570. BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI
191571. BNX2_MISC_PERR_ENA1_MCPQ_MISC
191572. BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI
191573. BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI
191574. BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI
191575. BNX2_MISC_PERR_ENA1_RDMAQ_MISC
191576. BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI
191577. BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI
191578. BNX2_MISC_PERR_ENA1_RLUPQ_MISC
191579. BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI
191580. BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI
191581. BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI
191582. BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI
191583. BNX2_MISC_PERR_ENA1_RV2PMQ_MISC
191584. BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI
191585. BNX2_MISC_PERR_ENA1_RV2PPQ_MISC
191586. BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI
191587. BNX2_MISC_PERR_ENA1_RV2PTQ_MISC
191588. BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI
191589. BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS
191590. BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM
191591. BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM
191592. BNX2_MISC_PERR_ENA1_RXPCQ_MISC
191593. BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI
191594. BNX2_MISC_PERR_ENA1_RXPQ_MISC
191595. BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI
191596. BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC
191597. BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC
191598. BNX2_MISC_PERR_ENA1_RXP_MISC_REGF
191599. BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD
191600. BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI
191601. BNX2_MISC_PERR_ENA1_TBDC_MISC
191602. BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI
191603. BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI
191604. BNX2_MISC_PERR_ENA1_TDMA_MISC
191605. BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0
191606. BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1
191607. BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI
191608. BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF
191609. BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD
191610. BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB
191611. BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI
191612. BNX2_MISC_PERR_ENA1_TSCH_MISC_LR
191613. BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI
191614. BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC
191615. BNX2_MISC_PERR_ENA1_TXP_MISC_REGF
191616. BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD
191617. BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX
191618. BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX
191619. BNX2_MISC_PERR_ENA1_UMP_MISC_RX
191620. BNX2_MISC_PERR_ENA1_UMP_MISC_TX
191621. BNX2_MISC_PERR_ENA2
191622. BNX2_MISC_PERR_ENA2_COMQ_MISC
191623. BNX2_MISC_PERR_ENA2_COMTQ_MISC
191624. BNX2_MISC_PERR_ENA2_COMXQ_MISC
191625. BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI
191626. BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI
191627. BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI
191628. BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI
191629. BNX2_MISC_PERR_ENA2_TASQ_MISC
191630. BNX2_MISC_PERR_ENA2_TBDRQ_MISC
191631. BNX2_MISC_PERR_ENA2_TDMAQ_MISC
191632. BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI
191633. BNX2_MISC_PERR_ENA2_TPATQ_MISC
191634. BNX2_MISC_PERR_ENA2_TSCHQ_MISC
191635. BNX2_MISC_PERR_ENA2_TXPQ_MISC
191636. BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI
191637. BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI
191638. BNX2_MISC_PERR_STATUS0
191639. BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR
191640. BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR
191641. BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR
191642. BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR
191643. BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR
191644. BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR
191645. BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR
191646. BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR
191647. BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR
191648. BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR
191649. BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR
191650. BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR
191651. BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR
191652. BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR
191653. BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR
191654. BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR
191655. BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR
191656. BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR
191657. BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR
191658. BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR
191659. BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR
191660. BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR
191661. BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR
191662. BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR
191663. BNX2_MISC_PERR_STATUS0_TBDC_PERR
191664. BNX2_MISC_PERR_STATUS0_TDMA_PERR
191665. BNX2_MISC_PERR_STATUS0_THBUF_PERR
191666. BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR
191667. BNX2_MISC_PERR_STATUS0_TPBUF_PERR
191668. BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR
191669. BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR
191670. BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR
191671. BNX2_MISC_PERR_STATUS1
191672. BNX2_MISC_PERR_STATUS1_COMQ_PERR
191673. BNX2_MISC_PERR_STATUS1_COMTQ_PERR
191674. BNX2_MISC_PERR_STATUS1_COMXQ_PERR
191675. BNX2_MISC_PERR_STATUS1_CPQ_PERR
191676. BNX2_MISC_PERR_STATUS1_CSQ_PERR
191677. BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR
191678. BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR
191679. BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR
191680. BNX2_MISC_PERR_STATUS1_HC_STATS_PERR
191681. BNX2_MISC_PERR_STATUS1_MCPQ_PERR
191682. BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR
191683. BNX2_MISC_PERR_STATUS1_RBDC_PERR
191684. BNX2_MISC_PERR_STATUS1_RDMAQ_PERR
191685. BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR
191686. BNX2_MISC_PERR_STATUS1_RLUPQ_PERR
191687. BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR
191688. BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR
191689. BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR
191690. BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR
191691. BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR
191692. BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR
191693. BNX2_MISC_PERR_STATUS1_RXPCQ_PERR
191694. BNX2_MISC_PERR_STATUS1_RXPQ_PERR
191695. BNX2_MISC_PERR_STATUS1_TASQ_PERR
191696. BNX2_MISC_PERR_STATUS1_TBDRQ_PERR
191697. BNX2_MISC_PERR_STATUS1_TDMAQ_PERR
191698. BNX2_MISC_PERR_STATUS1_TPATQ_PERR
191699. BNX2_MISC_PERR_STATUS1_TSCHQ_PERR
191700. BNX2_MISC_PERR_STATUS1_TXPQ_PERR
191701. BNX2_MISC_PERR_STATUS2
191702. BNX2_MISC_PERR_STATUS2_HB_MEM_PERR
191703. BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR
191704. BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR
191705. BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR
191706. BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR
191707. BNX2_MISC_PERR_STATUS2_UMP_RX_PERR
191708. BNX2_MISC_PERR_STATUS2_UMP_TX_PERR
191709. BNX2_MISC_PPIO
191710. BNX2_MISC_PPIO_CLR
191711. BNX2_MISC_PPIO_EVENT
191712. BNX2_MISC_PPIO_EVENT_ENABLE
191713. BNX2_MISC_PPIO_FLOAT
191714. BNX2_MISC_PPIO_INT
191715. BNX2_MISC_PPIO_INT_INT_STATE
191716. BNX2_MISC_PPIO_INT_OLD_CLR
191717. BNX2_MISC_PPIO_INT_OLD_SET
191718. BNX2_MISC_PPIO_INT_OLD_VALUE
191719. BNX2_MISC_PPIO_SET
191720. BNX2_MISC_PPIO_VALUE
191721. BNX2_MISC_RESERVED1
191722. BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE
191723. BNX2_MISC_RESERVED2
191724. BNX2_MISC_RESERVED2_LINK_IN_L23
191725. BNX2_MISC_RESERVED2_PCIE_DIS
191726. BNX2_MISC_RESET_NUMS
191727. BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS
191728. BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS
191729. BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS
191730. BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS
191731. BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS
191732. BNX2_MISC_SMB_HEARTBEAT
191733. BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT
191734. BNX2_MISC_SMB_IN
191735. BNX2_MISC_SMB_IN_DAT_IN
191736. BNX2_MISC_SMB_IN_DONE
191737. BNX2_MISC_SMB_IN_FIRSTBYTE
191738. BNX2_MISC_SMB_IN_RDY
191739. BNX2_MISC_SMB_IN_STATUS
191740. BNX2_MISC_SMB_IN_STATUS_OFLOW
191741. BNX2_MISC_SMB_IN_STATUS_OK
191742. BNX2_MISC_SMB_IN_STATUS_PEC
191743. BNX2_MISC_SMB_IN_STATUS_STOP
191744. BNX2_MISC_SMB_IN_STATUS_TIMEOUT
191745. BNX2_MISC_SMB_OUT
191746. BNX2_MISC_SMB_OUT_ACC_TYPE
191747. BNX2_MISC_SMB_OUT_DAT_OUT
191748. BNX2_MISC_SMB_OUT_ENB_PEC
191749. BNX2_MISC_SMB_OUT_GET_RX_LEN
191750. BNX2_MISC_SMB_OUT_LAST
191751. BNX2_MISC_SMB_OUT_RDY
191752. BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN
191753. BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN
191754. BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN
191755. BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN
191756. BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE
191757. BNX2_MISC_SMB_OUT_SMB_OUT_STATUS
191758. BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK
191759. BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST
191760. BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK
191761. BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK
191762. BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP
191763. BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST
191764. BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK
191765. BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT
191766. BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW
191767. BNX2_MISC_SMB_OUT_SMB_READ_LEN
191768. BNX2_MISC_SMB_OUT_START
191769. BNX2_MISC_SMB_POLL_ASF
191770. BNX2_MISC_SMB_POLL_ASF_POLL_ASF
191771. BNX2_MISC_SMB_POLL_LEGACY
191772. BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY
191773. BNX2_MISC_SMB_RETRAN
191774. BNX2_MISC_SMB_RETRAN_RETRAN
191775. BNX2_MISC_SMB_TIMESTAMP
191776. BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP
191777. BNX2_MISC_SMB_WATCHDOG
191778. BNX2_MISC_SMB_WATCHDOG_WATCHDOG
191779. BNX2_MISC_SM_ASF_CONTROL
191780. BNX2_MISC_SM_ASF_CONTROL_ASF_RST
191781. BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0
191782. BNX2_MISC_SM_ASF_CONTROL_HB_TO
191783. BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1
191784. BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2
191785. BNX2_MISC_SM_ASF_CONTROL_PA_TO
191786. BNX2_MISC_SM_ASF_CONTROL_PL_TO
191787. BNX2_MISC_SM_ASF_CONTROL_RES
191788. BNX2_MISC_SM_ASF_CONTROL_RT_TO
191789. BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD
191790. BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN
191791. BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN
191792. BNX2_MISC_SM_ASF_CONTROL_SMB_EN
191793. BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT
191794. BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT
191795. BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN
191796. BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE
191797. BNX2_MISC_SM_ASF_CONTROL_TSC_EN
191798. BNX2_MISC_SM_ASF_CONTROL_WG_TO
191799. BNX2_MISC_SPIO
191800. BNX2_MISC_SPIO_CLR
191801. BNX2_MISC_SPIO_EVENT
191802. BNX2_MISC_SPIO_EVENT_ENABLE
191803. BNX2_MISC_SPIO_FLOAT
191804. BNX2_MISC_SPIO_INT
191805. BNX2_MISC_SPIO_INT_INT_STATE_TE
191806. BNX2_MISC_SPIO_INT_INT_STATE_XI
191807. BNX2_MISC_SPIO_INT_OLD_CLR_TE
191808. BNX2_MISC_SPIO_INT_OLD_CLR_XI
191809. BNX2_MISC_SPIO_INT_OLD_SET_TE
191810. BNX2_MISC_SPIO_INT_OLD_SET_XI
191811. BNX2_MISC_SPIO_INT_OLD_VALUE_TE
191812. BNX2_MISC_SPIO_INT_OLD_VALUE_XI
191813. BNX2_MISC_SPIO_SET
191814. BNX2_MISC_SPIO_VALUE
191815. BNX2_MISC_USPLL_CTRL
191816. BNX2_MISC_USPLL_CTRL_ANALOG_RST
191817. BNX2_MISC_USPLL_CTRL_ATTEN_FREF
191818. BNX2_MISC_USPLL_CTRL_DIGITAL_RST
191819. BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS
191820. BNX2_MISC_USPLL_CTRL_KVCO_XF
191821. BNX2_MISC_USPLL_CTRL_KVCO_XS
191822. BNX2_MISC_USPLL_CTRL_LCPX
191823. BNX2_MISC_USPLL_CTRL_LOCK
191824. BNX2_MISC_USPLL_CTRL_PH_DET_DIS
191825. BNX2_MISC_USPLL_CTRL_RX
191826. BNX2_MISC_USPLL_CTRL_TESTA_EN
191827. BNX2_MISC_USPLL_CTRL_TESTA_SEL
191828. BNX2_MISC_USPLL_CTRL_TESTD_EN
191829. BNX2_MISC_USPLL_CTRL_TESTD_SEL
191830. BNX2_MISC_USPLL_CTRL_VCO_MG
191831. BNX2_MISC_USPLL_CTRL_VC_EN
191832. BNX2_MISC_VREG_CONTROL
191833. BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI
191834. BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI
191835. BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI
191836. BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI
191837. BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI
191838. BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI
191839. BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI
191840. BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI
191841. BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI
191842. BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI
191843. BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI
191844. BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI
191845. BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI
191846. BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI
191847. BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI
191848. BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI
191849. BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI
191850. BNX2_MISC_VREG_CONTROL_1_0_MGMT
191851. BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10
191852. BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12
191853. BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14
191854. BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16
191855. BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2
191856. BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4
191857. BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6
191858. BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8
191859. BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM
191860. BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10
191861. BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12
191862. BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14
191863. BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2
191864. BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4
191865. BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6
191866. BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8
191867. BNX2_MISC_VREG_CONTROL_1_2
191868. BNX2_MISC_VREG_CONTROL_2_5
191869. BNX2_MISC_VREG_CONTROL_2_5_MINUS10
191870. BNX2_MISC_VREG_CONTROL_2_5_MINUS12
191871. BNX2_MISC_VREG_CONTROL_2_5_MINUS14
191872. BNX2_MISC_VREG_CONTROL_2_5_MINUS16
191873. BNX2_MISC_VREG_CONTROL_2_5_MINUS2
191874. BNX2_MISC_VREG_CONTROL_2_5_MINUS4
191875. BNX2_MISC_VREG_CONTROL_2_5_MINUS6
191876. BNX2_MISC_VREG_CONTROL_2_5_MINUS8
191877. BNX2_MISC_VREG_CONTROL_2_5_NOM
191878. BNX2_MISC_VREG_CONTROL_2_5_PLUS10
191879. BNX2_MISC_VREG_CONTROL_2_5_PLUS12
191880. BNX2_MISC_VREG_CONTROL_2_5_PLUS14
191881. BNX2_MISC_VREG_CONTROL_2_5_PLUS2
191882. BNX2_MISC_VREG_CONTROL_2_5_PLUS4
191883. BNX2_MISC_VREG_CONTROL_2_5_PLUS6
191884. BNX2_MISC_VREG_CONTROL_2_5_PLUS8
191885. BNX2_MQ_BAD_RD_ADDR
191886. BNX2_MQ_BAD_WR_ADDR
191887. BNX2_MQ_COMMAND
191888. BNX2_MQ_COMMAND_ENABLED
191889. BNX2_MQ_COMMAND_IDB_CFG_ERROR
191890. BNX2_MQ_COMMAND_IDB_OVERFLOW
191891. BNX2_MQ_COMMAND_INIT
191892. BNX2_MQ_COMMAND_NO_BIN_ERROR
191893. BNX2_MQ_COMMAND_NO_MAP_ERROR
191894. BNX2_MQ_COMMAND_OVERFLOW
191895. BNX2_MQ_COMMAND_RD_ERROR
191896. BNX2_MQ_COMMAND_WR_ERROR
191897. BNX2_MQ_CONFIG
191898. BNX2_MQ_CONFIG2
191899. BNX2_MQ_CONFIG2_CONT_SZ
191900. BNX2_MQ_CONFIG2_FIRST_L4L5
191901. BNX2_MQ_CONFIG_BIN_MQ_MODE
191902. BNX2_MQ_CONFIG_CUR_DEPTH
191903. BNX2_MQ_CONFIG_DIS_IDB_DROP
191904. BNX2_MQ_CONFIG_HALT_DIS
191905. BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
191906. BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K
191907. BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256
191908. BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K
191909. BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K
191910. BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512
191911. BNX2_MQ_CONFIG_MAX_DEPTH
191912. BNX2_MQ_CONFIG_TX_HIGH_PRI
191913. BNX2_MQ_ENQUEUE1
191914. BNX2_MQ_ENQUEUE1_BYTE_MASK
191915. BNX2_MQ_ENQUEUE1_CID
191916. BNX2_MQ_ENQUEUE1_KNL_MODE
191917. BNX2_MQ_ENQUEUE1_OFFSET
191918. BNX2_MQ_ENQUEUE2
191919. BNX2_MQ_KNL_BYP_CMD_MASK1
191920. BNX2_MQ_KNL_BYP_CMD_MASK2
191921. BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1
191922. BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2
191923. BNX2_MQ_KNL_BYP_RX_V2P_MASK1
191924. BNX2_MQ_KNL_BYP_RX_V2P_MASK2
191925. BNX2_MQ_KNL_BYP_TX_MASK1
191926. BNX2_MQ_KNL_BYP_TX_MASK2
191927. BNX2_MQ_KNL_BYP_WIND_START
191928. BNX2_MQ_KNL_BYP_WIND_START_VALUE
191929. BNX2_MQ_KNL_BYP_WRITE_MASK1
191930. BNX2_MQ_KNL_BYP_WRITE_MASK2
191931. BNX2_MQ_KNL_CMD_MASK1
191932. BNX2_MQ_KNL_CMD_MASK2
191933. BNX2_MQ_KNL_COND_ENQUEUE_MASK1
191934. BNX2_MQ_KNL_COND_ENQUEUE_MASK2
191935. BNX2_MQ_KNL_RX_V2P_MASK1
191936. BNX2_MQ_KNL_RX_V2P_MASK2
191937. BNX2_MQ_KNL_TX_MASK1
191938. BNX2_MQ_KNL_TX_MASK2
191939. BNX2_MQ_KNL_WIND_END
191940. BNX2_MQ_KNL_WIND_END_VALUE
191941. BNX2_MQ_KNL_WRITE_MASK1
191942. BNX2_MQ_KNL_WRITE_MASK2
191943. BNX2_MQ_MAP_L2_3
191944. BNX2_MQ_MAP_L2_3_ARM
191945. BNX2_MQ_MAP_L2_3_BIN_OFFSET
191946. BNX2_MQ_MAP_L2_3_CTX_OFFSET
191947. BNX2_MQ_MAP_L2_3_DEFAULT
191948. BNX2_MQ_MAP_L2_3_ENA
191949. BNX2_MQ_MAP_L2_3_MQ_OFFSET
191950. BNX2_MQ_MAP_L2_3_SZ
191951. BNX2_MQ_MAP_L2_5
191952. BNX2_MQ_MAP_L2_5_ARM
191953. BNX2_MQ_MEM_RD_ADDR
191954. BNX2_MQ_MEM_RD_ADDR_VALUE
191955. BNX2_MQ_MEM_RD_DATA0
191956. BNX2_MQ_MEM_RD_DATA0_VALUE
191957. BNX2_MQ_MEM_RD_DATA1
191958. BNX2_MQ_MEM_RD_DATA1_VALUE
191959. BNX2_MQ_MEM_RD_DATA2
191960. BNX2_MQ_MEM_RD_DATA2_VALUE
191961. BNX2_MQ_MEM_RD_DATA2_VALUE_XI
191962. BNX2_MQ_MEM_WR_ADDR
191963. BNX2_MQ_MEM_WR_ADDR_VALUE
191964. BNX2_MQ_MEM_WR_DATA0
191965. BNX2_MQ_MEM_WR_DATA0_VALUE
191966. BNX2_MQ_MEM_WR_DATA1
191967. BNX2_MQ_MEM_WR_DATA1_VALUE
191968. BNX2_MQ_MEM_WR_DATA2
191969. BNX2_MQ_MEM_WR_DATA2_VALUE
191970. BNX2_MQ_MEM_WR_DATA2_VALUE_XI
191971. BNX2_MQ_STATUS
191972. BNX2_MQ_STATUS_CTX_ACCESS64_STAT
191973. BNX2_MQ_STATUS_CTX_ACCESS_STAT
191974. BNX2_MQ_STATUS_IDB_OFLOW_STAT
191975. BNX2_MQ_STATUS_PCI_STALL_STAT
191976. BNX2_MSIX_PBA_ADDR
191977. BNX2_MSIX_TABLE_ADDR
191978. BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG
191979. BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED
191980. BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE
191981. BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE
191982. BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE
191983. BNX2_NETLINK_SET_LINK_PHY_RESET
191984. BNX2_NETLINK_SET_LINK_SPEED_10
191985. BNX2_NETLINK_SET_LINK_SPEED_100
191986. BNX2_NETLINK_SET_LINK_SPEED_100FULL
191987. BNX2_NETLINK_SET_LINK_SPEED_100HALF
191988. BNX2_NETLINK_SET_LINK_SPEED_10FULL
191989. BNX2_NETLINK_SET_LINK_SPEED_10GFULL
191990. BNX2_NETLINK_SET_LINK_SPEED_10GHALF
191991. BNX2_NETLINK_SET_LINK_SPEED_10HALF
191992. BNX2_NETLINK_SET_LINK_SPEED_1GFULL
191993. BNX2_NETLINK_SET_LINK_SPEED_1GHALF
191994. BNX2_NETLINK_SET_LINK_SPEED_2G5FULL
191995. BNX2_NETLINK_SET_LINK_SPEED_2G5HALF
191996. BNX2_NEXT_RX_BD
191997. BNX2_NEXT_TX_BD
191998. BNX2_NUM_STATS
191999. BNX2_NUM_TESTS
192000. BNX2_NVM_ACCESS_ENABLE
192001. BNX2_NVM_ACCESS_ENABLE_EN
192002. BNX2_NVM_ACCESS_ENABLE_WR_EN
192003. BNX2_NVM_ADDR
192004. BNX2_NVM_ADDR_NVM_ADDR_VALUE
192005. BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG
192006. BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B
192007. BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI
192008. BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK
192009. BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA
192010. BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK
192011. BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI
192012. BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI
192013. BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI
192014. BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO
192015. BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI
192016. BNX2_NVM_CFG1
192017. BNX2_NVM_CFG1_BITBANG_MODE
192018. BNX2_NVM_CFG1_BUFFER_MODE
192019. BNX2_NVM_CFG1_COMPAT_BYPASSS
192020. BNX2_NVM_CFG1_FLASH_MODE
192021. BNX2_NVM_CFG1_FLASH_SIZE
192022. BNX2_NVM_CFG1_FW_FLASH_TYPE_EN
192023. BNX2_NVM_CFG1_FW_USTRAP_0
192024. BNX2_NVM_CFG1_FW_USTRAP_1
192025. BNX2_NVM_CFG1_FW_USTRAP_2
192026. BNX2_NVM_CFG1_FW_USTRAP_3
192027. BNX2_NVM_CFG1_PASS_MODE
192028. BNX2_NVM_CFG1_PROTECT_MODE
192029. BNX2_NVM_CFG1_SEE_CLK_DIV
192030. BNX2_NVM_CFG1_SPI_CLK_DIV
192031. BNX2_NVM_CFG1_STATUS_BIT
192032. BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY
192033. BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY
192034. BNX2_NVM_CFG1_STRAP_CONTROL_0
192035. BNX2_NVM_CFG2
192036. BNX2_NVM_CFG2_DUMMY
192037. BNX2_NVM_CFG2_ERASE_CMD
192038. BNX2_NVM_CFG2_READ_ID
192039. BNX2_NVM_CFG2_STATUS_CMD
192040. BNX2_NVM_CFG3
192041. BNX2_NVM_CFG3_BUFFER_RD_CMD
192042. BNX2_NVM_CFG3_BUFFER_WRITE_CMD
192043. BNX2_NVM_CFG3_READ_CMD
192044. BNX2_NVM_CFG3_WRITE_CMD
192045. BNX2_NVM_CFG4
192046. BNX2_NVM_CFG4_FLASH_SIZE
192047. BNX2_NVM_CFG4_FLASH_SIZE_128MBIT
192048. BNX2_NVM_CFG4_FLASH_SIZE_16MBIT
192049. BNX2_NVM_CFG4_FLASH_SIZE_1MBIT
192050. BNX2_NVM_CFG4_FLASH_SIZE_2MBIT
192051. BNX2_NVM_CFG4_FLASH_SIZE_32MBIT
192052. BNX2_NVM_CFG4_FLASH_SIZE_4MBIT
192053. BNX2_NVM_CFG4_FLASH_SIZE_64MBIT
192054. BNX2_NVM_CFG4_FLASH_SIZE_8MBIT
192055. BNX2_NVM_CFG4_FLASH_VENDOR
192056. BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL
192057. BNX2_NVM_CFG4_FLASH_VENDOR_ST
192058. BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC
192059. BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10
192060. BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11
192061. BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8
192062. BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9
192063. BNX2_NVM_CFG4_RESERVED
192064. BNX2_NVM_CFG4_STATUS_BIT_POLARITY
192065. BNX2_NVM_COMMAND
192066. BNX2_NVM_COMMAND_DOIT
192067. BNX2_NVM_COMMAND_DONE
192068. BNX2_NVM_COMMAND_ERASE
192069. BNX2_NVM_COMMAND_EWSR
192070. BNX2_NVM_COMMAND_FIRST
192071. BNX2_NVM_COMMAND_LAST
192072. BNX2_NVM_COMMAND_MODE_256
192073. BNX2_NVM_COMMAND_RD_ID
192074. BNX2_NVM_COMMAND_RD_STATUS
192075. BNX2_NVM_COMMAND_RST
192076. BNX2_NVM_COMMAND_WR
192077. BNX2_NVM_COMMAND_WRDI
192078. BNX2_NVM_COMMAND_WREN
192079. BNX2_NVM_COMMAND_WRSR
192080. BNX2_NVM_READ
192081. BNX2_NVM_READ_NVM_READ_VALUE
192082. BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG
192083. BNX2_NVM_READ_NVM_READ_VALUE_CS_B
192084. BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI
192085. BNX2_NVM_READ_NVM_READ_VALUE_EECLK
192086. BNX2_NVM_READ_NVM_READ_VALUE_EEDATA
192087. BNX2_NVM_READ_NVM_READ_VALUE_SCLK
192088. BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI
192089. BNX2_NVM_READ_NVM_READ_VALUE_SI
192090. BNX2_NVM_READ_NVM_READ_VALUE_SI_XI
192091. BNX2_NVM_READ_NVM_READ_VALUE_SO
192092. BNX2_NVM_READ_NVM_READ_VALUE_SO_XI
192093. BNX2_NVM_RECONFIG
192094. BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE
192095. BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL
192096. BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST
192097. BNX2_NVM_RECONFIG_RECONFIG_DONE
192098. BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE
192099. BNX2_NVM_RECONFIG_RESERVED
192100. BNX2_NVM_STATUS
192101. BNX2_NVM_STATUS_EE_FSM_STATE
192102. BNX2_NVM_STATUS_EQ_FSM_STATE
192103. BNX2_NVM_STATUS_PI_FSM_STATE
192104. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI
192105. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI
192106. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI
192107. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI
192108. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI
192109. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI
192110. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI
192111. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI
192112. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI
192113. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI
192114. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI
192115. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI
192116. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI
192117. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI
192118. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI
192119. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI
192120. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI
192121. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI
192122. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI
192123. BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI
192124. BNX2_NVM_STATUS_SPI_FSM_STATE_XI
192125. BNX2_NVM_SW_ARB
192126. BNX2_NVM_SW_ARB_ARB_ARB0
192127. BNX2_NVM_SW_ARB_ARB_ARB1
192128. BNX2_NVM_SW_ARB_ARB_ARB2
192129. BNX2_NVM_SW_ARB_ARB_ARB3
192130. BNX2_NVM_SW_ARB_ARB_REQ_CLR0
192131. BNX2_NVM_SW_ARB_ARB_REQ_CLR1
192132. BNX2_NVM_SW_ARB_ARB_REQ_CLR2
192133. BNX2_NVM_SW_ARB_ARB_REQ_CLR3
192134. BNX2_NVM_SW_ARB_ARB_REQ_SET0
192135. BNX2_NVM_SW_ARB_ARB_REQ_SET1
192136. BNX2_NVM_SW_ARB_ARB_REQ_SET2
192137. BNX2_NVM_SW_ARB_ARB_REQ_SET3
192138. BNX2_NVM_SW_ARB_REQ0
192139. BNX2_NVM_SW_ARB_REQ1
192140. BNX2_NVM_SW_ARB_REQ2
192141. BNX2_NVM_SW_ARB_REQ3
192142. BNX2_NVM_WRITE
192143. BNX2_NVM_WRITE1
192144. BNX2_NVM_WRITE1_SR_DATA
192145. BNX2_NVM_WRITE1_WRDI_CMD
192146. BNX2_NVM_WRITE1_WREN_CMD
192147. BNX2_NVM_WRITE_NVM_WRITE_VALUE
192148. BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG
192149. BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B
192150. BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI
192151. BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK
192152. BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA
192153. BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK
192154. BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI
192155. BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI
192156. BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI
192157. BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO
192158. BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI
192159. BNX2_NV_BUFFERED
192160. BNX2_NV_TRANSLATE
192161. BNX2_NV_WREN
192162. BNX2_PAGE_BITS
192163. BNX2_PAGE_SIZE
192164. BNX2_PCICFG_DEVICE_CONTROL
192165. BNX2_PCICFG_DEVICE_STATUS_NO_PEND
192166. BNX2_PCICFG_INT_ACK_CMD
192167. BNX2_PCICFG_INT_ACK_CMD_INDEX
192168. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID
192169. BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM
192170. BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT
192171. BNX2_PCICFG_INT_ACK_CMD_MASK_INT
192172. BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM
192173. BNX2_PCICFG_MAILBOX_QUEUE_ADDR
192174. BNX2_PCICFG_MAILBOX_QUEUE_DATA
192175. BNX2_PCICFG_MISC_CONFIG
192176. BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV
192177. BNX2_PCICFG_MISC_CONFIG_ASIC_ID
192178. BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV
192179. BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA
192180. BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY
192181. BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ
192182. BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN
192183. BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN
192184. BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN
192185. BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA
192186. BNX2_PCICFG_MISC_CONFIG_RESERVED1
192187. BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP
192188. BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP
192189. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP
192190. BNX2_PCICFG_MISC_STATUS
192191. BNX2_PCICFG_MISC_STATUS_32BIT_DET
192192. BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE
192193. BNX2_PCICFG_MISC_STATUS_INTA_VALUE
192194. BNX2_PCICFG_MISC_STATUS_M66EN
192195. BNX2_PCICFG_MISC_STATUS_PCIX_DET
192196. BNX2_PCICFG_MISC_STATUS_PCIX_SPEED
192197. BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100
192198. BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133
192199. BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66
192200. BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE
192201. BNX2_PCICFG_MSI_CONTROL
192202. BNX2_PCICFG_MSI_CONTROL_ENABLE
192203. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS
192204. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT
192205. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC
192206. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12
192207. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6
192208. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62
192209. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF
192210. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE
192211. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED
192212. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100
192213. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25
192214. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40
192215. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50
192216. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80
192217. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP
192218. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER
192219. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET
192220. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ
192221. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ
192222. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ
192223. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ
192224. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ
192225. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ
192226. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ
192227. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ
192228. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW
192229. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED
192230. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17
192231. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18
192232. BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19
192233. BNX2_PCICFG_REG_WINDOW
192234. BNX2_PCICFG_REG_WINDOW_ADDRESS
192235. BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL
192236. BNX2_PCICFG_STATUS_BIT_CLEAR_CMD
192237. BNX2_PCICFG_STATUS_BIT_SET_CMD
192238. BNX2_PCI_CFG_ACCESS_CMD
192239. BNX2_PCI_CFG_ACCESS_CMD_ADR
192240. BNX2_PCI_CFG_ACCESS_CMD_RD_REQ
192241. BNX2_PCI_CFG_ACCESS_CMD_WR_REQ
192242. BNX2_PCI_CFG_ACCESS_DATA
192243. BNX2_PCI_CONFIG_1
192244. BNX2_PCI_CONFIG_1_READ_BOUNDARY
192245. BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024
192246. BNX2_PCI_CONFIG_1_READ_BOUNDARY_128
192247. BNX2_PCI_CONFIG_1_READ_BOUNDARY_16
192248. BNX2_PCI_CONFIG_1_READ_BOUNDARY_256
192249. BNX2_PCI_CONFIG_1_READ_BOUNDARY_32
192250. BNX2_PCI_CONFIG_1_READ_BOUNDARY_512
192251. BNX2_PCI_CONFIG_1_READ_BOUNDARY_64
192252. BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF
192253. BNX2_PCI_CONFIG_1_RESERVED0
192254. BNX2_PCI_CONFIG_1_RESERVED1
192255. BNX2_PCI_CONFIG_1_WRITE_BOUNDARY
192256. BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024
192257. BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128
192258. BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16
192259. BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256
192260. BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32
192261. BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512
192262. BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64
192263. BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF
192264. BNX2_PCI_CONFIG_2
192265. BNX2_PCI_CONFIG_2_BAR1_64ENA
192266. BNX2_PCI_CONFIG_2_BAR1_SIZE
192267. BNX2_PCI_CONFIG_2_BAR1_SIZE_128K
192268. BNX2_PCI_CONFIG_2_BAR1_SIZE_128M
192269. BNX2_PCI_CONFIG_2_BAR1_SIZE_16M
192270. BNX2_PCI_CONFIG_2_BAR1_SIZE_1G
192271. BNX2_PCI_CONFIG_2_BAR1_SIZE_1M
192272. BNX2_PCI_CONFIG_2_BAR1_SIZE_256K
192273. BNX2_PCI_CONFIG_2_BAR1_SIZE_256M
192274. BNX2_PCI_CONFIG_2_BAR1_SIZE_2M
192275. BNX2_PCI_CONFIG_2_BAR1_SIZE_32M
192276. BNX2_PCI_CONFIG_2_BAR1_SIZE_4M
192277. BNX2_PCI_CONFIG_2_BAR1_SIZE_512K
192278. BNX2_PCI_CONFIG_2_BAR1_SIZE_512M
192279. BNX2_PCI_CONFIG_2_BAR1_SIZE_64K
192280. BNX2_PCI_CONFIG_2_BAR1_SIZE_64M
192281. BNX2_PCI_CONFIG_2_BAR1_SIZE_8M
192282. BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED
192283. BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI
192284. BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY
192285. BNX2_PCI_CONFIG_2_EXP_ROM_RETRY
192286. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE
192287. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K
192288. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K
192289. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M
192290. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K
192291. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M
192292. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K
192293. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K
192294. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M
192295. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K
192296. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K
192297. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M
192298. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K
192299. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K
192300. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K
192301. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M
192302. BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED
192303. BNX2_PCI_CONFIG_2_FIRST_CFG_DONE
192304. BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR
192305. BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT
192306. BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT
192307. BNX2_PCI_CONFIG_2_MAX_READ_LIMIT
192308. BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K
192309. BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K
192310. BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K
192311. BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512
192312. BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT
192313. BNX2_PCI_CONFIG_2_RESERVED0
192314. BNX2_PCI_CONFIG_2_RESERVED0_XI
192315. BNX2_PCI_CONFIG_3
192316. BNX2_PCI_CONFIG_3_FORCE_PME
192317. BNX2_PCI_CONFIG_3_PCI_POWER
192318. BNX2_PCI_CONFIG_3_PME_ENABLE
192319. BNX2_PCI_CONFIG_3_PME_STATUS
192320. BNX2_PCI_CONFIG_3_PM_STATE
192321. BNX2_PCI_CONFIG_3_REG_STICKY_BYTE
192322. BNX2_PCI_CONFIG_3_STICKY_BYTE
192323. BNX2_PCI_CONFIG_3_VAUX_PRESET
192324. BNX2_PCI_DEVICE_CAPABILITY
192325. BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT
192326. BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY
192327. BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY
192328. BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED
192329. BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT
192330. BNX2_PCI_EXP_ROM_ADDR
192331. BNX2_PCI_EXP_ROM_ADDR_ADDRESS
192332. BNX2_PCI_EXP_ROM_ADDR_REQ
192333. BNX2_PCI_EXP_ROM_DATA
192334. BNX2_PCI_GRC_WINDOW1_ADDR
192335. BNX2_PCI_GRC_WINDOW1_ADDR_VALUE
192336. BNX2_PCI_GRC_WINDOW2_ADDR
192337. BNX2_PCI_GRC_WINDOW2_ADDR_VALUE
192338. BNX2_PCI_GRC_WINDOW2_BASE
192339. BNX2_PCI_GRC_WINDOW3_ADDR
192340. BNX2_PCI_GRC_WINDOW3_ADDR_VALUE
192341. BNX2_PCI_GRC_WINDOW3_BASE
192342. BNX2_PCI_GRC_WINDOW_ADDR
192343. BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN
192344. BNX2_PCI_GRC_WINDOW_ADDR_VALUE
192345. BNX2_PCI_ID_VAL1
192346. BNX2_PCI_ID_VAL1_DEVICE_ID
192347. BNX2_PCI_ID_VAL1_VENDOR_ID
192348. BNX2_PCI_ID_VAL2
192349. BNX2_PCI_ID_VAL2_SUBSYSTEM_ID
192350. BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID
192351. BNX2_PCI_ID_VAL3
192352. BNX2_PCI_ID_VAL3_CLASS_CODE
192353. BNX2_PCI_ID_VAL3_REVISION_ID
192354. BNX2_PCI_ID_VAL4
192355. BNX2_PCI_ID_VAL4_CAP_ENA
192356. BNX2_PCI_ID_VAL4_CAP_ENA_0
192357. BNX2_PCI_ID_VAL4_CAP_ENA_1
192358. BNX2_PCI_ID_VAL4_CAP_ENA_10
192359. BNX2_PCI_ID_VAL4_CAP_ENA_11
192360. BNX2_PCI_ID_VAL4_CAP_ENA_12
192361. BNX2_PCI_ID_VAL4_CAP_ENA_13
192362. BNX2_PCI_ID_VAL4_CAP_ENA_14
192363. BNX2_PCI_ID_VAL4_CAP_ENA_15
192364. BNX2_PCI_ID_VAL4_CAP_ENA_2
192365. BNX2_PCI_ID_VAL4_CAP_ENA_3
192366. BNX2_PCI_ID_VAL4_CAP_ENA_4
192367. BNX2_PCI_ID_VAL4_CAP_ENA_5
192368. BNX2_PCI_ID_VAL4_CAP_ENA_6
192369. BNX2_PCI_ID_VAL4_CAP_ENA_7
192370. BNX2_PCI_ID_VAL4_CAP_ENA_8
192371. BNX2_PCI_ID_VAL4_CAP_ENA_9
192372. BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE
192373. BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE
192374. BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0
192375. BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21
192376. BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10
192377. BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0
192378. BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21
192379. BNX2_PCI_ID_VAL4_MSI_ENABLE
192380. BNX2_PCI_ID_VAL4_MSI_LIMIT
192381. BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP
192382. BNX2_PCI_ID_VAL4_MULTI_MSG_CAP
192383. BNX2_PCI_ID_VAL4_PM_SCALE_PRG
192384. BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0
192385. BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1
192386. BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2
192387. BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3
192388. BNX2_PCI_ID_VAL4_RESERVED0
192389. BNX2_PCI_ID_VAL4_RESERVED2
192390. BNX2_PCI_ID_VAL4_RESERVED3
192391. BNX2_PCI_ID_VAL4_RESERVED3_XI
192392. BNX2_PCI_ID_VAL5
192393. BNX2_PCI_ID_VAL5_D1_SUPPORT
192394. BNX2_PCI_ID_VAL5_D2_SUPPORT
192395. BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI
192396. BNX2_PCI_ID_VAL5_PME_IN_D0
192397. BNX2_PCI_ID_VAL5_PME_IN_D1
192398. BNX2_PCI_ID_VAL5_PME_IN_D2
192399. BNX2_PCI_ID_VAL5_PME_IN_D3_HOT
192400. BNX2_PCI_ID_VAL5_PM_VERSION_XI
192401. BNX2_PCI_ID_VAL5_RESERVED0_TE
192402. BNX2_PCI_ID_VAL5_RESERVED0_XI
192403. BNX2_PCI_ID_VAL6
192404. BNX2_PCI_ID_VAL6_BIST
192405. BNX2_PCI_ID_VAL6_MAX_LAT
192406. BNX2_PCI_ID_VAL6_MIN_GNT
192407. BNX2_PCI_ID_VAL6_RESERVED0
192408. BNX2_PCI_LINK_CAPABILITY
192409. BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT
192410. BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT
192411. BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT
192412. BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101
192413. BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110
192414. BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT
192415. BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101
192416. BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110
192417. BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT
192418. BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001
192419. BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010
192420. BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT
192421. BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001
192422. BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010
192423. BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED
192424. BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001
192425. BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010
192426. BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH
192427. BNX2_PCI_LINK_CAPABILITY_PORT_NUM
192428. BNX2_PCI_MSIX_CONTROL
192429. BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ
192430. BNX2_PCI_MSIX_CONTROL_RESERVED0
192431. BNX2_PCI_MSIX_PBA_OFF_BIT
192432. BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR
192433. BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF
192434. BNX2_PCI_MSIX_TBL_OFF_BIR
192435. BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR
192436. BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF
192437. BNX2_PCI_MSI_ADDR_H
192438. BNX2_PCI_MSI_ADDR_L
192439. BNX2_PCI_MSI_ADDR_L_VAL
192440. BNX2_PCI_MSI_DATA
192441. BNX2_PCI_MSI_DATA_MSI_DATA
192442. BNX2_PCI_MSI_MASK
192443. BNX2_PCI_MSI_MASK_MSI_MASK
192444. BNX2_PCI_MSI_PEND
192445. BNX2_PCI_MSI_PEND_MSI_PEND
192446. BNX2_PCI_PCIE_CAPABILITY
192447. BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1
192448. BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM
192449. BNX2_PCI_PCIE_DEVICE_CAPABILITY_2
192450. BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP
192451. BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP
192452. BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED
192453. BNX2_PCI_PCIE_LINK_CAPABILITY_2
192454. BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED
192455. BNX2_PCI_PCIX_EXTENDED_STATUS
192456. BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST
192457. BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP
192458. BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS
192459. BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX
192460. BNX2_PCI_PM_DATA_A
192461. BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG
192462. BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG
192463. BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG
192464. BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG
192465. BNX2_PCI_PM_DATA_B
192466. BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG
192467. BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG
192468. BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG
192469. BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG
192470. BNX2_PCI_PM_DATA_C
192471. BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG
192472. BNX2_PCI_PM_DATA_C_RESERVED0
192473. BNX2_PCI_SWAP_DIAG0
192474. BNX2_PCI_SWAP_DIAG1
192475. BNX2_PCI_VPD_ADDR_FLAG
192476. BNX2_PCI_VPD_ADDR_FLAG_ADDRESS
192477. BNX2_PCI_VPD_ADDR_FLAG_MSK
192478. BNX2_PCI_VPD_ADDR_FLAG_SL
192479. BNX2_PCI_VPD_ADDR_FLAG_WR
192480. BNX2_PCI_VPD_DATA
192481. BNX2_PCI_VPD_INTF
192482. BNX2_PCI_VPD_INTF_INTF_REQ
192483. BNX2_PG_CTX_MAP
192484. BNX2_PHY_FLAG_2_5G_CAPABLE
192485. BNX2_PHY_FLAG_CRC_FIX
192486. BNX2_PHY_FLAG_DIS_EARLY_DAC
192487. BNX2_PHY_FLAG_FORCED_DOWN
192488. BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING
192489. BNX2_PHY_FLAG_INT_MODE_LINK_READY
192490. BNX2_PHY_FLAG_INT_MODE_MASK
192491. BNX2_PHY_FLAG_MDIX
192492. BNX2_PHY_FLAG_NO_PARALLEL
192493. BNX2_PHY_FLAG_PARALLEL_DETECT
192494. BNX2_PHY_FLAG_REMOTE_PHY_CAP
192495. BNX2_PHY_FLAG_SERDES
192496. BNX2_PHY_LOOPBACK
192497. BNX2_PHY_LOOPBACK_FAILED
192498. BNX2_PM_OPS
192499. BNX2_PORT2_FEATURE
192500. BNX2_PORT2_FEATURE_IMD
192501. BNX2_PORT2_FEATURE_MBA
192502. BNX2_PORT2_FEATURE_VLAN
192503. BNX2_PORT2_FEATURE_WOL
192504. BNX2_PORT_FEATURE
192505. BNX2_PORT_FEATURE_ASF_ENABLED
192506. BNX2_PORT_FEATURE_BAR1_SIZE_128K
192507. BNX2_PORT_FEATURE_BAR1_SIZE_128M
192508. BNX2_PORT_FEATURE_BAR1_SIZE_16M
192509. BNX2_PORT_FEATURE_BAR1_SIZE_1G
192510. BNX2_PORT_FEATURE_BAR1_SIZE_1M
192511. BNX2_PORT_FEATURE_BAR1_SIZE_256K
192512. BNX2_PORT_FEATURE_BAR1_SIZE_256M
192513. BNX2_PORT_FEATURE_BAR1_SIZE_2M
192514. BNX2_PORT_FEATURE_BAR1_SIZE_32M
192515. BNX2_PORT_FEATURE_BAR1_SIZE_4M
192516. BNX2_PORT_FEATURE_BAR1_SIZE_512K
192517. BNX2_PORT_FEATURE_BAR1_SIZE_512M
192518. BNX2_PORT_FEATURE_BAR1_SIZE_64K
192519. BNX2_PORT_FEATURE_BAR1_SIZE_64M
192520. BNX2_PORT_FEATURE_BAR1_SIZE_8M
192521. BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED
192522. BNX2_PORT_FEATURE_BAR1_SIZE_MASK
192523. BNX2_PORT_FEATURE_IMD
192524. BNX2_PORT_FEATURE_IMD_ENABLED
192525. BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT
192526. BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE
192527. BNX2_PORT_FEATURE_MBA
192528. BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO
192529. BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS
192530. BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H
192531. BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H
192532. BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK
192533. BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS
192534. BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP
192535. BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK
192536. BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE
192537. BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL
192538. BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS
192539. BNX2_PORT_FEATURE_MBA_ENABLED
192540. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K
192541. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K
192542. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M
192543. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K
192544. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M
192545. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K
192546. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K
192547. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M
192548. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K
192549. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K
192550. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M
192551. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K
192552. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K
192553. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K
192554. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M
192555. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED
192556. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK
192557. BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS
192558. BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B
192559. BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S
192560. BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL
192561. BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF
192562. BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL
192563. BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF
192564. BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL
192565. BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF
192566. BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG
192567. BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK
192568. BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS
192569. BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK
192570. BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS
192571. BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE
192572. BNX2_PORT_FEATURE_MBA_VLAN_ENABLE
192573. BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK
192574. BNX2_PORT_FEATURE_VLAN
192575. BNX2_PORT_FEATURE_WOL
192576. BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000
192577. BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI
192578. BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE
192579. BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC
192580. BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI
192581. BNX2_PORT_FEATURE_WOL_DEFAULT_MASK
192582. BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS
192583. BNX2_PORT_FEATURE_WOL_ENABLED
192584. BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL
192585. BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF
192586. BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL
192587. BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF
192588. BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL
192589. BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF
192590. BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG
192591. BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK
192592. BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP
192593. BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP
192594. BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G
192595. BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G
192596. BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN
192597. BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK
192598. BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK
192599. BNX2_PORT_HW_CFG_CONFIG
192600. BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER
192601. BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER
192602. BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER
192603. BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER
192604. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER
192605. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER
192606. BNX2_PORT_HW_CFG_MAC_LOWER
192607. BNX2_PORT_HW_CFG_MAC_UPPER
192608. BNX2_PORT_HW_CFG_UPPERMAC_MASK
192609. BNX2_RBUF_BUF_DATA
192610. BNX2_RBUF_CLIST_DATA
192611. BNX2_RBUF_COMMAND
192612. BNX2_RBUF_COMMAND_ALLOC_REQ
192613. BNX2_RBUF_COMMAND_CU_ISOLATE_XI
192614. BNX2_RBUF_COMMAND_ENABLED
192615. BNX2_RBUF_COMMAND_EN_PRI_CHANGE_XI
192616. BNX2_RBUF_COMMAND_EN_PRI_CHNGE_TE
192617. BNX2_RBUF_COMMAND_FREE_INIT
192618. BNX2_RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI
192619. BNX2_RBUF_COMMAND_OVER_FREE
192620. BNX2_RBUF_COMMAND_PKT_OFFSET_OVFL
192621. BNX2_RBUF_COMMAND_RAM_INIT
192622. BNX2_RBUF_CONFIG
192623. BNX2_RBUF_CONFIG2
192624. BNX2_RBUF_CONFIG2_MAC_DROP_TRIP
192625. BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL
192626. BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP
192627. BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL
192628. BNX2_RBUF_CONFIG2_VAL
192629. BNX2_RBUF_CONFIG3
192630. BNX2_RBUF_CONFIG3_CU_DROP_TRIP
192631. BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL
192632. BNX2_RBUF_CONFIG3_CU_KEEP_TRIP
192633. BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL
192634. BNX2_RBUF_CONFIG3_VAL
192635. BNX2_RBUF_CONFIG_VAL
192636. BNX2_RBUF_CONFIG_XOFF_TRIP
192637. BNX2_RBUF_CONFIG_XOFF_TRIP_VAL
192638. BNX2_RBUF_CONFIG_XON_TRIP
192639. BNX2_RBUF_CONFIG_XON_TRIP_VAL
192640. BNX2_RBUF_FW_BUF_ALLOC
192641. BNX2_RBUF_FW_BUF_ALLOC_ALLOC_REQ
192642. BNX2_RBUF_FW_BUF_ALLOC_TYPE
192643. BNX2_RBUF_FW_BUF_ALLOC_VALUE
192644. BNX2_RBUF_FW_BUF_FREE
192645. BNX2_RBUF_FW_BUF_FREE_COUNT
192646. BNX2_RBUF_FW_BUF_FREE_FREE_REQ
192647. BNX2_RBUF_FW_BUF_FREE_HEAD
192648. BNX2_RBUF_FW_BUF_FREE_TAIL
192649. BNX2_RBUF_FW_BUF_FREE_TYPE
192650. BNX2_RBUF_FW_BUF_SEL
192651. BNX2_RBUF_FW_BUF_SEL_COUNT
192652. BNX2_RBUF_FW_BUF_SEL_HEAD
192653. BNX2_RBUF_FW_BUF_SEL_SEL_REQ
192654. BNX2_RBUF_FW_BUF_SEL_TAIL
192655. BNX2_RBUF_PKT_DATA
192656. BNX2_RBUF_STATUS1
192657. BNX2_RBUF_STATUS1_FREE_COUNT
192658. BNX2_RBUF_STATUS2
192659. BNX2_RBUF_STATUS2_FREE_HEAD
192660. BNX2_RBUF_STATUS2_FREE_TAIL
192661. BNX2_RD
192662. BNX2_REGDUMP_LEN
192663. BNX2_RLUP_RSS_COMMAND
192664. BNX2_RLUP_RSS_COMMAND_HASH_MASK
192665. BNX2_RLUP_RSS_COMMAND_READ
192666. BNX2_RLUP_RSS_COMMAND_RSS_IND_TABLE_ADDR
192667. BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK
192668. BNX2_RLUP_RSS_COMMAND_WRITE
192669. BNX2_RLUP_RSS_CONFIG
192670. BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI
192671. BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI
192672. BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI
192673. BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI
192674. BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI
192675. BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI
192676. BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI
192677. BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI
192678. BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI
192679. BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI
192680. BNX2_RLUP_RSS_DATA
192681. BNX2_RPHY_COPPER_LINK
192682. BNX2_RPHY_FLAGS
192683. BNX2_RPHY_LOAD_SIGNATURE
192684. BNX2_RPHY_SERDES_LINK
192685. BNX2_RPHY_SIGNATURE
192686. BNX2_RPM_ACPI_BYTE_ENABLE_CTRL
192687. BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS
192688. BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD
192689. BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_INIT
192690. BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_MODE
192691. BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_WR
192692. BNX2_RPM_ACPI_DATA
192693. BNX2_RPM_ACPI_DATA_PATTERN_BE
192694. BNX2_RPM_ACPI_DBG_BUF_W00
192695. BNX2_RPM_ACPI_DBG_BUF_W01
192696. BNX2_RPM_ACPI_DBG_BUF_W02
192697. BNX2_RPM_ACPI_DBG_BUF_W03
192698. BNX2_RPM_ACPI_DBG_BUF_W10
192699. BNX2_RPM_ACPI_DBG_BUF_W11
192700. BNX2_RPM_ACPI_DBG_BUF_W12
192701. BNX2_RPM_ACPI_DBG_BUF_W13
192702. BNX2_RPM_ACPI_DBG_BUF_W20
192703. BNX2_RPM_ACPI_DBG_BUF_W21
192704. BNX2_RPM_ACPI_DBG_BUF_W22
192705. BNX2_RPM_ACPI_DBG_BUF_W23
192706. BNX2_RPM_ACPI_DBG_BUF_W30
192707. BNX2_RPM_ACPI_DBG_BUF_W31
192708. BNX2_RPM_ACPI_DBG_BUF_W32
192709. BNX2_RPM_ACPI_DBG_BUF_W33
192710. BNX2_RPM_ACPI_PATTERN_CRC0
192711. BNX2_RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0
192712. BNX2_RPM_ACPI_PATTERN_CRC1
192713. BNX2_RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1
192714. BNX2_RPM_ACPI_PATTERN_CRC2
192715. BNX2_RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2
192716. BNX2_RPM_ACPI_PATTERN_CRC3
192717. BNX2_RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3
192718. BNX2_RPM_ACPI_PATTERN_CRC4
192719. BNX2_RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4
192720. BNX2_RPM_ACPI_PATTERN_CRC5
192721. BNX2_RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5
192722. BNX2_RPM_ACPI_PATTERN_CRC6
192723. BNX2_RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6
192724. BNX2_RPM_ACPI_PATTERN_CRC7
192725. BNX2_RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7
192726. BNX2_RPM_ACPI_PATTERN_CTRL
192727. BNX2_RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR
192728. BNX2_RPM_ACPI_PATTERN_CTRL_PATTERN_ID
192729. BNX2_RPM_ACPI_PATTERN_CTRL_WR
192730. BNX2_RPM_ACPI_PATTERN_LEN0
192731. BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0
192732. BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1
192733. BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2
192734. BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3
192735. BNX2_RPM_ACPI_PATTERN_LEN1
192736. BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4
192737. BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5
192738. BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6
192739. BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7
192740. BNX2_RPM_COMMAND
192741. BNX2_RPM_COMMAND_ENABLED
192742. BNX2_RPM_COMMAND_OVERRUN_ABORT
192743. BNX2_RPM_CONFIG
192744. BNX2_RPM_CONFIG_ACPI_ENA
192745. BNX2_RPM_CONFIG_ACPI_KEEP
192746. BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT
192747. BNX2_RPM_CONFIG_IGNORE_VLAN
192748. BNX2_RPM_CONFIG_MP_KEEP
192749. BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM
192750. BNX2_RPM_CONFIG_SORT_VECT_VAL
192751. BNX2_RPM_DEBUG0
192752. BNX2_RPM_DEBUG0_DONE
192753. BNX2_RPM_DEBUG0_FM_BCNT
192754. BNX2_RPM_DEBUG0_FM_STARTED
192755. BNX2_RPM_DEBUG0_IGNORE_VLAN
192756. BNX2_RPM_DEBUG0_IP_MORE_FRGMT
192757. BNX2_RPM_DEBUG0_LLC_SNAP
192758. BNX2_RPM_DEBUG0_RP_ENA_ACTIVE
192759. BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM
192760. BNX2_RPM_DEBUG0_T_DATA_OFST_VLD
192761. BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR
192762. BNX2_RPM_DEBUG0_T_IP_OFST_VLD
192763. BNX2_RPM_DEBUG0_T_TCP_OFST_VLD
192764. BNX2_RPM_DEBUG0_T_UDP_OFST_VLD
192765. BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM
192766. BNX2_RPM_DEBUG0_WAIT_4_DONE
192767. BNX2_RPM_DEBUG1
192768. BNX2_RPM_DEBUG1_EOF_0XTRA_WD
192769. BNX2_RPM_DEBUG1_FSM_CUR_ST
192770. BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY
192771. BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT
192772. BNX2_RPM_DEBUG1_FSM_CUR_ST_AH
192773. BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA
192774. BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP
192775. BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD
192776. BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP
192777. BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC
192778. BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL
192779. BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP
192780. BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE
192781. BNX2_RPM_DEBUG1_FSM_CUR_ST_IP
192782. BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START
192783. BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT
192784. BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP
192785. BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP
192786. BNX2_RPM_DEBUG1_HDR_BCNT
192787. BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D
192788. BNX2_RPM_DEBUG1_VLAN_REMOVED_D1
192789. BNX2_RPM_DEBUG1_VLAN_REMOVED_D2
192790. BNX2_RPM_DEBUG2
192791. BNX2_RPM_DEBUG2_CMD_HIT_VEC
192792. BNX2_RPM_DEBUG2_FM_DISCARD
192793. BNX2_RPM_DEBUG2_IPIPE_EMPTY
192794. BNX2_RPM_DEBUG2_IP_BCNT
192795. BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1
192796. BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2
192797. BNX2_RPM_DEBUG2_THIS_CMD_M1
192798. BNX2_RPM_DEBUG2_THIS_CMD_M2
192799. BNX2_RPM_DEBUG2_THIS_CMD_M3
192800. BNX2_RPM_DEBUG2_THIS_CMD_M4
192801. BNX2_RPM_DEBUG3
192802. BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR
192803. BNX2_RPM_DEBUG3_CCODE_EOF_ERROR
192804. BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT
192805. BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL
192806. BNX2_RPM_DEBUG3_DROP_NXT
192807. BNX2_RPM_DEBUG3_DROP_NXT_VLD
192808. BNX2_RPM_DEBUG3_FTQ_FSM
192809. BNX2_RPM_DEBUG3_FTQ_FSM_IDLE
192810. BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK
192811. BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE
192812. BNX2_RPM_DEBUG3_MBALLOC_FSM
192813. BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF
192814. BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF
192815. BNX2_RPM_DEBUG3_MBFREE_FSM
192816. BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE
192817. BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK
192818. BNX2_RPM_DEBUG3_MBWRITE_FSM
192819. BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA
192820. BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE
192821. BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF
192822. BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA
192823. BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD
192824. BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF
192825. BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK
192826. BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF
192827. BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP
192828. BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ
192829. BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ
192830. BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT
192831. BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT
192832. BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT
192833. BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL
192834. BNX2_RPM_DEBUG4
192835. BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE
192836. BNX2_RPM_DEBUG4_DFIFO_EMPTY
192837. BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER
192838. BNX2_RPM_DEBUG4_MBWRITE_FSM
192839. BNX2_RPM_DEBUG5
192840. BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY
192841. BNX2_RPM_DEBUG5_HOLDREG_DISCARD
192842. BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY
192843. BNX2_RPM_DEBUG5_HOLDREG_FULL_T
192844. BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL
192845. BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY
192846. BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY
192847. BNX2_RPM_DEBUG5_HOLDREG_RD
192848. BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT
192849. BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY
192850. BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR
192851. BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR
192852. BNX2_RPM_DEBUG5_RDROP_MC_EMPTY
192853. BNX2_RPM_DEBUG5_RDROP_MC_RPTR
192854. BNX2_RPM_DEBUG5_RDROP_RC_RPTR
192855. BNX2_RPM_DEBUG5_RDROP_WPTR
192856. BNX2_RPM_DEBUG6
192857. BNX2_RPM_DEBUG6_ACPI_VEC
192858. BNX2_RPM_DEBUG6_VEC
192859. BNX2_RPM_DEBUG7
192860. BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC
192861. BNX2_RPM_DEBUG8
192862. BNX2_RPM_DEBUG8_ALL_DONE
192863. BNX2_RPM_DEBUG8_BYTE_CTR
192864. BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2
192865. BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3
192866. BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT
192867. BNX2_RPM_DEBUG8_COMPARE_AT_W0
192868. BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA
192869. BNX2_RPM_DEBUG8_EOF_DET
192870. BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES
192871. BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES
192872. BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES
192873. BNX2_RPM_DEBUG8_PS_ACPI_FSM
192874. BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE
192875. BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR
192876. BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR
192877. BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR
192878. BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF
192879. BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR
192880. BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR
192881. BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR
192882. BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR
192883. BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA
192884. BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF
192885. BNX2_RPM_DEBUG8_SOF_DET
192886. BNX2_RPM_DEBUG8_THBUF_ADDR
192887. BNX2_RPM_DEBUG8_WAIT_4_SOF
192888. BNX2_RPM_DEBUG9
192889. BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN
192890. BNX2_RPM_DEBUG9_ACPI_MATCH_INT
192891. BNX2_RPM_DEBUG9_ACPI_RDE_PAT_ID_XI
192892. BNX2_RPM_DEBUG9_AEOF_DE_XI
192893. BNX2_RPM_DEBUG9_BEMEM_R_XI
192894. BNX2_RPM_DEBUG9_CALCRC_BUFFER_VLD_XI
192895. BNX2_RPM_DEBUG9_CALCRC_RESULT_XI
192896. BNX2_RPM_DEBUG9_DATA_IN_VL_XI
192897. BNX2_RPM_DEBUG9_EOF_VLDBYTE_XI
192898. BNX2_RPM_DEBUG9_EO_XI
192899. BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED
192900. BNX2_RPM_DEBUG9_OUTFIFO_COUNT
192901. BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED
192902. BNX2_RPM_DEBUG9_RDE_ACPI_RDY
192903. BNX2_RPM_DEBUG9_SO_XI
192904. BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT
192905. BNX2_RPM_DEBUG9_WD64_CT_XI
192906. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0
192907. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER
192908. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN
192909. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN
192910. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE
192911. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1
192912. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER
192913. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN
192914. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN
192915. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE
192916. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2
192917. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER
192918. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN
192919. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN
192920. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE
192921. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3
192922. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER
192923. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN
192924. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN
192925. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE
192926. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4
192927. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER
192928. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN
192929. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN
192930. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE
192931. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5
192932. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER
192933. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN
192934. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN
192935. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE
192936. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6
192937. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER
192938. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN
192939. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN
192940. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE
192941. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7
192942. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER
192943. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN
192944. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN
192945. BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE
192946. BNX2_RPM_MGMT_PKT_CTRL
192947. BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN
192948. BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN
192949. BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE
192950. BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT
192951. BNX2_RPM_RC_CNTL_0
192952. BNX2_RPM_RC_CNTL_0_CLASS
192953. BNX2_RPM_RC_CNTL_0_CMDSEL
192954. BNX2_RPM_RC_CNTL_0_CMDSEL_XI
192955. BNX2_RPM_RC_CNTL_0_COMP
192956. BNX2_RPM_RC_CNTL_0_COMP_EQUAL
192957. BNX2_RPM_RC_CNTL_0_COMP_GREATER
192958. BNX2_RPM_RC_CNTL_0_COMP_LESS
192959. BNX2_RPM_RC_CNTL_0_COMP_NEQUAL
192960. BNX2_RPM_RC_CNTL_0_DISCARD
192961. BNX2_RPM_RC_CNTL_0_HDR_TYPE
192962. BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA
192963. BNX2_RPM_RC_CNTL_0_HDR_TYPE_ICMPV6
192964. BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP
192965. BNX2_RPM_RC_CNTL_0_HDR_TYPE_START
192966. BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP
192967. BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP
192968. BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP
192969. BNX2_RPM_RC_CNTL_0_MAP
192970. BNX2_RPM_RC_CNTL_0_MAP_XI
192971. BNX2_RPM_RC_CNTL_0_MASK
192972. BNX2_RPM_RC_CNTL_0_NBIT
192973. BNX2_RPM_RC_CNTL_0_OFFSET
192974. BNX2_RPM_RC_CNTL_0_P1
192975. BNX2_RPM_RC_CNTL_0_P2
192976. BNX2_RPM_RC_CNTL_0_P3
192977. BNX2_RPM_RC_CNTL_0_P4
192978. BNX2_RPM_RC_CNTL_0_PRIORITY
192979. BNX2_RPM_RC_CNTL_0_SBIT
192980. BNX2_RPM_RC_CNTL_1
192981. BNX2_RPM_RC_CNTL_10
192982. BNX2_RPM_RC_CNTL_10_A
192983. BNX2_RPM_RC_CNTL_10_B
192984. BNX2_RPM_RC_CNTL_10_CLASS_XI
192985. BNX2_RPM_RC_CNTL_10_CMDSEL_XI
192986. BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI
192987. BNX2_RPM_RC_CNTL_10_COMP_GREATER_XI
192988. BNX2_RPM_RC_CNTL_10_COMP_LESS_XI
192989. BNX2_RPM_RC_CNTL_10_COMP_NEQUAL_XI
192990. BNX2_RPM_RC_CNTL_10_COMP_XI
192991. BNX2_RPM_RC_CNTL_10_DISCARD_XI
192992. BNX2_RPM_RC_CNTL_10_HDR_TYPE_DATA_XI
192993. BNX2_RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI
192994. BNX2_RPM_RC_CNTL_10_HDR_TYPE_IP_XI
192995. BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI
192996. BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI
192997. BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_XI
192998. BNX2_RPM_RC_CNTL_10_HDR_TYPE_UDP_XI
192999. BNX2_RPM_RC_CNTL_10_HDR_TYPE_XI
193000. BNX2_RPM_RC_CNTL_10_MAP_XI
193001. BNX2_RPM_RC_CNTL_10_MASK_XI
193002. BNX2_RPM_RC_CNTL_10_NBIT_XI
193003. BNX2_RPM_RC_CNTL_10_OFFSET_XI
193004. BNX2_RPM_RC_CNTL_10_P1_XI
193005. BNX2_RPM_RC_CNTL_10_P2_XI
193006. BNX2_RPM_RC_CNTL_10_P3_XI
193007. BNX2_RPM_RC_CNTL_10_P4_XI
193008. BNX2_RPM_RC_CNTL_10_PRIORITY_XI
193009. BNX2_RPM_RC_CNTL_10_SBIT_XI
193010. BNX2_RPM_RC_CNTL_11
193011. BNX2_RPM_RC_CNTL_11_A
193012. BNX2_RPM_RC_CNTL_11_B
193013. BNX2_RPM_RC_CNTL_11_CLASS_XI
193014. BNX2_RPM_RC_CNTL_11_CMDSEL_XI
193015. BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI
193016. BNX2_RPM_RC_CNTL_11_COMP_GREATER_XI
193017. BNX2_RPM_RC_CNTL_11_COMP_LESS_XI
193018. BNX2_RPM_RC_CNTL_11_COMP_NEQUAL_XI
193019. BNX2_RPM_RC_CNTL_11_COMP_XI
193020. BNX2_RPM_RC_CNTL_11_DISCARD_XI
193021. BNX2_RPM_RC_CNTL_11_HDR_TYPE_DATA_XI
193022. BNX2_RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI
193023. BNX2_RPM_RC_CNTL_11_HDR_TYPE_IP_XI
193024. BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI
193025. BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI
193026. BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_XI
193027. BNX2_RPM_RC_CNTL_11_HDR_TYPE_UDP_XI
193028. BNX2_RPM_RC_CNTL_11_HDR_TYPE_XI
193029. BNX2_RPM_RC_CNTL_11_MAP_XI
193030. BNX2_RPM_RC_CNTL_11_MASK_XI
193031. BNX2_RPM_RC_CNTL_11_NBIT_XI
193032. BNX2_RPM_RC_CNTL_11_OFFSET_XI
193033. BNX2_RPM_RC_CNTL_11_P1_XI
193034. BNX2_RPM_RC_CNTL_11_P2_XI
193035. BNX2_RPM_RC_CNTL_11_P3_XI
193036. BNX2_RPM_RC_CNTL_11_P4_XI
193037. BNX2_RPM_RC_CNTL_11_PRIORITY_XI
193038. BNX2_RPM_RC_CNTL_11_SBIT_XI
193039. BNX2_RPM_RC_CNTL_12
193040. BNX2_RPM_RC_CNTL_12_A
193041. BNX2_RPM_RC_CNTL_12_B
193042. BNX2_RPM_RC_CNTL_12_CLASS_XI
193043. BNX2_RPM_RC_CNTL_12_CMDSEL_XI
193044. BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI
193045. BNX2_RPM_RC_CNTL_12_COMP_GREATER_XI
193046. BNX2_RPM_RC_CNTL_12_COMP_LESS_XI
193047. BNX2_RPM_RC_CNTL_12_COMP_NEQUAL_XI
193048. BNX2_RPM_RC_CNTL_12_COMP_XI
193049. BNX2_RPM_RC_CNTL_12_DISCARD_XI
193050. BNX2_RPM_RC_CNTL_12_HDR_TYPE_DATA_XI
193051. BNX2_RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI
193052. BNX2_RPM_RC_CNTL_12_HDR_TYPE_IP_XI
193053. BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI
193054. BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI
193055. BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_XI
193056. BNX2_RPM_RC_CNTL_12_HDR_TYPE_UDP_XI
193057. BNX2_RPM_RC_CNTL_12_HDR_TYPE_XI
193058. BNX2_RPM_RC_CNTL_12_MAP_XI
193059. BNX2_RPM_RC_CNTL_12_MASK_XI
193060. BNX2_RPM_RC_CNTL_12_NBIT_XI
193061. BNX2_RPM_RC_CNTL_12_OFFSET_XI
193062. BNX2_RPM_RC_CNTL_12_P1_XI
193063. BNX2_RPM_RC_CNTL_12_P2_XI
193064. BNX2_RPM_RC_CNTL_12_P3_XI
193065. BNX2_RPM_RC_CNTL_12_P4_XI
193066. BNX2_RPM_RC_CNTL_12_PRIORITY_XI
193067. BNX2_RPM_RC_CNTL_12_SBIT_XI
193068. BNX2_RPM_RC_CNTL_13
193069. BNX2_RPM_RC_CNTL_13_A
193070. BNX2_RPM_RC_CNTL_13_B
193071. BNX2_RPM_RC_CNTL_13_CLASS_XI
193072. BNX2_RPM_RC_CNTL_13_CMDSEL_XI
193073. BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI
193074. BNX2_RPM_RC_CNTL_13_COMP_GREATER_XI
193075. BNX2_RPM_RC_CNTL_13_COMP_LESS_XI
193076. BNX2_RPM_RC_CNTL_13_COMP_NEQUAL_XI
193077. BNX2_RPM_RC_CNTL_13_COMP_XI
193078. BNX2_RPM_RC_CNTL_13_DISCARD_XI
193079. BNX2_RPM_RC_CNTL_13_HDR_TYPE_DATA_XI
193080. BNX2_RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI
193081. BNX2_RPM_RC_CNTL_13_HDR_TYPE_IP_XI
193082. BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI
193083. BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI
193084. BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_XI
193085. BNX2_RPM_RC_CNTL_13_HDR_TYPE_UDP_XI
193086. BNX2_RPM_RC_CNTL_13_HDR_TYPE_XI
193087. BNX2_RPM_RC_CNTL_13_MAP_XI
193088. BNX2_RPM_RC_CNTL_13_MASK_XI
193089. BNX2_RPM_RC_CNTL_13_NBIT_XI
193090. BNX2_RPM_RC_CNTL_13_OFFSET_XI
193091. BNX2_RPM_RC_CNTL_13_P1_XI
193092. BNX2_RPM_RC_CNTL_13_P2_XI
193093. BNX2_RPM_RC_CNTL_13_P3_XI
193094. BNX2_RPM_RC_CNTL_13_P4_XI
193095. BNX2_RPM_RC_CNTL_13_PRIORITY_XI
193096. BNX2_RPM_RC_CNTL_13_SBIT_XI
193097. BNX2_RPM_RC_CNTL_14
193098. BNX2_RPM_RC_CNTL_14_A
193099. BNX2_RPM_RC_CNTL_14_B
193100. BNX2_RPM_RC_CNTL_14_CLASS_XI
193101. BNX2_RPM_RC_CNTL_14_CMDSEL_XI
193102. BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI
193103. BNX2_RPM_RC_CNTL_14_COMP_GREATER_XI
193104. BNX2_RPM_RC_CNTL_14_COMP_LESS_XI
193105. BNX2_RPM_RC_CNTL_14_COMP_NEQUAL_XI
193106. BNX2_RPM_RC_CNTL_14_COMP_XI
193107. BNX2_RPM_RC_CNTL_14_DISCARD_XI
193108. BNX2_RPM_RC_CNTL_14_HDR_TYPE_DATA_XI
193109. BNX2_RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI
193110. BNX2_RPM_RC_CNTL_14_HDR_TYPE_IP_XI
193111. BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI
193112. BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI
193113. BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_XI
193114. BNX2_RPM_RC_CNTL_14_HDR_TYPE_UDP_XI
193115. BNX2_RPM_RC_CNTL_14_HDR_TYPE_XI
193116. BNX2_RPM_RC_CNTL_14_MAP_XI
193117. BNX2_RPM_RC_CNTL_14_MASK_XI
193118. BNX2_RPM_RC_CNTL_14_NBIT_XI
193119. BNX2_RPM_RC_CNTL_14_OFFSET_XI
193120. BNX2_RPM_RC_CNTL_14_P1_XI
193121. BNX2_RPM_RC_CNTL_14_P2_XI
193122. BNX2_RPM_RC_CNTL_14_P3_XI
193123. BNX2_RPM_RC_CNTL_14_P4_XI
193124. BNX2_RPM_RC_CNTL_14_PRIORITY_XI
193125. BNX2_RPM_RC_CNTL_14_SBIT_XI
193126. BNX2_RPM_RC_CNTL_15
193127. BNX2_RPM_RC_CNTL_15_A
193128. BNX2_RPM_RC_CNTL_15_B
193129. BNX2_RPM_RC_CNTL_15_CLASS_XI
193130. BNX2_RPM_RC_CNTL_15_CMDSEL_XI
193131. BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI
193132. BNX2_RPM_RC_CNTL_15_COMP_GREATER_XI
193133. BNX2_RPM_RC_CNTL_15_COMP_LESS_XI
193134. BNX2_RPM_RC_CNTL_15_COMP_NEQUAL_XI
193135. BNX2_RPM_RC_CNTL_15_COMP_XI
193136. BNX2_RPM_RC_CNTL_15_DISCARD_XI
193137. BNX2_RPM_RC_CNTL_15_HDR_TYPE_DATA_XI
193138. BNX2_RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI
193139. BNX2_RPM_RC_CNTL_15_HDR_TYPE_IP_XI
193140. BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI
193141. BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI
193142. BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_XI
193143. BNX2_RPM_RC_CNTL_15_HDR_TYPE_UDP_XI
193144. BNX2_RPM_RC_CNTL_15_HDR_TYPE_XI
193145. BNX2_RPM_RC_CNTL_15_MAP_XI
193146. BNX2_RPM_RC_CNTL_15_MASK_XI
193147. BNX2_RPM_RC_CNTL_15_NBIT_XI
193148. BNX2_RPM_RC_CNTL_15_OFFSET_XI
193149. BNX2_RPM_RC_CNTL_15_P1_XI
193150. BNX2_RPM_RC_CNTL_15_P2_XI
193151. BNX2_RPM_RC_CNTL_15_P3_XI
193152. BNX2_RPM_RC_CNTL_15_P4_XI
193153. BNX2_RPM_RC_CNTL_15_PRIORITY_XI
193154. BNX2_RPM_RC_CNTL_15_SBIT_XI
193155. BNX2_RPM_RC_CNTL_16
193156. BNX2_RPM_RC_CNTL_16_CLASS
193157. BNX2_RPM_RC_CNTL_16_CMDSEL
193158. BNX2_RPM_RC_CNTL_16_COMP
193159. BNX2_RPM_RC_CNTL_16_COMP_EQUAL
193160. BNX2_RPM_RC_CNTL_16_COMP_GREATER
193161. BNX2_RPM_RC_CNTL_16_COMP_LESS
193162. BNX2_RPM_RC_CNTL_16_COMP_NEQUAL
193163. BNX2_RPM_RC_CNTL_16_DISCARD
193164. BNX2_RPM_RC_CNTL_16_HDR_TYPE
193165. BNX2_RPM_RC_CNTL_16_HDR_TYPE_DATA
193166. BNX2_RPM_RC_CNTL_16_HDR_TYPE_ICMPV6
193167. BNX2_RPM_RC_CNTL_16_HDR_TYPE_IP
193168. BNX2_RPM_RC_CNTL_16_HDR_TYPE_START
193169. BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP
193170. BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP
193171. BNX2_RPM_RC_CNTL_16_HDR_TYPE_UDP
193172. BNX2_RPM_RC_CNTL_16_MAP
193173. BNX2_RPM_RC_CNTL_16_MASK
193174. BNX2_RPM_RC_CNTL_16_NBIT
193175. BNX2_RPM_RC_CNTL_16_OFFSET
193176. BNX2_RPM_RC_CNTL_16_P1
193177. BNX2_RPM_RC_CNTL_16_P2
193178. BNX2_RPM_RC_CNTL_16_P3
193179. BNX2_RPM_RC_CNTL_16_P4
193180. BNX2_RPM_RC_CNTL_16_PRIORITY
193181. BNX2_RPM_RC_CNTL_16_SBIT
193182. BNX2_RPM_RC_CNTL_17
193183. BNX2_RPM_RC_CNTL_17_CLASS
193184. BNX2_RPM_RC_CNTL_17_CMDSEL
193185. BNX2_RPM_RC_CNTL_17_COMP
193186. BNX2_RPM_RC_CNTL_17_COMP_EQUAL
193187. BNX2_RPM_RC_CNTL_17_COMP_GREATER
193188. BNX2_RPM_RC_CNTL_17_COMP_LESS
193189. BNX2_RPM_RC_CNTL_17_COMP_NEQUAL
193190. BNX2_RPM_RC_CNTL_17_DISCARD
193191. BNX2_RPM_RC_CNTL_17_HDR_TYPE
193192. BNX2_RPM_RC_CNTL_17_HDR_TYPE_DATA
193193. BNX2_RPM_RC_CNTL_17_HDR_TYPE_ICMPV6
193194. BNX2_RPM_RC_CNTL_17_HDR_TYPE_IP
193195. BNX2_RPM_RC_CNTL_17_HDR_TYPE_START
193196. BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP
193197. BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP
193198. BNX2_RPM_RC_CNTL_17_HDR_TYPE_UDP
193199. BNX2_RPM_RC_CNTL_17_MAP
193200. BNX2_RPM_RC_CNTL_17_MASK
193201. BNX2_RPM_RC_CNTL_17_NBIT
193202. BNX2_RPM_RC_CNTL_17_OFFSET
193203. BNX2_RPM_RC_CNTL_17_P1
193204. BNX2_RPM_RC_CNTL_17_P2
193205. BNX2_RPM_RC_CNTL_17_P3
193206. BNX2_RPM_RC_CNTL_17_P4
193207. BNX2_RPM_RC_CNTL_17_PRIORITY
193208. BNX2_RPM_RC_CNTL_17_SBIT
193209. BNX2_RPM_RC_CNTL_18
193210. BNX2_RPM_RC_CNTL_18_CLASS
193211. BNX2_RPM_RC_CNTL_18_CMDSEL
193212. BNX2_RPM_RC_CNTL_18_COMP
193213. BNX2_RPM_RC_CNTL_18_COMP_EQUAL
193214. BNX2_RPM_RC_CNTL_18_COMP_GREATER
193215. BNX2_RPM_RC_CNTL_18_COMP_LESS
193216. BNX2_RPM_RC_CNTL_18_COMP_NEQUAL
193217. BNX2_RPM_RC_CNTL_18_DISCARD
193218. BNX2_RPM_RC_CNTL_18_HDR_TYPE
193219. BNX2_RPM_RC_CNTL_18_HDR_TYPE_DATA
193220. BNX2_RPM_RC_CNTL_18_HDR_TYPE_ICMPV6
193221. BNX2_RPM_RC_CNTL_18_HDR_TYPE_IP
193222. BNX2_RPM_RC_CNTL_18_HDR_TYPE_START
193223. BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP
193224. BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP
193225. BNX2_RPM_RC_CNTL_18_HDR_TYPE_UDP
193226. BNX2_RPM_RC_CNTL_18_MAP
193227. BNX2_RPM_RC_CNTL_18_MASK
193228. BNX2_RPM_RC_CNTL_18_NBIT
193229. BNX2_RPM_RC_CNTL_18_OFFSET
193230. BNX2_RPM_RC_CNTL_18_P1
193231. BNX2_RPM_RC_CNTL_18_P2
193232. BNX2_RPM_RC_CNTL_18_P3
193233. BNX2_RPM_RC_CNTL_18_P4
193234. BNX2_RPM_RC_CNTL_18_PRIORITY
193235. BNX2_RPM_RC_CNTL_18_SBIT
193236. BNX2_RPM_RC_CNTL_19
193237. BNX2_RPM_RC_CNTL_19_CLASS
193238. BNX2_RPM_RC_CNTL_19_CMDSEL
193239. BNX2_RPM_RC_CNTL_19_COMP
193240. BNX2_RPM_RC_CNTL_19_COMP_EQUAL
193241. BNX2_RPM_RC_CNTL_19_COMP_GREATER
193242. BNX2_RPM_RC_CNTL_19_COMP_LESS
193243. BNX2_RPM_RC_CNTL_19_COMP_NEQUAL
193244. BNX2_RPM_RC_CNTL_19_DISCARD
193245. BNX2_RPM_RC_CNTL_19_HDR_TYPE
193246. BNX2_RPM_RC_CNTL_19_HDR_TYPE_DATA
193247. BNX2_RPM_RC_CNTL_19_HDR_TYPE_ICMPV6
193248. BNX2_RPM_RC_CNTL_19_HDR_TYPE_IP
193249. BNX2_RPM_RC_CNTL_19_HDR_TYPE_START
193250. BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP
193251. BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP
193252. BNX2_RPM_RC_CNTL_19_HDR_TYPE_UDP
193253. BNX2_RPM_RC_CNTL_19_MAP
193254. BNX2_RPM_RC_CNTL_19_MASK
193255. BNX2_RPM_RC_CNTL_19_NBIT
193256. BNX2_RPM_RC_CNTL_19_OFFSET
193257. BNX2_RPM_RC_CNTL_19_P1
193258. BNX2_RPM_RC_CNTL_19_P2
193259. BNX2_RPM_RC_CNTL_19_P3
193260. BNX2_RPM_RC_CNTL_19_P4
193261. BNX2_RPM_RC_CNTL_19_PRIORITY
193262. BNX2_RPM_RC_CNTL_19_SBIT
193263. BNX2_RPM_RC_CNTL_1_A
193264. BNX2_RPM_RC_CNTL_1_B
193265. BNX2_RPM_RC_CNTL_1_CLASS_XI
193266. BNX2_RPM_RC_CNTL_1_CMDSEL_XI
193267. BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI
193268. BNX2_RPM_RC_CNTL_1_COMP_GREATER_XI
193269. BNX2_RPM_RC_CNTL_1_COMP_LESS_XI
193270. BNX2_RPM_RC_CNTL_1_COMP_NEQUAL_XI
193271. BNX2_RPM_RC_CNTL_1_COMP_XI
193272. BNX2_RPM_RC_CNTL_1_DISCARD_XI
193273. BNX2_RPM_RC_CNTL_1_HDR_TYPE_DATA_XI
193274. BNX2_RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI
193275. BNX2_RPM_RC_CNTL_1_HDR_TYPE_IP_XI
193276. BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI
193277. BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI
193278. BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_XI
193279. BNX2_RPM_RC_CNTL_1_HDR_TYPE_UDP_XI
193280. BNX2_RPM_RC_CNTL_1_HDR_TYPE_XI
193281. BNX2_RPM_RC_CNTL_1_MAP_XI
193282. BNX2_RPM_RC_CNTL_1_MASK_XI
193283. BNX2_RPM_RC_CNTL_1_NBIT_XI
193284. BNX2_RPM_RC_CNTL_1_OFFSET_XI
193285. BNX2_RPM_RC_CNTL_1_P1_XI
193286. BNX2_RPM_RC_CNTL_1_P2_XI
193287. BNX2_RPM_RC_CNTL_1_P3_XI
193288. BNX2_RPM_RC_CNTL_1_P4_XI
193289. BNX2_RPM_RC_CNTL_1_PRIORITY_XI
193290. BNX2_RPM_RC_CNTL_1_SBIT_XI
193291. BNX2_RPM_RC_CNTL_2
193292. BNX2_RPM_RC_CNTL_2_A
193293. BNX2_RPM_RC_CNTL_2_B
193294. BNX2_RPM_RC_CNTL_2_CLASS_XI
193295. BNX2_RPM_RC_CNTL_2_CMDSEL_XI
193296. BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI
193297. BNX2_RPM_RC_CNTL_2_COMP_GREATER_XI
193298. BNX2_RPM_RC_CNTL_2_COMP_LESS_XI
193299. BNX2_RPM_RC_CNTL_2_COMP_NEQUAL_XI
193300. BNX2_RPM_RC_CNTL_2_COMP_XI
193301. BNX2_RPM_RC_CNTL_2_DISCARD_XI
193302. BNX2_RPM_RC_CNTL_2_HDR_TYPE_DATA_XI
193303. BNX2_RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI
193304. BNX2_RPM_RC_CNTL_2_HDR_TYPE_IP_XI
193305. BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI
193306. BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI
193307. BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_XI
193308. BNX2_RPM_RC_CNTL_2_HDR_TYPE_UDP_XI
193309. BNX2_RPM_RC_CNTL_2_HDR_TYPE_XI
193310. BNX2_RPM_RC_CNTL_2_MAP_XI
193311. BNX2_RPM_RC_CNTL_2_MASK_XI
193312. BNX2_RPM_RC_CNTL_2_NBIT_XI
193313. BNX2_RPM_RC_CNTL_2_OFFSET_XI
193314. BNX2_RPM_RC_CNTL_2_P1_XI
193315. BNX2_RPM_RC_CNTL_2_P2_XI
193316. BNX2_RPM_RC_CNTL_2_P3_XI
193317. BNX2_RPM_RC_CNTL_2_P4_XI
193318. BNX2_RPM_RC_CNTL_2_PRIORITY_XI
193319. BNX2_RPM_RC_CNTL_2_SBIT_XI
193320. BNX2_RPM_RC_CNTL_3
193321. BNX2_RPM_RC_CNTL_3_A
193322. BNX2_RPM_RC_CNTL_3_B
193323. BNX2_RPM_RC_CNTL_3_CLASS_XI
193324. BNX2_RPM_RC_CNTL_3_CMDSEL_XI
193325. BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI
193326. BNX2_RPM_RC_CNTL_3_COMP_GREATER_XI
193327. BNX2_RPM_RC_CNTL_3_COMP_LESS_XI
193328. BNX2_RPM_RC_CNTL_3_COMP_NEQUAL_XI
193329. BNX2_RPM_RC_CNTL_3_COMP_XI
193330. BNX2_RPM_RC_CNTL_3_DISCARD_XI
193331. BNX2_RPM_RC_CNTL_3_HDR_TYPE_DATA_XI
193332. BNX2_RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI
193333. BNX2_RPM_RC_CNTL_3_HDR_TYPE_IP_XI
193334. BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI
193335. BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI
193336. BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_XI
193337. BNX2_RPM_RC_CNTL_3_HDR_TYPE_UDP_XI
193338. BNX2_RPM_RC_CNTL_3_HDR_TYPE_XI
193339. BNX2_RPM_RC_CNTL_3_MAP_XI
193340. BNX2_RPM_RC_CNTL_3_MASK_XI
193341. BNX2_RPM_RC_CNTL_3_NBIT_XI
193342. BNX2_RPM_RC_CNTL_3_OFFSET_XI
193343. BNX2_RPM_RC_CNTL_3_P1_XI
193344. BNX2_RPM_RC_CNTL_3_P2_XI
193345. BNX2_RPM_RC_CNTL_3_P3_XI
193346. BNX2_RPM_RC_CNTL_3_P4_XI
193347. BNX2_RPM_RC_CNTL_3_PRIORITY_XI
193348. BNX2_RPM_RC_CNTL_3_SBIT_XI
193349. BNX2_RPM_RC_CNTL_4
193350. BNX2_RPM_RC_CNTL_4_A
193351. BNX2_RPM_RC_CNTL_4_B
193352. BNX2_RPM_RC_CNTL_4_CLASS_XI
193353. BNX2_RPM_RC_CNTL_4_CMDSEL_XI
193354. BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI
193355. BNX2_RPM_RC_CNTL_4_COMP_GREATER_XI
193356. BNX2_RPM_RC_CNTL_4_COMP_LESS_XI
193357. BNX2_RPM_RC_CNTL_4_COMP_NEQUAL_XI
193358. BNX2_RPM_RC_CNTL_4_COMP_XI
193359. BNX2_RPM_RC_CNTL_4_DISCARD_XI
193360. BNX2_RPM_RC_CNTL_4_HDR_TYPE_DATA_XI
193361. BNX2_RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI
193362. BNX2_RPM_RC_CNTL_4_HDR_TYPE_IP_XI
193363. BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI
193364. BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI
193365. BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_XI
193366. BNX2_RPM_RC_CNTL_4_HDR_TYPE_UDP_XI
193367. BNX2_RPM_RC_CNTL_4_HDR_TYPE_XI
193368. BNX2_RPM_RC_CNTL_4_MAP_XI
193369. BNX2_RPM_RC_CNTL_4_MASK_XI
193370. BNX2_RPM_RC_CNTL_4_NBIT_XI
193371. BNX2_RPM_RC_CNTL_4_OFFSET_XI
193372. BNX2_RPM_RC_CNTL_4_P1_XI
193373. BNX2_RPM_RC_CNTL_4_P2_XI
193374. BNX2_RPM_RC_CNTL_4_P3_XI
193375. BNX2_RPM_RC_CNTL_4_P4_XI
193376. BNX2_RPM_RC_CNTL_4_PRIORITY_XI
193377. BNX2_RPM_RC_CNTL_4_SBIT_XI
193378. BNX2_RPM_RC_CNTL_5
193379. BNX2_RPM_RC_CNTL_5_A
193380. BNX2_RPM_RC_CNTL_5_B
193381. BNX2_RPM_RC_CNTL_5_CLASS_XI
193382. BNX2_RPM_RC_CNTL_5_CMDSEL_XI
193383. BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI
193384. BNX2_RPM_RC_CNTL_5_COMP_GREATER_XI
193385. BNX2_RPM_RC_CNTL_5_COMP_LESS_XI
193386. BNX2_RPM_RC_CNTL_5_COMP_NEQUAL_XI
193387. BNX2_RPM_RC_CNTL_5_COMP_XI
193388. BNX2_RPM_RC_CNTL_5_DISCARD_XI
193389. BNX2_RPM_RC_CNTL_5_HDR_TYPE_DATA_XI
193390. BNX2_RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI
193391. BNX2_RPM_RC_CNTL_5_HDR_TYPE_IP_XI
193392. BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI
193393. BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI
193394. BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_XI
193395. BNX2_RPM_RC_CNTL_5_HDR_TYPE_UDP_XI
193396. BNX2_RPM_RC_CNTL_5_HDR_TYPE_XI
193397. BNX2_RPM_RC_CNTL_5_MAP_XI
193398. BNX2_RPM_RC_CNTL_5_MASK_XI
193399. BNX2_RPM_RC_CNTL_5_NBIT_XI
193400. BNX2_RPM_RC_CNTL_5_OFFSET_XI
193401. BNX2_RPM_RC_CNTL_5_P1_XI
193402. BNX2_RPM_RC_CNTL_5_P2_XI
193403. BNX2_RPM_RC_CNTL_5_P3_XI
193404. BNX2_RPM_RC_CNTL_5_P4_XI
193405. BNX2_RPM_RC_CNTL_5_PRIORITY_XI
193406. BNX2_RPM_RC_CNTL_5_SBIT_XI
193407. BNX2_RPM_RC_CNTL_6
193408. BNX2_RPM_RC_CNTL_6_A
193409. BNX2_RPM_RC_CNTL_6_B
193410. BNX2_RPM_RC_CNTL_6_CLASS_XI
193411. BNX2_RPM_RC_CNTL_6_CMDSEL_XI
193412. BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI
193413. BNX2_RPM_RC_CNTL_6_COMP_GREATER_XI
193414. BNX2_RPM_RC_CNTL_6_COMP_LESS_XI
193415. BNX2_RPM_RC_CNTL_6_COMP_NEQUAL_XI
193416. BNX2_RPM_RC_CNTL_6_COMP_XI
193417. BNX2_RPM_RC_CNTL_6_DISCARD_XI
193418. BNX2_RPM_RC_CNTL_6_HDR_TYPE_DATA_XI
193419. BNX2_RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI
193420. BNX2_RPM_RC_CNTL_6_HDR_TYPE_IP_XI
193421. BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI
193422. BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI
193423. BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_XI
193424. BNX2_RPM_RC_CNTL_6_HDR_TYPE_UDP_XI
193425. BNX2_RPM_RC_CNTL_6_HDR_TYPE_XI
193426. BNX2_RPM_RC_CNTL_6_MAP_XI
193427. BNX2_RPM_RC_CNTL_6_MASK_XI
193428. BNX2_RPM_RC_CNTL_6_NBIT_XI
193429. BNX2_RPM_RC_CNTL_6_OFFSET_XI
193430. BNX2_RPM_RC_CNTL_6_P1_XI
193431. BNX2_RPM_RC_CNTL_6_P2_XI
193432. BNX2_RPM_RC_CNTL_6_P3_XI
193433. BNX2_RPM_RC_CNTL_6_P4_XI
193434. BNX2_RPM_RC_CNTL_6_PRIORITY_XI
193435. BNX2_RPM_RC_CNTL_6_SBIT_XI
193436. BNX2_RPM_RC_CNTL_7
193437. BNX2_RPM_RC_CNTL_7_A
193438. BNX2_RPM_RC_CNTL_7_B
193439. BNX2_RPM_RC_CNTL_7_CLASS_XI
193440. BNX2_RPM_RC_CNTL_7_CMDSEL_XI
193441. BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI
193442. BNX2_RPM_RC_CNTL_7_COMP_GREATER_XI
193443. BNX2_RPM_RC_CNTL_7_COMP_LESS_XI
193444. BNX2_RPM_RC_CNTL_7_COMP_NEQUAL_XI
193445. BNX2_RPM_RC_CNTL_7_COMP_XI
193446. BNX2_RPM_RC_CNTL_7_DISCARD_XI
193447. BNX2_RPM_RC_CNTL_7_HDR_TYPE_DATA_XI
193448. BNX2_RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI
193449. BNX2_RPM_RC_CNTL_7_HDR_TYPE_IP_XI
193450. BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI
193451. BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI
193452. BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_XI
193453. BNX2_RPM_RC_CNTL_7_HDR_TYPE_UDP_XI
193454. BNX2_RPM_RC_CNTL_7_HDR_TYPE_XI
193455. BNX2_RPM_RC_CNTL_7_MAP_XI
193456. BNX2_RPM_RC_CNTL_7_MASK_XI
193457. BNX2_RPM_RC_CNTL_7_NBIT_XI
193458. BNX2_RPM_RC_CNTL_7_OFFSET_XI
193459. BNX2_RPM_RC_CNTL_7_P1_XI
193460. BNX2_RPM_RC_CNTL_7_P2_XI
193461. BNX2_RPM_RC_CNTL_7_P3_XI
193462. BNX2_RPM_RC_CNTL_7_P4_XI
193463. BNX2_RPM_RC_CNTL_7_PRIORITY_XI
193464. BNX2_RPM_RC_CNTL_7_SBIT_XI
193465. BNX2_RPM_RC_CNTL_8
193466. BNX2_RPM_RC_CNTL_8_A
193467. BNX2_RPM_RC_CNTL_8_B
193468. BNX2_RPM_RC_CNTL_8_CLASS_XI
193469. BNX2_RPM_RC_CNTL_8_CMDSEL_XI
193470. BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI
193471. BNX2_RPM_RC_CNTL_8_COMP_GREATER_XI
193472. BNX2_RPM_RC_CNTL_8_COMP_LESS_XI
193473. BNX2_RPM_RC_CNTL_8_COMP_NEQUAL_XI
193474. BNX2_RPM_RC_CNTL_8_COMP_XI
193475. BNX2_RPM_RC_CNTL_8_DISCARD_XI
193476. BNX2_RPM_RC_CNTL_8_HDR_TYPE_DATA_XI
193477. BNX2_RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI
193478. BNX2_RPM_RC_CNTL_8_HDR_TYPE_IP_XI
193479. BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI
193480. BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI
193481. BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_XI
193482. BNX2_RPM_RC_CNTL_8_HDR_TYPE_UDP_XI
193483. BNX2_RPM_RC_CNTL_8_HDR_TYPE_XI
193484. BNX2_RPM_RC_CNTL_8_MAP_XI
193485. BNX2_RPM_RC_CNTL_8_MASK_XI
193486. BNX2_RPM_RC_CNTL_8_NBIT_XI
193487. BNX2_RPM_RC_CNTL_8_OFFSET_XI
193488. BNX2_RPM_RC_CNTL_8_P1_XI
193489. BNX2_RPM_RC_CNTL_8_P2_XI
193490. BNX2_RPM_RC_CNTL_8_P3_XI
193491. BNX2_RPM_RC_CNTL_8_P4_XI
193492. BNX2_RPM_RC_CNTL_8_PRIORITY_XI
193493. BNX2_RPM_RC_CNTL_8_SBIT_XI
193494. BNX2_RPM_RC_CNTL_9
193495. BNX2_RPM_RC_CNTL_9_A
193496. BNX2_RPM_RC_CNTL_9_B
193497. BNX2_RPM_RC_CNTL_9_CLASS_XI
193498. BNX2_RPM_RC_CNTL_9_CMDSEL_XI
193499. BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI
193500. BNX2_RPM_RC_CNTL_9_COMP_GREATER_XI
193501. BNX2_RPM_RC_CNTL_9_COMP_LESS_XI
193502. BNX2_RPM_RC_CNTL_9_COMP_NEQUAL_XI
193503. BNX2_RPM_RC_CNTL_9_COMP_XI
193504. BNX2_RPM_RC_CNTL_9_DISCARD_XI
193505. BNX2_RPM_RC_CNTL_9_HDR_TYPE_DATA_XI
193506. BNX2_RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI
193507. BNX2_RPM_RC_CNTL_9_HDR_TYPE_IP_XI
193508. BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI
193509. BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI
193510. BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_XI
193511. BNX2_RPM_RC_CNTL_9_HDR_TYPE_UDP_XI
193512. BNX2_RPM_RC_CNTL_9_HDR_TYPE_XI
193513. BNX2_RPM_RC_CNTL_9_MAP_XI
193514. BNX2_RPM_RC_CNTL_9_MASK_XI
193515. BNX2_RPM_RC_CNTL_9_NBIT_XI
193516. BNX2_RPM_RC_CNTL_9_OFFSET_XI
193517. BNX2_RPM_RC_CNTL_9_P1_XI
193518. BNX2_RPM_RC_CNTL_9_P2_XI
193519. BNX2_RPM_RC_CNTL_9_P3_XI
193520. BNX2_RPM_RC_CNTL_9_P4_XI
193521. BNX2_RPM_RC_CNTL_9_PRIORITY_XI
193522. BNX2_RPM_RC_CNTL_9_SBIT_XI
193523. BNX2_RPM_RC_CONFIG
193524. BNX2_RPM_RC_CONFIG_DEF_CLASS
193525. BNX2_RPM_RC_CONFIG_KNUM_OVERWRITE
193526. BNX2_RPM_RC_CONFIG_RULE_ENABLE
193527. BNX2_RPM_RC_CONFIG_RULE_ENABLE_XI
193528. BNX2_RPM_RC_VALUE_MASK_0
193529. BNX2_RPM_RC_VALUE_MASK_0_MASK
193530. BNX2_RPM_RC_VALUE_MASK_0_VALUE
193531. BNX2_RPM_RC_VALUE_MASK_1
193532. BNX2_RPM_RC_VALUE_MASK_10
193533. BNX2_RPM_RC_VALUE_MASK_10_MASK
193534. BNX2_RPM_RC_VALUE_MASK_10_VALUE
193535. BNX2_RPM_RC_VALUE_MASK_11
193536. BNX2_RPM_RC_VALUE_MASK_11_MASK
193537. BNX2_RPM_RC_VALUE_MASK_11_VALUE
193538. BNX2_RPM_RC_VALUE_MASK_12
193539. BNX2_RPM_RC_VALUE_MASK_12_MASK
193540. BNX2_RPM_RC_VALUE_MASK_12_VALUE
193541. BNX2_RPM_RC_VALUE_MASK_13
193542. BNX2_RPM_RC_VALUE_MASK_13_MASK
193543. BNX2_RPM_RC_VALUE_MASK_13_VALUE
193544. BNX2_RPM_RC_VALUE_MASK_14
193545. BNX2_RPM_RC_VALUE_MASK_14_MASK
193546. BNX2_RPM_RC_VALUE_MASK_14_VALUE
193547. BNX2_RPM_RC_VALUE_MASK_15
193548. BNX2_RPM_RC_VALUE_MASK_15_MASK
193549. BNX2_RPM_RC_VALUE_MASK_15_VALUE
193550. BNX2_RPM_RC_VALUE_MASK_16
193551. BNX2_RPM_RC_VALUE_MASK_16_MASK
193552. BNX2_RPM_RC_VALUE_MASK_16_VALUE
193553. BNX2_RPM_RC_VALUE_MASK_17
193554. BNX2_RPM_RC_VALUE_MASK_17_MASK
193555. BNX2_RPM_RC_VALUE_MASK_17_VALUE
193556. BNX2_RPM_RC_VALUE_MASK_18
193557. BNX2_RPM_RC_VALUE_MASK_18_MASK
193558. BNX2_RPM_RC_VALUE_MASK_18_VALUE
193559. BNX2_RPM_RC_VALUE_MASK_19
193560. BNX2_RPM_RC_VALUE_MASK_19_MASK
193561. BNX2_RPM_RC_VALUE_MASK_19_VALUE
193562. BNX2_RPM_RC_VALUE_MASK_1_MASK
193563. BNX2_RPM_RC_VALUE_MASK_1_VALUE
193564. BNX2_RPM_RC_VALUE_MASK_2
193565. BNX2_RPM_RC_VALUE_MASK_2_MASK
193566. BNX2_RPM_RC_VALUE_MASK_2_VALUE
193567. BNX2_RPM_RC_VALUE_MASK_3
193568. BNX2_RPM_RC_VALUE_MASK_3_MASK
193569. BNX2_RPM_RC_VALUE_MASK_3_VALUE
193570. BNX2_RPM_RC_VALUE_MASK_4
193571. BNX2_RPM_RC_VALUE_MASK_4_MASK
193572. BNX2_RPM_RC_VALUE_MASK_4_VALUE
193573. BNX2_RPM_RC_VALUE_MASK_5
193574. BNX2_RPM_RC_VALUE_MASK_5_MASK
193575. BNX2_RPM_RC_VALUE_MASK_5_VALUE
193576. BNX2_RPM_RC_VALUE_MASK_6
193577. BNX2_RPM_RC_VALUE_MASK_6_MASK
193578. BNX2_RPM_RC_VALUE_MASK_6_VALUE
193579. BNX2_RPM_RC_VALUE_MASK_7
193580. BNX2_RPM_RC_VALUE_MASK_7_MASK
193581. BNX2_RPM_RC_VALUE_MASK_7_VALUE
193582. BNX2_RPM_RC_VALUE_MASK_8
193583. BNX2_RPM_RC_VALUE_MASK_8_MASK
193584. BNX2_RPM_RC_VALUE_MASK_8_VALUE
193585. BNX2_RPM_RC_VALUE_MASK_9
193586. BNX2_RPM_RC_VALUE_MASK_9_MASK
193587. BNX2_RPM_RC_VALUE_MASK_9_VALUE
193588. BNX2_RPM_SORT_USER0
193589. BNX2_RPM_SORT_USER0_BC_EN
193590. BNX2_RPM_SORT_USER0_ENA
193591. BNX2_RPM_SORT_USER0_MC_EN
193592. BNX2_RPM_SORT_USER0_MC_HSH_EN
193593. BNX2_RPM_SORT_USER0_PM_EN
193594. BNX2_RPM_SORT_USER0_PROM_EN
193595. BNX2_RPM_SORT_USER0_PROM_VLAN
193596. BNX2_RPM_SORT_USER0_VLAN_EN
193597. BNX2_RPM_SORT_USER0_VLAN_NOTMATCH
193598. BNX2_RPM_SORT_USER1
193599. BNX2_RPM_SORT_USER1_BC_EN
193600. BNX2_RPM_SORT_USER1_ENA
193601. BNX2_RPM_SORT_USER1_MC_EN
193602. BNX2_RPM_SORT_USER1_MC_HSH_EN
193603. BNX2_RPM_SORT_USER1_PM_EN
193604. BNX2_RPM_SORT_USER1_PROM_EN
193605. BNX2_RPM_SORT_USER1_PROM_VLAN
193606. BNX2_RPM_SORT_USER1_VLAN_EN
193607. BNX2_RPM_SORT_USER2
193608. BNX2_RPM_SORT_USER2_BC_EN
193609. BNX2_RPM_SORT_USER2_ENA
193610. BNX2_RPM_SORT_USER2_MC_EN
193611. BNX2_RPM_SORT_USER2_MC_HSH_EN
193612. BNX2_RPM_SORT_USER2_PM_EN
193613. BNX2_RPM_SORT_USER2_PROM_EN
193614. BNX2_RPM_SORT_USER2_PROM_VLAN
193615. BNX2_RPM_SORT_USER2_VLAN_EN
193616. BNX2_RPM_SORT_USER3
193617. BNX2_RPM_SORT_USER3_BC_EN
193618. BNX2_RPM_SORT_USER3_ENA
193619. BNX2_RPM_SORT_USER3_MC_EN
193620. BNX2_RPM_SORT_USER3_MC_HSH_EN
193621. BNX2_RPM_SORT_USER3_PM_EN
193622. BNX2_RPM_SORT_USER3_PROM_EN
193623. BNX2_RPM_SORT_USER3_PROM_VLAN
193624. BNX2_RPM_SORT_USER3_VLAN_EN
193625. BNX2_RPM_STATUS
193626. BNX2_RPM_STATUS_FREE_WAIT
193627. BNX2_RPM_STATUS_MBUF_WAIT
193628. BNX2_RPM_STAT_AC0
193629. BNX2_RPM_STAT_AC1
193630. BNX2_RPM_STAT_AC2
193631. BNX2_RPM_STAT_AC3
193632. BNX2_RPM_STAT_AC4
193633. BNX2_RPM_STAT_IFINFTQDISCARDS
193634. BNX2_RPM_STAT_IFINMBUFDISCARD
193635. BNX2_RPM_STAT_L2_FILTER_DISCARDS
193636. BNX2_RPM_STAT_RULE_CHECKER_DISCARDS
193637. BNX2_RPM_STAT_RULE_CHECKER_P4_HIT
193638. BNX2_RPM_VLAN_MATCH0
193639. BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE
193640. BNX2_RPM_VLAN_MATCH1
193641. BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE
193642. BNX2_RPM_VLAN_MATCH2
193643. BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE
193644. BNX2_RPM_VLAN_MATCH3
193645. BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE
193646. BNX2_RV2P_COMMAND
193647. BNX2_RV2P_COMMAND_ABORT0
193648. BNX2_RV2P_COMMAND_ABORT1
193649. BNX2_RV2P_COMMAND_ABORT2
193650. BNX2_RV2P_COMMAND_ABORT3
193651. BNX2_RV2P_COMMAND_ABORT4
193652. BNX2_RV2P_COMMAND_ABORT5
193653. BNX2_RV2P_COMMAND_CTXIF_RESET
193654. BNX2_RV2P_COMMAND_ENABLED
193655. BNX2_RV2P_COMMAND_PROC1_INTRPT
193656. BNX2_RV2P_COMMAND_PROC1_RESET
193657. BNX2_RV2P_COMMAND_PROC2_INTRPT
193658. BNX2_RV2P_COMMAND_PROC2_RESET
193659. BNX2_RV2P_CONFIG
193660. BNX2_RV2P_CONFIG_PAGE_SIZE
193661. BNX2_RV2P_CONFIG_PAGE_SIZE_128K
193662. BNX2_RV2P_CONFIG_PAGE_SIZE_16K
193663. BNX2_RV2P_CONFIG_PAGE_SIZE_1K
193664. BNX2_RV2P_CONFIG_PAGE_SIZE_1M
193665. BNX2_RV2P_CONFIG_PAGE_SIZE_256
193666. BNX2_RV2P_CONFIG_PAGE_SIZE_256K
193667. BNX2_RV2P_CONFIG_PAGE_SIZE_2K
193668. BNX2_RV2P_CONFIG_PAGE_SIZE_32K
193669. BNX2_RV2P_CONFIG_PAGE_SIZE_4K
193670. BNX2_RV2P_CONFIG_PAGE_SIZE_512
193671. BNX2_RV2P_CONFIG_PAGE_SIZE_512K
193672. BNX2_RV2P_CONFIG_PAGE_SIZE_64K
193673. BNX2_RV2P_CONFIG_PAGE_SIZE_8K
193674. BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0
193675. BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1
193676. BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2
193677. BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3
193678. BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4
193679. BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5
193680. BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0
193681. BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1
193682. BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2
193683. BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3
193684. BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4
193685. BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5
193686. BNX2_RV2P_CONFIG_STALL_PROC1
193687. BNX2_RV2P_CONFIG_STALL_PROC2
193688. BNX2_RV2P_DEBUG_VECT_PEEK
193689. BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN
193690. BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL
193691. BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE
193692. BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN
193693. BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL
193694. BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE
193695. BNX2_RV2P_GEN_BFR_ADDR_0
193696. BNX2_RV2P_GEN_BFR_ADDR_0_VALUE
193697. BNX2_RV2P_GEN_BFR_ADDR_1
193698. BNX2_RV2P_GEN_BFR_ADDR_1_VALUE
193699. BNX2_RV2P_GEN_BFR_ADDR_2
193700. BNX2_RV2P_GEN_BFR_ADDR_2_VALUE
193701. BNX2_RV2P_GEN_BFR_ADDR_3
193702. BNX2_RV2P_GEN_BFR_ADDR_3_VALUE
193703. BNX2_RV2P_GRC_PROC_DEBUG
193704. BNX2_RV2P_INSTR_HIGH
193705. BNX2_RV2P_INSTR_HIGH_HIGH
193706. BNX2_RV2P_INSTR_LOW
193707. BNX2_RV2P_INSTR_LOW_LOW
193708. BNX2_RV2P_MFTQ_CMD
193709. BNX2_RV2P_MFTQ_CMD_ADD_DATA
193710. BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN
193711. BNX2_RV2P_MFTQ_CMD_BUSY
193712. BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR
193713. BNX2_RV2P_MFTQ_CMD_OFFSET
193714. BNX2_RV2P_MFTQ_CMD_POP
193715. BNX2_RV2P_MFTQ_CMD_RD_DATA
193716. BNX2_RV2P_MFTQ_CMD_SFT_RESET
193717. BNX2_RV2P_MFTQ_CMD_WR_TOP
193718. BNX2_RV2P_MFTQ_CMD_WR_TOP_0
193719. BNX2_RV2P_MFTQ_CMD_WR_TOP_1
193720. BNX2_RV2P_MFTQ_CTL
193721. BNX2_RV2P_MFTQ_CTL_CUR_DEPTH
193722. BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE
193723. BNX2_RV2P_MFTQ_CTL_INTERVENE
193724. BNX2_RV2P_MFTQ_CTL_MAX_DEPTH
193725. BNX2_RV2P_MFTQ_CTL_OVERFLOW
193726. BNX2_RV2P_MPFE_PFE_CTL
193727. BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT
193728. BNX2_RV2P_MPFE_PFE_CTL_OFFSET
193729. BNX2_RV2P_MPFE_PFE_CTL_PFE_COUNT
193730. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE
193731. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0
193732. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_1
193733. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_10
193734. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_11
193735. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_12
193736. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_13
193737. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_14
193738. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_15
193739. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_2
193740. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_3
193741. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_4
193742. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_5
193743. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_6
193744. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_7
193745. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_8
193746. BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_9
193747. BNX2_RV2P_PFTQ_CMD
193748. BNX2_RV2P_PFTQ_CMD_ADD_DATA
193749. BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN
193750. BNX2_RV2P_PFTQ_CMD_BUSY
193751. BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR
193752. BNX2_RV2P_PFTQ_CMD_OFFSET
193753. BNX2_RV2P_PFTQ_CMD_POP
193754. BNX2_RV2P_PFTQ_CMD_RD_DATA
193755. BNX2_RV2P_PFTQ_CMD_SFT_RESET
193756. BNX2_RV2P_PFTQ_CMD_WR_TOP
193757. BNX2_RV2P_PFTQ_CMD_WR_TOP_0
193758. BNX2_RV2P_PFTQ_CMD_WR_TOP_1
193759. BNX2_RV2P_PFTQ_CTL
193760. BNX2_RV2P_PFTQ_CTL_CUR_DEPTH
193761. BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE
193762. BNX2_RV2P_PFTQ_CTL_INTERVENE
193763. BNX2_RV2P_PFTQ_CTL_MAX_DEPTH
193764. BNX2_RV2P_PFTQ_CTL_OVERFLOW
193765. BNX2_RV2P_PROC1_ADDR_CMD
193766. BNX2_RV2P_PROC1_ADDR_CMD_ADD
193767. BNX2_RV2P_PROC1_ADDR_CMD_RDWR
193768. BNX2_RV2P_PROC1_GRC_DEBUG
193769. BNX2_RV2P_PROC2_ADDR_CMD
193770. BNX2_RV2P_PROC2_ADDR_CMD_ADD
193771. BNX2_RV2P_PROC2_ADDR_CMD_RDWR
193772. BNX2_RV2P_PROC2_GRC_DEBUG
193773. BNX2_RV2P_RV2PMQ
193774. BNX2_RV2P_RV2PPQ
193775. BNX2_RV2P_RV2PTQ
193776. BNX2_RV2P_STATUS
193777. BNX2_RV2P_STATUS_ALWAYS_0
193778. BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT
193779. BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT
193780. BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT
193781. BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT
193782. BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT
193783. BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT
193784. BNX2_RV2P_TFTQ_CMD
193785. BNX2_RV2P_TFTQ_CMD_ADD_DATA
193786. BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN
193787. BNX2_RV2P_TFTQ_CMD_BUSY
193788. BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR
193789. BNX2_RV2P_TFTQ_CMD_OFFSET
193790. BNX2_RV2P_TFTQ_CMD_POP
193791. BNX2_RV2P_TFTQ_CMD_RD_DATA
193792. BNX2_RV2P_TFTQ_CMD_SFT_RESET
193793. BNX2_RV2P_TFTQ_CMD_WR_TOP
193794. BNX2_RV2P_TFTQ_CMD_WR_TOP_0
193795. BNX2_RV2P_TFTQ_CMD_WR_TOP_1
193796. BNX2_RV2P_TFTQ_CTL
193797. BNX2_RV2P_TFTQ_CTL_CUR_DEPTH
193798. BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE
193799. BNX2_RV2P_TFTQ_CTL_INTERVENE
193800. BNX2_RV2P_TFTQ_CTL_MAX_DEPTH
193801. BNX2_RV2P_TFTQ_CTL_OVERFLOW
193802. BNX2_RXP_CFTQ_CMD
193803. BNX2_RXP_CFTQ_CMD_ADD_DATA
193804. BNX2_RXP_CFTQ_CMD_ADD_INTERVEN
193805. BNX2_RXP_CFTQ_CMD_BUSY
193806. BNX2_RXP_CFTQ_CMD_INTERVENE_CLR
193807. BNX2_RXP_CFTQ_CMD_OFFSET
193808. BNX2_RXP_CFTQ_CMD_POP
193809. BNX2_RXP_CFTQ_CMD_RD_DATA
193810. BNX2_RXP_CFTQ_CMD_SFT_RESET
193811. BNX2_RXP_CFTQ_CMD_WR_TOP
193812. BNX2_RXP_CFTQ_CMD_WR_TOP_0
193813. BNX2_RXP_CFTQ_CMD_WR_TOP_1
193814. BNX2_RXP_CFTQ_CTL
193815. BNX2_RXP_CFTQ_CTL_CUR_DEPTH
193816. BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE
193817. BNX2_RXP_CFTQ_CTL_INTERVENE
193818. BNX2_RXP_CFTQ_CTL_MAX_DEPTH
193819. BNX2_RXP_CFTQ_CTL_OVERFLOW
193820. BNX2_RXP_CPU_DATA_ACCESS
193821. BNX2_RXP_CPU_DEBUG_VECT_PEEK
193822. BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN
193823. BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL
193824. BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE
193825. BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN
193826. BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL
193827. BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE
193828. BNX2_RXP_CPU_EVENT_MASK
193829. BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK
193830. BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK
193831. BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK
193832. BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK
193833. BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK
193834. BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK
193835. BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK
193836. BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK
193837. BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK
193838. BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK
193839. BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK
193840. BNX2_RXP_CPU_HW_BREAKPOINT
193841. BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS
193842. BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE
193843. BNX2_RXP_CPU_INSTRUCTION
193844. BNX2_RXP_CPU_INTERRUPT_ENABLE
193845. BNX2_RXP_CPU_INTERRUPT_SAVED_PC
193846. BNX2_RXP_CPU_INTERRUPT_VECTOR
193847. BNX2_RXP_CPU_LAST_BRANCH_ADDR
193848. BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA
193849. BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE
193850. BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH
193851. BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP
193852. BNX2_RXP_CPU_MODE
193853. BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA
193854. BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA
193855. BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA
193856. BNX2_RXP_CPU_MODE_INTERRUPT_ENA
193857. BNX2_RXP_CPU_MODE_LOCAL_RST
193858. BNX2_RXP_CPU_MODE_MSG_BIT1
193859. BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA
193860. BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA
193861. BNX2_RXP_CPU_MODE_SOFT_HALT
193862. BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA
193863. BNX2_RXP_CPU_MODE_STEP_ENA
193864. BNX2_RXP_CPU_PROGRAM_COUNTER
193865. BNX2_RXP_CPU_REG_FILE
193866. BNX2_RXP_CPU_STATE
193867. BNX2_RXP_CPU_STATE_ALIGN_HALTED
193868. BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED
193869. BNX2_RXP_CPU_STATE_BAD_INST_HALTED
193870. BNX2_RXP_CPU_STATE_BAD_PC_HALTED
193871. BNX2_RXP_CPU_STATE_BLOCKED_READ
193872. BNX2_RXP_CPU_STATE_BREAKPOINT
193873. BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL
193874. BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED
193875. BNX2_RXP_CPU_STATE_INST_FETCH_STALL
193876. BNX2_RXP_CPU_STATE_INTERRUPT
193877. BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED
193878. BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED
193879. BNX2_RXP_CPU_STATE_SOFT_HALTED
193880. BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW
193881. BNX2_RXP_FTQ_CMD
193882. BNX2_RXP_FTQ_CMD_ADD_DATA
193883. BNX2_RXP_FTQ_CMD_ADD_INTERVEN
193884. BNX2_RXP_FTQ_CMD_BUSY
193885. BNX2_RXP_FTQ_CMD_INTERVENE_CLR
193886. BNX2_RXP_FTQ_CMD_OFFSET
193887. BNX2_RXP_FTQ_CMD_POP
193888. BNX2_RXP_FTQ_CMD_RD_DATA
193889. BNX2_RXP_FTQ_CMD_SFT_RESET
193890. BNX2_RXP_FTQ_CMD_WR_TOP
193891. BNX2_RXP_FTQ_CMD_WR_TOP_0
193892. BNX2_RXP_FTQ_CMD_WR_TOP_1
193893. BNX2_RXP_FTQ_CTL
193894. BNX2_RXP_FTQ_CTL_CUR_DEPTH
193895. BNX2_RXP_FTQ_CTL_FORCE_INTERVENE
193896. BNX2_RXP_FTQ_CTL_INTERVENE
193897. BNX2_RXP_FTQ_CTL_MAX_DEPTH
193898. BNX2_RXP_FTQ_CTL_OVERFLOW
193899. BNX2_RXP_PFE_PFE_CTL
193900. BNX2_RXP_PFE_PFE_CTL_INC_USAGE_CNT
193901. BNX2_RXP_PFE_PFE_CTL_OFFSET
193902. BNX2_RXP_PFE_PFE_CTL_PFE_COUNT
193903. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE
193904. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_0
193905. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_1
193906. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_10
193907. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_11
193908. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_12
193909. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_13
193910. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_14
193911. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_15
193912. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_2
193913. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_3
193914. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_4
193915. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_5
193916. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_6
193917. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_7
193918. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_8
193919. BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_9
193920. BNX2_RXP_RXPCQ
193921. BNX2_RXP_RXPQ
193922. BNX2_RXP_SCRATCH
193923. BNX2_RXP_SCRATCH_RSS_TBL
193924. BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES
193925. BNX2_RXP_SCRATCH_RSS_TBL_SZ
193926. BNX2_RXP_SCRATCH_RXP_FLOOD
193927. BNX2_RX_ALIGN
193928. BNX2_RX_COPY_THRESH
193929. BNX2_RX_DESC_CNT
193930. BNX2_RX_IDX
193931. BNX2_RX_OFFSET
193932. BNX2_RX_PG_RING_IDX
193933. BNX2_RX_RING
193934. BNX2_RX_RING_IDX
193935. BNX2_SBLK_MSIX_ALIGN_SIZE
193936. BNX2_SERDES_AN_TIMEOUT
193937. BNX2_SERDES_FORCED_TIMEOUT
193938. BNX2_SHARED_FEATURE
193939. BNX2_SHARED_FEATURE_MASK
193940. BNX2_SHARED_HW_CFG
193941. BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK
193942. BNX2_SHARED_HW_CFG_CONFIG
193943. BNX2_SHARED_HW_CFG_CONFIG2
193944. BNX2_SHARED_HW_CFG_DESIGN_LOM
193945. BNX2_SHARED_HW_CFG_DESIGN_NIC
193946. BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX
193947. BNX2_SHARED_HW_CFG_LED_MODE_GPHY1
193948. BNX2_SHARED_HW_CFG_LED_MODE_GPHY2
193949. BNX2_SHARED_HW_CFG_LED_MODE_MAC
193950. BNX2_SHARED_HW_CFG_LED_MODE_MASK
193951. BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS
193952. BNX2_SHARED_HW_CFG_PART_NUM
193953. BNX2_SHARED_HW_CFG_PHY_2_5G
193954. BNX2_SHARED_HW_CFG_PHY_BACKPLANE
193955. BNX2_SHARED_HW_CFG_PHY_COPPER
193956. BNX2_SHARED_HW_CFG_PHY_FIBER
193957. BNX2_SHARED_HW_CFG_POWER_DISSIPATED
193958. BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK
193959. BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK
193960. BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK
193961. BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK
193962. BNX2_SHM_HDR_ADDR_0
193963. BNX2_SHM_HDR_ADDR_1
193964. BNX2_SHM_HDR_SIGNATURE
193965. BNX2_SHM_HDR_SIGNATURE_SIG
193966. BNX2_SHM_HDR_SIGNATURE_SIG_MASK
193967. BNX2_SHM_HDR_SIGNATURE_VER_MASK
193968. BNX2_SHM_HDR_SIGNATURE_VER_ONE
193969. BNX2_START_UNICAST_ADDRESS_INDEX
193970. BNX2_TBDC_BDIDX_BDIDX
193971. BNX2_TBDC_BDIDX_CMD
193972. BNX2_TBDC_BD_ADDR
193973. BNX2_TBDC_BIDX
193974. BNX2_TBDC_CAM_OPCODE
193975. BNX2_TBDC_CAM_OPCODE_CAM_VALIDS
193976. BNX2_TBDC_CAM_OPCODE_OPCODE
193977. BNX2_TBDC_CAM_OPCODE_OPCODE_CACHE_WRITE
193978. BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ
193979. BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_WRITE
193980. BNX2_TBDC_CAM_OPCODE_OPCODE_INVALIDATE
193981. BNX2_TBDC_CAM_OPCODE_OPCODE_RAM_READ
193982. BNX2_TBDC_CAM_OPCODE_OPCODE_RAM_WRITE
193983. BNX2_TBDC_CAM_OPCODE_OPCODE_SEARCH
193984. BNX2_TBDC_CAM_OPCODE_SMASK_BDIDX
193985. BNX2_TBDC_CAM_OPCODE_SMASK_CID
193986. BNX2_TBDC_CAM_OPCODE_SMASK_CMD
193987. BNX2_TBDC_CAM_OPCODE_WMT_FAILED
193988. BNX2_TBDC_CID
193989. BNX2_TBDC_COMMAND
193990. BNX2_TBDC_COMMAND_CMD_ENABLED
193991. BNX2_TBDC_COMMAND_CMD_FLUSH
193992. BNX2_TBDC_COMMAND_CMD_REG_ARB
193993. BNX2_TBDC_COMMAND_CMD_SOFT_RST
193994. BNX2_TBDC_COMMAND_WRCHK_ALL_ONES_ERROR
193995. BNX2_TBDC_COMMAND_WRCHK_ALL_ZEROS_ERROR
193996. BNX2_TBDC_COMMAND_WRCHK_ANY_ONES_ERROR
193997. BNX2_TBDC_COMMAND_WRCHK_ANY_ZEROS_ERROR
193998. BNX2_TBDC_COMMAND_WRCHK_RANGE_ERROR
193999. BNX2_TBDC_STATUS
194000. BNX2_TBDC_STATUS_FREE_CNT
194001. BNX2_TBDR_CKSUM_ERROR_STATUS
194002. BNX2_TBDR_CKSUM_ERROR_STATUS_CALCULATED
194003. BNX2_TBDR_CKSUM_ERROR_STATUS_EXPECTED
194004. BNX2_TBDR_COMMAND
194005. BNX2_TBDR_COMMAND_ENABLE
194006. BNX2_TBDR_COMMAND_MSTR_ABORT
194007. BNX2_TBDR_COMMAND_SOFT_RST
194008. BNX2_TBDR_CONFIG
194009. BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS
194010. BNX2_TBDR_CONFIG_MAX_BDS
194011. BNX2_TBDR_CONFIG_PAGE_SIZE
194012. BNX2_TBDR_CONFIG_PAGE_SIZE_128K
194013. BNX2_TBDR_CONFIG_PAGE_SIZE_16K
194014. BNX2_TBDR_CONFIG_PAGE_SIZE_1K
194015. BNX2_TBDR_CONFIG_PAGE_SIZE_1M
194016. BNX2_TBDR_CONFIG_PAGE_SIZE_256
194017. BNX2_TBDR_CONFIG_PAGE_SIZE_256K
194018. BNX2_TBDR_CONFIG_PAGE_SIZE_2K
194019. BNX2_TBDR_CONFIG_PAGE_SIZE_32K
194020. BNX2_TBDR_CONFIG_PAGE_SIZE_4K
194021. BNX2_TBDR_CONFIG_PAGE_SIZE_512
194022. BNX2_TBDR_CONFIG_PAGE_SIZE_512K
194023. BNX2_TBDR_CONFIG_PAGE_SIZE_64K
194024. BNX2_TBDR_CONFIG_PAGE_SIZE_8K
194025. BNX2_TBDR_CONFIG_PRIORITY
194026. BNX2_TBDR_CONFIG_SWAP_MODE
194027. BNX2_TBDR_DEBUG_VECT_PEEK
194028. BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN
194029. BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL
194030. BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE
194031. BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN
194032. BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL
194033. BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE
194034. BNX2_TBDR_FTQ_CMD
194035. BNX2_TBDR_FTQ_CMD_ADD_DATA
194036. BNX2_TBDR_FTQ_CMD_ADD_INTERVEN
194037. BNX2_TBDR_FTQ_CMD_BUSY
194038. BNX2_TBDR_FTQ_CMD_INTERVENE_CLR
194039. BNX2_TBDR_FTQ_CMD_OFFSET
194040. BNX2_TBDR_FTQ_CMD_POP
194041. BNX2_TBDR_FTQ_CMD_RD_DATA
194042. BNX2_TBDR_FTQ_CMD_SFT_RESET
194043. BNX2_TBDR_FTQ_CMD_WR_TOP
194044. BNX2_TBDR_FTQ_CMD_WR_TOP_0
194045. BNX2_TBDR_FTQ_CMD_WR_TOP_1
194046. BNX2_TBDR_FTQ_CTL
194047. BNX2_TBDR_FTQ_CTL_CUR_DEPTH
194048. BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE
194049. BNX2_TBDR_FTQ_CTL_INTERVENE
194050. BNX2_TBDR_FTQ_CTL_MAX_DEPTH
194051. BNX2_TBDR_FTQ_CTL_OVERFLOW
194052. BNX2_TBDR_STATUS
194053. BNX2_TBDR_STATUS_BURST_CNT
194054. BNX2_TBDR_STATUS_DMA_WAIT
194055. BNX2_TBDR_STATUS_FIFO_OVERFLOW
194056. BNX2_TBDR_STATUS_FIFO_UNDERFLOW
194057. BNX2_TBDR_STATUS_FTQ_ENTRY_CNT
194058. BNX2_TBDR_STATUS_FTQ_WAIT
194059. BNX2_TBDR_STATUS_SEARCHMISS_ERROR
194060. BNX2_TBDR_TBDRQ
194061. BNX2_TDMA_BD_IF_DEBUG
194062. BNX2_TDMA_COMMAND
194063. BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT
194064. BNX2_TDMA_COMMAND_CS16_ERR
194065. BNX2_TDMA_COMMAND_ENABLED
194066. BNX2_TDMA_COMMAND_FORCE_ILOCK_CKERR
194067. BNX2_TDMA_COMMAND_IFIFO_CLR
194068. BNX2_TDMA_COMMAND_MASK_CS1
194069. BNX2_TDMA_COMMAND_MASK_CS2
194070. BNX2_TDMA_COMMAND_MASK_CS3
194071. BNX2_TDMA_COMMAND_MASK_CS4
194072. BNX2_TDMA_COMMAND_MASTER_ABORT
194073. BNX2_TDMA_COMMAND_OFIFO_CLR
194074. BNX2_TDMA_CONFIG
194075. BNX2_TDMA_CONFIG_ALIGN_ENA
194076. BNX2_TDMA_CONFIG_BYTES_OST_1024_XI
194077. BNX2_TDMA_CONFIG_BYTES_OST_16384_XI
194078. BNX2_TDMA_CONFIG_BYTES_OST_2048_XI
194079. BNX2_TDMA_CONFIG_BYTES_OST_4096_XI
194080. BNX2_TDMA_CONFIG_BYTES_OST_512_XI
194081. BNX2_TDMA_CONFIG_BYTES_OST_8192_XI
194082. BNX2_TDMA_CONFIG_BYTES_OST_XI
194083. BNX2_TDMA_CONFIG_CHK_L2_BD
194084. BNX2_TDMA_CONFIG_CMPL_ENTRY
194085. BNX2_TDMA_CONFIG_FIFO_CMP
194086. BNX2_TDMA_CONFIG_FIFO_CMP_EN_XI
194087. BNX2_TDMA_CONFIG_HC_BYPASS_XI
194088. BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI
194089. BNX2_TDMA_CONFIG_IFIFO_DEPTH_16_XI
194090. BNX2_TDMA_CONFIG_IFIFO_DEPTH_32_XI
194091. BNX2_TDMA_CONFIG_IFIFO_DEPTH_4_XI
194092. BNX2_TDMA_CONFIG_IFIFO_DEPTH_64_XI
194093. BNX2_TDMA_CONFIG_IFIFO_DEPTH_8_XI
194094. BNX2_TDMA_CONFIG_IFIFO_DEPTH_XI
194095. BNX2_TDMA_CONFIG_LCL_MRRS_1024_XI
194096. BNX2_TDMA_CONFIG_LCL_MRRS_128_XI
194097. BNX2_TDMA_CONFIG_LCL_MRRS_2048_XI
194098. BNX2_TDMA_CONFIG_LCL_MRRS_256_XI
194099. BNX2_TDMA_CONFIG_LCL_MRRS_4096_XI
194100. BNX2_TDMA_CONFIG_LCL_MRRS_512_XI
194101. BNX2_TDMA_CONFIG_LCL_MRRS_EN_XI
194102. BNX2_TDMA_CONFIG_LCL_MRRS_XI
194103. BNX2_TDMA_CONFIG_LIMIT_SZ
194104. BNX2_TDMA_CONFIG_LIMIT_SZ_128
194105. BNX2_TDMA_CONFIG_LIMIT_SZ_256
194106. BNX2_TDMA_CONFIG_LIMIT_SZ_512
194107. BNX2_TDMA_CONFIG_LIMIT_SZ_64
194108. BNX2_TDMA_CONFIG_LINE_SZ
194109. BNX2_TDMA_CONFIG_LINE_SZ_128
194110. BNX2_TDMA_CONFIG_LINE_SZ_256
194111. BNX2_TDMA_CONFIG_LINE_SZ_512
194112. BNX2_TDMA_CONFIG_LINE_SZ_64
194113. BNX2_TDMA_CONFIG_NUM_DMA_CHAN
194114. BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0
194115. BNX2_TDMA_CONFIG_NUM_DMA_CHAN_1
194116. BNX2_TDMA_CONFIG_NUM_DMA_CHAN_2
194117. BNX2_TDMA_CONFIG_NUM_DMA_CHAN_3
194118. BNX2_TDMA_CONFIG_OFIFO_CMP
194119. BNX2_TDMA_CONFIG_OFIFO_CMP_2
194120. BNX2_TDMA_CONFIG_OFIFO_CMP_3
194121. BNX2_TDMA_CONFIG_ONE_DMA
194122. BNX2_TDMA_CONFIG_ONE_RECORD
194123. BNX2_TDMA_CTX_IF_DEBUG
194124. BNX2_TDMA_DBG_TRIGGER
194125. BNX2_TDMA_DBG_WATCHDOG
194126. BNX2_TDMA_DMAD_FSM
194127. BNX2_TDMA_DMAD_FSM_ARB_CTX
194128. BNX2_TDMA_DMAD_FSM_ARB_TBDC
194129. BNX2_TDMA_DMAD_FSM_BD
194130. BNX2_TDMA_DMAD_FSM_BD_INVLD
194131. BNX2_TDMA_DMAD_FSM_DMAD
194132. BNX2_TDMA_DMAD_FSM_DR_INTF
194133. BNX2_TDMA_DMAD_FSM_PUSH
194134. BNX2_TDMA_DMAD_IF_DEBUG
194135. BNX2_TDMA_DMAD_STATUS
194136. BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM
194137. BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY
194138. BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY
194139. BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY
194140. BNX2_TDMA_DR_IF_DEBUG
194141. BNX2_TDMA_DR_INTF_FSM
194142. BNX2_TDMA_DR_INTF_FSM_DMAD
194143. BNX2_TDMA_DR_INTF_FSM_DR_BUF
194144. BNX2_TDMA_DR_INTF_FSM_L2_COMP
194145. BNX2_TDMA_DR_INTF_FSM_TPATQ
194146. BNX2_TDMA_DR_INTF_FSM_TPBUF
194147. BNX2_TDMA_DR_INTF_STATUS
194148. BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT
194149. BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL
194150. BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE
194151. BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR
194152. BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR
194153. BNX2_TDMA_FTQ_CMD
194154. BNX2_TDMA_FTQ_CMD_ADD_DATA
194155. BNX2_TDMA_FTQ_CMD_ADD_INTERVEN
194156. BNX2_TDMA_FTQ_CMD_BUSY
194157. BNX2_TDMA_FTQ_CMD_INTERVENE_CLR
194158. BNX2_TDMA_FTQ_CMD_OFFSET
194159. BNX2_TDMA_FTQ_CMD_POP
194160. BNX2_TDMA_FTQ_CMD_RD_DATA
194161. BNX2_TDMA_FTQ_CMD_SFT_RESET
194162. BNX2_TDMA_FTQ_CMD_WR_TOP
194163. BNX2_TDMA_FTQ_CMD_WR_TOP_0
194164. BNX2_TDMA_FTQ_CMD_WR_TOP_1
194165. BNX2_TDMA_FTQ_CTL
194166. BNX2_TDMA_FTQ_CTL_CUR_DEPTH
194167. BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE
194168. BNX2_TDMA_FTQ_CTL_INTERVENE
194169. BNX2_TDMA_FTQ_CTL_MAX_DEPTH
194170. BNX2_TDMA_FTQ_CTL_OVERFLOW
194171. BNX2_TDMA_PAYLOAD_PROD
194172. BNX2_TDMA_PAYLOAD_PROD_VALUE
194173. BNX2_TDMA_PUSH_FSM
194174. BNX2_TDMA_STATUS
194175. BNX2_TDMA_STATUS_BURST_CNT
194176. BNX2_TDMA_STATUS_DMA_WAIT
194177. BNX2_TDMA_STATUS_FTQ_ENTRY_CNT
194178. BNX2_TDMA_STATUS_IFIFO_OVERFLOW
194179. BNX2_TDMA_STATUS_LOCK_WAIT
194180. BNX2_TDMA_STATUS_MAX_IFIFO_DEPTH
194181. BNX2_TDMA_STATUS_OFIFO_OVERFLOW
194182. BNX2_TDMA_STATUS_PATCH_FTQ_WAIT
194183. BNX2_TDMA_STATUS_PAYLOAD_WAIT
194184. BNX2_TDMA_TDMAQ
194185. BNX2_TDMA_TDMA_ILOCK_CKSUM
194186. BNX2_TDMA_TDMA_ILOCK_CKSUM_CALCULATED
194187. BNX2_TDMA_TDMA_ILOCK_CKSUM_EXPECTED
194188. BNX2_TDMA_TDMA_PCIE_CKSUM
194189. BNX2_TDMA_TDMA_PCIE_CKSUM_CALCULATED
194190. BNX2_TDMA_TDMA_PCIE_CKSUM_EXPECTED
194191. BNX2_TDMA_TPATQ_IF_DEBUG
194192. BNX2_TDMA_TPBUF_IF_DEBUG
194193. BNX2_TIMER_INTERVAL
194194. BNX2_TPAT_CPU_DATA_ACCESS
194195. BNX2_TPAT_CPU_DEBUG_VECT_PEEK
194196. BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN
194197. BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL
194198. BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE
194199. BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN
194200. BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL
194201. BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE
194202. BNX2_TPAT_CPU_EVENT_MASK
194203. BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK
194204. BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK
194205. BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK
194206. BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK
194207. BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK
194208. BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK
194209. BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK
194210. BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK
194211. BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK
194212. BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK
194213. BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK
194214. BNX2_TPAT_CPU_HW_BREAKPOINT
194215. BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS
194216. BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE
194217. BNX2_TPAT_CPU_INSTRUCTION
194218. BNX2_TPAT_CPU_INTERRUPT_ENABLE
194219. BNX2_TPAT_CPU_INTERRUPT_SAVED_PC
194220. BNX2_TPAT_CPU_INTERRUPT_VECTOR
194221. BNX2_TPAT_CPU_LAST_BRANCH_ADDR
194222. BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA
194223. BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE
194224. BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH
194225. BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP
194226. BNX2_TPAT_CPU_MODE
194227. BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA
194228. BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA
194229. BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA
194230. BNX2_TPAT_CPU_MODE_INTERRUPT_ENA
194231. BNX2_TPAT_CPU_MODE_LOCAL_RST
194232. BNX2_TPAT_CPU_MODE_MSG_BIT1
194233. BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA
194234. BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA
194235. BNX2_TPAT_CPU_MODE_SOFT_HALT
194236. BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA
194237. BNX2_TPAT_CPU_MODE_STEP_ENA
194238. BNX2_TPAT_CPU_PROGRAM_COUNTER
194239. BNX2_TPAT_CPU_REG_FILE
194240. BNX2_TPAT_CPU_STATE
194241. BNX2_TPAT_CPU_STATE_ALIGN_HALTED
194242. BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED
194243. BNX2_TPAT_CPU_STATE_BAD_INST_HALTED
194244. BNX2_TPAT_CPU_STATE_BAD_PC_HALTED
194245. BNX2_TPAT_CPU_STATE_BLOCKED_READ
194246. BNX2_TPAT_CPU_STATE_BREAKPOINT
194247. BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL
194248. BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED
194249. BNX2_TPAT_CPU_STATE_INST_FETCH_STALL
194250. BNX2_TPAT_CPU_STATE_INTERRUPT
194251. BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED
194252. BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED
194253. BNX2_TPAT_CPU_STATE_SOFT_HALTED
194254. BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW
194255. BNX2_TPAT_FTQ_CMD
194256. BNX2_TPAT_FTQ_CMD_ADD_DATA
194257. BNX2_TPAT_FTQ_CMD_ADD_INTERVEN
194258. BNX2_TPAT_FTQ_CMD_BUSY
194259. BNX2_TPAT_FTQ_CMD_INTERVENE_CLR
194260. BNX2_TPAT_FTQ_CMD_OFFSET
194261. BNX2_TPAT_FTQ_CMD_POP
194262. BNX2_TPAT_FTQ_CMD_RD_DATA
194263. BNX2_TPAT_FTQ_CMD_SFT_RESET
194264. BNX2_TPAT_FTQ_CMD_WR_TOP
194265. BNX2_TPAT_FTQ_CMD_WR_TOP_0
194266. BNX2_TPAT_FTQ_CMD_WR_TOP_1
194267. BNX2_TPAT_FTQ_CTL
194268. BNX2_TPAT_FTQ_CTL_CUR_DEPTH
194269. BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE
194270. BNX2_TPAT_FTQ_CTL_INTERVENE
194271. BNX2_TPAT_FTQ_CTL_MAX_DEPTH
194272. BNX2_TPAT_FTQ_CTL_OVERFLOW
194273. BNX2_TPAT_SCRATCH
194274. BNX2_TPAT_TPATQ
194275. BNX2_TSCH_TSS_CFG
194276. BNX2_TSCH_TSS_CFG_NUM_OF_TSS_CON
194277. BNX2_TSCH_TSS_CFG_TSS_START_CID
194278. BNX2_TXP_CPU_DATA_ACCESS
194279. BNX2_TXP_CPU_DEBUG_VECT_PEEK
194280. BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN
194281. BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL
194282. BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE
194283. BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN
194284. BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL
194285. BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE
194286. BNX2_TXP_CPU_EVENT_MASK
194287. BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK
194288. BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK
194289. BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK
194290. BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK
194291. BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK
194292. BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK
194293. BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK
194294. BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK
194295. BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK
194296. BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK
194297. BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK
194298. BNX2_TXP_CPU_HW_BREAKPOINT
194299. BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS
194300. BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE
194301. BNX2_TXP_CPU_INSTRUCTION
194302. BNX2_TXP_CPU_INTERRUPT_ENABLE
194303. BNX2_TXP_CPU_INTERRUPT_SAVED_PC
194304. BNX2_TXP_CPU_INTERRUPT_VECTOR
194305. BNX2_TXP_CPU_LAST_BRANCH_ADDR
194306. BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA
194307. BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE
194308. BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH
194309. BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP
194310. BNX2_TXP_CPU_MODE
194311. BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA
194312. BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA
194313. BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA
194314. BNX2_TXP_CPU_MODE_INTERRUPT_ENA
194315. BNX2_TXP_CPU_MODE_LOCAL_RST
194316. BNX2_TXP_CPU_MODE_MSG_BIT1
194317. BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA
194318. BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA
194319. BNX2_TXP_CPU_MODE_SOFT_HALT
194320. BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA
194321. BNX2_TXP_CPU_MODE_STEP_ENA
194322. BNX2_TXP_CPU_PROGRAM_COUNTER
194323. BNX2_TXP_CPU_REG_FILE
194324. BNX2_TXP_CPU_STATE
194325. BNX2_TXP_CPU_STATE_ALIGN_HALTED
194326. BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED
194327. BNX2_TXP_CPU_STATE_BAD_INST_HALTED
194328. BNX2_TXP_CPU_STATE_BAD_PC_HALTED
194329. BNX2_TXP_CPU_STATE_BLOCKED_READ
194330. BNX2_TXP_CPU_STATE_BREAKPOINT
194331. BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL
194332. BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED
194333. BNX2_TXP_CPU_STATE_INST_FETCH_STALL
194334. BNX2_TXP_CPU_STATE_INTERRUPT
194335. BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED
194336. BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED
194337. BNX2_TXP_CPU_STATE_SOFT_HALTED
194338. BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW
194339. BNX2_TXP_FTQ_CMD
194340. BNX2_TXP_FTQ_CMD_ADD_DATA
194341. BNX2_TXP_FTQ_CMD_ADD_INTERVEN
194342. BNX2_TXP_FTQ_CMD_BUSY
194343. BNX2_TXP_FTQ_CMD_INTERVENE_CLR
194344. BNX2_TXP_FTQ_CMD_OFFSET
194345. BNX2_TXP_FTQ_CMD_POP
194346. BNX2_TXP_FTQ_CMD_RD_DATA
194347. BNX2_TXP_FTQ_CMD_SFT_RESET
194348. BNX2_TXP_FTQ_CMD_WR_TOP
194349. BNX2_TXP_FTQ_CMD_WR_TOP_0
194350. BNX2_TXP_FTQ_CMD_WR_TOP_1
194351. BNX2_TXP_FTQ_CTL
194352. BNX2_TXP_FTQ_CTL_CUR_DEPTH
194353. BNX2_TXP_FTQ_CTL_FORCE_INTERVENE
194354. BNX2_TXP_FTQ_CTL_INTERVENE
194355. BNX2_TXP_FTQ_CTL_MAX_DEPTH
194356. BNX2_TXP_FTQ_CTL_OVERFLOW
194357. BNX2_TXP_SCRATCH
194358. BNX2_TXP_TXPQ
194359. BNX2_TX_DESC_CNT
194360. BNX2_TX_RING_IDX
194361. BNX2_VPD_LEN
194362. BNX2_VPD_NVRAM_OFFSET
194363. BNX2_WR
194364. BNX2_WR16
194365. BNXT_AGG_EVENT
194366. BNXT_AGG_IDX_BMAP_SIZE
194367. BNXT_AUTONEG_FLOW_CTRL
194368. BNXT_AUTONEG_SPEED
194369. BNXT_AUTO_MODE
194370. BNXT_CAG_REG_BASE
194371. BNXT_CAG_REG_LEGACY_INT_STATUS
194372. BNXT_CHIP_NUM_5730X
194373. BNXT_CHIP_NUM_5731X
194374. BNXT_CHIP_NUM_5740X
194375. BNXT_CHIP_NUM_5741X
194376. BNXT_CHIP_NUM_5745X
194377. BNXT_CHIP_NUM_57X0X
194378. BNXT_CHIP_NUM_57X1X
194379. BNXT_CHIP_NUM_58700
194380. BNXT_CHIP_NUM_588XX
194381. BNXT_CHIP_P4
194382. BNXT_CHIP_P4_PLUS
194383. BNXT_CHIP_P5
194384. BNXT_CHIP_TYPE_NITRO_A0
194385. BNXT_CNPQ
194386. BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE
194387. BNXT_COAL_CMPL_ENABLES
194388. BNXT_COAL_CMPL_MIN_TMR_ENABLE
194389. BNXT_COREDUMP_BUF_LEN
194390. BNXT_COREDUMP_H
194391. BNXT_CP_DB_IRQ_DIS
194392. BNXT_CTX_FLAG_INITED
194393. BNXT_DB_CQ
194394. BNXT_DB_CQ_ARM
194395. BNXT_DB_NQ_ARM_P5
194396. BNXT_DB_NQ_P5
194397. BNXT_DCB_H
194398. BNXT_DEFAULT_RX_RING_SIZE
194399. BNXT_DEFAULT_TX_RING_SIZE
194400. BNXT_DEF_STATS_COAL_TICKS
194401. BNXT_DEVLINK_H
194402. BNXT_DEVLINK_PARAM_ID_BASE
194403. BNXT_DEVLINK_PARAM_ID_GRE_VER_CHECK
194404. BNXT_DEV_STATE_CLOSING
194405. BNXT_DFLT_FW_RST_MAX_DSECS
194406. BNXT_DFLT_FW_RST_MIN_DSECS
194407. BNXT_DIR_RX
194408. BNXT_DIR_TX
194409. BNXT_DRV_TESTS
194410. BNXT_EN_FLAG_MSIX_REQUESTED
194411. BNXT_EN_FLAG_ROCEV1_CAP
194412. BNXT_EN_FLAG_ROCEV2_CAP
194413. BNXT_EN_FLAG_ROCE_CAP
194414. BNXT_ETHTOOL_H
194415. BNXT_ETHTOOL_TO_FW_SPDS
194416. BNXT_EXEC_FWD_RESP_SIZE_ERR
194417. BNXT_EXTLPBK_TEST_IDX
194418. BNXT_FEC_AUTONEG
194419. BNXT_FEC_ENC_BASE_R
194420. BNXT_FEC_ENC_RS
194421. BNXT_FID_INVALID
194422. BNXT_FIRMWARE_BIN_SIGNATURE
194423. BNXT_FIRST_PF_FID
194424. BNXT_FIRST_VF_FID
194425. BNXT_FLAG_AGG_RINGS
194426. BNXT_FLAG_ALL_CONFIG_FEATS
194427. BNXT_FLAG_CHIP_NITRO_A0
194428. BNXT_FLAG_CHIP_P5
194429. BNXT_FLAG_DIM
194430. BNXT_FLAG_DOUBLE_DB
194431. BNXT_FLAG_DSN_VALID
194432. BNXT_FLAG_EEE_CAP
194433. BNXT_FLAG_GRO
194434. BNXT_FLAG_JUMBO
194435. BNXT_FLAG_LRO
194436. BNXT_FLAG_MSIX_CAP
194437. BNXT_FLAG_MULTI_HOST
194438. BNXT_FLAG_NEW_RSS_CAP
194439. BNXT_FLAG_NO_AGG_RINGS
194440. BNXT_FLAG_PCIE_STATS
194441. BNXT_FLAG_PORT_STATS
194442. BNXT_FLAG_PORT_STATS_EXT
194443. BNXT_FLAG_RFS
194444. BNXT_FLAG_ROCEV1_CAP
194445. BNXT_FLAG_ROCEV2_CAP
194446. BNXT_FLAG_ROCE_CAP
194447. BNXT_FLAG_ROCE_MIRROR_CAP
194448. BNXT_FLAG_RX_PAGE_MODE
194449. BNXT_FLAG_SHARED_RINGS
194450. BNXT_FLAG_STRIP_VLAN
194451. BNXT_FLAG_TPA
194452. BNXT_FLAG_UDP_RSS_CAP
194453. BNXT_FLAG_USING_MSIX
194454. BNXT_FLAG_VF
194455. BNXT_FLAG_WOL_CAP
194456. BNXT_FLOW_STATS_BATCH_MAX
194457. BNXT_FLOW_STATS_SP_EVENT
194458. BNXT_FLTR_UPDATE
194459. BNXT_FLTR_VALID
194460. BNXT_FWD_RESP_SIZE_ERR
194461. BNXT_FW_CAP_CFA_ADV_FLOW
194462. BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX
194463. BNXT_FW_CAP_DCBX_AGENT
194464. BNXT_FW_CAP_ERROR_RECOVERY
194465. BNXT_FW_CAP_ERR_RECOVER_RELOAD
194466. BNXT_FW_CAP_EXT_STATS_SUPPORTED
194467. BNXT_FW_CAP_HOT_RESET
194468. BNXT_FW_CAP_IF_CHANGE
194469. BNXT_FW_CAP_KONG_MB_CHNL
194470. BNXT_FW_CAP_LLDP_AGENT
194471. BNXT_FW_CAP_NEW_RM
194472. BNXT_FW_CAP_OVS_64BIT_HANDLE
194473. BNXT_FW_CAP_PCIE_STATS_SUPPORTED
194474. BNXT_FW_CAP_PKG_VER
194475. BNXT_FW_CAP_SHORT_CMD
194476. BNXT_FW_CAP_TRUSTED_VF
194477. BNXT_FW_EXCEPTION_SP_EVENT
194478. BNXT_FW_HEALTH_REG
194479. BNXT_FW_HEALTH_REG_OFF
194480. BNXT_FW_HEALTH_REG_TYPE
194481. BNXT_FW_HEALTH_REG_TYPE_BAR0
194482. BNXT_FW_HEALTH_REG_TYPE_BAR1
194483. BNXT_FW_HEALTH_REG_TYPE_CFG
194484. BNXT_FW_HEALTH_REG_TYPE_GRC
194485. BNXT_FW_HEALTH_REG_TYPE_MASK
194486. BNXT_FW_HEALTH_WIN_BASE
194487. BNXT_FW_HEALTH_WIN_MAP_OFF
194488. BNXT_FW_HEARTBEAT_REG
194489. BNXT_FW_RESET_AP
194490. BNXT_FW_RESET_CHIP
194491. BNXT_FW_RESET_CNT_REG
194492. BNXT_FW_RESET_INPROG_REG
194493. BNXT_FW_RESET_NOTIFY_SP_EVENT
194494. BNXT_FW_RESET_STATE_ENABLE_DEV
194495. BNXT_FW_RESET_STATE_OPENING
194496. BNXT_FW_RESET_STATE_POLL_FW
194497. BNXT_FW_RESET_STATE_POLL_FW_DOWN
194498. BNXT_FW_RESET_STATE_POLL_VF
194499. BNXT_FW_RESET_STATE_RESET_FW
194500. BNXT_FW_STATUS_HEALTHY
194501. BNXT_FW_STATUS_SHUTDOWN
194502. BNXT_FW_TO_ETHTOOL_SPDS
194503. BNXT_GENEVE_ADD_PORT_SP_EVENT
194504. BNXT_GENEVE_DEL_PORT_SP_EVENT
194505. BNXT_GET_EVENT_PORT
194506. BNXT_GRCPF_REG_CHIMP_COMM
194507. BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER
194508. BNXT_GRCPF_REG_KONG_COMM
194509. BNXT_GRCPF_REG_KONG_COMM_TRIGGER
194510. BNXT_GRCPF_REG_WINDOW_BASE_OUT
194511. BNXT_GRC_BASE_MASK
194512. BNXT_GRC_OFFSET_MASK
194513. BNXT_H
194514. BNXT_HWRM_CHNL_CHIMP
194515. BNXT_HWRM_CHNL_KONG
194516. BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
194517. BNXT_HWRM_MAX_REQ_LEN
194518. BNXT_HWRM_PF_UNLOAD_SP_EVENT
194519. BNXT_HWRM_PORT_MODULE_SP_EVENT
194520. BNXT_HWRM_REQS_PER_PAGE
194521. BNXT_HWRM_REQ_MAX_SIZE
194522. BNXT_HWRM_SHORT_REQ_LEN
194523. BNXT_IPV4_HDR_SIZE
194524. BNXT_IPV6_HDR_SIZE
194525. BNXT_IRQ_TEST_IDX
194526. BNXT_LED_ALT_BLINK_CAP
194527. BNXT_LED_DFLT_ENA
194528. BNXT_LED_DFLT_ENABLES
194529. BNXT_LED_DFLT_ENA_SHIFT
194530. BNXT_LEGACY_COAL_CMPL_PARAMS
194531. BNXT_LINK_AUTO_ALLSPDS
194532. BNXT_LINK_AUTO_MSK
194533. BNXT_LINK_AUTO_NONE
194534. BNXT_LINK_AUTO_ONEORBELOW
194535. BNXT_LINK_AUTO_ONESPD
194536. BNXT_LINK_CHNG_SP_EVENT
194537. BNXT_LINK_DUPLEX_FULL
194538. BNXT_LINK_DUPLEX_HALF
194539. BNXT_LINK_LINK
194540. BNXT_LINK_NO_LINK
194541. BNXT_LINK_PAUSE_BOTH
194542. BNXT_LINK_PAUSE_RX
194543. BNXT_LINK_PAUSE_TX
194544. BNXT_LINK_SIGNAL
194545. BNXT_LINK_SPEED_100GB
194546. BNXT_LINK_SPEED_100MB
194547. BNXT_LINK_SPEED_10GB
194548. BNXT_LINK_SPEED_1GB
194549. BNXT_LINK_SPEED_20GB
194550. BNXT_LINK_SPEED_25GB
194551. BNXT_LINK_SPEED_2GB
194552. BNXT_LINK_SPEED_2_5GB
194553. BNXT_LINK_SPEED_40GB
194554. BNXT_LINK_SPEED_50GB
194555. BNXT_LINK_SPEED_CHNG_SP_EVENT
194556. BNXT_LINK_SPEED_MSK_100GB
194557. BNXT_LINK_SPEED_MSK_100MB
194558. BNXT_LINK_SPEED_MSK_10GB
194559. BNXT_LINK_SPEED_MSK_1GB
194560. BNXT_LINK_SPEED_MSK_20GB
194561. BNXT_LINK_SPEED_MSK_25GB
194562. BNXT_LINK_SPEED_MSK_2GB
194563. BNXT_LINK_SPEED_MSK_2_5GB
194564. BNXT_LINK_SPEED_MSK_40GB
194565. BNXT_LINK_SPEED_MSK_50GB
194566. BNXT_LLQ
194567. BNXT_MACLPBK_TEST_IDX
194568. BNXT_MAX_CTX_PER_VNIC
194569. BNXT_MAX_LED
194570. BNXT_MAX_MC_ADDRS
194571. BNXT_MAX_MTU
194572. BNXT_MAX_PAGE_MODE_MTU
194573. BNXT_MAX_PHY_I2C_RESP_SIZE
194574. BNXT_MAX_QUEUE
194575. BNXT_MAX_RX_DESC_CNT
194576. BNXT_MAX_RX_JUM_DESC_CNT
194577. BNXT_MAX_STATS_COAL_TICKS
194578. BNXT_MAX_TEST
194579. BNXT_MAX_TX_DESC_CNT
194580. BNXT_MAX_UC_ADDRS
194581. BNXT_MAX_ULP
194582. BNXT_MH
194583. BNXT_MIN_PKT_SIZE
194584. BNXT_MIN_ROCE_CP_RINGS
194585. BNXT_MIN_ROCE_STAT_CTXS
194586. BNXT_MIN_STATS_COAL_TICKS
194587. BNXT_MSIX_VEC_MAX
194588. BNXT_MSIX_VEC_MIN_MAX
194589. BNXT_NAPI_FLAG_XDP
194590. BNXT_NEW_RM
194591. BNXT_NPAR
194592. BNXT_NTP_FLTR_FLAGS
194593. BNXT_NTP_FLTR_HASH_MASK
194594. BNXT_NTP_FLTR_HASH_SIZE
194595. BNXT_NTP_FLTR_MAX_FLTR
194596. BNXT_NTP_TUNNEL_FLTR_FLAG
194597. BNXT_NUM_PCIE_STATS
194598. BNXT_NUM_PORT_STATS
194599. BNXT_NUM_STATS_PRI
194600. BNXT_NUM_SW_FUNC_STATS
194601. BNXT_NVM_FUNC_CFG
194602. BNXT_NVM_PORT_CFG
194603. BNXT_NVM_SHARED_CFG
194604. BNXT_OTHER_ULP
194605. BNXT_PAGE_SHIFT
194606. BNXT_PAGE_SIZE
194607. BNXT_PCIE_STATS_ENTRY
194608. BNXT_PCIE_STATS_OFFSET
194609. BNXT_PERIODIC_STATS_SP_EVENT
194610. BNXT_PF
194611. BNXT_PHYLPBK_TEST_IDX
194612. BNXT_PM_OPS
194613. BNXT_QPLIB_ACCESS_LOCAL_WRITE
194614. BNXT_QPLIB_ACCESS_MW_BIND
194615. BNXT_QPLIB_ACCESS_ON_DEMAND
194616. BNXT_QPLIB_ACCESS_REMOTE_ATOMIC
194617. BNXT_QPLIB_ACCESS_REMOTE_READ
194618. BNXT_QPLIB_ACCESS_REMOTE_WRITE
194619. BNXT_QPLIB_ACCESS_ZERO_BASED
194620. BNXT_QPLIB_BIND_SWQE_ACCESS_LOCAL_WRITE
194621. BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_ATOMIC
194622. BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_READ
194623. BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_WRITE
194624. BNXT_QPLIB_BIND_SWQE_ACCESS_WINDOW_BIND
194625. BNXT_QPLIB_CMDQE_BYTES
194626. BNXT_QPLIB_CMDQE_MAX_CNT_256
194627. BNXT_QPLIB_CMDQE_MAX_CNT_8192
194628. BNXT_QPLIB_CMDQE_UNITS
194629. BNXT_QPLIB_CREQE_CNT_PER_PG
194630. BNXT_QPLIB_CREQE_MAX_CNT
194631. BNXT_QPLIB_CREQE_PER_PG
194632. BNXT_QPLIB_CREQE_UNITS
194633. BNXT_QPLIB_FENCE_WRID
194634. BNXT_QPLIB_FR_PMR
194635. BNXT_QPLIB_MAX_CQE_ENTRY_SIZE
194636. BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE
194637. BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4
194638. BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6
194639. BNXT_QPLIB_MAX_IRRQE_ENTRY_SIZE
194640. BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE
194641. BNXT_QPLIB_MAX_NQE_ENTRY_SIZE
194642. BNXT_QPLIB_MAX_ORRQE_ENTRY_SIZE
194643. BNXT_QPLIB_MAX_OUT_RD_ATOM
194644. BNXT_QPLIB_MAX_PSNE_ENTRY_SIZE
194645. BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE
194646. BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
194647. BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2
194648. BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2
194649. BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE
194650. BNXT_QPLIB_MAX_RQE_ENTRY_SIZE
194651. BNXT_QPLIB_MAX_SQE_ENTRY_SIZE
194652. BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE
194653. BNXT_QPLIB_NQE_MAX_CNT
194654. BNXT_QPLIB_OOS_COUNT_MASK
194655. BNXT_QPLIB_QP_ID_INVALID
194656. BNXT_QPLIB_QP_MAX_SGL
194657. BNXT_QPLIB_QUEUE_START_PERIOD
194658. BNXT_QPLIB_RESERVED_QP_WRS
194659. BNXT_QPLIB_RSVD_LKEY
194660. BNXT_QPLIB_SWQE_FLAGS_INLINE
194661. BNXT_QPLIB_SWQE_FLAGS_RD_ATOMIC_FENCE
194662. BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP
194663. BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT
194664. BNXT_QPLIB_SWQE_FLAGS_UC_FENCE
194665. BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH
194666. BNXT_QPLIB_SWQE_PAGE_SIZE_1G
194667. BNXT_QPLIB_SWQE_PAGE_SIZE_1M
194668. BNXT_QPLIB_SWQE_PAGE_SIZE_256K
194669. BNXT_QPLIB_SWQE_PAGE_SIZE_2M
194670. BNXT_QPLIB_SWQE_PAGE_SIZE_4K
194671. BNXT_QPLIB_SWQE_PAGE_SIZE_4M
194672. BNXT_QPLIB_SWQE_PAGE_SIZE_64K
194673. BNXT_QPLIB_SWQE_PAGE_SIZE_8K
194674. BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP
194675. BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD
194676. BNXT_QPLIB_SWQE_TYPE_BIND_MW
194677. BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR
194678. BNXT_QPLIB_SWQE_TYPE_LOCAL_INV
194679. BNXT_QPLIB_SWQE_TYPE_RDMA_READ
194680. BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE
194681. BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM
194682. BNXT_QPLIB_SWQE_TYPE_RECV
194683. BNXT_QPLIB_SWQE_TYPE_RECV_RDMA_IMM
194684. BNXT_QPLIB_SWQE_TYPE_REG_MR
194685. BNXT_QPLIB_SWQE_TYPE_SEND
194686. BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM
194687. BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV
194688. BNXT_REDIRECT_EVENT
194689. BNXT_REJ_FWD_RESP_SIZE_ERR
194690. BNXT_RESET_TASK_SILENT_SP_EVENT
194691. BNXT_RESET_TASK_SP_EVENT
194692. BNXT_RE_ABI_VERSION
194693. BNXT_RE_ACTIVE_CQ
194694. BNXT_RE_ACTIVE_MR
194695. BNXT_RE_ACTIVE_MW
194696. BNXT_RE_ACTIVE_QP
194697. BNXT_RE_ACTIVE_SRQ
194698. BNXT_RE_AEQ_IDX
194699. BNXT_RE_AVID_OFFT
194700. BNXT_RE_AVID_SIZE
194701. BNXT_RE_BAD_RESP_ERR
194702. BNXT_RE_BEG_RESV_OFFT
194703. BNXT_RE_CHIP_ID0_CHIP_MET_SFT
194704. BNXT_RE_CHIP_ID0_CHIP_NUM_SFT
194705. BNXT_RE_CHIP_ID0_CHIP_REV_SFT
194706. BNXT_RE_DEFAULT_ACK_DELAY
194707. BNXT_RE_DESC
194708. BNXT_RE_DUP_REQ
194709. BNXT_RE_END_RESV_OFFT
194710. BNXT_RE_FENCE_BYTES
194711. BNXT_RE_FENCE_PBL_SIZE
194712. BNXT_RE_FLAG_GOT_MSIX
194713. BNXT_RE_FLAG_HAVE_L2_REF
194714. BNXT_RE_FLAG_IBDEV_REGISTERED
194715. BNXT_RE_FLAG_ISSUE_ROCE_STATS
194716. BNXT_RE_FLAG_NETDEV_REGISTERED
194717. BNXT_RE_FLAG_QOS_WORK_REG
194718. BNXT_RE_FLAG_RCFW_CHANNEL_EN
194719. BNXT_RE_FLAG_RESOURCES_ALLOCATED
194720. BNXT_RE_FLAG_RESOURCES_INITIALIZED
194721. BNXT_RE_LOCAL_PROTECTION_ERR
194722. BNXT_RE_LOCAL_QP_OP_ERR
194723. BNXT_RE_MAX_CQ_COUNT
194724. BNXT_RE_MAX_GID_PER_VF
194725. BNXT_RE_MAX_MRW_COUNT
194726. BNXT_RE_MAX_MRW_COUNT_256K
194727. BNXT_RE_MAX_MRW_COUNT_64K
194728. BNXT_RE_MAX_MR_SIZE
194729. BNXT_RE_MAX_MR_SIZE_HIGH
194730. BNXT_RE_MAX_MR_SIZE_LOW
194731. BNXT_RE_MAX_MSIX
194732. BNXT_RE_MAX_QPC_COUNT
194733. BNXT_RE_MAX_RETRY_EXCEEDED
194734. BNXT_RE_MAX_SRQC_COUNT
194735. BNXT_RE_MEM_MGMT_OP_ERR
194736. BNXT_RE_MIN_MSIX
194737. BNXT_RE_MISSING_RESP
194738. BNXT_RE_NQ_IDX
194739. BNXT_RE_NUM_COUNTERS
194740. BNXT_RE_OUT_OF_SEQ_ERR
194741. BNXT_RE_PAGE_SHIFT_1G
194742. BNXT_RE_PAGE_SHIFT_2M
194743. BNXT_RE_PAGE_SHIFT_4K
194744. BNXT_RE_PAGE_SHIFT_64K
194745. BNXT_RE_PAGE_SHIFT_8K
194746. BNXT_RE_PAGE_SHIFT_8M
194747. BNXT_RE_PAGE_SIZE_1G
194748. BNXT_RE_PAGE_SIZE_2M
194749. BNXT_RE_PAGE_SIZE_4K
194750. BNXT_RE_PAGE_SIZE_64K
194751. BNXT_RE_PAGE_SIZE_8K
194752. BNXT_RE_PAGE_SIZE_8M
194753. BNXT_RE_PCT_RSVD_FOR_PF
194754. BNXT_RE_RECOVERABLE_ERRORS
194755. BNXT_RE_REMOTE_ACCESS_ERR
194756. BNXT_RE_REMOTE_INVALID_REQ_ERR
194757. BNXT_RE_REMOTE_OP_ERR
194758. BNXT_RE_RESVD_MR_FOR_PF
194759. BNXT_RE_RES_CMP_ERR
194760. BNXT_RE_RES_CQ_LOAD_ERR
194761. BNXT_RE_RES_EXCEEDS_WQE
194762. BNXT_RE_RES_EXCEED_MAX
194763. BNXT_RE_RES_INVALID_DUP_RKEY
194764. BNXT_RE_RES_IRRQ_OFLOW
194765. BNXT_RE_RES_LENGTH_MISMATCH
194766. BNXT_RE_RES_MEM_ERROR
194767. BNXT_RE_RES_OPCODE_ERR
194768. BNXT_RE_RES_REM_INV_ERR
194769. BNXT_RE_RES_RX_DOMAIN_ERR
194770. BNXT_RE_RES_RX_INVALID_RKEY
194771. BNXT_RE_RES_RX_NO_PERM
194772. BNXT_RE_RES_RX_PCI_ERR
194773. BNXT_RE_RES_RX_RANGE_ERR
194774. BNXT_RE_RES_SRQ_ERR
194775. BNXT_RE_RES_SRQ_LOAD_ERR
194776. BNXT_RE_RES_TX_DOMAIN_ERR
194777. BNXT_RE_RES_TX_INVALID_RKEY
194778. BNXT_RE_RES_TX_NO_PERM
194779. BNXT_RE_RES_TX_PCI_ERR
194780. BNXT_RE_RES_TX_RANGE_ERR
194781. BNXT_RE_RES_UNALIGNED_ATOMIC
194782. BNXT_RE_RES_UNSUP_OPCODE
194783. BNXT_RE_RES_WQE_FORMAT_ERR
194784. BNXT_RE_RNR_NAKS_RCVD
194785. BNXT_RE_ROCEV2_IPV4_PACKET
194786. BNXT_RE_ROCEV2_IPV6_PACKET
194787. BNXT_RE_ROCE_V1_PACKET
194788. BNXT_RE_RQ_WQE_THRESHOLD
194789. BNXT_RE_RX_BYTES
194790. BNXT_RE_RX_DISCARDS
194791. BNXT_RE_RX_DROPS
194792. BNXT_RE_RX_PKTS
194793. BNXT_RE_SEQ_ERR_NAKS_RCVD
194794. BNXT_RE_TO_RETRANSMITS
194795. BNXT_RE_TX_BYTES
194796. BNXT_RE_TX_PKTS
194797. BNXT_RE_UCNTX_CMASK_HAVE_CCTX
194798. BNXT_RE_UD_QP_HW_STALL
194799. BNXT_RE_UNRECOVERABLE_ERR
194800. BNXT_RING_COAL_NOW_SP_EVENT
194801. BNXT_RMEM_RING_PTE_FLAG
194802. BNXT_RMEM_USE_FULL_PAGE_FLAG
194803. BNXT_RMEM_VALID_PTE_FLAG
194804. BNXT_ROCE_ULP
194805. BNXT_RST_RING_SP_EVENT
194806. BNXT_RX_COPY_THRESH
194807. BNXT_RX_DMA_OFFSET
194808. BNXT_RX_EVENT
194809. BNXT_RX_HDL
194810. BNXT_RX_MASK_SP_EVENT
194811. BNXT_RX_NTP_FLTR_SP_EVENT
194812. BNXT_RX_OFFSET
194813. BNXT_RX_PAGE_MODE
194814. BNXT_RX_PAGE_SHIFT
194815. BNXT_RX_PAGE_SIZE
194816. BNXT_RX_STATS_ENTRY
194817. BNXT_RX_STATS_EXT_COS_ENTRIES
194818. BNXT_RX_STATS_EXT_COS_ENTRY
194819. BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES
194820. BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY
194821. BNXT_RX_STATS_EXT_ENTRY
194822. BNXT_RX_STATS_EXT_OFFSET
194823. BNXT_RX_STATS_EXT_PFC_ENTRIES
194824. BNXT_RX_STATS_EXT_PFC_ENTRY
194825. BNXT_RX_STATS_OFFSET
194826. BNXT_RX_STATS_PRI_ENTRIES
194827. BNXT_RX_STATS_PRI_ENTRY
194828. BNXT_SINGLE_PF
194829. BNXT_SRIOV_CFG_WAIT_TMO
194830. BNXT_SRIOV_H
194831. BNXT_STATE_ABORT_ERR
194832. BNXT_STATE_FW_FATAL_COND
194833. BNXT_STATE_FW_RESET_DET
194834. BNXT_STATE_IN_FW_RESET
194835. BNXT_STATE_IN_SP_TASK
194836. BNXT_STATE_OPEN
194837. BNXT_STATE_READ_STATS
194838. BNXT_SUPPORTS_TPA
194839. BNXT_TC_ACTION_FLAG_DROP
194840. BNXT_TC_ACTION_FLAG_FWD
194841. BNXT_TC_ACTION_FLAG_FWD_VXLAN
194842. BNXT_TC_ACTION_FLAG_POP_VLAN
194843. BNXT_TC_ACTION_FLAG_PUSH_VLAN
194844. BNXT_TC_ACTION_FLAG_TUNNEL_DECAP
194845. BNXT_TC_ACTION_FLAG_TUNNEL_ENCAP
194846. BNXT_TC_FLOW_FLAGS_ETH_ADDRS
194847. BNXT_TC_FLOW_FLAGS_ICMP
194848. BNXT_TC_FLOW_FLAGS_IPV4_ADDRS
194849. BNXT_TC_FLOW_FLAGS_IPV6_ADDRS
194850. BNXT_TC_FLOW_FLAGS_PORTS
194851. BNXT_TC_FLOW_FLAGS_TUNL_ETH_ADDRS
194852. BNXT_TC_FLOW_FLAGS_TUNL_ID
194853. BNXT_TC_FLOW_FLAGS_TUNL_IPV4_ADDRS
194854. BNXT_TC_FLOW_FLAGS_TUNL_IPV6_ADDRS
194855. BNXT_TC_FLOW_FLAGS_TUNL_PORTS
194856. BNXT_TC_FLOW_FLAGS_TUNNEL
194857. BNXT_TC_H
194858. BNXT_TC_L2_KEY_LEN
194859. BNXT_TEST_FL_EXT_LPBK
194860. BNXT_TIMER_INTERVAL
194861. BNXT_TPA_INNER_L2_OFF
194862. BNXT_TPA_INNER_L3_OFF
194863. BNXT_TPA_L4_SIZE
194864. BNXT_TPA_OUTER_L3_OFF
194865. BNXT_TX_EVENT
194866. BNXT_TX_HDL
194867. BNXT_TX_PUSH_THRESH
194868. BNXT_TX_STATS_ENTRY
194869. BNXT_TX_STATS_EXT_COS_ENTRIES
194870. BNXT_TX_STATS_EXT_COS_ENTRY
194871. BNXT_TX_STATS_EXT_ENTRY
194872. BNXT_TX_STATS_EXT_OFFSET
194873. BNXT_TX_STATS_EXT_PFC_ENTRIES
194874. BNXT_TX_STATS_EXT_PFC_ENTRY
194875. BNXT_TX_STATS_OFFSET
194876. BNXT_TX_STATS_PRI_ENTRIES
194877. BNXT_TX_STATS_PRI_ENTRY
194878. BNXT_TX_TIMEOUT
194879. BNXT_UCODE_TRAILER_SIGNATURE
194880. BNXT_ULP_H
194881. BNXT_UPDATE_PHY_SP_EVENT
194882. BNXT_VF
194883. BNXT_VFR_H
194884. BNXT_VF_LINK_FORCED
194885. BNXT_VF_LINK_UP
194886. BNXT_VF_MAX_L2_CTX
194887. BNXT_VF_MAX_RSS_CTX
194888. BNXT_VF_MIN_L2_CTX
194889. BNXT_VF_MIN_RSS_CTX
194890. BNXT_VF_QOS
194891. BNXT_VF_RESV_STRATEGY_MAXIMAL
194892. BNXT_VF_RESV_STRATEGY_MINIMAL
194893. BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC
194894. BNXT_VF_SPOOFCHK
194895. BNXT_VF_TRUST
194896. BNXT_VNIC_MCAST_FLAG
194897. BNXT_VNIC_RFS_FLAG
194898. BNXT_VNIC_RFS_NEW_RSS_FLAG
194899. BNXT_VNIC_RSS_FLAG
194900. BNXT_VNIC_UCAST_FLAG
194901. BNXT_VXLAN_ADD_PORT_SP_EVENT
194902. BNXT_VXLAN_DEL_PORT_SP_EVENT
194903. BNXT_XDP_H
194904. BNX_DIR_ATTR_NONE
194905. BNX_DIR_ATTR_NO_CHKSUM
194906. BNX_DIR_ATTR_PROP_STREAM
194907. BNX_DIR_EXT_INACTIVE
194908. BNX_DIR_EXT_NONE
194909. BNX_DIR_EXT_UPDATE
194910. BNX_DIR_ORDINAL_FIRST
194911. BNX_DIR_TYPE_APE_FW
194912. BNX_DIR_TYPE_APE_PATCH
194913. BNX_DIR_TYPE_AVS
194914. BNX_DIR_TYPE_BONO_FW
194915. BNX_DIR_TYPE_BONO_PATCH
194916. BNX_DIR_TYPE_BOOTCODE
194917. BNX_DIR_TYPE_BOOTCODE_2
194918. BNX_DIR_TYPE_CCM
194919. BNX_DIR_TYPE_CHIMP_PATCH
194920. BNX_DIR_TYPE_EXP_ROM_MBA
194921. BNX_DIR_TYPE_EXT_PHY
194922. BNX_DIR_TYPE_FUNC_CFG
194923. BNX_DIR_TYPE_ISCSI_BOOT
194924. BNX_DIR_TYPE_ISCSI_BOOT_CFG6
194925. BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6
194926. BNX_DIR_TYPE_ISCSI_BOOT_IPV6
194927. BNX_DIR_TYPE_KONG_FW
194928. BNX_DIR_TYPE_KONG_PATCH
194929. BNX_DIR_TYPE_MGMT_AUDIT_LOG
194930. BNX_DIR_TYPE_MGMT_CFG
194931. BNX_DIR_TYPE_MGMT_DATA
194932. BNX_DIR_TYPE_MGMT_EVENT_LOG
194933. BNX_DIR_TYPE_MGMT_WEB_DATA
194934. BNX_DIR_TYPE_MGMT_WEB_META
194935. BNX_DIR_TYPE_PCIE
194936. BNX_DIR_TYPE_PCI_CFG
194937. BNX_DIR_TYPE_PKG_LOG
194938. BNX_DIR_TYPE_PORT_CFG
194939. BNX_DIR_TYPE_PORT_MACRO
194940. BNX_DIR_TYPE_SHARED_CFG
194941. BNX_DIR_TYPE_TANG_FW
194942. BNX_DIR_TYPE_TANG_PATCH
194943. BNX_DIR_TYPE_TSCF_UCODE
194944. BNX_DIR_TYPE_UNUSED
194945. BNX_DIR_TYPE_UPDATE
194946. BNX_DIR_TYPE_VPD
194947. BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS
194948. BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK
194949. BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP
194950. BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM
194951. BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION
194952. BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP
194953. BNX_PKG_LOG_FIELD_IDX_PKG_VERSION
194954. BN_MASK
194955. BO
194956. BO16
194957. BO16F
194958. BO16T
194959. BO32
194960. BO32DNZ
194961. BO32DZ
194962. BO32F
194963. BO32T
194964. BOARD
194965. BOARDID_LEN
194966. BOARDREG
194967. BOARDREV_PROMOTABLE
194968. BOARDREV_PROMOTED
194969. BOARD_40LD
194970. BOARD_503
194971. BOARD_503_ACC
194972. BOARD_503_ISL3861
194973. BOARD_503_ISL3863
194974. BOARD_505
194975. BOARD_505A
194976. BOARD_505AMX
194977. BOARD_505_2958
194978. BOARD_64BIT
194979. BOARD_A821
194980. BOARD_ACL8112
194981. BOARD_ACL8113
194982. BOARD_ACL8216
194983. BOARD_ACTIVE
194984. BOARD_ADLINK_PCI7224
194985. BOARD_ADLINK_PCI7248
194986. BOARD_ADLINK_PCI7296
194987. BOARD_APCI1016
194988. BOARD_APCI1516
194989. BOARD_APCI1648
194990. BOARD_APCI1696
194991. BOARD_APCI2016
194992. BOARD_APCI3000_16
194993. BOARD_APCI3000_4
194994. BOARD_APCI3000_8
194995. BOARD_APCI3001
194996. BOARD_APCI3002_16
194997. BOARD_APCI3002_4
194998. BOARD_APCI3002_8
194999. BOARD_APCI3003
195000. BOARD_APCI3006_16
195001. BOARD_APCI3006_4
195002. BOARD_APCI3006_8
195003. BOARD_APCI3010_16
195004. BOARD_APCI3010_4
195005. BOARD_APCI3010_8
195006. BOARD_APCI3016_16
195007. BOARD_APCI3016_4
195008. BOARD_APCI3016_8
195009. BOARD_APCI3100_16_4
195010. BOARD_APCI3100_8_4
195011. BOARD_APCI3106_16_4
195012. BOARD_APCI3106_8_4
195013. BOARD_APCI3110_16_4
195014. BOARD_APCI3110_8_4
195015. BOARD_APCI3116_16_4
195016. BOARD_APCI3116_8_4
195017. BOARD_APCI3120
195018. BOARD_APCI3500
195019. BOARD_BCM963XX_H_
195020. BOARD_BUDDHA
195021. BOARD_CATWEASEL
195022. BOARD_CB_PCIDIO24
195023. BOARD_CB_PCIDIO24H
195024. BOARD_CB_PCIDIO48H_NEW
195025. BOARD_CB_PCIDIO48H_OLD
195026. BOARD_CB_PCIDIO96H
195027. BOARD_CFG_STAT
195028. BOARD_CIODAS800
195029. BOARD_CIODAS801
195030. BOARD_CIODAS802
195031. BOARD_CIODAS80216
195032. BOARD_CONFIG_BUFSZ
195033. BOARD_CONTROL
195034. BOARD_CONTROL_REG
195035. BOARD_COUNT
195036. BOARD_CTRL
195037. BOARD_DAQBOARD2000
195038. BOARD_DAQBOARD2001
195039. BOARD_DAS1701AO
195040. BOARD_DAS1701ST
195041. BOARD_DAS1701ST_DA
195042. BOARD_DAS1702AO
195043. BOARD_DAS1702HR
195044. BOARD_DAS1702HR_DA
195045. BOARD_DAS1702ST
195046. BOARD_DAS1702ST_DA
195047. BOARD_DAS1801AO
195048. BOARD_DAS1801HC
195049. BOARD_DAS1801ST
195050. BOARD_DAS1801ST_DA
195051. BOARD_DAS1802AO
195052. BOARD_DAS1802HC
195053. BOARD_DAS1802HR
195054. BOARD_DAS1802HR_DA
195055. BOARD_DAS1802ST
195056. BOARD_DAS1802ST_DA
195057. BOARD_DAS800
195058. BOARD_DAS801
195059. BOARD_DAS802
195060. BOARD_DATA_MAGIC
195061. BOARD_DATA_MAGIC2
195062. BOARD_DDA02_12
195063. BOARD_DDA02_16
195064. BOARD_DDA04_12
195065. BOARD_DDA04_16
195066. BOARD_DDA08_12
195067. BOARD_DDA08_16
195068. BOARD_DM7520
195069. BOARD_DT3001
195070. BOARD_DT3001_PGL
195071. BOARD_DT3002
195072. BOARD_DT3003
195073. BOARD_DT3003_PGL
195074. BOARD_DT3004
195075. BOARD_DT3005
195076. BOARD_DTC3181E
195077. BOARD_EVENT_BIND
195078. BOARD_EVENT_DEMOD_LOCK
195079. BOARD_EVENT_DEMOD_UNLOCK
195080. BOARD_EVENT_EMERGENCY_WARNING_SIGNAL
195081. BOARD_EVENT_FE_LOCK
195082. BOARD_EVENT_FE_UNLOCK
195083. BOARD_EVENT_MULTIPLEX_ERRORS
195084. BOARD_EVENT_MULTIPLEX_OK
195085. BOARD_EVENT_POWER_INIT
195086. BOARD_EVENT_POWER_RESUME
195087. BOARD_EVENT_POWER_SUSPEND
195088. BOARD_EVENT_RECEPTION_1
195089. BOARD_EVENT_RECEPTION_2
195090. BOARD_EVENT_RECEPTION_3
195091. BOARD_EVENT_RECEPTION_LOST_0
195092. BOARD_EVENT_RECEPTION_MAX_4
195093. BOARD_EVENT_SCAN_COMP
195094. BOARD_EVENT_SCAN_PROG
195095. BOARD_EXT_FEATURE1_REG
195096. BOARD_EXT_FEATURE2_REG
195097. BOARD_FEATURES
195098. BOARD_GEO_ADDR_REG
195099. BOARD_GPIO_12
195100. BOARD_GPIO_13
195101. BOARD_GPIO_COMPONENT_BUS_ADAPTER
195102. BOARD_GPIO_COMPONENT_DEMOD
195103. BOARD_GPIO_FUNCTION_BOARD_OFF
195104. BOARD_GPIO_FUNCTION_BOARD_ON
195105. BOARD_GPIO_FUNCTION_COMPONENT_OFF
195106. BOARD_GPIO_FUNCTION_COMPONENT_ON
195107. BOARD_GPIO_FUNCTION_SUBBAND_GPIO
195108. BOARD_GPIO_FUNCTION_SUBBAND_PWM
195109. BOARD_GPIO_PACTRL
195110. BOARD_HP_C2502
195111. BOARD_ID
195112. BOARD_IDX_OVERFLOW
195113. BOARD_IDX_STATIC
195114. BOARD_ID_LANAI256
195115. BOARD_INFO
195116. BOARD_INIT
195117. BOARD_IOMAP
195118. BOARD_IO_ADDR
195119. BOARD_ISO813
195120. BOARD_JR3_1
195121. BOARD_JR3_2
195122. BOARD_JR3_3
195123. BOARD_JR3_4
195124. BOARD_JUMPER0_INSTALLED_BIT
195125. BOARD_JUMPER1_INSTALLED_BIT
195126. BOARD_ME2000
195127. BOARD_ME2600
195128. BOARD_ME4650
195129. BOARD_ME4660
195130. BOARD_ME4660I
195131. BOARD_ME4660IS
195132. BOARD_ME4660S
195133. BOARD_ME4670
195134. BOARD_ME4670I
195135. BOARD_ME4670IS
195136. BOARD_ME4670S
195137. BOARD_ME4680
195138. BOARD_ME4680I
195139. BOARD_ME4680IS
195140. BOARD_ME4680S
195141. BOARD_MEMMAP
195142. BOARD_MF624
195143. BOARD_MF634
195144. BOARD_MINICARD
195145. BOARD_MODFAIL_REG
195146. BOARD_MODRST_REG
195147. BOARD_NCR5380
195148. BOARD_NCR53C400
195149. BOARD_NCR53C400A
195150. BOARD_NI_PCI1200
195151. BOARD_NI_PCI6503
195152. BOARD_NI_PCI6503B
195153. BOARD_NI_PCI6503X
195154. BOARD_NI_PCIDIO96
195155. BOARD_NI_PCIDIO96B
195156. BOARD_NI_PXI6508
195157. BOARD_NI_PXI_6503
195158. BOARD_NOT_READY
195159. BOARD_PCI1710
195160. BOARD_PCI1710HG
195161. BOARD_PCI1711
195162. BOARD_PCI1713
195163. BOARD_PCI1731
195164. BOARD_PCI4520
195165. BOARD_PCI6014
195166. BOARD_PCI6023E
195167. BOARD_PCI6024E
195168. BOARD_PCI6025E
195169. BOARD_PCI6031E
195170. BOARD_PCI6032E
195171. BOARD_PCI6033E
195172. BOARD_PCI6034E
195173. BOARD_PCI6035E
195174. BOARD_PCI6036E
195175. BOARD_PCI6052E
195176. BOARD_PCI6071E
195177. BOARD_PCI6110
195178. BOARD_PCI6111
195179. BOARD_PCI6143
195180. BOARD_PCI6220
195181. BOARD_PCI6221
195182. BOARD_PCI6221_37PIN
195183. BOARD_PCI6224
195184. BOARD_PCI6225
195185. BOARD_PCI6229
195186. BOARD_PCI6250
195187. BOARD_PCI6251
195188. BOARD_PCI6254
195189. BOARD_PCI6259
195190. BOARD_PCI6280
195191. BOARD_PCI6281
195192. BOARD_PCI6284
195193. BOARD_PCI6289
195194. BOARD_PCI6509
195195. BOARD_PCI6510
195196. BOARD_PCI6511
195197. BOARD_PCI6512
195198. BOARD_PCI6513
195199. BOARD_PCI6514
195200. BOARD_PCI6515
195201. BOARD_PCI6516
195202. BOARD_PCI6517
195203. BOARD_PCI6518
195204. BOARD_PCI6519
195205. BOARD_PCI6520
195206. BOARD_PCI6521
195207. BOARD_PCI6527
195208. BOARD_PCI6528
195209. BOARD_PCI6534
195210. BOARD_PCI6601
195211. BOARD_PCI6602
195212. BOARD_PCI6608
195213. BOARD_PCI6624
195214. BOARD_PCI6703
195215. BOARD_PCI6704
195216. BOARD_PCI6711
195217. BOARD_PCI6713
195218. BOARD_PCI6731
195219. BOARD_PCI6733
195220. BOARD_PCI7230
195221. BOARD_PCI7233
195222. BOARD_PCI7234
195223. BOARD_PCI7432
195224. BOARD_PCI7433
195225. BOARD_PCI7434
195226. BOARD_PCI9118DG
195227. BOARD_PCI9118HG
195228. BOARD_PCI9118HR
195229. BOARD_PCIDAS1000
195230. BOARD_PCIDAS1001
195231. BOARD_PCIDAS1002
195232. BOARD_PCIDAS1200
195233. BOARD_PCIDAS1200_JR
195234. BOARD_PCIDAS1602_12
195235. BOARD_PCIDAS1602_16
195236. BOARD_PCIDAS1602_16_JR
195237. BOARD_PCIDAS4020_12
195238. BOARD_PCIDAS6013
195239. BOARD_PCIDAS6014
195240. BOARD_PCIDAS6023
195241. BOARD_PCIDAS6025
195242. BOARD_PCIDAS6030
195243. BOARD_PCIDAS6031
195244. BOARD_PCIDAS6032
195245. BOARD_PCIDAS6033
195246. BOARD_PCIDAS6034
195247. BOARD_PCIDAS6035
195248. BOARD_PCIDAS6036
195249. BOARD_PCIDAS6040
195250. BOARD_PCIDAS6052
195251. BOARD_PCIDAS6070
195252. BOARD_PCIDAS6071
195253. BOARD_PCIDAS6402_12
195254. BOARD_PCIDAS6402_16
195255. BOARD_PCIDAS6402_16_JR
195256. BOARD_PCIDAS64_M1_14
195257. BOARD_PCIDAS64_M1_16
195258. BOARD_PCIDAS64_M1_16_JR
195259. BOARD_PCIDAS64_M2_14
195260. BOARD_PCIDAS64_M2_16
195261. BOARD_PCIDAS64_M2_16_JR
195262. BOARD_PCIDAS64_M3_14
195263. BOARD_PCIDAS64_M3_16
195264. BOARD_PCIDAS64_M3_16_JR
195265. BOARD_PCIDIO_32HS
195266. BOARD_PCIE6251
195267. BOARD_PCIE6259
195268. BOARD_PCIMIO_16E_1
195269. BOARD_PCIMIO_16E_4
195270. BOARD_PCIMIO_16XE_10
195271. BOARD_PCIMIO_16XE_50
195272. BOARD_PCL812
195273. BOARD_PCL812PG
195274. BOARD_PCL813
195275. BOARD_PCL813B
195276. BOARD_PXI6025E
195277. BOARD_PXI6030E
195278. BOARD_PXI6031E
195279. BOARD_PXI6040E
195280. BOARD_PXI6052E
195281. BOARD_PXI6070E
195282. BOARD_PXI6071E
195283. BOARD_PXI6143
195284. BOARD_PXI6220
195285. BOARD_PXI6221
195286. BOARD_PXI6224
195287. BOARD_PXI6225
195288. BOARD_PXI6229
195289. BOARD_PXI6250
195290. BOARD_PXI6251
195291. BOARD_PXI6254
195292. BOARD_PXI6259
195293. BOARD_PXI6280
195294. BOARD_PXI6281
195295. BOARD_PXI6284
195296. BOARD_PXI6289
195297. BOARD_PXI6509
195298. BOARD_PXI6511
195299. BOARD_PXI6512
195300. BOARD_PXI6513
195301. BOARD_PXI6514
195302. BOARD_PXI6515
195303. BOARD_PXI6521
195304. BOARD_PXI6527
195305. BOARD_PXI6528
195306. BOARD_PXI6533
195307. BOARD_PXI6602
195308. BOARD_PXI6608
195309. BOARD_PXI6624
195310. BOARD_PXI6704
195311. BOARD_PXI6711
195312. BOARD_PXI6713
195313. BOARD_PXI6733
195314. BOARD_PXIE6251
195315. BOARD_PXIE6259
195316. BOARD_QME7342
195317. BOARD_QMH7342
195318. BOARD_QMH7360
195319. BOARD_RB532
195320. BOARD_RB532A
195321. BOARD_READY
195322. BOARD_RESET_BIT
195323. BOARD_RST_STATUS
195324. BOARD_SLOT
195325. BOARD_STATUS_REG
195326. BOARD_STRUCT
195327. BOARD_SW_READ_REG
195328. BOARD_TAG
195329. BOARD_TBEN_REG
195330. BOARD_TYPE_2GHZ
195331. BOARD_TYPE_5GHZ
195332. BOARD_TYPE_COM8_18XX
195333. BOARD_TYPE_DB1200
195334. BOARD_TYPE_DB1300
195335. BOARD_TYPE_DEFAULT
195336. BOARD_TYPE_DVP_18XX
195337. BOARD_TYPE_EVB_18XX
195338. BOARD_TYPE_FPGA_18XX
195339. BOARD_TYPE_HDK_18XX
195340. BOARD_TYPE_NORMAL_MASK
195341. BOARD_TYPE_PB1100
195342. BOARD_TYPE_TEST_MASK
195343. BOARD_USB_COMBO
195344. BOARD_USB_DONGLE
195345. BOARD_USB_HIGH_PA
195346. BOARD_USB_SOLO
195347. BOARD_VEC
195348. BOARD_VERS_MAX
195349. BOARD_XSURF
195350. BOCHS_QEMU_STDVGA
195351. BOCHS_UNKNOWN
195352. BOCnt
195353. BODNZ
195354. BODNZF
195355. BODNZFP
195356. BODNZM4
195357. BODNZP
195358. BODNZP4
195359. BODNZT
195360. BODNZTP
195361. BODY
195362. BODZ
195363. BODZF
195364. BODZFP
195365. BODZM4
195366. BODZP
195367. BODZP4
195368. BODZT
195369. BODZTP
195370. BOE
195371. BOF
195372. BOFDMEN
195373. BOFDMRXADCPHASE
195374. BOFDMSERVICE
195375. BOFDMTXDACPHASE
195376. BOFDMTXLENGTH
195377. BOFDMTXPARITY
195378. BOFDMTXRATE
195379. BOFDMTXRESERVED
195380. BOFDMTXSTART
195381. BOFDMTXSTATUS
195382. BOFDM_CONTINUE_TX
195383. BOFDM_SINGLE_CARRIER
195384. BOFDM_SINGLE_TONE
195385. BOFDM_TXON
195386. BOFDM_TXSC
195387. BOFF
195388. BOFFTMR
195389. BOFM4
195390. BOFP
195391. BOFP4
195392. BOGO_DIRENT_SIZE
195393. BOGUS
195394. BOGUS0
195395. BOGUS1
195396. BOGUS2
195397. BOGUS3
195398. BOGUSNTAG
195399. BOGUSTAG
195400. BOLR
195401. BON
195402. BONAIRE_GB_ADDR_CONFIG_GOLDEN
195403. BONAIRE_IO_MC_REGS_SIZE
195404. BONAIRE_MC2_UCODE_SIZE
195405. BONAIRE_MC_UCODE_SIZE
195406. BONAIRE_RLC_UCODE_SIZE
195407. BONAIRE_SMC_UCODE_SIZE
195408. BONAIRE_SMC_UCODE_START
195409. BONDING_SLAVE_STATE_ACTIVE
195410. BONDING_SLAVE_STATE_INACTIVE
195411. BONDING_SLAVE_STATE_NA
195412. BOND_3AD_STAT_LACPDU_ILLEGAL_RX
195413. BOND_3AD_STAT_LACPDU_RX
195414. BOND_3AD_STAT_LACPDU_TX
195415. BOND_3AD_STAT_LACPDU_UNKNOWN_RX
195416. BOND_3AD_STAT_MARKER_RESP_RX
195417. BOND_3AD_STAT_MARKER_RESP_TX
195418. BOND_3AD_STAT_MARKER_RX
195419. BOND_3AD_STAT_MARKER_TX
195420. BOND_3AD_STAT_MARKER_UNKNOWN_RX
195421. BOND_3AD_STAT_MAX
195422. BOND_3AD_STAT_PAD
195423. BOND_ABI_VERSION
195424. BOND_AD_BANDWIDTH
195425. BOND_AD_COUNT
195426. BOND_AD_INFO
195427. BOND_AD_STABLE
195428. BOND_ALB_DEFAULT_LP_INTERVAL
195429. BOND_ALB_INFO
195430. BOND_ALB_LP_INTERVAL
195431. BOND_ALB_LP_TICKS
195432. BOND_ARP_FILTER
195433. BOND_ARP_FILTER_ACTIVE
195434. BOND_ARP_FILTER_BACKUP
195435. BOND_ARP_TARGETS_ALL
195436. BOND_ARP_TARGETS_ANY
195437. BOND_ARP_VALIDATE_ACTIVE
195438. BOND_ARP_VALIDATE_ALL
195439. BOND_ARP_VALIDATE_BACKUP
195440. BOND_ARP_VALIDATE_NONE
195441. BOND_CHANGE_ACTIVE_OLD
195442. BOND_CHECK_MII_STATUS
195443. BOND_CTL
195444. BOND_DEFAULT_MAX_BONDS
195445. BOND_DEFAULT_MIIMON
195446. BOND_DEFAULT_RESEND_IGMP
195447. BOND_DEFAULT_TX_QUEUES
195448. BOND_ENC_FEATURES
195449. BOND_ENSLAVE_OLD
195450. BOND_FOM_ACTIVE
195451. BOND_FOM_FOLLOW
195452. BOND_FOM_NONE
195453. BOND_I2S_CLR
195454. BOND_INFO_QUERY_OLD
195455. BOND_LINK_BACK
195456. BOND_LINK_DOWN
195457. BOND_LINK_FAIL
195458. BOND_LINK_NOCHANGE
195459. BOND_LINK_UP
195460. BOND_MAX_ARP_TARGETS
195461. BOND_MODE
195462. BOND_MODE_8023AD
195463. BOND_MODE_ACTIVEBACKUP
195464. BOND_MODE_ALB
195465. BOND_MODE_ALL_EX
195466. BOND_MODE_BROADCAST
195467. BOND_MODE_ROUNDROBIN
195468. BOND_MODE_TLB
195469. BOND_MODE_XOR
195470. BOND_MPLS_FEATURES
195471. BOND_MSDC0E_CLR
195472. BOND_OPTFLAG_IFDOWN
195473. BOND_OPTFLAG_NOSLAVES
195474. BOND_OPTFLAG_RAWVAL
195475. BOND_OPT_ACTIVE_SLAVE
195476. BOND_OPT_AD_ACTOR_SYSTEM
195477. BOND_OPT_AD_ACTOR_SYS_PRIO
195478. BOND_OPT_AD_SELECT
195479. BOND_OPT_AD_USER_PORT_KEY
195480. BOND_OPT_ALL_SLAVES_ACTIVE
195481. BOND_OPT_ARP_ALL_TARGETS
195482. BOND_OPT_ARP_INTERVAL
195483. BOND_OPT_ARP_TARGETS
195484. BOND_OPT_ARP_VALIDATE
195485. BOND_OPT_DOWNDELAY
195486. BOND_OPT_FAIL_OVER_MAC
195487. BOND_OPT_LACP_RATE
195488. BOND_OPT_LAST
195489. BOND_OPT_LP_INTERVAL
195490. BOND_OPT_MAX_NAMELEN
195491. BOND_OPT_MIIMON
195492. BOND_OPT_MINLINKS
195493. BOND_OPT_MODE
195494. BOND_OPT_NUM_PEER_NOTIF
195495. BOND_OPT_NUM_PEER_NOTIF_ALIAS
195496. BOND_OPT_PACKETS_PER_SLAVE
195497. BOND_OPT_PEER_NOTIF_DELAY
195498. BOND_OPT_PRIMARY
195499. BOND_OPT_PRIMARY_RESELECT
195500. BOND_OPT_QUEUE_ID
195501. BOND_OPT_RESEND_IGMP
195502. BOND_OPT_SLAVES
195503. BOND_OPT_TLB_DYNAMIC_LB
195504. BOND_OPT_UPDELAY
195505. BOND_OPT_USE_CARRIER
195506. BOND_OPT_VALID
195507. BOND_OPT_XMIT_HASH
195508. BOND_PCIE_CLR
195509. BOND_PRI_RESELECT_ALWAYS
195510. BOND_PRI_RESELECT_BETTER
195511. BOND_PRI_RESELECT_FAILURE
195512. BOND_RELEASE_OLD
195513. BOND_SCHEDULE
195514. BOND_SETHWADDR_OLD
195515. BOND_SLAVE_INFO_QUERY_OLD
195516. BOND_SLAVE_NOTIFY_LATER
195517. BOND_SLAVE_NOTIFY_NOW
195518. BOND_STATE_ACTIVE
195519. BOND_STATE_BACKUP
195520. BOND_TLB_REBALANCE_INTERVAL
195521. BOND_TLB_REBALANCE_TICKS
195522. BOND_VALFLAG_DEFAULT
195523. BOND_VALFLAG_MAX
195524. BOND_VALFLAG_MIN
195525. BOND_VLAN_FEATURES
195526. BOND_XMIT_POLICY_ENCAP23
195527. BOND_XMIT_POLICY_ENCAP34
195528. BOND_XMIT_POLICY_LAYER2
195529. BOND_XMIT_POLICY_LAYER23
195530. BOND_XMIT_POLICY_LAYER34
195531. BOND_XSTATS_3AD
195532. BOND_XSTATS_MAX
195533. BOND_XSTATS_UNSPEC
195534. BONITO
195535. BONITO_BONGENCFG
195536. BONITO_BONGENCFG_BUSERREN
195537. BONITO_BONGENCFG_BYTESWAP
195538. BONITO_BONGENCFG_CACHEALG
195539. BONITO_BONGENCFG_CACHEALG_SHIFT
195540. BONITO_BONGENCFG_CACHESTOP
195541. BONITO_BONGENCFG_CPUSELFRESET
195542. BONITO_BONGENCFG_DEBUGMODE
195543. BONITO_BONGENCFG_FORCE_IRQA
195544. BONITO_BONGENCFG_IRQA_FROM_INT1
195545. BONITO_BONGENCFG_IRQA_ISOUT
195546. BONITO_BONGENCFG_MSTRBYTESWAP
195547. BONITO_BONGENCFG_NORETRYTIMEOUT
195548. BONITO_BONGENCFG_OFFSET
195549. BONITO_BONGENCFG_PCIQUEUE
195550. BONITO_BONGENCFG_PREFETCHEN
195551. BONITO_BONGENCFG_SHORTCOPYTIMEOUT
195552. BONITO_BONGENCFG_SNOOPEN
195553. BONITO_BONGENCFG_UNCACHED
195554. BONITO_BONGENCFG_WBEHINDEN
195555. BONITO_BONITOBASE
195556. BONITO_BONPONCFG
195557. BONITO_BONPONCFG_BURSTORDER
195558. BONITO_BONPONCFG_CONFIG_DIS
195559. BONITO_BONPONCFG_CPUBIGEND
195560. BONITO_BONPONCFG_CPUPARITY
195561. BONITO_BONPONCFG_CPUTYPE
195562. BONITO_BONPONCFG_CPUTYPE_SHIFT
195563. BONITO_BONPONCFG_IS_ARBITER
195564. BONITO_BONPONCFG_PCIRESET_OUT
195565. BONITO_BONPONCFG_ROMBOOT
195566. BONITO_BONPONCFG_ROMBOOT_CPURESET
195567. BONITO_BONPONCFG_ROMBOOT_FLASH
195568. BONITO_BONPONCFG_ROMBOOT_SDRAM
195569. BONITO_BONPONCFG_ROMBOOT_SHIFT
195570. BONITO_BONPONCFG_ROMBOOT_SOCKET
195571. BONITO_BONPONCFG_ROMCS0FAST
195572. BONITO_BONPONCFG_ROMCS0SAMP
195573. BONITO_BONPONCFG_ROMCS0WIDTH
195574. BONITO_BONPONCFG_ROMCS1FAST
195575. BONITO_BONPONCFG_ROMCS1SAMP
195576. BONITO_BONPONCFG_ROMCS1WIDTH
195577. BONITO_BONPONCFG_SYSCONTROLLERRD
195578. BONITO_BOOT_BASE
195579. BONITO_BOOT_SIZE
195580. BONITO_BOOT_TOP
195581. BONITO_CONFIGBASE
195582. BONITO_COPBASE
195583. BONITO_COPCTRL
195584. BONITO_COPDADDR
195585. BONITO_COPGO
195586. BONITO_COPPADDR
195587. BONITO_COPSTAT
195588. BONITO_DEV_BASE
195589. BONITO_DEV_SIZE
195590. BONITO_DEV_TOP
195591. BONITO_FLASH_BASE
195592. BONITO_FLASH_SIZE
195593. BONITO_FLASH_TOP
195594. BONITO_GPIODATA
195595. BONITO_GPIODATA_OFFSET
195596. BONITO_GPIOIE
195597. BONITO_GPIO_GPINR
195598. BONITO_GPIO_GPINR_SHIFT
195599. BONITO_GPIO_GPIOR
195600. BONITO_GPIO_GPIOR_SHIFT
195601. BONITO_GPIO_GPIOW
195602. BONITO_GPIO_GPIOW_SHIFT
195603. BONITO_GPIO_INR
195604. BONITO_GPIO_IOR
195605. BONITO_GPIO_IOW
195606. BONITO_ICU_COPYEMPTY
195607. BONITO_ICU_COPYERR
195608. BONITO_ICU_COPYRDY
195609. BONITO_ICU_DMAEMPTY
195610. BONITO_ICU_DMARDY
195611. BONITO_ICU_DRAMPERR
195612. BONITO_ICU_GPIN
195613. BONITO_ICU_GPINS
195614. BONITO_ICU_GPINS_SHIFT
195615. BONITO_ICU_GPIO
195616. BONITO_ICU_GPIOS
195617. BONITO_ICU_GPIOS_SHIFT
195618. BONITO_ICU_MASTERERR
195619. BONITO_ICU_MBOX
195620. BONITO_ICU_MBOXES
195621. BONITO_ICU_MBOXES_SHIFT
195622. BONITO_ICU_PCIIRQ
195623. BONITO_ICU_RETRYERR
195624. BONITO_ICU_SYSTEMERR
195625. BONITO_IDECOPCTRL_DMA_RSTBIT
195626. BONITO_IDECOPCTRL_DMA_STARTBIT
195627. BONITO_IDECOPDADDR_DMA_DADDR
195628. BONITO_IDECOPDADDR_DMA_DADDR_SHIFT
195629. BONITO_IDECOPGO_DMAWCOUNT
195630. BONITO_IDECOPGO_DMAWCOUNT_SHIFT
195631. BONITO_IDECOPGO_DMA_SIZE
195632. BONITO_IDECOPGO_DMA_SIZE_SHIFT
195633. BONITO_IDECOPGO_DMA_WRITE
195634. BONITO_IDECOPPADDR_DMA_PADDR
195635. BONITO_IDECOPPADDR_DMA_PADDR_SHIFT
195636. BONITO_INTEDGE
195637. BONITO_INTEN
195638. BONITO_INTENCLR
195639. BONITO_INTENSET
195640. BONITO_INTISR
195641. BONITO_INTPOL
195642. BONITO_INTSTEER
195643. BONITO_IODEVCFG
195644. BONITO_IODEVCFG_BUFFBIT_CS0
195645. BONITO_IODEVCFG_BUFFBIT_CS1
195646. BONITO_IODEVCFG_BUFFBIT_CS2
195647. BONITO_IODEVCFG_BUFFBIT_CS3
195648. BONITO_IODEVCFG_BUFFBIT_IDE
195649. BONITO_IODEVCFG_CPUCLOCKPERIOD
195650. BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT
195651. BONITO_IODEVCFG_DMAOFF_IDE
195652. BONITO_IODEVCFG_DMAOFF_IDE_SHIFT
195653. BONITO_IODEVCFG_DMAON_IDE
195654. BONITO_IODEVCFG_DMAON_IDE_SHIFT
195655. BONITO_IODEVCFG_EPROMSPLIT
195656. BONITO_IODEVCFG_MODEBIT_IDE
195657. BONITO_IODEVCFG_MOREABITS_CS0
195658. BONITO_IODEVCFG_MOREABITS_CS1
195659. BONITO_IODEVCFG_MOREABITS_CS2
195660. BONITO_IODEVCFG_MOREABITS_CS3
195661. BONITO_IODEVCFG_SPEEDBIT_CS0
195662. BONITO_IODEVCFG_SPEEDBIT_CS1
195663. BONITO_IODEVCFG_SPEEDBIT_CS2
195664. BONITO_IODEVCFG_SPEEDBIT_CS3
195665. BONITO_IODEVCFG_SPEEDBIT_IDE
195666. BONITO_IODEVCFG_WORDSWAPBIT_IDE
195667. BONITO_LDMAADDR
195668. BONITO_LDMABASE
195669. BONITO_LDMACTRL
195670. BONITO_LDMADATA
195671. BONITO_LDMAGO
195672. BONITO_LDMASTAT
195673. BONITO_PCIBADADDR
195674. BONITO_PCIBASE0
195675. BONITO_PCIBASE1
195676. BONITO_PCIBASE2
195677. BONITO_PCICACHECTRL
195678. BONITO_PCICACHECTRL_CACHECMD
195679. BONITO_PCICACHECTRL_CACHECMDLINE
195680. BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT
195681. BONITO_PCICACHECTRL_CACHECMD_SHIFT
195682. BONITO_PCICACHECTRL_CMDEXEC
195683. BONITO_PCICACHECTRL_CPUCOH_EN
195684. BONITO_PCICACHECTRL_CPUCOH_PRES
195685. BONITO_PCICACHECTRL_IOBCCOH_EN
195686. BONITO_PCICACHECTRL_IOBCCOH_PRES
195687. BONITO_PCICACHETAG
195688. BONITO_PCICFG_BASE
195689. BONITO_PCICFG_SIZE
195690. BONITO_PCICFG_TOP
195691. BONITO_PCICLASS
195692. BONITO_PCICMD
195693. BONITO_PCICMD_ASTEPEN
195694. BONITO_PCICMD_MABORT_CLR
195695. BONITO_PCICMD_MEMEN
195696. BONITO_PCICMD_MPERR_CLR
195697. BONITO_PCICMD_MSTREN
195698. BONITO_PCICMD_MTABORT_CLR
195699. BONITO_PCICMD_PERRRESPEN
195700. BONITO_PCICMD_PERR_CLR
195701. BONITO_PCICMD_SERREN
195702. BONITO_PCICMD_SERR_CLR
195703. BONITO_PCICMD_TABORT_CLR
195704. BONITO_PCICONFIGBASE
195705. BONITO_PCIDID
195706. BONITO_PCIEXPRBASE
195707. BONITO_PCIHI_BASE
195708. BONITO_PCIHI_SIZE
195709. BONITO_PCIHI_TOP
195710. BONITO_PCIINT
195711. BONITO_PCIIO_BASE
195712. BONITO_PCIIO_SIZE
195713. BONITO_PCIIO_TOP
195714. BONITO_PCILO0_BASE
195715. BONITO_PCILO1_BASE
195716. BONITO_PCILO2_BASE
195717. BONITO_PCILO_BASE
195718. BONITO_PCILO_SIZE
195719. BONITO_PCILO_TOP
195720. BONITO_PCILTIMER
195721. BONITO_PCILTIMER_BUSLATENCY
195722. BONITO_PCILTIMER_BUSLATENCY_SHIFT
195723. BONITO_PCIMAIL0
195724. BONITO_PCIMAIL0_OFFSET
195725. BONITO_PCIMAIL1
195726. BONITO_PCIMAIL1_OFFSET
195727. BONITO_PCIMAIL2
195728. BONITO_PCIMAIL2_OFFSET
195729. BONITO_PCIMAIL3
195730. BONITO_PCIMAIL3_OFFSET
195731. BONITO_PCIMAP
195732. BONITO_PCIMAP_CFG
195733. BONITO_PCIMAP_PCIMAP_2
195734. BONITO_PCIMAP_PCIMAP_LO0
195735. BONITO_PCIMAP_PCIMAP_LO0_SHIFT
195736. BONITO_PCIMAP_PCIMAP_LO1
195737. BONITO_PCIMAP_PCIMAP_LO1_SHIFT
195738. BONITO_PCIMAP_PCIMAP_LO2
195739. BONITO_PCIMAP_PCIMAP_LO2_SHIFT
195740. BONITO_PCIMAP_WIN
195741. BONITO_PCIMAP_WINBASE
195742. BONITO_PCIMAP_WINOFFSET
195743. BONITO_PCIMAP_WINSIZE
195744. BONITO_PCIMEMBASECFG
195745. BONITO_PCIMEMBASECFGBASE
195746. BONITO_PCIMEMBASECFGSIZE
195747. BONITO_PCIMEMBASECFG_ADDRMASK
195748. BONITO_PCIMEMBASECFG_ADDRTRANS
195749. BONITO_PCIMEMBASECFG_AMASK
195750. BONITO_PCIMEMBASECFG_ASHIFT
195751. BONITO_PCIMEMBASECFG_MASK
195752. BONITO_PCIMEMBASECFG_MEMBASE0_CACHED
195753. BONITO_PCIMEMBASECFG_MEMBASE0_IO
195754. BONITO_PCIMEMBASECFG_MEMBASE0_MASK
195755. BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT
195756. BONITO_PCIMEMBASECFG_MEMBASE0_TRANS
195757. BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT
195758. BONITO_PCIMEMBASECFG_MEMBASE1_CACHED
195759. BONITO_PCIMEMBASECFG_MEMBASE1_IO
195760. BONITO_PCIMEMBASECFG_MEMBASE1_MASK
195761. BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT
195762. BONITO_PCIMEMBASECFG_MEMBASE1_TRANS
195763. BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT
195764. BONITO_PCIMEMBASECFG_SIZE
195765. BONITO_PCIMSTAT
195766. BONITO_PCITOPHYS
195767. BONITO_PCI_REG
195768. BONITO_REGBASE
195769. BONITO_REG_BASE
195770. BONITO_REG_BLOCKMASK
195771. BONITO_REG_SIZE
195772. BONITO_REG_TOP
195773. BONITO_SDCFG
195774. BONITO_SDCFG_AABSENT
195775. BONITO_SDCFG_ABANKBIT
195776. BONITO_SDCFG_ACOLBITS
195777. BONITO_SDCFG_ACOLBITS_SHIFT
195778. BONITO_SDCFG_AROWBITS
195779. BONITO_SDCFG_AROWBITS_SHIFT
195780. BONITO_SDCFG_ASIDES
195781. BONITO_SDCFG_AWIDTH64
195782. BONITO_SDCFG_BABSENT
195783. BONITO_SDCFG_BBANKBIT
195784. BONITO_SDCFG_BCOLBITS
195785. BONITO_SDCFG_BCOLBITS_SHIFT
195786. BONITO_SDCFG_BROWBITS
195787. BONITO_SDCFG_BROWBITS_SHIFT
195788. BONITO_SDCFG_BSIDES
195789. BONITO_SDCFG_BWIDTH64
195790. BONITO_SDCFG_DRAMBURSTLEN
195791. BONITO_SDCFG_DRAMBURSTLEN_SHIFT
195792. BONITO_SDCFG_DRAMEXTREGS
195793. BONITO_SDCFG_DRAMMODESET
195794. BONITO_SDCFG_DRAMMODESET_DONE
195795. BONITO_SDCFG_DRAMPARITY
195796. BONITO_SDCFG_EXTPRECH
195797. BONITO_SDCFG_EXTRASCAS
195798. BONITO_SDCFG_EXTRASWIDTH
195799. BONITO_SDCFG_EXTRASWIDTH_SHIFT
195800. BONITO_SDCFG_EXTRDDATA
195801. BONITO_SOCKET_BASE
195802. BONITO_SOCKET_SIZE
195803. BONITO_SOCKET_TOP
195804. BONTMR
195805. BOOK
195806. BOOK3E_IDLE
195807. BOOK3E_IDLE_LOOP
195808. BOOK3E_PAGESZ_128GB
195809. BOOK3E_PAGESZ_128K
195810. BOOK3E_PAGESZ_128M
195811. BOOK3E_PAGESZ_16GB
195812. BOOK3E_PAGESZ_16K
195813. BOOK3E_PAGESZ_16M
195814. BOOK3E_PAGESZ_1GB
195815. BOOK3E_PAGESZ_1K
195816. BOOK3E_PAGESZ_1M
195817. BOOK3E_PAGESZ_1TB
195818. BOOK3E_PAGESZ_256GB
195819. BOOK3E_PAGESZ_256K
195820. BOOK3E_PAGESZ_256M
195821. BOOK3E_PAGESZ_2GB
195822. BOOK3E_PAGESZ_2K
195823. BOOK3E_PAGESZ_2M
195824. BOOK3E_PAGESZ_2TB
195825. BOOK3E_PAGESZ_32GB
195826. BOOK3E_PAGESZ_32K
195827. BOOK3E_PAGESZ_32M
195828. BOOK3E_PAGESZ_4GB
195829. BOOK3E_PAGESZ_4K
195830. BOOK3E_PAGESZ_4M
195831. BOOK3E_PAGESZ_512GB
195832. BOOK3E_PAGESZ_512K
195833. BOOK3E_PAGESZ_512M
195834. BOOK3E_PAGESZ_64GB
195835. BOOK3E_PAGESZ_64K
195836. BOOK3E_PAGESZ_64M
195837. BOOK3E_PAGESZ_8GB
195838. BOOK3E_PAGESZ_8K
195839. BOOK3E_PAGESZ_8M
195840. BOOK3S_HFLAG_DCBZ32
195841. BOOK3S_HFLAG_MULTI_PGSIZE
195842. BOOK3S_HFLAG_NATIVE_PS
195843. BOOK3S_HFLAG_NEW_TLBIE
195844. BOOK3S_HFLAG_PAIRED_SINGLE
195845. BOOK3S_HFLAG_SLB
195846. BOOK3S_HFLAG_SPLIT_HACK
195847. BOOK3S_INTERRUPT_ALIGNMENT
195848. BOOK3S_INTERRUPT_ALTIVEC
195849. BOOK3S_INTERRUPT_DATA_SEGMENT
195850. BOOK3S_INTERRUPT_DATA_STORAGE
195851. BOOK3S_INTERRUPT_DECREMENTER
195852. BOOK3S_INTERRUPT_DOORBELL
195853. BOOK3S_INTERRUPT_EXTERNAL
195854. BOOK3S_INTERRUPT_EXTERNAL_HV
195855. BOOK3S_INTERRUPT_FAC_UNAVAIL
195856. BOOK3S_INTERRUPT_FP_UNAVAIL
195857. BOOK3S_INTERRUPT_HMI
195858. BOOK3S_INTERRUPT_HV_DECREMENTER
195859. BOOK3S_INTERRUPT_HV_RM_HARD
195860. BOOK3S_INTERRUPT_HV_SOFTPATCH
195861. BOOK3S_INTERRUPT_H_DATA_STORAGE
195862. BOOK3S_INTERRUPT_H_DOORBELL
195863. BOOK3S_INTERRUPT_H_EMUL_ASSIST
195864. BOOK3S_INTERRUPT_H_FAC_UNAVAIL
195865. BOOK3S_INTERRUPT_H_INST_STORAGE
195866. BOOK3S_INTERRUPT_H_VIRT
195867. BOOK3S_INTERRUPT_INST_SEGMENT
195868. BOOK3S_INTERRUPT_INST_STORAGE
195869. BOOK3S_INTERRUPT_MACHINE_CHECK
195870. BOOK3S_INTERRUPT_PERFMON
195871. BOOK3S_INTERRUPT_PROGRAM
195872. BOOK3S_INTERRUPT_SYSCALL
195873. BOOK3S_INTERRUPT_SYSTEM_RESET
195874. BOOK3S_INTERRUPT_TRACE
195875. BOOK3S_INTERRUPT_VSX
195876. BOOK3S_IRQPRIO_ALIGNMENT
195877. BOOK3S_IRQPRIO_ALTIVEC
195878. BOOK3S_IRQPRIO_DATA_SEGMENT
195879. BOOK3S_IRQPRIO_DATA_STORAGE
195880. BOOK3S_IRQPRIO_DEBUG
195881. BOOK3S_IRQPRIO_DECREMENTER
195882. BOOK3S_IRQPRIO_EXTERNAL
195883. BOOK3S_IRQPRIO_FAC_UNAVAIL
195884. BOOK3S_IRQPRIO_FP_UNAVAIL
195885. BOOK3S_IRQPRIO_INST_SEGMENT
195886. BOOK3S_IRQPRIO_INST_STORAGE
195887. BOOK3S_IRQPRIO_MACHINE_CHECK
195888. BOOK3S_IRQPRIO_MAX
195889. BOOK3S_IRQPRIO_PERFORMANCE_MONITOR
195890. BOOK3S_IRQPRIO_PROGRAM
195891. BOOK3S_IRQPRIO_SYSCALL
195892. BOOK3S_IRQPRIO_SYSTEM_RESET
195893. BOOK3S_IRQPRIO_VSX
195894. BOOKE
195895. BOOKE_CLEAR_BTB
195896. BOOKE_INTERRUPT_ALIGNMENT
195897. BOOKE_INTERRUPT_ALTIVEC_ASSIST
195898. BOOKE_INTERRUPT_ALTIVEC_UNAVAIL
195899. BOOKE_INTERRUPT_AP_UNAVAIL
195900. BOOKE_INTERRUPT_CRITICAL
195901. BOOKE_INTERRUPT_DATA_STORAGE
195902. BOOKE_INTERRUPT_DEBUG
195903. BOOKE_INTERRUPT_DECREMENTER
195904. BOOKE_INTERRUPT_DOORBELL
195905. BOOKE_INTERRUPT_DOORBELL_CRITICAL
195906. BOOKE_INTERRUPT_DTLB_MISS
195907. BOOKE_INTERRUPT_EXTERNAL
195908. BOOKE_INTERRUPT_FIT
195909. BOOKE_INTERRUPT_FP_UNAVAIL
195910. BOOKE_INTERRUPT_GUEST_DBELL
195911. BOOKE_INTERRUPT_GUEST_DBELL_CRIT
195912. BOOKE_INTERRUPT_HV_PRIV
195913. BOOKE_INTERRUPT_HV_SYSCALL
195914. BOOKE_INTERRUPT_INST_STORAGE
195915. BOOKE_INTERRUPT_ITLB_MISS
195916. BOOKE_INTERRUPT_LRAT_ERROR
195917. BOOKE_INTERRUPT_MACHINE_CHECK
195918. BOOKE_INTERRUPT_PERFORMANCE_MONITOR
195919. BOOKE_INTERRUPT_PROGRAM
195920. BOOKE_INTERRUPT_SPE_FP_DATA
195921. BOOKE_INTERRUPT_SPE_FP_ROUND
195922. BOOKE_INTERRUPT_SPE_UNAVAIL
195923. BOOKE_INTERRUPT_SYSCALL
195924. BOOKE_INTERRUPT_WATCHDOG
195925. BOOKE_IRQMASK_CE
195926. BOOKE_IRQMASK_EE
195927. BOOKE_IRQPRIO_ALIGNMENT
195928. BOOKE_IRQPRIO_ALTIVEC_ASSIST
195929. BOOKE_IRQPRIO_ALTIVEC_UNAVAIL
195930. BOOKE_IRQPRIO_AP_UNAVAIL
195931. BOOKE_IRQPRIO_CRITICAL
195932. BOOKE_IRQPRIO_DATA_STORAGE
195933. BOOKE_IRQPRIO_DBELL
195934. BOOKE_IRQPRIO_DBELL_CRIT
195935. BOOKE_IRQPRIO_DEBUG
195936. BOOKE_IRQPRIO_DECREMENTER
195937. BOOKE_IRQPRIO_DTLB_MISS
195938. BOOKE_IRQPRIO_EXTERNAL
195939. BOOKE_IRQPRIO_EXTERNAL_LEVEL
195940. BOOKE_IRQPRIO_FIT
195941. BOOKE_IRQPRIO_FP_UNAVAIL
195942. BOOKE_IRQPRIO_INST_STORAGE
195943. BOOKE_IRQPRIO_ITLB_MISS
195944. BOOKE_IRQPRIO_MACHINE_CHECK
195945. BOOKE_IRQPRIO_MAX
195946. BOOKE_IRQPRIO_PERFORMANCE_MONITOR
195947. BOOKE_IRQPRIO_PROGRAM
195948. BOOKE_IRQPRIO_SPE_FP_DATA
195949. BOOKE_IRQPRIO_SPE_FP_ROUND
195950. BOOKE_IRQPRIO_SPE_UNAVAIL
195951. BOOKE_IRQPRIO_SYSCALL
195952. BOOKE_IRQPRIO_WATCHDOG
195953. BOOKE_LOAD_EXC_LEVEL_STACK
195954. BOOL
195955. BOOLEAN
195956. BOOL_DIR_NAME
195957. BOOL_FROM_REG
195958. BOOL_TO_REG
195959. BOOL_TO_STR
195960. BOOMERANG_TOTAL_SIZE
195961. BOOST_BOOST_CON
195962. BOOST_BUSY_STATE
195963. BOOST_CLK_CON
195964. BOOST_DPM_LEVEL
195965. BOOST_ENABLED
195966. BOOST_FSM_STATUS
195967. BOOST_HIGH_PERF_CNT0
195968. BOOST_HIGH_PERF_CNT1
195969. BOOST_HW_PWR_EN
195970. BOOST_HW_PWR_EN_MASK
195971. BOOST_ILMIN_100MA
195972. BOOST_ILMIN_125MA
195973. BOOST_ILMIN_150MA
195974. BOOST_ILMIN_175MA
195975. BOOST_ILMIN_200MA
195976. BOOST_ILMIN_225MA
195977. BOOST_ILMIN_250MA
195978. BOOST_ILMIN_75MA
195979. BOOST_ILMIN_MASK
195980. BOOST_LOW_FREQ_EN_MASK
195981. BOOST_LOW_FREQ_EN_SHIFT
195982. BOOST_OVP_DISABLED
195983. BOOST_PLL_H_CON
195984. BOOST_PLL_L_CON
195985. BOOST_RECOVERY_MASK
195986. BOOST_RECOVERY_SHIFT
195987. BOOST_SHORT_SWITCH_CNT
195988. BOOST_STATIS_THRESHOLD
195989. BOOST_SWITCH_CNT
195990. BOOST_SWITCH_THRESHOLD
195991. BOOST_SW_CTRL_MASK
195992. BOOST_SW_CTRL_SHIFT
195993. BOOT
195994. BOOTADDR
195995. BOOTADDR_M
195996. BOOTCONFIG
195997. BOOTFMS_MARK
195998. BOOTINFOV_MAGIC
195999. BOOTLD_START
196000. BOOTLOADER_BOOT_VECTOR
196001. BOOTLOADER_CW1X60
196002. BOOTLOADER_PARTITION
196003. BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR
196004. BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR
196005. BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR
196006. BOOTLOADER_PCI_READ_DESC_ADDR
196007. BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN
196008. BOOTLOADER_PRIV_DATA_BASE
196009. BOOTLOADER_SCRATCH_SIZE
196010. BOOTLUT_RESET_VECT
196011. BOOTME_DEBUG
196012. BOOTP_REPLY
196013. BOOTP_REQUEST
196014. BOOTROM_ADDRESS
196015. BOOTROM_BASE
196016. BOOTROM_OFFSET
196017. BOOTROM_SIZE
196018. BOOTSTATE_AV7110_BOOT_COMPLETE
196019. BOOTSTATE_BUFFER_EMPTY
196020. BOOTSTATE_BUFFER_FULL
196021. BOOTSTRAP_WORDS
196022. BOOTUP_MODE
196023. BOOTUP_MODE_INFO
196024. BOOTUP_PARAMS_REQUEST
196025. BOOTWP_MARK
196026. BOOTX_COLORTABLE_SIZE
196027. BOOT_0
196028. BOOT_1
196029. BOOT_10
196030. BOOT_11
196031. BOOT_12
196032. BOOT_13
196033. BOOT_14
196034. BOOT_15
196035. BOOT_16
196036. BOOT_17
196037. BOOT_18
196038. BOOT_2
196039. BOOT_3
196040. BOOT_4
196041. BOOT_5
196042. BOOT_6
196043. BOOT_7
196044. BOOT_8
196045. BOOT_8PSK
196046. BOOT_9
196047. BOOT_ACPI
196048. BOOT_ADDR
196049. BOOT_ADDR_CPUID_MASK
196050. BOOT_ARCH_NUBUS
196051. BOOT_ARCH_NUBUS_PDM
196052. BOOT_ARCH_NUBUS_PERFORMA
196053. BOOT_ARCH_NUBUS_POWERBOOK
196054. BOOT_ARCH_PCI
196055. BOOT_BIOS
196056. BOOT_BITOPS_H
196057. BOOT_BL_DOWNLOAD
196058. BOOT_BOOT_H
196059. BOOT_BUF_SIZE
196060. BOOT_BUF_SIZE_OFFSET
196061. BOOT_CAP_RESET_CMD
196062. BOOT_CF9_FORCE
196063. BOOT_CF9_SAFE
196064. BOOT_CFG_REV1
196065. BOOT_CFG_VLAN
196066. BOOT_CMD_FW_BY_USB
196067. BOOT_CMD_FW_IN_EEPROM
196068. BOOT_CMD_MAGIC_NUMBER
196069. BOOT_CMD_REG
196070. BOOT_CMD_RESP_FAIL
196071. BOOT_CMD_RESP_NOT_SUPPORTED
196072. BOOT_CMD_RESP_OK
196073. BOOT_CMD_UPDATE_BOOT2
196074. BOOT_CMD_UPDATE_FW
196075. BOOT_COMMAND_LINE_SIZE
196076. BOOT_COMPRESSED_DECOMPRESSOR_H
196077. BOOT_COMPRESSED_EBOOT_H
196078. BOOT_COMPRESSED_ERROR_H
196079. BOOT_COMPRESSED_MISC_H
196080. BOOT_COMPRESSED_PAGETABLE_H
196081. BOOT_CONSOLE_HPA_OFFSET
196082. BOOT_CONSOLE_PATH_OFFSET
196083. BOOT_CONSOLE_SPA_OFFSET
196084. BOOT_CPUCACHE_ENTRIES
196085. BOOT_CPUFLAGS_H
196086. BOOT_CPU_MODE_EL1
196087. BOOT_CPU_MODE_EL2
196088. BOOT_CPU_MODE_MISMATCH
196089. BOOT_CPU_READY
196090. BOOT_CTYPE_H
196091. BOOT_DATA
196092. BOOT_DATA_PRESERVED
196093. BOOT_DEF
196094. BOOT_DESC_VER_1
196095. BOOT_DESC_VER_2
196096. BOOT_DONE
196097. BOOT_EFI
196098. BOOT_ENABLE
196099. BOOT_ER
196100. BOOT_ERR
196101. BOOT_EVEC
196102. BOOT_FASTBOOT
196103. BOOT_FLAGS_ERASE
196104. BOOT_FLAG_INIT_CORE
196105. BOOT_FROM_EEPROM
196106. BOOT_FSM_TIMEOUT
196107. BOOT_HEAP_SIZE
196108. BOOT_IMG_SIZE
196109. BOOT_INFO_ADDR
196110. BOOT_INFO_COMPATIBLE_VERSION
196111. BOOT_INFO_IS_COMPATIBLE
196112. BOOT_INFO_IS_V2_COMPATIBLE
196113. BOOT_INFO_IS_V4_COMPATIBLE
196114. BOOT_INFO_VERSION
196115. BOOT_INIT_PGT_SIZE
196116. BOOT_KBD
196117. BOOT_KERNEL
196118. BOOT_LOADER_DIMM_STATUS
196119. BOOT_LOADER_EXPORT_H_
196120. BOOT_LOGIN_RESP_TOV
196121. BOOT_MAGIC
196122. BOOT_MAGIC_LIST_END
196123. BOOT_MAGIC_WORD
196124. BOOT_MEM_INIT_RAM
196125. BOOT_MEM_NOMAP
196126. BOOT_MEM_RAM
196127. BOOT_MEM_RESERVED
196128. BOOT_MEM_ROM_DATA
196129. BOOT_MODE_MASK
196130. BOOT_NMI_HANDLER
196131. BOOT_NMI_LOCK
196132. BOOT_NORMAL
196133. BOOT_NVEC
196134. BOOT_PARAMS_SIZE
196135. BOOT_PARAM_OFFSET_PORT0
196136. BOOT_PARAM_OFFSET_PORT1
196137. BOOT_PARAM_PRESERVE
196138. BOOT_PARTITION_SIZE_KiB
196139. BOOT_PCB
196140. BOOT_PERCPU_OFFSET
196141. BOOT_PGT_SIZE
196142. BOOT_PLL_2TO1_MODE
196143. BOOT_PLL_ASYNC_MODE
196144. BOOT_PLL_BYPASS
196145. BOOT_PLL_SOURCE_AFE
196146. BOOT_PLL_SOURCE_BUS
196147. BOOT_PLL_SOURCE_CPU
196148. BOOT_PLL_SOURCE_MASK
196149. BOOT_PLL_SOURCE_REF
196150. BOOT_PLL_SOURCE_XTAL
196151. BOOT_PW1
196152. BOOT_PW1_REG
196153. BOOT_PW2
196154. BOOT_PW2_REG
196155. BOOT_RECOVERY
196156. BOOT_REG
196157. BOOT_REG_BASE
196158. BOOT_RVEC
196159. BOOT_SEL0
196160. BOOT_SEL1
196161. BOOT_SEL2
196162. BOOT_SEQ_DONE
196163. BOOT_SERVICES
196164. BOOT_SIG
196165. BOOT_SIZE
196166. BOOT_SRC_NOR
196167. BOOT_STACK_ORDER
196168. BOOT_STACK_SIZE
196169. BOOT_STATUS_REG
196170. BOOT_STRING_H
196171. BOOT_THREAD_MODE
196172. BOOT_TIME_DELAY_MS
196173. BOOT_TO_EXECUTE
196174. BOOT_TO_EXECUTEOK
196175. BOOT_TRIPLE
196176. BOOT_VEC
196177. BOOT_VESA_H
196178. BOOT_VIDEO_H
196179. BOP_DEC
196180. BOP_INC
196181. BORDB
196182. BORDG
196183. BORDR
196184. BOSCH_C_CAN
196185. BOSCH_C_CAN_PLATFORM
196186. BOSCH_D_CAN
196187. BOSTON_CLK_COUNT
196188. BOSTON_CLK_CPU
196189. BOSTON_CLK_INPUT
196190. BOSTON_CLK_SYS
196191. BOSTON_PLAT_MMCMDIV
196192. BOSTON_PLAT_MMCMDIV_CLK0DIV
196193. BOSTON_PLAT_MMCMDIV_CLK1DIV
196194. BOSTON_PLAT_MMCMDIV_INPUT
196195. BOSTON_PLAT_MMCMDIV_MUL
196196. BOS_ATTR
196197. BOS_ATTR_BLOCK_SIZE_MASK_
196198. BOT
196199. BOTH
196200. BOTHEDGE
196201. BOTHER
196202. BOTH_BYTES
196203. BOTH_DIR
196204. BOTH_EADGE
196205. BOTH_EDGES
196206. BOTH_EMPTY
196207. BOTH_EYE
196208. BOTH_PRmn
196209. BOTH_QUERY_CONFIG
196210. BOTH_TIME_SET
196211. BOTM4
196212. BOTP
196213. BOTP4
196214. BOTTOMUP
196215. BOTTOM_CLIP
196216. BOTTOM_EDGE
196217. BOTTOM_END_POINT_DETECTION_LEVEL
196218. BOTTOM_OF_PIPE_TS
196219. BOTTOM_TO_TOP
196220. BOTTOM_UP_HEIGHT
196221. BOU
196222. BOUNCE_BUFFER_ORDER
196223. BOUNCE_BUFFER_SIZE
196224. BOUNCE_POLL
196225. BOUNCE_RACINGFAULTS
196226. BOUNCE_RANDOM
196227. BOUNCE_SIZE
196228. BOUNCE_VERIFY
196229. BOUNDARY_MULTI_CACHELINE
196230. BOUNDARY_OK
196231. BOUNDARY_SINGLE_CACHELINE
196232. BO_0_MASK
196233. BO_1_MASK
196234. BO_INVALID_FLAGS
196235. BO_LOCKED
196236. BO_MASK
196237. BO_PINNED
196238. BO_SHIFT
196239. BO_VALID
196240. BO_VM_ALL
196241. BO_VM_MAPPED
196242. BO_VM_NOT_MAPPED
196243. BP
196244. BPADDR
196245. BPAEND
196246. BPAR
196247. BPASTART
196248. BPC0A
196249. BPC0_BPU0
196250. BPC0_BPU1
196251. BPC0_BPU2
196252. BPC0_BPU3
196253. BPC0_BYPASS
196254. BPC0_COLOR
196255. BPC0_DPF
196256. BPC0_ECSENA
196257. BPC0_ERSY
196258. BPC0_GAUD
196259. BPC0_HAM
196260. BPC0_HIRES
196261. BPC0_LACE
196262. BPC0_LPEN
196263. BPC0_SHRES
196264. BPC0_UHRES
196265. BPC1
196266. BPC1A
196267. BPC2_KILLEHB
196268. BPC2_PF1P0
196269. BPC2_PF1P1
196270. BPC2_PF1P2
196271. BPC2_PF2P0
196272. BPC2_PF2P1
196273. BPC2_PF2P2
196274. BPC2_PF2PRI
196275. BPC2_RDRAM
196276. BPC2_SOGEN
196277. BPC2_ZDBPEN
196278. BPC2_ZDBPSEL0
196279. BPC2_ZDBPSEL1
196280. BPC2_ZDBPSEL2
196281. BPC2_ZDCTEN
196282. BPC3_BANK0
196283. BPC3_BANK1
196284. BPC3_BANK2
196285. BPC3_BRDRBLNK
196286. BPC3_BRDRSPRT
196287. BPC3_BRDRTRAN
196288. BPC3_EXTBLKEN
196289. BPC3_LOCT
196290. BPC3_PF2OF0
196291. BPC3_PF2OF1
196292. BPC3_PF2OF2
196293. BPC3_SPRES0
196294. BPC3_SPRES1
196295. BPC3_ZDCLKEN
196296. BPC4A
196297. BPC4_BPLAM0
196298. BPC4_BPLAM1
196299. BPC4_BPLAM2
196300. BPC4_BPLAM3
196301. BPC4_BPLAM4
196302. BPC4_BPLAM5
196303. BPC4_BPLAM6
196304. BPC4_BPLAM7
196305. BPC4_ESPRM4
196306. BPC4_ESPRM5
196307. BPC4_ESPRM6
196308. BPC4_ESPRM7
196309. BPC4_OSPRM4
196310. BPC4_OSPRM5
196311. BPC4_OSPRM6
196312. BPC4_OSPRM7
196313. BPC5
196314. BPC6
196315. BPC6A
196316. BPC8
196317. BPC8A
196318. BPCID_mskCID
196319. BPCID_offCID
196320. BPCI_CFGADDR_BUSNUM_SHF
196321. BPCI_CFGADDR_ENABLE
196322. BPCI_CFGADDR_FUNCTNUM_SHF
196323. BPCI_CFGADDR_REGNUM_SHF
196324. BPCI_IFCONTROL_BIST
196325. BPCI_IFCONTROL_CAP
196326. BPCI_IFCONTROL_CTO_SHF
196327. BPCI_IFCONTROL_HCE
196328. BPCI_IFCONTROL_MMC_SHF
196329. BPCI_IFCONTROL_RTO
196330. BPCI_IFCONTROL_SE
196331. BPCI_IFSTATUS_ARB
196332. BPCI_IFSTATUS_BADD
196333. BPCI_IFSTATUS_BC0F
196334. BPCI_IFSTATUS_BC1F
196335. BPCI_IFSTATUS_BSIZ
196336. BPCI_IFSTATUS_LCA
196337. BPCI_IFSTATUS_MA
196338. BPCI_IFSTATUS_MEM
196339. BPCI_IFSTATUS_MGT
196340. BPCI_IFSTATUS_MRT
196341. BPCI_IFSTATUS_MTT
196342. BPCI_IFSTATUS_PCIU
196343. BPCI_IFSTATUS_PEI
196344. BPCI_IFSTATUS_PER
196345. BPCI_IFSTATUS_PET
196346. BPCI_IFSTATUS_RTO
196347. BPCI_IFSTATUS_SER
196348. BPCI_IFSTATUS_STA
196349. BPCI_IFSTATUS_TA
196350. BPCI_RESETCTL_CT
196351. BPCI_RESETCTL_HM
196352. BPCI_RESETCTL_PE
196353. BPCI_RESETCTL_PR
196354. BPCI_RESETCTL_RI
196355. BPCI_RESETCTL_RT
196356. BPCK_VERSION
196357. BPCMD_BPDNE
196358. BPCMD_EBPRD
196359. BPCMD_EBPWR
196360. BPCR_AHBP
196361. BPCR_AVBP
196362. BPC_10
196363. BPC_12
196364. BPC_6
196365. BPC_8
196366. BPC_mskBE0
196367. BPC_mskBE1
196368. BPC_mskBE2
196369. BPC_mskBE3
196370. BPC_mskC
196371. BPC_mskEL
196372. BPC_mskP
196373. BPC_mskS
196374. BPC_mskT
196375. BPC_mskWP
196376. BPC_offBE0
196377. BPC_offBE1
196378. BPC_offBE2
196379. BPC_offBE3
196380. BPC_offC
196381. BPC_offEL
196382. BPC_offP
196383. BPC_offS
196384. BPC_offT
196385. BPC_offWP
196386. BPDATA
196387. BPDIV
196388. BPDU_TYPE_CONFIG
196389. BPDU_TYPE_TCN
196390. BPD_OPTION
196391. BPD_TH
196392. BPD_TH_OPT2
196393. BPEN
196394. BPENTER
196395. BPERDMAP
196396. BPEXIT
196397. BPFCLK_A_MARK
196398. BPFCLK_B_MARK
196399. BPFCLK_C_MARK
196400. BPFCLK_D_MARK
196401. BPFCLK_E_MARK
196402. BPFCLK_F_MARK
196403. BPFCLK_G_MARK
196404. BPFCLK_MARK
196405. BPFILTER_IPT_GET_MAX
196406. BPFILTER_IPT_SET_MAX
196407. BPFILTER_IPT_SO_GET_ENTRIES
196408. BPFILTER_IPT_SO_GET_INFO
196409. BPFILTER_IPT_SO_GET_REVISION_MATCH
196410. BPFILTER_IPT_SO_GET_REVISION_TARGET
196411. BPFILTER_IPT_SO_SET_ADD_COUNTERS
196412. BPFILTER_IPT_SO_SET_REPLACE
196413. BPFMD_MASK
196414. BPF_A
196415. BPF_ABS
196416. BPF_ADD
196417. BPF_ADJ_ROOM_ENCAP_L2_MASK
196418. BPF_ADJ_ROOM_ENCAP_L2_SHIFT
196419. BPF_ADJ_ROOM_MAC
196420. BPF_ADJ_ROOM_NET
196421. BPF_ALU
196422. BPF_ALU32_IMM
196423. BPF_ALU32_REG
196424. BPF_ALU64
196425. BPF_ALU64_IMM
196426. BPF_ALU64_REG
196427. BPF_ALU_ADD
196428. BPF_ALU_AND
196429. BPF_ALU_DIV
196430. BPF_ALU_LSH
196431. BPF_ALU_MOD
196432. BPF_ALU_MUL
196433. BPF_ALU_NEG
196434. BPF_ALU_NEG_VALUE
196435. BPF_ALU_NON_POINTER
196436. BPF_ALU_OR
196437. BPF_ALU_RSH
196438. BPF_ALU_SANITIZE
196439. BPF_ALU_SANITIZE_DST
196440. BPF_ALU_SANITIZE_SRC
196441. BPF_ALU_SUB
196442. BPF_ALU_XOR
196443. BPF_ANC
196444. BPF_ANCILLARY
196445. BPF_AND
196446. BPF_ANNOTATE_KV_PAIR
196447. BPF_ANY
196448. BPF_APROG_COMPAT
196449. BPF_APROG_SEC
196450. BPF_ARSH
196451. BPF_ATTACH_FAIL
196452. BPF_AX_HI
196453. BPF_AX_LO
196454. BPF_B
196455. BPF_BTF_GET_FD_BY_ID
196456. BPF_BTF_GET_FD_BY_ID_LAST_FIELD
196457. BPF_BTF_GET_NEXT_ID
196458. BPF_BTF_LOAD
196459. BPF_BTF_LOAD_LAST_FIELD
196460. BPF_BUILD_ID
196461. BPF_BUILD_ID_SIZE
196462. BPF_CALL
196463. BPF_CALL_0
196464. BPF_CALL_1
196465. BPF_CALL_2
196466. BPF_CALL_3
196467. BPF_CALL_4
196468. BPF_CALL_5
196469. BPF_CALL_ARGS
196470. BPF_CALL_REL
196471. BPF_CALL_x
196472. BPF_CAST_CALL
196473. BPF_CGROUP_DEVICE
196474. BPF_CGROUP_GETSOCKOPT
196475. BPF_CGROUP_GETSOCKOPT_MAX_OPTLEN
196476. BPF_CGROUP_INET4_BIND
196477. BPF_CGROUP_INET4_CONNECT
196478. BPF_CGROUP_INET4_POST_BIND
196479. BPF_CGROUP_INET6_BIND
196480. BPF_CGROUP_INET6_CONNECT
196481. BPF_CGROUP_INET6_POST_BIND
196482. BPF_CGROUP_INET_EGRESS
196483. BPF_CGROUP_INET_INGRESS
196484. BPF_CGROUP_INET_SOCK_CREATE
196485. BPF_CGROUP_MAX_PROGS
196486. BPF_CGROUP_PRE_CONNECT_ENABLED
196487. BPF_CGROUP_RUN_PROG_DEVICE_CGROUP
196488. BPF_CGROUP_RUN_PROG_GETSOCKOPT
196489. BPF_CGROUP_RUN_PROG_INET4_BIND
196490. BPF_CGROUP_RUN_PROG_INET4_CONNECT
196491. BPF_CGROUP_RUN_PROG_INET4_CONNECT_LOCK
196492. BPF_CGROUP_RUN_PROG_INET4_POST_BIND
196493. BPF_CGROUP_RUN_PROG_INET6_BIND
196494. BPF_CGROUP_RUN_PROG_INET6_CONNECT
196495. BPF_CGROUP_RUN_PROG_INET6_CONNECT_LOCK
196496. BPF_CGROUP_RUN_PROG_INET6_POST_BIND
196497. BPF_CGROUP_RUN_PROG_INET_EGRESS
196498. BPF_CGROUP_RUN_PROG_INET_INGRESS
196499. BPF_CGROUP_RUN_PROG_INET_SOCK
196500. BPF_CGROUP_RUN_PROG_SETSOCKOPT
196501. BPF_CGROUP_RUN_PROG_SOCK_OPS
196502. BPF_CGROUP_RUN_PROG_SYSCTL
196503. BPF_CGROUP_RUN_PROG_UDP4_RECVMSG_LOCK
196504. BPF_CGROUP_RUN_PROG_UDP4_SENDMSG_LOCK
196505. BPF_CGROUP_RUN_PROG_UDP6_RECVMSG_LOCK
196506. BPF_CGROUP_RUN_PROG_UDP6_SENDMSG_LOCK
196507. BPF_CGROUP_RUN_SA_PROG
196508. BPF_CGROUP_RUN_SA_PROG_LOCK
196509. BPF_CGROUP_RUN_SK_PROG
196510. BPF_CGROUP_SETSOCKOPT
196511. BPF_CGROUP_SOCK_OPS
196512. BPF_CGROUP_STORAGE_PERCPU
196513. BPF_CGROUP_STORAGE_SHARED
196514. BPF_CGROUP_SYSCTL
196515. BPF_CGROUP_UDP4_RECVMSG
196516. BPF_CGROUP_UDP4_SENDMSG
196517. BPF_CGROUP_UDP6_RECVMSG
196518. BPF_CGROUP_UDP6_SENDMSG
196519. BPF_CLASS
196520. BPF_COMPLEXITY_LIMIT_INSNS
196521. BPF_COMPLEXITY_LIMIT_JMP_SEQ
196522. BPF_COMPLEXITY_LIMIT_STATES
196523. BPF_CORE_READ
196524. BPF_CORE_SPEC_MAX_LEN
196525. BPF_DECLARE_PERCPU
196526. BPF_DEVCG_ACC_MKNOD
196527. BPF_DEVCG_ACC_READ
196528. BPF_DEVCG_ACC_WRITE
196529. BPF_DEVCG_DEV_BLOCK
196530. BPF_DEVCG_DEV_CHAR
196531. BPF_DIRECT_PKT_R2
196532. BPF_DIV
196533. BPF_DROP
196534. BPF_DW
196535. BPF_EAPROG_SEC
196536. BPF_EMIT_CALL
196537. BPF_EMIT_JMP
196538. BPF_END
196539. BPF_ENDIAN
196540. BPF_EXIST
196541. BPF_EXIT
196542. BPF_EXIT_INSN
196543. BPF_FD_TYPE_KPROBE
196544. BPF_FD_TYPE_KRETPROBE
196545. BPF_FD_TYPE_RAW_TRACEPOINT
196546. BPF_FD_TYPE_TRACEPOINT
196547. BPF_FD_TYPE_UPROBE
196548. BPF_FD_TYPE_URETPROBE
196549. BPF_FIB_LKUP_RET_BLACKHOLE
196550. BPF_FIB_LKUP_RET_FRAG_NEEDED
196551. BPF_FIB_LKUP_RET_FWD_DISABLED
196552. BPF_FIB_LKUP_RET_NOT_FWDED
196553. BPF_FIB_LKUP_RET_NO_NEIGH
196554. BPF_FIB_LKUP_RET_PROHIBIT
196555. BPF_FIB_LKUP_RET_SUCCESS
196556. BPF_FIB_LKUP_RET_UNREACHABLE
196557. BPF_FIB_LKUP_RET_UNSUPP_LWT
196558. BPF_FIB_LOOKUP_DIRECT
196559. BPF_FIB_LOOKUP_OUTPUT
196560. BPF_FIELD_SIZEOF
196561. BPF_FLOW_DISSECTOR
196562. BPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG
196563. BPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP
196564. BPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL
196565. BPF_FP_HI
196566. BPF_FP_LO
196567. BPF_FROM_BE
196568. BPF_FROM_LE
196569. BPF_FS_MAGIC
196570. BPF_FUNC_map_lookup_elem
196571. BPF_FUNC_map_update_elem
196572. BPF_F_ACCESS_MASK
196573. BPF_F_ADJ_ROOM_ENCAP_L2
196574. BPF_F_ADJ_ROOM_ENCAP_L3_IPV4
196575. BPF_F_ADJ_ROOM_ENCAP_L3_IPV6
196576. BPF_F_ADJ_ROOM_ENCAP_L3_MASK
196577. BPF_F_ADJ_ROOM_ENCAP_L4_GRE
196578. BPF_F_ADJ_ROOM_ENCAP_L4_UDP
196579. BPF_F_ADJ_ROOM_FIXED_GSO
196580. BPF_F_ADJ_ROOM_MASK
196581. BPF_F_ALLOW_MULTI
196582. BPF_F_ALLOW_OVERRIDE
196583. BPF_F_ANY_ALIGNMENT
196584. BPF_F_ATTACH_MASK
196585. BPF_F_CLONE
196586. BPF_F_CTXLEN_MASK
196587. BPF_F_CURRENT_CPU
196588. BPF_F_CURRENT_NETNS
196589. BPF_F_DONT_FRAGMENT
196590. BPF_F_FAST_STACK_CMP
196591. BPF_F_GET
196592. BPF_F_HDR_FIELD_MASK
196593. BPF_F_INDEX_MASK
196594. BPF_F_INGRESS
196595. BPF_F_INVALIDATE_HASH
196596. BPF_F_KEY
196597. BPF_F_KEY_VAL
196598. BPF_F_LOCK
196599. BPF_F_MARK_ENFORCE
196600. BPF_F_MARK_MANGLED_0
196601. BPF_F_NO_COMMON_LRU
196602. BPF_F_NO_PREALLOC
196603. BPF_F_NUMA_NODE
196604. BPF_F_PIN
196605. BPF_F_PIN_GET
196606. BPF_F_PSEUDO_HDR
196607. BPF_F_QUERY_EFFECTIVE
196608. BPF_F_RDONLY
196609. BPF_F_RDONLY_PROG
196610. BPF_F_RECOMPUTE_CSUM
196611. BPF_F_REUSE_STACKID
196612. BPF_F_SEQ_NUMBER
196613. BPF_F_SKIP_FIELD_MASK
196614. BPF_F_STACK_BUILD_ID
196615. BPF_F_STRICT_ALIGNMENT
196616. BPF_F_SYSCTL_BASE_NAME
196617. BPF_F_TEST_RND_HI32
196618. BPF_F_TEST_STATE_FREQ
196619. BPF_F_TUNINFO_IPV6
196620. BPF_F_USER_BUILD_ID
196621. BPF_F_USER_STACK
196622. BPF_F_VAL
196623. BPF_F_WRONLY
196624. BPF_F_WRONLY_PROG
196625. BPF_F_ZERO_CSUM_TX
196626. BPF_F_ZERO_SEED
196627. BPF_H
196628. BPF_HDR_START_MAC
196629. BPF_HDR_START_NET
196630. BPF_HELPER_MAKE_ENTRY
196631. BPF_IMM
196632. BPF_IND
196633. BPF_INET_SOCK_GET_COMMON
196634. BPF_INSN_2_LBL
196635. BPF_INSN_2_TBL
196636. BPF_INSN_3_LBL
196637. BPF_INSN_3_TBL
196638. BPF_INSN_MAP
196639. BPF_INSN_SAFETY
196640. BPF_JA
196641. BPF_JEQ
196642. BPF_JGE
196643. BPF_JGT
196644. BPF_JIT_MIPS_OP_H
196645. BPF_JIT_REGION_END
196646. BPF_JIT_REGION_SIZE
196647. BPF_JIT_REGION_START
196648. BPF_JIT_SCRATCH_REGS
196649. BPF_JLE
196650. BPF_JLT
196651. BPF_JMP
196652. BPF_JMP32
196653. BPF_JMP32_IMM
196654. BPF_JMP32_REG
196655. BPF_JMP_A
196656. BPF_JMP_IMM
196657. BPF_JMP_JA
196658. BPF_JMP_JEQ
196659. BPF_JMP_JGE
196660. BPF_JMP_JGT
196661. BPF_JMP_JSET
196662. BPF_JMP_REG
196663. BPF_JNE
196664. BPF_JSET
196665. BPF_JSGE
196666. BPF_JSGT
196667. BPF_JSLE
196668. BPF_JSLT
196669. BPF_JUMP
196670. BPF_K
196671. BPF_KPROBE_READ_RET_IP
196672. BPF_KRETPROBE_READ_RET_IP
196673. BPF_LABELS_MAX
196674. BPF_LD
196675. BPF_LDST_BYTES
196676. BPF_LDX
196677. BPF_LDX_B
196678. BPF_LDX_MEM
196679. BPF_LDX_W
196680. BPF_LD_ABS
196681. BPF_LD_B
196682. BPF_LD_H
196683. BPF_LD_IMM64
196684. BPF_LD_IMM64_RAW
196685. BPF_LD_IMM64_RAW_FULL
196686. BPF_LD_IND
196687. BPF_LD_MAP_FD
196688. BPF_LD_MAP_VALUE
196689. BPF_LD_W
196690. BPF_LEN
196691. BPF_LINE_INFO_ENC
196692. BPF_LINE_INFO_LINE_COL
196693. BPF_LINE_INFO_LINE_NUM
196694. BPF_LIRC_MODE2
196695. BPF_LL_OFF
196696. BPF_LOADER_ERRNO__COMPILE
196697. BPF_LOADER_ERRNO__CONFIG
196698. BPF_LOADER_ERRNO__EVENTNAME
196699. BPF_LOADER_ERRNO__GROUP
196700. BPF_LOADER_ERRNO__INTERNAL
196701. BPF_LOADER_ERRNO__OBJCONF_CONF
196702. BPF_LOADER_ERRNO__OBJCONF_MAP_EVTDIM
196703. BPF_LOADER_ERRNO__OBJCONF_MAP_EVTINH
196704. BPF_LOADER_ERRNO__OBJCONF_MAP_EVTTYPE
196705. BPF_LOADER_ERRNO__OBJCONF_MAP_IDX2BIG
196706. BPF_LOADER_ERRNO__OBJCONF_MAP_KEYSIZE
196707. BPF_LOADER_ERRNO__OBJCONF_MAP_MAPSIZE
196708. BPF_LOADER_ERRNO__OBJCONF_MAP_NOEVT
196709. BPF_LOADER_ERRNO__OBJCONF_MAP_NOTEXIST
196710. BPF_LOADER_ERRNO__OBJCONF_MAP_OPT
196711. BPF_LOADER_ERRNO__OBJCONF_MAP_TYPE
196712. BPF_LOADER_ERRNO__OBJCONF_MAP_VALUE
196713. BPF_LOADER_ERRNO__OBJCONF_MAP_VALUESIZE
196714. BPF_LOADER_ERRNO__OBJCONF_OPT
196715. BPF_LOADER_ERRNO__PROGCONF_TERM
196716. BPF_LOADER_ERRNO__PROLOGUE
196717. BPF_LOADER_ERRNO__PROLOGUE2BIG
196718. BPF_LOADER_ERRNO__PROLOGUEOOB
196719. BPF_LOCAL_LIST_T_OFFSET
196720. BPF_LOG_BUF_SIZE
196721. BPF_LOG_LEVEL
196722. BPF_LOG_LEVEL1
196723. BPF_LOG_LEVEL2
196724. BPF_LOG_MASK
196725. BPF_LOG_STATS
196726. BPF_LRU_LIST_T_ACTIVE
196727. BPF_LRU_LIST_T_FREE
196728. BPF_LRU_LIST_T_INACTIVE
196729. BPF_LRU_LOCAL_LIST_T_FREE
196730. BPF_LRU_LOCAL_LIST_T_PENDING
196731. BPF_LSH
196732. BPF_LWT_ENCAP_IP
196733. BPF_LWT_ENCAP_SEG6
196734. BPF_LWT_ENCAP_SEG6_INLINE
196735. BPF_LWT_REROUTE
196736. BPF_MAIN_FUNC
196737. BPF_MAJOR_VERSION
196738. BPF_MAP_CAN_READ
196739. BPF_MAP_CAN_WRITE
196740. BPF_MAP_CREATE
196741. BPF_MAP_CREATE_LAST_FIELD
196742. BPF_MAP_DELETE_ELEM
196743. BPF_MAP_DELETE_ELEM_LAST_FIELD
196744. BPF_MAP_FREEZE
196745. BPF_MAP_FREEZE_LAST_FIELD
196746. BPF_MAP_GET_FD_BY_ID
196747. BPF_MAP_GET_FD_BY_ID_LAST_FIELD
196748. BPF_MAP_GET_NEXT_ID
196749. BPF_MAP_GET_NEXT_KEY
196750. BPF_MAP_GET_NEXT_KEY_LAST_FIELD
196751. BPF_MAP_KEY_ALL
196752. BPF_MAP_KEY_RANGES
196753. BPF_MAP_LOOKUP_AND_DELETE_ELEM
196754. BPF_MAP_LOOKUP_AND_DELETE_ELEM_LAST_FIELD
196755. BPF_MAP_LOOKUP_ELEM
196756. BPF_MAP_LOOKUP_ELEM_LAST_FIELD
196757. BPF_MAP_OP_SET_EVSEL
196758. BPF_MAP_OP_SET_VALUE
196759. BPF_MAP_PTR
196760. BPF_MAP_PTR_POISON
196761. BPF_MAP_PTR_UNPRIV
196762. BPF_MAP_TYPE
196763. BPF_MAP_TYPE_ARRAY
196764. BPF_MAP_TYPE_ARRAY_OF_MAPS
196765. BPF_MAP_TYPE_CGROUP_ARRAY
196766. BPF_MAP_TYPE_CGROUP_STORAGE
196767. BPF_MAP_TYPE_CPUMAP
196768. BPF_MAP_TYPE_DEVMAP
196769. BPF_MAP_TYPE_DEVMAP_HASH
196770. BPF_MAP_TYPE_HASH
196771. BPF_MAP_TYPE_HASH_OF_MAPS
196772. BPF_MAP_TYPE_LPM_TRIE
196773. BPF_MAP_TYPE_LRU_HASH
196774. BPF_MAP_TYPE_LRU_PERCPU_HASH
196775. BPF_MAP_TYPE_PERCPU_ARRAY
196776. BPF_MAP_TYPE_PERCPU_CGROUP_STORAGE
196777. BPF_MAP_TYPE_PERCPU_HASH
196778. BPF_MAP_TYPE_PERF_EVENT_ARRAY
196779. BPF_MAP_TYPE_PROG_ARRAY
196780. BPF_MAP_TYPE_QUEUE
196781. BPF_MAP_TYPE_REUSEPORT_SOCKARRAY
196782. BPF_MAP_TYPE_SK_STORAGE
196783. BPF_MAP_TYPE_SOCKHASH
196784. BPF_MAP_TYPE_SOCKMAP
196785. BPF_MAP_TYPE_STACK
196786. BPF_MAP_TYPE_STACK_TRACE
196787. BPF_MAP_TYPE_UNSPEC
196788. BPF_MAP_TYPE_XSKMAP
196789. BPF_MAP_UPDATE_ELEM
196790. BPF_MAP_UPDATE_ELEM_LAST_FIELD
196791. BPF_MAXINSNS
196792. BPF_MAX_INSN_SIZE
196793. BPF_MAX_PROGS
196794. BPF_MAX_REFCNT
196795. BPF_MAX_SUBPROGS
196796. BPF_MAX_VAR_OFF
196797. BPF_MAX_VAR_SIZ
196798. BPF_MEM
196799. BPF_MEMWORDS
196800. BPF_MINOR_VERSION
196801. BPF_MISC
196802. BPF_MISCOP
196803. BPF_MISC_TAX
196804. BPF_MISC_TXA
196805. BPF_MOD
196806. BPF_MODE
196807. BPF_MOV
196808. BPF_MOV32_IMM
196809. BPF_MOV32_RAW
196810. BPF_MOV32_REG
196811. BPF_MOV64_IMM
196812. BPF_MOV64_RAW
196813. BPF_MOV64_REG
196814. BPF_MSH
196815. BPF_MUL
196816. BPF_M_MAP
196817. BPF_M_PROG
196818. BPF_M_UNSPEC
196819. BPF_NEG
196820. BPF_NET_OFF
196821. BPF_NOEXIST
196822. BPF_OBJ_FLAG_MASK
196823. BPF_OBJ_GET
196824. BPF_OBJ_GET_INFO_BY_FD
196825. BPF_OBJ_GET_INFO_BY_FD_LAST_FIELD
196826. BPF_OBJ_GET_NEXT_ID_LAST_FIELD
196827. BPF_OBJ_LAST_FIELD
196828. BPF_OBJ_MAP
196829. BPF_OBJ_NAME_LEN
196830. BPF_OBJ_PIN
196831. BPF_OBJ_PROG
196832. BPF_OBJ_UNKNOWN
196833. BPF_OFFLOAD_MAP_ALLOC
196834. BPF_OFFLOAD_MAP_FREE
196835. BPF_OK
196836. BPF_OP
196837. BPF_OR
196838. BPF_PACKET_HEADER
196839. BPF_PPC_NVR_MIN
196840. BPF_PPC_SLOWPATH_FRAME
196841. BPF_PPC_STACKFRAME
196842. BPF_PPC_STACK_BASIC
196843. BPF_PPC_STACK_LOCALS
196844. BPF_PPC_STACK_R3_OFF
196845. BPF_PPC_STACK_SAVE
196846. BPF_PROG
196847. BPF_PROG_ATTACH
196848. BPF_PROG_ATTACH_LAST_FIELD
196849. BPF_PROG_CGROUP_INET_EGRESS_RUN_ARRAY
196850. BPF_PROG_DETACH
196851. BPF_PROG_DETACH_LAST_FIELD
196852. BPF_PROG_GET_FD_BY_ID
196853. BPF_PROG_GET_FD_BY_ID_LAST_FIELD
196854. BPF_PROG_GET_NEXT_ID
196855. BPF_PROG_INFO_FIRST_ARRAY
196856. BPF_PROG_INFO_FUNC_INFO
196857. BPF_PROG_INFO_JITED_FUNC_LENS
196858. BPF_PROG_INFO_JITED_INSNS
196859. BPF_PROG_INFO_JITED_KSYMS
196860. BPF_PROG_INFO_JITED_LINE_INFO
196861. BPF_PROG_INFO_LAST_ARRAY
196862. BPF_PROG_INFO_LINE_INFO
196863. BPF_PROG_INFO_MAP_IDS
196864. BPF_PROG_INFO_PROG_TAGS
196865. BPF_PROG_INFO_XLATED_INSNS
196866. BPF_PROG_LOAD
196867. BPF_PROG_LOAD_LAST_FIELD
196868. BPF_PROG_QUERY
196869. BPF_PROG_QUERY_LAST_FIELD
196870. BPF_PROG_RUN
196871. BPF_PROG_RUN_ARRAY
196872. BPF_PROG_RUN_ARRAY_CHECK
196873. BPF_PROG_SEC
196874. BPF_PROG_SEC_IMPL
196875. BPF_PROG_TEST_RUN
196876. BPF_PROG_TEST_RUN_LAST_FIELD
196877. BPF_PROG_TYPE
196878. BPF_PROG_TYPE_CGROUP_DEVICE
196879. BPF_PROG_TYPE_CGROUP_SKB
196880. BPF_PROG_TYPE_CGROUP_SOCK
196881. BPF_PROG_TYPE_CGROUP_SOCKOPT
196882. BPF_PROG_TYPE_CGROUP_SOCK_ADDR
196883. BPF_PROG_TYPE_CGROUP_SYSCTL
196884. BPF_PROG_TYPE_FLOW_DISSECTOR
196885. BPF_PROG_TYPE_FNS
196886. BPF_PROG_TYPE_KPROBE
196887. BPF_PROG_TYPE_LIRC_MODE2
196888. BPF_PROG_TYPE_LWT_IN
196889. BPF_PROG_TYPE_LWT_OUT
196890. BPF_PROG_TYPE_LWT_SEG6LOCAL
196891. BPF_PROG_TYPE_LWT_XMIT
196892. BPF_PROG_TYPE_PERF_EVENT
196893. BPF_PROG_TYPE_RAW_TRACEPOINT
196894. BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE
196895. BPF_PROG_TYPE_SCHED_ACT
196896. BPF_PROG_TYPE_SCHED_CLS
196897. BPF_PROG_TYPE_SK_MSG
196898. BPF_PROG_TYPE_SK_REUSEPORT
196899. BPF_PROG_TYPE_SK_SKB
196900. BPF_PROG_TYPE_SOCKET_FILTER
196901. BPF_PROG_TYPE_SOCK_OPS
196902. BPF_PROG_TYPE_TRACEPOINT
196903. BPF_PROG_TYPE_UNSPEC
196904. BPF_PROG_TYPE_XDP
196905. BPF_PROLOGUE_FETCH_RESULT_REG
196906. BPF_PROLOGUE_MAX_ARGS
196907. BPF_PROLOGUE_START_ARG_REG
196908. BPF_PSEUDO_CALL
196909. BPF_PSEUDO_MAP_FD
196910. BPF_PSEUDO_MAP_VALUE
196911. BPF_R0
196912. BPF_R1
196913. BPF_R10
196914. BPF_R2
196915. BPF_R2_HI
196916. BPF_R2_LO
196917. BPF_R3
196918. BPF_R3_HI
196919. BPF_R3_LO
196920. BPF_R4
196921. BPF_R4_HI
196922. BPF_R4_LO
196923. BPF_R5
196924. BPF_R5_HI
196925. BPF_R5_LO
196926. BPF_R6
196927. BPF_R7
196928. BPF_R7_HI
196929. BPF_R7_LO
196930. BPF_R8
196931. BPF_R8_HI
196932. BPF_R8_LO
196933. BPF_R9
196934. BPF_R9_HI
196935. BPF_R9_LO
196936. BPF_RAND_SEXT_R7
196937. BPF_RAND_UEXT_R7
196938. BPF_RAW_INSN
196939. BPF_RAW_TP
196940. BPF_RAW_TRACEPOINT_OPEN
196941. BPF_RAW_TRACEPOINT_OPEN_LAST_FIELD
196942. BPF_READ
196943. BPF_REDIRECT
196944. BPF_REG_0
196945. BPF_REG_1
196946. BPF_REG_10
196947. BPF_REG_2
196948. BPF_REG_3
196949. BPF_REG_4
196950. BPF_REG_5
196951. BPF_REG_6
196952. BPF_REG_7
196953. BPF_REG_8
196954. BPF_REG_9
196955. BPF_REG_A
196956. BPF_REG_ARG1
196957. BPF_REG_ARG2
196958. BPF_REG_ARG3
196959. BPF_REG_ARG4
196960. BPF_REG_ARG5
196961. BPF_REG_AX
196962. BPF_REG_CTX
196963. BPF_REG_D
196964. BPF_REG_FP
196965. BPF_REG_H
196966. BPF_REG_SIZE
196967. BPF_REG_TMP
196968. BPF_REG_X
196969. BPF_RET
196970. BPF_RI_F_RF_NO_DIRECT
196971. BPF_RSH
196972. BPF_RVAL
196973. BPF_SIZE
196974. BPF_SIZEOF
196975. BPF_SIZE_MASK
196976. BPF_SIZE_MAX
196977. BPF_SKB_CB_LEN
196978. BPF_SK_LOOKUP
196979. BPF_SK_MSG_VERDICT
196980. BPF_SK_SKB_STREAM_PARSER
196981. BPF_SK_SKB_STREAM_VERDICT
196982. BPF_SK_STORAGE_CACHE_SIZE
196983. BPF_SK_STORAGE_GET_F_CREATE
196984. BPF_SK_STORAGE_MAP_TEST_NAME
196985. BPF_SK_STORAGE_MAP_TEST_NR_THREADS
196986. BPF_SK_STORAGE_MAP_TEST_RUNTIME_S
196987. BPF_SK_STORAGE_MAP_TEST_SK_PER_THREAD
196988. BPF_SOCKHASH_FILENAME
196989. BPF_SOCKMAP_FILENAME
196990. BPF_SOCK_ADDR_LOAD
196991. BPF_SOCK_ADDR_STORE
196992. BPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB
196993. BPF_SOCK_OPS_ALL_CB_FLAGS
196994. BPF_SOCK_OPS_BASE_RTT
196995. BPF_SOCK_OPS_NEEDS_ECN
196996. BPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB
196997. BPF_SOCK_OPS_RETRANS_CB
196998. BPF_SOCK_OPS_RETRANS_CB_FLAG
196999. BPF_SOCK_OPS_RTO_CB
197000. BPF_SOCK_OPS_RTO_CB_FLAG
197001. BPF_SOCK_OPS_RTT_CB
197002. BPF_SOCK_OPS_RTT_CB_FLAG
197003. BPF_SOCK_OPS_RWND_INIT
197004. BPF_SOCK_OPS_STATE_CB
197005. BPF_SOCK_OPS_STATE_CB_FLAG
197006. BPF_SOCK_OPS_TCP_CONNECT_CB
197007. BPF_SOCK_OPS_TCP_LISTEN_CB
197008. BPF_SOCK_OPS_TEST_FLAG
197009. BPF_SOCK_OPS_TIMEOUT_INIT
197010. BPF_SOCK_OPS_VOID
197011. BPF_SRC
197012. BPF_ST
197013. BPF_STACK_BUILD_ID_EMPTY
197014. BPF_STACK_BUILD_ID_IP
197015. BPF_STACK_BUILD_ID_VALID
197016. BPF_STMT
197017. BPF_STRTOX_BASE_MASK
197018. BPF_STX
197019. BPF_STX_MEM
197020. BPF_STX_XADD
197021. BPF_ST_MEM
197022. BPF_SUB
197023. BPF_SYM_ELF_TYPE
197024. BPF_TAG_FMT
197025. BPF_TAG_SIZE
197026. BPF_TAILCALL_CNT_SP_OFF
197027. BPF_TAILCALL_PROLOGUE_SIZE
197028. BPF_TAILCALL_PROLOGUE_SKIP
197029. BPF_TAIL_CALL
197030. BPF_TASK_FD_QUERY
197031. BPF_TASK_FD_QUERY_LAST_FIELD
197032. BPF_TAX
197033. BPF_TCP_CLOSE
197034. BPF_TCP_CLOSE_WAIT
197035. BPF_TCP_CLOSING
197036. BPF_TCP_ESTABLISHED
197037. BPF_TCP_FIN_WAIT1
197038. BPF_TCP_FIN_WAIT2
197039. BPF_TCP_LAST_ACK
197040. BPF_TCP_LISTEN
197041. BPF_TCP_MAX_STATES
197042. BPF_TCP_NEW_SYN_RECV
197043. BPF_TCP_SOCK_GET_COMMON
197044. BPF_TCP_SYN_RECV
197045. BPF_TCP_SYN_SENT
197046. BPF_TCP_TIME_WAIT
197047. BPF_TC_HI
197048. BPF_TC_LO
197049. BPF_TEST_RUN_DEFINE_EVENT
197050. BPF_TO_BE
197051. BPF_TO_LE
197052. BPF_TRACE_DEFN_x
197053. BPF_TRACE_MAX_PROGS
197054. BPF_TXA
197055. BPF_TYPE_MAP
197056. BPF_TYPE_PROG
197057. BPF_TYPE_UNSPEC
197058. BPF_VERIFIER_TMP_LOG_SIZE
197059. BPF_W
197060. BPF_WRITE
197061. BPF_X
197062. BPF_XADD
197063. BPF_XDP_SOCK_GET
197064. BPF_XOR
197065. BPF_ZEXT_REG
197066. BPHCMP_ENABLE
197067. BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK
197068. BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT
197069. BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK
197070. BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT
197071. BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK
197072. BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT
197073. BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK
197074. BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT
197075. BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK
197076. BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT
197077. BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK
197078. BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT
197079. BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK
197080. BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT
197081. BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK
197082. BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT
197083. BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK
197084. BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT
197085. BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK
197086. BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT
197087. BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK
197088. BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT
197089. BPHY_ADCBIAS
197090. BPHY_ANA11G_FILT_CTRL
197091. BPHY_ANACORE
197092. BPHY_ANGLE_SCALE
197093. BPHY_BAND_SEL_UP20
197094. BPHY_BB_CONFIG
197095. BPHY_BYPASS
197096. BPHY_CCK_COEFF1
197097. BPHY_CCK_COEFF2
197098. BPHY_CCK_DELAY_LONG
197099. BPHY_CCK_DELAY_SHORT
197100. BPHY_CCK_LMS_STEP
197101. BPHY_COEFFS
197102. BPHY_COUNTER_RESET
197103. BPHY_CRS_DROP_TO
197104. BPHY_DAC_CONTROL
197105. BPHY_DDFS_ENABLE
197106. BPHY_DEBUG
197107. BPHY_DIVERSITY_CTL
197108. BPHY_DSSS_COEFF1
197109. BPHY_DSSS_COEFF2
197110. BPHY_FINE_DIGIGAIN_CTRL
197111. BPHY_FREQ_CONTROL
197112. BPHY_FREQ_OFFSET
197113. BPHY_GAIN
197114. BPHY_HDR_TYPE
197115. BPHY_IQ_TRESH_H
197116. BPHY_IQ_TRESH_HH
197117. BPHY_IQ_TRESH_L
197118. BPHY_IQ_TRESH_LL
197119. BPHY_JSSI
197120. BPHY_LMS_CFF_READ
197121. BPHY_LMS_COEFF_I
197122. BPHY_LMS_COEFF_Q
197123. BPHY_LNA_GAIN_RANGE
197124. BPHY_LNA_GAIN_RANGE_10
197125. BPHY_LNA_GAIN_RANGE_32
197126. BPHY_LOCOMP_LUT
197127. BPHY_LOCOMP_LUT_END
197128. BPHY_LO_IQMAG_ACC
197129. BPHY_LO_LEAKAGE
197130. BPHY_LO_RSSI_ACC
197131. BPHY_OPTIONAL_MODES
197132. BPHY_OPTIONAL_MODES2
197133. BPHY_PA_TX_TIME_UP
197134. BPHY_PA_TX_TO
197135. BPHY_PEAK_CNT_THRESH
197136. BPHY_PEAK_ENERGY_HI
197137. BPHY_PEAK_ENERGY_LO
197138. BPHY_PHASE_SCALE
197139. BPHY_PHYCRSTH
197140. BPHY_PLCP_SHORT_TIME
197141. BPHY_PLCP_TIME
197142. BPHY_PLL_OUT
197143. BPHY_PPROC_CHAN_DELAY
197144. BPHY_REFRESH_CTRL
197145. BPHY_REFRESH_MAIN
197146. BPHY_REFRESH_TO0
197147. BPHY_REFRESH_TO1
197148. BPHY_REG_OFT_BASE
197149. BPHY_RFDC_CANCEL_CTL
197150. BPHY_RF_OVERRIDE
197151. BPHY_RF_OVERRIDE2
197152. BPHY_RF_TR_LOOKUP1
197153. BPHY_RF_TR_LOOKUP2
197154. BPHY_RSSI_LUT
197155. BPHY_RSSI_LUT_END
197156. BPHY_RSSI_TRESH
197157. BPHY_RX_DELAY_COMP
197158. BPHY_RX_FLTR_TIME_UP
197159. BPHY_RX_STATUS2
197160. BPHY_RX_STATUS3
197161. BPHY_SFD_CTL
197162. BPHY_SFD_TO
197163. BPHY_SHORT_SFD_NZEROS
197164. BPHY_SIFS_TIME
197165. BPHY_SIG_POW
197166. BPHY_SLOT_TIME
197167. BPHY_SPUR_CANCEL_CTRL
197168. BPHY_STEP
197169. BPHY_SYNC_CTL
197170. BPHY_SYNTH_DC_TO
197171. BPHY_TEST
197172. BPHY_TR_CORR
197173. BPHY_TR_LOSS_CTL
197174. BPHY_TSSI
197175. BPHY_TSSI2PWR_LUT
197176. BPHY_TSSI2PWR_LUT_END
197177. BPHY_TSSI_CTL
197178. BPHY_TSSI_LUT
197179. BPHY_TSSI_LUT_END
197180. BPHY_TXGAIN_LUT
197181. BPHY_TXGAIN_LUT_END
197182. BPHY_TX_DC_OFF1
197183. BPHY_TX_DC_OFF2
197184. BPHY_TX_EST_PWR
197185. BPHY_TX_POWER_OVERRIDE
197186. BPHY_TX_PWR_BASE_IDX
197187. BPHY_TX_PWR_CTRL
197188. BPHY_WARMUP
197189. BPIALL
197190. BPIALLIS
197191. BPL
197192. BPLLPOWERUP
197193. BPLL_CON0
197194. BPLL_CON1
197195. BPLL_CON2
197196. BPLL_LOCK
197197. BPL_ALIGN_SZ
197198. BPMACLOOPBACK
197199. BPMEMTYPE
197200. BPMEMTYPE_MASK
197201. BPMEMTYPE_SHIFT
197202. BPMP_ABI_RATCHET_VALUE
197203. BPMP_CLK_HAS_MUX
197204. BPMP_CLK_HAS_SET_RATE
197205. BPMP_CLK_IS_ROOT
197206. BPMP_EACCES
197207. BPMP_EBADCMD
197208. BPMP_EBADSLT
197209. BPMP_EFAULT
197210. BPMP_EINVAL
197211. BPMP_EIO
197212. BPMP_EISDIR
197213. BPMP_ENODEV
197214. BPMP_ENOENT
197215. BPMP_ENOHANDLER
197216. BPMP_ENOMEM
197217. BPMP_ENOSYS
197218. BPMP_ERANGE
197219. BPMP_ETIMEDOUT
197220. BPMTCFG
197221. BPMTCFG_MASK
197222. BPMTCFG_SHIFT
197223. BPMTC_mskBPMTC
197224. BPMTC_offBPMTC
197225. BPM_A2DP
197226. BPM_ADDR
197227. BPM_ADDR_MASK
197228. BPM_HFP
197229. BPM_HID
197230. BPM_PAN
197231. BPM_REG_CGCG_OVERRIDE
197232. BPM_REG_CGLS_EN
197233. BPM_REG_CGLS_ON
197234. BPM_REG_FGCG_MAX
197235. BPM_REG_FGCG_OVERRIDE
197236. BPM_REG_MGCG_OVERRIDE
197237. BPOFF
197238. BPON
197239. BPOR
197240. BPOR_RGB
197241. BPOWERMEASF_LENGTH
197242. BPOWERMEAST_LENGTH
197243. BPOWER_THRES
197244. BPP
197245. BPP16
197246. BPP24
197247. BPP32
197248. BPP8
197249. BPP_ASIC_1V7
197250. BPP_ASIC_1V8
197251. BPP_ASIC_1V9
197252. BPP_ASIC_2V0
197253. BPP_ASIC_2V7
197254. BPP_ASIC_2V8
197255. BPP_ASIC_3V2
197256. BPP_ASIC_3V3
197257. BPP_BLENDED_PIPE
197258. BPP_INVALID
197259. BPP_LDO_OFF
197260. BPP_LDO_ON
197261. BPP_LDO_POWB
197262. BPP_LDO_SUSPEND
197263. BPP_OFST
197264. BPP_PAD_1V8
197265. BPP_PAD_3V3
197266. BPP_PAD_MASK
197267. BPP_POWER_10_PERCENT_ON
197268. BPP_POWER_15_PERCENT_ON
197269. BPP_POWER_5_PERCENT_ON
197270. BPP_POWER_MASK
197271. BPP_POWER_OFF
197272. BPP_POWER_ON
197273. BPP_REG_TUNED18
197274. BPP_RW
197275. BPP_RX
197276. BPP_TUNED18_SHIFT_8402
197277. BPP_TUNED18_SHIFT_8411
197278. BPP_XX
197279. BPRCISH
197280. BPRCISH_MASK
197281. BPRCISH_SHIFT
197282. BPRCNSH
197283. BPRCNSH_MASK
197284. BPRCNSH_SHIFT
197285. BPRCOSH
197286. BPRCOSH_MASK
197287. BPRCOSH_SHIFT
197288. BPREMRPSR
197289. BPRINTK
197290. BPSDFFT_SAMPLE_POINT
197291. BPSD_ANTENNA_PATH
197292. BPSD_AVERAGE_NUM
197293. BPSD_FREQ
197294. BPSD_IQ_SWITCH
197295. BPSD_REPORT
197296. BPSD_RX_TRIGGER
197297. BPSD_SINE_TONE_SCALE
197298. BPSD_TX_TRIGGER
197299. BPSHCFG
197300. BPSHCFG_MASK
197301. BPSHCFG_SHIFT
197302. BPSIZE
197303. BPS_GDSC
197304. BPS_TO_BRG
197305. BPT
197306. BPTR_BPHW
197307. BPTR_JPT
197308. BPV
197309. BPWDB
197310. BPWED_TH
197311. BPWR
197312. BP_ABS_FUNC
197313. BP_ACCESS_WATCHPOINT
197314. BP_ACTIVE
197315. BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL
197316. BP_APBH_CTRL0_RESET_CHANNEL
197317. BP_BCH_FLASH0LAYOUT0_DATA0_SIZE
197318. BP_BCH_FLASH0LAYOUT0_ECC0
197319. BP_BCH_FLASH0LAYOUT0_META_SIZE
197320. BP_BCH_FLASH0LAYOUT0_NBLOCKS
197321. BP_BCH_FLASH0LAYOUT1_DATAN_SIZE
197322. BP_BCH_FLASH0LAYOUT1_ECCN
197323. BP_BCH_FLASH0LAYOUT1_PAGE_SIZE
197324. BP_BREAKPOINT
197325. BP_CCW_COMMAND
197326. BP_CCW_PIO_NUM
197327. BP_CIABR
197328. BP_CLKSEQ_BYPASS_SAIF
197329. BP_CLKSEQ_BYPASS_SAIF0
197330. BP_CLKSEQ_BYPASS_SSP
197331. BP_CLKSEQ_BYPASS_SSP0
197332. BP_CLPCR_LPM
197333. BP_CLPCR_STBY_COUNT
197334. BP_COMMAND
197335. BP_CPU_INTERRUPT_WAIT
197336. BP_DABR
197337. BP_DATAIN
197338. BP_DATAOUT
197339. BP_DEINSERT
197340. BP_DONE
197341. BP_EAGAIN
197342. BP_ECANCELED
197343. BP_ENET_DIV_TIME
197344. BP_ENET_SLEEP
197345. BP_FILTER
197346. BP_FRAC0_IO0FRAC
197347. BP_FRAC0_IO1FRAC
197348. BP_FRAC_IOFRAC
197349. BP_FROM_DCB
197350. BP_FUNC
197351. BP_FW_MB_IDX
197352. BP_FW_MB_IDX_VN
197353. BP_GPMI_CTRL0_ADDRESS
197354. BP_GPMI_CTRL0_COMMAND_MODE
197355. BP_GPMI_CTRL0_CS
197356. BP_GPMI_CTRL0_XFER_COUNT
197357. BP_GPMI_CTRL1_DECOUPLE_CS
197358. BP_GPMI_CTRL1_DLL_ENABLE
197359. BP_GPMI_CTRL1_HALF_PERIOD
197360. BP_GPMI_CTRL1_RDN_DELAY
197361. BP_GPMI_CTRL1_WRN_DLY_SEL
197362. BP_GPMI_ECCCTRL_BUFFER_MASK
197363. BP_GPMI_ECCCTRL_ECC_CMD
197364. BP_GPMI_TIMING0_ADDRESS_SETUP
197365. BP_GPMI_TIMING0_DATA_HOLD
197366. BP_GPMI_TIMING0_DATA_SETUP
197367. BP_GPMI_TIMING1_BUSY_TIMEOUT
197368. BP_HARDEN_EL2_SLOTS
197369. BP_HARDWARE_BREAKPOINT
197370. BP_ILT
197371. BP_INSERT
197372. BP_INT
197373. BP_L_ID
197374. BP_MAX_VN_NUM
197375. BP_MISC_CTRL
197376. BP_MMDC_MAPSR_PSD
197377. BP_MMDC_MAPSR_PSS
197378. BP_MMDC_MDMISC_DDR_TYPE
197379. BP_MSGIN
197380. BP_MSGOUT
197381. BP_MUX_MODE
197382. BP_NOMCP
197383. BP_NUM
197384. BP_PAD_CTL_IFMUX
197385. BP_PATH
197386. BP_PLL_MULT
197387. BP_PMCTRL_PSTOPO
197388. BP_PMCTRL_RUNM
197389. BP_PMCTRL_STOPM
197390. BP_POKE_BREAKPOINT
197391. BP_POLL_MAXCOUNT
197392. BP_POLL_TIME
197393. BP_PORT
197394. BP_PXP_ALPHA_A_CTRL_RSVD0
197395. BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA
197396. BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE
197397. BP_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE
197398. BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA
197399. BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE
197400. BP_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE
197401. BP_PXP_ALPHA_B_CTRL_1_ROP
197402. BP_PXP_ALPHA_B_CTRL_1_RSVD0
197403. BP_PXP_ALPHA_B_CTRL_1_RSVD1
197404. BP_PXP_ALPHA_B_CTRL_RSVD0
197405. BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA
197406. BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE
197407. BP_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE
197408. BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA
197409. BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE
197410. BP_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE
197411. BP_PXP_AS_BUF_ADDR
197412. BP_PXP_AS_CLRKEYHIGH_0_PIXEL
197413. BP_PXP_AS_CLRKEYHIGH_0_RSVD1
197414. BP_PXP_AS_CLRKEYHIGH_1_PIXEL
197415. BP_PXP_AS_CLRKEYHIGH_1_RSVD1
197416. BP_PXP_AS_CLRKEYLOW_0_PIXEL
197417. BP_PXP_AS_CLRKEYLOW_0_RSVD1
197418. BP_PXP_AS_CLRKEYLOW_1_PIXEL
197419. BP_PXP_AS_CLRKEYLOW_1_RSVD1
197420. BP_PXP_AS_CTRL_ALPHA
197421. BP_PXP_AS_CTRL_ALPHA_CTRL
197422. BP_PXP_AS_CTRL_FORMAT
197423. BP_PXP_AS_CTRL_ROP
197424. BP_PXP_AS_CTRL_RSVD1
197425. BP_PXP_AS_PITCH_PITCH
197426. BP_PXP_AS_PITCH_RSVD
197427. BP_PXP_CFA_DATA
197428. BP_PXP_CSC1_COEF0_C0
197429. BP_PXP_CSC1_COEF0_UV_OFFSET
197430. BP_PXP_CSC1_COEF0_Y_OFFSET
197431. BP_PXP_CSC1_COEF1_C1
197432. BP_PXP_CSC1_COEF1_C4
197433. BP_PXP_CSC1_COEF1_RSVD0
197434. BP_PXP_CSC1_COEF1_RSVD1
197435. BP_PXP_CSC1_COEF2_C2
197436. BP_PXP_CSC1_COEF2_C3
197437. BP_PXP_CSC1_COEF2_RSVD0
197438. BP_PXP_CSC1_COEF2_RSVD1
197439. BP_PXP_CSC2_COEF0_A1
197440. BP_PXP_CSC2_COEF0_A2
197441. BP_PXP_CSC2_COEF0_RSVD0
197442. BP_PXP_CSC2_COEF0_RSVD1
197443. BP_PXP_CSC2_COEF1_A3
197444. BP_PXP_CSC2_COEF1_B1
197445. BP_PXP_CSC2_COEF1_RSVD0
197446. BP_PXP_CSC2_COEF1_RSVD1
197447. BP_PXP_CSC2_COEF2_B2
197448. BP_PXP_CSC2_COEF2_B3
197449. BP_PXP_CSC2_COEF2_RSVD0
197450. BP_PXP_CSC2_COEF2_RSVD1
197451. BP_PXP_CSC2_COEF3_C1
197452. BP_PXP_CSC2_COEF3_C2
197453. BP_PXP_CSC2_COEF3_RSVD0
197454. BP_PXP_CSC2_COEF3_RSVD1
197455. BP_PXP_CSC2_COEF4_C3
197456. BP_PXP_CSC2_COEF4_D1
197457. BP_PXP_CSC2_COEF4_RSVD0
197458. BP_PXP_CSC2_COEF4_RSVD1
197459. BP_PXP_CSC2_COEF5_D2
197460. BP_PXP_CSC2_COEF5_D3
197461. BP_PXP_CSC2_COEF5_RSVD0
197462. BP_PXP_CSC2_COEF5_RSVD1
197463. BP_PXP_CSC2_CTRL_CSC_MODE
197464. BP_PXP_CSC2_CTRL_RSVD
197465. BP_PXP_CTRL2_ROTATE0
197466. BP_PXP_CTRL2_ROTATE1
197467. BP_PXP_CTRL2_RSVD0
197468. BP_PXP_CTRL2_RSVD3
197469. BP_PXP_CTRL_ROTATE0
197470. BP_PXP_CTRL_ROTATE1
197471. BP_PXP_CTRL_RSVD0
197472. BP_PXP_DATA_PATH_CTRL0_MUX0_SEL
197473. BP_PXP_DATA_PATH_CTRL0_MUX10_SEL
197474. BP_PXP_DATA_PATH_CTRL0_MUX11_SEL
197475. BP_PXP_DATA_PATH_CTRL0_MUX12_SEL
197476. BP_PXP_DATA_PATH_CTRL0_MUX13_SEL
197477. BP_PXP_DATA_PATH_CTRL0_MUX14_SEL
197478. BP_PXP_DATA_PATH_CTRL0_MUX15_SEL
197479. BP_PXP_DATA_PATH_CTRL0_MUX1_SEL
197480. BP_PXP_DATA_PATH_CTRL0_MUX2_SEL
197481. BP_PXP_DATA_PATH_CTRL0_MUX3_SEL
197482. BP_PXP_DATA_PATH_CTRL0_MUX4_SEL
197483. BP_PXP_DATA_PATH_CTRL0_MUX5_SEL
197484. BP_PXP_DATA_PATH_CTRL0_MUX6_SEL
197485. BP_PXP_DATA_PATH_CTRL0_MUX7_SEL
197486. BP_PXP_DATA_PATH_CTRL0_MUX8_SEL
197487. BP_PXP_DATA_PATH_CTRL0_MUX9_SEL
197488. BP_PXP_DATA_PATH_CTRL1_MUX16_SEL
197489. BP_PXP_DATA_PATH_CTRL1_MUX17_SEL
197490. BP_PXP_DATA_PATH_CTRL1_RSVD0
197491. BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT
197492. BP_PXP_DEBUGCTRL_RSVD
197493. BP_PXP_DEBUGCTRL_SELECT
197494. BP_PXP_DEBUG_DATA
197495. BP_PXP_INIT_MEM_CTRL_ADDR
197496. BP_PXP_INIT_MEM_CTRL_RSVD0
197497. BP_PXP_INIT_MEM_CTRL_SELECT
197498. BP_PXP_INIT_MEM_DATA_DATA
197499. BP_PXP_INIT_MEM_DATA_HIGH_DATA
197500. BP_PXP_IRQ_MASK_RSVD1
197501. BP_PXP_IRQ_RSVD1
197502. BP_PXP_LUT_ADDR_ADDR
197503. BP_PXP_LUT_ADDR_NUM_BYTES
197504. BP_PXP_LUT_ADDR_RSVD1
197505. BP_PXP_LUT_CTRL_LOOKUP_MODE
197506. BP_PXP_LUT_CTRL_OUT_MODE
197507. BP_PXP_LUT_CTRL_RSVD0
197508. BP_PXP_LUT_CTRL_RSVD1
197509. BP_PXP_LUT_CTRL_RSVD2
197510. BP_PXP_LUT_CTRL_RSVD3
197511. BP_PXP_LUT_DATA_DATA
197512. BP_PXP_LUT_EXTMEM_ADDR
197513. BP_PXP_NEXT_POINTER
197514. BP_PXP_OUT_AS_LRC_RSVD0
197515. BP_PXP_OUT_AS_LRC_RSVD1
197516. BP_PXP_OUT_AS_LRC_X
197517. BP_PXP_OUT_AS_LRC_Y
197518. BP_PXP_OUT_AS_ULC_RSVD0
197519. BP_PXP_OUT_AS_ULC_RSVD1
197520. BP_PXP_OUT_AS_ULC_X
197521. BP_PXP_OUT_AS_ULC_Y
197522. BP_PXP_OUT_BUF2_ADDR
197523. BP_PXP_OUT_BUF_ADDR
197524. BP_PXP_OUT_CTRL_ALPHA
197525. BP_PXP_OUT_CTRL_FORMAT
197526. BP_PXP_OUT_CTRL_INTERLACED_OUTPUT
197527. BP_PXP_OUT_CTRL_RSVD0
197528. BP_PXP_OUT_CTRL_RSVD1
197529. BP_PXP_OUT_LRC_RSVD0
197530. BP_PXP_OUT_LRC_RSVD1
197531. BP_PXP_OUT_LRC_X
197532. BP_PXP_OUT_LRC_Y
197533. BP_PXP_OUT_PITCH_PITCH
197534. BP_PXP_OUT_PITCH_RSVD
197535. BP_PXP_OUT_PS_LRC_RSVD0
197536. BP_PXP_OUT_PS_LRC_RSVD1
197537. BP_PXP_OUT_PS_LRC_X
197538. BP_PXP_OUT_PS_LRC_Y
197539. BP_PXP_OUT_PS_ULC_RSVD0
197540. BP_PXP_OUT_PS_ULC_RSVD1
197541. BP_PXP_OUT_PS_ULC_X
197542. BP_PXP_OUT_PS_ULC_Y
197543. BP_PXP_POWER_REG0_CTRL
197544. BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0
197545. BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN
197546. BP_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN
197547. BP_PXP_POWER_REG0_ROT0_MEM_LP_STATE
197548. BP_PXP_POWER_REG1_ALU_A_MEM_LP_STATE
197549. BP_PXP_POWER_REG1_ALU_B_MEM_LP_STATE
197550. BP_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE
197551. BP_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE
197552. BP_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE
197553. BP_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE
197554. BP_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE
197555. BP_PXP_POWER_REG1_ROT1_MEM_LP_STATE
197556. BP_PXP_POWER_REG1_RSVD0
197557. BP_PXP_PS_BACKGROUND_0_COLOR
197558. BP_PXP_PS_BACKGROUND_0_RSVD
197559. BP_PXP_PS_BACKGROUND_1_COLOR
197560. BP_PXP_PS_BACKGROUND_1_RSVD
197561. BP_PXP_PS_BUF_ADDR
197562. BP_PXP_PS_CLRKEYHIGH_0_PIXEL
197563. BP_PXP_PS_CLRKEYHIGH_0_RSVD1
197564. BP_PXP_PS_CLRKEYHIGH_1_PIXEL
197565. BP_PXP_PS_CLRKEYHIGH_1_RSVD1
197566. BP_PXP_PS_CLRKEYLOW_0_PIXEL
197567. BP_PXP_PS_CLRKEYLOW_0_RSVD1
197568. BP_PXP_PS_CLRKEYLOW_1_PIXEL
197569. BP_PXP_PS_CLRKEYLOW_1_RSVD1
197570. BP_PXP_PS_CTRL_DECX
197571. BP_PXP_PS_CTRL_DECY
197572. BP_PXP_PS_CTRL_FORMAT
197573. BP_PXP_PS_CTRL_RSVD1
197574. BP_PXP_PS_OFFSET_RSVD1
197575. BP_PXP_PS_OFFSET_RSVD2
197576. BP_PXP_PS_OFFSET_XOFFSET
197577. BP_PXP_PS_OFFSET_YOFFSET
197578. BP_PXP_PS_PITCH_PITCH
197579. BP_PXP_PS_PITCH_RSVD
197580. BP_PXP_PS_SCALE_XSCALE
197581. BP_PXP_PS_SCALE_YSCALE
197582. BP_PXP_PS_UBUF_ADDR
197583. BP_PXP_PS_VBUF_ADDR
197584. BP_PXP_STAT_AXI_ERROR_ID_0
197585. BP_PXP_STAT_AXI_ERROR_ID_1
197586. BP_PXP_STAT_BLOCKX
197587. BP_PXP_STAT_BLOCKY
197588. BP_PXP_VERSION_MAJOR
197589. BP_PXP_VERSION_MINOR
197590. BP_PXP_VERSION_STEP
197591. BP_READ_WATCHPOINT
197592. BP_REMOVED
197593. BP_RESULT_BADBIOSTABLE
197594. BP_RESULT_BADINPUT
197595. BP_RESULT_FAILURE
197596. BP_RESULT_NORECORD
197597. BP_RESULT_OK
197598. BP_RESULT_UNSUPPORTED
197599. BP_RW
197600. BP_SAIF_CLKMUX
197601. BP_SAIF_CTRL_BITCLK_MULT_RATE
197602. BP_SAIF_CTRL_CHANNEL_NUM_SELECT
197603. BP_SAIF_CTRL_DMAWAIT_COUNT
197604. BP_SAIF_CTRL_RSRVD2
197605. BP_SAIF_CTRL_WORD_LENGTH
197606. BP_SAIF_DATA_PCM_LEFT
197607. BP_SAIF_DATA_PCM_RIGHT
197608. BP_SAIF_DIV_FRAC_EN
197609. BP_SAIF_STAT_RSRVD0
197610. BP_SAIF_STAT_RSRVD1
197611. BP_SAIF_STAT_RSRVD2
197612. BP_SAIF_VERSION_MAJOR
197613. BP_SAIF_VERSION_MINOR
197614. BP_SAIF_VERSION_STEP
197615. BP_SET
197616. BP_SRC_SCR_CORE1_ENABLE
197617. BP_SRC_SCR_CORE1_RST
197618. BP_SRC_SCR_SW_GPU_RST
197619. BP_SRC_SCR_SW_IPU1_RST
197620. BP_SRC_SCR_SW_IPU2_RST
197621. BP_SRC_SCR_SW_OPEN_VG_RST
197622. BP_SRC_SCR_SW_VPU_RST
197623. BP_SRC_SCR_WARM_RESET_ENABLE
197624. BP_SSP_BLOCK_SIZE_BLOCK_COUNT
197625. BP_SSP_BLOCK_SIZE_BLOCK_SIZE
197626. BP_SSP_CMD0_BLOCK_COUNT
197627. BP_SSP_CMD0_BLOCK_SIZE
197628. BP_SSP_CMD0_CMD
197629. BP_SSP_CTRL0_BUS_WIDTH
197630. BP_SSP_CTRL0_XFER_COUNT
197631. BP_SSP_CTRL1_SSP_MODE
197632. BP_SSP_CTRL1_WORD_LENGTH
197633. BP_SSP_TIMING_CLOCK_DIVIDE
197634. BP_SSP_TIMING_CLOCK_RATE
197635. BP_SSP_TIMING_TIMEOUT
197636. BP_STATUS
197637. BP_TAG_COMMAND_LINE
197638. BP_TAG_FDT
197639. BP_TAG_FIRST
197640. BP_TAG_INITRD
197641. BP_TAG_LAST
197642. BP_TAG_MEMORY
197643. BP_TAG_SERIAL_BAUDRATE
197644. BP_TAG_SERIAL_PORT
197645. BP_THRESHOLD
197646. BP_TIMROT_MAJOR_VERSION
197647. BP_TIMROT_TIMCTRLn_SELECT
197648. BP_TRAP
197649. BP_UNDEFINED
197650. BP_VECTOR
197651. BP_VERSION
197652. BP_VF
197653. BP_VFDB
197654. BP_VF_BULLETIN
197655. BP_VF_BULLETIN_DMA
197656. BP_VF_CXT_PAGE
197657. BP_VF_MBX
197658. BP_VF_MBX_DMA
197659. BP_VN
197660. BP_W
197661. BP_WAIT
197662. BP_WRITE_WATCHPOINT
197663. BP_X
197664. BP_binary_search
197665. BP_fnode_parent
197666. BP_hbff
197667. BP_internal
197668. BQ24150
197669. BQ24150A
197670. BQ24151
197671. BQ24151A
197672. BQ24152
197673. BQ24153
197674. BQ24153A
197675. BQ24155
197676. BQ24156
197677. BQ24156A
197678. BQ24157S
197679. BQ24158
197680. BQ2415X_BIT_BOOST
197681. BQ2415X_BIT_CE
197682. BQ2415X_BIT_EN_STAT
197683. BQ2415X_BIT_HZ_MODE
197684. BQ2415X_BIT_OPA_MODE
197685. BQ2415X_BIT_OTG
197686. BQ2415X_BIT_OTG_EN
197687. BQ2415X_BIT_OTG_PL
197688. BQ2415X_BIT_TE
197689. BQ2415X_BIT_TMR_RST
197690. BQ2415X_BOOST_MODE_DISABLE
197691. BQ2415X_BOOST_MODE_ENABLE
197692. BQ2415X_BOOST_MODE_STATUS
197693. BQ2415X_BOOST_STATUS
197694. BQ2415X_CHARGER_DISABLE
197695. BQ2415X_CHARGER_ENABLE
197696. BQ2415X_CHARGER_H
197697. BQ2415X_CHARGER_STATUS
197698. BQ2415X_CHARGE_STATUS
197699. BQ2415X_CHARGE_TERMINATION_DISABLE
197700. BQ2415X_CHARGE_TERMINATION_ENABLE
197701. BQ2415X_CHARGE_TERMINATION_STATUS
197702. BQ2415X_FAULT_STATUS
197703. BQ2415X_HIGH_IMPEDANCE_DISABLE
197704. BQ2415X_HIGH_IMPEDANCE_ENABLE
197705. BQ2415X_HIGH_IMPEDANCE_STATUS
197706. BQ2415X_MASK_FAULT
197707. BQ2415X_MASK_LIMIT
197708. BQ2415X_MASK_PN
197709. BQ2415X_MASK_RESET
197710. BQ2415X_MASK_REVISION
197711. BQ2415X_MASK_STAT
197712. BQ2415X_MASK_VENDER
197713. BQ2415X_MASK_VI_CHRG
197714. BQ2415X_MASK_VI_TERM
197715. BQ2415X_MASK_VLOWV
197716. BQ2415X_MASK_VO
197717. BQ2415X_MODE_BOOST
197718. BQ2415X_MODE_DEDICATED_CHARGER
197719. BQ2415X_MODE_HOST_CHARGER
197720. BQ2415X_MODE_NONE
197721. BQ2415X_MODE_OFF
197722. BQ2415X_OTG_ACTIVATE_HIGH
197723. BQ2415X_OTG_ACTIVATE_LOW
197724. BQ2415X_OTG_LEVEL
197725. BQ2415X_OTG_PIN_DISABLE
197726. BQ2415X_OTG_PIN_ENABLE
197727. BQ2415X_OTG_PIN_STATUS
197728. BQ2415X_OTG_STATUS
197729. BQ2415X_PART_NUMBER
197730. BQ2415X_REG_CONTROL
197731. BQ2415X_REG_CURRENT
197732. BQ2415X_REG_STATUS
197733. BQ2415X_REG_VENDER
197734. BQ2415X_REG_VOLTAGE
197735. BQ2415X_RESET_CONTROL
197736. BQ2415X_RESET_CURRENT
197737. BQ2415X_RESET_STATUS
197738. BQ2415X_RESET_VOLTAGE
197739. BQ2415X_REVISION
197740. BQ2415X_SHIFT_FAULT
197741. BQ2415X_SHIFT_LIMIT
197742. BQ2415X_SHIFT_PN
197743. BQ2415X_SHIFT_REVISION
197744. BQ2415X_SHIFT_STAT
197745. BQ2415X_SHIFT_VENDER
197746. BQ2415X_SHIFT_VI_CHRG
197747. BQ2415X_SHIFT_VI_TERM
197748. BQ2415X_SHIFT_VLOWV
197749. BQ2415X_SHIFT_VO
197750. BQ2415X_STAT_PIN_DISABLE
197751. BQ2415X_STAT_PIN_ENABLE
197752. BQ2415X_STAT_PIN_STATUS
197753. BQ2415X_TIMER_RESET
197754. BQ2415X_TIMER_TIMEOUT
197755. BQ2415X_VENDER_CODE
197756. BQ24190_MANUFACTURER
197757. BQ24190_REG_CCC
197758. BQ24190_REG_CCC_FORCE_20PCT_MASK
197759. BQ24190_REG_CCC_FORCE_20PCT_SHIFT
197760. BQ24190_REG_CCC_ICHG_MASK
197761. BQ24190_REG_CCC_ICHG_SHIFT
197762. BQ24190_REG_CTTC
197763. BQ24190_REG_CTTC_CHG_TIMER_MASK
197764. BQ24190_REG_CTTC_CHG_TIMER_SHIFT
197765. BQ24190_REG_CTTC_EN_TERM_MASK
197766. BQ24190_REG_CTTC_EN_TERM_SHIFT
197767. BQ24190_REG_CTTC_EN_TIMER_MASK
197768. BQ24190_REG_CTTC_EN_TIMER_SHIFT
197769. BQ24190_REG_CTTC_JEITA_ISET_MASK
197770. BQ24190_REG_CTTC_JEITA_ISET_SHIFT
197771. BQ24190_REG_CTTC_TERM_STAT_MASK
197772. BQ24190_REG_CTTC_TERM_STAT_SHIFT
197773. BQ24190_REG_CTTC_WATCHDOG_MASK
197774. BQ24190_REG_CTTC_WATCHDOG_SHIFT
197775. BQ24190_REG_CVC
197776. BQ24190_REG_CVC_BATLOWV_MASK
197777. BQ24190_REG_CVC_BATLOWV_SHIFT
197778. BQ24190_REG_CVC_VRECHG_MASK
197779. BQ24190_REG_CVC_VRECHG_SHIFT
197780. BQ24190_REG_CVC_VREG_MASK
197781. BQ24190_REG_CVC_VREG_SHIFT
197782. BQ24190_REG_F
197783. BQ24190_REG_F_BAT_FAULT_MASK
197784. BQ24190_REG_F_BAT_FAULT_SHIFT
197785. BQ24190_REG_F_BOOST_FAULT_MASK
197786. BQ24190_REG_F_BOOST_FAULT_SHIFT
197787. BQ24190_REG_F_CHRG_FAULT_MASK
197788. BQ24190_REG_F_CHRG_FAULT_SHIFT
197789. BQ24190_REG_F_NTC_FAULT_MASK
197790. BQ24190_REG_F_NTC_FAULT_SHIFT
197791. BQ24190_REG_F_WATCHDOG_FAULT_MASK
197792. BQ24190_REG_F_WATCHDOG_FAULT_SHIFT
197793. BQ24190_REG_ICTRC
197794. BQ24190_REG_ICTRC_BAT_COMP_MASK
197795. BQ24190_REG_ICTRC_BAT_COMP_SHIFT
197796. BQ24190_REG_ICTRC_TREG_MASK
197797. BQ24190_REG_ICTRC_TREG_SHIFT
197798. BQ24190_REG_ICTRC_VCLAMP_MASK
197799. BQ24190_REG_ICTRC_VCLAMP_SHIFT
197800. BQ24190_REG_ISC
197801. BQ24190_REG_ISC_EN_HIZ_MASK
197802. BQ24190_REG_ISC_EN_HIZ_SHIFT
197803. BQ24190_REG_ISC_IINLIM_MASK
197804. BQ24190_REG_ISC_IINLIM_SHIFT
197805. BQ24190_REG_ISC_VINDPM_MASK
197806. BQ24190_REG_ISC_VINDPM_SHIFT
197807. BQ24190_REG_MOC
197808. BQ24190_REG_MOC_BATFET_DISABLE_MASK
197809. BQ24190_REG_MOC_BATFET_DISABLE_SHIFT
197810. BQ24190_REG_MOC_DPDM_EN_MASK
197811. BQ24190_REG_MOC_DPDM_EN_SHIFT
197812. BQ24190_REG_MOC_INT_MASK_MASK
197813. BQ24190_REG_MOC_INT_MASK_SHIFT
197814. BQ24190_REG_MOC_JEITA_VSET_MASK
197815. BQ24190_REG_MOC_JEITA_VSET_SHIFT
197816. BQ24190_REG_MOC_TMR2X_EN_MASK
197817. BQ24190_REG_MOC_TMR2X_EN_SHIFT
197818. BQ24190_REG_PCTCC
197819. BQ24190_REG_PCTCC_IPRECHG_MASK
197820. BQ24190_REG_PCTCC_IPRECHG_MAX
197821. BQ24190_REG_PCTCC_IPRECHG_MIN
197822. BQ24190_REG_PCTCC_IPRECHG_SHIFT
197823. BQ24190_REG_PCTCC_ITERM_MASK
197824. BQ24190_REG_PCTCC_ITERM_MAX
197825. BQ24190_REG_PCTCC_ITERM_MIN
197826. BQ24190_REG_PCTCC_ITERM_SHIFT
197827. BQ24190_REG_POC
197828. BQ24190_REG_POC_BOOST_LIM_MASK
197829. BQ24190_REG_POC_BOOST_LIM_SHIFT
197830. BQ24190_REG_POC_CHG_CONFIG_CHARGE
197831. BQ24190_REG_POC_CHG_CONFIG_DISABLE
197832. BQ24190_REG_POC_CHG_CONFIG_MASK
197833. BQ24190_REG_POC_CHG_CONFIG_OTG
197834. BQ24190_REG_POC_CHG_CONFIG_SHIFT
197835. BQ24190_REG_POC_RESET_MASK
197836. BQ24190_REG_POC_RESET_SHIFT
197837. BQ24190_REG_POC_SYS_MIN_MASK
197838. BQ24190_REG_POC_SYS_MIN_MAX
197839. BQ24190_REG_POC_SYS_MIN_MIN
197840. BQ24190_REG_POC_SYS_MIN_SHIFT
197841. BQ24190_REG_POC_WDT_RESET_MASK
197842. BQ24190_REG_POC_WDT_RESET_SHIFT
197843. BQ24190_REG_SS
197844. BQ24190_REG_SS_CHRG_STAT_MASK
197845. BQ24190_REG_SS_CHRG_STAT_SHIFT
197846. BQ24190_REG_SS_DPM_STAT_MASK
197847. BQ24190_REG_SS_DPM_STAT_SHIFT
197848. BQ24190_REG_SS_PG_STAT_MASK
197849. BQ24190_REG_SS_PG_STAT_SHIFT
197850. BQ24190_REG_SS_THERM_STAT_MASK
197851. BQ24190_REG_SS_THERM_STAT_SHIFT
197852. BQ24190_REG_SS_VBUS_STAT_MASK
197853. BQ24190_REG_SS_VBUS_STAT_SHIFT
197854. BQ24190_REG_SS_VSYS_STAT_MASK
197855. BQ24190_REG_SS_VSYS_STAT_SHIFT
197856. BQ24190_REG_VPRS
197857. BQ24190_REG_VPRS_DEV_REG_MASK
197858. BQ24190_REG_VPRS_DEV_REG_SHIFT
197859. BQ24190_REG_VPRS_PN_24190
197860. BQ24190_REG_VPRS_PN_24192
197861. BQ24190_REG_VPRS_PN_24192I
197862. BQ24190_REG_VPRS_PN_MASK
197863. BQ24190_REG_VPRS_PN_SHIFT
197864. BQ24190_REG_VPRS_TS_PROFILE_MASK
197865. BQ24190_REG_VPRS_TS_PROFILE_SHIFT
197866. BQ24190_SYSFS_FIELD
197867. BQ24190_SYSFS_FIELD_RO
197868. BQ24190_SYSFS_FIELD_RW
197869. BQ24250
197870. BQ24251
197871. BQ24257
197872. BQ24257_ICHG_MAP_SIZE
197873. BQ24257_IILIMIT_MAP_SIZE
197874. BQ24257_ILIM_SET_DELAY
197875. BQ24257_ITERM_MAP_SIZE
197876. BQ24257_MANUFACTURER
197877. BQ24257_PG_GPIO
197878. BQ24257_REG_1
197879. BQ24257_REG_2
197880. BQ24257_REG_3
197881. BQ24257_REG_4
197882. BQ24257_REG_5
197883. BQ24257_REG_6
197884. BQ24257_REG_7
197885. BQ24257_VBAT_MAP_SIZE
197886. BQ24257_VINDPM_MAP_SIZE
197887. BQ24257_VOVP_MAP_SIZE
197888. BQ24735_CHARGE_CURRENT
197889. BQ24735_CHARGE_CURRENT_MASK
197890. BQ24735_CHARGE_VOLTAGE
197891. BQ24735_CHARGE_VOLTAGE_MASK
197892. BQ24735_CHG_OPT
197893. BQ24735_CHG_OPT_AC_PRESENT
197894. BQ24735_CHG_OPT_CHARGE_DISABLE
197895. BQ24735_DEVICE_ID
197896. BQ24735_INPUT_CURRENT
197897. BQ24735_INPUT_CURRENT_MASK
197898. BQ24735_MANUFACTURER_ID
197899. BQ25890_BOOSTI_TBL_SIZE
197900. BQ25890_ID
197901. BQ25890_IRQ_PIN
197902. BQ25890_MANUFACTURER
197903. BQ25890_TREG_TBL_SIZE
197904. BQ25895_ID
197905. BQ25896_ID
197906. BQ27000
197907. BQ27000_FLAG_CHGS
197908. BQ27000_FLAG_CI
197909. BQ27000_FLAG_EDV1
197910. BQ27000_FLAG_EDVF
197911. BQ27000_FLAG_FC
197912. BQ27010
197913. BQ27411
197914. BQ27421
197915. BQ27425
197916. BQ27426
197917. BQ27441
197918. BQ27500
197919. BQ2750X
197920. BQ27510G1
197921. BQ27510G2
197922. BQ27510G3
197923. BQ2751X
197924. BQ27520G1
197925. BQ27520G2
197926. BQ27520G3
197927. BQ27520G4
197928. BQ27521
197929. BQ2752X
197930. BQ27530
197931. BQ27531
197932. BQ27541
197933. BQ27542
197934. BQ27545
197935. BQ27546
197936. BQ27621
197937. BQ27742
197938. BQ27XXX_CURRENT_CONSTANT
197939. BQ27XXX_DATA
197940. BQ27XXX_DM_BLOCK
197941. BQ27XXX_DM_BUF
197942. BQ27XXX_DM_CKSUM
197943. BQ27XXX_DM_CLASS
197944. BQ27XXX_DM_CTRL
197945. BQ27XXX_DM_DATA
197946. BQ27XXX_DM_DESIGN_CAPACITY
197947. BQ27XXX_DM_DESIGN_ENERGY
197948. BQ27XXX_DM_REG_ROWS
197949. BQ27XXX_DM_SZ
197950. BQ27XXX_DM_TERMINATE_VOLTAGE
197951. BQ27XXX_FLAG_CFGUP
197952. BQ27XXX_FLAG_DSC
197953. BQ27XXX_FLAG_FC
197954. BQ27XXX_FLAG_OT
197955. BQ27XXX_FLAG_OTC
197956. BQ27XXX_FLAG_OTD
197957. BQ27XXX_FLAG_SOC1
197958. BQ27XXX_FLAG_SOCF
197959. BQ27XXX_FLAG_UT
197960. BQ27XXX_MANUFACTURER
197961. BQ27XXX_MSLEEP
197962. BQ27XXX_O_CFGUP
197963. BQ27XXX_O_OTDC
197964. BQ27XXX_O_RAM
197965. BQ27XXX_O_UTOT
197966. BQ27XXX_O_ZERO
197967. BQ27XXX_POWER_CONSTANT
197968. BQ27XXX_REG_AE
197969. BQ27XXX_REG_AI
197970. BQ27XXX_REG_AP
197971. BQ27XXX_REG_CTRL
197972. BQ27XXX_REG_CYCT
197973. BQ27XXX_REG_DCAP
197974. BQ27XXX_REG_FCC
197975. BQ27XXX_REG_FLAGS
197976. BQ27XXX_REG_INT_TEMP
197977. BQ27XXX_REG_MAX
197978. BQ27XXX_REG_NAC
197979. BQ27XXX_REG_SOC
197980. BQ27XXX_REG_TEMP
197981. BQ27XXX_REG_TTE
197982. BQ27XXX_REG_TTECP
197983. BQ27XXX_REG_TTES
197984. BQ27XXX_REG_TTF
197985. BQ27XXX_REG_VOLT
197986. BQ27XXX_RESET
197987. BQ27XXX_RS
197988. BQ27XXX_SEALED
197989. BQ27XXX_SET_CFGUPDATE
197990. BQ27XXX_SOFT_RESET
197991. BQ32K_CALIBRATION
197992. BQ32K_CENT
197993. BQ32K_CENT_EN
197994. BQ32K_CFG2
197995. BQ32K_HOURS_MASK
197996. BQ32K_MINUTES
197997. BQ32K_MINUTES_MASK
197998. BQ32K_OF
197999. BQ32K_SECONDS
198000. BQ32K_SECONDS_MASK
198001. BQ32K_STOP
198002. BQ32K_TCFE
198003. BQ32K_TCH2
198004. BQDA
198005. BQL_ATTR
198006. BQPATH_LOOPBACK
198007. BQUNKNOWN
198008. BR
198009. BR00
198010. BR00_BITBLT_CLIENT
198011. BR00_OP_COLOR_BLT
198012. BR00_OP_SRC_COPY_BLT
198013. BR02
198014. BR03
198015. BR04
198016. BR05
198017. BR06
198018. BR07
198019. BR08
198020. BR09
198021. BR10
198022. BR11
198023. BR12
198024. BR13
198025. BR13_SOLID_PATTERN
198026. BR14
198027. BR15
198028. BR16
198029. BR17
198030. BR18
198031. BR19
198032. BR2684_ENCAPS_AUTODETECT
198033. BR2684_ENCAPS_LLC
198034. BR2684_ENCAPS_VC
198035. BR2684_ETHERTYPE_LEN
198036. BR2684_FCSIN_IGNORE
198037. BR2684_FCSIN_NO
198038. BR2684_FCSIN_VERIFY
198039. BR2684_FCSOUT_GENERATE
198040. BR2684_FCSOUT_NO
198041. BR2684_FCSOUT_SENDZERO
198042. BR2684_FIND_BYIFNAME
198043. BR2684_FIND_BYNOTHING
198044. BR2684_FIND_BYNUM
198045. BR2684_FLAG_ROUTED
198046. BR2684_MEDIA_802_4
198047. BR2684_MEDIA_802_6
198048. BR2684_MEDIA_ETHERNET
198049. BR2684_MEDIA_FDDI
198050. BR2684_MEDIA_TR
198051. BR2684_PAD_LEN
198052. BR2684_PAYLOAD_BRIDGED
198053. BR2684_PAYLOAD_ROUTED
198054. BR2684_SETFILT
198055. BR2684_VCC
198056. BR2RCCAMASK
198057. BRACKETED_INCLUDE
198058. BRADIO_TH
198059. BRAD_STALL
198060. BRAILLE_KEY
198061. BRAINBOXES_US_101_PID
198062. BRAINBOXES_US_160_1_PID
198063. BRAINBOXES_US_160_2_PID
198064. BRAINBOXES_US_160_3_PID
198065. BRAINBOXES_US_160_4_PID
198066. BRAINBOXES_US_160_5_PID
198067. BRAINBOXES_US_160_6_PID
198068. BRAINBOXES_US_160_7_PID
198069. BRAINBOXES_US_160_8_PID
198070. BRAINBOXES_US_257_PID
198071. BRAINBOXES_US_279_1_PID
198072. BRAINBOXES_US_279_2_PID
198073. BRAINBOXES_US_279_3_PID
198074. BRAINBOXES_US_279_4_PID
198075. BRAINBOXES_US_313_PID
198076. BRAINBOXES_US_324_PID
198077. BRAINBOXES_US_346_1_PID
198078. BRAINBOXES_US_346_2_PID
198079. BRAINBOXES_US_357_PID
198080. BRAINBOXES_US_606_1_PID
198081. BRAINBOXES_US_606_2_PID
198082. BRAINBOXES_US_606_3_PID
198083. BRAINBOXES_US_701_1_PID
198084. BRAINBOXES_US_701_2_PID
198085. BRAINBOXES_US_842_1_PID
198086. BRAINBOXES_US_842_2_PID
198087. BRAINBOXES_US_842_3_PID
198088. BRAINBOXES_US_842_4_PID
198089. BRAINBOXES_VID
198090. BRAINBOXES_VX_001_PID
198091. BRAINBOXES_VX_012_PID
198092. BRAINBOXES_VX_023_PID
198093. BRAINBOXES_VX_034_PID
198094. BRAIND
198095. BRANCH
198096. BRANCH32
198097. BRANCH32_ANNUL
198098. BRANCHES
198099. BRANCH_12
198100. BRANCH_8
198101. BRANCH_ABSOLUTE
198102. BRANCH_ALWAYS
198103. BRANCH_AUX
198104. BRANCH_CLK_OFF
198105. BRANCH_ELIF
198106. BRANCH_ELSE
198107. BRANCH_END
198108. BRANCH_ENDIF
198109. BRANCH_FLAGS
198110. BRANCH_HALT
198111. BRANCH_HALT_DELAY
198112. BRANCH_HALT_ENABLE
198113. BRANCH_HALT_ENABLE_VOTED
198114. BRANCH_HALT_SKIP
198115. BRANCH_HALT_VOTED
198116. BRANCH_IF
198117. BRANCH_IFTRUE
198118. BRANCH_IF_ANY_CHEETAH
198119. BRANCH_IF_CHEETAH_BASE
198120. BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON
198121. BRANCH_IF_JALAPENO
198122. BRANCH_IF_SUN4V
198123. BRANCH_LIKELY_TAKEN
198124. BRANCH_MAIN
198125. BRANCH_NOC_FSM_STATUS_MASK
198126. BRANCH_NOC_FSM_STATUS_ON
198127. BRANCH_NOC_FSM_STATUS_SHIFT
198128. BRANCH_OPT
198129. BRANCH_PROFILE
198130. BRANCH_REG_NOT_ZERO
198131. BRANCH_REG_NOT_ZERO_ANNUL
198132. BRANCH_REG_ZERO
198133. BRANCH_REG_ZERO_ANNUL
198134. BRANCH_SET_LINK
198135. BRANCH_TO_C000
198136. BRANCH_VERSION
198137. BRANCH_VOTED
198138. BRASL_EXPOLINE
198139. BRA_BUS_ERR
198140. BRA_DEV_ERR
198141. BRA_DONE_STATUS
198142. BRA_FAILED_OP
198143. BRA_HOST_BUSY
198144. BRA_HSTS_ERR_MASK
198145. BRA_INTR
198146. BRA_INTREN
198147. BRA_INUSE_STS
198148. BRA_LAST__BYTE
198149. BRA_PEC_EN
198150. BRA_SMB_BASE_ADDR
198151. BRA_SMB_CMD
198152. BRA_SMB_CMD_BLOCK
198153. BRA_SMB_CMD_BLOCK_PROCESS
198154. BRA_SMB_CMD_BYTE
198155. BRA_SMB_CMD_BYTE_DATA
198156. BRA_SMB_CMD_I2CREAD
198157. BRA_SMB_CMD_PROCESS_CALL
198158. BRA_SMB_CMD_QUICK
198159. BRA_SMB_CMD_WORD_DATA
198160. BRA_START
198161. BRB1_REG_BRB1_INT_MASK
198162. BRB1_REG_BRB1_INT_STS
198163. BRB1_REG_BRB1_PRTY_MASK
198164. BRB1_REG_BRB1_PRTY_STS
198165. BRB1_REG_BRB1_PRTY_STS_CLR
198166. BRB1_REG_FREE_LIST_PRS_CRDT
198167. BRB1_REG_FULL_0_XOFF_THRESHOLD_0
198168. BRB1_REG_FULL_0_XOFF_THRESHOLD_1
198169. BRB1_REG_FULL_0_XON_THRESHOLD_0
198170. BRB1_REG_FULL_0_XON_THRESHOLD_1
198171. BRB1_REG_FULL_1_XOFF_THRESHOLD_0
198172. BRB1_REG_FULL_1_XOFF_THRESHOLD_1
198173. BRB1_REG_FULL_1_XON_THRESHOLD_0
198174. BRB1_REG_FULL_1_XON_THRESHOLD_1
198175. BRB1_REG_FULL_LB_XOFF_THRESHOLD
198176. BRB1_REG_FULL_LB_XON_THRESHOLD
198177. BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0
198178. BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0
198179. BRB1_REG_LB_GUARANTIED
198180. BRB1_REG_LB_GUARANTIED_HYST
198181. BRB1_REG_LL_RAM
198182. BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0
198183. BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0
198184. BRB1_REG_MAC_0_CLASS_0_GUARANTIED
198185. BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST
198186. BRB1_REG_MAC_0_CLASS_1_GUARANTIED
198187. BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST
198188. BRB1_REG_MAC_1_CLASS_0_GUARANTIED
198189. BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST
198190. BRB1_REG_MAC_1_CLASS_1_GUARANTIED
198191. BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST
198192. BRB1_REG_MAC_GUARANTIED_0
198193. BRB1_REG_MAC_GUARANTIED_1
198194. BRB1_REG_NUM_OF_FULL_BLOCKS
198195. BRB1_REG_NUM_OF_FULL_CYCLES_0
198196. BRB1_REG_NUM_OF_FULL_CYCLES_1
198197. BRB1_REG_NUM_OF_FULL_CYCLES_4
198198. BRB1_REG_NUM_OF_PAUSE_CYCLES_0
198199. BRB1_REG_NUM_OF_PAUSE_CYCLES_1
198200. BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0
198201. BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1
198202. BRB1_REG_PAUSE_0_XON_THRESHOLD_0
198203. BRB1_REG_PAUSE_0_XON_THRESHOLD_1
198204. BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0
198205. BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1
198206. BRB1_REG_PAUSE_1_XON_THRESHOLD_0
198207. BRB1_REG_PAUSE_1_XON_THRESHOLD_1
198208. BRB1_REG_PAUSE_HIGH_THRESHOLD_0
198209. BRB1_REG_PAUSE_HIGH_THRESHOLD_1
198210. BRB1_REG_PAUSE_LOW_THRESHOLD_0
198211. BRB1_REG_PER_CLASS_GUARANTY_MODE
198212. BRB1_REG_PORT_NUM_OCC_BLOCKS_0
198213. BRB1_REG_SOFT_RESET
198214. BRB_REG_BIG_RAM_ADDRESS
198215. BRB_REG_BIG_RAM_DATA
198216. BRB_REG_BIG_RAM_DATA_SIZE
198217. BRB_REG_DBG_DWORD_ENABLE
198218. BRB_REG_DBG_FORCE_FRAME
198219. BRB_REG_DBG_FORCE_VALID
198220. BRB_REG_DBG_SELECT
198221. BRB_REG_DBG_SHIFT
198222. BRB_REG_HEADER_SIZE
198223. BRB_SIZE
198224. BRCFG_INTERRUPT
198225. BRCFG_INTERRUPT_MASK
198226. BRCFG_PCIE_RX0
198227. BRCFG_PCIE_RX_MSG_FILTER
198228. BRCL_EXPOLINE
198229. BRCMFMAC_BCDC_H
198230. BRCMFMAC_BUS_H
198231. BRCMFMAC_CFG80211_H
198232. BRCMFMAC_COMMONRING_H
198233. BRCMFMAC_COMMON_H
198234. BRCMFMAC_CORE_H
198235. BRCMFMAC_COUNTRY_BUF_SZ
198236. BRCMFMAC_DEBUG_H
198237. BRCMFMAC_FIRMWARE_H
198238. BRCMFMAC_FLOWRING_H
198239. BRCMFMAC_MSGBUF_H
198240. BRCMFMAC_PCIE_H
198241. BRCMFMAC_PCIE_STATE_DOWN
198242. BRCMFMAC_PCIE_STATE_UP
198243. BRCMFMAC_PDATA_NAME
198244. BRCMFMAC_PROTO_H
198245. BRCMFMAC_SDIO_H
198246. BRCMFMAC_USB_H
198247. BRCMFMAC_USB_STATE_DL_DONE
198248. BRCMFMAC_USB_STATE_DL_FAIL
198249. BRCMFMAC_USB_STATE_DOWN
198250. BRCMFMAC_USB_STATE_SLEEP
198251. BRCMFMAC_USB_STATE_UP
198252. BRCMF_AMPDU_RX_REORDER_MAXFLOWS
198253. BRCMF_ANT_MAX
198254. BRCMF_ARP_OL_AGENT
198255. BRCMF_ARP_OL_HOST_AUTO_REPLY
198256. BRCMF_ARP_OL_PEER_AUTO_REPLY
198257. BRCMF_ARP_OL_SNOOP
198258. BRCMF_ASSOC_PARAMS_FIXED_SIZE
198259. BRCMF_BCDC_VAL
198260. BRCMF_BSSIDX_INVALID
198261. BRCMF_BSS_INFO_VERSION
198262. BRCMF_BSS_RSSI_ON_CHANNEL
198263. BRCMF_BTA_VAL
198264. BRCMF_BTCOEX_DISABLED
198265. BRCMF_BTCOEX_ENABLED
198266. BRCMF_BTCOEX_OPPR_WIN_TIME
198267. BRCMF_BT_DHCP_FLAG_FORCE_TIMEOUT
198268. BRCMF_BT_DHCP_IDLE
198269. BRCMF_BT_DHCP_OPPR_WIN
198270. BRCMF_BT_DHCP_REG41
198271. BRCMF_BT_DHCP_REG50
198272. BRCMF_BT_DHCP_REG51
198273. BRCMF_BT_DHCP_REG64
198274. BRCMF_BT_DHCP_REG65
198275. BRCMF_BT_DHCP_REG66
198276. BRCMF_BT_DHCP_REG68
198277. BRCMF_BT_DHCP_REG71
198278. BRCMF_BT_DHCP_START
198279. BRCMF_BT_SCO_SAMPLES
198280. BRCMF_BUSTYPE_PCIE
198281. BRCMF_BUSTYPE_SDIO
198282. BRCMF_BUSTYPE_USB
198283. BRCMF_BUS_DOWN
198284. BRCMF_BUS_UP
198285. BRCMF_BYTES_ON
198286. BRCMF_BYTES_VAL
198287. BRCMF_CHIP_H
198288. BRCMF_CHIP_MAX_MEMSIZE
198289. BRCMF_CONN_VAL
198290. BRCMF_CONSOLE
198291. BRCMF_CONSOLE_BUFADDR_OFFSET
198292. BRCMF_CONSOLE_BUFSIZE_OFFSET
198293. BRCMF_CONSOLE_WRITEIDX_OFFSET
198294. BRCMF_COUNTRY_BUF_SZ
198295. BRCMF_CTL_ON
198296. BRCMF_CTL_VAL
198297. BRCMF_C_DISASSOC
198298. BRCMF_C_DOWN
198299. BRCMF_C_GET_AP
198300. BRCMF_C_GET_ASSOCLIST
198301. BRCMF_C_GET_AUTH
198302. BRCMF_C_GET_BANDLIST
198303. BRCMF_C_GET_BCNPRD
198304. BRCMF_C_GET_BSSID
198305. BRCMF_C_GET_BSS_INFO
198306. BRCMF_C_GET_CHANNEL
198307. BRCMF_C_GET_CURR_RATESET
198308. BRCMF_C_GET_DTIMPRD
198309. BRCMF_C_GET_GET_PKTCNTS
198310. BRCMF_C_GET_INFRA
198311. BRCMF_C_GET_KEY_PRIMARY
198312. BRCMF_C_GET_LRL
198313. BRCMF_C_GET_PHYLIST
198314. BRCMF_C_GET_PHYTYPE
198315. BRCMF_C_GET_PHY_NOISE
198316. BRCMF_C_GET_PM
198317. BRCMF_C_GET_RADIO
198318. BRCMF_C_GET_RATE
198319. BRCMF_C_GET_REGULATORY
198320. BRCMF_C_GET_REVINFO
198321. BRCMF_C_GET_RSSI
198322. BRCMF_C_GET_SRL
198323. BRCMF_C_GET_SSID
198324. BRCMF_C_GET_VALID_CHANNELS
198325. BRCMF_C_GET_VAR
198326. BRCMF_C_GET_VERSION
198327. BRCMF_C_GET_WSEC
198328. BRCMF_C_REASSOC
198329. BRCMF_C_SCAN
198330. BRCMF_C_SCAN_RESULTS
198331. BRCMF_C_SCB_DEAUTHENTICATE_FOR_REASON
198332. BRCMF_C_SET_AP
198333. BRCMF_C_SET_ASSOC_PREFER
198334. BRCMF_C_SET_AUTH
198335. BRCMF_C_SET_BCNPRD
198336. BRCMF_C_SET_CHANNEL
198337. BRCMF_C_SET_COUNTRY
198338. BRCMF_C_SET_DTIMPRD
198339. BRCMF_C_SET_FAKEFRAG
198340. BRCMF_C_SET_INFRA
198341. BRCMF_C_SET_KEY
198342. BRCMF_C_SET_KEY_PRIMARY
198343. BRCMF_C_SET_LRL
198344. BRCMF_C_SET_PASSIVE_SCAN
198345. BRCMF_C_SET_PM
198346. BRCMF_C_SET_PROMISC
198347. BRCMF_C_SET_RADIO
198348. BRCMF_C_SET_REGULATORY
198349. BRCMF_C_SET_ROAM_DELTA
198350. BRCMF_C_SET_ROAM_TRIGGER
198351. BRCMF_C_SET_SCAN_CHANNEL_TIME
198352. BRCMF_C_SET_SCAN_PASSIVE_TIME
198353. BRCMF_C_SET_SCAN_UNASSOC_TIME
198354. BRCMF_C_SET_SCB_AUTHORIZE
198355. BRCMF_C_SET_SCB_DEAUTHORIZE
198356. BRCMF_C_SET_SCB_TIMEOUT
198357. BRCMF_C_SET_SRL
198358. BRCMF_C_SET_SSID
198359. BRCMF_C_SET_VAR
198360. BRCMF_C_SET_WSEC
198361. BRCMF_C_SET_WSEC_PMK
198362. BRCMF_C_TERMINATED
198363. BRCMF_C_UP
198364. BRCMF_D2H_DEV_D3_ACK
198365. BRCMF_D2H_DEV_DS_ENTER_REQ
198366. BRCMF_D2H_DEV_DS_EXIT_NOTE
198367. BRCMF_D2H_DEV_FWHALT
198368. BRCMF_D2H_MSGRING_CONTROL_COMPLETE
198369. BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE
198370. BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM
198371. BRCMF_D2H_MSGRING_RX_COMPLETE
198372. BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
198373. BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7
198374. BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
198375. BRCMF_D2H_MSGRING_TX_COMPLETE
198376. BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE
198377. BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7
198378. BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM
198379. BRCMF_DATA_ON
198380. BRCMF_DATA_VAL
198381. BRCMF_DCMD_MAXLEN
198382. BRCMF_DCMD_MEDLEN
198383. BRCMF_DCMD_SMLEN
198384. BRCMF_DEFAULT_BCN_TIMEOUT_ROAM_OFF
198385. BRCMF_DEFAULT_BCN_TIMEOUT_ROAM_ON
198386. BRCMF_DEFAULT_RXGLOM_SIZE
198387. BRCMF_DEFAULT_SCAN_CHANNEL_TIME
198388. BRCMF_DEFAULT_SCAN_UNASSOC_TIME
198389. BRCMF_DEFAULT_TXGLOM_SIZE
198390. BRCMF_DEF_MAX_RXBUFPOST
198391. BRCMF_DMA_D2H_RINGUPD_BUF_LEN
198392. BRCMF_DMA_D2H_SCRATCH_BUF_LEN
198393. BRCMF_DRIVER_FIRMWARE_VERSION_LEN
198394. BRCMF_ENUM_DEF
198395. BRCMF_ESCAN_BUF_SIZE
198396. BRCMF_ESCAN_REQ_VERSION
198397. BRCMF_ESCAN_TIMER_INTERVAL_MS
198398. BRCMF_EVENTING_MASK_LEN
198399. BRCMF_EVENT_MSG_FLUSHTXQ
198400. BRCMF_EVENT_MSG_GROUP
198401. BRCMF_EVENT_MSG_LINK
198402. BRCMF_EVENT_ON
198403. BRCMF_EVENT_VAL
198404. BRCMF_E_IF_ADD
198405. BRCMF_E_IF_CHANGE
198406. BRCMF_E_IF_DEL
198407. BRCMF_E_IF_FLAG_NOIF
198408. BRCMF_E_IF_ROLE_AP
198409. BRCMF_E_IF_ROLE_P2P_CLIENT
198410. BRCMF_E_IF_ROLE_P2P_GO
198411. BRCMF_E_IF_ROLE_STA
198412. BRCMF_E_IF_ROLE_WDS
198413. BRCMF_E_LAST
198414. BRCMF_E_REASON_BCNS_LOST
198415. BRCMF_E_REASON_BETTER_AP
198416. BRCMF_E_REASON_DEAUTH
198417. BRCMF_E_REASON_DIRECTED_ROAM
198418. BRCMF_E_REASON_DISASSOC
198419. BRCMF_E_REASON_FAST_ROAM_FAILED
198420. BRCMF_E_REASON_FWSUP_BAD_UCAST_WEP128
198421. BRCMF_E_REASON_FWSUP_BAD_UCAST_WEP40
198422. BRCMF_E_REASON_FWSUP_DEAUTH
198423. BRCMF_E_REASON_FWSUP_DECRYPT_KEY_DATA
198424. BRCMF_E_REASON_FWSUP_GRP_KEY_CIPHER
198425. BRCMF_E_REASON_FWSUP_GRP_MSG1_NO_GTK
198426. BRCMF_E_REASON_FWSUP_GTK_DECRYPT_FAIL
198427. BRCMF_E_REASON_FWSUP_MSG3_IE_MISMATCH
198428. BRCMF_E_REASON_FWSUP_MSG3_NO_GTK
198429. BRCMF_E_REASON_FWSUP_MSG3_TOO_MANY_IE
198430. BRCMF_E_REASON_FWSUP_NO_INSTALL_FLAG
198431. BRCMF_E_REASON_FWSUP_OTHER
198432. BRCMF_E_REASON_FWSUP_PW_KEY_CIPHER
198433. BRCMF_E_REASON_FWSUP_SEND_FAIL
198434. BRCMF_E_REASON_FWSUP_UNSUP_KEY_LEN
198435. BRCMF_E_REASON_FWSUP_WPA_PSK_M1_TMO
198436. BRCMF_E_REASON_FWSUP_WPA_PSK_M3_TMO
198437. BRCMF_E_REASON_FWSUP_WPA_PSK_TMO
198438. BRCMF_E_REASON_INITIAL_ASSOC
198439. BRCMF_E_REASON_LINK_BSSCFG_DIS
198440. BRCMF_E_REASON_LOW_RSSI
198441. BRCMF_E_REASON_MINTXRATE
198442. BRCMF_E_REASON_TDLS_PEER_CONNECTED
198443. BRCMF_E_REASON_TDLS_PEER_DISCONNECTED
198444. BRCMF_E_REASON_TDLS_PEER_DISCOVERED
198445. BRCMF_E_REASON_TSPEC_REJECTED
198446. BRCMF_E_REASON_TXFAIL
198447. BRCMF_E_STATUS_11HQUIET
198448. BRCMF_E_STATUS_ABORT
198449. BRCMF_E_STATUS_ATTEMPT
198450. BRCMF_E_STATUS_CS_ABORT
198451. BRCMF_E_STATUS_ERROR
198452. BRCMF_E_STATUS_FAIL
198453. BRCMF_E_STATUS_FWSUP_COMPLETED
198454. BRCMF_E_STATUS_FWSUP_PREP_G2
198455. BRCMF_E_STATUS_FWSUP_PREP_M2
198456. BRCMF_E_STATUS_FWSUP_PREP_M4
198457. BRCMF_E_STATUS_FWSUP_TIMEOUT
198458. BRCMF_E_STATUS_FWSUP_WAIT_G1
198459. BRCMF_E_STATUS_FWSUP_WAIT_M1
198460. BRCMF_E_STATUS_FWSUP_WAIT_M3
198461. BRCMF_E_STATUS_NEWASSOC
198462. BRCMF_E_STATUS_NEWSCAN
198463. BRCMF_E_STATUS_NOCHANS
198464. BRCMF_E_STATUS_NO_ACK
198465. BRCMF_E_STATUS_NO_NETWORKS
198466. BRCMF_E_STATUS_PARTIAL
198467. BRCMF_E_STATUS_SUCCESS
198468. BRCMF_E_STATUS_SUPPRESS
198469. BRCMF_E_STATUS_TIMEOUT
198470. BRCMF_E_STATUS_UNSOLICITED
198471. BRCMF_FEAT_DEF
198472. BRCMF_FEAT_LAST
198473. BRCMF_FEAT_LIST
198474. BRCMF_FEAT_QUIRK_LAST
198475. BRCMF_FIL_ACTION_FRAME_SIZE
198476. BRCMF_FIL_ON
198477. BRCMF_FIL_P2P_IF_CLIENT
198478. BRCMF_FIL_P2P_IF_DEV
198479. BRCMF_FIL_P2P_IF_DYNBCN_GO
198480. BRCMF_FIL_P2P_IF_GO
198481. BRCMF_FIL_VAL
198482. BRCMF_FIRSTREAD
198483. BRCMF_FLOWRING_HASHSIZE
198484. BRCMF_FLOWRING_HASH_AP
198485. BRCMF_FLOWRING_HASH_STA
198486. BRCMF_FLOWRING_HIGH
198487. BRCMF_FLOWRING_INVALID_ID
198488. BRCMF_FLOWRING_INVALID_IFIDX
198489. BRCMF_FLOWRING_LOW
198490. BRCMF_FWCON_ON
198491. BRCMF_FWCON_VAL
198492. BRCMF_FWEH_EVENT_ENUM_DEFLIST
198493. BRCMF_FWS_BORROW_DEFER_PERIOD
198494. BRCMF_FWS_FCMODE_EXPLICIT_CREDIT
198495. BRCMF_FWS_FCMODE_IMPLIED_CREDIT
198496. BRCMF_FWS_FCMODE_NONE
198497. BRCMF_FWS_FIFO_AC_BE
198498. BRCMF_FWS_FIFO_AC_BK
198499. BRCMF_FWS_FIFO_AC_VI
198500. BRCMF_FWS_FIFO_AC_VO
198501. BRCMF_FWS_FIFO_ATIM
198502. BRCMF_FWS_FIFO_BCMC
198503. BRCMF_FWS_FIFO_COUNT
198504. BRCMF_FWS_FIFO_FIRST
198505. BRCMF_FWS_FLAGS_CREDIT_STATUS_SIGNALS
198506. BRCMF_FWS_FLAGS_HOST_PROPTXSTATUS_ACTIVE
198507. BRCMF_FWS_FLAGS_HOST_RXREORDER_ACTIVE
198508. BRCMF_FWS_FLAGS_PSQ_GENERATIONFSM_ENABLE
198509. BRCMF_FWS_FLAGS_PSQ_ZERO_BUFFER_ENABLE
198510. BRCMF_FWS_FLAGS_RSSI_SIGNALS
198511. BRCMF_FWS_FLAGS_XONXOFF_SIGNALS
198512. BRCMF_FWS_FLOWCONTROL_HIWATER
198513. BRCMF_FWS_FLOWCONTROL_LOWATER
198514. BRCMF_FWS_HANGER_ITEM_STATE_FREE
198515. BRCMF_FWS_HANGER_ITEM_STATE_INUSE
198516. BRCMF_FWS_HANGER_ITEM_STATE_INUSE_SUPPRESSED
198517. BRCMF_FWS_HANGER_MAXITEMS
198518. BRCMF_FWS_HOSTIF_FLOWSTATE_OFF
198519. BRCMF_FWS_HOSTIF_FLOWSTATE_ON
198520. BRCMF_FWS_HTOD_FLAG_PKTFROMHOST
198521. BRCMF_FWS_HTOD_FLAG_PKT_REQUESTED
198522. BRCMF_FWS_MAC_DESC_ID_INVALID
198523. BRCMF_FWS_MAC_DESC_TABLE_SIZE
198524. BRCMF_FWS_MODE_GET_REUSESEQ
198525. BRCMF_FWS_MODE_REUSESEQ_SHIFT
198526. BRCMF_FWS_MODE_SET_REUSESEQ
198527. BRCMF_FWS_PSQ_LEN
198528. BRCMF_FWS_PSQ_PREC_COUNT
198529. BRCMF_FWS_RET_OK_NOSCHEDULE
198530. BRCMF_FWS_RET_OK_SCHEDULE
198531. BRCMF_FWS_SKBSTATE_DELAYED
198532. BRCMF_FWS_SKBSTATE_NEW
198533. BRCMF_FWS_SKBSTATE_SUPPRESSED
198534. BRCMF_FWS_SKBSTATE_TIM
198535. BRCMF_FWS_STATE_CLOSE
198536. BRCMF_FWS_STATE_OPEN
198537. BRCMF_FWS_TLV_DEF
198538. BRCMF_FWS_TLV_DEFLIST
198539. BRCMF_FWS_TXSTATUS_CORE_SUPPRESS
198540. BRCMF_FWS_TXSTATUS_DISCARD
198541. BRCMF_FWS_TXSTATUS_FW_PS_SUPPRESS
198542. BRCMF_FWS_TXSTATUS_FW_TOSSED
198543. BRCMF_FWS_TXSTATUS_HOST_TOSSED
198544. BRCMF_FWS_TXSTAT_FIFO_MASK
198545. BRCMF_FWS_TXSTAT_FIFO_SHIFT
198546. BRCMF_FWS_TXSTAT_FLAGS_MASK
198547. BRCMF_FWS_TXSTAT_FLAGS_SHIFT
198548. BRCMF_FWS_TXSTAT_FREERUN_MASK
198549. BRCMF_FWS_TXSTAT_FREERUN_SHIFT
198550. BRCMF_FWS_TXSTAT_GENERATION_MASK
198551. BRCMF_FWS_TXSTAT_GENERATION_SHIFT
198552. BRCMF_FWS_TXSTAT_HSLOT_MASK
198553. BRCMF_FWS_TXSTAT_HSLOT_SHIFT
198554. BRCMF_FWS_TYPE_INVALID
198555. BRCMF_FWS_TYPE_SEQ_LEN
198556. BRCMF_FW_ALTPATH_LEN
198557. BRCMF_FW_DEF
198558. BRCMF_FW_DEFAULT_BOARDREV
198559. BRCMF_FW_DEFAULT_PATH
198560. BRCMF_FW_ENTRY
198561. BRCMF_FW_MAX_NVRAM_SIZE
198562. BRCMF_FW_NAME_LEN
198563. BRCMF_FW_NVRAM_DEVPATH_LEN
198564. BRCMF_FW_NVRAM_PCIEDEV_LEN
198565. BRCMF_FW_REQF_OPTIONAL
198566. BRCMF_FW_TYPE_BINARY
198567. BRCMF_FW_TYPE_NVRAM
198568. BRCMF_FW_UNSUPPORTED
198569. BRCMF_GLOM_ON
198570. BRCMF_GLOM_VAL
198571. BRCMF_GSCAN_CFG_ALL_BUCKETS_IN_1ST_SCAN
198572. BRCMF_GSCAN_CFG_FLAGS_ALL_RESULTS
198573. BRCMF_GSCAN_CFG_FLAGS_CHANGE_ONLY
198574. BRCMF_GSCAN_CFG_VERSION
198575. BRCMF_H2D_HOST_D0_INFORM
198576. BRCMF_H2D_HOST_D0_INFORM_IN_USE
198577. BRCMF_H2D_HOST_D3_INFORM
198578. BRCMF_H2D_HOST_DS_ACK
198579. BRCMF_H2D_MSGRING_CONTROL_SUBMIT
198580. BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE
198581. BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM
198582. BRCMF_H2D_MSGRING_FLOWRING_IDSTART
198583. BRCMF_H2D_MSGRING_RXPOST_SUBMIT
198584. BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE
198585. BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM
198586. BRCMF_H2D_TXFLOWRING_ITEMSIZE
198587. BRCMF_H2D_TXFLOWRING_MAX_ITEM
198588. BRCMF_HDRS_ON
198589. BRCMF_HDRS_VAL
198590. BRCMF_HE_CAP_MCS_MAP_NSS_MAX
198591. BRCMF_IDLE_ACTIVE
198592. BRCMF_IDLE_INTERVAL
198593. BRCMF_INFO_VAL
198594. BRCMF_INIT_CLKCTL1
198595. BRCMF_INTR_VAL
198596. BRCMF_IOCTL_REQ_PKTID
198597. BRCMF_JOIN_PREF_BAND
198598. BRCMF_JOIN_PREF_RSSI
198599. BRCMF_JOIN_PREF_RSSI_BOOST
198600. BRCMF_JOIN_PREF_RSSI_DELTA
198601. BRCMF_JOIN_PREF_WPA
198602. BRCMF_MAXPMKID
198603. BRCMF_MAXRATES_IN_SET
198604. BRCMF_MAX_ASSOCLIST
198605. BRCMF_MAX_DEFAULT_KEYS
198606. BRCMF_MAX_IFS
198607. BRCMF_MCSSET_LEN
198608. BRCMF_MFP_CAPABLE
198609. BRCMF_MFP_NONE
198610. BRCMF_MFP_REQUIRED
198611. BRCMF_MSGBUF_DELAY_TXWORKER_THRS
198612. BRCMF_MSGBUF_MAX_EVENTBUF_POST
198613. BRCMF_MSGBUF_MAX_IOCTLRESPBUF_POST
198614. BRCMF_MSGBUF_MAX_PKT_SIZE
198615. BRCMF_MSGBUF_PKT_FLAGS_FRAME_802_11
198616. BRCMF_MSGBUF_PKT_FLAGS_FRAME_802_3
198617. BRCMF_MSGBUF_PKT_FLAGS_FRAME_MASK
198618. BRCMF_MSGBUF_PKT_FLAGS_PRIO_SHIFT
198619. BRCMF_MSGBUF_RXBUFPOST_THRESHOLD
198620. BRCMF_MSGBUF_TRICKLE_TXWORKER_THRS
198621. BRCMF_MSGBUF_TX_FLUSH_CNT1
198622. BRCMF_MSGBUF_TX_FLUSH_CNT2
198623. BRCMF_MSGBUF_UPDATE_RX_PTR_THRS
198624. BRCMF_MSGBUF_VAL
198625. BRCMF_ND_INFO_TIMEOUT
198626. BRCMF_NETIF_STOP_REASON_DISCONNECTED
198627. BRCMF_NETIF_STOP_REASON_FLOW
198628. BRCMF_NETIF_STOP_REASON_FWS_FC
198629. BRCMF_NLATTR_DATA
198630. BRCMF_NLATTR_LEN
198631. BRCMF_NLATTR_MAX
198632. BRCMF_NLATTR_UNSPEC
198633. BRCMF_NROF_COMMON_MSGRINGS
198634. BRCMF_NROF_D2H_COMMON_MSGRINGS
198635. BRCMF_NROF_H2D_COMMON_MSGRINGS
198636. BRCMF_NUMCHANNELS
198637. BRCMF_OBSS_COEX_AUTO
198638. BRCMF_OBSS_COEX_OFF
198639. BRCMF_OBSS_COEX_ON
198640. BRCMF_P2P_DISABLE_TIMEOUT
198641. BRCMF_P2P_STATUS_ACTION_TX_COMPLETED
198642. BRCMF_P2P_STATUS_ACTION_TX_NOACK
198643. BRCMF_P2P_STATUS_DISCOVER_LISTEN
198644. BRCMF_P2P_STATUS_ENABLED
198645. BRCMF_P2P_STATUS_FINDING_COMMON_CHANNEL
198646. BRCMF_P2P_STATUS_GO_NEG_PHASE
198647. BRCMF_P2P_STATUS_IF_ADD
198648. BRCMF_P2P_STATUS_IF_CHANGED
198649. BRCMF_P2P_STATUS_IF_CHANGING
198650. BRCMF_P2P_STATUS_IF_DEL
198651. BRCMF_P2P_STATUS_IF_DELETING
198652. BRCMF_P2P_STATUS_SENDING_ACT_FRAME
198653. BRCMF_P2P_STATUS_WAITING_NEXT_ACT_FRAME
198654. BRCMF_P2P_STATUS_WAITING_NEXT_AF_LISTEN
198655. BRCMF_P2P_TEMP_CHAN
198656. BRCMF_P2P_WILDCARD_SSID
198657. BRCMF_P2P_WILDCARD_SSID_LEN
198658. BRCMF_PCIE2_INTA
198659. BRCMF_PCIE2_INTB
198660. BRCMF_PCIE_ARMCR4REG_BANKIDX
198661. BRCMF_PCIE_ARMCR4REG_BANKPDA
198662. BRCMF_PCIE_BAR0_REG_SIZE
198663. BRCMF_PCIE_BAR0_WINDOW
198664. BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET
198665. BRCMF_PCIE_BAR0_WRAPPERBASE
198666. BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET
198667. BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL
198668. BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2
198669. BRCMF_PCIE_CFGREG_MSI_ADDR_H
198670. BRCMF_PCIE_CFGREG_MSI_ADDR_L
198671. BRCMF_PCIE_CFGREG_MSI_CAP
198672. BRCMF_PCIE_CFGREG_MSI_DATA
198673. BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1
198674. BRCMF_PCIE_CFGREG_PM_CSR
198675. BRCMF_PCIE_CFGREG_RBAR_CTRL
198676. BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG
198677. BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG
198678. BRCMF_PCIE_CFGREG_STATUS_CMD
198679. BRCMF_PCIE_DEVICE
198680. BRCMF_PCIE_DEVICE_SUB
198681. BRCMF_PCIE_FLAGS_DTOH_SPLIT
198682. BRCMF_PCIE_FLAGS_HTOD_SPLIT
198683. BRCMF_PCIE_FW_CODE
198684. BRCMF_PCIE_FW_NVRAM
198685. BRCMF_PCIE_FW_UP_TIMEOUT
198686. BRCMF_PCIE_INT_0
198687. BRCMF_PCIE_INT_1
198688. BRCMF_PCIE_INT_DEF
198689. BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB
198690. BRCMF_PCIE_MAX_SHARED_VERSION
198691. BRCMF_PCIE_MBDATA_TIMEOUT
198692. BRCMF_PCIE_MB_INT_D2H0_DB0
198693. BRCMF_PCIE_MB_INT_D2H0_DB1
198694. BRCMF_PCIE_MB_INT_D2H1_DB0
198695. BRCMF_PCIE_MB_INT_D2H1_DB1
198696. BRCMF_PCIE_MB_INT_D2H2_DB0
198697. BRCMF_PCIE_MB_INT_D2H2_DB1
198698. BRCMF_PCIE_MB_INT_D2H3_DB0
198699. BRCMF_PCIE_MB_INT_D2H3_DB1
198700. BRCMF_PCIE_MB_INT_D2H_DB
198701. BRCMF_PCIE_MB_INT_FN0_0
198702. BRCMF_PCIE_MB_INT_FN0_1
198703. BRCMF_PCIE_MIN_SHARED_VERSION
198704. BRCMF_PCIE_PCIE2REG_CONFIGADDR
198705. BRCMF_PCIE_PCIE2REG_CONFIGDATA
198706. BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0
198707. BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1
198708. BRCMF_PCIE_PCIE2REG_INTMASK
198709. BRCMF_PCIE_PCIE2REG_MAILBOXINT
198710. BRCMF_PCIE_PCIE2REG_MAILBOXMASK
198711. BRCMF_PCIE_REG_INTMASK
198712. BRCMF_PCIE_REG_INTSTATUS
198713. BRCMF_PCIE_REG_LINK_STATUS_CTRL
198714. BRCMF_PCIE_REG_MAP_SIZE
198715. BRCMF_PCIE_REG_SBMBX
198716. BRCMF_PCIE_SHARED_DMA_2B_IDX
198717. BRCMF_PCIE_SHARED_DMA_INDEX
198718. BRCMF_PCIE_SHARED_HOSTRDY_DB1
198719. BRCMF_PCIE_SHARED_VERSION_7
198720. BRCMF_PCIE_SHARED_VERSION_MASK
198721. BRCMF_PCIE_VAL
198722. BRCMF_PFN_MACADDR_CFG_VER
198723. BRCMF_PFN_MAC_OUI_ONLY
198724. BRCMF_PFN_SET_MAC_UNASSOC
198725. BRCMF_PNO_ENABLE_ADAPTSCAN_BIT
198726. BRCMF_PNO_ENABLE_BD_SCAN_BIT
198727. BRCMF_PNO_FREQ_EXPO_MAX
198728. BRCMF_PNO_HIDDEN_BIT
198729. BRCMF_PNO_IMMEDIATE_SCAN_BIT
198730. BRCMF_PNO_MAX_BUCKETS
198731. BRCMF_PNO_MAX_PFN_COUNT
198732. BRCMF_PNO_REPEAT
198733. BRCMF_PNO_REPORT_NO_BATCH
198734. BRCMF_PNO_REPORT_SEPARATELY_BIT
198735. BRCMF_PNO_SCAN_COMPLETE
198736. BRCMF_PNO_SCAN_INCOMPLETE
198737. BRCMF_PNO_SCHED_SCAN_MAX_PERIOD
198738. BRCMF_PNO_SCHED_SCAN_MIN_PERIOD
198739. BRCMF_PNO_SCHED_SCAN_PERIOD
198740. BRCMF_PNO_VERSION
198741. BRCMF_PNO_WPA_AUTH_ANY
198742. BRCMF_POSTBOOT_ID
198743. BRCMF_PRIMARY_KEY
198744. BRCMF_PROFILE_FWSUP_1X
198745. BRCMF_PROFILE_FWSUP_NONE
198746. BRCMF_PROFILE_FWSUP_PSK
198747. BRCMF_PROTO_BCDC
198748. BRCMF_PROTO_MSGBUF
198749. BRCMF_PROT_FW_SIGNAL_MAX_TXBYTES
198750. BRCMF_QUIRK_DEF
198751. BRCMF_QUIRK_LIST
198752. BRCMF_RAMSIZE_MAGIC
198753. BRCMF_RAMSIZE_OFFSET
198754. BRCMF_RING_D2H_RING_COUNT_OFFSET
198755. BRCMF_RING_H2D_RING_COUNT_OFFSET
198756. BRCMF_RING_H2D_RING_MEM_OFFSET
198757. BRCMF_RING_H2D_RING_STATE_OFFSET
198758. BRCMF_RING_LEN_ITEMS_OFFSET
198759. BRCMF_RING_MAX_ITEM_OFFSET
198760. BRCMF_RING_MEM_BASE_ADDR_OFFSET
198761. BRCMF_RING_MEM_SZ
198762. BRCMF_RING_STATE_SZ
198763. BRCMF_RSN_KCK_LENGTH
198764. BRCMF_RSN_KEK_LENGTH
198765. BRCMF_RSN_REPLAY_LEN
198766. BRCMF_RXBOUND
198767. BRCMF_RXREORDER_CURIDX_OFFSET
198768. BRCMF_RXREORDER_CURIDX_VALID
198769. BRCMF_RXREORDER_DEL_FLOW
198770. BRCMF_RXREORDER_EXPIDX_OFFSET
198771. BRCMF_RXREORDER_EXPIDX_VALID
198772. BRCMF_RXREORDER_FLAGS_OFFSET
198773. BRCMF_RXREORDER_FLOWID_OFFSET
198774. BRCMF_RXREORDER_FLUSH_ALL
198775. BRCMF_RXREORDER_MAXIDX_OFFSET
198776. BRCMF_RXREORDER_NEW_HOLE
198777. BRCMF_SCANTYPE_ACTIVE
198778. BRCMF_SCANTYPE_DEFAULT
198779. BRCMF_SCANTYPE_PASSIVE
198780. BRCMF_SCAN_CHANNEL_TIME
198781. BRCMF_SCAN_IE_LEN_MAX
198782. BRCMF_SCAN_JOIN_ACTIVE_DWELL_TIME_MS
198783. BRCMF_SCAN_JOIN_PASSIVE_DWELL_TIME_MS
198784. BRCMF_SCAN_JOIN_PROBE_INTERVAL_MS
198785. BRCMF_SCAN_ON
198786. BRCMF_SCAN_PARAMS_COUNT_MASK
198787. BRCMF_SCAN_PARAMS_FIXED_SIZE
198788. BRCMF_SCAN_PARAMS_NSSID_SHIFT
198789. BRCMF_SCAN_PASSIVE_TIME
198790. BRCMF_SCAN_STATUS_ABORT
198791. BRCMF_SCAN_STATUS_BUSY
198792. BRCMF_SCAN_STATUS_SUPPRESS
198793. BRCMF_SCAN_UNASSOC_TIME
198794. BRCMF_SCAN_VAL
198795. BRCMF_SCB_TIMEOUT_VALUE
198796. BRCMF_SDALIGN
198797. BRCMF_SDIOD_DATA
198798. BRCMF_SDIOD_DOWN
198799. BRCMF_SDIOD_NOMEDIUM
198800. BRCMF_SDIO_DEVICE
198801. BRCMF_SDIO_FT_NORMAL
198802. BRCMF_SDIO_FT_SUB
198803. BRCMF_SDIO_FT_SUPER
198804. BRCMF_SDIO_FW_CODE
198805. BRCMF_SDIO_FW_NVRAM
198806. BRCMF_SDIO_MAX_ACCESS_ERRORS
198807. BRCMF_SDIO_VAL
198808. BRCMF_SHARED_CONSOLE_ADDR_OFFSET
198809. BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET
198810. BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET
198811. BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET
198812. BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET
198813. BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET
198814. BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET
198815. BRCMF_SHARED_MAX_RXBUFPOST_OFFSET
198816. BRCMF_SHARED_RING_BASE_OFFSET
198817. BRCMF_SHARED_RING_INFO_ADDR_OFFSET
198818. BRCMF_SHARED_RX_DATAOFFSET_OFFSET
198819. BRCMF_SKB_HTOD_SEQ_FROMDRV_MASK
198820. BRCMF_SKB_HTOD_SEQ_FROMDRV_SHIFT
198821. BRCMF_SKB_HTOD_SEQ_FROMFW_MASK
198822. BRCMF_SKB_HTOD_SEQ_FROMFW_SHIFT
198823. BRCMF_SKB_HTOD_SEQ_NR_MASK
198824. BRCMF_SKB_HTOD_SEQ_NR_SHIFT
198825. BRCMF_SKB_HTOD_TAG_FIFO_MASK
198826. BRCMF_SKB_HTOD_TAG_FIFO_SHIFT
198827. BRCMF_SKB_HTOD_TAG_FLAGS_MASK
198828. BRCMF_SKB_HTOD_TAG_FLAGS_SHIFT
198829. BRCMF_SKB_HTOD_TAG_FREERUN_MASK
198830. BRCMF_SKB_HTOD_TAG_FREERUN_SHIFT
198831. BRCMF_SKB_HTOD_TAG_GENERATION_MASK
198832. BRCMF_SKB_HTOD_TAG_GENERATION_SHIFT
198833. BRCMF_SKB_HTOD_TAG_HSLOT_MASK
198834. BRCMF_SKB_HTOD_TAG_HSLOT_SHIFT
198835. BRCMF_SKB_IF_FLAGS_IF_AP_MASK
198836. BRCMF_SKB_IF_FLAGS_IF_AP_SHIFT
198837. BRCMF_SKB_IF_FLAGS_INDEX_MASK
198838. BRCMF_SKB_IF_FLAGS_INDEX_SHIFT
198839. BRCMF_SKB_IF_FLAGS_REQUESTED_MASK
198840. BRCMF_SKB_IF_FLAGS_REQUESTED_SHIFT
198841. BRCMF_SKB_IF_FLAGS_REQ_CREDIT_MASK
198842. BRCMF_SKB_IF_FLAGS_REQ_CREDIT_SHIFT
198843. BRCMF_SKB_IF_FLAGS_SIGNAL_ONLY_MASK
198844. BRCMF_SKB_IF_FLAGS_SIGNAL_ONLY_SHIFT
198845. BRCMF_SKB_IF_FLAGS_TRANSMIT_MASK
198846. BRCMF_SKB_IF_FLAGS_TRANSMIT_SHIFT
198847. BRCMF_STA_AMPDU_CAP
198848. BRCMF_STA_AMSDU_CAP
198849. BRCMF_STA_APSD_BE
198850. BRCMF_STA_APSD_BK
198851. BRCMF_STA_APSD_VI
198852. BRCMF_STA_APSD_VO
198853. BRCMF_STA_ASSOC
198854. BRCMF_STA_AUTHE
198855. BRCMF_STA_AUTHO
198856. BRCMF_STA_BRCM
198857. BRCMF_STA_DWDS
198858. BRCMF_STA_DWDS_CAP
198859. BRCMF_STA_MIMO_PS
198860. BRCMF_STA_MIMO_RTS
198861. BRCMF_STA_NONERP
198862. BRCMF_STA_N_CAP
198863. BRCMF_STA_PS
198864. BRCMF_STA_RIFS_CAP
198865. BRCMF_STA_SCBSTATS
198866. BRCMF_STA_VHT_CAP
198867. BRCMF_STA_WDS
198868. BRCMF_STA_WDS_LINKUP
198869. BRCMF_STA_WME
198870. BRCMF_STA_WPS
198871. BRCMF_TDLS_MANUAL_EP_CREATE
198872. BRCMF_TDLS_MANUAL_EP_DELETE
198873. BRCMF_TDLS_MANUAL_EP_DISCOVERY
198874. BRCMF_TIMER_VAL
198875. BRCMF_TRACEPOINT_H_
198876. BRCMF_TRACE_VAL
198877. BRCMF_TRAP_INFO_SIZE
198878. BRCMF_TXBF_MU_BFE_CAP
198879. BRCMF_TXBF_MU_BFR_CAP
198880. BRCMF_TXBF_SU_BFE_CAP
198881. BRCMF_TXBF_SU_BFR_CAP
198882. BRCMF_TXBOUND
198883. BRCMF_TXMINMAX
198884. BRCMF_TX_IOCTL_MAX_MSG_SIZE
198885. BRCMF_USB_CBCTL_READ
198886. BRCMF_USB_CBCTL_WRITE
198887. BRCMF_USB_DEVICE
198888. BRCMF_USB_FW_CODE
198889. BRCMF_USB_MAX_PKT_SIZE
198890. BRCMF_USB_NRXQ
198891. BRCMF_USB_NTXQ
198892. BRCMF_USB_RESET_GETVER_LOOP_CNT
198893. BRCMF_USB_RESET_GETVER_SPINWAIT
198894. BRCMF_USB_VAL
198895. BRCMF_VHT_CAP_MCS_MAP_NSS_MAX
198896. BRCMF_VIF_EVENT_TIMEOUT
198897. BRCMF_VIF_STATUS_AP_CREATED
198898. BRCMF_VIF_STATUS_ASSOC_SUCCESS
198899. BRCMF_VIF_STATUS_CONNECTED
198900. BRCMF_VIF_STATUS_CONNECTING
198901. BRCMF_VIF_STATUS_DISCONNECTING
198902. BRCMF_VIF_STATUS_EAP_SUCCESS
198903. BRCMF_VIF_STATUS_READY
198904. BRCMF_VNDR_CMDS_DCMD
198905. BRCMF_VNDR_CMDS_LAST
198906. BRCMF_VNDR_CMDS_UNSPEC
198907. BRCMF_VNDR_IE_ASSOCREQ_FLAG
198908. BRCMF_VNDR_IE_ASSOCRSP_FLAG
198909. BRCMF_VNDR_IE_AUTHRSP_FLAG
198910. BRCMF_VNDR_IE_BEACON_FLAG
198911. BRCMF_VNDR_IE_CUSTOM_FLAG
198912. BRCMF_VNDR_IE_DISREQ_FLAG
198913. BRCMF_VNDR_IE_DISRSP_FLAG
198914. BRCMF_VNDR_IE_GONCFM_FLAG
198915. BRCMF_VNDR_IE_GONREQ_FLAG
198916. BRCMF_VNDR_IE_GONRSP_FLAG
198917. BRCMF_VNDR_IE_INVREQ_FLAG
198918. BRCMF_VNDR_IE_INVRSP_FLAG
198919. BRCMF_VNDR_IE_IWAPID_FLAG
198920. BRCMF_VNDR_IE_P2PAF_SHIFT
198921. BRCMF_VNDR_IE_PRBREQ_FLAG
198922. BRCMF_VNDR_IE_PRBRSP_FLAG
198923. BRCMF_VNDR_IE_PRDREQ_FLAG
198924. BRCMF_VNDR_IE_PRDRSP_FLAG
198925. BRCMF_WD_POLL
198926. BRCMF_WOWL_ARPOFFLOAD
198927. BRCMF_WOWL_BCAST
198928. BRCMF_WOWL_BCN
198929. BRCMF_WOWL_DIS
198930. BRCMF_WOWL_EAPID
198931. BRCMF_WOWL_ENAB_HWRADIO
198932. BRCMF_WOWL_EXTMAGPAT
198933. BRCMF_WOWL_FW_HALT
198934. BRCMF_WOWL_GTK_FAILURE
198935. BRCMF_WOWL_KEYROT
198936. BRCMF_WOWL_LINKDOWN
198937. BRCMF_WOWL_M1
198938. BRCMF_WOWL_MAGIC
198939. BRCMF_WOWL_MAXPATTERNS
198940. BRCMF_WOWL_MAXPATTERNSIZE
198941. BRCMF_WOWL_MDNS_CONFLICT
198942. BRCMF_WOWL_MDNS_SERVICE
198943. BRCMF_WOWL_MIC_FAIL
198944. BRCMF_WOWL_NEEDTKIP1
198945. BRCMF_WOWL_NET
198946. BRCMF_WOWL_PATTERN_TYPE_ARP
198947. BRCMF_WOWL_PATTERN_TYPE_BITMAP
198948. BRCMF_WOWL_PATTERN_TYPE_NA
198949. BRCMF_WOWL_PFN_FOUND
198950. BRCMF_WOWL_PME_GPIO
198951. BRCMF_WOWL_RETR
198952. BRCMF_WOWL_SCANOL
198953. BRCMF_WOWL_SECURE
198954. BRCMF_WOWL_TCPKEEP_DATA
198955. BRCMF_WOWL_TCPKEEP_TIME
198956. BRCMF_WOWL_TST
198957. BRCMF_WOWL_UNASSOC
198958. BRCMF_WOWL_WPA2
198959. BRCMF_WSEC_MAX_PSK_LEN
198960. BRCMF_WSEC_PASSPHRASE
198961. BRCMNAND_CMD_ADDRESS
198962. BRCMNAND_CMD_EXT_ADDRESS
198963. BRCMNAND_CMD_START
198964. BRCMNAND_CORR_ADDR
198965. BRCMNAND_CORR_COUNT
198966. BRCMNAND_CORR_EXT_ADDR
198967. BRCMNAND_CORR_THRESHOLD
198968. BRCMNAND_CORR_THRESHOLD_EXT
198969. BRCMNAND_CS0_BASE
198970. BRCMNAND_CS1_BASE
198971. BRCMNAND_CS_ACC_CONTROL
198972. BRCMNAND_CS_CFG
198973. BRCMNAND_CS_CFG_EXT
198974. BRCMNAND_CS_SELECT
198975. BRCMNAND_CS_TIMING1
198976. BRCMNAND_CS_TIMING2
198977. BRCMNAND_CS_XOR
198978. BRCMNAND_FC_BASE
198979. BRCMNAND_HAS_1K_SECTORS
198980. BRCMNAND_HAS_CACHE_MODE
198981. BRCMNAND_HAS_PREFETCH
198982. BRCMNAND_HAS_WP
198983. BRCMNAND_ID
198984. BRCMNAND_ID_EXT
198985. BRCMNAND_INTFC_STATUS
198986. BRCMNAND_LL_OP
198987. BRCMNAND_LL_RDATA
198988. BRCMNAND_MIN_BLOCKSIZE
198989. BRCMNAND_MIN_DEVSIZE
198990. BRCMNAND_MIN_PAGESIZE
198991. BRCMNAND_OOB_READ_10_BASE
198992. BRCMNAND_OOB_READ_BASE
198993. BRCMNAND_OOB_WRITE_10_BASE
198994. BRCMNAND_OOB_WRITE_BASE
198995. BRCMNAND_SEMAPHORE
198996. BRCMNAND_UNCORR_ADDR
198997. BRCMNAND_UNCORR_COUNT
198998. BRCMNAND_UNCORR_EXT_ADDR
198999. BRCMSTB_DTU_CONFIG_ENTRIES
199000. BRCMSTB_DTU_COUNT
199001. BRCMSTB_DTU_STATE_MAP_ENTRIES
199002. BRCMSTB_HASH_LEN
199003. BRCMSTB_PANIC_MAGIC
199004. BRCMSTB_S3_MAGIC
199005. BRCMSTB_S3_MAGIC_MASK
199006. BRCMSTB_S3_MAGIC_SHORT
199007. BRCMSTB_WKTMR_ALARM
199008. BRCMSTB_WKTMR_COUNTER
199009. BRCMSTB_WKTMR_DEFAULT_FREQ
199010. BRCMSTB_WKTMR_EVENT
199011. BRCMSTB_WKTMR_PRESCALER
199012. BRCMSTB_WKTMR_PRESCALER_VAL
199013. BRCMS_10_MHZ
199014. BRCMS_20_MHZ
199015. BRCMS_40_MHZ
199016. BRCMS_ANTIDX_11N
199017. BRCMS_ANTSEL_11N
199018. BRCMS_ANTSEL_11N_0
199019. BRCMS_ANTSEL_11N_1
199020. BRCMS_ANT_ISAUTO_11N
199021. BRCMS_BSS_HT
199022. BRCMS_CHAN_CHANNEL
199023. BRCMS_CHAN_PHYTYPE
199024. BRCMS_CLR_MIMO_PLCP_AMPDU
199025. BRCMS_DFS_EU
199026. BRCMS_DFS_FCC
199027. BRCMS_DFS_TPC
199028. BRCMS_EIRP
199029. BRCMS_FLUSH_TIMEOUT
199030. BRCMS_GET_CCK_PLCP_LEN
199031. BRCMS_GET_MIMO_PLCP_LEN
199032. BRCMS_GF_PREAMBLE
199033. BRCMS_HWRXOFF
199034. BRCMS_ISLCNPHY
199035. BRCMS_ISNPHY
199036. BRCMS_ISSSLPNPHY
199037. BRCMS_IS_MIMO_PLCP_AMPDU
199038. BRCMS_IS_MIMO_PREAMBLE
199039. BRCMS_LED_AL_MASK
199040. BRCMS_LED_BEH_MASK
199041. BRCMS_LED_NO
199042. BRCMS_LED_RADIO
199043. BRCMS_LEGACY_5G_RATE_OFFSET
199044. BRCMS_LONG_PREAMBLE
199045. BRCMS_MAXMCS
199046. BRCMS_MAXMODULES
199047. BRCMS_MAXPWR_MIMO_TBL_SIZE
199048. BRCMS_MAX_MAC_SUSPEND
199049. BRCMS_MM_PREAMBLE
199050. BRCMS_NO_40MHZ
199051. BRCMS_NO_MIMO
199052. BRCMS_NO_OFDM
199053. BRCMS_NUMRATES
199054. BRCMS_NUM_RATES_CCK
199055. BRCMS_NUM_RATES_MCS_1_STREAM
199056. BRCMS_NUM_RATES_MCS_2_STREAM
199057. BRCMS_NUM_RATES_MCS_3_STREAM
199058. BRCMS_NUM_RATES_MCS_4_STREAM
199059. BRCMS_NUM_RATES_OFDM
199060. BRCMS_N_BW_20ALL
199061. BRCMS_N_BW_20IN2G_40IN5G
199062. BRCMS_N_BW_40ALL
199063. BRCMS_N_PREAMBLE_GF
199064. BRCMS_N_PREAMBLE_GF_BRCM
199065. BRCMS_N_PREAMBLE_MIXEDMODE
199066. BRCMS_N_PROTECTION_20IN40
199067. BRCMS_N_PROTECTION_MIXEDMODE
199068. BRCMS_N_PROTECTION_OFF
199069. BRCMS_N_PROTECTION_OPTIONAL
199070. BRCMS_N_SGI_20
199071. BRCMS_N_SGI_40
199072. BRCMS_N_TXRX_CHAIN0
199073. BRCMS_N_TXRX_CHAIN1
199074. BRCMS_PEAK_CONDUCTED
199075. BRCMS_PHY_11N_CAP
199076. BRCMS_PHY_WAR_PR51571
199077. BRCMS_PLCP_AUTO
199078. BRCMS_PLCP_LONG
199079. BRCMS_PLCP_SHORT
199080. BRCMS_PLLREQ_FLIP
199081. BRCMS_PLLREQ_RADIO_MON
199082. BRCMS_PLLREQ_SHARED
199083. BRCMS_PRB_RESP_TIMEOUT
199084. BRCMS_PROTECTION_AUTO
199085. BRCMS_PROTECTION_CTL_LOCAL
199086. BRCMS_PROTECTION_CTL_OFF
199087. BRCMS_PROTECTION_CTL_OVERLAP
199088. BRCMS_PROTECTION_CTS_ONLY
199089. BRCMS_PROTECTION_MMHDR_ONLY
199090. BRCMS_PROTECTION_OFF
199091. BRCMS_PROTECTION_ON
199092. BRCMS_PROT_G_OVR
199093. BRCMS_PROT_G_SPEC
199094. BRCMS_PROT_G_USER
199095. BRCMS_PROT_N_CFG
199096. BRCMS_PROT_N_CFG_OVR
199097. BRCMS_PROT_N_NONGF
199098. BRCMS_PROT_N_NONGF_OVR
199099. BRCMS_PROT_N_OBSS
199100. BRCMS_PROT_N_PAM_OVR
199101. BRCMS_PROT_N_USER
199102. BRCMS_PROT_OVERLAP
199103. BRCMS_RADAR_TYPE_EU
199104. BRCMS_RATES_CCK
199105. BRCMS_RATES_CCK_OFDM
199106. BRCMS_RATES_OFDM
199107. BRCMS_RATE_FLAG
199108. BRCMS_RATE_MASK
199109. BRCMS_RATE_MASK_FULL
199110. BRCMS_RSSI_EXCELLENT
199111. BRCMS_RSSI_GOOD
199112. BRCMS_RSSI_INVALID
199113. BRCMS_RSSI_LOW
199114. BRCMS_RSSI_MINVAL
199115. BRCMS_RSSI_NO_SIGNAL
199116. BRCMS_RSSI_VERY_GOOD
199117. BRCMS_RSSI_VERY_LOW
199118. BRCMS_SET_MIMO_PLCP_AMPDU
199119. BRCMS_SET_MIMO_PLCP_LEN
199120. BRCMS_SET_SHORTSLOT_OVERRIDE
199121. BRCMS_SGI_CAP_PHY
199122. BRCMS_SHORTSLOT_AUTO
199123. BRCMS_SHORTSLOT_OFF
199124. BRCMS_SHORTSLOT_ON
199125. BRCMS_SHORT_PREAMBLE
199126. BRCMS_STBC_CAP_PHY
199127. BRCMS_STF_SS_STBC_RX
199128. BRCMS_STF_SS_STBC_TX
199129. BRCMS_TEMPSENSE_PERIOD
199130. BRCMS_TXPWR_DB_FACTOR
199131. BRCMS_TXPWR_MAX
199132. BRCMS_TYPE_ADHOC
199133. BRCMS_TYPE_AP
199134. BRCMS_TYPE_STATION
199135. BRCMS_USE_COREFLAGS
199136. BRCMS_WAKE_OVERRIDE_CLKCTL
199137. BRCMS_WAKE_OVERRIDE_FORCEFAST
199138. BRCMS_WAKE_OVERRIDE_MACSUSPEND
199139. BRCMS_WAKE_OVERRIDE_PHYREG
199140. BRCMS_WAKE_OVERRIDE_TXFIFO
199141. BRCMU_BOARDREV_LEN
199142. BRCMU_CHAN_BAND_2G
199143. BRCMU_CHAN_BAND_5G
199144. BRCMU_CHAN_BW_160
199145. BRCMU_CHAN_BW_20
199146. BRCMU_CHAN_BW_40
199147. BRCMU_CHAN_BW_80
199148. BRCMU_CHAN_BW_80P80
199149. BRCMU_CHAN_SB_L
199150. BRCMU_CHAN_SB_LL
199151. BRCMU_CHAN_SB_LLL
199152. BRCMU_CHAN_SB_LLU
199153. BRCMU_CHAN_SB_LU
199154. BRCMU_CHAN_SB_LUL
199155. BRCMU_CHAN_SB_LUU
199156. BRCMU_CHAN_SB_NONE
199157. BRCMU_CHAN_SB_U
199158. BRCMU_CHAN_SB_UL
199159. BRCMU_CHAN_SB_ULL
199160. BRCMU_CHAN_SB_ULU
199161. BRCMU_CHAN_SB_UU
199162. BRCMU_CHAN_SB_UUL
199163. BRCMU_CHAN_SB_UUU
199164. BRCMU_CHSPEC_CHH_MASK
199165. BRCMU_CHSPEC_CHH_SHIFT
199166. BRCMU_CHSPEC_CHL_MASK
199167. BRCMU_CHSPEC_CHL_SHIFT
199168. BRCMU_CHSPEC_CH_MASK
199169. BRCMU_CHSPEC_CH_SHIFT
199170. BRCMU_CHSPEC_D11AC_BND_2G
199171. BRCMU_CHSPEC_D11AC_BND_3G
199172. BRCMU_CHSPEC_D11AC_BND_4G
199173. BRCMU_CHSPEC_D11AC_BND_5G
199174. BRCMU_CHSPEC_D11AC_BND_MASK
199175. BRCMU_CHSPEC_D11AC_BND_SHIFT
199176. BRCMU_CHSPEC_D11AC_BW_10
199177. BRCMU_CHSPEC_D11AC_BW_160
199178. BRCMU_CHSPEC_D11AC_BW_20
199179. BRCMU_CHSPEC_D11AC_BW_40
199180. BRCMU_CHSPEC_D11AC_BW_5
199181. BRCMU_CHSPEC_D11AC_BW_80
199182. BRCMU_CHSPEC_D11AC_BW_8080
199183. BRCMU_CHSPEC_D11AC_BW_MASK
199184. BRCMU_CHSPEC_D11AC_BW_SHIFT
199185. BRCMU_CHSPEC_D11AC_SB_L
199186. BRCMU_CHSPEC_D11AC_SB_LL
199187. BRCMU_CHSPEC_D11AC_SB_LLL
199188. BRCMU_CHSPEC_D11AC_SB_LLU
199189. BRCMU_CHSPEC_D11AC_SB_LU
199190. BRCMU_CHSPEC_D11AC_SB_LUL
199191. BRCMU_CHSPEC_D11AC_SB_LUU
199192. BRCMU_CHSPEC_D11AC_SB_MASK
199193. BRCMU_CHSPEC_D11AC_SB_SHIFT
199194. BRCMU_CHSPEC_D11AC_SB_U
199195. BRCMU_CHSPEC_D11AC_SB_UL
199196. BRCMU_CHSPEC_D11AC_SB_ULL
199197. BRCMU_CHSPEC_D11AC_SB_ULU
199198. BRCMU_CHSPEC_D11AC_SB_UU
199199. BRCMU_CHSPEC_D11AC_SB_UUL
199200. BRCMU_CHSPEC_D11AC_SB_UUU
199201. BRCMU_CHSPEC_D11N_BND_2G
199202. BRCMU_CHSPEC_D11N_BND_5G
199203. BRCMU_CHSPEC_D11N_BND_MASK
199204. BRCMU_CHSPEC_D11N_BND_SHIFT
199205. BRCMU_CHSPEC_D11N_BW_10
199206. BRCMU_CHSPEC_D11N_BW_20
199207. BRCMU_CHSPEC_D11N_BW_40
199208. BRCMU_CHSPEC_D11N_BW_MASK
199209. BRCMU_CHSPEC_D11N_BW_SHIFT
199210. BRCMU_CHSPEC_D11N_SB_L
199211. BRCMU_CHSPEC_D11N_SB_MASK
199212. BRCMU_CHSPEC_D11N_SB_N
199213. BRCMU_CHSPEC_D11N_SB_SHIFT
199214. BRCMU_CHSPEC_D11N_SB_U
199215. BRCMU_CHSPEC_INVALID
199216. BRCMU_D11AC_IOTYPE
199217. BRCMU_D11N_IOTYPE
199218. BRCMU_DOTREV_LEN
199219. BRCM_2GHZ_2412_2462
199220. BRCM_2GHZ_2467_2472
199221. BRCM_2G_25MHZ_OFFSET
199222. BRCM_5GHZ_5180_5240
199223. BRCM_5GHZ_5260_5320
199224. BRCM_5GHZ_5500_5700
199225. BRCM_5GHZ_5745_5825
199226. BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE
199227. BRCM_AVS_CPUFREQ_NAME
199228. BRCM_AVS_CPUFREQ_PREFIX
199229. BRCM_AVS_CPU_DATA
199230. BRCM_AVS_CPU_INTR
199231. BRCM_AVS_HOST_INTR
199232. BRCM_BAND_2G
199233. BRCM_BAND_5G
199234. BRCM_BAND_ALL
199235. BRCM_BAND_AUTO
199236. BRCM_BDC_DESC
199237. BRCM_BDC_NAME
199238. BRCM_BrPRED_ALL_NOT_TAKEN
199239. BRCM_BrPRED_ALL_TAKEN
199240. BRCM_BrPRED_BHT_ENABLE
199241. BRCM_BrPRED_PREDICT_BACKWARD
199242. BRCM_CC_43143_CHIP_ID
199243. BRCM_CC_43235_CHIP_ID
199244. BRCM_CC_43236_CHIP_ID
199245. BRCM_CC_43238_CHIP_ID
199246. BRCM_CC_43241_CHIP_ID
199247. BRCM_CC_43242_CHIP_ID
199248. BRCM_CC_4329_CHIP_ID
199249. BRCM_CC_4330_CHIP_ID
199250. BRCM_CC_43340_CHIP_ID
199251. BRCM_CC_43341_CHIP_ID
199252. BRCM_CC_4334_CHIP_ID
199253. BRCM_CC_4335_CHIP_ID
199254. BRCM_CC_43362_CHIP_ID
199255. BRCM_CC_4339_CHIP_ID
199256. BRCM_CC_43430_CHIP_ID
199257. BRCM_CC_4345_CHIP_ID
199258. BRCM_CC_43465_CHIP_ID
199259. BRCM_CC_4350_CHIP_ID
199260. BRCM_CC_43525_CHIP_ID
199261. BRCM_CC_4354_CHIP_ID
199262. BRCM_CC_43566_CHIP_ID
199263. BRCM_CC_43567_CHIP_ID
199264. BRCM_CC_43569_CHIP_ID
199265. BRCM_CC_4356_CHIP_ID
199266. BRCM_CC_43570_CHIP_ID
199267. BRCM_CC_4358_CHIP_ID
199268. BRCM_CC_4359_CHIP_ID
199269. BRCM_CC_43602_CHIP_ID
199270. BRCM_CC_4365_CHIP_ID
199271. BRCM_CC_43664_CHIP_ID
199272. BRCM_CC_4366_CHIP_ID
199273. BRCM_CC_4371_CHIP_ID
199274. BRCM_CL45VEN_EEE_CONTROL
199275. BRCM_CNTRY_BUF_SZ
199276. BRCM_CPU_PART_BRAHMA_B53
199277. BRCM_CPU_PART_VULCAN
199278. BRCM_DL_DMA
199279. BRCM_DL_HT
199280. BRCM_DL_INFO
199281. BRCM_DL_INT
199282. BRCM_DL_MAC80211
199283. BRCM_DL_RX
199284. BRCM_DL_TX
199285. BRCM_EG_CID_MASK
199286. BRCM_EG_PID_MASK
199287. BRCM_EG_RC_EXCEPTION
199288. BRCM_EG_RC_MAC_LEARN
199289. BRCM_EG_RC_MASK
199290. BRCM_EG_RC_MIRROR
199291. BRCM_EG_RC_PROT_SNOOP
199292. BRCM_EG_RC_PROT_TERM
199293. BRCM_EG_RC_RSVD
199294. BRCM_EG_RC_SWITCH
199295. BRCM_EG_TC_MASK
199296. BRCM_EG_TC_SHIFT
199297. BRCM_FAMILY_3390A0
199298. BRCM_FAMILY_7250B0
199299. BRCM_FAMILY_7260A0
199300. BRCM_FAMILY_7271A0
199301. BRCM_FAMILY_7278A0
199302. BRCM_FAMILY_7364A0
199303. BRCM_FAMILY_7366C0
199304. BRCM_FAMILY_74371A0
199305. BRCM_FAMILY_7439B0
199306. BRCM_FAMILY_7445D0
199307. BRCM_FAMILY_COUNT
199308. BRCM_GET_CURR_RATESET
199309. BRCM_GET_PHYLIST
199310. BRCM_HDR_P5_EN
199311. BRCM_HDR_P7_EN
199312. BRCM_HDR_P8_EN
199313. BRCM_ID
199314. BRCM_IG_DSTMAP1_MASK
199315. BRCM_IG_DSTMAP2_MASK
199316. BRCM_IG_TC_MASK
199317. BRCM_IG_TC_SHIFT
199318. BRCM_IG_TE_MASK
199319. BRCM_IG_TS_SHIFT
199320. BRCM_MAXRATE
199321. BRCM_MESSAGE_BATCH
199322. BRCM_MESSAGE_MAX
199323. BRCM_MESSAGE_SBA
199324. BRCM_MESSAGE_SPU
199325. BRCM_MESSAGE_UNKNOWN
199326. BRCM_OPCODE_MASK
199327. BRCM_OPCODE_SHIFT
199328. BRCM_OUI
199329. BRCM_PCIE_4350_DEVICE_ID
199330. BRCM_PCIE_4354_DEVICE_ID
199331. BRCM_PCIE_4354_RAW_DEVICE_ID
199332. BRCM_PCIE_43567_DEVICE_ID
199333. BRCM_PCIE_4356_DEVICE_ID
199334. BRCM_PCIE_43570_DEVICE_ID
199335. BRCM_PCIE_4358_DEVICE_ID
199336. BRCM_PCIE_4359_DEVICE_ID
199337. BRCM_PCIE_43602_2G_DEVICE_ID
199338. BRCM_PCIE_43602_5G_DEVICE_ID
199339. BRCM_PCIE_43602_DEVICE_ID
199340. BRCM_PCIE_43602_RAW_DEVICE_ID
199341. BRCM_PCIE_4365_2G_DEVICE_ID
199342. BRCM_PCIE_4365_5G_DEVICE_ID
199343. BRCM_PCIE_4365_DEVICE_ID
199344. BRCM_PCIE_4366_2G_DEVICE_ID
199345. BRCM_PCIE_4366_5G_DEVICE_ID
199346. BRCM_PCIE_4366_DEVICE_ID
199347. BRCM_PCIE_4371_DEVICE_ID
199348. BRCM_PCIE_VENDOR_ID_BROADCOM
199349. BRCM_PERFCTRL_TC
199350. BRCM_PHY_MODEL
199351. BRCM_PHY_REV
199352. BRCM_PSEUDO_PHY_ADDR
199353. BRCM_RATE_11M
199354. BRCM_RATE_12M
199355. BRCM_RATE_18M
199356. BRCM_RATE_1M
199357. BRCM_RATE_24M
199358. BRCM_RATE_2M
199359. BRCM_RATE_36M
199360. BRCM_RATE_48M
199361. BRCM_RATE_54M
199362. BRCM_RATE_5M5
199363. BRCM_RATE_6M
199364. BRCM_RATE_9M
199365. BRCM_REV
199366. BRCM_SATA_BCM7425
199367. BRCM_SATA_BCM7445
199368. BRCM_SATA_NSP
199369. BRCM_SATA_PHY_DSL_28NM
199370. BRCM_SATA_PHY_IPROC_NS2
199371. BRCM_SATA_PHY_IPROC_NSP
199372. BRCM_SATA_PHY_IPROC_SR
199373. BRCM_SATA_PHY_STB_28NM
199374. BRCM_SATA_PHY_STB_40NM
199375. BRCM_SBA_CMD_HAS_OUTPUT
199376. BRCM_SBA_CMD_HAS_RESP
199377. BRCM_SBA_CMD_TYPE_A
199378. BRCM_SBA_CMD_TYPE_B
199379. BRCM_SBA_CMD_TYPE_C
199380. BRCM_SET_BCNPRD
199381. BRCM_SET_CHANNEL
199382. BRCM_SET_LRL
199383. BRCM_SET_SRL
199384. BRCM_TAG_GET_PORT
199385. BRCM_TAG_GET_QUEUE
199386. BRCM_TAG_LEN
199387. BRCM_TAG_SET_PORT_QUEUE
199388. BRCM_USB_43143_DEVICE_ID
199389. BRCM_USB_43235_LINKSYS_DEVICE_ID
199390. BRCM_USB_43236_DEVICE_ID
199391. BRCM_USB_43242_DEVICE_ID
199392. BRCM_USB_43242_LG_DEVICE_ID
199393. BRCM_USB_43569_DEVICE_ID
199394. BRCM_USB_BCMFW_DEVICE_ID
199395. BRCM_USB_PHY_2_0
199396. BRCM_USB_PHY_3_0
199397. BRCM_USB_PHY_ID_MAX
199398. BRCM_USB_VENDOR_ID_BROADCOM
199399. BRCM_USB_VENDOR_ID_LG
199400. BRCM_USB_VENDOR_ID_LINKSYS
199401. BRCM_ZSC_ALL_REGS_SELECT
199402. BRCM_ZSC_CONFIG_LMB0En
199403. BRCM_ZSC_CONFIG_LMB1En
199404. BRCM_ZSC_CONFIG_REG
199405. BRCM_ZSC_RBUS_ADDR_MAPPING_REG0
199406. BRCM_ZSC_RBUS_ADDR_MAPPING_REG1
199407. BRCM_ZSC_RBUS_ADDR_MAPPING_REG2
199408. BRCM_ZSC_REQ_BUFFER_REG
199409. BRCM_ZSC_SCB0_ADDR_MAPPING_REG0
199410. BRCM_ZSC_SCB0_ADDR_MAPPING_REG1
199411. BRCM_ZSC_SCB1_ADDR_MAPPING_REG0
199412. BRCM_ZSC_SCB1_ADDR_MAPPING_REG1
199413. BRCTL_ADD_BRIDGE
199414. BRCTL_ADD_IF
199415. BRCTL_DEL_BRIDGE
199416. BRCTL_DEL_IF
199417. BRCTL_GET_BRIDGES
199418. BRCTL_GET_BRIDGE_INFO
199419. BRCTL_GET_FDB_ENTRIES
199420. BRCTL_GET_PORT_INFO
199421. BRCTL_GET_PORT_LIST
199422. BRCTL_GET_VERSION
199423. BRCTL_SET_AGEING_TIME
199424. BRCTL_SET_BRIDGE_FORWARD_DELAY
199425. BRCTL_SET_BRIDGE_HELLO_TIME
199426. BRCTL_SET_BRIDGE_MAX_AGE
199427. BRCTL_SET_BRIDGE_PRIORITY
199428. BRCTL_SET_BRIDGE_STP_STATE
199429. BRCTL_SET_GC_INTERVAL
199430. BRCTL_SET_PATH_COST
199431. BRCTL_SET_PORT_PRIORITY
199432. BRCTL_VERSION
199433. BRC_DATA_SIZE
199434. BRC_TYPE_CBR
199435. BRC_TYPE_NONE
199436. BRC_TYPE_VBR
199437. BRC_TYPE_VBR_LOW_DELAY
199438. BRD0_OK
199439. BRD1_OK
199440. BRDAC0
199441. BRDAC1
199442. BRDAC2
199443. BRDAC3
199444. BRDAC4
199445. BRDAC5
199446. BRDCFG_START
199447. BRDNOGEN
199448. BRDV_BAUD_MASK
199449. BRDY
199450. BRDY0
199451. BRDY1
199452. BRDY2
199453. BRDY3
199454. BRDY4
199455. BRDY5
199456. BRDY6
199457. BRDY7
199458. BRDY8
199459. BRDY9
199460. BRDYE
199461. BRDYENB
199462. BRDYM
199463. BRDYSTS
199464. BRD_CNT_ADDR_A
199465. BRD_CNT_ADDR_B
199466. BRD_OK
199467. BREAK
199468. BREAKADR0_MASK
199469. BREAKADR1_MASK
199470. BREAKADR2_MASK
199471. BREAKADR3_MASK
199472. BREAKEN0
199473. BREAKEN1
199474. BREAKEN2
199475. BREAKEN3
199476. BREAKINST
199477. BREAKINST_ARM
199478. BREAKINST_THUMB
199479. BREAKME
199480. BREAKMEHEADER
199481. BREAKPOINT
199482. BREAKPOINT_INSTRUCTION
199483. BREAKPOINT_INSTRUCTION_2
199484. BREAKPOINT_INTERRUPT
199485. BREAKPOINT_REQUEST
199486. BREAKPOINT_TRAP
199487. BREAK_BATCH
199488. BREAK_INST
199489. BREAK_INSTR
199490. BREAK_INSTR_SIZE
199491. BREAK_LOGLEVEL
199492. BREAK_MASK
199493. BREAK_MATH
199494. BREAK_OFF
199495. BREAK_ON
199496. BREAK_REQUEST
199497. BREAK_REQUEST_TYPE
199498. BREAK_TO_DEBUGGER
199499. BREAK_UNMAP
199500. BREAK_WRITE
199501. BREGEN
199502. BREGULATOR0STANDBY
199503. BREGULATOR1STANDBY
199504. BREGULATORPLLSTANDBY
199505. BREGULATOR_ADJUST
199506. BREG_ENABLE
199507. BREG_ENABLE_FORCE
199508. BREG_PRESENT
199509. BRENAB
199510. BRENABL
199511. BREQ_BSACK_MARK
199512. BREQ_MARK
199513. BRESTP
199514. BRES_DST_ERR_DEC
199515. BRFEND
199516. BRFGAIN
199517. BRFMOD
199518. BRFREGOFFSETMASK
199519. BRFSI_3WIRE
199520. BRFSI_3WIRECLOCK
199521. BRFSI_3WIREDATA
199522. BRFSI_3WIRELOAD
199523. BRFSI_3WIRERW
199524. BRFSI_ANTSW
199525. BRFSI_ANTSWB
199526. BRFSI_PAPE
199527. BRFSI_PAPE5G
199528. BRFSI_RFENV
199529. BRFSI_TRSW
199530. BRFSI_TRSWB
199531. BRFSTART
199532. BRFSW_RXDEFAULTANT
199533. BRFSW_RXOPTIONANT
199534. BRFSW_TXDEFAULTANT
199535. BRFSW_TXOPTIONANT
199536. BRGACR
199537. BRGARXDAR
199538. BRGARXTCNT
199539. BRGARXTCR
199540. BRGATXSAR
199541. BRGATXTCNT
199542. BRGATXTCR
199543. BRGCKR
199544. BRGCNT
199545. BRGCTRL_DETSERR
199546. BRGCTRL_SECBUSRESET
199547. BRGREG
199548. BRG_INT_CLK
199549. BRG_TO_BPS
199550. BRG_UART_CLK
199551. BRG_UART_CLK_DIV16
199552. BRH_OP
199553. BRI
199554. BRI1
199555. BRIDGE
199556. BRIDGE_101
199557. BRIDGE_102
199558. BRIDGE_103
199559. BRIDGE_9XX_ADDRESS_ERROR0
199560. BRIDGE_9XX_ADDRESS_ERROR1
199561. BRIDGE_9XX_ADDRESS_ERROR2
199562. BRIDGE_9XX_DRAM_BAR
199563. BRIDGE_9XX_DRAM_CHNL_TRANSLN
199564. BRIDGE_9XX_DRAM_LIMIT
199565. BRIDGE_9XX_DRAM_NODE_TRANSLN
199566. BRIDGE_9XX_FLASH_BAR
199567. BRIDGE_9XX_FLASH_BAR_LIMIT
199568. BRIDGE_9XX_PCIEIO_BASE0
199569. BRIDGE_9XX_PCIEIO_BASE1
199570. BRIDGE_9XX_PCIEIO_BASE2
199571. BRIDGE_9XX_PCIEIO_BASE3
199572. BRIDGE_9XX_PCIEIO_LIMIT0
199573. BRIDGE_9XX_PCIEIO_LIMIT1
199574. BRIDGE_9XX_PCIEIO_LIMIT2
199575. BRIDGE_9XX_PCIEIO_LIMIT3
199576. BRIDGE_9XX_PCIEMEM_BASE0
199577. BRIDGE_9XX_PCIEMEM_BASE1
199578. BRIDGE_9XX_PCIEMEM_BASE2
199579. BRIDGE_9XX_PCIEMEM_BASE3
199580. BRIDGE_9XX_PCIEMEM_LIMIT0
199581. BRIDGE_9XX_PCIEMEM_LIMIT1
199582. BRIDGE_9XX_PCIEMEM_LIMIT2
199583. BRIDGE_9XX_PCIEMEM_LIMIT3
199584. BRIDGE_ADDRESS_ERROR0
199585. BRIDGE_ADDRESS_ERROR1
199586. BRIDGE_ADDRESS_ERROR2
199587. BRIDGE_ADDR_ENTRY
199588. BRIDGE_AERR1_CLEAR
199589. BRIDGE_AERR1_DEV_STAT
199590. BRIDGE_AERR1_LOG1
199591. BRIDGE_AERR1_LOG2
199592. BRIDGE_AERR1_LOG3
199593. BRIDGE_AERR_CLEAR
199594. BRIDGE_AERR_DEV_STAT
199595. BRIDGE_AERR_INTR_EN
199596. BRIDGE_AERR_INTR_LOG1
199597. BRIDGE_AERR_INTR_LOG2
199598. BRIDGE_AERR_INTR_LOG3
199599. BRIDGE_AERR_UPG
199600. BRIDGE_ARB
199601. BRIDGE_ARB_FREEZE_GNT
199602. BRIDGE_ARB_HPRI_RING_B0
199603. BRIDGE_ARB_HPRI_RING_B1
199604. BRIDGE_ARB_HPRI_RING_B2
199605. BRIDGE_ARB_LPRI_RING_B0
199606. BRIDGE_ARB_LPRI_RING_B1
199607. BRIDGE_ARB_LPRI_RING_B2
199608. BRIDGE_ARB_REQ_WAIT_EN
199609. BRIDGE_ARB_REQ_WAIT_EN_MASK
199610. BRIDGE_ARB_REQ_WAIT_TICK
199611. BRIDGE_ARB_REQ_WAIT_TICK_MASK
199612. BRIDGE_ATE_RAM
199613. BRIDGE_ATE_RAM_SIZE
199614. BRIDGE_BAR
199615. BRIDGE_BITERR_INT_EN
199616. BRIDGE_BUSNUM_BAR0
199617. BRIDGE_BUSNUM_BAR1
199618. BRIDGE_BUSNUM_BAR2
199619. BRIDGE_BUSNUM_BAR3
199620. BRIDGE_BUSNUM_BAR4
199621. BRIDGE_BUSNUM_BAR5
199622. BRIDGE_BUSNUM_BAR6
199623. BRIDGE_BUS_GIO_TIMEOUT
199624. BRIDGE_BUS_PCI_RETRY_CNT
199625. BRIDGE_BUS_PCI_RETRY_HLD
199626. BRIDGE_BUS_PCI_RETRY_HLD_MASK
199627. BRIDGE_BUS_PCI_RETRY_MASK
199628. BRIDGE_BUS_TIMEOUT
199629. BRIDGE_CAUSE
199630. BRIDGE_CAUSE_OFF
199631. BRIDGE_CFG_0
199632. BRIDGE_CFG_4
199633. BRIDGE_CFG_BAR
199634. BRIDGE_CMS_WEIGHT
199635. BRIDGE_COMP_WEIGHT
199636. BRIDGE_CONFIG1_BASE
199637. BRIDGE_CONFIG_BASE
199638. BRIDGE_CONFIG_END
199639. BRIDGE_CONFIG_SLOT_SIZE
199640. BRIDGE_CONTROLLER
199641. BRIDGE_CREDIT
199642. BRIDGE_CTRL_CLR_RLLP_CNT
199643. BRIDGE_CTRL_CLR_TLLP_CNT
199644. BRIDGE_CTRL_EN_CLK33
199645. BRIDGE_CTRL_EN_CLK40
199646. BRIDGE_CTRL_EN_CLK50
199647. BRIDGE_CTRL_FLASH_WR_EN
199648. BRIDGE_CTRL_F_BAD_PKT
199649. BRIDGE_CTRL_IO_SWAP
199650. BRIDGE_CTRL_LLP_XBAR_CRD
199651. BRIDGE_CTRL_LLP_XBAR_CRD_MASK
199652. BRIDGE_CTRL_MAX_TRANS
199653. BRIDGE_CTRL_MAX_TRANS_MASK
199654. BRIDGE_CTRL_MEM_SWAP
199655. BRIDGE_CTRL_PAGE_SIZE
199656. BRIDGE_CTRL_RST
199657. BRIDGE_CTRL_RST_MASK
199658. BRIDGE_CTRL_RST_PIN
199659. BRIDGE_CTRL_SSRAM_128K
199660. BRIDGE_CTRL_SSRAM_1K
199661. BRIDGE_CTRL_SSRAM_512K
199662. BRIDGE_CTRL_SSRAM_64K
199663. BRIDGE_CTRL_SSRAM_SIZE
199664. BRIDGE_CTRL_SSRAM_SIZE_MASK
199665. BRIDGE_CTRL_SS_PAR_BAD
199666. BRIDGE_CTRL_SS_PAR_EN
199667. BRIDGE_CTRL_SYS_END
199668. BRIDGE_CTRL_WIDGET_ID
199669. BRIDGE_CTRL_WIDGET_ID_MASK
199670. BRIDGE_DBE_COUNTS
199671. BRIDGE_DEFEATURE
199672. BRIDGE_DEVICE
199673. BRIDGE_DEVICE0
199674. BRIDGE_DEVICE_MASK
199675. BRIDGE_DEVICE_OFF
199676. BRIDGE_DEVIO
199677. BRIDGE_DEVIO0
199678. BRIDGE_DEVIO1
199679. BRIDGE_DEVIO2
199680. BRIDGE_DEVIO_1MB
199681. BRIDGE_DEVIO_2MB
199682. BRIDGE_DEVIO_OFF
199683. BRIDGE_DEV_BARRIER
199684. BRIDGE_DEV_CNT
199685. BRIDGE_DEV_COH
199686. BRIDGE_DEV_D32_BITS
199687. BRIDGE_DEV_D64_BITS
199688. BRIDGE_DEV_DEV_IO_MEM
199689. BRIDGE_DEV_DEV_SIZE
199690. BRIDGE_DEV_DEV_SWAP
199691. BRIDGE_DEV_DIR_WRGA_EN
199692. BRIDGE_DEV_ERR_LOCK_EN
199693. BRIDGE_DEV_FORCE_PCI_PAR
199694. BRIDGE_DEV_GBR
199695. BRIDGE_DEV_OFF_ADDR_SHFT
199696. BRIDGE_DEV_OFF_MASK
199697. BRIDGE_DEV_PAGE_CHK_DIS
199698. BRIDGE_DEV_PMU_BITS
199699. BRIDGE_DEV_PMU_WRGA_EN
199700. BRIDGE_DEV_PRECISE
199701. BRIDGE_DEV_PREF
199702. BRIDGE_DEV_RT
199703. BRIDGE_DEV_SWAP_DIR
199704. BRIDGE_DEV_SWAP_PMU
199705. BRIDGE_DEV_VIRTUAL_EN
199706. BRIDGE_DIRECT_32_SEG_SIZE
199707. BRIDGE_DIRECT_32_TO_XTALK
199708. BRIDGE_DIRMAP_ADD512
199709. BRIDGE_DIRMAP_OFF
199710. BRIDGE_DIRMAP_OFF_ADDRSHFT
199711. BRIDGE_DIRMAP_RMF_64
199712. BRIDGE_DIRMAP_W_ID
199713. BRIDGE_DIRMAP_W_ID_SHFT
199714. BRIDGE_DIR_MAP
199715. BRIDGE_DMAENG_WEIGHT
199716. BRIDGE_DMA_DIRECT_BASE
199717. BRIDGE_DMA_DIRECT_SIZE
199718. BRIDGE_DMA_MAPPED_BASE
199719. BRIDGE_DMA_MAPPED_SIZE
199720. BRIDGE_DRAM_0_BAR
199721. BRIDGE_DRAM_1_BAR
199722. BRIDGE_DRAM_2_BAR
199723. BRIDGE_DRAM_3_BAR
199724. BRIDGE_DRAM_4_BAR
199725. BRIDGE_DRAM_5_BAR
199726. BRIDGE_DRAM_6_BAR
199727. BRIDGE_DRAM_7_BAR
199728. BRIDGE_DRAM_BAR
199729. BRIDGE_DRAM_CHNL_TRANSLN
199730. BRIDGE_DRAM_CHN_0_MTR_0_BAR
199731. BRIDGE_DRAM_CHN_0_MTR_1_BAR
199732. BRIDGE_DRAM_CHN_0_MTR_2_BAR
199733. BRIDGE_DRAM_CHN_0_MTR_3_BAR
199734. BRIDGE_DRAM_CHN_0_MTR_4_BAR
199735. BRIDGE_DRAM_CHN_0_MTR_5_BAR
199736. BRIDGE_DRAM_CHN_0_MTR_6_BAR
199737. BRIDGE_DRAM_CHN_0_MTR_7_BAR
199738. BRIDGE_DRAM_CHN_1_MTR_0_BAR
199739. BRIDGE_DRAM_CHN_1_MTR_1_BAR
199740. BRIDGE_DRAM_CHN_1_MTR_2_BAR
199741. BRIDGE_DRAM_CHN_1_MTR_3_BAR
199742. BRIDGE_DRAM_CHN_1_MTR_4_BAR
199743. BRIDGE_DRAM_CHN_1_MTR_5_BAR
199744. BRIDGE_DRAM_CHN_1_MTR_6_BAR
199745. BRIDGE_DRAM_CHN_1_MTR_7_BAR
199746. BRIDGE_DRAM_LIMIT
199747. BRIDGE_DRAM_NODE_TRANSLN
199748. BRIDGE_ENCAP
199749. BRIDGE_ERROR_INTERRUPT_EN
199750. BRIDGE_ERROR_INTR
199751. BRIDGE_ERRUPPR_ADDRMASK
199752. BRIDGE_ERRUPPR_DEVICE
199753. BRIDGE_ERRUPPR_DEVMASTER
199754. BRIDGE_ERRUPPR_DEVNUM_MASK
199755. BRIDGE_ERRUPPR_DEVNUM_SHFT
199756. BRIDGE_ERRUPPR_PCIVDEV
199757. BRIDGE_EVEN_RESP
199758. BRIDGE_EVNTCTR1_HI
199759. BRIDGE_EVNTCTR1_LOW
199760. BRIDGE_EVNTCTR2_HI
199761. BRIDGE_EVNTCTR2_LOW
199762. BRIDGE_EVNT_CNT_CTL2
199763. BRIDGE_EVNT_CNT_CTRL1
199764. BRIDGE_EVNT_CNT_CTRL2
199765. BRIDGE_EVNT_COUNTER1
199766. BRIDGE_EVNT_COUNTER2
199767. BRIDGE_EXTERNAL_FLASH
199768. BRIDGE_EXT_SSRAM
199769. BRIDGE_FLAGS_MASTER
199770. BRIDGE_FLAGS_SELF
199771. BRIDGE_FLASH_BAR
199772. BRIDGE_FLASH_BAR0
199773. BRIDGE_FLASH_BAR1
199774. BRIDGE_FLASH_BAR2
199775. BRIDGE_FLASH_BAR3
199776. BRIDGE_FLASH_LIMIT0
199777. BRIDGE_FLASH_LIMIT1
199778. BRIDGE_FLASH_LIMIT2
199779. BRIDGE_FLASH_LIMIT3
199780. BRIDGE_FLASH_WEIGHT
199781. BRIDGE_GIO_MEM32_BASE
199782. BRIDGE_GIO_MEM32_LIMIT
199783. BRIDGE_GIO_WEIGHT
199784. BRIDGE_HTCFG_BAR
199785. BRIDGE_HTINT_BAR
199786. BRIDGE_HTIO_BAR
199787. BRIDGE_HTMEM_BAR
199788. BRIDGE_HTPIC_BAR
199789. BRIDGE_HTSM_BAR
199790. BRIDGE_IMR_BAD_XREQ_PKT
199791. BRIDGE_IMR_BAD_XRESP_PKT
199792. BRIDGE_IMR_GIO_B_ENBL_ERR
199793. BRIDGE_IMR_GIO_MST_TIMEOUT
199794. BRIDGE_IMR_INT
199795. BRIDGE_IMR_INT_MSK
199796. BRIDGE_IMR_INVLD_ADDR
199797. BRIDGE_IMR_LLP_RCTY
199798. BRIDGE_IMR_LLP_REC_CBERR
199799. BRIDGE_IMR_LLP_REC_SNERR
199800. BRIDGE_IMR_LLP_TCTY
199801. BRIDGE_IMR_LLP_TX_RETRY
199802. BRIDGE_IMR_PCI_ABORT
199803. BRIDGE_IMR_PCI_MST_TIMEOUT
199804. BRIDGE_IMR_PCI_PARITY
199805. BRIDGE_IMR_PCI_PERR
199806. BRIDGE_IMR_PCI_RETRY_CNT
199807. BRIDGE_IMR_PCI_SERR
199808. BRIDGE_IMR_PMU_ESIZE_FAULT
199809. BRIDGE_IMR_REQ_XTLK_ERR
199810. BRIDGE_IMR_RESP_XTLK_ERR
199811. BRIDGE_IMR_SSRAM_PERR
199812. BRIDGE_IMR_UNEXP_RESP
199813. BRIDGE_IMR_UNSUPPORTED_XOP
199814. BRIDGE_IMR_XREAD_REQ_TIMEOUT
199815. BRIDGE_IMR_XREQ_FIFO_OFLOW
199816. BRIDGE_INTERNAL_ATES
199817. BRIDGE_INTMODE_CLR_PKT_EN
199818. BRIDGE_INT_ADDR
199819. BRIDGE_INT_ADDR0
199820. BRIDGE_INT_ADDR_DEST_IO
199821. BRIDGE_INT_ADDR_DEST_MEM
199822. BRIDGE_INT_ADDR_FLD
199823. BRIDGE_INT_ADDR_HOST
199824. BRIDGE_INT_ADDR_MASK
199825. BRIDGE_INT_ADDR_NASID_SHFT
199826. BRIDGE_INT_ADDR_OFF
199827. BRIDGE_INT_DEVICE
199828. BRIDGE_INT_DEV_MASK
199829. BRIDGE_INT_DEV_SET
199830. BRIDGE_INT_DEV_SHFT
199831. BRIDGE_INT_ENABLE
199832. BRIDGE_INT_HOST_ERR
199833. BRIDGE_INT_MODE
199834. BRIDGE_INT_RST_STAT
199835. BRIDGE_INT_STATUS
199836. BRIDGE_INT_TIMER0
199837. BRIDGE_INT_TIMER1
199838. BRIDGE_INT_TIMER1_CLR
199839. BRIDGE_INVERT_LED
199840. BRIDGE_IO_ACC
199841. BRIDGE_IO_MAX
199842. BRIDGE_IO_MIN
199843. BRIDGE_IPC_OUTPUT_PAYLOAD_REG
199844. BRIDGE_IRR_ALL_CLR
199845. BRIDGE_IRR_CRP_GRP
199846. BRIDGE_IRR_CRP_GRP_CLR
199847. BRIDGE_IRR_GIO_GRP
199848. BRIDGE_IRR_GIO_GRP_CLR
199849. BRIDGE_IRR_LLP_GRP
199850. BRIDGE_IRR_LLP_GRP_CLR
199851. BRIDGE_IRR_MULTI_CLR
199852. BRIDGE_IRR_PCI_GRP
199853. BRIDGE_IRR_PCI_GRP_CLR
199854. BRIDGE_IRR_REQ_DSP_GRP
199855. BRIDGE_IRR_REQ_DSP_GRP_CLR
199856. BRIDGE_IRR_RESP_BUF_GRP
199857. BRIDGE_IRR_RESP_BUF_GRP_CLR
199858. BRIDGE_IRR_SSRAM_GRP
199859. BRIDGE_IRR_SSRAM_GRP_CLR
199860. BRIDGE_ISR_BAD_XREQ_PKT
199861. BRIDGE_ISR_BAD_XRESP_PKT
199862. BRIDGE_ISR_ERRORS
199863. BRIDGE_ISR_ERROR_DUMP
199864. BRIDGE_ISR_ERROR_FATAL
199865. BRIDGE_ISR_GIO_B_ENBL_ERR
199866. BRIDGE_ISR_GIO_MST_TIMEOUT
199867. BRIDGE_ISR_INT
199868. BRIDGE_ISR_INT_MSK
199869. BRIDGE_ISR_INVLD_ADDR
199870. BRIDGE_ISR_LINK_ERROR
199871. BRIDGE_ISR_LLP_RCTY
199872. BRIDGE_ISR_LLP_REC_CBERR
199873. BRIDGE_ISR_LLP_REC_SNERR
199874. BRIDGE_ISR_LLP_TCTY
199875. BRIDGE_ISR_LLP_TX_RETRY
199876. BRIDGE_ISR_MULTI_ERR
199877. BRIDGE_ISR_PCIBUS_ERROR
199878. BRIDGE_ISR_PCIBUS_PIOERR
199879. BRIDGE_ISR_PCI_ABORT
199880. BRIDGE_ISR_PCI_MST_TIMEOUT
199881. BRIDGE_ISR_PCI_PARITY
199882. BRIDGE_ISR_PCI_PERR
199883. BRIDGE_ISR_PCI_RETRY_CNT
199884. BRIDGE_ISR_PCI_SERR
199885. BRIDGE_ISR_PMU_ESIZE_FAULT
199886. BRIDGE_ISR_REQ_XTLK_ERR
199887. BRIDGE_ISR_RESP_XTLK_ERR
199888. BRIDGE_ISR_SSRAM_PERR
199889. BRIDGE_ISR_UNEXP_RESP
199890. BRIDGE_ISR_UNSUPPORTED_XOP
199891. BRIDGE_ISR_XREAD_REQ_TIMEOUT
199892. BRIDGE_ISR_XREQ_FIFO_OFLOW
199893. BRIDGE_ISR_XTALK_ERROR
199894. BRIDGE_LINE_FLUSH0
199895. BRIDGE_LINE_FLUSH1
199896. BRIDGE_LOCAL_BASE
199897. BRIDGE_MASK
199898. BRIDGE_MASK_OFF
199899. BRIDGE_MAX_PIO_ADDR_IO
199900. BRIDGE_MAX_PIO_ADDR_MEM
199901. BRIDGE_MEM_ACC
199902. BRIDGE_MEM_MAX
199903. BRIDGE_MEM_MIN
199904. BRIDGE_MIN_PIO_ADDR_IO
199905. BRIDGE_MIN_PIO_ADDR_MEM
199906. BRIDGE_MODE
199907. BRIDGE_MODE_HAIRPIN
199908. BRIDGE_MODE_UNDEF
199909. BRIDGE_MODE_UNSPEC
199910. BRIDGE_MODE_VEB
199911. BRIDGE_MODE_VEPA
199912. BRIDGE_NBU_EVENT_CNT_CTL
199913. BRIDGE_NET_WEIGHT
199914. BRIDGE_NIC
199915. BRIDGE_NODE_ID
199916. BRIDGE_NT1003
199917. BRIDGE_NT1004
199918. BRIDGE_NT1005
199919. BRIDGE_NW800
199920. BRIDGE_NW801
199921. BRIDGE_NW802
199922. BRIDGE_ODD_RESP
199923. BRIDGE_OV511
199924. BRIDGE_OV511PLUS
199925. BRIDGE_OV518
199926. BRIDGE_OV518PLUS
199927. BRIDGE_OV519
199928. BRIDGE_OVFX2
199929. BRIDGE_PCIE0_WEIGHT
199930. BRIDGE_PCIE1_WEIGHT
199931. BRIDGE_PCIE2_WEIGHT
199932. BRIDGE_PCIE3_WEIGHT
199933. BRIDGE_PCIEIO_BASE0
199934. BRIDGE_PCIEIO_BASE1
199935. BRIDGE_PCIEIO_BASE2
199936. BRIDGE_PCIEIO_BASE3
199937. BRIDGE_PCIEIO_BASE4
199938. BRIDGE_PCIEIO_BASE5
199939. BRIDGE_PCIEIO_BASE6
199940. BRIDGE_PCIEIO_LIMIT0
199941. BRIDGE_PCIEIO_LIMIT1
199942. BRIDGE_PCIEIO_LIMIT2
199943. BRIDGE_PCIEIO_LIMIT3
199944. BRIDGE_PCIEIO_LIMIT4
199945. BRIDGE_PCIEIO_LIMIT5
199946. BRIDGE_PCIEIO_LIMIT6
199947. BRIDGE_PCIEMEM_BASE0
199948. BRIDGE_PCIEMEM_BASE1
199949. BRIDGE_PCIEMEM_BASE2
199950. BRIDGE_PCIEMEM_BASE3
199951. BRIDGE_PCIEMEM_BASE4
199952. BRIDGE_PCIEMEM_BASE5
199953. BRIDGE_PCIEMEM_BASE6
199954. BRIDGE_PCIEMEM_LIMIT0
199955. BRIDGE_PCIEMEM_LIMIT1
199956. BRIDGE_PCIEMEM_LIMIT2
199957. BRIDGE_PCIEMEM_LIMIT3
199958. BRIDGE_PCIEMEM_LIMIT4
199959. BRIDGE_PCIEMEM_LIMIT5
199960. BRIDGE_PCIEMEM_LIMIT6
199961. BRIDGE_PCIE_CFG_BASE
199962. BRIDGE_PCIE_CFG_LIMIT
199963. BRIDGE_PCIIO_XTALK_ALIAS_BASE
199964. BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
199965. BRIDGE_PCIXCFG_BAR
199966. BRIDGE_PCIXIO_BAR
199967. BRIDGE_PCIXMEM_BAR
199968. BRIDGE_PCI_BUS_TIMEOUT
199969. BRIDGE_PCI_CFG
199970. BRIDGE_PCI_CFG_BASE
199971. BRIDGE_PCI_CFG_LIMIT
199972. BRIDGE_PCI_ERR_LOWER
199973. BRIDGE_PCI_ERR_UPPER
199974. BRIDGE_PCI_IACK
199975. BRIDGE_PCI_IO_BASE
199976. BRIDGE_PCI_IO_LIMIT
199977. BRIDGE_PCI_MEM32_BASE
199978. BRIDGE_PCI_MEM32_LIMIT
199979. BRIDGE_PCI_MEM64_BASE
199980. BRIDGE_PCI_MEM64_LIMIT
199981. BRIDGE_PHNX_IO_BAR
199982. BRIDGE_PHYS_BASE
199983. BRIDGE_PIO32_XTALK_ALIAS_BASE
199984. BRIDGE_PIO32_XTALK_ALIAS_LIMIT
199985. BRIDGE_PIO64_XTALK_ALIAS_BASE
199986. BRIDGE_PIO64_XTALK_ALIAS_LIMIT
199987. BRIDGE_POE_WEIGHT
199988. BRIDGE_RAM_PERR
199989. BRIDGE_RESERVED1
199990. BRIDGE_RESP_CLEAR
199991. BRIDGE_RESP_ERRRUPPR_BUFMASK
199992. BRIDGE_RESP_ERRUPPR_BUFNUM
199993. BRIDGE_RESP_ERRUPPR_BUFNUM_MASK
199994. BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT
199995. BRIDGE_RESP_ERRUPPR_DEVICE
199996. BRIDGE_RESP_ERRUPPR_DEVNUM_MASK
199997. BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT
199998. BRIDGE_RESP_STATUS
199999. BRIDGE_REV_A
200000. BRIDGE_REV_B
200001. BRIDGE_REV_C
200002. BRIDGE_REV_D
200003. BRIDGE_RRB_CLEAR
200004. BRIDGE_RRB_DEV
200005. BRIDGE_RRB_EN
200006. BRIDGE_RRB_INUSE
200007. BRIDGE_RRB_PDEV
200008. BRIDGE_RRB_VALID
200009. BRIDGE_RRB_VDEV
200010. BRIDGE_SBE_COUNTS
200011. BRIDGE_SCRATCH0
200012. BRIDGE_SCRATCH1
200013. BRIDGE_SCRATCH2
200014. BRIDGE_SCRATCH3
200015. BRIDGE_SEC_WEIGHT
200016. BRIDGE_SN9C102P
200017. BRIDGE_SN9C105
200018. BRIDGE_SN9C110
200019. BRIDGE_SN9C120
200020. BRIDGE_SPCA504
200021. BRIDGE_SPCA504B
200022. BRIDGE_SPCA504C
200023. BRIDGE_SPCA533
200024. BRIDGE_SPCA536
200025. BRIDGE_SRAM_BAR
200026. BRIDGE_SSRAM_0K
200027. BRIDGE_SSRAM_128K
200028. BRIDGE_SSRAM_512K
200029. BRIDGE_SSRAM_64K
200030. BRIDGE_ST6422
200031. BRIDGE_STATUS_0
200032. BRIDGE_STAT_FLASH_SELECT
200033. BRIDGE_STAT_LLP_REC_CNT
200034. BRIDGE_STAT_LLP_TX_CNT
200035. BRIDGE_STAT_PCI_GIO_N
200036. BRIDGE_STAT_PENDING
200037. BRIDGE_STRUCT_VERSION
200038. BRIDGE_STV600
200039. BRIDGE_STV602
200040. BRIDGE_STV610
200041. BRIDGE_SYS2IO_CREDITS
200042. BRIDGE_TAG_ECC_ADDR_ERROR0
200043. BRIDGE_TAG_ECC_ADDR_ERROR1
200044. BRIDGE_TAG_ECC_ADDR_ERROR2
200045. BRIDGE_TMO_GIO_TIMEOUT_MASK
200046. BRIDGE_TMO_PCI_RETRY_CNT_MASK
200047. BRIDGE_TMO_PCI_RETRY_CNT_MAX
200048. BRIDGE_TMO_PCI_RETRY_HLD_MASK
200049. BRIDGE_TP6800
200050. BRIDGE_TP6810
200051. BRIDGE_TRACEBUF_ACCESS
200052. BRIDGE_TRACEBUF_CTRL
200053. BRIDGE_TRACEBUF_INIT
200054. BRIDGE_TRACEBUF_MATCH0
200055. BRIDGE_TRACEBUF_MATCH1
200056. BRIDGE_TRACEBUF_MATCH_HI
200057. BRIDGE_TRACEBUF_MATCH_LOW
200058. BRIDGE_TRACEBUF_READ_DATA0
200059. BRIDGE_TRACEBUF_READ_DATA1
200060. BRIDGE_TRACEBUF_READ_DATA2
200061. BRIDGE_TRACEBUF_READ_DATA3
200062. BRIDGE_TRACEBUF_STATUS
200063. BRIDGE_TYPE0_CFG_DEV
200064. BRIDGE_TYPE0_CFG_DEV0
200065. BRIDGE_TYPE0_CFG_DEVF
200066. BRIDGE_TYPE0_CFG_FUNC_OFF
200067. BRIDGE_TYPE0_CFG_SLOT_OFF
200068. BRIDGE_TYPE1_CFG
200069. BRIDGE_USB_WEIGHT
200070. BRIDGE_VC0321
200071. BRIDGE_VC0323
200072. BRIDGE_VIRT_BASE
200073. BRIDGE_VLAN_INFO_BRENTRY
200074. BRIDGE_VLAN_INFO_MASTER
200075. BRIDGE_VLAN_INFO_PVID
200076. BRIDGE_VLAN_INFO_RANGE_BEGIN
200077. BRIDGE_VLAN_INFO_RANGE_END
200078. BRIDGE_VLAN_INFO_UNTAGGED
200079. BRIDGE_W9968CF
200080. BRIDGE_WIDGET_MFGR_NUM
200081. BRIDGE_WIDGET_PART_NUM
200082. BRIDGE_WID_AUX_ERR
200083. BRIDGE_WID_CONTROL
200084. BRIDGE_WID_ERR_CMDWORD
200085. BRIDGE_WID_ERR_LOWER
200086. BRIDGE_WID_ERR_UPPER
200087. BRIDGE_WID_ID
200088. BRIDGE_WID_INT_LOWER
200089. BRIDGE_WID_INT_UPPER
200090. BRIDGE_WID_LLP
200091. BRIDGE_WID_REQ_TIMEOUT
200092. BRIDGE_WID_RESP_LOWER
200093. BRIDGE_WID_RESP_UPPER
200094. BRIDGE_WID_STAT
200095. BRIDGE_WID_TFLUSH
200096. BRIDGE_WID_TST_PIN_CTRL
200097. BRIDGE_WINS_BASE
200098. BRIDGE_WINS_CPU0_BASE
200099. BRIDGE_WINS_CPU1_BASE
200100. BRIDGE_WINS_SZ
200101. BRIDGE_WR_REQ_BUF
200102. BRIDGE_WR_REQ_BUF0
200103. BRIDGE_WR_REQ_BUF_OFF
200104. BRIDGE_XSTATS_MAX
200105. BRIDGE_XSTATS_MCAST
200106. BRIDGE_XSTATS_PAD
200107. BRIDGE_XSTATS_UNSPEC
200108. BRIDGE_XSTATS_VLAN
200109. BRIDGE_ZC301
200110. BRIDGE_ZC303
200111. BRIGHT
200112. BRIGHTNESS
200113. BRIGHTNESSOFF
200114. BRIGHTNESS_CTRL_BYTE
200115. BRIGHTNESS_DEF
200116. BRIGHTNESS_DEFAULT
200117. BRIGHTNESS_FORMATTER
200118. BRIGHTNESS_MASK
200119. BRIGHTNESS_MAX_LEVEL
200120. BRIGHTNESS_MIN_LEVEL
200121. BRIGHTNESS_REG
200122. BRIGHTNESS_SEM
200123. BRIGHTNESS_TOKEN
200124. BRIGHT_CNTL_BLOCK_ON
200125. BRIGHT_GREEN
200126. BRIGHT_RED
200127. BRIGHT_YELLOW
200128. BRI_PER_XBOW
200129. BRK64_OPCODE_KPROBES
200130. BRK64_OPCODE_UPROBES
200131. BRKD
200132. BRKE
200133. BRKIE
200134. BRKINT
200135. BRK_ABRT
200136. BRK_BUG
200137. BRK_DIVZERO
200138. BRK_KDB
200139. BRK_KPROBE_BP
200140. BRK_KPROBE_SSTEPBP
200141. BRK_MEMU
200142. BRK_MULOVF
200143. BRK_OVERFLOW
200144. BRK_RANGE
200145. BRK_RND_MASK
200146. BRK_SSTEPBP
200147. BRK_UPROBE
200148. BRK_UPROBE_XOL
200149. BRK_USERBP
200150. BRL_COND_FSYS_BUBBLE_DOWN
200151. BRL_INST
200152. BRL_UC_ROW
200153. BRM_status_show
200154. BRNF_PROTO_8021Q
200155. BRNF_PROTO_PPPOE
200156. BRNF_PROTO_UNCHANGED
200157. BRO1
200158. BROADCAST
200159. BROADCAST_ADDR
200160. BROADCAST_ADDRESS
200161. BROADCAST_ALL
200162. BROADCAST_CHANNEL_INITIAL
200163. BROADCAST_CHANNEL_VALID
200164. BROADCAST_DEAUTH
200165. BROADCAST_ENTRY
200166. BROADCAST_FLAG
200167. BROADCAST_HW_Q
200168. BROADCAST_LID_TYPE
200169. BROADCAST_ONE
200170. BROADCAST_PATTERN
200171. BROADCAST_PROMISC_ONLY
200172. BROADCAST_REGISTERED
200173. BROADCAST_RX_TIMEOUT_DEF_VALUE
200174. BROADCAST_SCAN
200175. BROADCAST_STORM_PROTECTION_RATE
200176. BROADCAST_STORM_PROT_RATE
200177. BROADCAST_STORM_RATE
200178. BROADCAST_STORM_RATE_HI
200179. BROADCAST_STORM_RATE_LO
200180. BROADCAST_STORM_VALUE
200181. BROADCOM_MII_REG4
200182. BROADCOM_MII_REG5
200183. BROADCOM_MII_REG7
200184. BROADCOM_MII_REG8
200185. BROADCOM_OUI
200186. BROADCOM_T4
200187. BROADWELL
200188. BROAD_EN
200189. BROKEN_ACQUIRE
200190. BROKEN_ACQUIRED
200191. BROKEN_ADDRCHG_REV
200192. BROKEN_BIOS
200193. BROKEN_CONTENDED
200194. BROKEN_EEPROM_DRIVER_DATA
200195. BROKEN_GRAPHICS_PROGRAMS
200196. BROKEN_MAX
200197. BROKEN_MSG_ADDR_HI
200198. BROKEN_MSG_ADDR_LO
200199. BROKEN_RELEASE
200200. BROKEN_X86_ALIGNMENT
200201. BROM_BR
200202. BROM_DT
200203. BROM_MODE
200204. BROM_RD
200205. BROM_REG
200206. BROM_SR
200207. BROM_WR
200208. BROOKTREE_878_DEVICE
200209. BROPT_GROUP_ADDR_SET
200210. BROPT_HAS_IPV6_ADDR
200211. BROPT_MTU_SET_BY_USER
200212. BROPT_MULTICAST_ENABLED
200213. BROPT_MULTICAST_QUERIER
200214. BROPT_MULTICAST_QUERY_USE_IFADDR
200215. BROPT_MULTICAST_STATS_ENABLED
200216. BROPT_NEIGH_SUPPRESS_ENABLED
200217. BROPT_NF_CALL_ARPTABLES
200218. BROPT_NF_CALL_IP6TABLES
200219. BROPT_NF_CALL_IPTABLES
200220. BROPT_NO_LL_LEARN
200221. BROPT_VLAN_BRIDGE_BINDING
200222. BROPT_VLAN_ENABLED
200223. BROPT_VLAN_STATS_ENABLED
200224. BROPT_VLAN_STATS_PER_PORT
200225. BROWNSTONE_NR_IRQS
200226. BROXTON_PMIC_WC_HRV
200227. BRPORT_ATTR
200228. BRPORT_ATTR_FLAG
200229. BRPORT_ATTR_RAW
200230. BRPRIV
200231. BRP_EXT_BRPE_MASK
200232. BRP_EXT_BRPE_SHIFT
200233. BRRA
200234. BRRB
200235. BRR_EN
200236. BRRx_MASK
200237. BRSRC
200238. BRSR_ACKSHORTPMB
200239. BRSR_AckShortPmb
200240. BRSSI_GEN
200241. BRSSI_H
200242. BRSSI_TABLE_SELECT
200243. BRST
200244. BRSTCNTRL
200245. BRST_LEN
200246. BRST_SIZE
200247. BRS_CTRL
200248. BRS_READY
200249. BRT
200250. BRTAKEN
200251. BRTL8256REG_MODE_CTRL0
200252. BRTL8256REG_MODE_CTRL1
200253. BRTL8256REG_RXLPFBW
200254. BRTL8256REG_TXLPFBW
200255. BRTL8258_RSSILPFBW
200256. BRTL8258_RXLPFBW
200257. BRTL8258_TXLPFBW
200258. BRT_MASK
200259. BRT_MODE_MASK
200260. BRT_MODE_SHFT
200261. BRUSH_SCALE
200262. BRUSH_SOLIDCOLOR
200263. BRUSH_Y_X
200264. BRXAGC_EN
200265. BRXAGC_FREEZE_THRES
200266. BRXAGC_FREEZE_THRES_MODE
200267. BRXAGC_MIN
200268. BRXAGC_TOGETHEREN
200269. BRXAGC_TOGETHER_EN
200270. BRXANTENNA_POWER_SHIFT
200271. BRXEVM1ST
200272. BRXEVM2ND
200273. BRXFRAME_FUARD_COUNTER_L
200274. BRXHP2RX
200275. BRXHPCCKINI
200276. BRXHPSETTLE_BBP
200277. BRXHPTX
200278. BRXHP_BBP1
200279. BRXHP_BBP2
200280. BRXHP_BBP3
200281. BRXHP_FINAL
200282. BRXHP_INI
200283. BRXHP_RSSI
200284. BRXHP_TRLNA
200285. BRXHTAGC_EN
200286. BRXHTAGC_MIN
200287. BRXHTDAGC_EN
200288. BRXHTSETTLE_BBPPW
200289. BRXHTSETTLE_HSSI
200290. BRXHTSETTLE_IDLE
200291. BRXHTSETTLE_RESERVED
200292. BRXHTSETTLE_RXHP
200293. BRXHT_RXHP_BBP
200294. BRXHT_RXHP_EN
200295. BRXHT_RXHP_FINAL
200296. BRXIQIMB_A
200297. BRXIQIMB_B
200298. BRXIQIMB_C
200299. BRXIQIMB_D
200300. BRXMAC_ALIGN_ERR_CNT
200301. BRXMAC_ALIGN_ERR_CNT_COUNT
200302. BRXMAC_BYTE_CNT
200303. BRXMAC_BYTE_CNT_COUNT
200304. BRXMAC_CODE_VIOL_ERR_CNT
200305. BRXMAC_CODE_VIOL_ERR_CNT_COUNT
200306. BRXMAC_CONFIG
200307. BRXMAC_CONFIG_ADDR_FILT_EN
200308. BRXMAC_CONFIG_DISCARD_DIS
200309. BRXMAC_CONFIG_ENABLE
200310. BRXMAC_CONFIG_HASH_FILT_EN
200311. BRXMAC_CONFIG_PROMISC
200312. BRXMAC_CONFIG_PROMISC_GRP
200313. BRXMAC_CONFIG_STRIP_FCS
200314. BRXMAC_CONFIG_STRIP_PAD
200315. BRXMAC_CRC_ERR_CNT
200316. BRXMAC_FRAME_CNT
200317. BRXMAC_FRAME_CNT_COUNT
200318. BRXMAC_MAX_LEN_ERR_CNT
200319. BRXMAC_STATUS
200320. BRXMAC_STATUS_ALIGN_ERR_EXP
200321. BRXMAC_STATUS_CRC_ERR_EXP
200322. BRXMAC_STATUS_FRAME_CNT_EXP
200323. BRXMAC_STATUS_LEN_ERR_EXP
200324. BRXMAC_STATUS_MASK
200325. BRXMAC_STATUS_OVERFLOW
200326. BRXMAC_STATUS_RX_PKT
200327. BRXMAC_SW_RST
200328. BRXMAC_SW_RST_RESET
200329. BRXMF_HOLD
200330. BRXNB_NOTCH
200331. BRXPATH
200332. BRXPATH_A
200333. BRXPATH_B
200334. BRXPATH_C
200335. BRXPATH_D
200336. BRXPD_DC_COUNT_MAX
200337. BRXPD_DELAY_TH
200338. BRXPD_DELAY_TH1
200339. BRXPD_DELAY_TH2
200340. BRXPROCESS_DELAY
200341. BRXPROCESS_TIME_BBPPW
200342. BRXPROCESS_TIME_DAGC
200343. BRXPW_RADIO_EN
200344. BRXPW_RADIO_TH
200345. BRXQUICK_AGCEN
200346. BRXRSSI_CMP_EN
200347. BRXSC
200348. BRXSEARCHRANGE_GI2_EARLY
200349. BRXSETTLE_ANTSW
200350. BRXSETTLE_ANTSW_RSSI
200351. BRXSETTLE_BBP
200352. BRXSETTLE_HSSI
200353. BRXSETTLE_LNA
200354. BRXSETTLE_RSSI
200355. BRXSETTLE_RXHP
200356. BRXSETTLE_TRSW
200357. BRXSGI_GUARD_L
200358. BRXSGI_SEARCH_L
200359. BRXSGI_TH
200360. BRXSNR_A
200361. BRXSNR_B
200362. BRXSNR_C
200363. BRXSNR_D
200364. BRX_AGCSHIFT
200365. BRX_AGC_ADDRESS_FOR_LNA
200366. BRX_AGC_FREEZE_THRES
200367. BRX_ANTDIV_EN
200368. BRX_DCNF_TYPE
200369. BRX_DFIR_MODE
200370. BRX_FREEZESTEP_AGC0
200371. BRX_FREEZESTEP_AGC1
200372. BRX_FREEZESTEP_AGC2
200373. BRX_FREEZESTEP_AGC3
200374. BRX_HIGHPOWER_FLOW
200375. BRX_HT
200376. BRX_HT_BW
200377. BRX_INITIALGAIN
200378. BRX_LDC_OFFSET
200379. BRX_MAX_SIZE
200380. BRX_MIN_SIZE
200381. BRX_NAME
200382. BRX_OVERFLOW_CHECKTYPE
200383. BRX_PAD_SINK
200384. BRX_PESUDO_NOISESTATE_A
200385. BRX_PESUDO_NOISESTATE_B
200386. BRX_PESUDO_NOISESTATE_C
200387. BRX_PESUDO_NOISESTATE_D
200388. BRX_PESUDO_NOISE_A
200389. BRX_PESUDO_NOISE_B
200390. BRX_PESUDO_NOISE_C
200391. BRX_PESUDO_NOISE_D
200392. BRX_PESUDO_NOISE_ON
200393. BRX_QDC_OFFSET
200394. BR_ABORT
200395. BR_ACQUIRE
200396. BR_ACQUIRE_RESULT
200397. BR_ADDR
200398. BR_ADMIN_COST
200399. BR_ALWAYS
200400. BR_ATTEMPT_ACQUIRE
200401. BR_AT_MSK
200402. BR_AUTO_MASK
200403. BR_BA
200404. BR_BA_MSK
200405. BR_BA_SHIFT
200406. BR_BCAST_FLOOD
200407. BR_BCC
200408. BR_BEQ
200409. BR_BGE
200410. BR_BHS
200411. BR_BLO
200412. BR_BLT
200413. BR_BMI
200414. BR_BNE
200415. BR_BOOLOPT_MAX
200416. BR_BOOLOPT_NO_LL_LEARN
200417. BR_BPDU_GUARD
200418. BR_CLEAR_DEATH_NOTIFICATION_DONE
200419. BR_CODE_COMPONENT_ID
200420. BR_CODE_COMPONENT_VERSION
200421. BR_CODE_DEPENDENT_IF
200422. BR_CODE_DESCR
200423. BR_CODE_END_OF_BRA
200424. BR_CODE_EXPOSED_IF
200425. BR_CODE_MAX
200426. BR_CODE_MIN
200427. BR_CSS_NONE
200428. BR_DEAD_BINDER
200429. BR_DEAD_REPLY
200430. BR_DECC
200431. BR_DECC_CHK
200432. BR_DECC_CHK_GEN
200433. BR_DECC_OFF
200434. BR_DECC_SHIFT
200435. BR_DECREFS
200436. BR_DEFAULT_AGEING_TIME
200437. BR_DESC_PRIV_CAP_AESCCMP
200438. BR_DESC_PRIV_CAP_CCX_CP
200439. BR_DESC_PRIV_CAP_CCX_MIC
200440. BR_DESC_PRIV_CAP_MICHAEL
200441. BR_DESC_PRIV_CAP_TKIP
200442. BR_DESC_PRIV_CAP_WEP
200443. BR_ERROR
200444. BR_EV_PIP_COND
200445. BR_EV_PIP_UNCOND
200446. BR_EX_DMA_r14
200447. BR_FAILED_REPLY
200448. BR_FINISHED
200449. BR_FLOOD
200450. BR_GROUPFWD_8021AD
200451. BR_GROUPFWD_DEFAULT
200452. BR_GROUPFWD_LACP
200453. BR_GROUPFWD_MACPAUSE
200454. BR_GROUPFWD_RESTRICTED
200455. BR_GROUPFWD_STP
200456. BR_HAIRPIN_MODE
200457. BR_HASH_BITS
200458. BR_HASH_SIZE
200459. BR_HOLD_TIME
200460. BR_HRZ
200461. BR_IFCLR
200462. BR_IFSET
200463. BR_INCREFS
200464. BR_INPUT_SKB_CB
200465. BR_INPUT_SKB_CB_MROUTERS_ONLY
200466. BR_INSTR
200467. BR_INTERFACE_ROLE_CLIENT
200468. BR_INTERFACE_ROLE_SERVER
200469. BR_ISOLATED
200470. BR_KERNEL_STP
200471. BR_LEARNING
200472. BR_LEARNING_SYNC
200473. BR_MAX_FORWARD_DELAY
200474. BR_MAX_HELLO_TIME
200475. BR_MAX_MAX_AGE
200476. BR_MAX_PATH_COST
200477. BR_MAX_PORTS
200478. BR_MAX_PORT_PRIORITY
200479. BR_MAX_TX_POWER
200480. BR_MCAST_DIR_RX
200481. BR_MCAST_DIR_SIZE
200482. BR_MCAST_DIR_TX
200483. BR_MCAST_FLOOD
200484. BR_MIN_FORWARD_DELAY
200485. BR_MIN_HELLO_TIME
200486. BR_MIN_MAX_AGE
200487. BR_MIN_PATH_COST
200488. BR_MSEL
200489. BR_MSEL_SHIFT
200490. BR_MS_FCM
200491. BR_MS_GPCM
200492. BR_MS_MSK
200493. BR_MS_SDRAM
200494. BR_MS_UPMA
200495. BR_MS_UPMB
200496. BR_MS_UPMC
200497. BR_MULTICAST_DEFAULT_HASH_MAX
200498. BR_MULTICAST_FAST_LEAVE
200499. BR_MULTICAST_TO_UNICAST
200500. BR_NEIGH_SUPPRESS
200501. BR_NEVER
200502. BR_NOOP
200503. BR_NO_STP
200504. BR_OFF_RELO
200505. BR_OK
200506. BR_OP
200507. BR_PARE
200508. BR_PKT_BROADCAST
200509. BR_PKT_MULTICAST
200510. BR_PKT_UNICAST
200511. BR_PORT_BITS
200512. BR_PORT_FLAGS_HW_OFFLOAD
200513. BR_PROMISC
200514. BR_PROXYARP
200515. BR_PROXYARP_WIFI
200516. BR_PS
200517. BR_PS_16
200518. BR_PS_32
200519. BR_PS_8
200520. BR_PS_MSK
200521. BR_PS_SHIFT
200522. BR_RELEASE
200523. BR_REPLY
200524. BR_RES
200525. BR_ROOT_BLOCK
200526. BR_SPAWN_LOOPER
200527. BR_STACK_ADDR
200528. BR_STATE_BLOCKING
200529. BR_STATE_DISABLED
200530. BR_STATE_FORWARDING
200531. BR_STATE_LEARNING
200532. BR_STATE_LISTENING
200533. BR_STP_PROG
200534. BR_TRANSACTION
200535. BR_TRANSACTION_COMPLETE
200536. BR_TRANSACTION_SEC_CTX
200537. BR_UKN
200538. BR_ULT
200539. BR_UNC
200540. BR_USER_STP
200541. BR_V
200542. BR_VECTOR
200543. BR_VERSION
200544. BR_VLAN_TUNNEL
200545. BR_VLFLAG_ADDED_BY_SWITCHDEV
200546. BR_VLFLAG_PER_PORT_STATS
200547. BR_V_SHIFT
200548. BR_WP
200549. BR_WP_SHIFT
200550. BS
200551. BS0
200552. BS0_ACK
200553. BS0_ATN
200554. BS0_CD
200555. BS0_IO
200556. BS0_MSG
200557. BS0_PHASE
200558. BS0_REQ
200559. BS1
200560. BS1_BSY
200561. BS1_RST
200562. BS1_SEL
200563. BSARCH_GI2_LATE
200564. BSARCH_SHORT_EARLY
200565. BSARCH_SHORT_LATE
200566. BSAT_REG
200567. BSA_USB_CMD
200568. BSBD_OPTION
200569. BSBD_START_OFFSET
200570. BSBE1_D01A_H
200571. BSBE1_H
200572. BSC
200573. BSC_CNT_REG1_MASK
200574. BSC_CNT_REG1_SHIFT
200575. BSC_CS0BCR
200576. BSC_CS0WCR
200577. BSC_CS4BCR
200578. BSC_CS4WCR
200579. BSC_CS6ABCR
200580. BSC_CTLHI_REG_DATAREG_SIZE_MASK
200581. BSC_CTLHI_REG_IGNORE_ACK_MASK
200582. BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK
200583. BSC_CTLHI_REG_WAIT_DIS_MASK
200584. BSC_CTL_REG_DIV_CLK_MASK
200585. BSC_CTL_REG_DTF_MASK
200586. BSC_CTL_REG_INT_EN_MASK
200587. BSC_CTL_REG_INT_EN_SHIFT
200588. BSC_CTL_REG_SCL_SEL_MASK
200589. BSC_CTL_REG_SCL_SEL_SHIFT
200590. BSC_IIC_EN_ENABLE_MASK
200591. BSC_IIC_EN_INTRP_MASK
200592. BSC_IIC_EN_NOACK_MASK
200593. BSC_IIC_EN_NOSTART_MASK
200594. BSC_IIC_EN_NOSTOP_MASK
200595. BSC_IIC_EN_RESTART_MASK
200596. BSC_SRC
200597. BSC_START
200598. BSC_STOP
200599. BSC_T_OFF
200600. BSC_T_ON
200601. BSC_T_STEP
200602. BSDI_PARTITION
200603. BSDLY
200604. BSD_CURRENT_VERSION
200605. BSD_DISKMAGIC
200606. BSD_FS_UNUSED
200607. BSD_HASH
200608. BSD_HWS_PGA_GEN7
200609. BSD_INIT_BITS
200610. BSD_KEY
200611. BSD_LIST_HEAD
200612. BSD_MAKE_OPT
200613. BSD_MAXPARTITIONS
200614. BSD_MAX_BITS
200615. BSD_MIN_BITS
200616. BSD_NBITS
200617. BSD_OVHD
200618. BSD_RING_BASE
200619. BSD_VERSION
200620. BSEARCH
200621. BSEC
200622. BSEL
200623. BSEL_SOC_FUSE_001
200624. BSEL_SOC_FUSE_101
200625. BSEL_SOC_FUSE_111
200626. BSEL_SOC_FUSE_MASK
200627. BSET_CACHELINE
200628. BSET_MAGIC
200629. BSE_CONFIG
200630. BSE_DMA_BUSY
200631. BSE_ICMDQUE_EMPTY
200632. BSE_INT_ENB
200633. BSF
200634. BSFACTOR_QMA1
200635. BSFACTOR_QMA2
200636. BSFACTOR_QMA3
200637. BSFACTOR_QMA4
200638. BSFACTOR_QMA5
200639. BSFACTOR_QMA6
200640. BSFACTOR_QMA7
200641. BSFACTOR_QMA8
200642. BSFACTOR_QMA9
200643. BSGIEN
200644. BSG_DEFAULT_CMDS
200645. BSG_DESCRIPTION
200646. BSG_FLAG_Q_AT_HEAD
200647. BSG_FLAG_Q_AT_TAIL
200648. BSG_LIST_ARRAY_SIZE
200649. BSG_MAX_DEVS
200650. BSG_MBOX_SIZE
200651. BSG_PROTOCOL_SCSI
200652. BSG_SUB_PROTOCOL_SCSI_CMD
200653. BSG_SUB_PROTOCOL_SCSI_TMF
200654. BSG_SUB_PROTOCOL_SCSI_TRANSPORT
200655. BSG_VERSION
200656. BSH5
200657. BSH6
200658. BSHIFT_L
200659. BSHORTCFO
200660. BSHORTCFOF_LENGTH
200661. BSHORTCFOT_LENGTH
200662. BSHUFFLE_OPF
200663. BSIGEVM
200664. BSIGTONE_IM
200665. BSIGTONE_RE
200666. BSLIP_EN
200667. BSM_BASE
200668. BSM_CFG_VAL1
200669. BSM_CFG_VAL2
200670. BSM_CTRL_BSM_EN
200671. BSM_DRAM_DATA_BYTECOUNT_REG
200672. BSM_DRAM_DATA_PTR_REG
200673. BSM_DRAM_INST_BYTECOUNT_REG
200674. BSM_DRAM_INST_LOAD
200675. BSM_DRAM_INST_PTR_REG
200676. BSM_END
200677. BSM_SRAM_LOWER_BOUND
200678. BSM_SRAM_SIZE
200679. BSM_WR_CTRL_REG
200680. BSM_WR_CTRL_REG_BIT_START
200681. BSM_WR_CTRL_REG_BIT_START_EN
200682. BSM_WR_DWCOUNT_REG
200683. BSM_WR_MEM_DST_REG
200684. BSM_WR_MEM_SRC_REG
200685. BSM_WR_STATUS_REG
200686. BSNR_EVMF_LENGTH
200687. BSNR_EVMT_LENGTH
200688. BSO_BAD
200689. BSO_MASK
200690. BSO_NOERROR
200691. BSO_OVERSIZED
200692. BSO_SHORT
200693. BSP
200694. BSPI
200695. BSPI_ADDRLEN_3BYTES
200696. BSPI_ADDRLEN_4BYTES
200697. BSPI_B0_CTRL
200698. BSPI_B0_STATUS
200699. BSPI_B1_CTRL
200700. BSPI_B1_STATUS
200701. BSPI_BITS_PER_CYCLE
200702. BSPI_BITS_PER_PHASE
200703. BSPI_BPP_ADDR_SELECT_MASK
200704. BSPI_BPP_MODE_SELECT_MASK
200705. BSPI_BSPI_FLASH_UPPER_ADDR_BYTE
200706. BSPI_BSPI_PIO_DATA
200707. BSPI_BSPI_PIO_IODIR
200708. BSPI_BSPI_PIO_MODE_ENABLE
200709. BSPI_BSPI_XOR_ENABLE
200710. BSPI_BSPI_XOR_VALUE
200711. BSPI_BUSY_STATUS
200712. BSPI_CMD_AND_MODE_BYTE
200713. BSPI_DONE
200714. BSPI_ERR
200715. BSPI_FLEX_MODE_ENABLE
200716. BSPI_INTR_STATUS
200717. BSPI_LR_INTERRUPTS_ALL
200718. BSPI_LR_INTERRUPTS_DATA
200719. BSPI_LR_INTERRUPTS_ERROR
200720. BSPI_MAST_N_BOOT_CTRL
200721. BSPI_RAF_CTRL
200722. BSPI_RAF_CTRL_CLEAR_MASK
200723. BSPI_RAF_CTRL_START_MASK
200724. BSPI_RAF_CURR_ADDR
200725. BSPI_RAF_FULLNESS
200726. BSPI_RAF_NUM_WORDS
200727. BSPI_RAF_READ_DATA
200728. BSPI_RAF_START_ADDR
200729. BSPI_RAF_STATUS
200730. BSPI_RAF_STATUS_FIFO_EMPTY_MASK
200731. BSPI_RAF_WATERMARK
200732. BSPI_RAF_WORD_CNT
200733. BSPI_READ_LENGTH
200734. BSPI_REVISION_ID
200735. BSPI_SCRATCH
200736. BSPI_STRAP_OVERRIDE_CTRL
200737. BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE
200738. BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL
200739. BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD
200740. BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE
200741. BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE
200742. BSP_CLOCK_STOP
200743. BSP_GEN_FIXED_KEY
200744. BSP_GEN_RANDOM_KEY
200745. BSP_MASK
200746. BSP_OFF
200747. BSP_RESTORE_RANDOM_KEY
200748. BSP_SHIFT
200749. BSR
200750. BSRLI10
200751. BSRLI2
200752. BSRLI20
200753. BSRLI4
200754. BSRU6_H
200755. BSR_128
200756. BSR_16
200757. BSR_4096
200758. BSR_64
200759. BSR_8
200760. BSR_BULK_IN_FULL
200761. BSR_BULK_OUT_FULL
200762. BSR_LINK
200763. BSR_LOCATION
200764. BSR_MAX
200765. BSR_MAX_DEVS
200766. BSR_REG
200767. BSR_UNKNOWN
200768. BSS
200769. BSSIDInfo
200770. BSSIDR
200771. BSSID_OFT
200772. BSSID_SZ
200773. BSSListElement
200774. BSSListRid
200775. BSSListRidExtra
200776. BSS_CHANGED_AP_PROBE_RESP
200777. BSS_CHANGED_ARP_FILTER
200778. BSS_CHANGED_ASSOC
200779. BSS_CHANGED_BANDWIDTH
200780. BSS_CHANGED_BASIC_RATES
200781. BSS_CHANGED_BEACON
200782. BSS_CHANGED_BEACON_ENABLED
200783. BSS_CHANGED_BEACON_INFO
200784. BSS_CHANGED_BEACON_INT
200785. BSS_CHANGED_BSSID
200786. BSS_CHANGED_CQM
200787. BSS_CHANGED_ERP_CTS_PROT
200788. BSS_CHANGED_ERP_PREAMBLE
200789. BSS_CHANGED_ERP_SLOT
200790. BSS_CHANGED_FTM_RESPONDER
200791. BSS_CHANGED_HE_OBSS_PD
200792. BSS_CHANGED_HT
200793. BSS_CHANGED_IBSS
200794. BSS_CHANGED_IDLE
200795. BSS_CHANGED_KEEP_ALIVE
200796. BSS_CHANGED_MCAST_RATE
200797. BSS_CHANGED_MU_GROUPS
200798. BSS_CHANGED_OCB
200799. BSS_CHANGED_P2P_PS
200800. BSS_CHANGED_PS
200801. BSS_CHANGED_QOS
200802. BSS_CHANGED_SSID
200803. BSS_CHANGED_TWT
200804. BSS_CHANGED_TXPOWER
200805. BSS_CMP_HIDE_NUL
200806. BSS_CMP_HIDE_ZLEN
200807. BSS_CMP_REGULAR
200808. BSS_DECRYPTED
200809. BSS_DISCONNECTED
200810. BSS_FIRST_SECTIONS
200811. BSS_HT
200812. BSS_ID_LENGTH
200813. BSS_INFO_BASIC
200814. BSS_INFO_BMC_INFO
200815. BSS_INFO_EXT_BSS
200816. BSS_INFO_LQ_RM
200817. BSS_INFO_MAX_NUM
200818. BSS_INFO_OMAC
200819. BSS_INFO_PM
200820. BSS_INFO_RA
200821. BSS_INFO_RF_CH
200822. BSS_INFO_ROAM_DETECTION
200823. BSS_INFO_SYNC_MODE
200824. BSS_INFO_UAPSD
200825. BSS_IRAM
200826. BSS_LOSE_EVENT_ID
200827. BSS_LOSS_EVENT_ID
200828. BSS_MAIN
200829. BSS_MEMBERSHIP_SELECTOR_HT_PHY
200830. BSS_MEMBERSHIP_SELECTOR_VHT_PHY
200831. BSS_NUM_MASK
200832. BSS_PARAM_FLAGS_CTS_PROT
200833. BSS_PARAM_FLAGS_SHORT_PREAMBLE
200834. BSS_PARAM_FLAGS_SHORT_SLOT_TIME
200835. BSS_ROLE_BIT_MASK
200836. BSS_SECTION
200837. BSS_SRAM
200838. BSS_STACK
200839. BSS_TYPE_AD_HOC
200840. BSS_TYPE_AP_BSS
200841. BSS_TYPE_IBSS
200842. BSS_TYPE_INFRASTRUCTURE
200843. BSS_TYPE_STA_BSS
200844. BST1
200845. BST5
200846. BST6
200847. BSTAS
200848. BSTAS_S
200849. BSTATUS1
200850. BSTAT_ACK
200851. BSTAT_ATN
200852. BSTAT_BSY
200853. BSTAT_CMD
200854. BSTAT_COLD_START
200855. BSTAT_CP_RUNNING
200856. BSTAT_IO
200857. BSTAT_MON_TOO_BIG
200858. BSTAT_MSG
200859. BSTAT_RDM0
200860. BSTAT_RDM1
200861. BSTAT_RDM2
200862. BSTAT_RDM3
200863. BSTAT_REQ
200864. BSTAT_SEL
200865. BSTAT_SELFTEST_FAIL
200866. BSTAT_SELFTEST_OK
200867. BSTBC_EN
200868. BSTEN
200869. BSTEV_RBO
200870. BSTEV_TBO
200871. BSTS
200872. BSTUCK_THRESH
200873. BSTUCK_THRESHOLD
200874. BST_SW_CR
200875. BSU
200876. BSUB_TUNE
200877. BSU_MASK
200878. BSU_SHIFT
200879. BSWAP
200880. BSWAP_MASK
200881. BSWP
200882. BSW_0
200883. BSW_1
200884. BS_ACTIVESIZE
200885. BS_ATOPEN
200886. BS_ATRDPEND
200887. BS_ATREADY
200888. BS_ATTIMER
200889. BS_ATWRPEND
200890. BS_B1OPEN
200891. BS_B2OPEN
200892. BS_BG_COLOR
200893. BS_CMD_INIT_DSPE_CFG
200894. BS_CMD_INIT_DSPE_TMG
200895. BS_CMD_INIT_ROTMODE
200896. BS_CMD_INIT_SYS_RUN
200897. BS_CMD_LD_IMG
200898. BS_CMD_LD_IMG_AREA
200899. BS_CMD_LD_IMG_END
200900. BS_CMD_RD_REG
200901. BS_CMD_RD_WFM_INFO
200902. BS_CMD_UPD_FULL
200903. BS_CMD_UPD_GDRV_CLR
200904. BS_CMD_UPD_INIT
200905. BS_CMD_WAIT_DSPE_FREND
200906. BS_CMD_WAIT_DSPE_TRG
200907. BS_CMD_WR_REG
200908. BS_COLOR_REG
200909. BS_CORRECTABLE_ERR_MSK
200910. BS_CRC0_HIGH
200911. BS_CRC0_LOW
200912. BS_CRC1_HIGH
200913. BS_CRC1_LOW
200914. BS_CS
200915. BS_CTRL_BM
200916. BS_CTRL_CRC
200917. BS_CTRL_DL
200918. BS_CTRL_EN
200919. BS_CTRL_HMASK
200920. BS_CTRL_PM
200921. BS_CTRL_SBS
200922. BS_CTRL_TE
200923. BS_CTRL_TM
200924. BS_CTRL_TS
200925. BS_CTRL_VD
200926. BS_CTRL_VM
200927. BS_DC
200928. BS_DRIFT_TO
200929. BS_EXT_ROM
200930. BS_FLASH
200931. BS_FRAME_TO
200932. BS_HINTERVALS
200933. BS_H_INTVALS
200934. BS_INFO
200935. BS_INIT
200936. BS_MARK
200937. BS_MII0
200938. BS_MMIO_CMD
200939. BS_MMIO_DATA
200940. BS_NAND
200941. BS_NUM_INPUT_IDS
200942. BS_NUM_OUTPUT_IDS
200943. BS_N_MARK
200944. BS_PCI
200945. BS_PREFETCH_LINE
200946. BS_PROG_LINE
200947. BS_READABLE
200948. BS_REG_PRC
200949. BS_REG_REV
200950. BS_RESETTING
200951. BS_RMII0
200952. BS_SPI
200953. BS_SPIFLASH_PAGE_SIZE
200954. BS_SUSPEND
200955. BS_SYNC
200956. BS_SYNC_HSP
200957. BS_SYNC_HSW
200958. BS_SYNC_VSP
200959. BS_SYNC_VSW
200960. BS_T0_INTERVAL
200961. BS_T1_INTERVAL
200962. BS_T2_INTERVAL
200963. BS_TE_TO
200964. BS_UART1
200965. BS_UNCORRECTABLE_BIT
200966. BS_USER
200967. BS_VAL
200968. BS_VINTERVALS
200969. BS_V_INTVALS
200970. BS_WR
200971. BS_WRITABLE
200972. BS__MARK
200973. BT
200974. BT431_CMD_1_1_MUX
200975. BT431_CMD_4_1_MUX
200976. BT431_CMD_5_1_MUX
200977. BT431_CMD_CURS_ENABLE
200978. BT431_CMD_OR_CURSORS
200979. BT431_CMD_THICK_1
200980. BT431_CMD_THICK_3
200981. BT431_CMD_THICK_5
200982. BT431_CMD_THICK_7
200983. BT431_CMD_XHAIR_ENABLE
200984. BT431_CMD_XOR_CURSORS
200985. BT431_CMD_xxx_MUX
200986. BT431_CURSOR_SIZE
200987. BT431_REG_CMD
200988. BT431_REG_CRAM_BASE
200989. BT431_REG_CRAM_END
200990. BT431_REG_CXHI
200991. BT431_REG_CXLO
200992. BT431_REG_CYHI
200993. BT431_REG_CYLO
200994. BT431_REG_WHHI
200995. BT431_REG_WHLO
200996. BT431_REG_WWHI
200997. BT431_REG_WWLO
200998. BT431_REG_WXHI
200999. BT431_REG_WXLO
201000. BT431_REG_WYHI
201001. BT431_REG_WYLO
201002. BT445_CSR_ADDR_REG
201003. BT445_CSR_REVISION
201004. BT445_PROTOCOL
201005. BT445_REVISION_REG
201006. BT459_ADDR_HI
201007. BT459_ADDR_LO
201008. BT459_BLINK_MASK
201009. BT459_CMAP
201010. BT459_CMD_REG_0
201011. BT459_CMD_REG_1
201012. BT459_CMD_REG_2
201013. BT459_CUR_CLR_1
201014. BT459_CUR_CLR_2
201015. BT459_CUR_CLR_3
201016. BT459_CUR_CMD_REG
201017. BT459_DATA
201018. BT459_LOAD_ADDR
201019. BT459_PALETTE
201020. BT459_READ_MASK
201021. BT459_REG_ACC
201022. BT459_WRITE
201023. BT463_ADDR_HI
201024. BT463_ADDR_LO
201025. BT463_BLINK_MASK_0
201026. BT463_BLINK_MASK_1
201027. BT463_BLINK_MASK_2
201028. BT463_BLINK_MASK_3
201029. BT463_CMD_REG_0
201030. BT463_CMD_REG_1
201031. BT463_CMD_REG_2
201032. BT463_CUR_CLR_0
201033. BT463_CUR_CLR_1
201034. BT463_LOAD_ADDR
201035. BT463_PALETTE
201036. BT463_READ_MASK_0
201037. BT463_READ_MASK_1
201038. BT463_READ_MASK_2
201039. BT463_READ_MASK_3
201040. BT463_REG_ACC
201041. BT463_WINDOW_TYPE_BASE
201042. BT463_WRITE
201043. BT485_ADDR_CUR_READ
201044. BT485_ADDR_CUR_WRITE
201045. BT485_ADDR_PAL_READ
201046. BT485_ADDR_PAL_WRITE
201047. BT485_CMD_0
201048. BT485_CMD_1
201049. BT485_CMD_2
201050. BT485_CMD_3
201051. BT485_CUR_HIGH_X
201052. BT485_CUR_HIGH_Y
201053. BT485_CUR_LOW_X
201054. BT485_CUR_LOW_Y
201055. BT485_CUR_RAM
201056. BT485_DATA_CUR
201057. BT485_DATA_PAL
201058. BT485_PIXEL_MASK
201059. BT485_READ_BIT
201060. BT485_STATUS
201061. BT485_WRITE
201062. BT485_WRITE_BIT
201063. BT819_FIFO_RESET_HIGH
201064. BT819_FIFO_RESET_LOW
201065. BT848_ADC
201066. BT848_ADC_AGC_EN
201067. BT848_ADC_CLK_SLEEP
201068. BT848_ADC_CRUSH
201069. BT848_ADC_C_SLEEP
201070. BT848_ADC_RESERVED
201071. BT848_ADC_SYNC_T
201072. BT848_ADC_Y_SLEEP
201073. BT848_ADELAY
201074. BT848_BDELAY
201075. BT848_BRIGHT
201076. BT848_CAP_CTL
201077. BT848_CAP_CTL_CAPTURE_EVEN
201078. BT848_CAP_CTL_CAPTURE_ODD
201079. BT848_CAP_CTL_CAPTURE_VBI_EVEN
201080. BT848_CAP_CTL_CAPTURE_VBI_ODD
201081. BT848_CAP_CTL_DITH_FRAME
201082. BT848_COLOR_CTL
201083. BT848_COLOR_CTL_BSWAP_EVEN
201084. BT848_COLOR_CTL_BSWAP_ODD
201085. BT848_COLOR_CTL_COLOR_BARS
201086. BT848_COLOR_CTL_EXT_FRMRATE
201087. BT848_COLOR_CTL_GAMMA
201088. BT848_COLOR_CTL_RGB_DED
201089. BT848_COLOR_CTL_WSWAP_EVEN
201090. BT848_COLOR_CTL_WSWAP_ODD
201091. BT848_COLOR_FMT
201092. BT848_COLOR_FMT_BtYUV
201093. BT848_COLOR_FMT_E_BtYUV
201094. BT848_COLOR_FMT_E_RAW
201095. BT848_COLOR_FMT_E_RGB15
201096. BT848_COLOR_FMT_E_RGB16
201097. BT848_COLOR_FMT_E_RGB24
201098. BT848_COLOR_FMT_E_RGB32
201099. BT848_COLOR_FMT_E_RGB8
201100. BT848_COLOR_FMT_E_Y8
201101. BT848_COLOR_FMT_E_YCrCb411
201102. BT848_COLOR_FMT_E_YCrCb422
201103. BT848_COLOR_FMT_E_YUY2
201104. BT848_COLOR_FMT_O_BtYUV
201105. BT848_COLOR_FMT_O_RAW
201106. BT848_COLOR_FMT_O_RGB15
201107. BT848_COLOR_FMT_O_RGB16
201108. BT848_COLOR_FMT_O_RGB24
201109. BT848_COLOR_FMT_O_RGB32
201110. BT848_COLOR_FMT_O_RGB8
201111. BT848_COLOR_FMT_O_Y8
201112. BT848_COLOR_FMT_O_YCrCb411
201113. BT848_COLOR_FMT_O_YCrCb422
201114. BT848_COLOR_FMT_O_YUY2
201115. BT848_COLOR_FMT_RAW
201116. BT848_COLOR_FMT_RGB15
201117. BT848_COLOR_FMT_RGB16
201118. BT848_COLOR_FMT_RGB24
201119. BT848_COLOR_FMT_RGB32
201120. BT848_COLOR_FMT_RGB8
201121. BT848_COLOR_FMT_Y8
201122. BT848_COLOR_FMT_YCrCb411
201123. BT848_COLOR_FMT_YCrCb422
201124. BT848_COLOR_FMT_YUY2
201125. BT848_CONTRAST_LO
201126. BT848_CONTROL_CBSENSE
201127. BT848_CONTROL_COMP
201128. BT848_CONTROL_CON_MSB
201129. BT848_CONTROL_LDEC
201130. BT848_CONTROL_LNOTCH
201131. BT848_CONTROL_SAT_U_MSB
201132. BT848_CONTROL_SAT_V_MSB
201133. BT848_DSTATUS
201134. BT848_DSTATUS_COF
201135. BT848_DSTATUS_CSEL
201136. BT848_DSTATUS_FIELD
201137. BT848_DSTATUS_HLOC
201138. BT848_DSTATUS_LOF
201139. BT848_DSTATUS_NUML
201140. BT848_DSTATUS_PLOCK
201141. BT848_DSTATUS_PRES
201142. BT848_DVSIF
201143. BT848_E_CONTROL
201144. BT848_E_CROP
201145. BT848_E_HACTIVE_LO
201146. BT848_E_HDELAY_LO
201147. BT848_E_HSCALE_HI
201148. BT848_E_HSCALE_LO
201149. BT848_E_SCLOOP
201150. BT848_E_VACTIVE_LO
201151. BT848_E_VDELAY_LO
201152. BT848_E_VSCALE_HI
201153. BT848_E_VSCALE_LO
201154. BT848_E_VTC
201155. BT848_FCAP
201156. BT848_FIFO_STATUS_EOL1
201157. BT848_FIFO_STATUS_EOL2
201158. BT848_FIFO_STATUS_EOL3
201159. BT848_FIFO_STATUS_EOL4
201160. BT848_FIFO_STATUS_FM1
201161. BT848_FIFO_STATUS_FM3
201162. BT848_FIFO_STATUS_PXV
201163. BT848_FIFO_STATUS_SOL
201164. BT848_FIFO_STATUS_VRE
201165. BT848_FIFO_STATUS_VRO
201166. BT848_GPIO_DATA
201167. BT848_GPIO_DMA_CTL
201168. BT848_GPIO_DMA_CTL_FIFO_ENABLE
201169. BT848_GPIO_DMA_CTL_GPCLKMODE
201170. BT848_GPIO_DMA_CTL_GPINTC
201171. BT848_GPIO_DMA_CTL_GPINTI
201172. BT848_GPIO_DMA_CTL_GPIOMODE
201173. BT848_GPIO_DMA_CTL_GPWEC
201174. BT848_GPIO_DMA_CTL_PKTP_16
201175. BT848_GPIO_DMA_CTL_PKTP_32
201176. BT848_GPIO_DMA_CTL_PKTP_4
201177. BT848_GPIO_DMA_CTL_PKTP_8
201178. BT848_GPIO_DMA_CTL_PLTP1_16
201179. BT848_GPIO_DMA_CTL_PLTP1_32
201180. BT848_GPIO_DMA_CTL_PLTP1_4
201181. BT848_GPIO_DMA_CTL_PLTP1_8
201182. BT848_GPIO_DMA_CTL_PLTP23_16
201183. BT848_GPIO_DMA_CTL_PLTP23_32
201184. BT848_GPIO_DMA_CTL_PLTP23_4
201185. BT848_GPIO_DMA_CTL_PLTP23_8
201186. BT848_GPIO_DMA_CTL_RISC_ENABLE
201187. BT848_GPIO_OUT_EN
201188. BT848_GPIO_REG_INP
201189. BT848_HUE
201190. BT848_I2C
201191. BT848_I2C_DIV
201192. BT848_I2C_SCL
201193. BT848_I2C_SDA
201194. BT848_I2C_SYNC
201195. BT848_I2C_W3B
201196. BT848_IFORM
201197. BT848_IFORM_AUTO
201198. BT848_IFORM_HACTIVE
201199. BT848_IFORM_MUX0
201200. BT848_IFORM_MUX1
201201. BT848_IFORM_MUX2
201202. BT848_IFORM_MUXSEL
201203. BT848_IFORM_NORM
201204. BT848_IFORM_NTSC
201205. BT848_IFORM_NTSC_J
201206. BT848_IFORM_PAL_BDGHI
201207. BT848_IFORM_PAL_M
201208. BT848_IFORM_PAL_N
201209. BT848_IFORM_PAL_NC
201210. BT848_IFORM_SECAM
201211. BT848_IFORM_XT0
201212. BT848_IFORM_XT1
201213. BT848_IFORM_XTAUTO
201214. BT848_IFORM_XTBOTH
201215. BT848_IFORM_XTSEL
201216. BT848_INT_ETBF
201217. BT848_INT_FBUS
201218. BT848_INT_FDSR
201219. BT848_INT_FIELD
201220. BT848_INT_FMTCHG
201221. BT848_INT_FTRGT
201222. BT848_INT_GPINT
201223. BT848_INT_HLOCK
201224. BT848_INT_HSYNC
201225. BT848_INT_I2CDONE
201226. BT848_INT_MASK
201227. BT848_INT_OCERR
201228. BT848_INT_OFLOW
201229. BT848_INT_PABORT
201230. BT848_INT_PPERR
201231. BT848_INT_RACK
201232. BT848_INT_RIPERR
201233. BT848_INT_RISCI
201234. BT848_INT_RISCS
201235. BT848_INT_RISC_EN
201236. BT848_INT_SCERR
201237. BT848_INT_STAT
201238. BT848_INT_VPRES
201239. BT848_INT_VSYNC
201240. BT848_OFORM
201241. BT848_OFORM_CORE0
201242. BT848_OFORM_CORE16
201243. BT848_OFORM_CORE32
201244. BT848_OFORM_CORE8
201245. BT848_OFORM_RANGE
201246. BT848_O_CONTROL
201247. BT848_O_CROP
201248. BT848_O_HACTIVE_LO
201249. BT848_O_HDELAY_LO
201250. BT848_O_HSCALE_HI
201251. BT848_O_HSCALE_LO
201252. BT848_O_SCLOOP
201253. BT848_O_VACTIVE_LO
201254. BT848_O_VDELAY_LO
201255. BT848_O_VSCALE_HI
201256. BT848_O_VSCALE_LO
201257. BT848_O_VTC
201258. BT848_PLL_C
201259. BT848_PLL_F_HI
201260. BT848_PLL_F_LO
201261. BT848_PLL_X
201262. BT848_PLL_XCI
201263. BT848_RISC_BYTE0
201264. BT848_RISC_BYTE1
201265. BT848_RISC_BYTE2
201266. BT848_RISC_BYTE3
201267. BT848_RISC_BYTE_ALL
201268. BT848_RISC_BYTE_NONE
201269. BT848_RISC_COUNT
201270. BT848_RISC_EOL
201271. BT848_RISC_IRQ
201272. BT848_RISC_JUMP
201273. BT848_RISC_RESYNC
201274. BT848_RISC_SKIP
201275. BT848_RISC_SKIP123
201276. BT848_RISC_SOL
201277. BT848_RISC_STRT_ADD
201278. BT848_RISC_SYNC
201279. BT848_RISC_WRITE
201280. BT848_RISC_WRITE123
201281. BT848_RISC_WRITE1S23
201282. BT848_RISC_WRITEC
201283. BT848_SAT_U_LO
201284. BT848_SAT_V_LO
201285. BT848_SCLOOP_CAGC
201286. BT848_SCLOOP_CKILL
201287. BT848_SCLOOP_HFILT_AUTO
201288. BT848_SCLOOP_HFILT_CIF
201289. BT848_SCLOOP_HFILT_ICON
201290. BT848_SCLOOP_HFILT_MAXP
201291. BT848_SCLOOP_HFILT_MEDP
201292. BT848_SCLOOP_HFILT_MINP
201293. BT848_SCLOOP_HFILT_QCIF
201294. BT848_SCLOOP_PEAK
201295. BT848_SRESET
201296. BT848_TDEC
201297. BT848_TDEC_DEC_FIELD
201298. BT848_TDEC_DEC_RAT
201299. BT848_TDEC_FLDALIGN
201300. BT848_TEST
201301. BT848_TGCTRL
201302. BT848_TGLB
201303. BT848_VBI_PACK_DEL
201304. BT848_VBI_PACK_DEL_EXT_FRAME
201305. BT848_VBI_PACK_DEL_VBI_HDELAY
201306. BT848_VBI_PACK_DEL_VBI_PKT_HI
201307. BT848_VBI_PACK_SIZE
201308. BT848_VSCALE_COMB
201309. BT848_VSCALE_HI
201310. BT848_VSCALE_INT
201311. BT848_VSCALE_YCOMB
201312. BT848_VTC_HSFMT
201313. BT848_VTC_VFILT_2TAP
201314. BT848_VTC_VFILT_3TAP
201315. BT848_VTC_VFILT_4TAP
201316. BT848_VTC_VFILT_5TAP
201317. BT848_VTOTAL_HI
201318. BT848_VTOTAL_LO
201319. BT848_WC_DOWN
201320. BT848_WC_UP
201321. BT856_NR_REG
201322. BT856_REG_OFFSET
201323. BT878_ACAP_EN
201324. BT878_AFBUS
201325. BT878_AFDSR
201326. BT878_AFP_LEN
201327. BT878_AFTRGT
201328. BT878_AGPIO_DMA_CTL
201329. BT878_AINT_MASK
201330. BT878_AINT_STAT
201331. BT878_ALP_LEN
201332. BT878_AOCERR
201333. BT878_AOFLOW
201334. BT878_APABORT
201335. BT878_APACK_LEN
201336. BT878_APPERR
201337. BT878_ARIPERR
201338. BT878_ARISCI
201339. BT878_ARISCS
201340. BT878_ARISC_EN
201341. BT878_ARISC_PC
201342. BT878_ARISC_START
201343. BT878_ASCERR
201344. BT878_A_G2X
201345. BT878_A_GAIN
201346. BT878_A_PWRDN
201347. BT878_A_SEL
201348. BT878_DA_APP
201349. BT878_DA_DPM
201350. BT878_DA_ES2
201351. BT878_DA_IOM
201352. BT878_DA_LMT
201353. BT878_DA_LRD
201354. BT878_DA_LRI
201355. BT878_DA_MLB
201356. BT878_DA_SBR
201357. BT878_DA_SCE
201358. BT878_DA_SDR
201359. BT878_DEVCTRL
201360. BT878_EN_TBFX
201361. BT878_EN_VSFX
201362. BT878_FIFO_EN
201363. BT878_GPIO_DMA_CTL
201364. BT878_I2CDONE
201365. BT878_I2CRACK
201366. BT878_I2C_MODE
201367. BT878_I2C_NOSTART
201368. BT878_I2C_NOSTOP
201369. BT878_I2C_RATE
201370. BT878_INT_MASK
201371. BT878_INT_STAT
201372. BT878_MAX
201373. BT878_PKTP
201374. BT878_RISC_EN
201375. BT878_RISC_SYNC_MASK
201376. BT878_VERSION_CODE
201377. BT8XXGPIO_NR_GPIOS
201378. BTA
201379. BTABLESEL
201380. BTAILCFO
201381. BTAILCFOF_LENGTH
201382. BTAILCFOT_LENGTH
201383. BTAMP_EVENT_CONNECTION_START
201384. BTAMP_EVENT_CONNECTION_STOP
201385. BTAMP_EVENT_CONNECTION_TERMINATED
201386. BTAMP_EVENT_TYPE_MAX
201387. BTA_COMPLETED
201388. BTA_EN
201389. BTA_FINISHED
201390. BTA_REQ
201391. BTA_TO_CNT
201392. BTB_FLUSH
201393. BTB_FLUSH_SIZE
201394. BTB_HEADROOM_BLOCKS
201395. BTB_JUMBO_PKT_BLOCKS
201396. BTB_MAX_BLOCKS
201397. BTB_PURE_LB_FACTOR
201398. BTB_PURE_LB_RATIO
201399. BTB_REG_BIG_RAM_ADDRESS
201400. BTB_REG_BIG_RAM_DATA
201401. BTB_REG_DBG_DWORD_ENABLE
201402. BTB_REG_DBG_FORCE_FRAME
201403. BTB_REG_DBG_FORCE_VALID
201404. BTB_REG_DBG_SELECT
201405. BTB_REG_DBG_SHIFT
201406. BTB_REG_HEADER_SIZE
201407. BTB_TIMER_DISABLE
201408. BTCDBGINFO
201409. BTCGB0_Vdroop_Enable_MASK
201410. BTCGB0_Vdroop_Enable_SHIFT
201411. BTCGB1_Vdroop_Enable_MASK
201412. BTCGB1_Vdroop_Enable_SHIFT
201413. BTCGB_VDROOP_TABLE_MAX_ENTRIES
201414. BTCOEXVERSION
201415. BTCOEX_ALIVE
201416. BTCOEX_H
201417. BTCOMPARE
201418. BTCR
201419. BTCS
201420. BTCVSD_RX_BUF_SIZE
201421. BTCVSD_RX_PACKET_SIZE
201422. BTCVSD_SND_NAME
201423. BTCVSD_TX_BUF_SIZE
201424. BTCVSD_TX_PACKET_SIZE
201425. BTC_ANTENNA_AT_AUX_PORT
201426. BTC_ANTENNA_AT_MAIN_PORT
201427. BTC_ANTENNA_POS
201428. BTC_ANT_PATH_AUTO
201429. BTC_ANT_PATH_BT
201430. BTC_ANT_PATH_PTA
201431. BTC_ANT_PATH_WIFI
201432. BTC_ANT_PATH_WIFI5G
201433. BTC_ANT_TYPE_0
201434. BTC_ANT_TYPE_1
201435. BTC_ANT_TYPE_2
201436. BTC_ANT_TYPE_3
201437. BTC_ANT_TYPE_4
201438. BTC_ANT_TYPE_MAX
201439. BTC_ANT_WIFI_AT_AUX
201440. BTC_ANT_WIFI_AT_CPL_AUX
201441. BTC_ANT_WIFI_AT_CPL_MAIN
201442. BTC_ANT_WIFI_AT_MAIN
201443. BTC_ASSOCIATE_5G_FINISH
201444. BTC_ASSOCIATE_5G_START
201445. BTC_ASSOCIATE_FINISH
201446. BTC_ASSOCIATE_MAX
201447. BTC_ASSOCIATE_START
201448. BTC_BOARD_INFO
201449. BTC_BT_INFO
201450. BTC_BT_LINK_INFO
201451. BTC_BT_REG_BLUEWIZE
201452. BTC_BT_REG_LE
201453. BTC_BT_REG_MAX
201454. BTC_BT_REG_MODEM
201455. BTC_BT_REG_RF
201456. BTC_BT_REG_TYPE
201457. BTC_BT_REG_VENDOR
201458. BTC_CCK_1
201459. BTC_CCK_11
201460. BTC_CCK_2
201461. BTC_CCK_5_5
201462. BTC_CGULVCONTROL_DFLT
201463. BTC_CGULVPARAMETER_DFLT
201464. BTC_CHIP_CSR_BC4
201465. BTC_CHIP_CSR_BC8
201466. BTC_CHIP_INTERFACE
201467. BTC_CHIP_MAX
201468. BTC_CHIP_RTL8723A
201469. BTC_CHIP_RTL8723B
201470. BTC_CHIP_RTL8821
201471. BTC_CHIP_TYPE
201472. BTC_CHIP_UNDEF
201473. BTC_COEXIST
201474. BTC_CTRL_COLD_EXT
201475. BTC_CTRL_COMP_EN
201476. BTC_CTRL_HOT_EXT_N
201477. BTC_DBG_DISP_BT_FW_VER
201478. BTC_DBG_DISP_BT_LINK_INFO
201479. BTC_DBG_DISP_COEX_STATISTICS
201480. BTC_DBG_DISP_FW_PWR_MODE_CMD
201481. BTC_DBG_DISP_MAX
201482. BTC_DBG_DISP_TYPE
201483. BTC_DBG_DISP_WIFI_STATUS
201484. BTC_DBG_MAX
201485. BTC_DBG_OPCODE
201486. BTC_DBG_SET_COEX_BT_AFH_MAP
201487. BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT
201488. BTC_DBG_SET_COEX_BT_ONLY
201489. BTC_DBG_SET_COEX_DEC_BT_PWR
201490. BTC_DBG_SET_COEX_NORMAL
201491. BTC_DBG_SET_COEX_WIFI_ONLY
201492. BTC_DMDP
201493. BTC_DMSP
201494. BTC_FREQ_2_4G
201495. BTC_FREQ_5G
201496. BTC_FREQ_MAX
201497. BTC_GET_BL_BT_SCO_BUSY
201498. BTC_GET_BL_EXT_SWITCH
201499. BTC_GET_BL_FW_READY
201500. BTC_GET_BL_HS_CONNECTING
201501. BTC_GET_BL_HS_OPERATION
201502. BTC_GET_BL_IS_ASUS_8723B
201503. BTC_GET_BL_RF4CE_CONNECTED
201504. BTC_GET_BL_WIFI_4_WAY_PROGRESS
201505. BTC_GET_BL_WIFI_AP_MODE_ENABLE
201506. BTC_GET_BL_WIFI_BUSY
201507. BTC_GET_BL_WIFI_CONNECTED
201508. BTC_GET_BL_WIFI_DHCP
201509. BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED
201510. BTC_GET_BL_WIFI_ENABLE_ENCRYPTION
201511. BTC_GET_BL_WIFI_IN_EARLY_SUSPEND
201512. BTC_GET_BL_WIFI_IS_IN_MP_MODE
201513. BTC_GET_BL_WIFI_LINK
201514. BTC_GET_BL_WIFI_ROAM
201515. BTC_GET_BL_WIFI_SCAN
201516. BTC_GET_BL_WIFI_SOFTAP_IDLE
201517. BTC_GET_BL_WIFI_SOFTAP_LINKING
201518. BTC_GET_BL_WIFI_UNDER_5G
201519. BTC_GET_BL_WIFI_UNDER_B_MODE
201520. BTC_GET_DRIVER_TEST_CFG
201521. BTC_GET_MAX
201522. BTC_GET_S4_HS_RSSI
201523. BTC_GET_S4_WIFI_RSSI
201524. BTC_GET_TYPE
201525. BTC_GET_U1_ANT_TYPE
201526. BTC_GET_U1_AP_NUM
201527. BTC_GET_U1_IOT_PEER
201528. BTC_GET_U1_LPS_MODE
201529. BTC_GET_U1_MAC_PHY_MODE
201530. BTC_GET_U1_WIFI_CENTRAL_CHNL
201531. BTC_GET_U1_WIFI_DOT11_CHNL
201532. BTC_GET_U1_WIFI_HS_CHNL
201533. BTC_GET_U4_BT_DEVICE_INFO
201534. BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL
201535. BTC_GET_U4_BT_PATCH_VER
201536. BTC_GET_U4_SUPPORTED_FEATURE
201537. BTC_GET_U4_SUPPORTED_VERSION
201538. BTC_GET_U4_VENDOR
201539. BTC_GET_U4_WIFI_BW
201540. BTC_GET_U4_WIFI_FW_VER
201541. BTC_GET_U4_WIFI_IQK_FAIL
201542. BTC_GET_U4_WIFI_IQK_OK
201543. BTC_GET_U4_WIFI_IQK_TOTAL
201544. BTC_GET_U4_WIFI_LINK_STATUS
201545. BTC_GET_U4_WIFI_TRAFFIC_DIRECTION
201546. BTC_INTF_GSPI
201547. BTC_INTF_MAX
201548. BTC_INTF_PCI
201549. BTC_INTF_SDIO
201550. BTC_INTF_UNKNOWN
201551. BTC_INTF_USB
201552. BTC_IOT_PEER_AIRGO
201553. BTC_IOT_PEER_ATHEROS
201554. BTC_IOT_PEER_BROADCOM
201555. BTC_IOT_PEER_CISCO
201556. BTC_IOT_PEER_MARVELL
201557. BTC_IOT_PEER_MAX
201558. BTC_IOT_PEER_MERU
201559. BTC_IOT_PEER_RALINK
201560. BTC_IOT_PEER_REALTEK
201561. BTC_IOT_PEER_REALTEK_92SE
201562. BTC_IOT_PEER_REALTEK_JAGUAR_BCUTAP
201563. BTC_IOT_PEER_REALTEK_JAGUAR_CCUTAP
201564. BTC_IOT_PEER_REALTEK_SOFTAP
201565. BTC_IOT_PEER_SELF_SOFTAP
201566. BTC_IOT_PEER_UNKNOWN
201567. BTC_IO_MC_REGS_SIZE
201568. BTC_IPS_ENTER
201569. BTC_IPS_LEAVE
201570. BTC_IPS_MAX
201571. BTC_LHP_UVD_DFLT
201572. BTC_LMP_UVD_DFLT
201573. BTC_LPS_DISABLE
201574. BTC_LPS_ENABLE
201575. BTC_LPS_MAX
201576. BTC_MCS_0
201577. BTC_MCS_1
201578. BTC_MCS_10
201579. BTC_MCS_11
201580. BTC_MCS_12
201581. BTC_MCS_13
201582. BTC_MCS_14
201583. BTC_MCS_15
201584. BTC_MCS_16
201585. BTC_MCS_17
201586. BTC_MCS_18
201587. BTC_MCS_19
201588. BTC_MCS_2
201589. BTC_MCS_20
201590. BTC_MCS_21
201591. BTC_MCS_22
201592. BTC_MCS_23
201593. BTC_MCS_24
201594. BTC_MCS_25
201595. BTC_MCS_26
201596. BTC_MCS_27
201597. BTC_MCS_28
201598. BTC_MCS_29
201599. BTC_MCS_3
201600. BTC_MCS_30
201601. BTC_MCS_31
201602. BTC_MCS_32
201603. BTC_MCS_4
201604. BTC_MCS_5
201605. BTC_MCS_6
201606. BTC_MCS_7
201607. BTC_MCS_8
201608. BTC_MCS_9
201609. BTC_MC_UCODE_SIZE
201610. BTC_MEDIA_CONNECT
201611. BTC_MEDIA_DISCONNECT
201612. BTC_MEDIA_MAX
201613. BTC_MGCG_SEQUENCE
201614. BTC_MIMO_PS_DYNAMIC
201615. BTC_MIMO_PS_STATIC
201616. BTC_MP_UNKNOWN
201617. BTC_MSG_ALGORITHM
201618. BTC_MSG_INTERFACE
201619. BTC_MSG_MAX
201620. BTC_MSG_TYPE
201621. BTC_MULTIPORT_MAX
201622. BTC_MULTIPORT_MCC_2BAND
201623. BTC_MULTIPORT_MCC_2CHANNEL
201624. BTC_MULTIPORT_SCC
201625. BTC_NOTIFY_TYPE_ASSOCIATE
201626. BTC_NOTIFY_TYPE_IPS
201627. BTC_NOTIFY_TYPE_LPS
201628. BTC_NOTIFY_TYPE_MEDIA_STATUS
201629. BTC_NOTIFY_TYPE_SCAN
201630. BTC_NOTIFY_TYPE_SPECIAL_PACKET
201631. BTC_NOTIFY_TYPE_STACK_OPERATION
201632. BTC_NOT_SWITCH
201633. BTC_OFDM_12
201634. BTC_OFDM_18
201635. BTC_OFDM_24
201636. BTC_OFDM_36
201637. BTC_OFDM_48
201638. BTC_OFDM_54
201639. BTC_OFDM_6
201640. BTC_OFDM_9
201641. BTC_PACKET_ARP
201642. BTC_PACKET_DHCP
201643. BTC_PACKET_EAPOL
201644. BTC_PACKET_MAX
201645. BTC_PACKET_UNKNOWN
201646. BTC_PKT_CTRL
201647. BTC_PKT_MGNT
201648. BTC_PKT_NOT_FOR_ME
201649. BTC_PKT_UNKNOWN
201650. BTC_POWERSAVE_TYPE
201651. BTC_PRINT
201652. BTC_PRINT_ADDR
201653. BTC_PRINT_DATA
201654. BTC_PRINT_F
201655. BTC_PS_LPS_MAX
201656. BTC_PS_LPS_OFF
201657. BTC_PS_LPS_ON
201658. BTC_PS_MAX
201659. BTC_PS_WIFI_NATIVE
201660. BTC_RATE_DISABLE
201661. BTC_RATE_ENABLE
201662. BTC_RATE_MAX
201663. BTC_RF_A
201664. BTC_RF_B
201665. BTC_RF_C
201666. BTC_RF_D
201667. BTC_RF_OFF
201668. BTC_RF_ON
201669. BTC_RLP_UVD_DFLT
201670. BTC_RMP_UVD_DFLT
201671. BTC_ROLE_AP
201672. BTC_ROLE_HS_MODE
201673. BTC_ROLE_IBSS
201674. BTC_ROLE_MAX
201675. BTC_ROLE_STATION
201676. BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT
201677. BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT
201678. BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT
201679. BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT
201680. BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT
201681. BTC_RSSI_HIGH
201682. BTC_RSSI_LOW
201683. BTC_RSSI_MAX
201684. BTC_RSSI_MEDIUM
201685. BTC_RSSI_STATE
201686. BTC_RSSI_STATE_HIGH
201687. BTC_RSSI_STATE_LOW
201688. BTC_RSSI_STATE_MEDIUM
201689. BTC_RSSI_STATE_STAY_HIGH
201690. BTC_RSSI_STATE_STAY_LOW
201691. BTC_RSSI_STATE_STAY_MEDIUM
201692. BTC_SCAN_FINISH
201693. BTC_SCAN_MAX
201694. BTC_SCAN_START
201695. BTC_SCAN_START_2G
201696. BTC_SET_ACT_AGGREGATE_CTRL
201697. BTC_SET_ACT_ANTPOSREGRISTRY_CTRL
201698. BTC_SET_ACT_CTRL_8723B_ANT
201699. BTC_SET_ACT_CTRL_BT_COEX
201700. BTC_SET_ACT_CTRL_BT_INFO
201701. BTC_SET_ACT_DISABLE_LOW_POWER
201702. BTC_SET_ACT_ENTER_LPS
201703. BTC_SET_ACT_GET_BT_RSSI
201704. BTC_SET_ACT_INC_FORCE_EXEC_PWR_CMD_CNT
201705. BTC_SET_ACT_LEAVE_LPS
201706. BTC_SET_ACT_NORMAL_LPS
201707. BTC_SET_ACT_POST_NORMAL_LPS
201708. BTC_SET_ACT_PRE_NORMAL_LPS
201709. BTC_SET_ACT_SEND_MIMO_PS
201710. BTC_SET_ACT_UPDATE_RAMASK
201711. BTC_SET_BL_BT_CTRL_AGG_SIZE
201712. BTC_SET_BL_BT_DISABLE
201713. BTC_SET_BL_BT_LIMITED_DIG
201714. BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL
201715. BTC_SET_BL_BT_SCO_BUSY
201716. BTC_SET_BL_BT_TRAFFIC_BUSY
201717. BTC_SET_BL_BT_TX_RX_MASK
201718. BTC_SET_BL_FORCE_TO_ROAM
201719. BTC_SET_BL_INC_SCAN_DEV_NUM
201720. BTC_SET_BL_MIRACAST_PLUS_BT
201721. BTC_SET_BL_TO_REJ_AP_AGG_PKT
201722. BTC_SET_MAX
201723. BTC_SET_MIMO_PS_MODE
201724. BTC_SET_TYPE
201725. BTC_SET_U1_1ANT_LPS
201726. BTC_SET_U1_1ANT_RPWM
201727. BTC_SET_U1_AGG_BUF_SIZE
201728. BTC_SET_U1_LPS_VAL
201729. BTC_SET_U1_RPWM_VAL
201730. BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE
201731. BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON
201732. BTC_SET_UI_SCAN_SIG_COMPENSATION
201733. BTC_SMSP
201734. BTC_STACK_INFO
201735. BTC_STACK_OP_INQ_PAGE_PAIR_FINISH
201736. BTC_STACK_OP_INQ_PAGE_PAIR_START
201737. BTC_STACK_OP_MAX
201738. BTC_STACK_OP_NONE
201739. BTC_STATISTICS
201740. BTC_SWITCH_MAX
201741. BTC_SWITCH_TO_24G
201742. BTC_SWITCH_TO_24G_NOFORSCAN
201743. BTC_SWITCH_TO_5G
201744. BTC_SYSLS_SEQUENCE
201745. BTC_UNKNOWN
201746. BTC_VENDOR_ASUS
201747. BTC_VENDOR_LENOVO
201748. BTC_VENDOR_OTHER
201749. BTC_VHT_1SS_MCS_0
201750. BTC_VHT_1SS_MCS_1
201751. BTC_VHT_1SS_MCS_2
201752. BTC_VHT_1SS_MCS_3
201753. BTC_VHT_1SS_MCS_4
201754. BTC_VHT_1SS_MCS_5
201755. BTC_VHT_1SS_MCS_6
201756. BTC_VHT_1SS_MCS_7
201757. BTC_VHT_1SS_MCS_8
201758. BTC_VHT_1SS_MCS_9
201759. BTC_VHT_2SS_MCS_0
201760. BTC_VHT_2SS_MCS_1
201761. BTC_VHT_2SS_MCS_2
201762. BTC_VHT_2SS_MCS_3
201763. BTC_VHT_2SS_MCS_4
201764. BTC_VHT_2SS_MCS_5
201765. BTC_VHT_2SS_MCS_6
201766. BTC_VHT_2SS_MCS_7
201767. BTC_VHT_2SS_MCS_8
201768. BTC_VHT_2SS_MCS_9
201769. BTC_VHT_3SS_MCS_0
201770. BTC_VHT_3SS_MCS_1
201771. BTC_VHT_3SS_MCS_2
201772. BTC_VHT_3SS_MCS_3
201773. BTC_VHT_3SS_MCS_4
201774. BTC_VHT_3SS_MCS_5
201775. BTC_VHT_3SS_MCS_6
201776. BTC_VHT_3SS_MCS_7
201777. BTC_VHT_3SS_MCS_8
201778. BTC_VHT_3SS_MCS_9
201779. BTC_VHT_4SS_MCS_0
201780. BTC_VHT_4SS_MCS_1
201781. BTC_VHT_4SS_MCS_2
201782. BTC_VHT_4SS_MCS_3
201783. BTC_VHT_4SS_MCS_4
201784. BTC_VHT_4SS_MCS_5
201785. BTC_VHT_4SS_MCS_6
201786. BTC_VHT_4SS_MCS_7
201787. BTC_VHT_4SS_MCS_8
201788. BTC_VHT_4SS_MCS_9
201789. BTC_WIFI_BW_HT20
201790. BTC_WIFI_BW_HT40
201791. BTC_WIFI_BW_HT80
201792. BTC_WIFI_BW_LEGACY
201793. BTC_WIFI_BW_MAX
201794. BTC_WIFI_BW_MODE
201795. BTC_WIFI_PNP
201796. BTC_WIFI_PNP_MAX
201797. BTC_WIFI_PNP_SLEEP
201798. BTC_WIFI_PNP_SLEEP_KEEP_ANT
201799. BTC_WIFI_PNP_WAKE_UP
201800. BTC_WIFI_ROLE
201801. BTC_WIFI_STAT_ANT_DIV
201802. BTC_WIFI_STAT_INIT
201803. BTC_WIFI_STAT_IQK
201804. BTC_WIFI_STAT_MAX
201805. BTC_WIFI_STAT_MP_OFF
201806. BTC_WIFI_STAT_NORMAL
201807. BTC_WIFI_STAT_NORMAL_OFF
201808. BTC_WIFI_TRAFFIC_DIR
201809. BTC_WIFI_TRAFFIC_MAX
201810. BTC_WIFI_TRAFFIC_RX
201811. BTC_WIFI_TRAFFIC_TX
201812. BTDLH
201813. BTDLL
201814. BTEMP_BALL
201815. BTEMP_BATCTRL_CURR_SRC_120UA
201816. BTEMP_BATCTRL_CURR_SRC_16UA
201817. BTEMP_BATCTRL_CURR_SRC_18UA
201818. BTEMP_BATCTRL_CURR_SRC_20UA
201819. BTEMP_BATCTRL_CURR_SRC_60UA
201820. BTEMP_BATCTRL_CURR_SRC_7UA
201821. BTEMP_HIGH_TH_52
201822. BTEMP_HIGH_TH_57_0
201823. BTEMP_HIGH_TH_57_1
201824. BTEMP_HIGH_TH_62
201825. BTEMP_PULL_UP
201826. BTEMP_THERMAL_HIGH_LIMIT_52
201827. BTEMP_THERMAL_HIGH_LIMIT_57
201828. BTEMP_THERMAL_HIGH_LIMIT_62
201829. BTEMP_THERMAL_LOW_LIMIT
201830. BTEMP_THERMAL_MED_LIMIT
201831. BTEOFF_CTRL
201832. BTEOFF_DEST
201833. BTEOFF_INT
201834. BTEOFF_NOTIFY
201835. BTEOFF_SRC
201836. BTEOFF_STAT
201837. BTE_CTRL
201838. BTE_CTRL_BW_LIMITER_MASK
201839. BTE_CTRL_BW_LIMITER_SHIFT
201840. BTF
201841. BTFCR
201842. BTF_ARRAY_ENC
201843. BTF_CONST_ENC
201844. BTF_ELF_SEC
201845. BTF_END_RAW
201846. BTF_ENUM_ENC
201847. BTF_EXT_ELF_SEC
201848. BTF_FUNC_ENC
201849. BTF_FUNC_PROTO_ARG_ENC
201850. BTF_FUNC_PROTO_ENC
201851. BTF_FWD_ENC
201852. BTF_INFO_ENC
201853. BTF_INFO_KFLAG
201854. BTF_INFO_KIND
201855. BTF_INFO_MASK
201856. BTF_INFO_VLEN
201857. BTF_INT_BITS
201858. BTF_INT_BOOL
201859. BTF_INT_CHAR
201860. BTF_INT_ENC
201861. BTF_INT_ENCODING
201862. BTF_INT_MASK
201863. BTF_INT_OFFSET
201864. BTF_INT_SIGNED
201865. BTF_IN_PROGRESS_ID
201866. BTF_KIND_ARRAY
201867. BTF_KIND_CONST
201868. BTF_KIND_DATASEC
201869. BTF_KIND_ENUM
201870. BTF_KIND_FUNC
201871. BTF_KIND_FUNC_PROTO
201872. BTF_KIND_FWD
201873. BTF_KIND_INT
201874. BTF_KIND_MAX
201875. BTF_KIND_PTR
201876. BTF_KIND_RESTRICT
201877. BTF_KIND_STRUCT
201878. BTF_KIND_TYPEDEF
201879. BTF_KIND_UNION
201880. BTF_KIND_UNKN
201881. BTF_KIND_VAR
201882. BTF_KIND_VOLATILE
201883. BTF_LOG_BUF_SIZE
201884. BTF_MAGIC
201885. BTF_MAX_NAME_OFFSET
201886. BTF_MAX_NR_TYPES
201887. BTF_MAX_SIZE
201888. BTF_MAX_STR_OFFSET
201889. BTF_MAX_TYPE
201890. BTF_MAX_VLEN
201891. BTF_MEMBER_BITFIELD_SIZE
201892. BTF_MEMBER_BIT_OFFSET
201893. BTF_MEMBER_ENC
201894. BTF_MEMBER_OFFSET
201895. BTF_PARAM_ENC
201896. BTF_PRINT_ARG
201897. BTF_PRINT_TYPE
201898. BTF_PTR_ENC
201899. BTF_RESTRICT_ENC
201900. BTF_STRUCT_ENC
201901. BTF_STR_OFFSET_VALID
201902. BTF_STR_SEC
201903. BTF_TYPEDEF_ENC
201904. BTF_TYPE_ARRAY_ENC
201905. BTF_TYPE_ENC
201906. BTF_TYPE_ID_VALID
201907. BTF_TYPE_INT_ENC
201908. BTF_UNION_ENC
201909. BTF_UNPROCESSED_ID
201910. BTF_VAR_ENC
201911. BTF_VAR_GLOBAL_ALLOCATED
201912. BTF_VAR_SECINFO_ENC
201913. BTF_VAR_STATIC
201914. BTF_VERSION
201915. BTF_VOLATILE_ENC
201916. BTH2_OFFSET
201917. BTHEVMCFG
201918. BTH_16B_PRN
201919. BTH_9B_PRN
201920. BTH_ACK_MASK
201921. BTH_BECN_MASK
201922. BTH_DEF_PKEY
201923. BTH_FECN_MASK
201924. BTH_MIG_MASK
201925. BTH_PAD_MASK
201926. BTH_PSN_MASK
201927. BTH_QPN_MASK
201928. BTH_RESV6A_MASK
201929. BTH_RESV7_MASK
201930. BTH_SEQ_MASK
201931. BTH_SE_MASK
201932. BTH_TVER
201933. BTH_TVER_MASK
201934. BTIER
201935. BTIIR
201936. BTINFO_BT_AUTO_RPT
201937. BTINFO_B_A2DP
201938. BTINFO_B_ACL_BUSY
201939. BTINFO_B_CONNECTION
201940. BTINFO_B_FTP
201941. BTINFO_B_HID
201942. BTINFO_B_INQ_PAGE
201943. BTINFO_B_SCO_BUSY
201944. BTINFO_B_SCO_ESCO
201945. BTINFO_WIFI_FETCH
201946. BTINFO_WK_CID
201947. BTISR
201948. BTI_PAGE_OVF
201949. BTLCR
201950. BTLSR
201951. BTL_S1TY_SUBBYTE
201952. BTL_S2TY_SUBBYTE
201953. BTMCR
201954. BTMODE
201955. BTMSR
201956. BTMTKSDIO_PM_OPS
201957. BTMTKSDIO_TX_WAIT_VND_EVT
201958. BTMTKUART_FLAG_STANDALONE_HW
201959. BTMTKUART_REQUIRED_WAKEUP
201960. BTMTKUART_TX_STATE_ACTIVE
201961. BTMTKUART_TX_STATE_WAKEUP
201962. BTMTKUART_TX_WAIT_VND_EVT
201963. BTMTK_WMT_FUNC_CTRL
201964. BTMTK_WMT_INVALID
201965. BTMTK_WMT_ON_DONE
201966. BTMTK_WMT_ON_PROGRESS
201967. BTMTK_WMT_ON_UNDONE
201968. BTMTK_WMT_PATCH_DONE
201969. BTMTK_WMT_PATCH_DWNLD
201970. BTMTK_WMT_PATCH_UNDONE
201971. BTMTK_WMT_RST
201972. BTMTK_WMT_SEMAPHORE
201973. BTM_HEADER_LEN
201974. BTM_UPLD_SIZE
201975. BTNAMSIZ
201976. BTN_0
201977. BTN_1
201978. BTN_2
201979. BTN_3
201980. BTN_4
201981. BTN_5
201982. BTN_6
201983. BTN_7
201984. BTN_8
201985. BTN_9
201986. BTN_A
201987. BTN_B
201988. BTN_BACK
201989. BTN_BASE
201990. BTN_BASE2
201991. BTN_BASE3
201992. BTN_BASE4
201993. BTN_BASE5
201994. BTN_BASE6
201995. BTN_C
201996. BTN_DEAD
201997. BTN_DIGI
201998. BTN_DPAD_DOWN
201999. BTN_DPAD_LEFT
202000. BTN_DPAD_RIGHT
202001. BTN_DPAD_UP
202002. BTN_EAST
202003. BTN_EXTRA
202004. BTN_FORWARD
202005. BTN_GAMEPAD
202006. BTN_GEAR_DOWN
202007. BTN_GEAR_UP
202008. BTN_JOYSTICK
202009. BTN_LEFT
202010. BTN_LEFT_BIT
202011. BTN_LEFT_MASK
202012. BTN_MIDDLE
202013. BTN_MIDDLE_BIT
202014. BTN_MISC
202015. BTN_MODE
202016. BTN_MOUSE
202017. BTN_NORTH
202018. BTN_ONLY_MODE_NAME
202019. BTN_PINKIE
202020. BTN_RIGHT
202021. BTN_RIGHT_BIT
202022. BTN_SELECT
202023. BTN_SIDE
202024. BTN_SOUTH
202025. BTN_START
202026. BTN_STYLUS
202027. BTN_STYLUS2
202028. BTN_STYLUS3
202029. BTN_TASK
202030. BTN_THUMB
202031. BTN_THUMB2
202032. BTN_THUMBL
202033. BTN_THUMBR
202034. BTN_TL
202035. BTN_TL2
202036. BTN_TOOL_AIRBRUSH
202037. BTN_TOOL_BRUSH
202038. BTN_TOOL_DOUBLETAP
202039. BTN_TOOL_FINGER
202040. BTN_TOOL_LENS
202041. BTN_TOOL_MOUSE
202042. BTN_TOOL_PEN
202043. BTN_TOOL_PENCIL
202044. BTN_TOOL_QUADTAP
202045. BTN_TOOL_QUINTTAP
202046. BTN_TOOL_RUBBER
202047. BTN_TOOL_TRIPLETAP
202048. BTN_TOP
202049. BTN_TOP2
202050. BTN_TOUCH
202051. BTN_TR
202052. BTN_TR2
202053. BTN_TRIGGER
202054. BTN_TRIGGER_HAPPY
202055. BTN_TRIGGER_HAPPY1
202056. BTN_TRIGGER_HAPPY10
202057. BTN_TRIGGER_HAPPY11
202058. BTN_TRIGGER_HAPPY12
202059. BTN_TRIGGER_HAPPY13
202060. BTN_TRIGGER_HAPPY14
202061. BTN_TRIGGER_HAPPY15
202062. BTN_TRIGGER_HAPPY16
202063. BTN_TRIGGER_HAPPY17
202064. BTN_TRIGGER_HAPPY18
202065. BTN_TRIGGER_HAPPY19
202066. BTN_TRIGGER_HAPPY2
202067. BTN_TRIGGER_HAPPY20
202068. BTN_TRIGGER_HAPPY21
202069. BTN_TRIGGER_HAPPY22
202070. BTN_TRIGGER_HAPPY23
202071. BTN_TRIGGER_HAPPY24
202072. BTN_TRIGGER_HAPPY25
202073. BTN_TRIGGER_HAPPY26
202074. BTN_TRIGGER_HAPPY27
202075. BTN_TRIGGER_HAPPY28
202076. BTN_TRIGGER_HAPPY29
202077. BTN_TRIGGER_HAPPY3
202078. BTN_TRIGGER_HAPPY30
202079. BTN_TRIGGER_HAPPY31
202080. BTN_TRIGGER_HAPPY32
202081. BTN_TRIGGER_HAPPY33
202082. BTN_TRIGGER_HAPPY34
202083. BTN_TRIGGER_HAPPY35
202084. BTN_TRIGGER_HAPPY36
202085. BTN_TRIGGER_HAPPY37
202086. BTN_TRIGGER_HAPPY38
202087. BTN_TRIGGER_HAPPY39
202088. BTN_TRIGGER_HAPPY4
202089. BTN_TRIGGER_HAPPY40
202090. BTN_TRIGGER_HAPPY5
202091. BTN_TRIGGER_HAPPY6
202092. BTN_TRIGGER_HAPPY7
202093. BTN_TRIGGER_HAPPY8
202094. BTN_TRIGGER_HAPPY9
202095. BTN_WEST
202096. BTN_WHEEL
202097. BTN_X
202098. BTN_Y
202099. BTN_Z
202100. BTOBB
202101. BTOBBT
202102. BTO_BCR
202103. BTPROTO_AVDTP
202104. BTPROTO_BNEP
202105. BTPROTO_CMTP
202106. BTPROTO_HCI
202107. BTPROTO_HIDP
202108. BTPROTO_L2CAP
202109. BTPROTO_RFCOMM
202110. BTPROTO_SCO
202111. BTR0_BRP_MASK
202112. BTR0_SET_BRP
202113. BTR0_SET_SJW
202114. BTR0_SJW_MASK
202115. BTR0_SJW_SHIFT
202116. BTR1_SAM_SHIFT
202117. BTR1_SET_SAM
202118. BTR1_SET_TSEG1
202119. BTR1_SET_TSEG2
202120. BTR1_TSEG1_MASK
202121. BTR1_TSEG2_MASK
202122. BTR1_TSEG2_SHIFT
202123. BTRACKING_MODE
202124. BTRAP
202125. BTRAPS
202126. BTRAPTL1
202127. BTRBR
202128. BTREE_ATTR_BADCLOSE
202129. BTREE_CSUM_XOR
202130. BTREE_DOUBLE_TYPE
202131. BTREE_FLAG
202132. BTREE_FLOAT_TYPE
202133. BTREE_FLUSH_NR
202134. BTREE_FN
202135. BTREE_H
202136. BTREE_INSERT_STATUS_BACK_MERGE
202137. BTREE_INSERT_STATUS_FRONT_MERGE
202138. BTREE_INSERT_STATUS_INSERT
202139. BTREE_INSERT_STATUS_NO_INSERT
202140. BTREE_INSERT_STATUS_OVERWROTE
202141. BTREE_INT32_TYPE
202142. BTREE_INT64_TYPE
202143. BTREE_KEYTYPE
202144. BTREE_MAX_PAGES
202145. BTREE_NODE_dirty
202146. BTREE_NODE_io_error
202147. BTREE_NODE_journal_flush
202148. BTREE_NODE_write_idx
202149. BTREE_PRIO
202150. BTREE_STRING_TYPE
202151. BTREE_TP
202152. BTREE_TYPE_BITS
202153. BTREE_TYPE_GEO
202154. BTREE_TYPE_HEAD
202155. BTREE_TYPE_SUFFIX
202156. BTREE_UINT32_TYPE
202157. BTREE_UINT64_TYPE
202158. BTREND
202159. BTRFSIC_BLOCK_HASHTABLE_SIZE
202160. BTRFSIC_BLOCK_LINK_HASHTABLE_SIZE
202161. BTRFSIC_BLOCK_LINK_MAGIC_NUMBER
202162. BTRFSIC_BLOCK_MAGIC_NUMBER
202163. BTRFSIC_BLOCK_STACK_FRAME_MAGIC_NUMBER
202164. BTRFSIC_DEV2STATE_HASHTABLE_SIZE
202165. BTRFSIC_DEV2STATE_MAGIC_NUMBER
202166. BTRFSIC_GENERATION_UNKNOWN
202167. BTRFSIC_PRINT_MASK_END_IO_BIO_BH
202168. BTRFSIC_PRINT_MASK_INITIAL_ALL_TREES
202169. BTRFSIC_PRINT_MASK_INITIAL_DATABASE
202170. BTRFSIC_PRINT_MASK_INITIAL_TREE
202171. BTRFSIC_PRINT_MASK_NUM_COPIES
202172. BTRFSIC_PRINT_MASK_ROOT_CHUNK_LOG_TREE_LOCATION
202173. BTRFSIC_PRINT_MASK_SUBMIT_BIO_BH
202174. BTRFSIC_PRINT_MASK_SUBMIT_BIO_BH_VERBOSE
202175. BTRFSIC_PRINT_MASK_SUPERBLOCK_WRITE
202176. BTRFSIC_PRINT_MASK_TREE_AFTER_SB_WRITE
202177. BTRFSIC_PRINT_MASK_TREE_BEFORE_SB_WRITE
202178. BTRFSIC_PRINT_MASK_TREE_WITH_ALL_MIRRORS
202179. BTRFSIC_PRINT_MASK_VERBOSE
202180. BTRFSIC_PRINT_MASK_VERY_VERBOSE
202181. BTRFSIC_TREE_DUMP_MAX_INDENT_LEVEL
202182. BTRFS_ADD_DELAYED_EXTENT
202183. BTRFS_ADD_DELAYED_REF
202184. BTRFS_ASYNC_THREAD_H
202185. BTRFS_ATTR
202186. BTRFS_ATTR_PTR
202187. BTRFS_ATTR_RW
202188. BTRFS_AVAIL_ALLOC_BIT_SINGLE
202189. BTRFS_BACKREF_H
202190. BTRFS_BACKREF_REV_MASK
202191. BTRFS_BACKREF_REV_MAX
202192. BTRFS_BACKREF_REV_SHIFT
202193. BTRFS_BALANCE_ARGS_CONVERT
202194. BTRFS_BALANCE_ARGS_DEVID
202195. BTRFS_BALANCE_ARGS_DRANGE
202196. BTRFS_BALANCE_ARGS_LIMIT
202197. BTRFS_BALANCE_ARGS_LIMIT_RANGE
202198. BTRFS_BALANCE_ARGS_MASK
202199. BTRFS_BALANCE_ARGS_PROFILES
202200. BTRFS_BALANCE_ARGS_SOFT
202201. BTRFS_BALANCE_ARGS_STRIPES_RANGE
202202. BTRFS_BALANCE_ARGS_USAGE
202203. BTRFS_BALANCE_ARGS_USAGE_RANGE
202204. BTRFS_BALANCE_ARGS_VRANGE
202205. BTRFS_BALANCE_CTL_CANCEL
202206. BTRFS_BALANCE_CTL_PAUSE
202207. BTRFS_BALANCE_DATA
202208. BTRFS_BALANCE_FORCE
202209. BTRFS_BALANCE_ITEM_KEY
202210. BTRFS_BALANCE_METADATA
202211. BTRFS_BALANCE_OBJECTID
202212. BTRFS_BALANCE_RESUME
202213. BTRFS_BALANCE_STATE_CANCEL_REQ
202214. BTRFS_BALANCE_STATE_PAUSE_REQ
202215. BTRFS_BALANCE_STATE_RUNNING
202216. BTRFS_BALANCE_SYSTEM
202217. BTRFS_BALANCE_TYPE_MASK
202218. BTRFS_BDEV_BLOCKSIZE
202219. BTRFS_BIO_INLINE_CSUM_SIZE
202220. BTRFS_BLOCK_FLAG_FULL_BACKREF
202221. BTRFS_BLOCK_GROUP_DATA
202222. BTRFS_BLOCK_GROUP_DUP
202223. BTRFS_BLOCK_GROUP_H
202224. BTRFS_BLOCK_GROUP_ITEM_KEY
202225. BTRFS_BLOCK_GROUP_METADATA
202226. BTRFS_BLOCK_GROUP_PROFILE_MASK
202227. BTRFS_BLOCK_GROUP_RAID0
202228. BTRFS_BLOCK_GROUP_RAID1
202229. BTRFS_BLOCK_GROUP_RAID10
202230. BTRFS_BLOCK_GROUP_RAID1_MASK
202231. BTRFS_BLOCK_GROUP_RAID5
202232. BTRFS_BLOCK_GROUP_RAID56_MASK
202233. BTRFS_BLOCK_GROUP_RAID6
202234. BTRFS_BLOCK_GROUP_RESERVED
202235. BTRFS_BLOCK_GROUP_SYSTEM
202236. BTRFS_BLOCK_GROUP_TYPE_MASK
202237. BTRFS_BLOCK_RSV_CHUNK
202238. BTRFS_BLOCK_RSV_DELALLOC
202239. BTRFS_BLOCK_RSV_DELOPS
202240. BTRFS_BLOCK_RSV_DELREFS
202241. BTRFS_BLOCK_RSV_EMPTY
202242. BTRFS_BLOCK_RSV_GLOBAL
202243. BTRFS_BLOCK_RSV_H
202244. BTRFS_BLOCK_RSV_TEMP
202245. BTRFS_BLOCK_RSV_TRANS
202246. BTRFS_BTREE_INODE_OBJECTID
202247. BTRFS_BYTES_TO_BLKS
202248. BTRFS_CACHE_ERROR
202249. BTRFS_CACHE_FAST
202250. BTRFS_CACHE_FINISHED
202251. BTRFS_CACHE_NO
202252. BTRFS_CACHE_STARTED
202253. BTRFS_CHECK_INTEGRITY_H
202254. BTRFS_CHUNK_ITEM_KEY
202255. BTRFS_CHUNK_TREE_OBJECTID
202256. BTRFS_COMPARE_TREE_CHANGED
202257. BTRFS_COMPARE_TREE_DELETED
202258. BTRFS_COMPARE_TREE_NEW
202259. BTRFS_COMPARE_TREE_SAME
202260. BTRFS_COMPRESSION_H
202261. BTRFS_COMPRESS_LZO
202262. BTRFS_COMPRESS_NONE
202263. BTRFS_COMPRESS_TYPES
202264. BTRFS_COMPRESS_ZLIB
202265. BTRFS_COMPRESS_ZSTD
202266. BTRFS_CSUM_SIZE
202267. BTRFS_CSUM_TREE_OBJECTID
202268. BTRFS_CSUM_TYPE_CRC32
202269. BTRFS_CTREE_H
202270. BTRFS_DATA_RELOC_TREE_OBJECTID
202271. BTRFS_DC_CLEAR
202272. BTRFS_DC_ERROR
202273. BTRFS_DC_SETUP
202274. BTRFS_DC_WRITTEN
202275. BTRFS_DEFAULT_COMMIT_INTERVAL
202276. BTRFS_DEFAULT_MAX_INLINE
202277. BTRFS_DEFRAG_BATCH
202278. BTRFS_DEFRAG_RANGE_COMPRESS
202279. BTRFS_DEFRAG_RANGE_START_IO
202280. BTRFS_DELALLOC_SPACE_H
202281. BTRFS_DELAYED_BACKGROUND
202282. BTRFS_DELAYED_BATCH
202283. BTRFS_DELAYED_DELETION_ITEM
202284. BTRFS_DELAYED_INODE_H
202285. BTRFS_DELAYED_INSERTION_ITEM
202286. BTRFS_DELAYED_NODE_DEL_IREF
202287. BTRFS_DELAYED_NODE_INODE_DIRTY
202288. BTRFS_DELAYED_NODE_IN_LIST
202289. BTRFS_DELAYED_REF_H
202290. BTRFS_DELAYED_WRITEBACK
202291. BTRFS_DEVICE_GETSET_FUNCS
202292. BTRFS_DEVICE_PATH_NAME_MAX
202293. BTRFS_DEVICE_SPEC_BY_ID
202294. BTRFS_DEV_EXTENT_KEY
202295. BTRFS_DEV_ITEMS_OBJECTID
202296. BTRFS_DEV_ITEM_KEY
202297. BTRFS_DEV_REPLACE_DEVID
202298. BTRFS_DEV_REPLACE_H
202299. BTRFS_DEV_REPLACE_ITEM_CONT_READING_FROM_SRCDEV_MODE_ALWAYS
202300. BTRFS_DEV_REPLACE_ITEM_CONT_READING_FROM_SRCDEV_MODE_AVOID
202301. BTRFS_DEV_REPLACE_KEY
202302. BTRFS_DEV_STATE_FLUSH_SENT
202303. BTRFS_DEV_STATE_IN_FS_METADATA
202304. BTRFS_DEV_STATE_MISSING
202305. BTRFS_DEV_STATE_REPLACE_TGT
202306. BTRFS_DEV_STATE_WRITEABLE
202307. BTRFS_DEV_STATS_KEY
202308. BTRFS_DEV_STATS_OBJECTID
202309. BTRFS_DEV_STATS_RESET
202310. BTRFS_DEV_STAT_CORRUPTION_ERRS
202311. BTRFS_DEV_STAT_FLUSH_ERRS
202312. BTRFS_DEV_STAT_GENERATION_ERRS
202313. BTRFS_DEV_STAT_READ_ERRS
202314. BTRFS_DEV_STAT_VALUES_MAX
202315. BTRFS_DEV_STAT_WRITE_ERRS
202316. BTRFS_DEV_TREE_OBJECTID
202317. BTRFS_DIO_ORIG_BIO_SUBMITTED
202318. BTRFS_DIRTY_METADATA_THRESH
202319. BTRFS_DIR_INDEX_KEY
202320. BTRFS_DIR_ITEM_KEY
202321. BTRFS_DIR_LOG_INDEX_KEY
202322. BTRFS_DIR_LOG_ITEM_KEY
202323. BTRFS_DISK_IO_H
202324. BTRFS_DONT_NEED_LOG_SYNC
202325. BTRFS_DONT_NEED_TRANS_COMMIT
202326. BTRFS_DROP_DELAYED_REF
202327. BTRFS_EMPTY_DIR_SIZE
202328. BTRFS_EMPTY_SUBVOL_DIR_OBJECTID
202329. BTRFS_ERROR_DEV_EXCL_RUN_IN_PROGRESS
202330. BTRFS_ERROR_DEV_MISSING_NOT_FOUND
202331. BTRFS_ERROR_DEV_ONLY_WRITABLE
202332. BTRFS_ERROR_DEV_RAID10_MIN_NOT_MET
202333. BTRFS_ERROR_DEV_RAID1_MIN_NOT_MET
202334. BTRFS_ERROR_DEV_RAID5_MIN_NOT_MET
202335. BTRFS_ERROR_DEV_RAID6_MIN_NOT_MET
202336. BTRFS_ERROR_DEV_TGT_REPLACE
202337. BTRFS_EXPORT_H
202338. BTRFS_EXTENDED_PROFILE_MASK
202339. BTRFS_EXTENT_CSUM_KEY
202340. BTRFS_EXTENT_CSUM_OBJECTID
202341. BTRFS_EXTENT_DATA_KEY
202342. BTRFS_EXTENT_DATA_REF_KEY
202343. BTRFS_EXTENT_FLAG_DATA
202344. BTRFS_EXTENT_FLAG_SUPER
202345. BTRFS_EXTENT_FLAG_TREE_BLOCK
202346. BTRFS_EXTENT_IO_H
202347. BTRFS_EXTENT_ITEM_KEY
202348. BTRFS_EXTENT_MAP_H
202349. BTRFS_EXTENT_REF_V0_KEY
202350. BTRFS_EXTENT_TREE_OBJECTID
202351. BTRFS_FEATURE_COMPAT_RO_FREE_SPACE_TREE
202352. BTRFS_FEATURE_COMPAT_RO_FREE_SPACE_TREE_VALID
202353. BTRFS_FEATURE_COMPAT_RO_SAFE_CLEAR
202354. BTRFS_FEATURE_COMPAT_RO_SAFE_SET
202355. BTRFS_FEATURE_COMPAT_RO_SUPP
202356. BTRFS_FEATURE_COMPAT_SAFE_CLEAR
202357. BTRFS_FEATURE_COMPAT_SAFE_SET
202358. BTRFS_FEATURE_COMPAT_SUPP
202359. BTRFS_FEATURE_INCOMPAT_BIG_METADATA
202360. BTRFS_FEATURE_INCOMPAT_COMPRESS_LZO
202361. BTRFS_FEATURE_INCOMPAT_COMPRESS_ZSTD
202362. BTRFS_FEATURE_INCOMPAT_DEFAULT_SUBVOL
202363. BTRFS_FEATURE_INCOMPAT_EXTENDED_IREF
202364. BTRFS_FEATURE_INCOMPAT_METADATA_UUID
202365. BTRFS_FEATURE_INCOMPAT_MIXED_BACKREF
202366. BTRFS_FEATURE_INCOMPAT_MIXED_GROUPS
202367. BTRFS_FEATURE_INCOMPAT_NO_HOLES
202368. BTRFS_FEATURE_INCOMPAT_RAID56
202369. BTRFS_FEATURE_INCOMPAT_SAFE_CLEAR
202370. BTRFS_FEATURE_INCOMPAT_SAFE_SET
202371. BTRFS_FEATURE_INCOMPAT_SKINNY_METADATA
202372. BTRFS_FEATURE_INCOMPAT_SUPP
202373. BTRFS_FEATURE_NAME_MAX
202374. BTRFS_FEAT_ATTR
202375. BTRFS_FEAT_ATTR_COMPAT
202376. BTRFS_FEAT_ATTR_COMPAT_RO
202377. BTRFS_FEAT_ATTR_INCOMPAT
202378. BTRFS_FEAT_ATTR_PTR
202379. BTRFS_FID_SIZE_CONNECTABLE
202380. BTRFS_FID_SIZE_CONNECTABLE_ROOT
202381. BTRFS_FID_SIZE_NON_CONNECTABLE
202382. BTRFS_FIEMAP_FLAGS
202383. BTRFS_FILE_EXTENT_INLINE
202384. BTRFS_FILE_EXTENT_INLINE_DATA_START
202385. BTRFS_FILE_EXTENT_PREALLOC
202386. BTRFS_FILE_EXTENT_REG
202387. BTRFS_FILE_EXTENT_TYPES
202388. BTRFS_FIRST_CHUNK_TREE_OBJECTID
202389. BTRFS_FIRST_FREE_OBJECTID
202390. BTRFS_FREE_INO_OBJECTID
202391. BTRFS_FREE_SPACE_BITMAP
202392. BTRFS_FREE_SPACE_BITMAP_BITS
202393. BTRFS_FREE_SPACE_BITMAP_KEY
202394. BTRFS_FREE_SPACE_BITMAP_SIZE
202395. BTRFS_FREE_SPACE_CACHE_H
202396. BTRFS_FREE_SPACE_EXTENT
202397. BTRFS_FREE_SPACE_EXTENT_KEY
202398. BTRFS_FREE_SPACE_INFO_KEY
202399. BTRFS_FREE_SPACE_OBJECTID
202400. BTRFS_FREE_SPACE_TREE_H
202401. BTRFS_FREE_SPACE_TREE_OBJECTID
202402. BTRFS_FREE_SPACE_USING_BITMAPS
202403. BTRFS_FSID_SIZE
202404. BTRFS_FS_BALANCE_RUNNING
202405. BTRFS_FS_BARRIER
202406. BTRFS_FS_BTREE_ERR
202407. BTRFS_FS_CLEANER_RUNNING
202408. BTRFS_FS_CLOSING_DONE
202409. BTRFS_FS_CLOSING_START
202410. BTRFS_FS_CREATING_FREE_SPACE_TREE
202411. BTRFS_FS_CSUM_IMPL_FAST
202412. BTRFS_FS_EXCL_OP
202413. BTRFS_FS_FROZEN
202414. BTRFS_FS_LOG1_ERR
202415. BTRFS_FS_LOG2_ERR
202416. BTRFS_FS_LOG_RECOVERING
202417. BTRFS_FS_NEED_ASYNC_COMMIT
202418. BTRFS_FS_OPEN
202419. BTRFS_FS_QUOTA_ENABLED
202420. BTRFS_FS_QUOTA_OVERRIDE
202421. BTRFS_FS_STATE_DEV_REPLACING
202422. BTRFS_FS_STATE_DUMMY_FS_INFO
202423. BTRFS_FS_STATE_ERROR
202424. BTRFS_FS_STATE_REMOUNTING
202425. BTRFS_FS_STATE_TRANS_ABORTED
202426. BTRFS_FS_TREE_OBJECTID
202427. BTRFS_FS_UPDATE_UUID_TREE_GEN
202428. BTRFS_FT_BLKDEV
202429. BTRFS_FT_CHRDEV
202430. BTRFS_FT_DIR
202431. BTRFS_FT_FIFO
202432. BTRFS_FT_MAX
202433. BTRFS_FT_REG_FILE
202434. BTRFS_FT_SOCK
202435. BTRFS_FT_SYMLINK
202436. BTRFS_FT_UNKNOWN
202437. BTRFS_FT_XATTR
202438. BTRFS_GROUP_FLAGS
202439. BTRFS_HEADER_FLAG_RELOC
202440. BTRFS_HEADER_FLAG_WRITTEN
202441. BTRFS_I
202442. BTRFS_INODE_APPEND
202443. BTRFS_INODE_COMPRESS
202444. BTRFS_INODE_COPY_EVERYTHING
202445. BTRFS_INODE_DIRSYNC
202446. BTRFS_INODE_DUMMY
202447. BTRFS_INODE_EXTREF_KEY
202448. BTRFS_INODE_FLAG_MASK
202449. BTRFS_INODE_H
202450. BTRFS_INODE_HAS_ASYNC_EXTENT
202451. BTRFS_INODE_HAS_PROPS
202452. BTRFS_INODE_IMMUTABLE
202453. BTRFS_INODE_IN_DEFRAG
202454. BTRFS_INODE_IN_DELALLOC_LIST
202455. BTRFS_INODE_ITEM_KEY
202456. BTRFS_INODE_MAP_H
202457. BTRFS_INODE_NEEDS_FULL_SYNC
202458. BTRFS_INODE_NOATIME
202459. BTRFS_INODE_NOCOMPRESS
202460. BTRFS_INODE_NODATACOW
202461. BTRFS_INODE_NODATASUM
202462. BTRFS_INODE_NODUMP
202463. BTRFS_INODE_ORDERED_DATA_CLOSE
202464. BTRFS_INODE_PREALLOC
202465. BTRFS_INODE_READDIO_NEED_LOCK
202466. BTRFS_INODE_READONLY
202467. BTRFS_INODE_REF_KEY
202468. BTRFS_INODE_ROOT_ITEM_INIT
202469. BTRFS_INODE_SNAPSHOT_FLUSH
202470. BTRFS_INODE_SYNC
202471. BTRFS_INO_LOOKUP_PATH_MAX
202472. BTRFS_INO_LOOKUP_USER_PATH_MAX
202473. BTRFS_IOCTL_DEV_REPLACE_CMD_CANCEL
202474. BTRFS_IOCTL_DEV_REPLACE_CMD_START
202475. BTRFS_IOCTL_DEV_REPLACE_CMD_STATUS
202476. BTRFS_IOCTL_DEV_REPLACE_CONT_READING_FROM_SRCDEV_MODE_ALWAYS
202477. BTRFS_IOCTL_DEV_REPLACE_CONT_READING_FROM_SRCDEV_MODE_AVOID
202478. BTRFS_IOCTL_DEV_REPLACE_RESULT_ALREADY_STARTED
202479. BTRFS_IOCTL_DEV_REPLACE_RESULT_NOT_STARTED
202480. BTRFS_IOCTL_DEV_REPLACE_RESULT_NO_ERROR
202481. BTRFS_IOCTL_DEV_REPLACE_RESULT_SCRUB_INPROGRESS
202482. BTRFS_IOCTL_DEV_REPLACE_STATE_CANCELED
202483. BTRFS_IOCTL_DEV_REPLACE_STATE_FINISHED
202484. BTRFS_IOCTL_DEV_REPLACE_STATE_NEVER_STARTED
202485. BTRFS_IOCTL_DEV_REPLACE_STATE_STARTED
202486. BTRFS_IOCTL_DEV_REPLACE_STATE_SUSPENDED
202487. BTRFS_IOCTL_MAGIC
202488. BTRFS_IOC_ADD_DEV
202489. BTRFS_IOC_BALANCE
202490. BTRFS_IOC_BALANCE_CTL
202491. BTRFS_IOC_BALANCE_PROGRESS
202492. BTRFS_IOC_BALANCE_V2
202493. BTRFS_IOC_CLONE
202494. BTRFS_IOC_CLONE_RANGE
202495. BTRFS_IOC_DEFAULT_SUBVOL
202496. BTRFS_IOC_DEFRAG
202497. BTRFS_IOC_DEFRAG_RANGE
202498. BTRFS_IOC_DEVICES_READY
202499. BTRFS_IOC_DEV_INFO
202500. BTRFS_IOC_DEV_REPLACE
202501. BTRFS_IOC_FILE_EXTENT_SAME
202502. BTRFS_IOC_FORGET_DEV
202503. BTRFS_IOC_FS_INFO
202504. BTRFS_IOC_GET_DEV_STATS
202505. BTRFS_IOC_GET_FEATURES
202506. BTRFS_IOC_GET_FSLABEL
202507. BTRFS_IOC_GET_SUBVOL_INFO
202508. BTRFS_IOC_GET_SUBVOL_ROOTREF
202509. BTRFS_IOC_GET_SUPPORTED_FEATURES
202510. BTRFS_IOC_INO_LOOKUP
202511. BTRFS_IOC_INO_LOOKUP_USER
202512. BTRFS_IOC_INO_PATHS
202513. BTRFS_IOC_LOGICAL_INO
202514. BTRFS_IOC_LOGICAL_INO_V2
202515. BTRFS_IOC_QGROUP_ASSIGN
202516. BTRFS_IOC_QGROUP_CREATE
202517. BTRFS_IOC_QGROUP_LIMIT
202518. BTRFS_IOC_QUOTA_CTL
202519. BTRFS_IOC_QUOTA_RESCAN
202520. BTRFS_IOC_QUOTA_RESCAN_STATUS
202521. BTRFS_IOC_QUOTA_RESCAN_WAIT
202522. BTRFS_IOC_RESIZE
202523. BTRFS_IOC_RM_DEV
202524. BTRFS_IOC_RM_DEV_V2
202525. BTRFS_IOC_SCAN_DEV
202526. BTRFS_IOC_SCRUB
202527. BTRFS_IOC_SCRUB_CANCEL
202528. BTRFS_IOC_SCRUB_PROGRESS
202529. BTRFS_IOC_SEND
202530. BTRFS_IOC_SEND_32
202531. BTRFS_IOC_SET_FEATURES
202532. BTRFS_IOC_SET_FSLABEL
202533. BTRFS_IOC_SET_RECEIVED_SUBVOL
202534. BTRFS_IOC_SET_RECEIVED_SUBVOL_32
202535. BTRFS_IOC_SNAP_CREATE
202536. BTRFS_IOC_SNAP_CREATE_V2
202537. BTRFS_IOC_SNAP_DESTROY
202538. BTRFS_IOC_SPACE_INFO
202539. BTRFS_IOC_START_SYNC
202540. BTRFS_IOC_SUBVOL_CREATE
202541. BTRFS_IOC_SUBVOL_CREATE_V2
202542. BTRFS_IOC_SUBVOL_GETFLAGS
202543. BTRFS_IOC_SUBVOL_SETFLAGS
202544. BTRFS_IOC_SYNC
202545. BTRFS_IOC_TRANS_END
202546. BTRFS_IOC_TRANS_START
202547. BTRFS_IOC_TREE_SEARCH
202548. BTRFS_IOC_TREE_SEARCH_V2
202549. BTRFS_IOC_WAIT_SYNC
202550. BTRFS_IOPRIO_READA
202551. BTRFS_LABEL_SIZE
202552. BTRFS_LAST_FREE_OBJECTID
202553. BTRFS_LEAF_DATA_OFFSET
202554. BTRFS_LEAF_DATA_SIZE
202555. BTRFS_LINK_MAX
202556. BTRFS_LOCKING_H
202557. BTRFS_LOGICAL_INO_ARGS_IGNORE_OFFSET
202558. BTRFS_MAGIC
202559. BTRFS_MAP_DISCARD
202560. BTRFS_MAP_GET_READ_MIRRORS
202561. BTRFS_MAP_READ
202562. BTRFS_MAP_WRITE
202563. BTRFS_MAX_COMPRESSED
202564. BTRFS_MAX_DATA_CHUNK_SIZE
202565. BTRFS_MAX_DEDUPE_LEN
202566. BTRFS_MAX_DEVS
202567. BTRFS_MAX_DEVS_SYS_CHUNK
202568. BTRFS_MAX_EXTENT_ITEM_SIZE
202569. BTRFS_MAX_EXTENT_SIZE
202570. BTRFS_MAX_INLINE_DATA_SIZE
202571. BTRFS_MAX_ITEM_SIZE
202572. BTRFS_MAX_LEVEL
202573. BTRFS_MAX_METADATA_BLOCKSIZE
202574. BTRFS_MAX_MIRRORS
202575. BTRFS_MAX_ROOTREF_BUFFER_NUM
202576. BTRFS_MAX_UNCOMPRESSED
202577. BTRFS_MAX_XATTR_SIZE
202578. BTRFS_METADATA_ITEM_KEY
202579. BTRFS_MINOR
202580. BTRFS_MISC_H
202581. BTRFS_MIXED_BACKREF_REV
202582. BTRFS_MOUNT_AUTO_DEFRAG
202583. BTRFS_MOUNT_CHECK_INTEGRITY
202584. BTRFS_MOUNT_CHECK_INTEGRITY_INCLUDING_EXTENT_DATA
202585. BTRFS_MOUNT_CLEAR_CACHE
202586. BTRFS_MOUNT_COMPRESS
202587. BTRFS_MOUNT_DEGRADED
202588. BTRFS_MOUNT_DISCARD
202589. BTRFS_MOUNT_ENOSPC_DEBUG
202590. BTRFS_MOUNT_FLUSHONCOMMIT
202591. BTRFS_MOUNT_FORCE_COMPRESS
202592. BTRFS_MOUNT_FRAGMENT_DATA
202593. BTRFS_MOUNT_FRAGMENT_METADATA
202594. BTRFS_MOUNT_FREE_SPACE_TREE
202595. BTRFS_MOUNT_INODE_MAP_CACHE
202596. BTRFS_MOUNT_NOBARRIER
202597. BTRFS_MOUNT_NODATACOW
202598. BTRFS_MOUNT_NODATASUM
202599. BTRFS_MOUNT_NOLOGREPLAY
202600. BTRFS_MOUNT_NOSSD
202601. BTRFS_MOUNT_NOTREELOG
202602. BTRFS_MOUNT_PANIC_ON_FATAL_ERROR
202603. BTRFS_MOUNT_REF_VERIFY
202604. BTRFS_MOUNT_RESCAN_UUID_TREE
202605. BTRFS_MOUNT_SKIP_BALANCE
202606. BTRFS_MOUNT_SPACE_CACHE
202607. BTRFS_MOUNT_SSD
202608. BTRFS_MOUNT_SSD_SPREAD
202609. BTRFS_MOUNT_USEBACKUPROOT
202610. BTRFS_MOUNT_USER_SUBVOL_RM_ALLOWED
202611. BTRFS_MULTIPLE_OBJECTIDS
202612. BTRFS_NAME_LEN
202613. BTRFS_NEED_LOG_SYNC
202614. BTRFS_NEED_TRANS_COMMIT
202615. BTRFS_NODEPTRS_PER_BLOCK
202616. BTRFS_NO_LOG_SYNC
202617. BTRFS_NR_RAID_TYPES
202618. BTRFS_NR_WORKSPACE_MANAGERS
202619. BTRFS_NUM_BACKUP_ROOTS
202620. BTRFS_OLDEST_GENERATION
202621. BTRFS_OLD_BACKREF_REV
202622. BTRFS_ORDERED_COMPLETE
202623. BTRFS_ORDERED_COMPRESSED
202624. BTRFS_ORDERED_DATA_H
202625. BTRFS_ORDERED_DIRECT
202626. BTRFS_ORDERED_IOERR
202627. BTRFS_ORDERED_IO_DONE
202628. BTRFS_ORDERED_NOCOW
202629. BTRFS_ORDERED_PREALLOC
202630. BTRFS_ORDERED_REGULAR
202631. BTRFS_ORDERED_TRUNCATED
202632. BTRFS_ORDERED_UPDATED_ISIZE
202633. BTRFS_ORPHAN_ITEM_KEY
202634. BTRFS_ORPHAN_OBJECTID
202635. BTRFS_PATH_NAME_MAX
202636. BTRFS_PENDING_CLEAR_INODE_MAP_CACHE
202637. BTRFS_PENDING_COMMIT
202638. BTRFS_PENDING_SET_INODE_MAP_CACHE
202639. BTRFS_PERSISTENT_ITEM_KEY
202640. BTRFS_PRINT_TREE_H
202641. BTRFS_PROPS_H
202642. BTRFS_PROP_HANDLERS_HT_BITS
202643. BTRFS_QGROUP_H
202644. BTRFS_QGROUP_INFO_KEY
202645. BTRFS_QGROUP_INHERIT_SET_LIMITS
202646. BTRFS_QGROUP_LEVEL_SHIFT
202647. BTRFS_QGROUP_LIMIT_EXCL_CMPR
202648. BTRFS_QGROUP_LIMIT_KEY
202649. BTRFS_QGROUP_LIMIT_MAX_EXCL
202650. BTRFS_QGROUP_LIMIT_MAX_RFER
202651. BTRFS_QGROUP_LIMIT_RFER_CMPR
202652. BTRFS_QGROUP_LIMIT_RSV_EXCL
202653. BTRFS_QGROUP_LIMIT_RSV_RFER
202654. BTRFS_QGROUP_OPERATIONS
202655. BTRFS_QGROUP_RELATION_KEY
202656. BTRFS_QGROUP_RSV_DATA
202657. BTRFS_QGROUP_RSV_LAST
202658. BTRFS_QGROUP_RSV_META_PERTRANS
202659. BTRFS_QGROUP_RSV_META_PREALLOC
202660. BTRFS_QGROUP_STATUS_FLAG_INCONSISTENT
202661. BTRFS_QGROUP_STATUS_FLAG_ON
202662. BTRFS_QGROUP_STATUS_FLAG_RESCAN
202663. BTRFS_QGROUP_STATUS_KEY
202664. BTRFS_QGROUP_STATUS_VERSION
202665. BTRFS_QUOTA_CTL_DISABLE
202666. BTRFS_QUOTA_CTL_ENABLE
202667. BTRFS_QUOTA_CTL_RESCAN__NOTUSED
202668. BTRFS_QUOTA_TREE_OBJECTID
202669. BTRFS_RAID56_H
202670. BTRFS_RAID_DUP
202671. BTRFS_RAID_RAID0
202672. BTRFS_RAID_RAID1
202673. BTRFS_RAID_RAID10
202674. BTRFS_RAID_RAID5
202675. BTRFS_RAID_RAID6
202676. BTRFS_RAID_SINGLE
202677. BTRFS_RBIO_PARITY_SCRUB
202678. BTRFS_RBIO_READ_REBUILD
202679. BTRFS_RBIO_REBUILD_MISSING
202680. BTRFS_RBIO_WRITE
202681. BTRFS_RCU_STRING_H
202682. BTRFS_READ_LOCK
202683. BTRFS_READ_LOCK_BLOCKING
202684. BTRFS_REF_DATA
202685. BTRFS_REF_LAST
202686. BTRFS_REF_METADATA
202687. BTRFS_REF_NOT_SET
202688. BTRFS_REF_TYPE_ANY
202689. BTRFS_REF_TYPE_BLOCK
202690. BTRFS_REF_TYPE_DATA
202691. BTRFS_REF_TYPE_INVALID
202692. BTRFS_REF_VERIFY_H
202693. BTRFS_RESERVE_FLUSH_ALL
202694. BTRFS_RESERVE_FLUSH_EVICT
202695. BTRFS_RESERVE_FLUSH_LIMIT
202696. BTRFS_RESERVE_NO_FLUSH
202697. BTRFS_ROOT_BACKREF_KEY
202698. BTRFS_ROOT_DEAD_RELOC_TREE
202699. BTRFS_ROOT_DEAD_TREE
202700. BTRFS_ROOT_DEFRAG_RUNNING
202701. BTRFS_ROOT_DELETING
202702. BTRFS_ROOT_DIRTY
202703. BTRFS_ROOT_FORCE_COW
202704. BTRFS_ROOT_IN_RADIX
202705. BTRFS_ROOT_IN_TRANS_SETUP
202706. BTRFS_ROOT_ITEM_KEY
202707. BTRFS_ROOT_MULTI_LOG_TASKS
202708. BTRFS_ROOT_ORPHAN_ITEM_INSERTED
202709. BTRFS_ROOT_REF_COWS
202710. BTRFS_ROOT_REF_KEY
202711. BTRFS_ROOT_SUBVOL_DEAD
202712. BTRFS_ROOT_SUBVOL_RDONLY
202713. BTRFS_ROOT_TRACK_DIRTY
202714. BTRFS_ROOT_TRANS_TAG
202715. BTRFS_ROOT_TREE_DIR_OBJECTID
202716. BTRFS_ROOT_TREE_OBJECTID
202717. BTRFS_SAME_DATA_DIFFERS
202718. BTRFS_SCRUB_READONLY
202719. BTRFS_SEARCH_ARGS_BUFSIZE
202720. BTRFS_SEND_A_ATIME
202721. BTRFS_SEND_A_CLONE_CTRANSID
202722. BTRFS_SEND_A_CLONE_LEN
202723. BTRFS_SEND_A_CLONE_OFFSET
202724. BTRFS_SEND_A_CLONE_PATH
202725. BTRFS_SEND_A_CLONE_UUID
202726. BTRFS_SEND_A_CTIME
202727. BTRFS_SEND_A_CTRANSID
202728. BTRFS_SEND_A_DATA
202729. BTRFS_SEND_A_FILE_OFFSET
202730. BTRFS_SEND_A_GID
202731. BTRFS_SEND_A_INO
202732. BTRFS_SEND_A_MAX
202733. BTRFS_SEND_A_MODE
202734. BTRFS_SEND_A_MTIME
202735. BTRFS_SEND_A_OTIME
202736. BTRFS_SEND_A_PATH
202737. BTRFS_SEND_A_PATH_LINK
202738. BTRFS_SEND_A_PATH_TO
202739. BTRFS_SEND_A_RDEV
202740. BTRFS_SEND_A_SIZE
202741. BTRFS_SEND_A_UID
202742. BTRFS_SEND_A_UNSPEC
202743. BTRFS_SEND_A_UUID
202744. BTRFS_SEND_A_XATTR_DATA
202745. BTRFS_SEND_A_XATTR_NAME
202746. BTRFS_SEND_BUF_SIZE
202747. BTRFS_SEND_C_CHMOD
202748. BTRFS_SEND_C_CHOWN
202749. BTRFS_SEND_C_CLONE
202750. BTRFS_SEND_C_END
202751. BTRFS_SEND_C_LINK
202752. BTRFS_SEND_C_MAX
202753. BTRFS_SEND_C_MKDIR
202754. BTRFS_SEND_C_MKFIFO
202755. BTRFS_SEND_C_MKFILE
202756. BTRFS_SEND_C_MKNOD
202757. BTRFS_SEND_C_MKSOCK
202758. BTRFS_SEND_C_REMOVE_XATTR
202759. BTRFS_SEND_C_RENAME
202760. BTRFS_SEND_C_RMDIR
202761. BTRFS_SEND_C_SET_XATTR
202762. BTRFS_SEND_C_SNAPSHOT
202763. BTRFS_SEND_C_SUBVOL
202764. BTRFS_SEND_C_SYMLINK
202765. BTRFS_SEND_C_TRUNCATE
202766. BTRFS_SEND_C_UNLINK
202767. BTRFS_SEND_C_UNSPEC
202768. BTRFS_SEND_C_UPDATE_EXTENT
202769. BTRFS_SEND_C_UTIMES
202770. BTRFS_SEND_C_WRITE
202771. BTRFS_SEND_FLAG_MASK
202772. BTRFS_SEND_FLAG_NO_FILE_DATA
202773. BTRFS_SEND_FLAG_OMIT_END_CMD
202774. BTRFS_SEND_FLAG_OMIT_STREAM_HEADER
202775. BTRFS_SEND_H
202776. BTRFS_SEND_READ_SIZE
202777. BTRFS_SEND_STREAM_MAGIC
202778. BTRFS_SEND_STREAM_VERSION
202779. BTRFS_SEND_TRANS_STUB
202780. BTRFS_SETGET_FUNCS
202781. BTRFS_SETGET_HEADER_FUNCS
202782. BTRFS_SETGET_STACK_FUNCS
202783. BTRFS_SHARED_BLOCK_REF_KEY
202784. BTRFS_SHARED_DATA_REF_KEY
202785. BTRFS_SPACE_INFO_GLOBAL_RSV
202786. BTRFS_SPACE_INFO_H
202787. BTRFS_STRING_ITEM_KEY
202788. BTRFS_STRIPE_HASH_TABLE_BITS
202789. BTRFS_STRIPE_LEN
202790. BTRFS_SUBVOL_CREATE_ASYNC
202791. BTRFS_SUBVOL_NAME_MAX
202792. BTRFS_SUBVOL_QGROUP_INHERIT
202793. BTRFS_SUBVOL_RDONLY
202794. BTRFS_SUPER_FLAG_CHANGING_FSID
202795. BTRFS_SUPER_FLAG_CHANGING_FSID_V2
202796. BTRFS_SUPER_FLAG_ERROR
202797. BTRFS_SUPER_FLAG_METADUMP
202798. BTRFS_SUPER_FLAG_METADUMP_V2
202799. BTRFS_SUPER_FLAG_SEEDING
202800. BTRFS_SUPER_FLAG_SUPP
202801. BTRFS_SUPER_INFO_OFFSET
202802. BTRFS_SUPER_INFO_SIZE
202803. BTRFS_SUPER_MAGIC
202804. BTRFS_SUPER_MIRROR_MAX
202805. BTRFS_SUPER_MIRROR_SHIFT
202806. BTRFS_SYSFS_H
202807. BTRFS_SYSTEM_CHUNK_ARRAY_SIZE
202808. BTRFS_TEMPORARY_ITEM_KEY
202809. BTRFS_TESTS_H
202810. BTRFS_TEST_MAGIC
202811. BTRFS_TLV_BINARY
202812. BTRFS_TLV_STRING
202813. BTRFS_TLV_TIMESPEC
202814. BTRFS_TLV_U16
202815. BTRFS_TLV_U32
202816. BTRFS_TLV_U64
202817. BTRFS_TLV_U8
202818. BTRFS_TLV_UUID
202819. BTRFS_TOTAL_BYTES_PINNED_BATCH
202820. BTRFS_TRANSACTION_H
202821. BTRFS_TRANS_CACHE_ENOSPC
202822. BTRFS_TRANS_DIRTY_BG_RUN
202823. BTRFS_TRANS_HAVE_FREE_BGS
202824. BTRFS_TREE_BLOCK_REF_KEY
202825. BTRFS_TREE_CHECKER_H
202826. BTRFS_TREE_LOG_FIXUP_OBJECTID
202827. BTRFS_TREE_LOG_H
202828. BTRFS_TREE_LOG_OBJECTID
202829. BTRFS_TREE_RELOC_OBJECTID
202830. BTRFS_ULIST_H
202831. BTRFS_UPDATE_DELAYED_HEAD
202832. BTRFS_UUID_KEY_RECEIVED_SUBVOL
202833. BTRFS_UUID_KEY_SUBVOL
202834. BTRFS_UUID_SIZE
202835. BTRFS_UUID_TREE_OBJECTID
202836. BTRFS_UUID_UNPARSED_SIZE
202837. BTRFS_VOLUMES_H
202838. BTRFS_VOL_ARG_V2_FLAGS_SUPPORTED
202839. BTRFS_VOL_NAME_MAX
202840. BTRFS_WQ_ENDIO_DATA
202841. BTRFS_WQ_ENDIO_DIO_REPAIR
202842. BTRFS_WQ_ENDIO_FREE_SPACE
202843. BTRFS_WQ_ENDIO_METADATA
202844. BTRFS_WQ_ENDIO_RAID56
202845. BTRFS_WRITE_LOCK
202846. BTRFS_WRITE_LOCK_BLOCKING
202847. BTRFS_XATTR_H
202848. BTRFS_XATTR_ITEM_KEY
202849. BTRFS_ZLIB_DEFAULT_LEVEL
202850. BTRF_HWPDN_N
202851. BTRSSI_FREQ
202852. BTRSSI_LATCH_PHASE
202853. BTRSTART
202854. BTRSW
202855. BTRSW_ISOLATION_A
202856. BTRSW_ISOLATION_B
202857. BTRSW_ISOLATION_C
202858. BTRSW_ISOLATION_D
202859. BTRSW_TRI_ONLY
202860. BTR_BRP_MASK
202861. BTR_BRP_SHIFT
202862. BTR_DRIFT_MARGIN
202863. BTR_EXIT_MARGIN
202864. BTR_SJW_MASK
202865. BTR_SJW_SHIFT
202866. BTR_TSEG1_MASK
202867. BTR_TSEG1_SHIFT
202868. BTR_TSEG2_MASK
202869. BTR_TSEG2_SHIFT
202870. BTSDIO_DMA_ALIGN
202871. BTSPR
202872. BTSTAT_ABORTQUEUE
202873. BTSTAT_BADMSG
202874. BTSTAT_BUSFREE
202875. BTSTAT_BUSRESET
202876. BTSTAT_DATARUN
202877. BTSTAT_DATA_UNDERRUN
202878. BTSTAT_DISCONNECT
202879. BTSTAT_HAHARDWARE
202880. BTSTAT_HASOFTWARE
202881. BTSTAT_HATIMEOUT
202882. BTSTAT_INVPARAM
202883. BTSTAT_INVPHASE
202884. BTSTAT_LINKED_COMMAND_COMPLETED
202885. BTSTAT_LINKED_COMMAND_COMPLETED_WITH_FLAG
202886. BTSTAT_LUNMISMATCH
202887. BTSTAT_NORESPONSE
202888. BTSTAT_RECVRST
202889. BTSTAT_SCSIPARITY
202890. BTSTAT_SELTIMEO
202891. BTSTAT_SENSFAILED
202892. BTSTAT_SENTRST
202893. BTSTAT_SUCCESS
202894. BTSTAT_TAGREJECT
202895. BTS_BUFFER_SIZE
202896. BTS_RECORD_SIZE
202897. BTS_SAFETY_MARGIN
202898. BTS_STATE_ACTIVE
202899. BTS_STATE_INACTIVE
202900. BTS_STATE_STOPPED
202901. BTTHR
202902. BTTINFO_FLAG_ERROR
202903. BTTINFO_MAJOR_VERSION
202904. BTTINFO_SIG_LEN
202905. BTTINFO_UUID_LEN
202906. BTTV_ALT_DATA
202907. BTTV_ALT_DCLK
202908. BTTV_ALT_NCONFIG
202909. BTTV_BOARD_ACORP_Y878F
202910. BTTV_BOARD_ADLINK_MPG24
202911. BTTV_BOARD_ADLINK_RTV24
202912. BTTV_BOARD_ADSTECH_TV
202913. BTTV_BOARD_AD_TVK503
202914. BTTV_BOARD_AIMMS
202915. BTTV_BOARD_APAC_VIEWCOMP
202916. BTTV_BOARD_APOSONIC_WDVR
202917. BTTV_BOARD_ASKEY_CPH03X
202918. BTTV_BOARD_ASKEY_CPH060
202919. BTTV_BOARD_ASOUND_SKYEYE
202920. BTTV_BOARD_ATI_TVWONDER
202921. BTTV_BOARD_ATI_TVWONDERVE
202922. BTTV_BOARD_AVDVBT_761
202923. BTTV_BOARD_AVDVBT_771
202924. BTTV_BOARD_AVEC_INTERCAP
202925. BTTV_BOARD_AVERMEDIA
202926. BTTV_BOARD_AVERMEDIA98
202927. BTTV_BOARD_AVPHONE98
202928. BTTV_BOARD_BESTBUY_EASYTV
202929. BTTV_BOARD_BESTBUY_EASYTV2
202930. BTTV_BOARD_BT848_CAP_14
202931. BTTV_BOARD_CEI_RAFFLES
202932. BTTV_BOARD_CHRONOS_VS2
202933. BTTV_BOARD_CONCEPTRONIC_CTVFMI2
202934. BTTV_BOARD_CONFERENCETV
202935. BTTV_BOARD_CONTVFMI
202936. BTTV_BOARD_CYBERVISION_CV06
202937. BTTV_BOARD_DIAMOND
202938. BTTV_BOARD_DSP_TCVIDEO
202939. BTTV_BOARD_DVICO_DVBT_LITE
202940. BTTV_BOARD_DVICO_FUSIONHDTV_2
202941. BTTV_BOARD_DVICO_FUSIONHDTV_5_LITE
202942. BTTV_BOARD_DYNALINK
202943. BTTV_BOARD_EAGLE
202944. BTTV_BOARD_ENLTV_FM_2
202945. BTTV_BOARD_EURESYS_PICOLO
202946. BTTV_BOARD_FLYVIDEO
202947. BTTV_BOARD_FLYVIDEO2000
202948. BTTV_BOARD_FLYVIDEO98EZ
202949. BTTV_BOARD_FLYVIDEO_98
202950. BTTV_BOARD_FLYVIDEO_98FM
202951. BTTV_BOARD_FORMAC_PROTV
202952. BTTV_BOARD_GEOVISION_GV600
202953. BTTV_BOARD_GEOVISION_GV800S
202954. BTTV_BOARD_GEOVISION_GV800S_SL
202955. BTTV_BOARD_GMV1
202956. BTTV_BOARD_GRANDTEC
202957. BTTV_BOARD_GRANDTEC_MULTI
202958. BTTV_BOARD_GVBCTV3PCI
202959. BTTV_BOARD_GVBCTV4PCI
202960. BTTV_BOARD_GVBCTV5PCI
202961. BTTV_BOARD_HAUPPAUGE
202962. BTTV_BOARD_HAUPPAUGE878
202963. BTTV_BOARD_HAUPPAUGEPVR
202964. BTTV_BOARD_HAUPPAUGE_IMPACTVCB
202965. BTTV_BOARD_HAUPPAUG_WCAM
202966. BTTV_BOARD_HERCULES_SM_TV
202967. BTTV_BOARD_IDS_EAGLE
202968. BTTV_BOARD_INTEL
202969. BTTV_BOARD_INTEL_C_S_PCI
202970. BTTV_BOARD_IPROTV
202971. BTTV_BOARD_IVC100
202972. BTTV_BOARD_IVC120
202973. BTTV_BOARD_IVC200
202974. BTTV_BOARD_IVCE8784
202975. BTTV_BOARD_KODICOM_4400R
202976. BTTV_BOARD_KODICOM_4400R_SL
202977. BTTV_BOARD_KOZUMI_KTV_01C
202978. BTTV_BOARD_KWORLD
202979. BTTV_BOARD_KWORLD_VSTREAM_XPERT
202980. BTTV_BOARD_LIFETEC_9415
202981. BTTV_BOARD_LIFE_FLYKIT
202982. BTTV_BOARD_LMLBT4
202983. BTTV_BOARD_MACHTV
202984. BTTV_BOARD_MACHTV_MAGICTV
202985. BTTV_BOARD_MAGICTVIEW061
202986. BTTV_BOARD_MAGICTVIEW063
202987. BTTV_BOARD_MATRIX_VISION
202988. BTTV_BOARD_MATRIX_VISION2
202989. BTTV_BOARD_MATRIX_VISIONSLC
202990. BTTV_BOARD_MATRIX_VISIONSQ
202991. BTTV_BOARD_MAXI
202992. BTTV_BOARD_MIRO
202993. BTTV_BOARD_MIROPRO
202994. BTTV_BOARD_MM100PCTV
202995. BTTV_BOARD_MODTEC_205
202996. BTTV_BOARD_NEBULA_DIGITV
202997. BTTV_BOARD_NGSTV_PLUS
202998. BTTV_BOARD_ONAIR_TV
202999. BTTV_BOARD_OSPREY101_848
203000. BTTV_BOARD_OSPREY1x0
203001. BTTV_BOARD_OSPREY1x0_848
203002. BTTV_BOARD_OSPREY1x1
203003. BTTV_BOARD_OSPREY1x1_SVID
203004. BTTV_BOARD_OSPREY2000
203005. BTTV_BOARD_OSPREY2x0
203006. BTTV_BOARD_OSPREY2x0_SVID
203007. BTTV_BOARD_OSPREY2xx
203008. BTTV_BOARD_OSPREY440
203009. BTTV_BOARD_OSPREY500
203010. BTTV_BOARD_OSPREY540
203011. BTTV_BOARD_PACETV
203012. BTTV_BOARD_PCI_8604PW
203013. BTTV_BOARD_PC_HDTV
203014. BTTV_BOARD_PHOEBE_TVMAS
203015. BTTV_BOARD_PICOLO_TETRA_CHIP
203016. BTTV_BOARD_PINNACLE
203017. BTTV_BOARD_PINNACLEPRO
203018. BTTV_BOARD_PINNACLESAT
203019. BTTV_BOARD_PIXVIEWPLAYTV
203020. BTTV_BOARD_POWERCLR_MTV878
203021. BTTV_BOARD_PV143
203022. BTTV_BOARD_PV150
203023. BTTV_BOARD_PV183
203024. BTTV_BOARD_PV951
203025. BTTV_BOARD_PV_BT878P_2E
203026. BTTV_BOARD_PV_BT878P_9B
203027. BTTV_BOARD_PV_BT878P_PLUS
203028. BTTV_BOARD_PV_M4900
203029. BTTV_BOARD_PXC200
203030. BTTV_BOARD_PXELVWPLTVPAK
203031. BTTV_BOARD_PXELVWPLTVPRO
203032. BTTV_BOARD_RV605
203033. BTTV_BOARD_SABRENT_TVFM
203034. BTTV_BOARD_SENSORAY311_611
203035. BTTV_BOARD_SIGMA_TVII_FM
203036. BTTV_BOARD_SIMUS_GVC1100
203037. BTTV_BOARD_SPIRIT_TV
203038. BTTV_BOARD_SSAI_SECURITY
203039. BTTV_BOARD_SSAI_ULTRASOUND
203040. BTTV_BOARD_STB
203041. BTTV_BOARD_STB2
203042. BTTV_BOARD_SUPER_TV
203043. BTTV_BOARD_TEKRAM_M205
203044. BTTV_BOARD_TERRATV
203045. BTTV_BOARD_TERRATVALUE
203046. BTTV_BOARD_TERRATVALUER
203047. BTTV_BOARD_TERRATVRADIO
203048. BTTV_BOARD_TEV560
203049. BTTV_BOARD_TIBET_CS16
203050. BTTV_BOARD_TURBOTV
203051. BTTV_BOARD_TVIEW_RDS_FM
203052. BTTV_BOARD_TVT_TD3116
203053. BTTV_BOARD_TWINHAN_DST
203054. BTTV_BOARD_TYPHOON_TVIEW
203055. BTTV_BOARD_TYPHOON_TVTUNERPCI
203056. BTTV_BOARD_UNKNOWN
203057. BTTV_BOARD_VD009X1_VD011_COMBI
203058. BTTV_BOARD_VD009X1_VD011_MINIDIN
203059. BTTV_BOARD_VD009_COMBI
203060. BTTV_BOARD_VD009_MINIDIN
203061. BTTV_BOARD_VD012
203062. BTTV_BOARD_VD012_X1
203063. BTTV_BOARD_VD012_X2
203064. BTTV_BOARD_VGEAR_MYVCD
203065. BTTV_BOARD_VHX
203066. BTTV_BOARD_VOBIS_BOOSTAR
203067. BTTV_BOARD_VOODOOTV_200
203068. BTTV_BOARD_VOODOOTV_FM
203069. BTTV_BOARD_WINDVR
203070. BTTV_BOARD_WINFAST2000
203071. BTTV_BOARD_WINFASTVC100
203072. BTTV_BOARD_WINVIEW_601
203073. BTTV_BOARD_XGUARD
203074. BTTV_BOARD_ZOLTRIX
203075. BTTV_BOARD_ZOLTRIX_GENIE
203076. BTTV_FREE_IDLE
203077. BTTV_MAX
203078. BTTV_MAX_FBUF
203079. BTTV_NORMS
203080. BTTV_TIMEOUT
203081. BTTV_VERSION
203082. BTT_ALIGN
203083. BTT_DEFAULT_NFREE
203084. BTT_PG_SIZE
203085. BTT_SIG
203086. BTT_SIG_LEN
203087. BTUART
203088. BTUART_BASE
203089. BTUSB_AMP
203090. BTUSB_ATH3012
203091. BTUSB_BCM2045
203092. BTUSB_BCM92035
203093. BTUSB_BCM_APPLE
203094. BTUSB_BCM_PATCHRAM
203095. BTUSB_BOOTING
203096. BTUSB_BOOTLOADER
203097. BTUSB_BROKEN_ISOC
203098. BTUSB_BULK_RUNNING
203099. BTUSB_CSR
203100. BTUSB_CW6622
203101. BTUSB_DIAG_RUNNING
203102. BTUSB_DID_ISO_RESUME
203103. BTUSB_DIGIANSWER
203104. BTUSB_DOWNLOADING
203105. BTUSB_FIRMWARE_FAILED
203106. BTUSB_FIRMWARE_LOADED
203107. BTUSB_HW_RESET_ACTIVE
203108. BTUSB_IFNUM_2
203109. BTUSB_IGNORE
203110. BTUSB_INTEL
203111. BTUSB_INTEL_BOOT
203112. BTUSB_INTEL_NEW
203113. BTUSB_INTR_RUNNING
203114. BTUSB_ISOC_RUNNING
203115. BTUSB_MARVELL
203116. BTUSB_MAX_ISOC_FRAMES
203117. BTUSB_MEDIATEK
203118. BTUSB_OOB_WAKE_ENABLED
203119. BTUSB_QCA_ROME
203120. BTUSB_REALTEK
203121. BTUSB_SNIFFER
203122. BTUSB_SUSPENDING
203123. BTUSB_SWAVE
203124. BTUSB_TX_WAIT_VND_EVT
203125. BTUSB_WAKEUP_DISABLE
203126. BTUSB_WRONG_SCO_MTU
203127. BTXCH_EMU_ENABLE
203128. BTXDATAINIT
203129. BTXDATATYPE
203130. BTXDFIRMODE
203131. BTXHTADVANCECODING
203132. BTXHTAGGREATION
203133. BTXHTBW
203134. BTXHTCRC8
203135. BTXHTLENGTH
203136. BTXHTMCSRATE
203137. BTXHTMODE
203138. BTXHTNUMBERHT_LTF
203139. BTXHTRESERVED
203140. BTXHTSHORTGI
203141. BTXHTSIG1
203142. BTXHTSIG2
203143. BTXHTSMOOTHING
203144. BTXHTSOUNDING
203145. BTXHTSTBC
203146. BTXIDCOFFSET
203147. BTXIDLEINTERVAL
203148. BTXIQDCOFFSET
203149. BTXIQIMB_A
203150. BTXIQIMB_C
203151. BTXIQIMB_D
203152. BTXIQIMB_b
203153. BTXLSIG
203154. BTXMACHEADER
203155. BTXMAC_BYTE_CNT
203156. BTXMAC_BYTE_CNT_COUNT
203157. BTXMAC_CONFIG
203158. BTXMAC_CONFIG_ENABLE
203159. BTXMAC_CONFIG_FCS_DISABLE
203160. BTXMAC_FRM_CNT
203161. BTXMAC_FRM_CNT_COUNT
203162. BTXMAC_STATUS
203163. BTXMAC_STATUS_BYTE_CNT_EXP
203164. BTXMAC_STATUS_FRAME_CNT_EXP
203165. BTXMAC_STATUS_MASK
203166. BTXMAC_STATUS_MAX_PKT_ERR
203167. BTXMAC_STATUS_UNDERRUN
203168. BTXMAC_STATUS_XMIT
203169. BTXMAC_SW_RST
203170. BTXMAC_SW_RST_RESET
203171. BTXPATH
203172. BTXPATH_A
203173. BTXPATH_B
203174. BTXPATH_C
203175. BTXPATH_D
203176. BTXPESUDO_NOISEON
203177. BTXPESUDO_NOISE_A
203178. BTXPESUDO_NOISE_B
203179. BTXPESUDO_NOISE_C
203180. BTXPESUDO_NOISE_D
203181. BTXRANDOMSEED
203182. BTX_AGCRATECCK
203183. BT_2WIRE
203184. BT_601
203185. BT_709
203186. BT_8192E_2ANT_BT_STATUS_ACL_BUSY
203187. BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY
203188. BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE
203189. BT_8192E_2ANT_BT_STATUS_INQ_PAGE
203190. BT_8192E_2ANT_BT_STATUS_MAX
203191. BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE
203192. BT_8192E_2ANT_BT_STATUS_SCO_BUSY
203193. BT_8192E_2ANT_COEX_ALGO_A2DP
203194. BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS
203195. BT_8192E_2ANT_COEX_ALGO_HID
203196. BT_8192E_2ANT_COEX_ALGO_HID_A2DP
203197. BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR
203198. BT_8192E_2ANT_COEX_ALGO_MAX
203199. BT_8192E_2ANT_COEX_ALGO_PANEDR
203200. BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP
203201. BT_8192E_2ANT_COEX_ALGO_PANEDR_HID
203202. BT_8192E_2ANT_COEX_ALGO_PANHS
203203. BT_8192E_2ANT_COEX_ALGO_SCO
203204. BT_8192E_2ANT_COEX_ALGO_SCO_PAN
203205. BT_8192E_2ANT_COEX_ALGO_UNDEFINED
203206. BT_8723B_1ANT_BT_STATUS
203207. BT_8723B_1ANT_BT_STATUS_ACL_BUSY
203208. BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY
203209. BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE
203210. BT_8723B_1ANT_BT_STATUS_INQ_PAGE
203211. BT_8723B_1ANT_BT_STATUS_MAX
203212. BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE
203213. BT_8723B_1ANT_BT_STATUS_SCO_BUSY
203214. BT_8723B_1ANT_COEX_ALGO
203215. BT_8723B_1ANT_COEX_ALGO_A2DP
203216. BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS
203217. BT_8723B_1ANT_COEX_ALGO_HID
203218. BT_8723B_1ANT_COEX_ALGO_HID_A2DP
203219. BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR
203220. BT_8723B_1ANT_COEX_ALGO_MAX
203221. BT_8723B_1ANT_COEX_ALGO_PANEDR
203222. BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP
203223. BT_8723B_1ANT_COEX_ALGO_PANEDR_HID
203224. BT_8723B_1ANT_COEX_ALGO_PANHS
203225. BT_8723B_1ANT_COEX_ALGO_SCO
203226. BT_8723B_1ANT_COEX_ALGO_UNDEFINED
203227. BT_8723B_1ANT_WIFI_NOISY_THRESH
203228. BT_8723B_1ANT_WIFI_STATUS
203229. BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY
203230. BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE
203231. BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN
203232. BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT
203233. BT_8723B_1ANT_WIFI_STATUS_MAX
203234. BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN
203235. BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE
203236. BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES
203237. BT_8723B_2ANT_BT_STATUS
203238. BT_8723B_2ANT_BT_STATUS_ACL_BUSY
203239. BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY
203240. BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE
203241. BT_8723B_2ANT_BT_STATUS_INQ_PAGE
203242. BT_8723B_2ANT_BT_STATUS_MAX
203243. BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE
203244. BT_8723B_2ANT_BT_STATUS_SCO_BUSY
203245. BT_8723B_2ANT_COEX_ALGO
203246. BT_8723B_2ANT_COEX_ALGO_A2DP
203247. BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS
203248. BT_8723B_2ANT_COEX_ALGO_HID
203249. BT_8723B_2ANT_COEX_ALGO_HID_A2DP
203250. BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR
203251. BT_8723B_2ANT_COEX_ALGO_MAX
203252. BT_8723B_2ANT_COEX_ALGO_PANEDR
203253. BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP
203254. BT_8723B_2ANT_COEX_ALGO_PANEDR_HID
203255. BT_8723B_2ANT_COEX_ALGO_PANHS
203256. BT_8723B_2ANT_COEX_ALGO_SCO
203257. BT_8723B_2ANT_COEX_ALGO_UNDEFINED
203258. BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES
203259. BT_8821A_1ANT_BT_STATUS_ACL_BUSY
203260. BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY
203261. BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE
203262. BT_8821A_1ANT_BT_STATUS_INQ_PAGE
203263. BT_8821A_1ANT_BT_STATUS_MAX
203264. BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE
203265. BT_8821A_1ANT_BT_STATUS_SCO_BUSY
203266. BT_8821A_1ANT_COEX_ALGO
203267. BT_8821A_1ANT_COEX_ALGO_A2DP
203268. BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS
203269. BT_8821A_1ANT_COEX_ALGO_HID
203270. BT_8821A_1ANT_COEX_ALGO_HID_A2DP
203271. BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR
203272. BT_8821A_1ANT_COEX_ALGO_MAX
203273. BT_8821A_1ANT_COEX_ALGO_PANEDR
203274. BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP
203275. BT_8821A_1ANT_COEX_ALGO_PANEDR_HID
203276. BT_8821A_1ANT_COEX_ALGO_PANHS
203277. BT_8821A_1ANT_COEX_ALGO_SCO
203278. BT_8821A_1ANT_COEX_ALGO_UNDEFINED
203279. BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY
203280. BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE
203281. BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN
203282. BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT
203283. BT_8821A_1ANT_WIFI_STATUS_MAX
203284. BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN
203285. BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE
203286. BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES
203287. BT_8821A_2ANT_BT_STATUS_ACL_BUSY
203288. BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY
203289. BT_8821A_2ANT_BT_STATUS_CON_IDLE
203290. BT_8821A_2ANT_BT_STATUS_IDLE
203291. BT_8821A_2ANT_BT_STATUS_MAX
203292. BT_8821A_2ANT_BT_STATUS_NON_IDLE
203293. BT_8821A_2ANT_BT_STATUS_SCO_BUSY
203294. BT_8821A_2ANT_COEX_ALGO_A2DP
203295. BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS
203296. BT_8821A_2ANT_COEX_ALGO_HID
203297. BT_8821A_2ANT_COEX_ALGO_HID_A2DP
203298. BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR
203299. BT_8821A_2ANT_COEX_ALGO_MAX
203300. BT_8821A_2ANT_COEX_ALGO_PANEDR
203301. BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP
203302. BT_8821A_2ANT_COEX_ALGO_PANEDR_HID
203303. BT_8821A_2ANT_COEX_ALGO_PANHS
203304. BT_8821A_2ANT_COEX_ALGO_SCO
203305. BT_8821A_2ANT_COEX_ALGO_UNDEFINED
203306. BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES
203307. BT_A2DP
203308. BT_ACCEL
203309. BT_AGCTABLE_OFF
203310. BT_AGCTABLE_ON
203311. BT_AGG_THRESHOLD_DEF
203312. BT_AGG_THRESHOLD_MAX
203313. BT_AGG_THRESHOLD_MIN
203314. BT_ALPINE
203315. BT_B2H_ATN
203316. BT_B2S
203317. BT_BA_SHIFT
203318. BT_BB_BACKOFF_OFF
203319. BT_BB_BACKOFF_ON
203320. BT_BMC2HOST
203321. BT_BMC_BUFFER_SIZE
203322. BT_BMC_HWRST
203323. BT_BMC_IOCTL_SMS_ATN
203324. BT_BOUND
203325. BT_BUSY
203326. BT_B_BUSY
203327. BT_CAL_DATA_SIZE
203328. BT_CAL_HDR_LEN
203329. BT_CARD_READY_IND
203330. BT_CARMINE
203331. BT_CHANNEL_POLICY
203332. BT_CHANNEL_POLICY_AMP_PREFERRED
203333. BT_CHANNEL_POLICY_BREDR_ONLY
203334. BT_CHANNEL_POLICY_BREDR_PREFERRED
203335. BT_CI_COMPLIANCE_BOTH
203336. BT_CI_COMPLIANCE_NONE
203337. BT_CI_COMPLIANCE_PRIMARY
203338. BT_CI_COMPLIANCE_SECONDARY
203339. BT_CLOSED
203340. BT_CLR
203341. BT_CLR_RD_PTR
203342. BT_CLR_WR_PTR
203343. BT_CMD_AUTO_SLEEP_MODE
203344. BT_CMD_HOST_SLEEP_CONFIG
203345. BT_CMD_HOST_SLEEP_ENABLE
203346. BT_CMD_LOAD_CONFIG_DATA
203347. BT_CMD_MODULE_CFG_REQ
203348. BT_CMD_PSCAN_WIN_REPORT_ENABLE
203349. BT_CMD_ROUTE_SCO_TO_HOST
203350. BT_CMD_SET_BDADDR
203351. BT_CMD_SYNC_SHIFT
203352. BT_COEXIST
203353. BT_COEX_ANT_TYPE_ANTDIV
203354. BT_COEX_ANT_TYPE_DETECTED
203355. BT_COEX_ANT_TYPE_PG
203356. BT_COEX_BASE_ADDRESS
203357. BT_COEX_BT
203358. BT_COEX_CFG0
203359. BT_COEX_CFG1
203360. BT_COEX_CI
203361. BT_COEX_CORUN_ENABLED
203362. BT_COEX_DISABLE
203363. BT_COEX_ENABLE
203364. BT_COEX_HIGH_BAND_RET
203365. BT_COEX_INVALID_LUT
203366. BT_COEX_LOOSE_LUT
203367. BT_COEX_MAX_LUT
203368. BT_COEX_MECH_A2DP
203369. BT_COEX_MECH_COMMON
203370. BT_COEX_MECH_FTP_A2DP
203371. BT_COEX_MECH_HID
203372. BT_COEX_MECH_HID_A2DP
203373. BT_COEX_MECH_HID_PAN
203374. BT_COEX_MECH_HID_SCO_ESCO
203375. BT_COEX_MECH_MAX
203376. BT_COEX_MECH_NONE
203377. BT_COEX_MECH_PAN
203378. BT_COEX_MECH_PAN_A2DP
203379. BT_COEX_MECH_SCO
203380. BT_COEX_MPLUT_BOOST_ENABLED
203381. BT_COEX_MPLUT_ENABLED
203382. BT_COEX_NW
203383. BT_COEX_PRIO_TBL_DISABLED
203384. BT_COEX_PRIO_TBL_EVT_DTIM
203385. BT_COEX_PRIO_TBL_EVT_INIT_CALIB1
203386. BT_COEX_PRIO_TBL_EVT_INIT_CALIB2
203387. BT_COEX_PRIO_TBL_EVT_MAX
203388. BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH1
203389. BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH2
203390. BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW1
203391. BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW2
203392. BT_COEX_PRIO_TBL_EVT_RESERVED0
203393. BT_COEX_PRIO_TBL_EVT_RESERVED1
203394. BT_COEX_PRIO_TBL_EVT_RESERVED2
203395. BT_COEX_PRIO_TBL_EVT_RESERVED3
203396. BT_COEX_PRIO_TBL_EVT_RESERVED4
203397. BT_COEX_PRIO_TBL_EVT_RESERVED5
203398. BT_COEX_PRIO_TBL_EVT_RESERVED6
203399. BT_COEX_PRIO_TBL_EVT_SCAN24
203400. BT_COEX_PRIO_TBL_EVT_SCAN52
203401. BT_COEX_PRIO_TBL_MAX
203402. BT_COEX_PRIO_TBL_PRIO_BYPASS
203403. BT_COEX_PRIO_TBL_PRIO_COEX_OFF
203404. BT_COEX_PRIO_TBL_PRIO_COEX_ON
203405. BT_COEX_PRIO_TBL_PRIO_HIGH
203406. BT_COEX_PRIO_TBL_PRIO_LOW
203407. BT_COEX_PRIO_TBL_PRIO_RSRVD1
203408. BT_COEX_PRIO_TBL_PRIO_RSRVD2
203409. BT_COEX_STATE_BT30
203410. BT_COEX_STATE_BTINFO_B_FTP_A2DP
203411. BT_COEX_STATE_BTINFO_B_HID_SCOESCO
203412. BT_COEX_STATE_BTINFO_COMMON
203413. BT_COEX_STATE_BT_CNT_LEVEL_0
203414. BT_COEX_STATE_BT_CNT_LEVEL_1
203415. BT_COEX_STATE_BT_CNT_LEVEL_2
203416. BT_COEX_STATE_BT_CNT_LEVEL_3
203417. BT_COEX_STATE_BT_DOWNLINK
203418. BT_COEX_STATE_BT_IDLE
203419. BT_COEX_STATE_BT_INQ_PAGE
203420. BT_COEX_STATE_BT_RSSI_LOW
203421. BT_COEX_STATE_BT_UPLINK
203422. BT_COEX_STATE_DEC_BT_POWER
203423. BT_COEX_STATE_HOLD_FOR_BT_OPERATION
203424. BT_COEX_STATE_PROFILE_A2DP
203425. BT_COEX_STATE_PROFILE_HID
203426. BT_COEX_STATE_PROFILE_PAN
203427. BT_COEX_STATE_PROFILE_SCO
203428. BT_COEX_STATE_WIFI_DOWNLINK
203429. BT_COEX_STATE_WIFI_HT20
203430. BT_COEX_STATE_WIFI_HT40
203431. BT_COEX_STATE_WIFI_IDLE
203432. BT_COEX_STATE_WIFI_LEGACY
203433. BT_COEX_STATE_WIFI_RSSI_1_HIGH
203434. BT_COEX_STATE_WIFI_RSSI_1_LOW
203435. BT_COEX_STATE_WIFI_RSSI_1_MEDIUM
203436. BT_COEX_STATE_WIFI_RSSI_HIGH
203437. BT_COEX_STATE_WIFI_RSSI_LOW
203438. BT_COEX_STATE_WIFI_RSSI_MEDIUM
203439. BT_COEX_STATE_WIFI_UPLINK
203440. BT_COEX_SYNC2SCO_ENABLED
203441. BT_COEX_TIGHT_LUT
203442. BT_COEX_TX_DIS_LUT
203443. BT_COEX_UPDATE_REDUCED_TXP
203444. BT_COEX_WIFI
203445. BT_CONFIG
203446. BT_CONNECT
203447. BT_CONNECT2
203448. BT_CONNECTED
203449. BT_CONTROL
203450. BT_CONTROL_BT_GRANT
203451. BT_CORAL
203452. BT_CORALP
203453. BT_CR0
203454. BT_CR0_ENABLE_IBT
203455. BT_CR0_EN_CLR_SLV_RDP
203456. BT_CR0_EN_CLR_SLV_WRP
203457. BT_CR0_IO_BASE
203458. BT_CR0_IRQ
203459. BT_CR1
203460. BT_CR1_IRQ_H2B
203461. BT_CR1_IRQ_HBUSY
203462. BT_CR2
203463. BT_CR2_IRQ_H2B
203464. BT_CR2_IRQ_HBUSY
203465. BT_CR3
203466. BT_CSR_BC4
203467. BT_CSR_BC8
203468. BT_CTL_HWPDN
203469. BT_CTRL
203470. BT_CTRL_B2H_ATN
203471. BT_CTRL_B_BUSY
203472. BT_CTRL_CLR_RD_PTR
203473. BT_CTRL_CLR_WR_PTR
203474. BT_CTRL_H2B_ATN
203475. BT_CTRL_H_BUSY
203476. BT_CTRL_OEM0
203477. BT_CTRL_SMS_ATN
203478. BT_CVSD_CLEAR
203479. BT_CVSD_INTERRUPT
203480. BT_CVSD_RX_OVERFLOW
203481. BT_CVSD_RX_READY
203482. BT_CVSD_TX_NREADY
203483. BT_CVSD_TX_UNDERFLOW
203484. BT_DBG
203485. BT_DBG_PROFILE_A2DP
203486. BT_DBG_PROFILE_HID
203487. BT_DBG_PROFILE_HID_A2DP
203488. BT_DBG_PROFILE_HID_PAN
203489. BT_DBG_PROFILE_MAX
203490. BT_DBG_PROFILE_NONE
203491. BT_DBG_PROFILE_PAN
203492. BT_DBG_PROFILE_PAN_A2DP
203493. BT_DBG_PROFILE_SCO
203494. BT_DEBUG_ENABLE
203495. BT_DEBUG_MSG
203496. BT_DEBUG_OFF
203497. BT_DEBUG_STATES
203498. BT_DEFER_SETUP
203499. BT_DELETE
203500. BT_DEVICE
203501. BT_DEVICE_WACOM
203502. BT_DISABLE_REDUCED_TXPOWER_THRESHOLD
203503. BT_DISCONN
203504. BT_DONE
203505. BT_DURATION_LIMIT_DEF
203506. BT_DURATION_LIMIT_MAX
203507. BT_DURATION_LIMIT_MIN
203508. BT_ENABLE_2_WIRE
203509. BT_ENABLE_CHANNEL_ANNOUNCE
203510. BT_ENABLE_PRIORITY
203511. BT_ENABLE_REDUCED_TXPOWER_THRESHOLD
203512. BT_EP
203513. BT_ERR
203514. BT_ERR_RATELIMITED
203515. BT_EVENT_AUTO_SLEEP_MODE
203516. BT_EVENT_HOST_SLEEP_CONFIG
203517. BT_EVENT_HOST_SLEEP_ENABLE
203518. BT_EVENT_MODULE_CFG_REQ
203519. BT_EVENT_POWER_STATE
203520. BT_FLUSHABLE
203521. BT_FLUSHABLE_OFF
203522. BT_FLUSHABLE_ON
203523. BT_FORCE_ANT_AUTO
203524. BT_FORCE_ANT_BT
203525. BT_FORCE_ANT_DIS
203526. BT_FORCE_ANT_MAX
203527. BT_FORCE_ANT_WIFI
203528. BT_FRAG_THRESHOLD_DEF
203529. BT_FRAG_THRESHOLD_MAX
203530. BT_FRAG_THRESHOLD_MIN
203531. BT_FUNC
203532. BT_FUNC_EN
203533. BT_FW_COEX_THRESH_20
203534. BT_FW_COEX_THRESH_23
203535. BT_FW_COEX_THRESH_25
203536. BT_FW_COEX_THRESH_30
203537. BT_FW_COEX_THRESH_35
203538. BT_FW_COEX_THRESH_40
203539. BT_FW_COEX_THRESH_45
203540. BT_FW_COEX_THRESH_47
203541. BT_FW_COEX_THRESH_50
203542. BT_FW_COEX_THRESH_55
203543. BT_FW_COEX_THRESH_TOL
203544. BT_FW_NAV_OFF
203545. BT_FW_NAV_ON
203546. BT_GD5480
203547. BT_GETPAGE
203548. BT_GETSEARCH
203549. BT_H2B_ATN
203550. BT_HID
203551. BT_HID_IDLE
203552. BT_HIGH_TRAFFIC
203553. BT_HWPDN_EN
203554. BT_HWPDN_SL
203555. BT_HWROF_EN
203556. BT_HWRS
203557. BT_H_BUSY
203558. BT_IDLE
203559. BT_IGNITIONPRO_ID
203560. BT_INFO
203561. BT_INFO_8192E_2ANT_B_A2DP
203562. BT_INFO_8192E_2ANT_B_ACL_BUSY
203563. BT_INFO_8192E_2ANT_B_CONNECTION
203564. BT_INFO_8192E_2ANT_B_FTP
203565. BT_INFO_8192E_2ANT_B_HID
203566. BT_INFO_8192E_2ANT_B_INQ_PAGE
203567. BT_INFO_8192E_2ANT_B_SCO_BUSY
203568. BT_INFO_8192E_2ANT_B_SCO_ESCO
203569. BT_INFO_8723B_1ANT_A2DP_BASIC_RATE
203570. BT_INFO_8723B_1ANT_B_A2DP
203571. BT_INFO_8723B_1ANT_B_ACL_BUSY
203572. BT_INFO_8723B_1ANT_B_CONNECTION
203573. BT_INFO_8723B_1ANT_B_FTP
203574. BT_INFO_8723B_1ANT_B_HID
203575. BT_INFO_8723B_1ANT_B_INQ_PAGE
203576. BT_INFO_8723B_1ANT_B_SCO_BUSY
203577. BT_INFO_8723B_1ANT_B_SCO_ESCO
203578. BT_INFO_8723B_2ANT_B_A2DP
203579. BT_INFO_8723B_2ANT_B_ACL_BUSY
203580. BT_INFO_8723B_2ANT_B_CONNECTION
203581. BT_INFO_8723B_2ANT_B_FTP
203582. BT_INFO_8723B_2ANT_B_HID
203583. BT_INFO_8723B_2ANT_B_INQ_PAGE
203584. BT_INFO_8723B_2ANT_B_SCO_BUSY
203585. BT_INFO_8723B_2ANT_B_SCO_ESCO
203586. BT_INFO_8821A_1ANT_A2DP_BASIC_RATE
203587. BT_INFO_8821A_1ANT_B_A2DP
203588. BT_INFO_8821A_1ANT_B_ACL_BUSY
203589. BT_INFO_8821A_1ANT_B_CONNECTION
203590. BT_INFO_8821A_1ANT_B_FTP
203591. BT_INFO_8821A_1ANT_B_HID
203592. BT_INFO_8821A_1ANT_B_INQ_PAGE
203593. BT_INFO_8821A_1ANT_B_SCO_BUSY
203594. BT_INFO_8821A_1ANT_B_SCO_ESCO
203595. BT_INFO_8821A_2ANT_B_A2DP
203596. BT_INFO_8821A_2ANT_B_ACL_BUSY
203597. BT_INFO_8821A_2ANT_B_CONNECTION
203598. BT_INFO_8821A_2ANT_B_FTP
203599. BT_INFO_8821A_2ANT_B_HID
203600. BT_INFO_8821A_2ANT_B_INQ_PAGE
203601. BT_INFO_8821A_2ANT_B_SCO_BUSY
203602. BT_INFO_8821A_2ANT_B_SCO_ESCO
203603. BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND
203604. BT_INFO_SRC_8192E_2ANT_BT_RSP
203605. BT_INFO_SRC_8192E_2ANT_MAX
203606. BT_INFO_SRC_8192E_2ANT_WIFI_FW
203607. BT_INFO_SRC_8723B_1ANT
203608. BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND
203609. BT_INFO_SRC_8723B_1ANT_BT_RSP
203610. BT_INFO_SRC_8723B_1ANT_MAX
203611. BT_INFO_SRC_8723B_1ANT_WIFI_FW
203612. BT_INFO_SRC_8723B_2ANT
203613. BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND
203614. BT_INFO_SRC_8723B_2ANT_BT_RSP
203615. BT_INFO_SRC_8723B_2ANT_MAX
203616. BT_INFO_SRC_8723B_2ANT_WIFI_FW
203617. BT_INFO_SRC_8723B_BT_ACTIVE_SEND
203618. BT_INFO_SRC_8723B_BT_RSP
203619. BT_INFO_SRC_8723B_WIFI_FW
203620. BT_INFO_SRC_8821A_1ANT_BT_ACTIVE_SEND
203621. BT_INFO_SRC_8821A_1ANT_BT_RSP
203622. BT_INFO_SRC_8821A_1ANT_MAX
203623. BT_INFO_SRC_8821A_1ANT_WIFI_FW
203624. BT_INFO_SRC_8821A_2ANT_BT_ACTIVE_SEND
203625. BT_INFO_SRC_8821A_2ANT_BT_RSP
203626. BT_INFO_SRC_8821A_2ANT_MAX
203627. BT_INFO_SRC_8821A_2ANT_WIFI_FW
203628. BT_INFO_STATE_ACL_ONLY_BUSY
203629. BT_INFO_STATE_ACL_SCO_BUSY
203630. BT_INFO_STATE_CONNECT_IDLE
203631. BT_INFO_STATE_DISABLED
203632. BT_INFO_STATE_HID_BUSY
203633. BT_INFO_STATE_HID_SCO_BUSY
203634. BT_INFO_STATE_INQ_OR_PAG
203635. BT_INFO_STATE_MAX
203636. BT_INFO_STATE_NO_CONNECTION
203637. BT_INFO_STATE_SCO_ONLY_BUSY
203638. BT_INSERT
203639. BT_INTERNAL
203640. BT_INTMASK
203641. BT_INTMASK_B2H_IRQ
203642. BT_INTMASK_B2H_IRQEN
203643. BT_INTMASK_BMC_HWRST
203644. BT_INTMASK_R
203645. BT_INTMASK_W
203646. BT_IO_BASE
203647. BT_IRQ
203648. BT_ISSC_3WIRE
203649. BT_IS_ROOT
203650. BT_KILLSWITCH_MASK
203651. BT_LAGUNA
203652. BT_LAGUNAB
203653. BT_LEAD_TIME_DEF
203654. BT_LEAD_TIME_MAX
203655. BT_LEAD_TIME_MIN
203656. BT_LEAF
203657. BT_LEFTMOST
203658. BT_LIME
203659. BT_LISTEN
203660. BT_LOOKUP
203661. BT_LOW_TRAFFIC
203662. BT_MARK_DIRTY
203663. BT_MASK
203664. BT_MAX_AG
203665. BT_MAX_KILL_DEF
203666. BT_MAX_KILL_MAX
203667. BT_MAX_KILL_MIN
203668. BT_MAX_PROTO
203669. BT_MBI_UNIT_AUNIT
203670. BT_MBI_UNIT_BUNIT
203671. BT_MBI_UNIT_CPU
203672. BT_MBI_UNIT_GFX
203673. BT_MBI_UNIT_PCIE
203674. BT_MBI_UNIT_PMC
203675. BT_MBI_UNIT_SATA
203676. BT_MBI_UNIT_SMC
203677. BT_MBI_UNIT_SMI
203678. BT_MBI_UNIT_USB
203679. BT_MBOX
203680. BT_MBOX_MSG
203681. BT_MBOX_PRINT
203682. BT_MINT
203683. BT_MOTOR_EXT_BE
203684. BT_MOTOR_EXT_GUB
203685. BT_MOTOR_EXT_GUL
203686. BT_MOTOR_EXT_GULB
203687. BT_MP_INFO_OP_LNA_CONSTRAINT
203688. BT_MP_INFO_OP_PATCH_VER
203689. BT_MP_INFO_OP_READ_REG
203690. BT_MP_INFO_OP_SCAN_TYPE
203691. BT_MP_INFO_OP_SUPP_FEAT
203692. BT_MP_INFO_OP_SUPP_VER
203693. BT_MP_OP_ENABLE_CFO_TRACKING
203694. BT_MP_OP_GET_AFH_MAP_H
203695. BT_MP_OP_GET_AFH_MAP_L
203696. BT_MP_OP_GET_AFH_MAP_M
203697. BT_MP_OP_GET_AFH_STATUS
203698. BT_MP_OP_GET_BD_ADDR_H
203699. BT_MP_OP_GET_BD_ADDR_L
203700. BT_MP_OP_GET_BT_STATUS
203701. BT_MP_OP_GET_BT_VERSION
203702. BT_MP_OP_GET_CFO_HDR_QUALITY_H
203703. BT_MP_OP_GET_CFO_HDR_QUALITY_L
203704. BT_MP_OP_GET_RSSI
203705. BT_MP_OP_GET_RX_ERROR_BITS_H
203706. BT_MP_OP_GET_RX_ERROR_BITS_L
203707. BT_MP_OP_GET_RX_PKT_CNT_H
203708. BT_MP_OP_GET_RX_PKT_CNT_L
203709. BT_MP_OP_GET_TARGET_BD_ADDR_H
203710. BT_MP_OP_GET_TARGET_BD_ADDR_L
203711. BT_MP_OP_READ_REG
203712. BT_MP_OP_RESET
203713. BT_MP_OP_SET_BD_ADDR_H
203714. BT_MP_OP_SET_BD_ADDR_L
203715. BT_MP_OP_SET_BT_MODE
203716. BT_MP_OP_SET_CHNL_TX_GAIN
203717. BT_MP_OP_SET_PKT_CNT_H_PKT_INTV
203718. BT_MP_OP_SET_PKT_CNT_L_PL_TYPE
203719. BT_MP_OP_SET_PKT_HEADER
203720. BT_MP_OP_SET_PKT_TYPE_LEN
203721. BT_MP_OP_SET_TARGET_BD_ADDR_H
203722. BT_MP_OP_SET_TARGET_BD_ADDR_L
203723. BT_MP_OP_SET_THERMAL_METER
203724. BT_MP_OP_SET_TRACKING_INTERVAL
203725. BT_MP_OP_SET_TX_POWER_CALIBRATION
203726. BT_MP_OP_SET_WHITENCOEFF
203727. BT_MP_OP_TEST_CTRL
203728. BT_MP_OP_WRITE_REG_ADDR
203729. BT_MP_OP_WRITE_REG_VALUE
203730. BT_NONE
203731. BT_NORMAL_RETRY_LIMIT
203732. BT_NORMAL_TIMEOUT
203733. BT_OEM0
203734. BT_OFF
203735. BT_ON
203736. BT_ON_NO_CONNECTION
203737. BT_ON_THRESHOLD_DEF
203738. BT_ON_THRESHOLD_MAX
203739. BT_ON_THRESHOLD_MIN
203740. BT_OPEN
203741. BT_OP_GET_AFH_MAP_H
203742. BT_OP_GET_AFH_MAP_L
203743. BT_OP_GET_AFH_MAP_M
203744. BT_OP_GET_BT_ANT_DET_VAL
203745. BT_OP_GET_BT_BLE_SCAN_PARA
203746. BT_OP_GET_BT_BLE_SCAN_TYPE
203747. BT_OP_GET_BT_COEX_SUPPORTED_FEATURE
203748. BT_OP_GET_BT_COEX_SUPPORTED_VERSION
203749. BT_OP_GET_BT_DEVICE_INFO
203750. BT_OP_GET_BT_FORBIDDEN_SLOT_VAL
203751. BT_OP_GET_BT_VERSION
203752. BT_OP_MAX
203753. BT_OP_PRIORITY_DETECTED
203754. BT_OP_READ_REG
203755. BT_OP_SCAN
203756. BT_OP_WRITE_REG_ADDR
203757. BT_OP_WRITE_REG_VALUE
203758. BT_OTHERBUSY
203759. BT_OTHER_ACTION
203760. BT_Operation
203761. BT_PAGE
203762. BT_PAN
203763. BT_PICASSO
203764. BT_PICASSO4
203765. BT_PICCOLO
203766. BT_PLUGGED_MASK
203767. BT_POP
203768. BT_POWER
203769. BT_POWER_FORCE_ACTIVE_OFF
203770. BT_POWER_FORCE_ACTIVE_ON
203771. BT_POWER_MASK
203772. BT_PROFILE_A2DP
203773. BT_PROFILE_HID
203774. BT_PROFILE_NONE
203775. BT_PROFILE_NOTIFICATION
203776. BT_PROFILE_PAN
203777. BT_PROFILE_SCO
203778. BT_PS_DISABLE
203779. BT_PS_ENABLE
203780. BT_PS_SLEEP
203781. BT_PTA_AVALANCHE_EVENT_ID
203782. BT_PTA_MODE_OFF
203783. BT_PTA_MODE_ON
203784. BT_PTA_PREDICTION_EVENT_ID
203785. BT_PTA_SENSE_EVENT_ID
203786. BT_PUSH
203787. BT_PUTPAGE
203788. BT_PUTSEARCH
203789. BT_QOSNULL_PG
203790. BT_QOS_NULL_PG
203791. BT_Q_PKT_OFF
203792. BT_Q_PKT_ON
203793. BT_RADIO_INDIVIDUAL
203794. BT_RADIO_SHARED
203795. BT_RANDOM
203796. BT_RCVMTU
203797. BT_REDUCED_TX_POWER_BIT
203798. BT_REGISTER_TIMEOUT
203799. BT_RESET_DELAY
203800. BT_RF_RX_LPF_CORNER_RESUME
203801. BT_RF_RX_LPF_CORNER_SHRINK
203802. BT_RIGHTMOST
203803. BT_ROOT
203804. BT_RSSI_STATE_AMDPU_OFF
203805. BT_RSSI_STATE_BG_EDCA_LOW
203806. BT_RSSI_STATE_HIGH
203807. BT_RSSI_STATE_LOW
203808. BT_RSSI_STATE_MEDIUM
203809. BT_RSSI_STATE_NORMAL_POWER
203810. BT_RSSI_STATE_SPECIAL_LOW
203811. BT_RSSI_STATE_STAY_HIGH
203812. BT_RSSI_STATE_STAY_LOW
203813. BT_RSSI_STATE_STAY_MEDIUM
203814. BT_RSSI_STATE_TXPOWER_LOW
203815. BT_RSTS
203816. BT_RTL8192E
203817. BT_RTL8723A
203818. BT_RTL8723B
203819. BT_RTL8756
203820. BT_RTL8812A
203821. BT_RTL8821A
203822. BT_RX_PKT_TYPE_OFST
203823. BT_RX_THRESHOLD
203824. BT_SCAN
203825. BT_SCO
203826. BT_SCO_BAND
203827. BT_SCO_CVSD_10
203828. BT_SCO_CVSD_120
203829. BT_SCO_CVSD_20
203830. BT_SCO_CVSD_30
203831. BT_SCO_CVSD_60
203832. BT_SCO_CVSD_90
203833. BT_SCO_CVSD_MAX
203834. BT_SCO_DIRECT_ARM2BT
203835. BT_SCO_DIRECT_BT2ARM
203836. BT_SCO_NB
203837. BT_SCO_STATE_ENDING
203838. BT_SCO_STATE_IDLE
203839. BT_SCO_STATE_LOOPBACK
203840. BT_SCO_STATE_RUNNING
203841. BT_SCO_WB
203842. BT_SD64
203843. BT_SECURITY
203844. BT_SECURITY_FIPS
203845. BT_SECURITY_HIGH
203846. BT_SECURITY_LOW
203847. BT_SECURITY_MEDIUM
203848. BT_SECURITY_SDP
203849. BT_SEQUENTIAL
203850. BT_SEQ_DONT_CARE
203851. BT_SEQ_GET_AFH_MAP_H
203852. BT_SEQ_GET_AFH_MAP_L
203853. BT_SEQ_GET_AFH_MAP_M
203854. BT_SEQ_GET_BT_ANT_DET_VAL
203855. BT_SEQ_GET_BT_BLE_SCAN_PARA
203856. BT_SEQ_GET_BT_BLE_SCAN_TYPE
203857. BT_SEQ_GET_BT_COEX_SUPPORTED_FEATURE
203858. BT_SEQ_GET_BT_COEX_SUPPORTED_VERSION
203859. BT_SEQ_GET_BT_DEVICE_INFO
203860. BT_SEQ_GET_BT_FORB_SLOT_VAL
203861. BT_SEQ_GET_BT_VERSION
203862. BT_SESSION_ACTIVITY_1_UART_MSG
203863. BT_SESSION_ACTIVITY_2_UART_MSG
203864. BT_SI_SM_RETURN
203865. BT_SKB_RESERVE
203866. BT_SK_DEFER_SETUP
203867. BT_SK_SUSPEND
203868. BT_SMS_ATN
203869. BT_SNDMTU
203870. BT_SPECTRUM
203871. BT_SPEC_1_0_b
203872. BT_SPEC_1_1
203873. BT_SPEC_1_2
203874. BT_SPEC_2_0_EDR
203875. BT_SPEC_2_1_EDR
203876. BT_SPEC_3_0_HS
203877. BT_SPEC_4_0
203878. BT_STACK
203879. BT_STACK_DUMP
203880. BT_STACK_FULL
203881. BT_STATE_CHANGE
203882. BT_STATE_CLEAR_B2H
203883. BT_STATE_IDLE
203884. BT_STATE_LONG_BUSY
203885. BT_STATE_PRINTME
203886. BT_STATE_READ_BYTES
203887. BT_STATE_READ_WAIT
203888. BT_STATE_RESET1
203889. BT_STATE_RESET2
203890. BT_STATE_RESET3
203891. BT_STATE_RESTART
203892. BT_STATE_WRITE_BYTES
203893. BT_STATE_WRITE_CONSUME
203894. BT_STATE_XACTION_START
203895. BT_STATUS
203896. BT_SUBSYS_REVISION
203897. BT_SUBSYS_VERSION
203898. BT_SWAPPED
203899. BT_TMP_BUF_SIZE
203900. BT_TXRX_CNT_LEVEL_0
203901. BT_TXRX_CNT_LEVEL_1
203902. BT_TXRX_CNT_LEVEL_2
203903. BT_TXRX_CNT_LEVEL_3
203904. BT_TXRX_CNT_THRES_1
203905. BT_TXRX_CNT_THRES_2
203906. BT_TXRX_CNT_THRES_3
203907. BT_TX_PWR_OFF
203908. BT_TX_PWR_ON
203909. BT_TX_RATE_ADAPTIVE_LOW_PENALTY
203910. BT_TX_RATE_ADAPTIVE_NORMAL
203911. BT_TX_THRESHOLD
203912. BT_TYPE
203913. BT_UART_MSG_2_FRAME1RESERVED1_MSK
203914. BT_UART_MSG_2_FRAME1RESERVED1_POS
203915. BT_UART_MSG_2_FRAME1RESERVED2_MSK
203916. BT_UART_MSG_2_FRAME1RESERVED2_POS
203917. BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_MSK
203918. BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS
203919. BT_UART_MSG_2_FRAME2RESERVED_MSK
203920. BT_UART_MSG_2_FRAME2RESERVED_POS
203921. BT_UART_MSG_2_FRAME3BRLASTTXPOWER_MSK
203922. BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS
203923. BT_UART_MSG_2_FRAME3INQPAGESRMODE_MSK
203924. BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS
203925. BT_UART_MSG_2_FRAME3LEMASTER_MSK
203926. BT_UART_MSG_2_FRAME3LEMASTER_POS
203927. BT_UART_MSG_2_FRAME3RESERVED_MSK
203928. BT_UART_MSG_2_FRAME3RESERVED_POS
203929. BT_UART_MSG_2_FRAME4LELASTTXPOWER_MSK
203930. BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS
203931. BT_UART_MSG_2_FRAME4NUMLECONN_MSK
203932. BT_UART_MSG_2_FRAME4NUMLECONN_POS
203933. BT_UART_MSG_2_FRAME4RESERVED_MSK
203934. BT_UART_MSG_2_FRAME4RESERVED_POS
203935. BT_UART_MSG_2_FRAME5BTMINRSSI_MSK
203936. BT_UART_MSG_2_FRAME5BTMINRSSI_POS
203937. BT_UART_MSG_2_FRAME5LEADVERMODE_MSK
203938. BT_UART_MSG_2_FRAME5LEADVERMODE_POS
203939. BT_UART_MSG_2_FRAME5LESCANINITMODE_MSK
203940. BT_UART_MSG_2_FRAME5LESCANINITMODE_POS
203941. BT_UART_MSG_2_FRAME5RESERVED_MSK
203942. BT_UART_MSG_2_FRAME5RESERVED_POS
203943. BT_UART_MSG_2_FRAME6LECONNINTERVAL_MSK
203944. BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS
203945. BT_UART_MSG_2_FRAME6RESERVED_MSK
203946. BT_UART_MSG_2_FRAME6RESERVED_POS
203947. BT_UART_MSG_2_FRAME6RFU_MSK
203948. BT_UART_MSG_2_FRAME6RFU_POS
203949. BT_UART_MSG_2_FRAME7LECONNSLAVELAT_MSK
203950. BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS
203951. BT_UART_MSG_2_FRAME7LEPROFILE1_MSK
203952. BT_UART_MSG_2_FRAME7LEPROFILE1_POS
203953. BT_UART_MSG_2_FRAME7LEPROFILE2_MSK
203954. BT_UART_MSG_2_FRAME7LEPROFILE2_POS
203955. BT_UART_MSG_2_FRAME7LEPROFILEOTHER_MSK
203956. BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS
203957. BT_UART_MSG_2_FRAME7RESERVED_MSK
203958. BT_UART_MSG_2_FRAME7RESERVED_POS
203959. BT_UART_MSG_FRAME1MSGTYPE_MSK
203960. BT_UART_MSG_FRAME1MSGTYPE_POS
203961. BT_UART_MSG_FRAME1RESERVED_MSK
203962. BT_UART_MSG_FRAME1RESERVED_POS
203963. BT_UART_MSG_FRAME1SSN_MSK
203964. BT_UART_MSG_FRAME1SSN_POS
203965. BT_UART_MSG_FRAME1UPDATEREQ_MSK
203966. BT_UART_MSG_FRAME1UPDATEREQ_POS
203967. BT_UART_MSG_FRAME2CHLSEQN_MSK
203968. BT_UART_MSG_FRAME2CHLSEQN_POS
203969. BT_UART_MSG_FRAME2INBAND_MSK
203970. BT_UART_MSG_FRAME2INBAND_POS
203971. BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK
203972. BT_UART_MSG_FRAME2OPENCONNECTIONS_POS
203973. BT_UART_MSG_FRAME2RESERVED_MSK
203974. BT_UART_MSG_FRAME2RESERVED_POS
203975. BT_UART_MSG_FRAME2TRAFFICLOAD_MSK
203976. BT_UART_MSG_FRAME2TRAFFICLOAD_POS
203977. BT_UART_MSG_FRAME3A2DP_MSK
203978. BT_UART_MSG_FRAME3A2DP_POS
203979. BT_UART_MSG_FRAME3ACL_MSK
203980. BT_UART_MSG_FRAME3ACL_POS
203981. BT_UART_MSG_FRAME3MASTER_MSK
203982. BT_UART_MSG_FRAME3MASTER_POS
203983. BT_UART_MSG_FRAME3OBEX_MSK
203984. BT_UART_MSG_FRAME3OBEX_POS
203985. BT_UART_MSG_FRAME3RESERVED_MSK
203986. BT_UART_MSG_FRAME3RESERVED_POS
203987. BT_UART_MSG_FRAME3SCOESCO_MSK
203988. BT_UART_MSG_FRAME3SCOESCO_POS
203989. BT_UART_MSG_FRAME3SNIFF_MSK
203990. BT_UART_MSG_FRAME3SNIFF_POS
203991. BT_UART_MSG_FRAME4IDLEDURATION_MSK
203992. BT_UART_MSG_FRAME4IDLEDURATION_POS
203993. BT_UART_MSG_FRAME4RESERVED_MSK
203994. BT_UART_MSG_FRAME4RESERVED_POS
203995. BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK
203996. BT_UART_MSG_FRAME5ESCORETRANSMIT_POS
203997. BT_UART_MSG_FRAME5RESERVED_MSK
203998. BT_UART_MSG_FRAME5RESERVED_POS
203999. BT_UART_MSG_FRAME5RXACTIVITY_MSK
204000. BT_UART_MSG_FRAME5RXACTIVITY_POS
204001. BT_UART_MSG_FRAME5TXACTIVITY_MSK
204002. BT_UART_MSG_FRAME5TXACTIVITY_POS
204003. BT_UART_MSG_FRAME6DISCOVERABLE_MSK
204004. BT_UART_MSG_FRAME6DISCOVERABLE_POS
204005. BT_UART_MSG_FRAME6RESERVED_MSK
204006. BT_UART_MSG_FRAME6RESERVED_POS
204007. BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK
204008. BT_UART_MSG_FRAME6SNIFFINTERVAL_POS
204009. BT_UART_MSG_FRAME7CONNECTABLE_MSK
204010. BT_UART_MSG_FRAME7CONNECTABLE_POS
204011. BT_UART_MSG_FRAME7INQUIRY_MSK
204012. BT_UART_MSG_FRAME7INQUIRY_POS
204013. BT_UART_MSG_FRAME7PAGE_MSK
204014. BT_UART_MSG_FRAME7PAGE_POS
204015. BT_UART_MSG_FRAME7RESERVED_MSK
204016. BT_UART_MSG_FRAME7RESERVED_POS
204017. BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK
204018. BT_UART_MSG_FRAME7SNIFFACTIVITY_POS
204019. BT_VENDOR_ID_APPLE
204020. BT_VERY_HIGH_TRAFFIC
204021. BT_VOICE
204022. BT_VOICE_CVSD_16BIT
204023. BT_VOICE_TRANSPARENT
204024. BT_WARN
204025. BT_WIFI_COEX_STATE
204026. BU21013_CALIB_REG
204027. BU21013_CLK_MODE_CALIB
204028. BU21013_CLK_MODE_DIV
204029. BU21013_CLK_MODE_EXT
204030. BU21013_CLK_MODE_REG
204031. BU21013_DELTA_0_6
204032. BU21013_DONE
204033. BU21013_DONE_REG
204034. BU21013_FILTER_EN
204035. BU21013_FILTER_REG
204036. BU21013_GAIN_0
204037. BU21013_GAIN_1
204038. BU21013_GAIN_2
204039. BU21013_GAIN_REG
204040. BU21013_IDLET_0
204041. BU21013_IDLET_1
204042. BU21013_IDLET_2
204043. BU21013_IDLET_3
204044. BU21013_IDLE_INTERMIT_EN
204045. BU21013_IDLE_REG
204046. BU21013_INT_CLR_REG
204047. BU21013_INT_MODE_EDGE
204048. BU21013_INT_MODE_LEVEL
204049. BU21013_INT_MODE_REG
204050. BU21013_NUMBER_OF_X_SENSORS
204051. BU21013_NUMBER_OF_Y_SENSORS
204052. BU21013_OFFSET_MODE_DEFAULT
204053. BU21013_OFFSET_MODE_DISABLE
204054. BU21013_OFFSET_MODE_MOVE
204055. BU21013_OFFSET_MODE_REG
204056. BU21013_POS_MODE1_0
204057. BU21013_POS_MODE1_1
204058. BU21013_POS_MODE1_2
204059. BU21013_POS_MODE1_REG
204060. BU21013_POS_MODE2_AVG1
204061. BU21013_POS_MODE2_AVG2
204062. BU21013_POS_MODE2_EN_RAW
204063. BU21013_POS_MODE2_EN_XY
204064. BU21013_POS_MODE2_MULTI
204065. BU21013_POS_MODE2_REG
204066. BU21013_POS_MODE2_ZERO
204067. BU21013_RESET_ENABLE
204068. BU21013_RESET_REG
204069. BU21013_SENSORS_BTN_0_7_REG
204070. BU21013_SENSORS_BTN_16_23_REG
204071. BU21013_SENSORS_BTN_8_15_REG
204072. BU21013_SENSORS_EN_0_7
204073. BU21013_SENSORS_EN_16_23
204074. BU21013_SENSORS_EN_8_15
204075. BU21013_SENSOR_0_7_REG
204076. BU21013_SENSOR_16_23_REG
204077. BU21013_SENSOR_8_15_REG
204078. BU21013_TH_OFF_0
204079. BU21013_TH_OFF_1
204080. BU21013_TH_OFF_2
204081. BU21013_TH_OFF_3
204082. BU21013_TH_OFF_4
204083. BU21013_TH_OFF_5
204084. BU21013_TH_OFF_6
204085. BU21013_TH_OFF_7
204086. BU21013_TH_OFF_MAX
204087. BU21013_TH_OFF_REG
204088. BU21013_TH_ON_0
204089. BU21013_TH_ON_1
204090. BU21013_TH_ON_2
204091. BU21013_TH_ON_3
204092. BU21013_TH_ON_4
204093. BU21013_TH_ON_5
204094. BU21013_TH_ON_6
204095. BU21013_TH_ON_7
204096. BU21013_TH_ON_MAX
204097. BU21013_TH_ON_REG
204098. BU21013_X1_POS_LSB_REG
204099. BU21013_X1_POS_MSB_REG
204100. BU21013_X2_POS_LSB_REG
204101. BU21013_X2_POS_MSB_REG
204102. BU21013_XY_EDGE_REG
204103. BU21013_X_EDGE_0
204104. BU21013_X_EDGE_1
204105. BU21013_X_EDGE_2
204106. BU21013_X_EDGE_3
204107. BU21013_Y1_POS_LSB_REG
204108. BU21013_Y1_POS_MSB_REG
204109. BU21013_Y2_POS_LSB_REG
204110. BU21013_Y2_POS_MSB_REG
204111. BU21013_Y_EDGE_0
204112. BU21013_Y_EDGE_1
204113. BU21013_Y_EDGE_2
204114. BU21013_Y_EDGE_3
204115. BU21023_FIRMWARE_NAME
204116. BU21023_NAME
204117. BU21029_AUTOSCAN
204118. BU21029_CFR0_REG
204119. BU21029_CFR1_REG
204120. BU21029_CFR2_REG
204121. BU21029_CFR3_REG
204122. BU21029_HWID_REG
204123. BU21029_LDO_REG
204124. BU2614_BUS_SIZE
204125. BU2614_FMES_BITS
204126. BU2614_FMES_MASK
204127. BU2614_FMES_SHIFT
204128. BU2614_FMUN_BITS
204129. BU2614_FMUN_MASK
204130. BU2614_FMUN_SHIFT
204131. BU2614_FREQ_BITS
204132. BU2614_FREQ_MASK
204133. BU2614_FREQ_SHIFT
204134. BU2614_PORT_BITS
204135. BU2614_PORT_MASK
204136. BU2614_PORT_SHIFT
204137. BU2614_STDF_BITS
204138. BU2614_STDF_MASK
204139. BU2614_STDF_SHIFT
204140. BU2614_SWAL_BITS
204141. BU2614_SWAL_MASK
204142. BU2614_SWAL_SHIFT
204143. BU2614_SWIN_BITS
204144. BU2614_SWIN_MASK
204145. BU2614_SWIN_SHIFT
204146. BU2614_TEST_BITS
204147. BU2614_TEST_MASK
204148. BU2614_TEST_SHIFT
204149. BU2614_VOID2_BITS
204150. BU2614_VOID2_MASK
204151. BU2614_VOID2_SHIFT
204152. BU2614_VOID_BITS
204153. BU2614_VOID_MASK
204154. BU2614_VOID_SHIFT
204155. BUBBLE_F
204156. BUBBLE_S
204157. BUBBLE_V
204158. BUCHCFG
204159. BUCK1
204160. BUCK1_ACTIVE_CR
204161. BUCK1_PULL_DOWN_MASK
204162. BUCK1_PULL_DOWN_REG
204163. BUCK1_RATE_MASK
204164. BUCK1_STDBY_CR
204165. BUCK2
204166. BUCK2_ACTIVE_CR
204167. BUCK2_PULL_DOWN_MASK
204168. BUCK2_PULL_DOWN_REG
204169. BUCK2_RATE_MASK
204170. BUCK2_STDBY_CR
204171. BUCK3
204172. BUCK3_ACTIVE_CR
204173. BUCK3_PULL_DOWN_MASK
204174. BUCK3_PULL_DOWN_REG
204175. BUCK3_STDBY_CR
204176. BUCK4
204177. BUCK4_ACTIVE_CR
204178. BUCK4_PULL_DOWN_MASK
204179. BUCK4_PULL_DOWN_REG
204180. BUCK4_STDBY_CR
204181. BUCK5
204182. BUCK6
204183. BUCKETS
204184. BUCKET_CAPACITY_ACCESS
204185. BUCKET_FULLNESS_ACCESS
204186. BUCKET_GC_GEN_MAX
204187. BUCKET_HASH_BITS
204188. BUCKET_MAX_SIZE
204189. BUCKET_SIZE
204190. BUCKET_SPACE
204191. BUCKS_ICCTO_CR
204192. BUCKS_ICCTO_CR_REG_MASK
204193. BUCKS_MASK_RANK_CR
204194. BUCKS_MASK_RESET_CR
204195. BUCKS_PD_CR
204196. BUCKS_PD_CR_REG_MASK
204197. BUCK_DVFS_DONE_MASK
204198. BUCK_DVFS_DONE_MASK_SFT
204199. BUCK_DVFS_DONE_SFT
204200. BUCK_ENABLE_MASK
204201. BUCK_FPWM_MASK
204202. BUCK_FPWM_SHIFT
204203. BUCK_HPLP_ENABLE_MASK
204204. BUCK_HPLP_SHIFT
204205. BUCK_ILMIN_100MA
204206. BUCK_ILMIN_150MA
204207. BUCK_ILMIN_200MA
204208. BUCK_ILMIN_250MA
204209. BUCK_ILMIN_300MA
204210. BUCK_ILMIN_350MA
204211. BUCK_ILMIN_400MA
204212. BUCK_ILMIN_50MA
204213. BUCK_ILMIN_MASK
204214. BUCK_MASK_RANK_REGISTER_MASK
204215. BUCK_MASK_RESET_REGISTER_MASK
204216. BUCK_MODE_AUTO
204217. BUCK_MODE_MANUAL
204218. BUCK_MODE_SLEEP
204219. BUCK_MODE_SYNC
204220. BUCK_RAMPRATE_10P00MV
204221. BUCK_RAMPRATE_125MV
204222. BUCK_RAMPRATE_1P25MV
204223. BUCK_RAMPRATE_250MV
204224. BUCK_RAMPRATE_2P50MV
204225. BUCK_RAMPRATE_5P00MV
204226. BUCK_RAMPRATE_MASK
204227. BUCK_RAMP_MAX
204228. BUCK_REG_MODE
204229. BUCK_REG_MODE_VBAT
204230. BUCK_REG_MODE_VSYS
204231. BUCK_SETTING
204232. BUCK_SLEEP_SETTING
204233. BUCK_TARGET_VOL_MASK
204234. BUCK_UV_ACT_DISABLE
204235. BUCK_UV_ACT_MASK
204236. BUCK_VID_MASK
204237. BUCK_VOLTAGE_MASK
204238. BUCK_VOL_CHANGE_FLAG_GO
204239. BUCK_VOL_CHANGE_FLAG_MASK
204240. BUCK_VOL_CHANGE_FLAG_TARGET
204241. BUCK_VOL_CHANGE_SHIFT
204242. BUCSR_BBFI
204243. BUCSR_BPEN
204244. BUCSR_INIT
204245. BUCSR_LS_EN
204246. BUCSR_STAC_EN
204247. BUDDHA_BASE1
204248. BUDDHA_BASE2
204249. BUDDHA_BASE3
204250. BUDDHA_CONTROL
204251. BUDDHA_IRQ
204252. BUDDHA_IRQ1
204253. BUDDHA_IRQ2
204254. BUDDHA_IRQ3
204255. BUDDHA_IRQ_MR
204256. BUDDHA_NUM_HWIFS
204257. BUDDIES_MAX
204258. BUDDY_MASK
204259. BUDDY_SHIFT
204260. BUDGET_CIN1200C
204261. BUDGET_CIN1200C_MK3
204262. BUDGET_CIN1200S
204263. BUDGET_CIN1200T
204264. BUDGET_FS_ACTIVY
204265. BUDGET_KNC1C
204266. BUDGET_KNC1CP
204267. BUDGET_KNC1CP_MK3
204268. BUDGET_KNC1C_MK3
204269. BUDGET_KNC1C_TDA10024
204270. BUDGET_KNC1S
204271. BUDGET_KNC1S2
204272. BUDGET_KNC1SP
204273. BUDGET_KNC1T
204274. BUDGET_KNC1TP
204275. BUDGET_PATCH
204276. BUDGET_TT
204277. BUDGET_TT_HW_DISEQC
204278. BUDGET_TVSTAR
204279. BUDGET_VIDEO_PORTA
204280. BUDGET_VIDEO_PORTB
204281. BUDMIN
204282. BUDSIZE
204283. BUD_ITEM
204284. BUF
204285. BUF0_LEN
204286. BUF1_LEN
204287. BUFCFG_INDATAOV_EN
204288. BUFCFG_INDATAOV_MASK
204289. BUFCFG_INDATAOV_VAL
204290. BUFCFG_OD_EN
204291. BUFCFG_OFFSET
204292. BUFCFG_OUTDATAOV_EN
204293. BUFCFG_OUTDATAOV_MASK
204294. BUFCFG_OUTDATAOV_VAL
204295. BUFCFG_OVINEN
204296. BUFCFG_OVINEN_EN
204297. BUFCFG_OVINEN_MASK
204298. BUFCFG_OVOUTEN
204299. BUFCFG_OVOUTEN_EN
204300. BUFCFG_OVOUTEN_MASK
204301. BUFCFG_PD_EN
204302. BUFCFG_PINMODE_GPIO
204303. BUFCFG_PINMODE_MASK
204304. BUFCFG_PINMODE_SHIFT
204305. BUFCFG_PUPD_VAL_20K
204306. BUFCFG_PUPD_VAL_2K
204307. BUFCFG_PUPD_VAL_50K
204308. BUFCFG_PUPD_VAL_910
204309. BUFCFG_PUPD_VAL_MASK
204310. BUFCFG_PUPD_VAL_SHIFT
204311. BUFCFG_PU_EN
204312. BUFCFG_Px_EN_MASK
204313. BUFCFG_SLEWSEL
204314. BUFDATALEN_LEN
204315. BUFDATALEN_POS
204316. BUFDESC_LCMD_LEN
204317. BUFDESC_SCMD_LEN
204318. BUFDESC_SEG_NUM
204319. BUFF0_CMAP0
204320. BUFF1_BASE
204321. BUFF1_CMAP0
204322. BUFF1_CMAP3
204323. BUFF1_SIZE
204324. BUFFER
204325. BUFFERED_FLAGS
204326. BUFFERED_FLASH_BYTE_ADDR_MASK
204327. BUFFERED_FLASH_PAGE_BITS
204328. BUFFERED_FLASH_PAGE_SIZE
204329. BUFFERED_FLASH_PHY_PAGE_SIZE
204330. BUFFERED_FLASH_TOTAL_SIZE
204331. BUFFERLISTSIZE
204332. BUFFERS_ADDR
204333. BUFFER_1_FRAME
204334. BUFFER_2_FRAME
204335. BUFFER_96_BIT
204336. BUFFER_ADDR
204337. BUFFER_ALIGN
204338. BUFFER_ALIGNMENT
204339. BUFFER_ALLOCATION
204340. BUFFER_AVAILABLE
204341. BUFFER_A_STATE
204342. BUFFER_BYTES_MAX
204343. BUFFER_BYTES_MAX_MULTICH
204344. BUFFER_B_STATE
204345. BUFFER_CHECK
204346. BUFFER_CLASS_B
204347. BUFFER_CLASS_C
204348. BUFFER_CLASS_D
204349. BUFFER_CLASS_E
204350. BUFFER_CONFIGURATION
204351. BUFFER_CONFIGURATION_EPA1024DB
204352. BUFFER_CONFIGURATION_EPA1024_EPB1024
204353. BUFFER_CONFIGURATION_EPA1024_EPB512
204354. BUFFER_CONFIGURATION_EPA512_EPB512
204355. BUFFER_CONFIG_3333
204356. BUFFER_CONFIG_4422
204357. BUFFER_CONFIG_8022
204358. BUFFER_CONFIG_FW17
204359. BUFFER_CONTROL_EPP
204360. BUFFER_CONTROL_HOST
204361. BUFFER_CONTROL_MPEGE
204362. BUFFER_CONTROL_SB2D
204363. BUFFER_CONTROL_VI
204364. BUFFER_COUNT
204365. BUFFER_CRC
204366. BUFFER_EMPTY
204367. BUFFER_END
204368. BUFFER_EXT_DFL_SIZE
204369. BUFFER_FILL_VALUE
204370. BUFFER_FLAGS_DISCARD
204371. BUFFER_FLUSH
204372. BUFFER_FNS
204373. BUFFER_FULL
204374. BUFFER_GP_RECV
204375. BUFFER_GP_XMIT
204376. BUFFER_HEADER
204377. BUFFER_ITEM_PER_CPU
204378. BUFFER_L1_NBR
204379. BUFFER_L1_SIZE
204380. BUFFER_L2_NBR
204381. BUFFER_L2_SIZE
204382. BUFFER_LENGTH
204383. BUFFER_LIMIT_FOR_32_BIT
204384. BUFFER_MAGN_LARGE
204385. BUFFER_MAGN_NBR
204386. BUFFER_MAGN_SMALL
204387. BUFFER_MAX_DELAY
204388. BUFFER_MIN_SIZE
204389. BUFFER_MODE
204390. BUFFER_MODE_INTR_DISBL
204391. BUFFER_MODE_INTR_ENBL
204392. BUFFER_MODE_MASK
204393. BUFFER_NONE
204394. BUFFER_NUM
204395. BUFFER_ORDER
204396. BUFFER_OWNED_BY_DMA
204397. BUFFER_PTR
204398. BUFFER_PTR2
204399. BUFFER_PTR_MASK
204400. BUFFER_S1_NBR
204401. BUFFER_S1_SIZE
204402. BUFFER_S2_NBR
204403. BUFFER_S2_SIZE
204404. BUFFER_SCHEME_NBR
204405. BUFFER_SCHEME_ONE
204406. BUFFER_SCHEME_TWO
204407. BUFFER_SIG
204408. BUFFER_SIZE
204409. BUFFER_SIZETWO
204410. BUFFER_SIZE_DEFAULT
204411. BUFFER_SIZE_INCREMENT
204412. BUFFER_STREAM_RESULTS
204413. BUFFER_TIMEOUT
204414. BUFFER_TRACE
204415. BUFFER_TRACE2
204416. BUFFER_VCHANS_ALL
204417. BUFFER_VCHANS_LIMITED
204418. BUFFER_WARNING_WAIT
204419. BUFFER_WATERSHED_DEFAULT
204420. BUFFSIZE
204421. BUFF_DFL
204422. BUFF_FLAGS_OFFSET
204423. BUFF_FREE
204424. BUFF_LCL
204425. BUFF_MAX
204426. BUFF_MIN
204427. BUFF_SIZE_MAX
204428. BUFF_STATUS_CELL_AV
204429. BUFF_STATUS_EMPTY
204430. BUFF_STATUS_LAST_CELL_AV
204431. BUFF_STATUS_MASK
204432. BUFF_SZ
204433. BUFF_TYPE_BDE_64
204434. BUFF_TYPE_BDE_64I
204435. BUFF_TYPE_BDE_64IP
204436. BUFF_TYPE_BDE_64P
204437. BUFF_TYPE_BDE_IMMED
204438. BUFF_TYPE_BLP_64
204439. BUFF_TYPE_BLP_64P
204440. BUFF_USB
204441. BUFF_VALID
204442. BUFINIT_START
204443. BUFLEN
204444. BUFLEN_16K
204445. BUFMAX
204446. BUFMGR_DMA_DESC_POOL_ADDR
204447. BUFMGR_DMA_DESC_POOL_SIZE
204448. BUFMGR_DMA_HIGH_WATER
204449. BUFMGR_DMA_LOW_WATER
204450. BUFMGR_HWDIAG_0
204451. BUFMGR_HWDIAG_1
204452. BUFMGR_HWDIAG_2
204453. BUFMGR_MB_ALLOC_BIT
204454. BUFMGR_MB_HIGH_WATER
204455. BUFMGR_MB_MACRX_LOW_WATER
204456. BUFMGR_MB_POOL_ADDR
204457. BUFMGR_MB_POOL_SIZE
204458. BUFMGR_MB_RDMA_LOW_WATER
204459. BUFMGR_MODE
204460. BUFMGR_MODE_ATTN_ENABLE
204461. BUFMGR_MODE_BM_TEST
204462. BUFMGR_MODE_ENABLE
204463. BUFMGR_MODE_MBLOW_ATTN_ENAB
204464. BUFMGR_MODE_NO_TX_UNDERRUN
204465. BUFMGR_MODE_RESET
204466. BUFMGR_RX_DMA_ALLOC_REQ
204467. BUFMGR_RX_DMA_ALLOC_RESP
204468. BUFMGR_RX_MB_ALLOC_REQ
204469. BUFMGR_RX_MB_ALLOC_RESP
204470. BUFMGR_STATUS
204471. BUFMGR_STATUS_ERROR
204472. BUFMGR_STATUS_MBLOW
204473. BUFMGR_TX_DMA_ALLOC_REQ
204474. BUFMGR_TX_DMA_ALLOC_RESP
204475. BUFMGR_TX_MB_ALLOC_REQ
204476. BUFMGR_TX_MB_ALLOC_RESP
204477. BUFN1_SIZE
204478. BUFN2_SIZE
204479. BUFN3_SIZE
204480. BUFN4_SIZE
204481. BUFNMB
204482. BUFNMB_MASK
204483. BUFNO_MASK
204484. BUFNO_SHIFT
204485. BUFNR
204486. BUFPOOL_DESC_SIZE
204487. BUFPOOL_MODE
204488. BUFPOOL_TIMEOUT
204489. BUFSIZE
204490. BUFSIZE_MASK
204491. BUFSIZE_SHIFT
204492. BUFSTAT_AVAILABLE
204493. BUFSTAT_INPROGRESS
204494. BUFSTAT_READY
204495. BUFSTAT_UNINITIALIZED
204496. BUFSZ
204497. BUFS_MAX
204498. BUFTBL_ENTRY_LEN
204499. BUFTBL_ENTRY_OID_LBN
204500. BUFTBL_ENTRY_OID_LEN
204501. BUFTBL_ENTRY_OID_OFST
204502. BUFTBL_ENTRY_OID_WIDTH
204503. BUFTBL_ENTRY_PGSZ_LBN
204504. BUFTBL_ENTRY_PGSZ_LEN
204505. BUFTBL_ENTRY_PGSZ_OFST
204506. BUFTBL_ENTRY_PGSZ_WIDTH
204507. BUFTBL_ENTRY_RAWADDR_HI_OFST
204508. BUFTBL_ENTRY_RAWADDR_LBN
204509. BUFTBL_ENTRY_RAWADDR_LEN
204510. BUFTBL_ENTRY_RAWADDR_LO_OFST
204511. BUFTBL_ENTRY_RAWADDR_OFST
204512. BUFTBL_ENTRY_RAWADDR_WIDTH
204513. BUF_ACC_ATYP
204514. BUF_ACC_BUSW_16
204515. BUF_ACC_BUSW_32
204516. BUF_ACC_DMAREN
204517. BUF_ACC_DMAWEN
204518. BUF_AGGR
204519. BUF_ALLOC_MAX_NUM_FRAGS
204520. BUF_AMOUNT_OFFSET
204521. BUF_AMPDU
204522. BUF_AVAIL_IRQ
204523. BUF_BUFFER_START
204524. BUF_BUF_LEN
204525. BUF_CACHE_HASH_SIZE
204526. BUF_CACHE_SIZE
204527. BUF_CFG
204528. BUF_CHAIN_SIZE
204529. BUF_CHIP_ALLOCED
204530. BUF_CHUNK_SIZE
204531. BUF_CIRC_BUFF
204532. BUF_CLR
204533. BUF_CMD_G_REVISION
204534. BUF_CMD_SIG_END
204535. BUF_CMD_S_CARRIER
204536. BUF_CMD_S_RXSENSOR
204537. BUF_CMD_S_TIMEOUT
204538. BUF_CMD_S_TXMASK
204539. BUF_CNT_INT_00
204540. BUF_CNT_INT_03
204541. BUF_CNT_INT_05
204542. BUF_CNT_INT_06
204543. BUF_CNT_INT_07
204544. BUF_CNT_INT_08
204545. BUF_CNT_INT_09
204546. BUF_CNT_INT_10
204547. BUF_CNT_INT_11
204548. BUF_CNT_INT_12
204549. BUF_CNT_INT_13
204550. BUF_CNT_INT_14
204551. BUF_CNT_INT_15
204552. BUF_CNT_INT_HSW
204553. BUF_CNT_INT_KEY
204554. BUF_CNT_INT_MDM
204555. BUF_COMMAND_HEADER
204556. BUF_COMMAND_MASK
204557. BUF_COMMAND_NULL
204558. BUF_CTRL
204559. BUF_DATA_COUNT
204560. BUF_DATA_FORMAT
204561. BUF_DATA_FORMAT_10_10_10_2
204562. BUF_DATA_FORMAT_10_11_11
204563. BUF_DATA_FORMAT_11_11_10
204564. BUF_DATA_FORMAT_16
204565. BUF_DATA_FORMAT_16_16
204566. BUF_DATA_FORMAT_16_16_16_16
204567. BUF_DATA_FORMAT_2_10_10_10
204568. BUF_DATA_FORMAT_32
204569. BUF_DATA_FORMAT_32_32
204570. BUF_DATA_FORMAT_32_32_32
204571. BUF_DATA_FORMAT_32_32_32_32
204572. BUF_DATA_FORMAT_8
204573. BUF_DATA_FORMAT_8_8
204574. BUF_DATA_FORMAT_8_8_8_8
204575. BUF_DATA_FORMAT_INVALID
204576. BUF_DATA_FORMAT_RESERVED_15
204577. BUF_DATA_OFFSET_MASK
204578. BUF_DATA_OFFSET_SHIFT
204579. BUF_DOUBLE
204580. BUF_EMPTY
204581. BUF_EVENT
204582. BUF_FMT
204583. BUF_FMT_10_10_10_2_SINT
204584. BUF_FMT_10_10_10_2_SNORM
204585. BUF_FMT_10_10_10_2_SSCALED
204586. BUF_FMT_10_10_10_2_UINT
204587. BUF_FMT_10_10_10_2_UNORM
204588. BUF_FMT_10_10_10_2_USCALED
204589. BUF_FMT_10_11_11_FLOAT
204590. BUF_FMT_10_11_11_SINT
204591. BUF_FMT_10_11_11_SNORM
204592. BUF_FMT_10_11_11_SSCALED
204593. BUF_FMT_10_11_11_UINT
204594. BUF_FMT_10_11_11_UNORM
204595. BUF_FMT_10_11_11_USCALED
204596. BUF_FMT_11_11_10_FLOAT
204597. BUF_FMT_11_11_10_SINT
204598. BUF_FMT_11_11_10_SNORM
204599. BUF_FMT_11_11_10_SSCALED
204600. BUF_FMT_11_11_10_UINT
204601. BUF_FMT_11_11_10_UNORM
204602. BUF_FMT_11_11_10_USCALED
204603. BUF_FMT_16_16_16_16_FLOAT
204604. BUF_FMT_16_16_16_16_SINT
204605. BUF_FMT_16_16_16_16_SNORM
204606. BUF_FMT_16_16_16_16_SSCALED
204607. BUF_FMT_16_16_16_16_UINT
204608. BUF_FMT_16_16_16_16_UNORM
204609. BUF_FMT_16_16_16_16_USCALED
204610. BUF_FMT_16_16_FLOAT
204611. BUF_FMT_16_16_SINT
204612. BUF_FMT_16_16_SNORM
204613. BUF_FMT_16_16_SSCALED
204614. BUF_FMT_16_16_UINT
204615. BUF_FMT_16_16_UNORM
204616. BUF_FMT_16_16_USCALED
204617. BUF_FMT_16_FLOAT
204618. BUF_FMT_16_SINT
204619. BUF_FMT_16_SNORM
204620. BUF_FMT_16_SSCALED
204621. BUF_FMT_16_UINT
204622. BUF_FMT_16_UNORM
204623. BUF_FMT_16_USCALED
204624. BUF_FMT_2_10_10_10_SINT
204625. BUF_FMT_2_10_10_10_SNORM
204626. BUF_FMT_2_10_10_10_SSCALED
204627. BUF_FMT_2_10_10_10_UINT
204628. BUF_FMT_2_10_10_10_UNORM
204629. BUF_FMT_2_10_10_10_USCALED
204630. BUF_FMT_32_32_32_32_FLOAT
204631. BUF_FMT_32_32_32_32_SINT
204632. BUF_FMT_32_32_32_32_UINT
204633. BUF_FMT_32_32_32_FLOAT
204634. BUF_FMT_32_32_32_SINT
204635. BUF_FMT_32_32_32_UINT
204636. BUF_FMT_32_32_FLOAT
204637. BUF_FMT_32_32_SINT
204638. BUF_FMT_32_32_UINT
204639. BUF_FMT_32_FLOAT
204640. BUF_FMT_32_SINT
204641. BUF_FMT_32_UINT
204642. BUF_FMT_8_8_8_8_SINT
204643. BUF_FMT_8_8_8_8_SNORM
204644. BUF_FMT_8_8_8_8_SSCALED
204645. BUF_FMT_8_8_8_8_UINT
204646. BUF_FMT_8_8_8_8_UNORM
204647. BUF_FMT_8_8_8_8_USCALED
204648. BUF_FMT_8_8_SINT
204649. BUF_FMT_8_8_SNORM
204650. BUF_FMT_8_8_SSCALED
204651. BUF_FMT_8_8_UINT
204652. BUF_FMT_8_8_UNORM
204653. BUF_FMT_8_8_USCALED
204654. BUF_FMT_8_SINT
204655. BUF_FMT_8_SNORM
204656. BUF_FMT_8_SSCALED
204657. BUF_FMT_8_UINT
204658. BUF_FMT_8_UNORM
204659. BUF_FMT_8_USCALED
204660. BUF_FMT_INVALID
204661. BUF_FMT_RESERVED_100
204662. BUF_FMT_RESERVED_101
204663. BUF_FMT_RESERVED_102
204664. BUF_FMT_RESERVED_103
204665. BUF_FMT_RESERVED_104
204666. BUF_FMT_RESERVED_105
204667. BUF_FMT_RESERVED_106
204668. BUF_FMT_RESERVED_107
204669. BUF_FMT_RESERVED_108
204670. BUF_FMT_RESERVED_109
204671. BUF_FMT_RESERVED_110
204672. BUF_FMT_RESERVED_111
204673. BUF_FMT_RESERVED_112
204674. BUF_FMT_RESERVED_113
204675. BUF_FMT_RESERVED_114
204676. BUF_FMT_RESERVED_115
204677. BUF_FMT_RESERVED_116
204678. BUF_FMT_RESERVED_117
204679. BUF_FMT_RESERVED_118
204680. BUF_FMT_RESERVED_119
204681. BUF_FMT_RESERVED_120
204682. BUF_FMT_RESERVED_121
204683. BUF_FMT_RESERVED_122
204684. BUF_FMT_RESERVED_123
204685. BUF_FMT_RESERVED_124
204686. BUF_FMT_RESERVED_125
204687. BUF_FMT_RESERVED_126
204688. BUF_FMT_RESERVED_127
204689. BUF_FMT_RESERVED_78
204690. BUF_FMT_RESERVED_79
204691. BUF_FMT_RESERVED_80
204692. BUF_FMT_RESERVED_81
204693. BUF_FMT_RESERVED_82
204694. BUF_FMT_RESERVED_83
204695. BUF_FMT_RESERVED_84
204696. BUF_FMT_RESERVED_85
204697. BUF_FMT_RESERVED_86
204698. BUF_FMT_RESERVED_87
204699. BUF_FMT_RESERVED_88
204700. BUF_FMT_RESERVED_89
204701. BUF_FMT_RESERVED_90
204702. BUF_FMT_RESERVED_91
204703. BUF_FMT_RESERVED_92
204704. BUF_FMT_RESERVED_93
204705. BUF_FMT_RESERVED_94
204706. BUF_FMT_RESERVED_95
204707. BUF_FMT_RESERVED_96
204708. BUF_FMT_RESERVED_97
204709. BUF_FMT_RESERVED_98
204710. BUF_FMT_RESERVED_99
204711. BUF_FORMAT_CSR
204712. BUF_FULL
204713. BUF_GPIO_INT_MASK
204714. BUF_HEADROOM
204715. BUF_HEAD_OFFSET
204716. BUF_HW_CMD_HEADER
204717. BUF_HW_OWNED
204718. BUF_IRQ_PEND
204719. BUF_ITEM
204720. BUF_KEY
204721. BUF_KEYS_CNT
204722. BUF_KEYS_HICNT
204723. BUF_LEN
204724. BUF_LEN_CODE_2K
204725. BUF_LEN_MASK
204726. BUF_LEN_MAX
204727. BUF_LG
204728. BUF_MASK
204729. BUF_MAX_DATA_SIZE
204730. BUF_MAX_PERCENT
204731. BUF_MAX_VAL
204732. BUF_MIN_VAL
204733. BUF_MISSED_KEYS
204734. BUF_MSU_LENGTH
204735. BUF_MSU_OFFSET
204736. BUF_NONE
204737. BUF_NOT_EMPTY
204738. BUF_NUM_FORMAT
204739. BUF_NUM_FORMAT_FLOAT
204740. BUF_NUM_FORMAT_RESERVED_6
204741. BUF_NUM_FORMAT_SINT
204742. BUF_NUM_FORMAT_SNORM
204743. BUF_NUM_FORMAT_SNORM_NZ
204744. BUF_NUM_FORMAT_SNORM_OGL
204745. BUF_NUM_FORMAT_SSCALED
204746. BUF_NUM_FORMAT_UINT
204747. BUF_NUM_FORMAT_UNORM
204748. BUF_NUM_FORMAT_UNORM_UINT
204749. BUF_NUM_FORMAT_USCALED
204750. BUF_OFFSET
204751. BUF_OFFSET_CPU
204752. BUF_OFFSET_LNC
204753. BUF_OWNED_BY_DMA
204754. BUF_PAGE_HDR_SIZE
204755. BUF_PAGE_SIZE
204756. BUF_PAR
204757. BUF_PART_FULL
204758. BUF_PENDING
204759. BUF_PREDICTION_SZ
204760. BUF_PRINT
204761. BUF_PTR
204762. BUF_PULSE_BIT
204763. BUF_REPEAT_BYTE
204764. BUF_REPEAT_MASK
204765. BUF_RESERVE_PERCENT
204766. BUF_RSP_PULSE_COUNT
204767. BUF_SAMPLE_MASK
204768. BUF_SCSI_ALLOCED
204769. BUF_SINGLE
204770. BUF_SIR_CODE_L1
204771. BUF_SIR_CODE_L2
204772. BUF_SIZE
204773. BUF_SIZE_16KiB
204774. BUF_SIZE_2KiB
204775. BUF_SIZE_4KiB
204776. BUF_SIZE_8KiB
204777. BUF_SM
204778. BUF_STATE
204779. BUF_STATE_EMPTY
204780. BUF_STATE_FULL
204781. BUF_STATE_RECEIVING
204782. BUF_STATE_SENDING
204783. BUF_SWAP_32BIT
204784. BUF_SW_OWNED
204785. BUF_SZ
204786. BUF_SZ_4K
204787. BUF_TAILROOM
204788. BUF_TAIL_OFFSET
204789. BUF_THREAD_ID_SIZE
204790. BUF_TYPE_GEM
204791. BUF_TYPE_USERPTR
204792. BUG
204793. BUG10934_RESET_INTERVAL
204794. BUG17190_INTERVAL
204795. BUGFIX
204796. BUGFLAG_DONE
204797. BUGFLAG_NO_CUT_HERE
204798. BUGFLAG_ONCE
204799. BUGFLAG_TAINT
204800. BUGFLAG_UNWINDER
204801. BUGFLAG_WARNING
204802. BUGGY_PXA2XX_UDC_USBTEST
204803. BUGLVL
204804. BUG_83C690
204805. BUG_BRK_IMM
204806. BUG_GET_TAINT
204807. BUG_H
204808. BUG_IF_WRONG_CR3
204809. BUG_INSTR
204810. BUG_INSTR_VALUE
204811. BUG_ON
204812. BUG_ON_H
204813. BUG_TABLE
204814. BUG_TRAP_TYPE_BUG
204815. BUG_TRAP_TYPE_NONE
204816. BUG_TRAP_TYPE_WARN
204817. BUID_HI
204818. BUID_LO
204819. BUILD
204820. BUILDIO
204821. BUILDIO_IOPORT
204822. BUILDIO_MEM
204823. BUILDSTRING
204824. BUILDTIME
204825. BUILDUSER
204826. BUILD_ASSERT
204827. BUILD_BUG
204828. BUILD_BUG_ON
204829. BUILD_BUG_ON_INVALID
204830. BUILD_BUG_ON_MSG
204831. BUILD_BUG_ON_NOT_POWER_OF_2
204832. BUILD_BUG_ON_ZERO
204833. BUILD_CONTROLS_SHADOW
204834. BUILD_EMBED_FIRST_CHUNK
204835. BUILD_FPR_ACCESS
204836. BUILD_HANDLER
204837. BUILD_HYDRA_CMD
204838. BUILD_ID_MD5
204839. BUILD_ID_SHA
204840. BUILD_ID_SIZE
204841. BUILD_ID_URANDOM
204842. BUILD_INTERRUPT
204843. BUILD_INTERRUPT3
204844. BUILD_IPIC_INTERNAL
204845. BUILD_KVM_GPR_ACCESSORS
204846. BUILD_LOCK_OPS
204847. BUILD_LOGIC_IO
204848. BUILD_PAGE_FIRST_CHUNK
204849. BUILD_PERCPU_HELPER
204850. BUILD_PERDEV_HELPER
204851. BUILD_PTE_RANGE_OP
204852. BUILD_RAC_CACHE_OP
204853. BUILD_RAxTID
204854. BUILD_RESP_RING_CONFIG
204855. BUILD_RING_BASE_ADDR
204856. BUILD_RING_CONFIG
204857. BUILD_ROLLBACK_PROLOGUE
204858. BUILD_SALT
204859. BUILD_SCSIID
204860. BUILD_SHOW_FUNC_FAN
204861. BUILD_SHOW_FUNC_INT
204862. BUILD_SHOW_FUNC_INT_LITE
204863. BUILD_SHOW_FUNC_STR
204864. BUILD_SINGLE_CMD_FUNC
204865. BUILD_SISL_ASTATUS_FC_PORT
204866. BUILD_SMPT
204867. BUILD_SPI_FIFO_RW
204868. BUILD_STORE_FUNC_DEG
204869. BUILD_STORE_FUNC_INT
204870. BUILD_STR
204871. BUILD_SWAP
204872. BUILD_TCL
204873. BUILD_TCL_RAW
204874. BUILD_TIMESTAMP
204875. BUILD_TRAP_HANDLER
204876. BUILD_VDSO32
204877. BUILD_VDSO32_64
204878. BUILD_VDSO64
204879. BUILD_VDSOX32
204880. BUILTIN_EXTEND_WITH_PROM
204881. BUILTIN_H
204882. BUI_ITEM
204883. BULKINEP
204884. BULK_BUFFER_SIZE
204885. BULK_BUF_SIZE
204886. BULK_FIFO_SIZE
204887. BULK_IN
204888. BULK_INDEX
204889. BULK_IN_DLY
204890. BULK_IN_DLY_MASK
204891. BULK_IN_DLY_MASK_
204892. BULK_IN_EP
204893. BULK_IN_PIPE
204894. BULK_OUT
204895. BULK_OUT_EP
204896. BULK_OUT_PIPE
204897. BULK_OUT_SIZE
204898. BULK_PRIORITY
204899. BULK_SIZE
204900. BULK_TIMEOUT
204901. BULK_URB_RX_SIZE
204902. BULK_URB_TIMEOUT
204903. BULK_URB_TX_SIZE
204904. BULLETIN_ATTEMPTS
204905. BULLETIN_CONTENT_LEGACY_SIZE
204906. BULLETIN_CONTENT_SIZE
204907. BULLETIN_CRC_SEED
204908. BUNDLEMAX
204909. BUNDLESMALL
204910. BUNDLE_A_MASK
204911. BUNDLE_B_MASK
204912. BUNDLE_ID_NONE
204913. BUNIT_REG_BISOC
204914. BUPDEQZ
204915. BUPD_CFO
204916. BUPD_CFO_OFFDATA
204917. BUPD_CLKO
204918. BUPD_CLKO_LTF
204919. BUP_ICH_SEL_150UA
204920. BUP_ICH_SEL_300UA
204921. BUP_ICH_SEL_50UA
204922. BUP_ICH_SEL_700UA
204923. BUP_VCH_RANGE
204924. BUP_VCH_SEL_2P5V
204925. BUP_VCH_SEL_2P6V
204926. BUP_VCH_SEL_2P7V
204927. BUP_VCH_SEL_2P8V
204928. BUP_VCH_SEL_2P9V
204929. BUP_VCH_SEL_3P0V
204930. BUP_VCH_SEL_3P1V
204931. BUP_VCH_SEL_3P2V
204932. BUP_VCH_SEL_3P3V
204933. BURGUNDY_HPDETECT_IMAC_LOWER
204934. BURGUNDY_HPDETECT_IMAC_SIDE
204935. BURGUNDY_HPDETECT_IMAC_UPPER
204936. BURGUNDY_HPDETECT_PMAC_BACK
204937. BURGUNDY_HP_LEFT
204938. BURGUNDY_HP_RIGHT
204939. BURGUNDY_LINEOUT_LEFT
204940. BURGUNDY_LINEOUT_RIGHT
204941. BURGUNDY_OUTPUT_INTERN
204942. BURGUNDY_OUTPUT_LEFT
204943. BURGUNDY_OUTPUT_RIGHT
204944. BURGUNDY_SWITCH_B
204945. BURGUNDY_SWITCH_W
204946. BURGUNDY_VOLUME_2B
204947. BURGUNDY_VOLUME_B
204948. BURGUNDY_VOLUME_OFFSET
204949. BURGUNDY_VOLUME_W
204950. BURN_HOSTED_FW
204951. BURST
204952. BURSTLENGTH_MASK
204953. BURSTLENGTH_SHIFT
204954. BURST_BASEFREQ_HZ
204955. BURST_CAP
204956. BURST_CAP_MASK
204957. BURST_CAP_MASK_
204958. BURST_CAP_SIZE_MASK_
204959. BURST_DATA_k
204960. BURST_DISABLE
204961. BURST_EN
204962. BURST_IO32
204963. BURST_IO8
204964. BURST_LENGTH_1
204965. BURST_LENGTH_2
204966. BURST_LENGTH_4
204967. BURST_LENGTH_8
204968. BURST_LEN_OFFSET
204969. BURST_LIMIT_MASK
204970. BURST_LP
204971. BURST_MAX_16
204972. BURST_MAX_4
204973. BURST_MAX_8
204974. BURST_MEM32
204975. BURST_MODE
204976. BURST_RADV
204977. BURST_RDTR
204978. BURST_SINGLE
204979. BURST_SIZE_NS
204980. BURST_SIZE_X2
204981. BURST_SIZE_X4
204982. BURST_SIZE_X8
204983. BURST_TO_BYTE
204984. BURST_TYPE
204985. BURST_WRITE_MAX
204986. BUS0_PLL_CON0
204987. BUS0_PLL_LOCK
204988. BUS1_DPLL_CON0
204989. BUS1_DPLL_LOCK
204990. BUSCFG_CBY
204991. BUSCFG_DR0
204992. BUSCFG_DR1
204993. BUSCFG_DT1
204994. BUSCFG_POL
204995. BUSCON1_BCGEN_RES
204996. BUSCON1_CMULT4
204997. BUSCON1_HOLDC1
204998. BUSCON1_RECOVC1
204999. BUSCON1_SETUP
205000. BUSCON1_WAITRDC2
205001. BUSCON1_WAITWRC2
205002. BUSCTLREG
205003. BUSCTL_ACK
205004. BUSCTL_ATN
205005. BUSCTL_BSY
205006. BUSCTL_DATAOUT_ENB
205007. BUSCTL_RST
205008. BUSCTL_SEL
205009. BUSDEF
205010. BUSDIV
205011. BUSERRADREG
205012. BUSERR_IRQ
205013. BUSFREE
205014. BUSID
205015. BUSID_SIZE
205016. BUSMASTER_EOL_INT
205017. BUSMASTER_EOL_INT_AK
205018. BUSMASTER_EOL_INT_EN
205019. BUSMASTER_TIMEOUT
205020. BUSMON_ACK
205021. BUSMON_ATN
205022. BUSMON_BSY
205023. BUSMON_BUS_FREE
205024. BUSMON_CD
205025. BUSMON_COMMAND
205026. BUSMON_DATA_IN
205027. BUSMON_DATA_OUT
205028. BUSMON_IO
205029. BUSMON_MESSAGE_IN
205030. BUSMON_MESSAGE_OUT
205031. BUSMON_MSG
205032. BUSMON_PHASE_MASK
205033. BUSMON_REQ
205034. BUSMON_RESELECT
205035. BUSMON_SEL
205036. BUSMON_SELECT
205037. BUSMON_STATUS
205038. BUSMS
205039. BUSON
205040. BUSOP_GET
205041. BUSOP_SET
205042. BUSPHASE_COMMAND
205043. BUSPHASE_DATA_IN
205044. BUSPHASE_DATA_OUT
205045. BUSPHASE_MESSAGE_IN
205046. BUSPHASE_MESSAGE_OUT
205047. BUSPHASE_SELECT
205048. BUSPHASE_STATUS
205049. BUSPOWER_MASK
205050. BUSRCON0
205051. BUSRCON0_AGEN_SERIAL_FLASH
205052. BUSRCON0_PORTW_8_BIT_MUX
205053. BUSSTATE_OFF
205054. BUSSTATE_ON
205055. BUSSTATE_TRISTATE
205056. BUSTEST_R
205057. BUSTEST_W
205058. BUSTYPE_CBUS
205059. BUSTYPE_CBUSII
205060. BUSTYPE_EISA
205061. BUSTYPE_FUTURE
205062. BUSTYPE_INTERN
205063. BUSTYPE_ISA
205064. BUSTYPE_MBI
205065. BUSTYPE_MBII
205066. BUSTYPE_MCA
205067. BUSTYPE_MPI
205068. BUSTYPE_MPSA
205069. BUSTYPE_NUBUS
205070. BUSTYPE_PCI
205071. BUSTYPE_PCMCIA
205072. BUSTYPE_TC
205073. BUSTYPE_VL
205074. BUSTYPE_VME
205075. BUSTYPE_XPRESS
205076. BUSUTIL
205077. BUSWAIT
205078. BUSWCON0
205079. BUSWCON0_AGEN_SERIAL_FLASH
205080. BUSWIDTH
205081. BUSY
205082. BUSY_CYCLES
205083. BUSY_EVEN
205084. BUSY_F
205085. BUSY_FID
205086. BUSY_LOOPS
205087. BUSY_MASK
205088. BUSY_MAX_RETRIES
205089. BUSY_ODD
205090. BUSY_POLL_BUDGET
205091. BUSY_READING_REG_VF_LOOP_COUNT
205092. BUSY_RELEASE_ATTEMPTS
205093. BUSY_S
205094. BUSY_SLOT
205095. BUSY_STATE
205096. BUSY_TIMEOUT
205097. BUSY_V
205098. BUSY_WAIT_US
205099. BUSY_WORKER_HASH_ORDER
205100. BUS_16
205101. BUS_16_BIT
205102. BUS_8
205103. BUS_8_BIT
205104. BUS_ACCESS_FLAG
205105. BUS_ADB
205106. BUS_ADRALN
205107. BUS_ADRERR
205108. BUS_AGP_AD_STEPPING_EN
205109. BUS_ALIGN
205110. BUS_AMIGA
205111. BUS_AND_STATUS_REG
205112. BUS_APER_REG_DIS
205113. BUS_ATARI
205114. BUS_ATTR_RO
205115. BUS_ATTR_RW
205116. BUS_ATTR_WO
205117. BUS_BLUETOOTH
205118. BUS_CEC
205119. BUS_CFG
205120. BUS_CFG_RXTXWEIGHT_1_1
205121. BUS_CFG_RXTXWEIGHT_2_1
205122. BUS_CFG_RXTXWEIGHT_3_1
205123. BUS_CFG_RXTXWEIGHT_4_1
205124. BUS_CHECK
205125. BUS_CLK_11
205126. BUS_CLK_1_5
205127. BUS_CLK_45
205128. BUS_CLK_90
205129. BUS_CLOCK
205130. BUS_CNTL
205131. BUS_CNTL1
205132. BUS_CNTL1_AGPCLK_VALID
205133. BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK
205134. BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT
205135. BUS_CNTL1__AGPCLK_VALID
205136. BUS_CNTL1__AGPCLK_VALID_MASK
205137. BUS_CNTL1__AGPCLK_VALID__SHIFT
205138. BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS
205139. BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK
205140. BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT
205141. BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS
205142. BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK
205143. BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT
205144. BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE
205145. BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK
205146. BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT
205147. BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS
205148. BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK
205149. BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT
205150. BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS
205151. BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK
205152. BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT
205153. BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK
205154. BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT
205155. BUS_CNTL1__PMI_BM_DISABLE
205156. BUS_CNTL1__PMI_BM_DISABLE_MASK
205157. BUS_CNTL1__PMI_BM_DISABLE__SHIFT
205158. BUS_CNTL1__PMI_INT_DISABLE
205159. BUS_CNTL1__PMI_INT_DISABLE_MASK
205160. BUS_CNTL1__PMI_INT_DISABLE__SHIFT
205161. BUS_CNTL1__PMI_IO_DISABLE
205162. BUS_CNTL1__PMI_IO_DISABLE_MASK
205163. BUS_CNTL1__PMI_IO_DISABLE__SHIFT
205164. BUS_CNTL1__PMI_MEM_DISABLE
205165. BUS_CNTL1__PMI_MEM_DISABLE_MASK
205166. BUS_CNTL1__PMI_MEM_DISABLE__SHIFT
205167. BUS_CNTL1__SEND_SBA_LATENCY_MASK
205168. BUS_CNTL1__SEND_SBA_LATENCY__SHIFT
205169. BUS_CNTL_IND__BIF_ERR_RTR_BKPRESSURE_EN_MASK
205170. BUS_CNTL_IND__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT
205171. BUS_CNTL_IND__BIOS_ROM_DIS_MASK
205172. BUS_CNTL_IND__BIOS_ROM_DIS__SHIFT
205173. BUS_CNTL_IND__BIOS_ROM_WRT_EN_MASK
205174. BUS_CNTL_IND__BIOS_ROM_WRT_EN__SHIFT
205175. BUS_CNTL_IND__PMI_BM_DIS_MASK
205176. BUS_CNTL_IND__PMI_BM_DIS__SHIFT
205177. BUS_CNTL_IND__PMI_INT_DIS_MASK
205178. BUS_CNTL_IND__PMI_INT_DIS__SHIFT
205179. BUS_CNTL_IND__PMI_IO_DIS_MASK
205180. BUS_CNTL_IND__PMI_IO_DIS__SHIFT
205181. BUS_CNTL_IND__PMI_MEM_DIS_MASK
205182. BUS_CNTL_IND__PMI_MEM_DIS__SHIFT
205183. BUS_CNTL_IND__RD_STALL_IO_WR_MASK
205184. BUS_CNTL_IND__RD_STALL_IO_WR__SHIFT
205185. BUS_CNTL_IND__SET_AZ_TC_MASK
205186. BUS_CNTL_IND__SET_AZ_TC__SHIFT
205187. BUS_CNTL_IND__SET_MC_TC_MASK
205188. BUS_CNTL_IND__SET_MC_TC__SHIFT
205189. BUS_CNTL_IND__VGA_MEM_COHERENCY_DIS_MASK
205190. BUS_CNTL_IND__VGA_MEM_COHERENCY_DIS__SHIFT
205191. BUS_CNTL_IND__VGA_REG_COHERENCY_DIS_MASK
205192. BUS_CNTL_IND__VGA_REG_COHERENCY_DIS__SHIFT
205193. BUS_CNTL_IND__ZERO_BE_RD_EN_MASK
205194. BUS_CNTL_IND__ZERO_BE_RD_EN__SHIFT
205195. BUS_CNTL_IND__ZERO_BE_WR_EN_MASK
205196. BUS_CNTL_IND__ZERO_BE_WR_EN__SHIFT
205197. BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK
205198. BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT
205199. BUS_CNTL__BIOS_ROM_DIS_MASK
205200. BUS_CNTL__BIOS_ROM_DIS__SHIFT
205201. BUS_CNTL__BIOS_ROM_WRT_EN_MASK
205202. BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT
205203. BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK
205204. BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__MASK
205205. BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT
205206. BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK
205207. BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__MASK
205208. BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT
205209. BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK
205210. BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__MASK
205211. BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT
205212. BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK
205213. BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__MASK
205214. BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT
205215. BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK
205216. BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__MASK
205217. BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT
205218. BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK
205219. BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT
205220. BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK
205221. BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT
205222. BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK
205223. BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT
205224. BUS_CNTL__PMI_BM_DIS_MASK
205225. BUS_CNTL__PMI_BM_DIS__SHIFT
205226. BUS_CNTL__PMI_INT_DIS_DN_MASK
205227. BUS_CNTL__PMI_INT_DIS_DN__MASK
205228. BUS_CNTL__PMI_INT_DIS_DN__SHIFT
205229. BUS_CNTL__PMI_INT_DIS_EP_MASK
205230. BUS_CNTL__PMI_INT_DIS_EP__MASK
205231. BUS_CNTL__PMI_INT_DIS_EP__SHIFT
205232. BUS_CNTL__PMI_INT_DIS_MASK
205233. BUS_CNTL__PMI_INT_DIS_SWUS_MASK
205234. BUS_CNTL__PMI_INT_DIS_SWUS__MASK
205235. BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT
205236. BUS_CNTL__PMI_INT_DIS__SHIFT
205237. BUS_CNTL__PMI_IO_DIS_MASK
205238. BUS_CNTL__PMI_IO_DIS__SHIFT
205239. BUS_CNTL__PMI_MEM_DIS_MASK
205240. BUS_CNTL__PMI_MEM_DIS__SHIFT
205241. BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK
205242. BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT
205243. BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK
205244. BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT
205245. BUS_CNTL__RD_STALL_IO_WR_MASK
205246. BUS_CNTL__RD_STALL_IO_WR__MASK
205247. BUS_CNTL__RD_STALL_IO_WR__SHIFT
205248. BUS_CNTL__SET_AZ_TC_MASK
205249. BUS_CNTL__SET_AZ_TC__MASK
205250. BUS_CNTL__SET_AZ_TC__SHIFT
205251. BUS_CNTL__SET_MC_TC_MASK
205252. BUS_CNTL__SET_MC_TC__MASK
205253. BUS_CNTL__SET_MC_TC__SHIFT
205254. BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK
205255. BUS_CNTL__UR_OVRD_FOR_ECRC_EN__MASK
205256. BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT
205257. BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK
205258. BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT
205259. BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK
205260. BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT
205261. BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK
205262. BUS_CNTL__VGA_MEM_COHERENCY_DIS__MASK
205263. BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT
205264. BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK
205265. BUS_CNTL__VGA_REG_COHERENCY_DIS__MASK
205266. BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT
205267. BUS_CNTL__ZERO_BE_RD_EN_MASK
205268. BUS_CNTL__ZERO_BE_RD_EN__MASK
205269. BUS_CNTL__ZERO_BE_RD_EN__SHIFT
205270. BUS_CNTL__ZERO_BE_WR_EN_MASK
205271. BUS_CNTL__ZERO_BE_WR_EN__MASK
205272. BUS_CNTL__ZERO_BE_WR_EN__SHIFT
205273. BUS_CONTROL
205274. BUS_CONTROL_AVAILABLE
205275. BUS_CONVERTER
205276. BUS_CTRL_ENDIAN_CONF
205277. BUS_CTRL_ENDIAN_CONF_MASK
205278. BUS_CTRL_ENDIAN_NSP_CONF
205279. BUS_DBG
205280. BUS_DBL_RESYNC
205281. BUS_DESCRIPTOR
205282. BUS_DEVICE_RESET
205283. BUS_DIS_ROM
205284. BUS_DMA
205285. BUS_DMASYNC_POSTREAD
205286. BUS_DMASYNC_POSTWRITE
205287. BUS_DMASYNC_PREREAD
205288. BUS_DMASYNC_PREWRITE
205289. BUS_DMA_ALLOCNOW
205290. BUS_DMA_LOAD_SEGS
205291. BUS_DMA_NOWAIT
205292. BUS_DMA_WAITOK
205293. BUS_EDD
205294. BUS_ERR
205295. BUS_ERROR
205296. BUS_ERROR_APERR
205297. BUS_ERROR_BADCMD
205298. BUS_ERROR_BADMA
205299. BUS_ERROR_BADMB
205300. BUS_ERROR_BADMC
205301. BUS_ERROR_BUSERR
205302. BUS_ERROR_CIQTO
205303. BUS_ERROR_CPU0PB
205304. BUS_ERROR_CPU0PS
205305. BUS_ERROR_CPU1PB
205306. BUS_ERROR_CPU1PS
205307. BUS_ERROR_CTRL_PERR
205308. BUS_ERROR_ILL
205309. BUS_ERROR_INTR
205310. BUS_ERROR_INTR_CLR
205311. BUS_ERROR_INTR_EN
205312. BUS_ERROR_INTR_MASK
205313. BUS_ERROR_JBUS_ILL_B
205314. BUS_ERROR_JBUS_ILL_C
205315. BUS_ERROR_LPQTO
205316. BUS_ERROR_RD_PERR
205317. BUS_ERROR_SFPQTO
205318. BUS_ERROR_SNOOP_ERR
205319. BUS_ERROR_SNOOP_GR
205320. BUS_ERROR_SNOOP_OWN
205321. BUS_ERROR_SNOOP_PCI
205322. BUS_ERROR_SNOOP_RD
205323. BUS_ERROR_SNOOP_RDO
205324. BUS_ERROR_SNOOP_RDS
205325. BUS_ERROR_SNOOP_RDSA
205326. BUS_ERROR_SSMDIS
205327. BUS_ERROR_TIMEOUT
205328. BUS_ERROR_UFPQTO
205329. BUS_ERROR_UNMAP
205330. BUS_ERROR_WDATA_PERR
205331. BUS_FAULT
205332. BUS_FIFO_ERR_ACK
205333. BUS_FLUSH_BUF
205334. BUS_FREE
205335. BUS_FREE_OCCUER
205336. BUS_FREE_ST
205337. BUS_FREE_TIMING
205338. BUS_GAMEPORT
205339. BUS_GSC
205340. BUS_HEADER_LEN
205341. BUS_HIL
205342. BUS_HOST
205343. BUS_HOST_ERR_ACK
205344. BUS_I2C
205345. BUS_I3C_MST_FREE
205346. BUS_I8042
205347. BUS_IDENTIFY
205348. BUS_IDLE
205349. BUS_IDLE_TIMEOUT
205350. BUS_IDLE_TIMING
205351. BUS_INACTIVE_LIMIT_TIME
205352. BUS_INTEL_ISHTP
205353. BUS_IOCTL
205354. BUS_ISA
205355. BUS_ISAPNP
205356. BUS_ISA_MEM_BASE
205357. BUS_ISA_PORT_BASE
205358. BUS_ISA_PORT_SHIFT
205359. BUS_L2P
205360. BUS_MASTER_DIS
205361. BUS_MASTER_INT
205362. BUS_MATRIX_REMAP_CONFIG
205363. BUS_MAX_ADDR
205364. BUS_MCEERR_AO
205365. BUS_MCEERR_AR
205366. BUS_MODE
205367. BUS_MODE_BO
205368. BUS_MODE_BO_BE
205369. BUS_MODE_DBO_
205370. BUS_MODE_DMA_BURST_LENGTH_1
205371. BUS_MODE_DMA_BURST_LENGTH_16
205372. BUS_MODE_DMA_BURST_LENGTH_2
205373. BUS_MODE_DMA_BURST_LENGTH_32
205374. BUS_MODE_DMA_BURST_LENGTH_4
205375. BUS_MODE_DMA_BURST_LENGTH_8
205376. BUS_MODE_DTB
205377. BUS_MODE_GBL
205378. BUS_MODE_PCI
205379. BUS_MODE_PCIX
205380. BUS_MODE_SWR_
205381. BUS_MSG
205382. BUS_MSTR_DISCONNECT_EN
205383. BUS_MSTR_RD_LINE
205384. BUS_MSTR_RD_MULT
205385. BUS_MSTR_RESET
205386. BUS_MSTR_WS
205387. BUS_MULTI
205388. BUS_NODATA
205389. BUS_NOINTR
205390. BUS_NOTIFY_ADD_DEVICE
205391. BUS_NOTIFY_BIND_DRIVER
205392. BUS_NOTIFY_BOUND_DRIVER
205393. BUS_NOTIFY_DEL_DEVICE
205394. BUS_NOTIFY_DRIVER_NOT_BOUND
205395. BUS_NOTIFY_REMOVED_DEVICE
205396. BUS_NOTIFY_UNBIND_DRIVER
205397. BUS_NOTIFY_UNBOUND_DRIVER
205398. BUS_OBJERR
205399. BUS_OFFSET
205400. BUS_PACKET
205401. BUS_PARKING_DIS
205402. BUS_PARPORT
205403. BUS_PCI
205404. BUS_PCI_READ_RETRY_EN
205405. BUS_PCI_WRT_RETRY_EN
205406. BUS_PIO
205407. BUS_PLATFORM
205408. BUS_PLL_CON0
205409. BUS_PLL_CON1
205410. BUS_PLL_FDET
205411. BUS_PLL_FREQ_DET
205412. BUS_PLL_LOCK
205413. BUS_PLL_SOURCE_SHIFT
205414. BUS_POSSESSION
205415. BUS_POWER
205416. BUS_POWER_PATH_MODE_ENA
205417. BUS_POWER_PATH_PRECHG_ENA
205418. BUS_PP_PRECHG_CURRENT_MASK
205419. BUS_PROBLEM
205420. BUS_PROTO
205421. BUS_RDY_READ_DLY
205422. BUS_RD_ABORT_EN
205423. BUS_RD_DISCARD_EN
205424. BUS_READ_BURST
205425. BUS_REGION
205426. BUS_REQUEST_MAX_NUM
205427. BUS_RESET_ASCQ
205428. BUS_RESET_SETTLE_TIME
205429. BUS_RESTRICT_CAP
205430. BUS_RESTRICT_CFG
205431. BUS_RMI
205432. BUS_ROM_WRT_EN
205433. BUS_ROOT_DEVICE
205434. BUS_ROTATION_DIS
205435. BUS_RS232
205436. BUS_SATURATION_RATIO
205437. BUS_SLOT_SZ
205438. BUS_SPACE_MAXADDR
205439. BUS_SPACE_MAXADDR_32BIT
205440. BUS_SPACE_MAXSIZE_32BIT
205441. BUS_SPACE_MEMIO
205442. BUS_SPACE_PIO
205443. BUS_SPEED
205444. BUS_SPEED_1
205445. BUS_SPEED_100
205446. BUS_SPEED_125_MHZ
205447. BUS_SPEED_133
205448. BUS_SPEED_2
205449. BUS_SPEED_25_MHZ
205450. BUS_SPEED_33
205451. BUS_SPEED_41_66_MHZ
205452. BUS_SPEED_62_5_MHZ
205453. BUS_SPEED_66
205454. BUS_SPEED_66PCIX
205455. BUS_SPEED_66UNKNOWN
205456. BUS_SPI
205457. BUS_STATUS
205458. BUS_STATUS_AVAILABLE
205459. BUS_STOP_REQ_DIS
205460. BUS_SUSPEND
205461. BUS_SZ16
205462. BUS_SZ32
205463. BUS_SZ8
205464. BUS_TIMER
205465. BUS_TRACE
205466. BUS_TYPE
205467. BUS_TYPE_PCCARD
205468. BUS_TYPE_PCI
205469. BUS_TYPE_SMI
205470. BUS_TYPE_XSMI
205471. BUS_UNKNOWN
205472. BUS_USB
205473. BUS_VECTOR_NAME_LEN
205474. BUS_VIRTUAL
205475. BUS_VSYS_VOL_SELECT_3P325V
205476. BUS_VSYS_VOL_SELECT_3P6V
205477. BUS_VSYS_VOL_SELECT_3P9V
205478. BUS_VSYS_VOL_SELECT_4P3V
205479. BUS_VSYS_VOL_SELECT_MASK
205480. BUS_WIDTH
205481. BUS_WIDTH_1
205482. BUS_WIDTH_4
205483. BUS_WIDTH_8
205484. BUS_WRT_BURST
205485. BUS_XTKBD
205486. BUSx_NR_CLK
205487. BUTTON
205488. BUTTONS_COUNT_THRESHOLD
205489. BUTTONS_POLL_INTERVAL
205490. BUTTONS_STATUS_MASK
205491. BUTTON_DELAY
205492. BUTTON_MINOR
205493. BUTTON_PRESSED
205494. BUTTON_PRESS_DETECTED
205495. BUTTON_PRESS_INTR_MASK
205496. BUTTON_TYPE1
205497. BUTTON_TYPE2
205498. BUTTON_TYPE3
205499. BUTTON_TYPE4
205500. BUTTON_TYPES
205501. BUZZER_ON
205502. BUZZ_CONTROLLER
205503. BU_EMP
205504. BV
205505. BVAL
205506. BVD1
205507. BVD2
205508. BVEC_ITER_ALL_INIT
205509. BVEC_POOL_BITS
205510. BVEC_POOL_IDX
205511. BVEC_POOL_MAX
205512. BVEC_POOL_NR
205513. BVEC_POOL_OFFSET
205514. BVME6000_BOOTI_VERSION
205515. BVME_ABORT_STATUS
205516. BVME_ACR_A16VBA
205517. BVME_ACR_A24LBA
205518. BVME_ACR_A24MSK
205519. BVME_ACR_A24VBA
205520. BVME_ACR_A32LBA
205521. BVME_ACR_A32MSK
205522. BVME_ACR_A32VBA
205523. BVME_ACR_ADDRCTL
205524. BVME_CONFIG_REG
205525. BVME_CONFIG_SW1
205526. BVME_CONFIG_SW2
205527. BVME_CONFIG_SW3
205528. BVME_CONFIG_SW4
205529. BVME_ETHERR
205530. BVME_ETHIRQ_REG
205531. BVME_I596_BASE
205532. BVME_IRQ_ABORT
205533. BVME_IRQ_I596
205534. BVME_IRQ_PRN
205535. BVME_IRQ_RTC
205536. BVME_IRQ_SCCA_RX
205537. BVME_IRQ_SCCA_SPCOND
205538. BVME_IRQ_SCCA_STAT
205539. BVME_IRQ_SCCA_TX
205540. BVME_IRQ_SCCB_RX
205541. BVME_IRQ_SCCB_SPCOND
205542. BVME_IRQ_SCCB_STAT
205543. BVME_IRQ_SCCB_TX
205544. BVME_IRQ_SCC_BASE
205545. BVME_IRQ_SCSI
205546. BVME_IRQ_TIMER
205547. BVME_IRQ_TYPE_PRIO
205548. BVME_LOCAL_IRQ_STAT
205549. BVME_NCR53C710_BASE
205550. BVME_PIT_BASE
205551. BVME_RTC_BASE
205552. BVME_SCC_A_ADDR
205553. BVME_SCC_B_ADDR
205554. BVME_SCC_RTxC
205555. BV_DETECT_BAD0
205556. BV_DETECT_BAD1
205557. BV_DETECT_GOOD
205558. BV_DETECT_MASK
205559. BV_DETECT_WARN
205560. BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED
205561. BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED
205562. BV_GPMI_CTRL0_ADDRESS__NAND_ALE
205563. BV_GPMI_CTRL0_ADDRESS__NAND_CLE
205564. BV_GPMI_CTRL0_ADDRESS__NAND_DATA
205565. BV_GPMI_CTRL0_COMMAND_MODE__READ
205566. BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE
205567. BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY
205568. BV_GPMI_CTRL0_COMMAND_MODE__WRITE
205569. BV_GPMI_CTRL0_WORD_LENGTH__16_BIT
205570. BV_GPMI_CTRL0_WORD_LENGTH__8_BIT
205571. BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH
205572. BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW
205573. BV_GPMI_CTRL1_DEV_RESET__DISABLED
205574. BV_GPMI_CTRL1_DEV_RESET__ENABLED
205575. BV_GPMI_CTRL1_GPMI_MODE__ATA
205576. BV_GPMI_CTRL1_GPMI_MODE__NAND
205577. BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS
205578. BV_GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS
205579. BV_GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS
205580. BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY
205581. BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY
205582. BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
205583. BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE
205584. BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE
205585. BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE
205586. BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE
205587. BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0
205588. BV_KALINDI_A2
205589. BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__0
205590. BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__1
205591. BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__0
205592. BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__1
205593. BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__0
205594. BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__1
205595. BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__0
205596. BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__1
205597. BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__2
205598. BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__3
205599. BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__0
205600. BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__1
205601. BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__2
205602. BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__3
205603. BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__0
205604. BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__1
205605. BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__0
205606. BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__1
205607. BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__0
205608. BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__1
205609. BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__2
205610. BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__3
205611. BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__0
205612. BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__1
205613. BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__2
205614. BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__3
205615. BV_PXP_ALPHA_B_CTRL_1_ROP__MASKAS
205616. BV_PXP_ALPHA_B_CTRL_1_ROP__MASKASNOT
205617. BV_PXP_ALPHA_B_CTRL_1_ROP__MASKNOTAS
205618. BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEAS
205619. BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEASNOT
205620. BV_PXP_ALPHA_B_CTRL_1_ROP__MERGENOTAS
205621. BV_PXP_ALPHA_B_CTRL_1_ROP__NOT
205622. BV_PXP_ALPHA_B_CTRL_1_ROP__NOTCOPYAS
205623. BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMASKAS
205624. BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMERGEAS
205625. BV_PXP_ALPHA_B_CTRL_1_ROP__NOTXORAS
205626. BV_PXP_ALPHA_B_CTRL_1_ROP__XORAS
205627. BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__0
205628. BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__1
205629. BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__0
205630. BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__1
205631. BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__0
205632. BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__1
205633. BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__0
205634. BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__1
205635. BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__2
205636. BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__3
205637. BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__0
205638. BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__1
205639. BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__2
205640. BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__3
205641. BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__0
205642. BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__1
205643. BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__0
205644. BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__1
205645. BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__0
205646. BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__1
205647. BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__2
205648. BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__3
205649. BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__0
205650. BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__1
205651. BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__2
205652. BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__3
205653. BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded
205654. BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply
205655. BV_PXP_AS_CTRL_ALPHA_CTRL__Override
205656. BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs
205657. BV_PXP_AS_CTRL_FORMAT__ARGB1555
205658. BV_PXP_AS_CTRL_FORMAT__ARGB4444
205659. BV_PXP_AS_CTRL_FORMAT__ARGB8888
205660. BV_PXP_AS_CTRL_FORMAT__RGB444
205661. BV_PXP_AS_CTRL_FORMAT__RGB555
205662. BV_PXP_AS_CTRL_FORMAT__RGB565
205663. BV_PXP_AS_CTRL_FORMAT__RGB888
205664. BV_PXP_AS_CTRL_FORMAT__RGBA8888
205665. BV_PXP_AS_CTRL_ROP__MASKAS
205666. BV_PXP_AS_CTRL_ROP__MASKASNOT
205667. BV_PXP_AS_CTRL_ROP__MASKNOTAS
205668. BV_PXP_AS_CTRL_ROP__MERGEAS
205669. BV_PXP_AS_CTRL_ROP__MERGEASNOT
205670. BV_PXP_AS_CTRL_ROP__MERGENOTAS
205671. BV_PXP_AS_CTRL_ROP__NOT
205672. BV_PXP_AS_CTRL_ROP__NOTCOPYAS
205673. BV_PXP_AS_CTRL_ROP__NOTMASKAS
205674. BV_PXP_AS_CTRL_ROP__NOTMERGEAS
205675. BV_PXP_AS_CTRL_ROP__NOTXORAS
205676. BV_PXP_AS_CTRL_ROP__XORAS
205677. BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr
205678. BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV
205679. BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB
205680. BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB
205681. BV_PXP_CTRL2_BLOCK_SIZE__16X16
205682. BV_PXP_CTRL2_BLOCK_SIZE__8X8
205683. BV_PXP_CTRL2_ROTATE0__ROT_0
205684. BV_PXP_CTRL2_ROTATE0__ROT_180
205685. BV_PXP_CTRL2_ROTATE0__ROT_270
205686. BV_PXP_CTRL2_ROTATE0__ROT_90
205687. BV_PXP_CTRL2_ROTATE1__ROT_0
205688. BV_PXP_CTRL2_ROTATE1__ROT_180
205689. BV_PXP_CTRL2_ROTATE1__ROT_270
205690. BV_PXP_CTRL2_ROTATE1__ROT_90
205691. BV_PXP_CTRL_BLOCK_SIZE__16X16
205692. BV_PXP_CTRL_BLOCK_SIZE__8X8
205693. BV_PXP_CTRL_ROTATE0__ROT_0
205694. BV_PXP_CTRL_ROTATE0__ROT_180
205695. BV_PXP_CTRL_ROTATE0__ROT_270
205696. BV_PXP_CTRL_ROTATE0__ROT_90
205697. BV_PXP_CTRL_ROTATE1__ROT_0
205698. BV_PXP_CTRL_ROTATE1__ROT_180
205699. BV_PXP_CTRL_ROTATE1__ROT_270
205700. BV_PXP_CTRL_ROTATE1__ROT_90
205701. BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__0
205702. BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__1
205703. BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__2
205704. BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__3
205705. BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__0
205706. BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__1
205707. BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__2
205708. BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__3
205709. BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__0
205710. BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__1
205711. BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__2
205712. BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__3
205713. BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__0
205714. BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__1
205715. BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__2
205716. BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__3
205717. BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__0
205718. BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__1
205719. BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__2
205720. BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__3
205721. BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__0
205722. BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__1
205723. BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__2
205724. BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__3
205725. BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__0
205726. BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__1
205727. BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__2
205728. BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__3
205729. BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__0
205730. BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__1
205731. BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__2
205732. BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__3
205733. BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__0
205734. BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__1
205735. BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__2
205736. BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__3
205737. BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__0
205738. BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__1
205739. BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__2
205740. BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__3
205741. BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__0
205742. BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__1
205743. BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__2
205744. BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__3
205745. BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__0
205746. BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__1
205747. BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__2
205748. BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__3
205749. BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__0
205750. BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__1
205751. BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__2
205752. BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__3
205753. BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__0
205754. BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__1
205755. BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__2
205756. BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__3
205757. BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__0
205758. BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__1
205759. BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__2
205760. BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__3
205761. BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__0
205762. BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__1
205763. BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__2
205764. BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__3
205765. BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__0
205766. BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__1
205767. BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__2
205768. BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__3
205769. BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__0
205770. BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__1
205771. BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__2
205772. BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__3
205773. BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT
205774. BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT
205775. BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT
205776. BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT
205777. BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE
205778. BV_PXP_DEBUGCTRL_SELECT__ASBUF
205779. BV_PXP_DEBUGCTRL_SELECT__CTRL
205780. BV_PXP_DEBUGCTRL_SELECT__LUT_HIT
205781. BV_PXP_DEBUGCTRL_SELECT__LUT_LAT
205782. BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT
205783. BV_PXP_DEBUGCTRL_SELECT__LUT_MISS
205784. BV_PXP_DEBUGCTRL_SELECT__LUT_STAT
205785. BV_PXP_DEBUGCTRL_SELECT__NONE
205786. BV_PXP_DEBUGCTRL_SELECT__OUTBUF0
205787. BV_PXP_DEBUGCTRL_SELECT__OUTBUF1
205788. BV_PXP_DEBUGCTRL_SELECT__OUTBUF2
205789. BV_PXP_DEBUGCTRL_SELECT__PSBAX
205790. BV_PXP_DEBUGCTRL_SELECT__PSBAY
205791. BV_PXP_DEBUGCTRL_SELECT__PSBUF
205792. BV_PXP_DEBUGCTRL_SELECT__ROTATION
205793. BV_PXP_INIT_MEM_CTRL_SELECT__ALU_A
205794. BV_PXP_INIT_MEM_CTRL_SELECT__ALU_B
205795. BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR0
205796. BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR1
205797. BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_LUT
205798. BV_PXP_INIT_MEM_CTRL_SELECT__DITHER1_LUT
205799. BV_PXP_INIT_MEM_CTRL_SELECT__DITHER2_LUT
205800. BV_PXP_INIT_MEM_CTRL_SELECT__RESERVED
205801. BV_PXP_INIT_MEM_CTRL_SELECT__WFE_A_FETCH
205802. BV_PXP_INIT_MEM_CTRL_SELECT__WFE_B_FETCH
205803. BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565
205804. BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444
205805. BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454
205806. BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8
205807. BV_PXP_LUT_CTRL_OUT_MODE__RESERVED
205808. BV_PXP_LUT_CTRL_OUT_MODE__RGB888
205809. BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA
205810. BV_PXP_LUT_CTRL_OUT_MODE__Y8
205811. BV_PXP_OUT_CTRL_FORMAT__ARGB1555
205812. BV_PXP_OUT_CTRL_FORMAT__ARGB4444
205813. BV_PXP_OUT_CTRL_FORMAT__ARGB8888
205814. BV_PXP_OUT_CTRL_FORMAT__RGB444
205815. BV_PXP_OUT_CTRL_FORMAT__RGB555
205816. BV_PXP_OUT_CTRL_FORMAT__RGB565
205817. BV_PXP_OUT_CTRL_FORMAT__RGB888
205818. BV_PXP_OUT_CTRL_FORMAT__RGB888P
205819. BV_PXP_OUT_CTRL_FORMAT__UYVY1P422
205820. BV_PXP_OUT_CTRL_FORMAT__VYUY1P422
205821. BV_PXP_OUT_CTRL_FORMAT__Y4
205822. BV_PXP_OUT_CTRL_FORMAT__Y8
205823. BV_PXP_OUT_CTRL_FORMAT__YUV1P444
205824. BV_PXP_OUT_CTRL_FORMAT__YUV2P420
205825. BV_PXP_OUT_CTRL_FORMAT__YUV2P422
205826. BV_PXP_OUT_CTRL_FORMAT__YVU2P420
205827. BV_PXP_OUT_CTRL_FORMAT__YVU2P422
205828. BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0
205829. BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1
205830. BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED
205831. BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE
205832. BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__DS
205833. BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__LS
205834. BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__NONE
205835. BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__SD
205836. BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__DS
205837. BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__LS
205838. BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__NONE
205839. BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__SD
205840. BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__DS
205841. BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__LS
205842. BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__NONE
205843. BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__SD
205844. BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__DS
205845. BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__LS
205846. BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__NONE
205847. BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__SD
205848. BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__DS
205849. BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__LS
205850. BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__NONE
205851. BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__SD
205852. BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__DS
205853. BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__LS
205854. BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__NONE
205855. BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__SD
205856. BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__DS
205857. BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__LS
205858. BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__NONE
205859. BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__SD
205860. BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__DS
205861. BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__LS
205862. BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__NONE
205863. BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__SD
205864. BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__DS
205865. BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__LS
205866. BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__NONE
205867. BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__SD
205868. BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__DS
205869. BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__LS
205870. BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__NONE
205871. BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__SD
205872. BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__DS
205873. BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__LS
205874. BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__NONE
205875. BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__SD
205876. BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__DS
205877. BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__LS
205878. BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__NONE
205879. BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__SD
205880. BV_PXP_PS_CTRL_DECX__DECX2
205881. BV_PXP_PS_CTRL_DECX__DECX4
205882. BV_PXP_PS_CTRL_DECX__DECX8
205883. BV_PXP_PS_CTRL_DECX__DISABLE
205884. BV_PXP_PS_CTRL_DECY__DECY2
205885. BV_PXP_PS_CTRL_DECY__DECY4
205886. BV_PXP_PS_CTRL_DECY__DECY8
205887. BV_PXP_PS_CTRL_DECY__DISABLE
205888. BV_PXP_PS_CTRL_FORMAT__RGB444
205889. BV_PXP_PS_CTRL_FORMAT__RGB555
205890. BV_PXP_PS_CTRL_FORMAT__RGB565
205891. BV_PXP_PS_CTRL_FORMAT__RGB888
205892. BV_PXP_PS_CTRL_FORMAT__UYVY1P422
205893. BV_PXP_PS_CTRL_FORMAT__VYUY1P422
205894. BV_PXP_PS_CTRL_FORMAT__Y4
205895. BV_PXP_PS_CTRL_FORMAT__Y8
205896. BV_PXP_PS_CTRL_FORMAT__YUV1P444
205897. BV_PXP_PS_CTRL_FORMAT__YUV2P420
205898. BV_PXP_PS_CTRL_FORMAT__YUV2P422
205899. BV_PXP_PS_CTRL_FORMAT__YUV420
205900. BV_PXP_PS_CTRL_FORMAT__YUV422
205901. BV_PXP_PS_CTRL_FORMAT__YVU2P420
205902. BV_PXP_PS_CTRL_FORMAT__YVU2P422
205903. BV_SSP_CTRL1_SSP_MODE__MS
205904. BV_SSP_CTRL1_SSP_MODE__SD_MMC
205905. BV_SSP_CTRL1_SSP_MODE__SPI
205906. BV_SSP_CTRL1_SSP_MODE__SSI
205907. BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS
205908. BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS
205909. BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS
205910. BV_TIMROT_VERSION_1
205911. BV_TIMROT_VERSION_2
205912. BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL
205913. BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL
205914. BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS
205915. BW
205916. BW16
205917. BW20
205918. BW2VBPS
205919. BW2_FLAG_BLANKED
205920. BW40MINUS
205921. BW40PLUS
205922. BW5
205923. BW6
205924. BWCTRL
205925. BWCTRL_MASK
205926. BWC_LOSSLESS
205927. BWC_Q_HIGH
205928. BWC_Q_MED
205929. BWF
205930. BWF_EN
205931. BWINDOW_L
205932. BWIN_ENH_L
205933. BWIN_INDEX_BITS
205934. BWIN_SIZE
205935. BWIN_SIZEMASK
205936. BWIN_SIZE_BITS
205937. BWIN_WIDGETADDR
205938. BWIN_WIDGET_MASK
205939. BWIN_WINDOWNUM
205940. BWMapping_8723B
205941. BWOPMODE
205942. BWORD
205943. BWORD0
205944. BWORD1
205945. BWR_EN
205946. BWTWO_CTL_DIVISOR_MASK
205947. BWTWO_CTL_ENABLE_CURCMP
205948. BWTWO_CTL_ENABLE_INTS
205949. BWTWO_CTL_ENABLE_TIMING
205950. BWTWO_CTL_ENABLE_VIDEO
205951. BWTWO_CTL_XTAL_MASK
205952. BWTWO_REGISTER_OFFSET
205953. BWTWO_SR_1152_900_76_A
205954. BWTWO_SR_1152_900_76_B
205955. BWTWO_SR_1600_1280
205956. BWTWO_SR_ID_MASK
205957. BWTWO_SR_ID_MONO
205958. BWTWO_SR_ID_MONO_ECL
205959. BWTWO_SR_ID_MSYNC
205960. BWTWO_SR_ID_NOCONN
205961. BWTWO_SR_RES_MASK
205962. BWTWO_STAT_ID_MASK
205963. BWTWO_STAT_MSENSE_MASK
205964. BWTWO_STAT_PENDING_INT
205965. BW_10
205966. BW_1_5_MHZ
205967. BW_20
205968. BW_20MHZ
205969. BW_2_MHZ
205970. BW_40
205971. BW_40MHZ
205972. BW_5_MHZ
205973. BW_6_MHZ
205974. BW_7_MHZ
205975. BW_80
205976. BW_8_MHZ
205977. BW_AUTO_SWITCH_HIGH_LOW
205978. BW_AUTO_SWITCH_LOW_HIGH
205979. BW_CALCS_VERSION_CARRIZO
205980. BW_CALCS_VERSION_INVALID
205981. BW_CALCS_VERSION_POLARIS10
205982. BW_CALCS_VERSION_POLARIS11
205983. BW_CALCS_VERSION_POLARIS12
205984. BW_CALCS_VERSION_STONEY
205985. BW_CALCS_VERSION_VEGA10
205986. BW_CALCS_VERSION_VEGAM
205987. BW_CID
205988. BW_CTRL
205989. BW_CTRL_COARSE__gi_coarse_exp_MASK
205990. BW_CTRL_COARSE__gi_coarse_exp__SHIFT
205991. BW_CTRL_COARSE__gi_coarse_mant_MASK
205992. BW_CTRL_COARSE__gi_coarse_mant__SHIFT
205993. BW_CTRL_COARSE__gp_coarse_exp_MASK
205994. BW_CTRL_COARSE__gp_coarse_exp__SHIFT
205995. BW_CTRL_COARSE__gp_coarse_mant_MASK
205996. BW_CTRL_COARSE__gp_coarse_mant__SHIFT
205997. BW_CTRL_COARSE__nctl_coarse_frac_res_MASK
205998. BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT
205999. BW_CTRL_COARSE__nctl_coarse_res_MASK
206000. BW_CTRL_COARSE__nctl_coarse_res__SHIFT
206001. BW_CTRL_FINE__dpll_cfg_3_MASK
206002. BW_CTRL_FINE__dpll_cfg_3__SHIFT
206003. BW_CTRL_USER_TIMER
206004. BW_DBUS_CTRL
206005. BW_DBUS_DATA
206006. BW_DCC_0_125_PERCENT
206007. BW_DCC_0_25_PERCENT
206008. BW_DCC_0_5_PERCENT
206009. BW_DCC_16_PERCENT
206010. BW_DCC_1_PERCENT
206011. BW_DCC_2_PERCENT
206012. BW_DCC_4_PERCENT
206013. BW_DCC_8_PERCENT
206014. BW_FIXED_BITS_PER_FRACTIONAL_PART
206015. BW_FIXED_GET_INTEGER_PART
206016. BW_FIXED_H_
206017. BW_FIXED_MAX_I32
206018. BW_FIXED_MIN_I32
206019. BW_FM_RADIO
206020. BW_HOST_DELAY
206021. BW_HUB_LS_SETUP
206022. BW_IND_BIAS
206023. BW_INTR_TABLE
206024. BW_INTR_TABLE_CLEAR
206025. BW_ISDBT_13SEG
206026. BW_ISDBT_1SEG
206027. BW_ISDBT_3SEG
206028. BW_LOCAL_BASE
206029. BW_MANT_16
206030. BW_MANT_20
206031. BW_MANT_24
206032. BW_OPMODE
206033. BW_OPMODE_11J
206034. BW_OPMODE_20MHZ
206035. BW_OPMODE_5G
206036. BW_PERCENT
206037. BW_PRESCALER
206038. BW_PTIMER_COUNTER
206039. BW_PTIMER_COUNTER2
206040. BW_PTIMER_CTRL
206041. BW_PTIMER_LIMIT
206042. BW_PTIMER_NDLIMIT
206043. BW_RATE
206044. BW_SCALE
206045. BW_SETTING
206046. BW_SHIFT
206047. BW_TIMER_COUNTER
206048. BW_TIMER_COUNTER2
206049. BW_TIMER_CTRL
206050. BW_TIMER_LIMIT
206051. BW_TIMER_NDLIMIT
206052. BW_UNIT
206053. BW_UNKNOWN
206054. BW_VALUE_UNIT_PERCENT1_100
206055. BW_VAL_TRACE_COUNT
206056. BW_VAL_TRACE_END_VOLTAGE_LEVEL
206057. BW_VAL_TRACE_END_WATERMARKS
206058. BW_VAL_TRACE_FINISH
206059. BW_VAL_TRACE_SETUP
206060. BW_VAL_TRACE_SKIP
206061. BX
206062. BXATXAGC
206063. BXBTXAGC
206064. BXCTXAGC
206065. BXDTXAGC
206066. BXTALCAP
206067. BXTALCAP01
206068. BXTALCAP23
206069. BXTALCAP92X
206070. BXTALPOWERUP
206071. BXTWC_ADCIRQ
206072. BXTWC_ADC_IRQ
206073. BXTWC_ADC_LVL1_IRQ
206074. BXTWC_BCUIRQ
206075. BXTWC_BCU_IRQ
206076. BXTWC_BCU_LVL1_IRQ
206077. BXTWC_CHGR0IRQ
206078. BXTWC_CHGR0_IRQ
206079. BXTWC_CHGR1IRQ
206080. BXTWC_CHGR1_IRQ
206081. BXTWC_CHGRCTRL0_ADDR
206082. BXTWC_CHGRCTRL1_ADDR
206083. BXTWC_CHGRCTRL2_ADDR
206084. BXTWC_CHGRSTATUS_ADDR
206085. BXTWC_CHGR_LVL1_IRQ
206086. BXTWC_CHIPID
206087. BXTWC_CHIPVER
206088. BXTWC_CHRTTADDR_ADDR
206089. BXTWC_CHRTTDATA_ADDR
206090. BXTWC_CRITIRQ
206091. BXTWC_CRIT_IRQ
206092. BXTWC_CRIT_LVL1_IRQ
206093. BXTWC_DBGUSBBC1_ADDR
206094. BXTWC_DBGUSBBC2_ADDR
206095. BXTWC_DBGUSBBCSTAT_ADDR
206096. BXTWC_DEVICE1_ADDR
206097. BXTWC_DEVICE2_ADDR
206098. BXTWC_DEVICE3_ADDR
206099. BXTWC_GPIOIRQ0
206100. BXTWC_GPIOIRQ1
206101. BXTWC_GPIO_LVL1_IRQ
206102. BXTWC_IRQLVL1
206103. BXTWC_MADCIRQ
206104. BXTWC_MBCUIRQ
206105. BXTWC_MCHGR0IRQ
206106. BXTWC_MCHGR1IRQ
206107. BXTWC_MCRITIRQ
206108. BXTWC_MGPIO0IRQ
206109. BXTWC_MGPIO1IRQ
206110. BXTWC_MIRQLVL1
206111. BXTWC_MIRQLVL1_MCHGR
206112. BXTWC_MIRQLVL1_MTMU
206113. BXTWC_MPWRBTNIRQ
206114. BXTWC_MTHRM0IRQ
206115. BXTWC_MTHRM1IRQ
206116. BXTWC_MTHRM2IRQ
206117. BXTWC_MTMUIRQ
206118. BXTWC_MTMUIRQ_REG
206119. BXTWC_PWRBTNIRQ
206120. BXTWC_PWRBTN_IRQ
206121. BXTWC_PWRBTN_LVL1_IRQ
206122. BXTWC_SCHGRIRQ0_ADDR
206123. BXTWC_STHRM0IRQ
206124. BXTWC_STHRM1IRQ
206125. BXTWC_STHRM2IRQ
206126. BXTWC_STHRMIRQ0_ADDR
206127. BXTWC_THRM0IRQ
206128. BXTWC_THRM1IRQ
206129. BXTWC_THRM2IRQ
206130. BXTWC_THRMBATZONE_ADDR
206131. BXTWC_THRMZN0H_ADDR
206132. BXTWC_THRMZN0L_ADDR
206133. BXTWC_THRMZN1H_ADDR
206134. BXTWC_THRMZN1L_ADDR
206135. BXTWC_THRMZN2H_ADDR
206136. BXTWC_THRMZN2L_ADDR
206137. BXTWC_THRMZN3H_ADDR
206138. BXTWC_THRMZN3L_ADDR
206139. BXTWC_THRMZN4H_ADDR
206140. BXTWC_THRMZN4L_ADDR
206141. BXTWC_THRM_LVL1_IRQ
206142. BXTWC_TMUIRQ
206143. BXTWC_TMU_ALRM_IRQ
206144. BXTWC_TMU_ALRM_MASK
206145. BXTWC_TMU_IRQ
206146. BXTWC_TMU_LVL1_IRQ
206147. BXTWC_TMU_SYS_ALRM
206148. BXTWC_TMU_WK_ALRM
206149. BXTWC_UIBTN_IRQ
206150. BXTWC_USBC_IRQ
206151. BXTWC_USBIDCTRL_ADDR
206152. BXTWC_USBIDEN_MASK
206153. BXTWC_USBIDSTAT_ADDR
206154. BXTWC_USBPATH_ADDR
206155. BXTWC_USBPHYCTRL_ADDR
206156. BXTWC_USBSRCDETSTATUS_ADDR
206157. BXTWC_WAKESRC2_ADDR
206158. BXTWC_WAKESRC_ADDR
206159. BXT_ADSP_ERROR_CODE
206160. BXT_ADSP_FW_BIN_HDR_OFFSET
206161. BXT_ADSP_FW_STATUS
206162. BXT_ADSP_SRAM0_BASE
206163. BXT_ADSP_SRAM1_BASE
206164. BXT_Ax_DEVICE_ID
206165. BXT_BASEFW_TIMEOUT
206166. BXT_BASE_FW_MODULE_ID
206167. BXT_BLC_PWM_CTL
206168. BXT_BLC_PWM_DUTY
206169. BXT_BLC_PWM_ENABLE
206170. BXT_BLC_PWM_FREQ
206171. BXT_BLC_PWM_POLARITY
206172. BXT_Bx_DEVICE_ID
206173. BXT_CDCLK_CD2X_DIV_SEL_1
206174. BXT_CDCLK_CD2X_DIV_SEL_1_5
206175. BXT_CDCLK_CD2X_DIV_SEL_2
206176. BXT_CDCLK_CD2X_DIV_SEL_4
206177. BXT_CDCLK_CD2X_DIV_SEL_MASK
206178. BXT_CDCLK_CD2X_PIPE
206179. BXT_CDCLK_CD2X_PIPE_NONE
206180. BXT_CDCLK_SSA_PRECHARGE_ENABLE
206181. BXT_COMMUNITY
206182. BXT_CSR_DC3_DC5_COUNT
206183. BXT_CSR_MAX_FW_SIZE
206184. BXT_CSR_PATH
206185. BXT_CSR_VERSION_REQUIRED
206186. BXT_D0I3_DELAY
206187. BXT_DDIA_HPD_INVERT
206188. BXT_DDIB_HPD_INVERT
206189. BXT_DDIC_HPD_INVERT
206190. BXT_DDI_HPD_INVERT_MASK
206191. BXT_DEFEATURE_DPI_FIFO_CTR
206192. BXT_DE_PLL_CTL
206193. BXT_DE_PLL_ENABLE
206194. BXT_DE_PLL_LOCK
206195. BXT_DE_PLL_PLL_ENABLE
206196. BXT_DE_PLL_RATIO
206197. BXT_DE_PLL_RATIO_MASK
206198. BXT_DE_PORT_GMBUS
206199. BXT_DE_PORT_HOTPLUG_MASK
206200. BXT_DE_PORT_HP_DDIA
206201. BXT_DE_PORT_HP_DDIB
206202. BXT_DE_PORT_HP_DDIC
206203. BXT_DIALOG_CODEC_DAI
206204. BXT_DISPLAY_DC_OFF_POWER_DOMAINS
206205. BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS
206206. BXT_DISP_PW_DPIO_CMN_A
206207. BXT_DPCM_AUDIO_CP
206208. BXT_DPCM_AUDIO_DMIC_CP
206209. BXT_DPCM_AUDIO_HDMI1_PB
206210. BXT_DPCM_AUDIO_HDMI2_PB
206211. BXT_DPCM_AUDIO_HDMI3_PB
206212. BXT_DPCM_AUDIO_HS_PB
206213. BXT_DPCM_AUDIO_PB
206214. BXT_DPCM_AUDIO_REF_CP
206215. BXT_DPHY_DEFEATURE_EN
206216. BXT_DPIO_CMN_A_POWER_DOMAINS
206217. BXT_DPIO_CMN_BC_POWER_DOMAINS
206218. BXT_DRAM_CHANNEL_ACTIVE_MASK
206219. BXT_DRAM_CHANNEL_ACTIVE_SHIFT
206220. BXT_DRAM_RANK_DUAL
206221. BXT_DRAM_RANK_MASK
206222. BXT_DRAM_RANK_SINGLE
206223. BXT_DRAM_SIZE_12GBIT
206224. BXT_DRAM_SIZE_16GBIT
206225. BXT_DRAM_SIZE_4GBIT
206226. BXT_DRAM_SIZE_6GBIT
206227. BXT_DRAM_SIZE_8GBIT
206228. BXT_DRAM_SIZE_MASK
206229. BXT_DRAM_SIZE_SHIFT
206230. BXT_DRAM_TYPE_DDR3
206231. BXT_DRAM_TYPE_DDR4
206232. BXT_DRAM_TYPE_LPDDR3
206233. BXT_DRAM_TYPE_LPDDR4
206234. BXT_DRAM_TYPE_MASK
206235. BXT_DRAM_TYPE_SHIFT
206236. BXT_DRAM_WIDTH_MASK
206237. BXT_DRAM_WIDTH_SHIFT
206238. BXT_DRAM_WIDTH_X16
206239. BXT_DRAM_WIDTH_X32
206240. BXT_DRAM_WIDTH_X64
206241. BXT_DRAM_WIDTH_X8
206242. BXT_DSC_ENABLE
206243. BXT_DSIA_16X_BY1
206244. BXT_DSIA_16X_BY2
206245. BXT_DSIA_16X_BY3
206246. BXT_DSIA_16X_BY4
206247. BXT_DSIA_16X_MASK
206248. BXT_DSIC_16X_BY1
206249. BXT_DSIC_16X_BY2
206250. BXT_DSIC_16X_BY3
206251. BXT_DSIC_16X_BY4
206252. BXT_DSIC_16X_MASK
206253. BXT_DSI_FREQ_SEL_MASK
206254. BXT_DSI_FREQ_SEL_SHIFT
206255. BXT_DSI_PLL_CTL
206256. BXT_DSI_PLL_DO_ENABLE
206257. BXT_DSI_PLL_ENABLE
206258. BXT_DSI_PLL_LOCKED
206259. BXT_DSI_PLL_PVD_RATIO_1
206260. BXT_DSI_PLL_PVD_RATIO_MASK
206261. BXT_DSI_PLL_PVD_RATIO_SHIFT
206262. BXT_DSI_PLL_RATIO_MASK
206263. BXT_DSI_PLL_RATIO_MAX
206264. BXT_DSI_PLL_RATIO_MIN
206265. BXT_D_CR_DRP0_DUNIT
206266. BXT_D_CR_DRP0_DUNIT8
206267. BXT_D_CR_DRP0_DUNIT9
206268. BXT_D_CR_DRP0_DUNIT_END
206269. BXT_D_CR_DRP0_DUNIT_START
206270. BXT_FREG_NUM
206271. BXT_FW_ROM_INIT_RETRY
206272. BXT_GMBUS_GATING_DIS
206273. BXT_GPI_IE
206274. BXT_GPI_IS
206275. BXT_GT_PERF_STATUS
206276. BXT_HOSTSW_OWN
206277. BXT_INIT_TIMEOUT
206278. BXT_INSTANCE_ID
206279. BXT_IPC_PURGE_FW
206280. BXT_MAXIM_CODEC_DAI
206281. BXT_MAX_VAR_OUTPUT_KHZ
206282. BXT_MEMORY_FREQ_MULTIPLIER_HZ
206283. BXT_MIPI1_8X_BY3_DIVIDER_MASK
206284. BXT_MIPI1_8X_BY3_SHIFT
206285. BXT_MIPI1_DIV_SHIFT
206286. BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK
206287. BXT_MIPI1_RX_ESCLK_LOWER_SHIFT
206288. BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK
206289. BXT_MIPI1_RX_ESCLK_UPPER_SHIFT
206290. BXT_MIPI1_TX_ESCLK_FIXDIV_MASK
206291. BXT_MIPI1_TX_ESCLK_SHIFT
206292. BXT_MIPI2_8X_BY3_DIVIDER_MASK
206293. BXT_MIPI2_8X_BY3_SHIFT
206294. BXT_MIPI2_DIV_SHIFT
206295. BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK
206296. BXT_MIPI2_RX_ESCLK_LOWER_SHIFT
206297. BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK
206298. BXT_MIPI2_RX_ESCLK_UPPER_SHIFT
206299. BXT_MIPI2_TX_ESCLK_FIXDIV_MASK
206300. BXT_MIPI2_TX_ESCLK_SHIFT
206301. BXT_MIPI_8X_BY3_DIVIDER
206302. BXT_MIPI_8X_BY3_DIVIDER_MASK
206303. BXT_MIPI_8X_BY3_SHIFT
206304. BXT_MIPI_BASE
206305. BXT_MIPI_CLOCK_CTL
206306. BXT_MIPI_DIV_SHIFT
206307. BXT_MIPI_PORT_CTRL
206308. BXT_MIPI_RX_ESCLK_LOWER_DIVIDER
206309. BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK
206310. BXT_MIPI_RX_ESCLK_LOWER_SHIFT
206311. BXT_MIPI_RX_ESCLK_UPPER_DIVIDER
206312. BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK
206313. BXT_MIPI_RX_ESCLK_UPPER_SHIFT
206314. BXT_MIPI_TRANS_HACTIVE
206315. BXT_MIPI_TRANS_VACTIVE
206316. BXT_MIPI_TRANS_VTOTAL
206317. BXT_MIPI_TX_ESCLK_DIVIDER
206318. BXT_MIPI_TX_ESCLK_FIXDIV_MASK
206319. BXT_MIPI_TX_ESCLK_SHIFT
206320. BXT_PADCFGLOCK
206321. BXT_PAD_OWN
206322. BXT_PHY_BASE
206323. BXT_PHY_CMNLANE_POWERDOWN_ACK
206324. BXT_PHY_CTL
206325. BXT_PHY_CTL_FAMILY
206326. BXT_PHY_LANE_ENABLED
206327. BXT_PHY_LANE_POWERDOWN_ACK
206328. BXT_PIPE_SELECT
206329. BXT_PIPE_SELECT_MASK
206330. BXT_PIPE_SELECT_SHIFT
206331. BXT_PIXEL_OVERLAP_CNT_MASK
206332. BXT_PIXEL_OVERLAP_CNT_SHIFT
206333. BXT_PORT_CL1CM_DW0
206334. BXT_PORT_CL1CM_DW10
206335. BXT_PORT_CL1CM_DW28
206336. BXT_PORT_CL1CM_DW30
206337. BXT_PORT_CL1CM_DW9
206338. BXT_PORT_CL2CM_DW6
206339. BXT_PORT_PCS_DW10_GRP
206340. BXT_PORT_PCS_DW10_LN01
206341. BXT_PORT_PCS_DW12_GRP
206342. BXT_PORT_PCS_DW12_LN01
206343. BXT_PORT_PCS_DW12_LN23
206344. BXT_PORT_PLL
206345. BXT_PORT_PLL_EBB_0
206346. BXT_PORT_PLL_EBB_4
206347. BXT_PORT_PLL_ENABLE
206348. BXT_PORT_REF_DW3
206349. BXT_PORT_REF_DW6
206350. BXT_PORT_REF_DW8
206351. BXT_PORT_TX_DW14_LN
206352. BXT_PORT_TX_DW2_GRP
206353. BXT_PORT_TX_DW2_LN0
206354. BXT_PORT_TX_DW3_GRP
206355. BXT_PORT_TX_DW3_LN0
206356. BXT_PORT_TX_DW4_GRP
206357. BXT_PORT_TX_DW4_LN0
206358. BXT_PORT_TX_DW5_GRP
206359. BXT_PORT_TX_DW5_LN0
206360. BXT_POWER_CYCLE_DELAY_MASK
206361. BXT_PR
206362. BXT_PR_NUM
206363. BXT_P_CR_GT_DISP_PWRON
206364. BXT_P_CR_MC_BIOS_REQ_0_0_0
206365. BXT_P_DSI_REGULATOR_CFG
206366. BXT_P_DSI_REGULATOR_TX_CTRL
206367. BXT_REF_CLOCK_KHZ
206368. BXT_REQ_DATA_MASK
206369. BXT_REVID_A0
206370. BXT_REVID_A1
206371. BXT_REVID_B0
206372. BXT_REVID_B_LAST
206373. BXT_REVID_C0
206374. BXT_RGB_FLIP
206375. BXT_ROM_INIT
206376. BXT_ROM_INIT_TIMEOUT
206377. BXT_RP_STATE_CAP
206378. BXT_SSFSTS_CTL
206379. BXT_WOPCM_RC6_CTX_RESERVED
206380. BX_ANALOG_IN
206381. BX_ANALOG_OUT
206382. BX_DIGITAL_IN
206383. BX_DIGITAL_OUT
206384. BX_NUM
206385. BX_RESET_CNTL_IND__LINK_TRAIN_EN_MASK
206386. BX_RESET_CNTL_IND__LINK_TRAIN_EN__SHIFT
206387. BX_RESET_CNTL__LINK_TRAIN_EN_MASK
206388. BX_RESET_CNTL__LINK_TRAIN_EN__MASK
206389. BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT
206390. BX_RESET_EN_IND__COR_RESET_EN_MASK
206391. BX_RESET_EN_IND__COR_RESET_EN__SHIFT
206392. BX_RESET_EN_IND__REG_RESET_EN_MASK
206393. BX_RESET_EN_IND__REG_RESET_EN__SHIFT
206394. BX_RESET_EN_IND__STY_RESET_EN_MASK
206395. BX_RESET_EN_IND__STY_RESET_EN__SHIFT
206396. BX_RESET_EN__COR_RESET_EN_MASK
206397. BX_RESET_EN__COR_RESET_EN__MASK
206398. BX_RESET_EN__COR_RESET_EN__SHIFT
206399. BX_RESET_EN__DB_APER_RESET_EN_MASK
206400. BX_RESET_EN__DB_APER_RESET_EN__SHIFT
206401. BX_RESET_EN__FLR_TIMER_SEL_MASK
206402. BX_RESET_EN__FLR_TIMER_SEL__SHIFT
206403. BX_RESET_EN__FLR_TWICE_EN_MASK
206404. BX_RESET_EN__FLR_TWICE_EN__MASK
206405. BX_RESET_EN__FLR_TWICE_EN__SHIFT
206406. BX_RESET_EN__PF_FLR_NEWHDL_EN_MASK
206407. BX_RESET_EN__PF_FLR_NEWHDL_EN__SHIFT
206408. BX_RESET_EN__REG_RESET_EN_MASK
206409. BX_RESET_EN__REG_RESET_EN__MASK
206410. BX_RESET_EN__REG_RESET_EN__SHIFT
206411. BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK
206412. BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__MASK
206413. BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT
206414. BX_RESET_EN__STY_RESET_EN_MASK
206415. BX_RESET_EN__STY_RESET_EN__MASK
206416. BX_RESET_EN__STY_RESET_EN__SHIFT
206417. BYD_CMD_SET_ABSOLUTE_MODE
206418. BYD_CMD_SET_BOTTOM_EDGE_REGION
206419. BYD_CMD_SET_EDGE_MOTION
206420. BYD_CMD_SET_EDGE_MOTION_SPEED
206421. BYD_CMD_SET_HANDEDNESS
206422. BYD_CMD_SET_LEFT_EDGE_REGION
206423. BYD_CMD_SET_MULTITOUCH
206424. BYD_CMD_SET_OFFSCREEN_SWIPE
206425. BYD_CMD_SET_ONE_FINGER_SCROLL
206426. BYD_CMD_SET_ONE_FINGER_SCROLL_FUNC
206427. BYD_CMD_SET_PALM_CHECK
206428. BYD_CMD_SET_PHYSICAL_BUTTONS
206429. BYD_CMD_SET_RIGHT_EDGE_REGION
206430. BYD_CMD_SET_SLIDING_SPEED
206431. BYD_CMD_SET_TAP
206432. BYD_CMD_SET_TAP_DRAG
206433. BYD_CMD_SET_TAP_DRAG_DELAY_TIME
206434. BYD_CMD_SET_TOP_EDGE_REGION
206435. BYD_CMD_SET_TOUCH_SENSITIVITY
206436. BYD_CMD_SET_TWO_FINGER_SCROLL
206437. BYD_CMD_SET_TWO_FINGER_SCROLL_FUNC
206438. BYD_DT
206439. BYD_PACKET_ABSOLUTE
206440. BYD_PACKET_FOUR_FINGER_DOWN
206441. BYD_PACKET_FOUR_FINGER_UP
206442. BYD_PACKET_LEFT_AND_RIGHT_CORNER_CLICK
206443. BYD_PACKET_LEFT_CORNER_CLICK
206444. BYD_PACKET_ONTO_PAD_SWIPE_DOWN
206445. BYD_PACKET_ONTO_PAD_SWIPE_LEFT
206446. BYD_PACKET_ONTO_PAD_SWIPE_RIGHT
206447. BYD_PACKET_ONTO_PAD_SWIPE_UP
206448. BYD_PACKET_PINCH_IN
206449. BYD_PACKET_PINCH_OUT
206450. BYD_PACKET_REGION_SCROLL_DOWN
206451. BYD_PACKET_REGION_SCROLL_LEFT
206452. BYD_PACKET_REGION_SCROLL_RIGHT
206453. BYD_PACKET_REGION_SCROLL_UP
206454. BYD_PACKET_RELATIVE
206455. BYD_PACKET_RIGHT_CORNER_CLICK
206456. BYD_PACKET_ROTATE_ANTICLOCKWISE
206457. BYD_PACKET_ROTATE_CLOCKWISE
206458. BYD_PACKET_THREE_FINGER_SWIPE_DOWN
206459. BYD_PACKET_THREE_FINGER_SWIPE_LEFT
206460. BYD_PACKET_THREE_FINGER_SWIPE_RIGHT
206461. BYD_PACKET_THREE_FINGER_SWIPE_UP
206462. BYD_PACKET_TWO_FINGER_SCROLL_DOWN
206463. BYD_PACKET_TWO_FINGER_SCROLL_LEFT
206464. BYD_PACKET_TWO_FINGER_SCROLL_RIGHT
206465. BYD_PACKET_TWO_FINGER_SCROLL_UP
206466. BYD_PAD_HEIGHT
206467. BYD_PAD_RESOLUTION
206468. BYD_PAD_WIDTH
206469. BYD_TOUCH_TIMEOUT
206470. BYP
206471. BYPASS
206472. BYPASSCTRL_SYS
206473. BYPASSCTRL_SYS_GPCPLL_SHIFT
206474. BYPASSCTRL_SYS_GPCPLL_WIDTH
206475. BYPASSD
206476. BYPASSD_MASK
206477. BYPASSD_SHIFT
206478. BYPASS_ADDR_PHASE
206479. BYPASS_APIC_DEASSERT
206480. BYPASS_CPU_SHIFT
206481. BYPASS_CPU_WIDTH
206482. BYPASS_DC_SHIFT
206483. BYPASS_DC_WIDTH
206484. BYPASS_DDR_SHIFT
206485. BYPASS_DDR_WIDTH
206486. BYPASS_EN
206487. BYPASS_GAMUT
206488. BYPASS_ICSC
206489. BYPASS_MASK
206490. BYPASS_MODE
206491. BYPASS_PCS_RX
206492. BYPASS_PCS_TX
206493. BYPASS_RSM_DLL_CAL
206494. BYPASS_RSM_SAMP_CAL
206495. BYPASS_SHIFT
206496. BYPASS_THRESHOLD
206497. BYPASS_VCO_RANGE
206498. BYPASS_VM
206499. BYPASS_VOLUME
206500. BYP_AB_CTRL
206501. BYREF_ALL
206502. BYREF_STRUCT
206503. BYTCR_INPUT_DEFAULTS
206504. BYTE
206505. BYTE0
206506. BYTE0_CLK_SRC
206507. BYTE0_DATA_MASK
206508. BYTE0_DATA_SHIFT
206509. BYTE0_MASK_MASK
206510. BYTE0_MASK_SHIFT
206511. BYTE1
206512. BYTE1_CLK_SRC
206513. BYTE1_MASK
206514. BYTE2
206515. BYTE2_MASK
206516. BYTE3
206517. BYTE3_MASK
206518. BYTEALIGN
206519. BYTEBITS
206520. BYTECNT_S
206521. BYTECNT_V
206522. BYTEREV
206523. BYTESEX_BE
206524. BYTESEX_LE
206525. BYTESEX_PDP
206526. BYTESWAP_DATA
206527. BYTES_DMAED
206528. BYTES_FOR_QID
206529. BYTES_FOR_QID_SHIFT
206530. BYTES_IN_DWORD
206531. BYTES_PER_CHANNEL
206532. BYTES_PER_COUNTER
206533. BYTES_PER_DHLEN_UNIT
206534. BYTES_PER_FIFO_WORD
206535. BYTES_PER_FRAME
206536. BYTES_PER_KBIT
206537. BYTES_PER_LONG
206538. BYTES_PER_MPI_LIMB
206539. BYTES_PER_NS
206540. BYTES_PER_PIXEL
206541. BYTES_PER_POINTER
206542. BYTES_PER_ROW
206543. BYTES_PER_SAMPLE
206544. BYTES_PER_SAMPLE_USB
206545. BYTES_PER_WORD
206546. BYTES_THRESH
206547. BYTES_TO_ALIGN
206548. BYTES_TO_BE_TYPE
206549. BYTES_TO_BITS
206550. BYTES_TO_DWORDS
206551. BYTES_TO_MB
206552. BYTES_TO_NS
206553. BYTES_TO_OWORDS
206554. BYTES_TO_QWORDS
206555. BYTES_TRANSFERRED
206556. BYTE_ALIGN
206557. BYTE_BIG
206558. BYTE_CLK_CNTL
206559. BYTE_CLK_SEL_10MHZ
206560. BYTE_CLK_SEL_20MHZ
206561. BYTE_CLK_SEL_5MHZ
206562. BYTE_CNT
206563. BYTE_COPY_FWD
206564. BYTE_CORE_SET_HIGH
206565. BYTE_CORE_SET_LOW
206566. BYTE_DATA
206567. BYTE_DONE_STS
206568. BYTE_EN
206569. BYTE_ENABLE_MASK
206570. BYTE_EN_BYTE
206571. BYTE_EN_DWORD
206572. BYTE_EN_END_MASK
206573. BYTE_EN_SIX_BYTES
206574. BYTE_EN_START_MASK
206575. BYTE_EN_WORD
206576. BYTE_FOUND
206577. BYTE_HEX_FMT
206578. BYTE_LANE0
206579. BYTE_LANE1
206580. BYTE_LANE2
206581. BYTE_LANE3
206582. BYTE_LITTLE
206583. BYTE_MASK
206584. BYTE_MODE
206585. BYTE_NOT_FOUND
206586. BYTE_NUMBER
206587. BYTE_OFFSET
206588. BYTE_ORDER_LSB_TO_MSB
206589. BYTE_ORDER_MASK
206590. BYTE_ORDER_MSB_TO_LSB
206591. BYTE_PER_SAMPLE
206592. BYTE_PIPE_TYPE
206593. BYTE_PROGRAM
206594. BYTE_REF
206595. BYTE_REG_BITS_IS_ON
206596. BYTE_REG_BITS_OFF
206597. BYTE_REG_BITS_ON
206598. BYTE_REG_BITS_SET
206599. BYTE_SET_THRESHOLD
206600. BYTE_SHIFT
206601. BYTE_SWAP
206602. BYTE_SWAP_NOSWAP
206603. BYTE_SWAP_SWAP2
206604. BYTE_SWAP_SWAP4
206605. BYTE_SWAP_SWAP4HW
206606. BYTE_TEST
206607. BYTE_TIME_FULLSPEED
206608. BYTE_TIME_LOWSPEED
206609. BYTE_TO_BURST
206610. BYTE_UNITS
206611. BYTE_WIDE
206612. BYT_AEGEX_10
206613. BYT_ALTER_GPIO_MUX
206614. BYT_BCR
206615. BYT_BCR_WPD
206616. BYT_CHT_ES8316_INTMIC_IN1_MAP
206617. BYT_CHT_ES8316_INTMIC_IN2_MAP
206618. BYT_CHT_ES8316_JD_INVERTED
206619. BYT_CHT_ES8316_MAP
206620. BYT_CHT_ES8316_MONO_SPEAKER
206621. BYT_CHT_ES8316_SSP0
206622. BYT_CODEC_DAI1
206623. BYT_CODEC_DAI2
206624. BYT_CONF0_REG
206625. BYT_CONF0_RESTORE_MASK
206626. BYT_CONF1_REG
206627. BYT_CRC_HRV
206628. BYT_DEBOUNCE_EN
206629. BYT_DEBOUNCE_PULSE_12MS
206630. BYT_DEBOUNCE_PULSE_1500US
206631. BYT_DEBOUNCE_PULSE_24MS
206632. BYT_DEBOUNCE_PULSE_375US
206633. BYT_DEBOUNCE_PULSE_3MS
206634. BYT_DEBOUNCE_PULSE_6MS
206635. BYT_DEBOUNCE_PULSE_750US
206636. BYT_DEBOUNCE_PULSE_MASK
206637. BYT_DEBOUNCE_REG
206638. BYT_DEFAULT_GPIO_MUX
206639. BYT_DFT_REG
206640. BYT_DIRECT_IRQ_EN
206641. BYT_DIR_MASK
206642. BYT_DSP_BAR
206643. BYT_FREG_NUM
206644. BYT_FW_MOD_OFFSET
206645. BYT_FW_MOD_TABLE_OFFSET
206646. BYT_FW_MOD_TABLE_SIZE
206647. BYT_GLITCH_FILTER_EN
206648. BYT_GLITCH_F_FAST_CLK
206649. BYT_GLITCH_F_SLOW_CLK
206650. BYT_IMR_BAR
206651. BYT_INPUT_EN
206652. BYT_INT_STAT_REG
206653. BYT_IODEN
206654. BYT_IOSF_OCP_NETCTRL0
206655. BYT_IOSF_OCP_TIMEOUT_BASE
206656. BYT_IOSF_SCCEP
206657. BYT_LEVEL
206658. BYT_NCORE_ACPI_UID
206659. BYT_NGPIO_NCORE
206660. BYT_NGPIO_SCORE
206661. BYT_NGPIO_SUS
206662. BYT_OUTPUT_EN
206663. BYT_PANIC_OFFSET
206664. BYT_PCI_BAR
206665. BYT_PCI_BAR_SIZE
206666. BYT_PCM_COUNT
206667. BYT_PIN_MUX
206668. BYT_POV_P1006W
206669. BYT_PR
206670. BYT_PRV_CLK
206671. BYT_PRV_CLK_EN
206672. BYT_PRV_CLK_M_VAL_SHIFT
206673. BYT_PRV_CLK_N_VAL_SHIFT
206674. BYT_PRV_CLK_UPDATE
206675. BYT_PR_NUM
206676. BYT_PTE_SNOOPED_BY_CPU_CACHES
206677. BYT_PTE_WRITEABLE
206678. BYT_PULL_ASSIGN_DOWN
206679. BYT_PULL_ASSIGN_MASK
206680. BYT_PULL_ASSIGN_SHIFT
206681. BYT_PULL_ASSIGN_UP
206682. BYT_PULL_STR_10K
206683. BYT_PULL_STR_20K
206684. BYT_PULL_STR_2K
206685. BYT_PULL_STR_40K
206686. BYT_PULL_STR_MASK
206687. BYT_PULL_STR_SHIFT
206688. BYT_RT5640_DIFF_MIC
206689. BYT_RT5640_DMIC1_MAP
206690. BYT_RT5640_DMIC2_MAP
206691. BYT_RT5640_DMIC_EN
206692. BYT_RT5640_IN1_MAP
206693. BYT_RT5640_IN3_MAP
206694. BYT_RT5640_JDSRC
206695. BYT_RT5640_JD_NOT_INV
206696. BYT_RT5640_JD_SRC_GPIO1
206697. BYT_RT5640_JD_SRC_GPIO2
206698. BYT_RT5640_JD_SRC_GPIO3
206699. BYT_RT5640_JD_SRC_GPIO4
206700. BYT_RT5640_JD_SRC_JD1_IN4P
206701. BYT_RT5640_JD_SRC_JD2_IN4N
206702. BYT_RT5640_MAP
206703. BYT_RT5640_MCLK_25MHZ
206704. BYT_RT5640_MCLK_EN
206705. BYT_RT5640_MONO_SPEAKER
206706. BYT_RT5640_OVCD_SF
206707. BYT_RT5640_OVCD_SF_0P5
206708. BYT_RT5640_OVCD_SF_0P75
206709. BYT_RT5640_OVCD_SF_1P0
206710. BYT_RT5640_OVCD_SF_1P5
206711. BYT_RT5640_OVCD_TH
206712. BYT_RT5640_OVCD_TH_1500UA
206713. BYT_RT5640_OVCD_TH_2000UA
206714. BYT_RT5640_OVCD_TH_600UA
206715. BYT_RT5640_SSP0_AIF1
206716. BYT_RT5640_SSP0_AIF2
206717. BYT_RT5640_SSP2_AIF2
206718. BYT_RT5651_DEFAULT_QUIRKS
206719. BYT_RT5651_DMIC_EN
206720. BYT_RT5651_DMIC_MAP
206721. BYT_RT5651_HP_LR_SWAPPED
206722. BYT_RT5651_IN1_IN2_MAP
206723. BYT_RT5651_IN1_MAP
206724. BYT_RT5651_IN2_MAP
206725. BYT_RT5651_JD1_1
206726. BYT_RT5651_JD1_2
206727. BYT_RT5651_JD2
206728. BYT_RT5651_JDSRC
206729. BYT_RT5651_JD_NOT_INV
206730. BYT_RT5651_JD_NULL
206731. BYT_RT5651_MAP
206732. BYT_RT5651_MCLK_25MHZ
206733. BYT_RT5651_MCLK_EN
206734. BYT_RT5651_MONO_SPEAKER
206735. BYT_RT5651_OVCD_SF
206736. BYT_RT5651_OVCD_SF_0P5
206737. BYT_RT5651_OVCD_SF_0P75
206738. BYT_RT5651_OVCD_SF_1P0
206739. BYT_RT5651_OVCD_SF_1P5
206740. BYT_RT5651_OVCD_TH
206741. BYT_RT5651_OVCD_TH_1500UA
206742. BYT_RT5651_OVCD_TH_2000UA
206743. BYT_RT5651_OVCD_TH_600UA
206744. BYT_RT5651_SSP0_AIF1
206745. BYT_RT5651_SSP0_AIF2
206746. BYT_RT5651_SSP2_AIF2
206747. BYT_SCORE_ACPI_UID
206748. BYT_SOC_DTS_APIC_IRQ
206749. BYT_SSFSTS_CTL
206750. BYT_STACK_DUMP_SIZE
206751. BYT_SUS_ACPI_UID
206752. BYT_THINKPAD_10
206753. BYT_TRIG_LVL
206754. BYT_TRIG_MASK
206755. BYT_TRIG_NEG
206756. BYT_TRIG_POS
206757. BYT_TX_OVF_INT
206758. BYT_TX_OVF_INT_MASK
206759. BYT_VAL_REG
206760. BYT_VAL_RESTORE_MASK
206761. BY_AL2230_REG_LEN
206762. BY_AL7230_REG_LEN
206763. BY_PASS_MIN_LEVEL
206764. BY_PASS_PRIO_NUM_LEVELS
206765. BZEBRA1_CHANNEL_NUM
206766. BZEBRA1_HSSIENABLE
206767. BZEBRA1_RXCHANGEPUMP
206768. BZEBRA1_RXCOUNTER
206769. BZEBRA1_RXLPFBW
206770. BZEBRA1_TRXCONTROL
206771. BZEBRA1_TRXGAINSETTING
206772. BZEBRA1_TXCHANGEPUMP
206773. BZEBRA1_TXLPFBW
206774. BZIP2_IOBUF_SIZE
206775. B_
206776. B_16
206777. B_32
206778. B_AIDL_BDIS
206779. B_ALPHA
206780. B_ASE0_BRST
206781. B_ASE_BRST
206782. B_BLK_HEAD
206783. B_BREAK
206784. B_CAP
206785. B_CAPSYM
206786. B_CC_REG_DIVERSITY__A
206787. B_CC_REG_JTAGID_L__A
206788. B_CC_REG_OSC_MODE_M20
206789. B_CC_REG_OSC_MODE__A
206790. B_CC_REG_PLL_MODE_BYPASS_PLL
206791. B_CC_REG_PLL_MODE_PUMP_CUR_12
206792. B_CC_REG_PLL_MODE__A
206793. B_CC_REG_PWD_MODE_DOWN_PLL
206794. B_CC_REG_PWD_MODE__A
206795. B_CC_REG_REF_DIVIDE__A
206796. B_CC_REG_UPDATE_KEY
206797. B_CC_REG_UPDATE__A
206798. B_CE_COMM_EXEC__A
206799. B_CE_REG_ATT__A
206800. B_CE_REG_AVG_POW__A
206801. B_CE_REG_COMM_EXEC__A
206802. B_CE_REG_FI_EXP_NORM__A
206803. B_CE_REG_FI_SHT_INCR__A
206804. B_CE_REG_FR_BYPASS__A
206805. B_CE_REG_FR_ERR_SH__A
206806. B_CE_REG_FR_MAN_SH__A
206807. B_CE_REG_FR_MID_TAP__A
206808. B_CE_REG_FR_MODE__A
206809. B_CE_REG_FR_PM_SET__A
206810. B_CE_REG_FR_RIO_G00__A
206811. B_CE_REG_FR_RIO_G01__A
206812. B_CE_REG_FR_RIO_G02__A
206813. B_CE_REG_FR_RIO_G03__A
206814. B_CE_REG_FR_RIO_G04__A
206815. B_CE_REG_FR_RIO_G05__A
206816. B_CE_REG_FR_RIO_G06__A
206817. B_CE_REG_FR_RIO_G07__A
206818. B_CE_REG_FR_RIO_G08__A
206819. B_CE_REG_FR_RIO_G09__A
206820. B_CE_REG_FR_RIO_G10__A
206821. B_CE_REG_FR_RIO_GAIN__A
206822. B_CE_REG_FR_SQS_G00__A
206823. B_CE_REG_FR_SQS_G01__A
206824. B_CE_REG_FR_SQS_G02__A
206825. B_CE_REG_FR_SQS_G03__A
206826. B_CE_REG_FR_SQS_G04__A
206827. B_CE_REG_FR_SQS_G05__A
206828. B_CE_REG_FR_SQS_G06__A
206829. B_CE_REG_FR_SQS_G07__A
206830. B_CE_REG_FR_SQS_G08__A
206831. B_CE_REG_FR_SQS_G09__A
206832. B_CE_REG_FR_SQS_G10__A
206833. B_CE_REG_FR_SQS_G11__A
206834. B_CE_REG_FR_SQS_G12__A
206835. B_CE_REG_FR_SQS_TRH__A
206836. B_CE_REG_FR_TAP_SH__A
206837. B_CE_REG_FR_TIMAG00__A
206838. B_CE_REG_FR_TIMAG01__A
206839. B_CE_REG_FR_TIMAG02__A
206840. B_CE_REG_FR_TIMAG03__A
206841. B_CE_REG_FR_TIMAG04__A
206842. B_CE_REG_FR_TIMAG05__A
206843. B_CE_REG_FR_TIMAG06__A
206844. B_CE_REG_FR_TIMAG07__A
206845. B_CE_REG_FR_TIMAG08__A
206846. B_CE_REG_FR_TIMAG09__A
206847. B_CE_REG_FR_TIMAG10__A
206848. B_CE_REG_FR_TIMAG11__A
206849. B_CE_REG_FR_TREAL00__A
206850. B_CE_REG_FR_TREAL01__A
206851. B_CE_REG_FR_TREAL02__A
206852. B_CE_REG_FR_TREAL03__A
206853. B_CE_REG_FR_TREAL04__A
206854. B_CE_REG_FR_TREAL05__A
206855. B_CE_REG_FR_TREAL06__A
206856. B_CE_REG_FR_TREAL07__A
206857. B_CE_REG_FR_TREAL08__A
206858. B_CE_REG_FR_TREAL09__A
206859. B_CE_REG_FR_TREAL10__A
206860. B_CE_REG_FR_TREAL11__A
206861. B_CE_REG_IR_INPUTSEL__A
206862. B_CE_REG_IR_NEXP_THRES__A
206863. B_CE_REG_IR_STARTPOS__A
206864. B_CE_REG_MAX_POW__A
206865. B_CE_REG_NE_ERR_SELECT__A
206866. B_CE_REG_NE_MIXAVG__A
206867. B_CE_REG_NE_NUPD_OFS__A
206868. B_CE_REG_NE_TD_CAL__A
206869. B_CE_REG_NRED__A
206870. B_CE_REG_PE_NEXP_OFFS__A
206871. B_CE_REG_PE_TIMESHIFT__A
206872. B_CE_REG_TAPSET__A
206873. B_CE_REG_TI_PHN_ENABLE__A
206874. B_CE_REG_TP_A0_MU_LMS_STEP__A
206875. B_CE_REG_TP_A0_TAP_NEW_VALID__A
206876. B_CE_REG_TP_A0_TAP_NEW__A
206877. B_CE_REG_TP_A1_MU_LMS_STEP__A
206878. B_CE_REG_TP_A1_TAP_NEW_VALID__A
206879. B_CE_REG_TP_A1_TAP_NEW__A
206880. B_CHILD_SIZE
206881. B_CP_COMM_EXEC__A
206882. B_CP_REG_AC_AMP_FIX__A
206883. B_CP_REG_AC_AMP_MODE__A
206884. B_CP_REG_AC_ANG_MODE__A
206885. B_CP_REG_AC_AVER_POW__A
206886. B_CP_REG_AC_MAX_POW__A
206887. B_CP_REG_AC_NEXP_OFFS__A
206888. B_CP_REG_AC_WEIGHT_EXP__A
206889. B_CP_REG_AC_WEIGHT_MAN__A
206890. B_CP_REG_BR_SPL_OFFSET__A
206891. B_CP_REG_BR_STR_DEL__A
206892. B_CP_REG_COMM_EXEC__A
206893. B_CP_REG_INTERVAL__A
206894. B_CP_REG_RT_ANG_INC0__A
206895. B_CP_REG_RT_ANG_INC1__A
206896. B_CP_REG_RT_DETECT_TRH__A
206897. B_CTL
206898. B_CUT_VERSION
206899. B_DATA_PLS
206900. B_DEFAULT_MASK
206901. B_DEFAULT_MASK_SFT
206902. B_DEFAULT_SFT
206903. B_DIRTY
206904. B_DMA_contig
206905. B_DMA_sg
206906. B_EC_OC_REG_AVR_ASH_CNT__A
206907. B_EC_OC_REG_AVR_BSH_CNT__A
206908. B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE
206909. B_EC_OC_REG_COMM_EXEC_CTL_HOLD
206910. B_EC_OC_REG_COMM_EXEC__A
206911. B_EC_OC_REG_COMM_INT_STA__A
206912. B_EC_OC_REG_DTO_BUR__A
206913. B_EC_OC_REG_DTO_CLKMODE__A
206914. B_EC_OC_REG_DTO_INC_HIP__A
206915. B_EC_OC_REG_DTO_INC_LOP__A
206916. B_EC_OC_REG_DTO_PER__A
206917. B_EC_OC_REG_IPR_INV_MPG__A
206918. B_EC_OC_REG_OCR_MPG_UOS_INIT
206919. B_EC_OC_REG_OCR_MPG_UOS__A
206920. B_EC_OC_REG_OCR_MPG_UOS__M
206921. B_EC_OC_REG_OCR_MPG_USR_DAT__A
206922. B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR
206923. B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE
206924. B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE
206925. B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M
206926. B_EC_OC_REG_OC_MODE_HIP__A
206927. B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC
206928. B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M
206929. B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL
206930. B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M
206931. B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE
206932. B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE
206933. B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M
206934. B_EC_OC_REG_OC_MODE_LOP__A
206935. B_EC_OC_REG_OC_MPG_SIO__A
206936. B_EC_OC_REG_OC_MPG_SIO__M
206937. B_EC_OC_REG_RCN_CLP_HIP__A
206938. B_EC_OC_REG_RCN_CLP_LOP__A
206939. B_EC_OC_REG_RCN_CRA_HIP__A
206940. B_EC_OC_REG_RCN_CRA_LOP__A
206941. B_EC_OC_REG_RCN_CST_HIP__A
206942. B_EC_OC_REG_RCN_CST_LOP__A
206943. B_EC_OC_REG_RCN_GAI_LVL__A
206944. B_EC_OC_REG_RCN_MAP_HIP__A
206945. B_EC_OC_REG_RCN_MAP_LOP__A
206946. B_EC_OC_REG_RCN_MODE__A
206947. B_EC_OC_REG_RCN_SET_LVL__A
206948. B_EC_OC_REG_RCR_CLKMODE__A
206949. B_EC_OC_REG_SNC_ISC_LVL_OSC__M
206950. B_EC_OC_REG_SNC_ISC_LVL__A
206951. B_EC_OC_REG_TMD_CUR_CNT__A
206952. B_EC_OC_REG_TMD_HIL_MAR__A
206953. B_EC_OC_REG_TMD_LOL_MAR__A
206954. B_EC_OC_REG_TMD_TOP_CNT__A
206955. B_EC_OC_REG_TMD_TOP_MODE__A
206956. B_EC_OD_DEINT_RAM__A
206957. B_EC_OD_REG_COMM_EXEC__A
206958. B_EC_OD_REG_SYNC__A
206959. B_EC_RS_EC_RAM__A
206960. B_EC_RS_REG_COMM_EXEC__A
206961. B_EC_RS_REG_REQ_PCK_CNT__A
206962. B_EC_RS_REG_VAL_PCK
206963. B_EC_RS_REG_VAL__A
206964. B_EC_SB_REG_ALPHA__A
206965. B_EC_SB_REG_COMM_EXEC__A
206966. B_EC_SB_REG_CONST_16QAM
206967. B_EC_SB_REG_CONST_64QAM
206968. B_EC_SB_REG_CONST_QPSK
206969. B_EC_SB_REG_CONST__A
206970. B_EC_SB_REG_CSI_HI__A
206971. B_EC_SB_REG_CSI_LO__A
206972. B_EC_SB_REG_CSI_OFS0__A
206973. B_EC_SB_REG_CSI_OFS1__A
206974. B_EC_SB_REG_CSI_OFS2__A
206975. B_EC_SB_REG_PRIOR_HI
206976. B_EC_SB_REG_PRIOR_LO
206977. B_EC_SB_REG_PRIOR__A
206978. B_EC_SB_REG_SCALE_BIT2__A
206979. B_EC_SB_REG_SCALE_LSB__A
206980. B_EC_SB_REG_SCALE_MSB__A
206981. B_EC_SB_REG_SMB_TGL__A
206982. B_EC_SB_REG_SNR_HI__A
206983. B_EC_SB_REG_SNR_LO__A
206984. B_EC_SB_REG_SNR_MID__A
206985. B_EC_SB_REG_TR_MODE_2K
206986. B_EC_SB_REG_TR_MODE_8K
206987. B_EC_SB_REG_TR_MODE__A
206988. B_EC_VD_REG_COMM_EXEC__A
206989. B_EC_VD_REG_FORCE__A
206990. B_EC_VD_REG_REQ_SMB_CNT__A
206991. B_EC_VD_REG_RLK_ENA__A
206992. B_EC_VD_REG_SET_CODERATE_C1_2
206993. B_EC_VD_REG_SET_CODERATE_C2_3
206994. B_EC_VD_REG_SET_CODERATE_C3_4
206995. B_EC_VD_REG_SET_CODERATE_C5_6
206996. B_EC_VD_REG_SET_CODERATE_C7_8
206997. B_EC_VD_REG_SET_CODERATE__A
206998. B_EQ_COMM_EXEC__A
206999. B_EQ_REG_COMM_EXEC__A
207000. B_EQ_REG_COMM_MB__A
207001. B_EQ_REG_IS_CLIP_EXP__A
207002. B_EQ_REG_IS_GAIN_EXP__A
207003. B_EQ_REG_IS_GAIN_MAN__A
207004. B_EQ_REG_OT_ALPHA__A
207005. B_EQ_REG_OT_CONST__A
207006. B_EQ_REG_OT_CSI_OFFSET__A
207007. B_EQ_REG_OT_CSI_STEP__A
207008. B_EQ_REG_OT_QNT_THRES0__A
207009. B_EQ_REG_OT_QNT_THRES1__A
207010. B_EQ_REG_RC_SEL_CAR_DIV_ON
207011. B_EQ_REG_RC_SEL_CAR_FFTMODE__M
207012. B_EQ_REG_RC_SEL_CAR_INIT
207013. B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC
207014. B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE
207015. B_EQ_REG_RC_SEL_CAR_MEAS_A_CC
207016. B_EQ_REG_RC_SEL_CAR_MEAS_B_CE
207017. B_EQ_REG_RC_SEL_CAR_PASS_A_CC
207018. B_EQ_REG_RC_SEL_CAR_PASS_B_CE
207019. B_EQ_REG_RC_SEL_CAR__A
207020. B_EQ_REG_SN_CEGAIN__A
207021. B_EQ_REG_SN_OFFSET__A
207022. B_EQ_REG_TD_REQ_SMB_CNT__A
207023. B_EQ_REG_TD_TPS_PWR_OFS__A
207024. B_EXNUM
207025. B_FE_AD_REG_CLKNEG__A
207026. B_FE_AD_REG_COMM_EXEC__A
207027. B_FE_AD_REG_FDB_IN__A
207028. B_FE_AD_REG_INVEXT__A
207029. B_FE_AD_REG_PD__A
207030. B_FE_AG_REG_ACE_AUR_CNT__A
207031. B_FE_AG_REG_ACE_RUR_CNT__A
207032. B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT
207033. B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT
207034. B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M
207035. B_FE_AG_REG_AG_AGC_SIO__A
207036. B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC
207037. B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC
207038. B_FE_AG_REG_AG_MODE_HIP_MODE_J__M
207039. B_FE_AG_REG_AG_MODE_HIP__A
207040. B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC
207041. B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC
207042. B_FE_AG_REG_AG_MODE_LOP_MODE_4__M
207043. B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC
207044. B_FE_AG_REG_AG_MODE_LOP_MODE_5__M
207045. B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC
207046. B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC
207047. B_FE_AG_REG_AG_MODE_LOP_MODE_C__M
207048. B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC
207049. B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC
207050. B_FE_AG_REG_AG_MODE_LOP_MODE_E__M
207051. B_FE_AG_REG_AG_MODE_LOP__A
207052. B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN
207053. B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN
207054. B_FE_AG_REG_AG_PGA_MODE__A
207055. B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE
207056. B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE
207057. B_FE_AG_REG_AG_PWD_PWD_PD2__M
207058. B_FE_AG_REG_AG_PWD__A
207059. B_FE_AG_REG_BGC_CGC_WRI__A
207060. B_FE_AG_REG_BGC_FGC_WRI__A
207061. B_FE_AG_REG_CDR_RUR_CNT__A
207062. B_FE_AG_REG_COMM_EXEC__A
207063. B_FE_AG_REG_DCE_AUR_CNT__A
207064. B_FE_AG_REG_DCE_RUR_CNT__A
207065. B_FE_AG_REG_EGC_FAS_DEC__A
207066. B_FE_AG_REG_EGC_FAS_INC__A
207067. B_FE_AG_REG_EGC_FLA_DEC__A
207068. B_FE_AG_REG_EGC_FLA_INC__A
207069. B_FE_AG_REG_EGC_FLA_RGN__A
207070. B_FE_AG_REG_EGC_JMP_PSN__A
207071. B_FE_AG_REG_EGC_RUR_CNT__A
207072. B_FE_AG_REG_EGC_SET_LVL__A
207073. B_FE_AG_REG_EGC_SET_LVL__M
207074. B_FE_AG_REG_EGC_SLO_DEC__A
207075. B_FE_AG_REG_EGC_SLO_INC__A
207076. B_FE_AG_REG_EGC_SLO_RGN__A
207077. B_FE_AG_REG_FGM_WRI__A
207078. B_FE_AG_REG_GC1_AGC_DAT__A
207079. B_FE_AG_REG_GC1_AGC_DAT__M
207080. B_FE_AG_REG_GC1_AGC_MAX__A
207081. B_FE_AG_REG_GC1_AGC_MIN__A
207082. B_FE_AG_REG_GC1_AGC_OFF__A
207083. B_FE_AG_REG_GC1_AGC_RIC__A
207084. B_FE_AG_REG_IND_DEL__A
207085. B_FE_AG_REG_IND_PD1_WRI__A
207086. B_FE_AG_REG_IND_THD_HIL__A
207087. B_FE_AG_REG_IND_THD_LOL__A
207088. B_FE_AG_REG_IND_WIN__A
207089. B_FE_AG_REG_PDA_AUR_CNT__A
207090. B_FE_AG_REG_PDA_AVE_DAT__A
207091. B_FE_AG_REG_PDA_RUR_CNT__A
207092. B_FE_AG_REG_PDC_FLA_RGN__A
207093. B_FE_AG_REG_PDC_FLA_STP__A
207094. B_FE_AG_REG_PDC_JMP_PSN__A
207095. B_FE_AG_REG_PDC_MAP_DAT__A
207096. B_FE_AG_REG_PDC_MAX__A
207097. B_FE_AG_REG_PDC_PD2_WRI__A
207098. B_FE_AG_REG_PDC_RUR_CNT__A
207099. B_FE_AG_REG_PDC_SET_LVL__A
207100. B_FE_AG_REG_PDC_SLO_STP__A
207101. B_FE_AG_REG_PM1_AGC_WRI__A
207102. B_FE_AG_REG_PM1_AGC_WRI__M
207103. B_FE_AG_REG_PM2_AGC_WRI__A
207104. B_FE_AG_REG_TGA_AUR_CNT__A
207105. B_FE_AG_REG_TGA_AVE_DAT__A
207106. B_FE_AG_REG_TGA_RUR_CNT__A
207107. B_FE_AG_REG_TGC_FLA_RGN__A
207108. B_FE_AG_REG_TGC_FLA_STP__A
207109. B_FE_AG_REG_TGC_JMP_PSN__A
207110. B_FE_AG_REG_TGC_MAP_DAT__A
207111. B_FE_AG_REG_TGC_RUR_CNT__A
207112. B_FE_AG_REG_TGC_SET_LVL__A
207113. B_FE_AG_REG_TGC_SET_LVL__M
207114. B_FE_AG_REG_TGC_SLO_STP__A
207115. B_FE_CF_REG_COMM_EXEC__A
207116. B_FE_CF_REG_IMP_VAL__A
207117. B_FE_CF_REG_MAX_LEV__A
207118. B_FE_CF_REG_MEAS_VAL__A
207119. B_FE_CF_REG_NR__A
207120. B_FE_CF_REG_SCL__A
207121. B_FE_COMM_EXEC__A
207122. B_FE_CU_REG_COMM_EXEC__A
207123. B_FE_CU_REG_CTR_NFC_ICR__A
207124. B_FE_CU_REG_CTR_NFC_OCR__A
207125. B_FE_CU_REG_DIV_NFC_CLP__A
207126. B_FE_CU_REG_FRM_CNT_RST__A
207127. B_FE_CU_REG_FRM_CNT_STR__A
207128. B_FE_FD_REG_COMM_EXEC__A
207129. B_FE_FD_REG_MAX_LEV__A
207130. B_FE_FD_REG_MEAS_VAL__A
207131. B_FE_FD_REG_NR__A
207132. B_FE_FD_REG_SCL__A
207133. B_FE_FS_REG_ADD_INC_LOP__A
207134. B_FE_FS_REG_COMM_EXEC__A
207135. B_FE_IF_REG_COMM_EXEC__A
207136. B_FE_IF_REG_INCR0__A
207137. B_FE_IF_REG_INCR0__M
207138. B_FE_IF_REG_INCR0__W
207139. B_FE_IF_REG_INCR1__A
207140. B_FE_IF_REG_INCR1__M
207141. B_FIFO_SIZE
207142. B_FRAME
207143. B_FRAMING
207144. B_FREE_SPACE
207145. B_FT_COMM_EXEC__A
207146. B_FT_REG_COMM_EXEC__A
207147. B_GOT_CALLBACK
207148. B_HI_COMM_EXEC__A
207149. B_HI_COMM_MB__A
207150. B_HI_CT_REG_COMM_STATE__A
207151. B_HI_IF_RAM_TRP_BPT0__AX
207152. B_HI_IF_RAM_USR_BEGIN__A
207153. B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF
207154. B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON
207155. B_HI_RA_RAM_SRV_CFG_ACT_BRD__M
207156. B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE
207157. B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON
207158. B_HI_RA_RAM_SRV_CFG_ACT__A
207159. B_HI_RA_RAM_SRV_CFG_BDL__A
207160. B_HI_RA_RAM_SRV_CFG_DIV__A
207161. B_HI_RA_RAM_SRV_CFG_KEY__A
207162. B_HI_RA_RAM_SRV_CFG_WUP__A
207163. B_HI_RA_RAM_SRV_CMD_CONFIG
207164. B_HI_RA_RAM_SRV_CMD_EXECUTE
207165. B_HI_RA_RAM_SRV_CMD_RESET
207166. B_HI_RA_RAM_SRV_CMD__A
207167. B_HI_RA_RAM_SRV_RES__A
207168. B_HI_RA_RAM_SRV_RST_KEY_ACT
207169. B_HI_RA_RAM_SRV_RST_KEY__A
207170. B_HI_RA_RAM_USR_BEGIN__A
207171. B_HNP_FAIL
207172. B_INI_MASK
207173. B_INI_MASK_SFT
207174. B_INI_SFT
207175. B_INSN
207176. B_IS_IN_TREE
207177. B_IS_ITEMS_LEVEL
207178. B_IS_KEYS_LEVEL
207179. B_I_DEH
207180. B_I_DEH_ENTRY_FILE_NAME
207181. B_I_POS_UNFM_POINTER
207182. B_I_STAT_DATA
207183. B_LC_COMM_EXEC__A
207184. B_LC_RA_RAM_FILTER_CRMM_A__A
207185. B_LC_RA_RAM_FILTER_CRMM_A__PRE
207186. B_LC_RA_RAM_FILTER_CRMM_B__A
207187. B_LC_RA_RAM_FILTER_CRMM_B__PRE
207188. B_LC_RA_RAM_FILTER_SRMM_A__A
207189. B_LC_RA_RAM_FILTER_SRMM_A__PRE
207190. B_LC_RA_RAM_FILTER_SRMM_B__A
207191. B_LC_RA_RAM_FILTER_SRMM_B__PRE
207192. B_LC_RA_RAM_FILTER_SYM_SET__A
207193. B_LC_RA_RAM_FILTER_SYM_SET__PRE
207194. B_LC_RA_RAM_IFINCR_NOM_L__A
207195. B_LEVEL
207196. B_MASK
207197. B_MODE_MAX_RIX
207198. B_MST_CTLR
207199. B_NOTIFICATION
207200. B_NR_ITEMS
207201. B_NUM
207202. B_N_CHILD
207203. B_N_CHILD_NUM
207204. B_OS_NAME_LENGTH
207205. B_OVERRUN
207206. B_OWNED_BY_CHIP
207207. B_OWNED_BY_HOST
207208. B_PACK_CHARS
207209. B_PARITY
207210. B_PRIGHT_DELIM_KEY
207211. B_QUEUED
207212. B_READING
207213. B_RING_SIGNAL
207214. B_RS_H_DONE
207215. B_RX_CARRIER
207216. B_SC_COMM_EXEC_CTL_STOP
207217. B_SC_COMM_EXEC__A
207218. B_SC_COMM_STATE__A
207219. B_SC_RA_RAM_BAND__A
207220. B_SC_RA_RAM_BE_OPT_DELAY__A
207221. B_SC_RA_RAM_BE_OPT_ENA_CP_OPT
207222. B_SC_RA_RAM_BE_OPT_ENA__A
207223. B_SC_RA_RAM_CMD_ADDR__A
207224. B_SC_RA_RAM_CMD_GET_OP_PARAM
207225. B_SC_RA_RAM_CMD_PROC_START
207226. B_SC_RA_RAM_CMD_SET_PREF_PARAM
207227. B_SC_RA_RAM_CMD__A
207228. B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
207229. B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M
207230. B_SC_RA_RAM_CONFIG_FREQSCAN__M
207231. B_SC_RA_RAM_CONFIG_FR_ENABLE__M
207232. B_SC_RA_RAM_CONFIG_SLAVE__M
207233. B_SC_RA_RAM_CONFIG__A
207234. B_SC_RA_RAM_CO_TD_CAL_2K__A
207235. B_SC_RA_RAM_CO_TD_CAL_8K__A
207236. B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A
207237. B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A
207238. B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A
207239. B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A
207240. B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A
207241. B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A
207242. B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A
207243. B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A
207244. B_SC_RA_RAM_DRIVER_VERSION__AX
207245. B_SC_RA_RAM_ECHO_SHIFT_LIM__A
207246. B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE
207247. B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE
207248. B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE
207249. B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE
207250. B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE
207251. B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE
207252. B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE
207253. B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE
207254. B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE
207255. B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE
207256. B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE
207257. B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE
207258. B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE
207259. B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE
207260. B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE
207261. B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE
207262. B_SC_RA_RAM_IF_SAVE__AX
207263. B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A
207264. B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE
207265. B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A
207266. B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE
207267. B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A
207268. B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE
207269. B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A
207270. B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE
207271. B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A
207272. B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE
207273. B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A
207274. B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE
207275. B_SC_RA_RAM_IR_FINE_2K_FREQINC__A
207276. B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE
207277. B_SC_RA_RAM_IR_FINE_2K_KAISINC__A
207278. B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE
207279. B_SC_RA_RAM_IR_FINE_2K_LENGTH__A
207280. B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE
207281. B_SC_RA_RAM_IR_FINE_8K_FREQINC__A
207282. B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE
207283. B_SC_RA_RAM_IR_FINE_8K_KAISINC__A
207284. B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE
207285. B_SC_RA_RAM_IR_FINE_8K_LENGTH__A
207286. B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE
207287. B_SC_RA_RAM_LC_ABS_2K__A
207288. B_SC_RA_RAM_LC_ABS_2K__PRE
207289. B_SC_RA_RAM_LC_ABS_8K__A
207290. B_SC_RA_RAM_LC_ABS_8K__PRE
207291. B_SC_RA_RAM_LOCKTRACK_MIN
207292. B_SC_RA_RAM_LOCK_DEMOD__M
207293. B_SC_RA_RAM_LOCK_FEC__M
207294. B_SC_RA_RAM_LOCK_MPEG__M
207295. B_SC_RA_RAM_LOCK__A
207296. B_SC_RA_RAM_OP_AUTO_CONST__M
207297. B_SC_RA_RAM_OP_AUTO_GUARD__M
207298. B_SC_RA_RAM_OP_AUTO_HIER__M
207299. B_SC_RA_RAM_OP_AUTO_MODE__M
207300. B_SC_RA_RAM_OP_AUTO_RATE__M
207301. B_SC_RA_RAM_OP_PARAM_CONST_QAM16
207302. B_SC_RA_RAM_OP_PARAM_CONST_QAM64
207303. B_SC_RA_RAM_OP_PARAM_CONST_QPSK
207304. B_SC_RA_RAM_OP_PARAM_GUARD_16
207305. B_SC_RA_RAM_OP_PARAM_GUARD_32
207306. B_SC_RA_RAM_OP_PARAM_GUARD_4
207307. B_SC_RA_RAM_OP_PARAM_GUARD_8
207308. B_SC_RA_RAM_OP_PARAM_HIER_A1
207309. B_SC_RA_RAM_OP_PARAM_HIER_A2
207310. B_SC_RA_RAM_OP_PARAM_HIER_A4
207311. B_SC_RA_RAM_OP_PARAM_HIER_NO
207312. B_SC_RA_RAM_OP_PARAM_MODE_2K
207313. B_SC_RA_RAM_OP_PARAM_MODE_8K
207314. B_SC_RA_RAM_OP_PARAM_PRIO_HI
207315. B_SC_RA_RAM_OP_PARAM_PRIO_LO
207316. B_SC_RA_RAM_OP_PARAM_RATE_1_2
207317. B_SC_RA_RAM_OP_PARAM_RATE_2_3
207318. B_SC_RA_RAM_OP_PARAM_RATE_3_4
207319. B_SC_RA_RAM_OP_PARAM_RATE_5_6
207320. B_SC_RA_RAM_OP_PARAM_RATE_7_8
207321. B_SC_RA_RAM_PARAM0__A
207322. B_SC_RA_RAM_PARAM1__A
207323. B_SC_RA_RAM_PROC_LOCKTRACK
207324. B_SC_RA_RAM_SAMPLE_RATE_COUNT__A
207325. B_SC_RA_RAM_SAMPLE_RATE_STEP__A
207326. B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M
207327. B_SE0_SRP
207328. B_SRP_DONE
207329. B_SRP_FAIL
207330. B_SRP_STARTED
207331. B_SRP_TMROUT
207332. B_SSEND_SRP
207333. B_SUB_VAL
207334. B_SUPPORTED_RATES
207335. B_SYM
207336. B_TIMED_OUT
207337. B_TX_CARRIER
207338. B_TYPE_LARGE
207339. B_WDLM
207340. B_WRITING
207341. B_vmalloc
207342. BaSetupTimeOut
207343. BackCaptureEffect
207344. BackModify
207345. BackOptional
207346. BackRandom
207347. BadMemory
207348. BankFileID
207349. BankHeight
207350. BankInterleaveSize
207351. BankSwapBytes
207352. BankTiling
207353. BankWidth
207354. BankWidthHeight
207355. BaseA0
207356. BaseA1
207357. BaseA1_in
207358. BaseA1_out
207359. BaseA2
207360. BaseA2_in
207361. BaseA2_out
207362. BaseA3
207363. BaseBand_Config_AGC_TAB
207364. BaseBand_Config_AGC_TAB_2G
207365. BaseBand_Config_AGC_TAB_5G
207366. BaseBand_Config_PHY_REG
207367. BaseBand_Config_PHY_REG_PG
207368. BaseBand_Config_Type
207369. BasicControl
207370. BasicModeCtrl
207371. BasicModeStatus
207372. BasicStatus
207373. Bcast_DID
207374. BcstFramesRcvdOk
207375. BcstFramesXmtdOk
207376. BcstOctetRcvOk
207377. BcstOctetXmtOk
207378. Beacon_en
207379. BeginDisconnect
207380. BenqDC1016
207381. BinEventCntl
207382. BinMapMode
207383. BinSizeExtend
207384. BinningMode
207385. BiosMode
207386. BiosReg
207387. Bit2KB
207388. BitOp
207389. BitTime
207390. Bitfield_deposit
207391. Bitfield_extract
207392. Bitfield_mask
207393. Bitfield_signed_extract
207394. BitmapExtent08
207395. BitmapExtent32
207396. Bitmap_sync
207397. BiuSlaveCmdGstNum
207398. BiuSlvErHi
207399. BiuSlvErLow
207400. BiuTimeoutHi
207401. BiuTimeoutLow
207402. BlendOp
207403. BlendOpt
207404. BlinkTimerCallback
207405. BlinkWorkItemCallback
207406. BlitBitmap
207407. BlitBmp
207408. Blktrace_running
207409. Blktrace_setup
207410. Blktrace_stopped
207411. BlockAdrs
207412. BlockRead
207413. BlockWrite
207414. Blocked
207415. BlockedBadBlocks
207416. Bool
207417. Boolean
207418. BootRom
207419. BootRomAddr
207420. BootRomData
207421. Bprotocol
207422. Bps_to_icc
207423. BrdcstPkt
207424. Break_cnt
207425. BtoKB
207426. BtoMB
207427. BuddhaType
207428. BuddhaType_Enum
207429. Buf_size
207430. BufferControl
207431. BufferDesc
207432. BufferExchangeFlags
207433. BuildLAF
207434. BurstA1_in
207435. BurstA1_out
207436. BurstA2_in
207437. BurstA2_out
207438. BurstLen4
207439. BurstLenShift
207440. BusDevRst
207441. BusMode
207442. BusTypes_type
207443. Butt_Reg
207444. Byte
207445. ByteIO_t
207446. ByteOp
207447. Byte_t